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Linux/sound/sparc/amd7930.c

  1 /*
  2  * Driver for AMD7930 sound chips found on Sparcs.
  3  * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net>
  4  *
  5  * Based entirely upon drivers/sbus/audio/amd7930.c which is:
  6  * Copyright (C) 1996,1997 Thomas K. Dyas (tdyas@eden.rutgers.edu)
  7  *
  8  * --- Notes from Thomas's original driver ---
  9  * This is the lowlevel driver for the AMD7930 audio chip found on all
 10  * sun4c machines and some sun4m machines.
 11  *
 12  * The amd7930 is actually an ISDN chip which has a very simple
 13  * integrated audio encoder/decoder. When Sun decided on what chip to
 14  * use for audio, they had the brilliant idea of using the amd7930 and
 15  * only connecting the audio encoder/decoder pins.
 16  *
 17  * Thanks to the AMD engineer who was able to get us the AMD79C30
 18  * databook which has all the programming information and gain tables.
 19  *
 20  * Advanced Micro Devices' Am79C30A is an ISDN/audio chip used in the
 21  * SparcStation 1+.  The chip provides microphone and speaker interfaces
 22  * which provide mono-channel audio at 8K samples per second via either
 23  * 8-bit A-law or 8-bit mu-law encoding.  Also, the chip features an
 24  * ISDN BRI Line Interface Unit (LIU), I.430 S/T physical interface,
 25  * which performs basic D channel LAPD processing and provides raw
 26  * B channel data.  The digital audio channel, the two ISDN B channels,
 27  * and two 64 Kbps channels to the microprocessor are all interconnected
 28  * via a multiplexer.
 29  * --- End of notes from Thoamas's original driver ---
 30  */
 31 
 32 #include <linux/module.h>
 33 #include <linux/kernel.h>
 34 #include <linux/slab.h>
 35 #include <linux/init.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/moduleparam.h>
 38 #include <linux/of.h>
 39 #include <linux/of_device.h>
 40 
 41 #include <sound/core.h>
 42 #include <sound/pcm.h>
 43 #include <sound/info.h>
 44 #include <sound/control.h>
 45 #include <sound/initval.h>
 46 
 47 #include <asm/io.h>
 48 #include <asm/irq.h>
 49 #include <asm/prom.h>
 50 
 51 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 52 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 53 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
 54 
 55 module_param_array(index, int, NULL, 0444);
 56 MODULE_PARM_DESC(index, "Index value for Sun AMD7930 soundcard.");
 57 module_param_array(id, charp, NULL, 0444);
 58 MODULE_PARM_DESC(id, "ID string for Sun AMD7930 soundcard.");
 59 module_param_array(enable, bool, NULL, 0444);
 60 MODULE_PARM_DESC(enable, "Enable Sun AMD7930 soundcard.");
 61 MODULE_AUTHOR("Thomas K. Dyas and David S. Miller");
 62 MODULE_DESCRIPTION("Sun AMD7930");
 63 MODULE_LICENSE("GPL");
 64 MODULE_SUPPORTED_DEVICE("{{Sun,AMD7930}}");
 65 
 66 /* Device register layout.  */
 67 
 68 /* Register interface presented to the CPU by the amd7930. */
 69 #define AMD7930_CR      0x00UL          /* Command Register (W) */
 70 #define AMD7930_IR      AMD7930_CR      /* Interrupt Register (R) */
 71 #define AMD7930_DR      0x01UL          /* Data Register (R/W) */
 72 #define AMD7930_DSR1    0x02UL          /* D-channel Status Register 1 (R) */
 73 #define AMD7930_DER     0x03UL          /* D-channel Error Register (R) */
 74 #define AMD7930_DCTB    0x04UL          /* D-channel Transmit Buffer (W) */
 75 #define AMD7930_DCRB    AMD7930_DCTB    /* D-channel Receive Buffer (R) */
 76 #define AMD7930_BBTB    0x05UL          /* Bb-channel Transmit Buffer (W) */
 77 #define AMD7930_BBRB    AMD7930_BBTB    /* Bb-channel Receive Buffer (R) */
 78 #define AMD7930_BCTB    0x06UL          /* Bc-channel Transmit Buffer (W) */
 79 #define AMD7930_BCRB    AMD7930_BCTB    /* Bc-channel Receive Buffer (R) */
 80 #define AMD7930_DSR2    0x07UL          /* D-channel Status Register 2 (R) */
 81 
 82 /* Indirect registers in the Main Audio Processor. */
 83 struct amd7930_map {
 84         __u16   x[8];
 85         __u16   r[8];
 86         __u16   gx;
 87         __u16   gr;
 88         __u16   ger;
 89         __u16   stgr;
 90         __u16   ftgr;
 91         __u16   atgr;
 92         __u8    mmr1;
 93         __u8    mmr2;
 94 };
 95 
 96 /* After an amd7930 interrupt, reading the Interrupt Register (ir)
 97  * clears the interrupt and returns a bitmask indicating which
 98  * interrupt source(s) require service.
 99  */
100 
101 #define AMR_IR_DTTHRSH                  0x01 /* D-channel xmit threshold */
102 #define AMR_IR_DRTHRSH                  0x02 /* D-channel recv threshold */
103 #define AMR_IR_DSRI                     0x04 /* D-channel packet status */
104 #define AMR_IR_DERI                     0x08 /* D-channel error */
105 #define AMR_IR_BBUF                     0x10 /* B-channel data xfer */
106 #define AMR_IR_LSRI                     0x20 /* LIU status */
107 #define AMR_IR_DSR2I                    0x40 /* D-channel buffer status */
108 #define AMR_IR_MLTFRMI                  0x80 /* multiframe or PP */
109 
110 /* The amd7930 has "indirect registers" which are accessed by writing
111  * the register number into the Command Register and then reading or
112  * writing values from the Data Register as appropriate. We define the
113  * AMR_* macros to be the indirect register numbers and AM_* macros to
114  * be bits in whatever register is referred to.
115  */
116 
117 /* Initialization */
118 #define AMR_INIT                        0x21
119 #define         AM_INIT_ACTIVE                  0x01
120 #define         AM_INIT_DATAONLY                0x02
121 #define         AM_INIT_POWERDOWN               0x03
122 #define         AM_INIT_DISABLE_INTS            0x04
123 #define AMR_INIT2                       0x20
124 #define         AM_INIT2_ENABLE_POWERDOWN       0x20
125 #define         AM_INIT2_ENABLE_MULTIFRAME      0x10
126 
127 /* Line Interface Unit */
128 #define AMR_LIU_LSR                     0xA1
129 #define         AM_LIU_LSR_STATE                0x07
130 #define         AM_LIU_LSR_F3                   0x08
131 #define         AM_LIU_LSR_F7                   0x10
132 #define         AM_LIU_LSR_F8                   0x20
133 #define         AM_LIU_LSR_HSW                  0x40
134 #define         AM_LIU_LSR_HSW_CHG              0x80
135 #define AMR_LIU_LPR                     0xA2
136 #define AMR_LIU_LMR1                    0xA3
137 #define         AM_LIU_LMR1_B1_ENABL            0x01
138 #define         AM_LIU_LMR1_B2_ENABL            0x02
139 #define         AM_LIU_LMR1_F_DISABL            0x04
140 #define         AM_LIU_LMR1_FA_DISABL           0x08
141 #define         AM_LIU_LMR1_REQ_ACTIV           0x10
142 #define         AM_LIU_LMR1_F8_F3               0x20
143 #define         AM_LIU_LMR1_LIU_ENABL           0x40
144 #define AMR_LIU_LMR2                    0xA4
145 #define         AM_LIU_LMR2_DECHO               0x01
146 #define         AM_LIU_LMR2_DLOOP               0x02
147 #define         AM_LIU_LMR2_DBACKOFF            0x04
148 #define         AM_LIU_LMR2_EN_F3_INT           0x08
149 #define         AM_LIU_LMR2_EN_F8_INT           0x10
150 #define         AM_LIU_LMR2_EN_HSW_INT          0x20
151 #define         AM_LIU_LMR2_EN_F7_INT           0x40
152 #define AMR_LIU_2_4                     0xA5
153 #define AMR_LIU_MF                      0xA6
154 #define AMR_LIU_MFSB                    0xA7
155 #define AMR_LIU_MFQB                    0xA8
156 
157 /* Multiplexor */
158 #define AMR_MUX_MCR1                    0x41
159 #define AMR_MUX_MCR2                    0x42
160 #define AMR_MUX_MCR3                    0x43
161 #define         AM_MUX_CHANNEL_B1               0x01
162 #define         AM_MUX_CHANNEL_B2               0x02
163 #define         AM_MUX_CHANNEL_Ba               0x03
164 #define         AM_MUX_CHANNEL_Bb               0x04
165 #define         AM_MUX_CHANNEL_Bc               0x05
166 #define         AM_MUX_CHANNEL_Bd               0x06
167 #define         AM_MUX_CHANNEL_Be               0x07
168 #define         AM_MUX_CHANNEL_Bf               0x08
169 #define AMR_MUX_MCR4                    0x44
170 #define         AM_MUX_MCR4_ENABLE_INTS         0x08
171 #define         AM_MUX_MCR4_REVERSE_Bb          0x10
172 #define         AM_MUX_MCR4_REVERSE_Bc          0x20
173 #define AMR_MUX_1_4                     0x45
174 
175 /* Main Audio Processor */
176 #define AMR_MAP_X                       0x61
177 #define AMR_MAP_R                       0x62
178 #define AMR_MAP_GX                      0x63
179 #define AMR_MAP_GR                      0x64
180 #define AMR_MAP_GER                     0x65
181 #define AMR_MAP_STGR                    0x66
182 #define AMR_MAP_FTGR_1_2                0x67
183 #define AMR_MAP_ATGR_1_2                0x68
184 #define AMR_MAP_MMR1                    0x69
185 #define         AM_MAP_MMR1_ALAW                0x01
186 #define         AM_MAP_MMR1_GX                  0x02
187 #define         AM_MAP_MMR1_GR                  0x04
188 #define         AM_MAP_MMR1_GER                 0x08
189 #define         AM_MAP_MMR1_X                   0x10
190 #define         AM_MAP_MMR1_R                   0x20
191 #define         AM_MAP_MMR1_STG                 0x40
192 #define         AM_MAP_MMR1_LOOPBACK            0x80
193 #define AMR_MAP_MMR2                    0x6A
194 #define         AM_MAP_MMR2_AINB                0x01
195 #define         AM_MAP_MMR2_LS                  0x02
196 #define         AM_MAP_MMR2_ENABLE_DTMF         0x04
197 #define         AM_MAP_MMR2_ENABLE_TONEGEN      0x08
198 #define         AM_MAP_MMR2_ENABLE_TONERING     0x10
199 #define         AM_MAP_MMR2_DISABLE_HIGHPASS    0x20
200 #define         AM_MAP_MMR2_DISABLE_AUTOZERO    0x40
201 #define AMR_MAP_1_10                    0x6B
202 #define AMR_MAP_MMR3                    0x6C
203 #define AMR_MAP_STRA                    0x6D
204 #define AMR_MAP_STRF                    0x6E
205 #define AMR_MAP_PEAKX                   0x70
206 #define AMR_MAP_PEAKR                   0x71
207 #define AMR_MAP_15_16                   0x72
208 
209 /* Data Link Controller */
210 #define AMR_DLC_FRAR_1_2_3              0x81
211 #define AMR_DLC_SRAR_1_2_3              0x82
212 #define AMR_DLC_TAR                     0x83
213 #define AMR_DLC_DRLR                    0x84
214 #define AMR_DLC_DTCR                    0x85
215 #define AMR_DLC_DMR1                    0x86
216 #define         AMR_DLC_DMR1_DTTHRSH_INT        0x01
217 #define         AMR_DLC_DMR1_DRTHRSH_INT        0x02
218 #define         AMR_DLC_DMR1_TAR_ENABL          0x04
219 #define         AMR_DLC_DMR1_EORP_INT           0x08
220 #define         AMR_DLC_DMR1_EN_ADDR1           0x10
221 #define         AMR_DLC_DMR1_EN_ADDR2           0x20
222 #define         AMR_DLC_DMR1_EN_ADDR3           0x40
223 #define         AMR_DLC_DMR1_EN_ADDR4           0x80
224 #define         AMR_DLC_DMR1_EN_ADDRS           0xf0
225 #define AMR_DLC_DMR2                    0x87
226 #define         AMR_DLC_DMR2_RABRT_INT          0x01
227 #define         AMR_DLC_DMR2_RESID_INT          0x02
228 #define         AMR_DLC_DMR2_COLL_INT           0x04
229 #define         AMR_DLC_DMR2_FCS_INT            0x08
230 #define         AMR_DLC_DMR2_OVFL_INT           0x10
231 #define         AMR_DLC_DMR2_UNFL_INT           0x20
232 #define         AMR_DLC_DMR2_OVRN_INT           0x40
233 #define         AMR_DLC_DMR2_UNRN_INT           0x80
234 #define AMR_DLC_1_7                     0x88
235 #define AMR_DLC_DRCR                    0x89
236 #define AMR_DLC_RNGR1                   0x8A
237 #define AMR_DLC_RNGR2                   0x8B
238 #define AMR_DLC_FRAR4                   0x8C
239 #define AMR_DLC_SRAR4                   0x8D
240 #define AMR_DLC_DMR3                    0x8E
241 #define         AMR_DLC_DMR3_VA_INT             0x01
242 #define         AMR_DLC_DMR3_EOTP_INT           0x02
243 #define         AMR_DLC_DMR3_LBRP_INT           0x04
244 #define         AMR_DLC_DMR3_RBA_INT            0x08
245 #define         AMR_DLC_DMR3_LBT_INT            0x10
246 #define         AMR_DLC_DMR3_TBE_INT            0x20
247 #define         AMR_DLC_DMR3_RPLOST_INT         0x40
248 #define         AMR_DLC_DMR3_KEEP_FCS           0x80
249 #define AMR_DLC_DMR4                    0x8F
250 #define         AMR_DLC_DMR4_RCV_1              0x00
251 #define         AMR_DLC_DMR4_RCV_2              0x01
252 #define         AMR_DLC_DMR4_RCV_4              0x02
253 #define         AMR_DLC_DMR4_RCV_8              0x03
254 #define         AMR_DLC_DMR4_RCV_16             0x01
255 #define         AMR_DLC_DMR4_RCV_24             0x02
256 #define         AMR_DLC_DMR4_RCV_30             0x03
257 #define         AMR_DLC_DMR4_XMT_1              0x00
258 #define         AMR_DLC_DMR4_XMT_2              0x04
259 #define         AMR_DLC_DMR4_XMT_4              0x08
260 #define         AMR_DLC_DMR4_XMT_8              0x0c
261 #define         AMR_DLC_DMR4_XMT_10             0x08
262 #define         AMR_DLC_DMR4_XMT_14             0x0c
263 #define         AMR_DLC_DMR4_IDLE_MARK          0x00
264 #define         AMR_DLC_DMR4_IDLE_FLAG          0x10
265 #define         AMR_DLC_DMR4_ADDR_BOTH          0x00
266 #define         AMR_DLC_DMR4_ADDR_1ST           0x20
267 #define         AMR_DLC_DMR4_ADDR_2ND           0xa0
268 #define         AMR_DLC_DMR4_CR_ENABLE          0x40
269 #define AMR_DLC_12_15                   0x90
270 #define AMR_DLC_ASR                     0x91
271 #define AMR_DLC_EFCR                    0x92
272 #define         AMR_DLC_EFCR_EXTEND_FIFO        0x01
273 #define         AMR_DLC_EFCR_SEC_PKT_INT        0x02
274 
275 #define AMR_DSR1_VADDR                  0x01
276 #define AMR_DSR1_EORP                   0x02
277 #define AMR_DSR1_PKT_IP                 0x04
278 #define AMR_DSR1_DECHO_ON               0x08
279 #define AMR_DSR1_DLOOP_ON               0x10
280 #define AMR_DSR1_DBACK_OFF              0x20
281 #define AMR_DSR1_EOTP                   0x40
282 #define AMR_DSR1_CXMT_ABRT              0x80
283 
284 #define AMR_DSR2_LBRP                   0x01
285 #define AMR_DSR2_RBA                    0x02
286 #define AMR_DSR2_RPLOST                 0x04
287 #define AMR_DSR2_LAST_BYTE              0x08
288 #define AMR_DSR2_TBE                    0x10
289 #define AMR_DSR2_MARK_IDLE              0x20
290 #define AMR_DSR2_FLAG_IDLE              0x40
291 #define AMR_DSR2_SECOND_PKT             0x80
292 
293 #define AMR_DER_RABRT                   0x01
294 #define AMR_DER_RFRAME                  0x02
295 #define AMR_DER_COLLISION               0x04
296 #define AMR_DER_FCS                     0x08
297 #define AMR_DER_OVFL                    0x10
298 #define AMR_DER_UNFL                    0x20
299 #define AMR_DER_OVRN                    0x40
300 #define AMR_DER_UNRN                    0x80
301 
302 /* Peripheral Port */
303 #define AMR_PP_PPCR1                    0xC0
304 #define AMR_PP_PPSR                     0xC1
305 #define AMR_PP_PPIER                    0xC2
306 #define AMR_PP_MTDR                     0xC3
307 #define AMR_PP_MRDR                     0xC3
308 #define AMR_PP_CITDR0                   0xC4
309 #define AMR_PP_CIRDR0                   0xC4
310 #define AMR_PP_CITDR1                   0xC5
311 #define AMR_PP_CIRDR1                   0xC5
312 #define AMR_PP_PPCR2                    0xC8
313 #define AMR_PP_PPCR3                    0xC9
314 
315 struct snd_amd7930 {
316         spinlock_t              lock;
317         void __iomem            *regs;
318         u32                     flags;
319 #define AMD7930_FLAG_PLAYBACK   0x00000001
320 #define AMD7930_FLAG_CAPTURE    0x00000002
321 
322         struct amd7930_map      map;
323 
324         struct snd_card         *card;
325         struct snd_pcm          *pcm;
326         struct snd_pcm_substream        *playback_substream;
327         struct snd_pcm_substream        *capture_substream;
328 
329         /* Playback/Capture buffer state. */
330         unsigned char           *p_orig, *p_cur;
331         int                     p_left;
332         unsigned char           *c_orig, *c_cur;
333         int                     c_left;
334 
335         int                     rgain;
336         int                     pgain;
337         int                     mgain;
338 
339         struct platform_device  *op;
340         unsigned int            irq;
341         struct snd_amd7930      *next;
342 };
343 
344 static struct snd_amd7930 *amd7930_list;
345 
346 /* Idle the AMD7930 chip.  The amd->lock is not held.  */
347 static __inline__ void amd7930_idle(struct snd_amd7930 *amd)
348 {
349         unsigned long flags;
350 
351         spin_lock_irqsave(&amd->lock, flags);
352         sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
353         sbus_writeb(0, amd->regs + AMD7930_DR);
354         spin_unlock_irqrestore(&amd->lock, flags);
355 }
356 
357 /* Enable chip interrupts.  The amd->lock is not held.  */
358 static __inline__ void amd7930_enable_ints(struct snd_amd7930 *amd)
359 {
360         unsigned long flags;
361 
362         spin_lock_irqsave(&amd->lock, flags);
363         sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
364         sbus_writeb(AM_INIT_ACTIVE, amd->regs + AMD7930_DR);
365         spin_unlock_irqrestore(&amd->lock, flags);
366 }
367 
368 /* Disable chip interrupts.  The amd->lock is not held.  */
369 static __inline__ void amd7930_disable_ints(struct snd_amd7930 *amd)
370 {
371         unsigned long flags;
372 
373         spin_lock_irqsave(&amd->lock, flags);
374         sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
375         sbus_writeb(AM_INIT_ACTIVE | AM_INIT_DISABLE_INTS, amd->regs + AMD7930_DR);
376         spin_unlock_irqrestore(&amd->lock, flags);
377 }
378 
379 /* Commit amd7930_map settings to the hardware.
380  * The amd->lock is held and local interrupts are disabled.
381  */
382 static void __amd7930_write_map(struct snd_amd7930 *amd)
383 {
384         struct amd7930_map *map = &amd->map;
385 
386         sbus_writeb(AMR_MAP_GX, amd->regs + AMD7930_CR);
387         sbus_writeb(((map->gx >> 0) & 0xff), amd->regs + AMD7930_DR);
388         sbus_writeb(((map->gx >> 8) & 0xff), amd->regs + AMD7930_DR);
389 
390         sbus_writeb(AMR_MAP_GR, amd->regs + AMD7930_CR);
391         sbus_writeb(((map->gr >> 0) & 0xff), amd->regs + AMD7930_DR);
392         sbus_writeb(((map->gr >> 8) & 0xff), amd->regs + AMD7930_DR);
393 
394         sbus_writeb(AMR_MAP_STGR, amd->regs + AMD7930_CR);
395         sbus_writeb(((map->stgr >> 0) & 0xff), amd->regs + AMD7930_DR);
396         sbus_writeb(((map->stgr >> 8) & 0xff), amd->regs + AMD7930_DR);
397 
398         sbus_writeb(AMR_MAP_GER, amd->regs + AMD7930_CR);
399         sbus_writeb(((map->ger >> 0) & 0xff), amd->regs + AMD7930_DR);
400         sbus_writeb(((map->ger >> 8) & 0xff), amd->regs + AMD7930_DR);
401 
402         sbus_writeb(AMR_MAP_MMR1, amd->regs + AMD7930_CR);
403         sbus_writeb(map->mmr1, amd->regs + AMD7930_DR);
404 
405         sbus_writeb(AMR_MAP_MMR2, amd->regs + AMD7930_CR);
406         sbus_writeb(map->mmr2, amd->regs + AMD7930_DR);
407 }
408 
409 /* gx, gr & stg gains.  this table must contain 256 elements with
410  * the 0th being "infinity" (the magic value 9008).  The remaining
411  * elements match sun's gain curve (but with higher resolution):
412  * -18 to 0dB in .16dB steps then 0 to 12dB in .08dB steps.
413  */
414 static __const__ __u16 gx_coeff[256] = {
415         0x9008, 0x8b7c, 0x8b51, 0x8b45, 0x8b42, 0x8b3b, 0x8b36, 0x8b33,
416         0x8b32, 0x8b2a, 0x8b2b, 0x8b2c, 0x8b25, 0x8b23, 0x8b22, 0x8b22,
417         0x9122, 0x8b1a, 0x8aa3, 0x8aa3, 0x8b1c, 0x8aa6, 0x912d, 0x912b,
418         0x8aab, 0x8b12, 0x8aaa, 0x8ab2, 0x9132, 0x8ab4, 0x913c, 0x8abb,
419         0x9142, 0x9144, 0x9151, 0x8ad5, 0x8aeb, 0x8a79, 0x8a5a, 0x8a4a,
420         0x8b03, 0x91c2, 0x91bb, 0x8a3f, 0x8a33, 0x91b2, 0x9212, 0x9213,
421         0x8a2c, 0x921d, 0x8a23, 0x921a, 0x9222, 0x9223, 0x922d, 0x9231,
422         0x9234, 0x9242, 0x925b, 0x92dd, 0x92c1, 0x92b3, 0x92ab, 0x92a4,
423         0x92a2, 0x932b, 0x9341, 0x93d3, 0x93b2, 0x93a2, 0x943c, 0x94b2,
424         0x953a, 0x9653, 0x9782, 0x9e21, 0x9d23, 0x9cd2, 0x9c23, 0x9baa,
425         0x9bde, 0x9b33, 0x9b22, 0x9b1d, 0x9ab2, 0xa142, 0xa1e5, 0x9a3b,
426         0xa213, 0xa1a2, 0xa231, 0xa2eb, 0xa313, 0xa334, 0xa421, 0xa54b,
427         0xada4, 0xac23, 0xab3b, 0xaaab, 0xaa5c, 0xb1a3, 0xb2ca, 0xb3bd,
428         0xbe24, 0xbb2b, 0xba33, 0xc32b, 0xcb5a, 0xd2a2, 0xe31d, 0x0808,
429         0x72ba, 0x62c2, 0x5c32, 0x52db, 0x513e, 0x4cce, 0x43b2, 0x4243,
430         0x41b4, 0x3b12, 0x3bc3, 0x3df2, 0x34bd, 0x3334, 0x32c2, 0x3224,
431         0x31aa, 0x2a7b, 0x2aaa, 0x2b23, 0x2bba, 0x2c42, 0x2e23, 0x25bb,
432         0x242b, 0x240f, 0x231a, 0x22bb, 0x2241, 0x2223, 0x221f, 0x1a33,
433         0x1a4a, 0x1acd, 0x2132, 0x1b1b, 0x1b2c, 0x1b62, 0x1c12, 0x1c32,
434         0x1d1b, 0x1e71, 0x16b1, 0x1522, 0x1434, 0x1412, 0x1352, 0x1323,
435         0x1315, 0x12bc, 0x127a, 0x1235, 0x1226, 0x11a2, 0x1216, 0x0a2a,
436         0x11bc, 0x11d1, 0x1163, 0x0ac2, 0x0ab2, 0x0aab, 0x0b1b, 0x0b23,
437         0x0b33, 0x0c0f, 0x0bb3, 0x0c1b, 0x0c3e, 0x0cb1, 0x0d4c, 0x0ec1,
438         0x079a, 0x0614, 0x0521, 0x047c, 0x0422, 0x03b1, 0x03e3, 0x0333,
439         0x0322, 0x031c, 0x02aa, 0x02ba, 0x02f2, 0x0242, 0x0232, 0x0227,
440         0x0222, 0x021b, 0x01ad, 0x0212, 0x01b2, 0x01bb, 0x01cb, 0x01f6,
441         0x0152, 0x013a, 0x0133, 0x0131, 0x012c, 0x0123, 0x0122, 0x00a2,
442         0x011b, 0x011e, 0x0114, 0x00b1, 0x00aa, 0x00b3, 0x00bd, 0x00ba,
443         0x00c5, 0x00d3, 0x00f3, 0x0062, 0x0051, 0x0042, 0x003b, 0x0033,
444         0x0032, 0x002a, 0x002c, 0x0025, 0x0023, 0x0022, 0x001a, 0x0021,
445         0x001b, 0x001b, 0x001d, 0x0015, 0x0013, 0x0013, 0x0012, 0x0012,
446         0x000a, 0x000a, 0x0011, 0x0011, 0x000b, 0x000b, 0x000c, 0x000e,
447 };
448 
449 static __const__ __u16 ger_coeff[] = {
450         0x431f, /* 5. dB */
451         0x331f, /* 5.5 dB */
452         0x40dd, /* 6. dB */
453         0x11dd, /* 6.5 dB */
454         0x440f, /* 7. dB */
455         0x411f, /* 7.5 dB */
456         0x311f, /* 8. dB */
457         0x5520, /* 8.5 dB */
458         0x10dd, /* 9. dB */
459         0x4211, /* 9.5 dB */
460         0x410f, /* 10. dB */
461         0x111f, /* 10.5 dB */
462         0x600b, /* 11. dB */
463         0x00dd, /* 11.5 dB */
464         0x4210, /* 12. dB */
465         0x110f, /* 13. dB */
466         0x7200, /* 14. dB */
467         0x2110, /* 15. dB */
468         0x2200, /* 15.9 dB */
469         0x000b, /* 16.9 dB */
470         0x000f  /* 18. dB */
471 };
472 
473 /* Update amd7930_map settings and program them into the hardware.
474  * The amd->lock is held and local interrupts are disabled.
475  */
476 static void __amd7930_update_map(struct snd_amd7930 *amd)
477 {
478         struct amd7930_map *map = &amd->map;
479         int level;
480 
481         map->gx = gx_coeff[amd->rgain];
482         map->stgr = gx_coeff[amd->mgain];
483         level = (amd->pgain * (256 + ARRAY_SIZE(ger_coeff))) >> 8;
484         if (level >= 256) {
485                 map->ger = ger_coeff[level - 256];
486                 map->gr = gx_coeff[255];
487         } else {
488                 map->ger = ger_coeff[0];
489                 map->gr = gx_coeff[level];
490         }
491         __amd7930_write_map(amd);
492 }
493 
494 static irqreturn_t snd_amd7930_interrupt(int irq, void *dev_id)
495 {
496         struct snd_amd7930 *amd = dev_id;
497         unsigned int elapsed;
498         u8 ir;
499 
500         spin_lock(&amd->lock);
501 
502         elapsed = 0;
503 
504         ir = sbus_readb(amd->regs + AMD7930_IR);
505         if (ir & AMR_IR_BBUF) {
506                 u8 byte;
507 
508                 if (amd->flags & AMD7930_FLAG_PLAYBACK) {
509                         if (amd->p_left > 0) {
510                                 byte = *(amd->p_cur++);
511                                 amd->p_left--;
512                                 sbus_writeb(byte, amd->regs + AMD7930_BBTB);
513                                 if (amd->p_left == 0)
514                                         elapsed |= AMD7930_FLAG_PLAYBACK;
515                         } else
516                                 sbus_writeb(0, amd->regs + AMD7930_BBTB);
517                 } else if (amd->flags & AMD7930_FLAG_CAPTURE) {
518                         byte = sbus_readb(amd->regs + AMD7930_BBRB);
519                         if (amd->c_left > 0) {
520                                 *(amd->c_cur++) = byte;
521                                 amd->c_left--;
522                                 if (amd->c_left == 0)
523                                         elapsed |= AMD7930_FLAG_CAPTURE;
524                         }
525                 }
526         }
527         spin_unlock(&amd->lock);
528 
529         if (elapsed & AMD7930_FLAG_PLAYBACK)
530                 snd_pcm_period_elapsed(amd->playback_substream);
531         else
532                 snd_pcm_period_elapsed(amd->capture_substream);
533 
534         return IRQ_HANDLED;
535 }
536 
537 static int snd_amd7930_trigger(struct snd_amd7930 *amd, unsigned int flag, int cmd)
538 {
539         unsigned long flags;
540         int result = 0;
541 
542         spin_lock_irqsave(&amd->lock, flags);
543         if (cmd == SNDRV_PCM_TRIGGER_START) {
544                 if (!(amd->flags & flag)) {
545                         amd->flags |= flag;
546 
547                         /* Enable B channel interrupts.  */
548                         sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
549                         sbus_writeb(AM_MUX_MCR4_ENABLE_INTS, amd->regs + AMD7930_DR);
550                 }
551         } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
552                 if (amd->flags & flag) {
553                         amd->flags &= ~flag;
554 
555                         /* Disable B channel interrupts.  */
556                         sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
557                         sbus_writeb(0, amd->regs + AMD7930_DR);
558                 }
559         } else {
560                 result = -EINVAL;
561         }
562         spin_unlock_irqrestore(&amd->lock, flags);
563 
564         return result;
565 }
566 
567 static int snd_amd7930_playback_trigger(struct snd_pcm_substream *substream,
568                                         int cmd)
569 {
570         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
571         return snd_amd7930_trigger(amd, AMD7930_FLAG_PLAYBACK, cmd);
572 }
573 
574 static int snd_amd7930_capture_trigger(struct snd_pcm_substream *substream,
575                                        int cmd)
576 {
577         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
578         return snd_amd7930_trigger(amd, AMD7930_FLAG_CAPTURE, cmd);
579 }
580 
581 static int snd_amd7930_playback_prepare(struct snd_pcm_substream *substream)
582 {
583         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
584         struct snd_pcm_runtime *runtime = substream->runtime;
585         unsigned int size = snd_pcm_lib_buffer_bytes(substream);
586         unsigned long flags;
587         u8 new_mmr1;
588 
589         spin_lock_irqsave(&amd->lock, flags);
590 
591         amd->flags |= AMD7930_FLAG_PLAYBACK;
592 
593         /* Setup the pseudo-dma transfer pointers.  */
594         amd->p_orig = amd->p_cur = runtime->dma_area;
595         amd->p_left = size;
596 
597         /* Put the chip into the correct encoding format.  */
598         new_mmr1 = amd->map.mmr1;
599         if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
600                 new_mmr1 |= AM_MAP_MMR1_ALAW;
601         else
602                 new_mmr1 &= ~AM_MAP_MMR1_ALAW;
603         if (new_mmr1 != amd->map.mmr1) {
604                 amd->map.mmr1 = new_mmr1;
605                 __amd7930_update_map(amd);
606         }
607 
608         spin_unlock_irqrestore(&amd->lock, flags);
609 
610         return 0;
611 }
612 
613 static int snd_amd7930_capture_prepare(struct snd_pcm_substream *substream)
614 {
615         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
616         struct snd_pcm_runtime *runtime = substream->runtime;
617         unsigned int size = snd_pcm_lib_buffer_bytes(substream);
618         unsigned long flags;
619         u8 new_mmr1;
620 
621         spin_lock_irqsave(&amd->lock, flags);
622 
623         amd->flags |= AMD7930_FLAG_CAPTURE;
624 
625         /* Setup the pseudo-dma transfer pointers.  */
626         amd->c_orig = amd->c_cur = runtime->dma_area;
627         amd->c_left = size;
628 
629         /* Put the chip into the correct encoding format.  */
630         new_mmr1 = amd->map.mmr1;
631         if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
632                 new_mmr1 |= AM_MAP_MMR1_ALAW;
633         else
634                 new_mmr1 &= ~AM_MAP_MMR1_ALAW;
635         if (new_mmr1 != amd->map.mmr1) {
636                 amd->map.mmr1 = new_mmr1;
637                 __amd7930_update_map(amd);
638         }
639 
640         spin_unlock_irqrestore(&amd->lock, flags);
641 
642         return 0;
643 }
644 
645 static snd_pcm_uframes_t snd_amd7930_playback_pointer(struct snd_pcm_substream *substream)
646 {
647         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
648         size_t ptr;
649 
650         if (!(amd->flags & AMD7930_FLAG_PLAYBACK))
651                 return 0;
652         ptr = amd->p_cur - amd->p_orig;
653         return bytes_to_frames(substream->runtime, ptr);
654 }
655 
656 static snd_pcm_uframes_t snd_amd7930_capture_pointer(struct snd_pcm_substream *substream)
657 {
658         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
659         size_t ptr;
660 
661         if (!(amd->flags & AMD7930_FLAG_CAPTURE))
662                 return 0;
663 
664         ptr = amd->c_cur - amd->c_orig;
665         return bytes_to_frames(substream->runtime, ptr);
666 }
667 
668 /* Playback and capture have identical properties.  */
669 static struct snd_pcm_hardware snd_amd7930_pcm_hw =
670 {
671         .info                   = (SNDRV_PCM_INFO_MMAP |
672                                    SNDRV_PCM_INFO_MMAP_VALID |
673                                    SNDRV_PCM_INFO_INTERLEAVED |
674                                    SNDRV_PCM_INFO_BLOCK_TRANSFER |
675                                    SNDRV_PCM_INFO_HALF_DUPLEX),
676         .formats                = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
677         .rates                  = SNDRV_PCM_RATE_8000,
678         .rate_min               = 8000,
679         .rate_max               = 8000,
680         .channels_min           = 1,
681         .channels_max           = 1,
682         .buffer_bytes_max       = (64*1024),
683         .period_bytes_min       = 1,
684         .period_bytes_max       = (64*1024),
685         .periods_min            = 1,
686         .periods_max            = 1024,
687 };
688 
689 static int snd_amd7930_playback_open(struct snd_pcm_substream *substream)
690 {
691         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
692         struct snd_pcm_runtime *runtime = substream->runtime;
693 
694         amd->playback_substream = substream;
695         runtime->hw = snd_amd7930_pcm_hw;
696         return 0;
697 }
698 
699 static int snd_amd7930_capture_open(struct snd_pcm_substream *substream)
700 {
701         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
702         struct snd_pcm_runtime *runtime = substream->runtime;
703 
704         amd->capture_substream = substream;
705         runtime->hw = snd_amd7930_pcm_hw;
706         return 0;
707 }
708 
709 static int snd_amd7930_playback_close(struct snd_pcm_substream *substream)
710 {
711         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
712 
713         amd->playback_substream = NULL;
714         return 0;
715 }
716 
717 static int snd_amd7930_capture_close(struct snd_pcm_substream *substream)
718 {
719         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
720 
721         amd->capture_substream = NULL;
722         return 0;
723 }
724 
725 static int snd_amd7930_hw_params(struct snd_pcm_substream *substream,
726                                     struct snd_pcm_hw_params *hw_params)
727 {
728         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
729 }
730 
731 static int snd_amd7930_hw_free(struct snd_pcm_substream *substream)
732 {
733         return snd_pcm_lib_free_pages(substream);
734 }
735 
736 static struct snd_pcm_ops snd_amd7930_playback_ops = {
737         .open           =       snd_amd7930_playback_open,
738         .close          =       snd_amd7930_playback_close,
739         .ioctl          =       snd_pcm_lib_ioctl,
740         .hw_params      =       snd_amd7930_hw_params,
741         .hw_free        =       snd_amd7930_hw_free,
742         .prepare        =       snd_amd7930_playback_prepare,
743         .trigger        =       snd_amd7930_playback_trigger,
744         .pointer        =       snd_amd7930_playback_pointer,
745 };
746 
747 static struct snd_pcm_ops snd_amd7930_capture_ops = {
748         .open           =       snd_amd7930_capture_open,
749         .close          =       snd_amd7930_capture_close,
750         .ioctl          =       snd_pcm_lib_ioctl,
751         .hw_params      =       snd_amd7930_hw_params,
752         .hw_free        =       snd_amd7930_hw_free,
753         .prepare        =       snd_amd7930_capture_prepare,
754         .trigger        =       snd_amd7930_capture_trigger,
755         .pointer        =       snd_amd7930_capture_pointer,
756 };
757 
758 static int snd_amd7930_pcm(struct snd_amd7930 *amd)
759 {
760         struct snd_pcm *pcm;
761         int err;
762 
763         if ((err = snd_pcm_new(amd->card,
764                                /* ID */             "sun_amd7930",
765                                /* device */         0,
766                                /* playback count */ 1,
767                                /* capture count */  1, &pcm)) < 0)
768                 return err;
769 
770         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_amd7930_playback_ops);
771         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_amd7930_capture_ops);
772 
773         pcm->private_data = amd;
774         pcm->info_flags = 0;
775         strcpy(pcm->name, amd->card->shortname);
776         amd->pcm = pcm;
777 
778         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
779                                               snd_dma_continuous_data(GFP_KERNEL),
780                                               64*1024, 64*1024);
781 
782         return 0;
783 }
784 
785 #define VOLUME_MONITOR  0
786 #define VOLUME_CAPTURE  1
787 #define VOLUME_PLAYBACK 2
788 
789 static int snd_amd7930_info_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_info *uinfo)
790 {
791         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
792         uinfo->count = 1;
793         uinfo->value.integer.min = 0;
794         uinfo->value.integer.max = 255;
795 
796         return 0;
797 }
798 
799 static int snd_amd7930_get_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol)
800 {
801         struct snd_amd7930 *amd = snd_kcontrol_chip(kctl);
802         int type = kctl->private_value;
803         int *swval;
804 
805         switch (type) {
806         case VOLUME_MONITOR:
807                 swval = &amd->mgain;
808                 break;
809         case VOLUME_CAPTURE:
810                 swval = &amd->rgain;
811                 break;
812         case VOLUME_PLAYBACK:
813         default:
814                 swval = &amd->pgain;
815                 break;
816         }
817 
818         ucontrol->value.integer.value[0] = *swval;
819 
820         return 0;
821 }
822 
823 static int snd_amd7930_put_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol)
824 {
825         struct snd_amd7930 *amd = snd_kcontrol_chip(kctl);
826         unsigned long flags;
827         int type = kctl->private_value;
828         int *swval, change;
829 
830         switch (type) {
831         case VOLUME_MONITOR:
832                 swval = &amd->mgain;
833                 break;
834         case VOLUME_CAPTURE:
835                 swval = &amd->rgain;
836                 break;
837         case VOLUME_PLAYBACK:
838         default:
839                 swval = &amd->pgain;
840                 break;
841         }
842 
843         spin_lock_irqsave(&amd->lock, flags);
844 
845         if (*swval != ucontrol->value.integer.value[0]) {
846                 *swval = ucontrol->value.integer.value[0] & 0xff;
847                 __amd7930_update_map(amd);
848                 change = 1;
849         } else
850                 change = 0;
851 
852         spin_unlock_irqrestore(&amd->lock, flags);
853 
854         return change;
855 }
856 
857 static struct snd_kcontrol_new amd7930_controls[] = {
858         {
859                 .iface          =       SNDRV_CTL_ELEM_IFACE_MIXER,
860                 .name           =       "Monitor Volume",
861                 .index          =       0,
862                 .info           =       snd_amd7930_info_volume,
863                 .get            =       snd_amd7930_get_volume,
864                 .put            =       snd_amd7930_put_volume,
865                 .private_value  =       VOLUME_MONITOR,
866         },
867         {
868                 .iface          =       SNDRV_CTL_ELEM_IFACE_MIXER,
869                 .name           =       "Capture Volume",
870                 .index          =       0,
871                 .info           =       snd_amd7930_info_volume,
872                 .get            =       snd_amd7930_get_volume,
873                 .put            =       snd_amd7930_put_volume,
874                 .private_value  =       VOLUME_CAPTURE,
875         },
876         {
877                 .iface          =       SNDRV_CTL_ELEM_IFACE_MIXER,
878                 .name           =       "Playback Volume",
879                 .index          =       0,
880                 .info           =       snd_amd7930_info_volume,
881                 .get            =       snd_amd7930_get_volume,
882                 .put            =       snd_amd7930_put_volume,
883                 .private_value  =       VOLUME_PLAYBACK,
884         },
885 };
886 
887 static int snd_amd7930_mixer(struct snd_amd7930 *amd)
888 {
889         struct snd_card *card;
890         int idx, err;
891 
892         if (snd_BUG_ON(!amd || !amd->card))
893                 return -EINVAL;
894 
895         card = amd->card;
896         strcpy(card->mixername, card->shortname);
897 
898         for (idx = 0; idx < ARRAY_SIZE(amd7930_controls); idx++) {
899                 if ((err = snd_ctl_add(card,
900                                        snd_ctl_new1(&amd7930_controls[idx], amd))) < 0)
901                         return err;
902         }
903 
904         return 0;
905 }
906 
907 static int snd_amd7930_free(struct snd_amd7930 *amd)
908 {
909         struct platform_device *op = amd->op;
910 
911         amd7930_idle(amd);
912 
913         if (amd->irq)
914                 free_irq(amd->irq, amd);
915 
916         if (amd->regs)
917                 of_iounmap(&op->resource[0], amd->regs,
918                            resource_size(&op->resource[0]));
919 
920         kfree(amd);
921 
922         return 0;
923 }
924 
925 static int snd_amd7930_dev_free(struct snd_device *device)
926 {
927         struct snd_amd7930 *amd = device->device_data;
928 
929         return snd_amd7930_free(amd);
930 }
931 
932 static struct snd_device_ops snd_amd7930_dev_ops = {
933         .dev_free       =       snd_amd7930_dev_free,
934 };
935 
936 static int snd_amd7930_create(struct snd_card *card,
937                               struct platform_device *op,
938                               int irq, int dev,
939                               struct snd_amd7930 **ramd)
940 {
941         struct snd_amd7930 *amd;
942         unsigned long flags;
943         int err;
944 
945         *ramd = NULL;
946         amd = kzalloc(sizeof(*amd), GFP_KERNEL);
947         if (amd == NULL)
948                 return -ENOMEM;
949 
950         spin_lock_init(&amd->lock);
951         amd->card = card;
952         amd->op = op;
953 
954         amd->regs = of_ioremap(&op->resource[0], 0,
955                                resource_size(&op->resource[0]), "amd7930");
956         if (!amd->regs) {
957                 snd_printk(KERN_ERR
958                            "amd7930-%d: Unable to map chip registers.\n", dev);
959                 return -EIO;
960         }
961 
962         amd7930_idle(amd);
963 
964         if (request_irq(irq, snd_amd7930_interrupt,
965                         IRQF_SHARED, "amd7930", amd)) {
966                 snd_printk(KERN_ERR "amd7930-%d: Unable to grab IRQ %d\n",
967                            dev, irq);
968                 snd_amd7930_free(amd);
969                 return -EBUSY;
970         }
971         amd->irq = irq;
972 
973         amd7930_enable_ints(amd);
974 
975         spin_lock_irqsave(&amd->lock, flags);
976 
977         amd->rgain = 128;
978         amd->pgain = 200;
979         amd->mgain = 0;
980 
981         memset(&amd->map, 0, sizeof(amd->map));
982         amd->map.mmr1 = (AM_MAP_MMR1_GX | AM_MAP_MMR1_GER |
983                          AM_MAP_MMR1_GR | AM_MAP_MMR1_STG);
984         amd->map.mmr2 = (AM_MAP_MMR2_LS | AM_MAP_MMR2_AINB);
985 
986         __amd7930_update_map(amd);
987 
988         /* Always MUX audio (Ba) to channel Bb. */
989         sbus_writeb(AMR_MUX_MCR1, amd->regs + AMD7930_CR);
990         sbus_writeb(AM_MUX_CHANNEL_Ba | (AM_MUX_CHANNEL_Bb << 4),
991                     amd->regs + AMD7930_DR);
992 
993         spin_unlock_irqrestore(&amd->lock, flags);
994 
995         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
996                                   amd, &snd_amd7930_dev_ops)) < 0) {
997                 snd_amd7930_free(amd);
998                 return err;
999         }
1000 
1001         *ramd = amd;
1002         return 0;
1003 }
1004 
1005 static int amd7930_sbus_probe(struct platform_device *op)
1006 {
1007         struct resource *rp = &op->resource[0];
1008         static int dev_num;
1009         struct snd_card *card;
1010         struct snd_amd7930 *amd;
1011         int err, irq;
1012 
1013         irq = op->archdata.irqs[0];
1014 
1015         if (dev_num >= SNDRV_CARDS)
1016                 return -ENODEV;
1017         if (!enable[dev_num]) {
1018                 dev_num++;
1019                 return -ENOENT;
1020         }
1021 
1022         err = snd_card_create(index[dev_num], id[dev_num], THIS_MODULE, 0,
1023                               &card);
1024         if (err < 0)
1025                 return err;
1026 
1027         strcpy(card->driver, "AMD7930");
1028         strcpy(card->shortname, "Sun AMD7930");
1029         sprintf(card->longname, "%s at 0x%02lx:0x%08Lx, irq %d",
1030                 card->shortname,
1031                 rp->flags & 0xffL,
1032                 (unsigned long long)rp->start,
1033                 irq);
1034 
1035         if ((err = snd_amd7930_create(card, op,
1036                                       irq, dev_num, &amd)) < 0)
1037                 goto out_err;
1038 
1039         if ((err = snd_amd7930_pcm(amd)) < 0)
1040                 goto out_err;
1041 
1042         if ((err = snd_amd7930_mixer(amd)) < 0)
1043                 goto out_err;
1044 
1045         if ((err = snd_card_register(card)) < 0)
1046                 goto out_err;
1047 
1048         amd->next = amd7930_list;
1049         amd7930_list = amd;
1050 
1051         dev_num++;
1052 
1053         return 0;
1054 
1055 out_err:
1056         snd_card_free(card);
1057         return err;
1058 }
1059 
1060 static const struct of_device_id amd7930_match[] = {
1061         {
1062                 .name = "audio",
1063         },
1064         {},
1065 };
1066 
1067 static struct platform_driver amd7930_sbus_driver = {
1068         .driver = {
1069                 .name = "audio",
1070                 .owner = THIS_MODULE,
1071                 .of_match_table = amd7930_match,
1072         },
1073         .probe          = amd7930_sbus_probe,
1074 };
1075 
1076 static int __init amd7930_init(void)
1077 {
1078         return platform_driver_register(&amd7930_sbus_driver);
1079 }
1080 
1081 static void __exit amd7930_exit(void)
1082 {
1083         struct snd_amd7930 *p = amd7930_list;
1084 
1085         while (p != NULL) {
1086                 struct snd_amd7930 *next = p->next;
1087 
1088                 snd_card_free(p->card);
1089 
1090                 p = next;
1091         }
1092 
1093         amd7930_list = NULL;
1094 
1095         platform_driver_unregister(&amd7930_sbus_driver);
1096 }
1097 
1098 module_init(amd7930_init);
1099 module_exit(amd7930_exit);
1100 

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