Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/sound/soc/tegra/tegra30_i2s.c

  1 /*
  2  * tegra30_i2s.c - Tegra30 I2S driver
  3  *
  4  * Author: Stephen Warren <swarren@nvidia.com>
  5  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
  6  *
  7  * Based on code copyright/by:
  8  *
  9  * Copyright (c) 2009-2010, NVIDIA Corporation.
 10  * Scott Peterson <speterson@nvidia.com>
 11  *
 12  * Copyright (C) 2010 Google, Inc.
 13  * Iliyan Malchev <malchev@google.com>
 14  *
 15  * This program is free software; you can redistribute it and/or modify it
 16  * under the terms and conditions of the GNU General Public License,
 17  * version 2, as published by the Free Software Foundation.
 18  *
 19  * This program is distributed in the hope it will be useful, but WITHOUT
 20  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 21  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 22  * more details.
 23  *
 24  * You should have received a copy of the GNU General Public License
 25  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 26  */
 27 
 28 #include <linux/clk.h>
 29 #include <linux/device.h>
 30 #include <linux/io.h>
 31 #include <linux/module.h>
 32 #include <linux/of.h>
 33 #include <linux/of_device.h>
 34 #include <linux/platform_device.h>
 35 #include <linux/pm_runtime.h>
 36 #include <linux/regmap.h>
 37 #include <linux/slab.h>
 38 #include <sound/core.h>
 39 #include <sound/pcm.h>
 40 #include <sound/pcm_params.h>
 41 #include <sound/soc.h>
 42 #include <sound/dmaengine_pcm.h>
 43 
 44 #include "tegra30_ahub.h"
 45 #include "tegra30_i2s.h"
 46 
 47 #define DRV_NAME "tegra30-i2s"
 48 
 49 static int tegra30_i2s_runtime_suspend(struct device *dev)
 50 {
 51         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
 52 
 53         regcache_cache_only(i2s->regmap, true);
 54 
 55         clk_disable_unprepare(i2s->clk_i2s);
 56 
 57         return 0;
 58 }
 59 
 60 static int tegra30_i2s_runtime_resume(struct device *dev)
 61 {
 62         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
 63         int ret;
 64 
 65         ret = clk_prepare_enable(i2s->clk_i2s);
 66         if (ret) {
 67                 dev_err(dev, "clk_enable failed: %d\n", ret);
 68                 return ret;
 69         }
 70 
 71         regcache_cache_only(i2s->regmap, false);
 72 
 73         return 0;
 74 }
 75 
 76 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
 77                                 unsigned int fmt)
 78 {
 79         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 80         unsigned int mask = 0, val = 0;
 81 
 82         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 83         case SND_SOC_DAIFMT_NB_NF:
 84                 break;
 85         default:
 86                 return -EINVAL;
 87         }
 88 
 89         mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
 90         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 91         case SND_SOC_DAIFMT_CBS_CFS:
 92                 val |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
 93                 break;
 94         case SND_SOC_DAIFMT_CBM_CFM:
 95                 break;
 96         default:
 97                 return -EINVAL;
 98         }
 99 
100         mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
101                 TEGRA30_I2S_CTRL_LRCK_MASK;
102         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
103         case SND_SOC_DAIFMT_DSP_A:
104                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
105                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
106                 break;
107         case SND_SOC_DAIFMT_DSP_B:
108                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
109                 val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
110                 break;
111         case SND_SOC_DAIFMT_I2S:
112                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
113                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
114                 break;
115         case SND_SOC_DAIFMT_RIGHT_J:
116                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
117                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
118                 break;
119         case SND_SOC_DAIFMT_LEFT_J:
120                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
121                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
122                 break;
123         default:
124                 return -EINVAL;
125         }
126 
127         pm_runtime_get_sync(dai->dev);
128         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
129         pm_runtime_put(dai->dev);
130 
131         return 0;
132 }
133 
134 static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
135                                  struct snd_pcm_hw_params *params,
136                                  struct snd_soc_dai *dai)
137 {
138         struct device *dev = dai->dev;
139         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
140         unsigned int mask, val, reg;
141         int ret, sample_size, srate, i2sclock, bitcnt;
142         struct tegra30_ahub_cif_conf cif_conf;
143 
144         if (params_channels(params) != 2)
145                 return -EINVAL;
146 
147         mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
148         switch (params_format(params)) {
149         case SNDRV_PCM_FORMAT_S16_LE:
150                 val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
151                 sample_size = 16;
152                 break;
153         default:
154                 return -EINVAL;
155         }
156 
157         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
158 
159         srate = params_rate(params);
160 
161         /* Final "* 2" required by Tegra hardware */
162         i2sclock = srate * params_channels(params) * sample_size * 2;
163 
164         bitcnt = (i2sclock / (2 * srate)) - 1;
165         if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
166                 return -EINVAL;
167 
168         ret = clk_set_rate(i2s->clk_i2s, i2sclock);
169         if (ret) {
170                 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
171                 return ret;
172         }
173 
174         val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
175 
176         if (i2sclock % (2 * srate))
177                 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
178 
179         regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
180 
181         cif_conf.threshold = 0;
182         cif_conf.audio_channels = 2;
183         cif_conf.client_channels = 2;
184         cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
185         cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
186         cif_conf.expand = 0;
187         cif_conf.stereo_conv = 0;
188         cif_conf.replicate = 0;
189         cif_conf.truncate = 0;
190         cif_conf.mono_conv = 0;
191 
192         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
193                 cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
194                 reg = TEGRA30_I2S_CIF_RX_CTRL;
195         } else {
196                 cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
197                 reg = TEGRA30_I2S_CIF_TX_CTRL;
198         }
199 
200         i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);
201 
202         val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
203               (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
204         regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
205 
206         return 0;
207 }
208 
209 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
210 {
211         tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
212         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
213                            TEGRA30_I2S_CTRL_XFER_EN_TX,
214                            TEGRA30_I2S_CTRL_XFER_EN_TX);
215 }
216 
217 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
218 {
219         tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
220         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
221                            TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
222 }
223 
224 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
225 {
226         tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
227         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
228                            TEGRA30_I2S_CTRL_XFER_EN_RX,
229                            TEGRA30_I2S_CTRL_XFER_EN_RX);
230 }
231 
232 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
233 {
234         tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
235         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
236                            TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
237 }
238 
239 static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
240                                 struct snd_soc_dai *dai)
241 {
242         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
243 
244         switch (cmd) {
245         case SNDRV_PCM_TRIGGER_START:
246         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
247         case SNDRV_PCM_TRIGGER_RESUME:
248                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
249                         tegra30_i2s_start_playback(i2s);
250                 else
251                         tegra30_i2s_start_capture(i2s);
252                 break;
253         case SNDRV_PCM_TRIGGER_STOP:
254         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
255         case SNDRV_PCM_TRIGGER_SUSPEND:
256                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
257                         tegra30_i2s_stop_playback(i2s);
258                 else
259                         tegra30_i2s_stop_capture(i2s);
260                 break;
261         default:
262                 return -EINVAL;
263         }
264 
265         return 0;
266 }
267 
268 static int tegra30_i2s_probe(struct snd_soc_dai *dai)
269 {
270         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
271 
272         dai->capture_dma_data = &i2s->capture_dma_data;
273         dai->playback_dma_data = &i2s->playback_dma_data;
274 
275         return 0;
276 }
277 
278 static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
279         .set_fmt        = tegra30_i2s_set_fmt,
280         .hw_params      = tegra30_i2s_hw_params,
281         .trigger        = tegra30_i2s_trigger,
282 };
283 
284 static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
285         .probe = tegra30_i2s_probe,
286         .playback = {
287                 .stream_name = "Playback",
288                 .channels_min = 2,
289                 .channels_max = 2,
290                 .rates = SNDRV_PCM_RATE_8000_96000,
291                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
292         },
293         .capture = {
294                 .stream_name = "Capture",
295                 .channels_min = 2,
296                 .channels_max = 2,
297                 .rates = SNDRV_PCM_RATE_8000_96000,
298                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
299         },
300         .ops = &tegra30_i2s_dai_ops,
301         .symmetric_rates = 1,
302 };
303 
304 static const struct snd_soc_component_driver tegra30_i2s_component = {
305         .name           = DRV_NAME,
306 };
307 
308 static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
309 {
310         switch (reg) {
311         case TEGRA30_I2S_CTRL:
312         case TEGRA30_I2S_TIMING:
313         case TEGRA30_I2S_OFFSET:
314         case TEGRA30_I2S_CH_CTRL:
315         case TEGRA30_I2S_SLOT_CTRL:
316         case TEGRA30_I2S_CIF_RX_CTRL:
317         case TEGRA30_I2S_CIF_TX_CTRL:
318         case TEGRA30_I2S_FLOWCTL:
319         case TEGRA30_I2S_TX_STEP:
320         case TEGRA30_I2S_FLOW_STATUS:
321         case TEGRA30_I2S_FLOW_TOTAL:
322         case TEGRA30_I2S_FLOW_OVER:
323         case TEGRA30_I2S_FLOW_UNDER:
324         case TEGRA30_I2S_LCOEF_1_4_0:
325         case TEGRA30_I2S_LCOEF_1_4_1:
326         case TEGRA30_I2S_LCOEF_1_4_2:
327         case TEGRA30_I2S_LCOEF_1_4_3:
328         case TEGRA30_I2S_LCOEF_1_4_4:
329         case TEGRA30_I2S_LCOEF_1_4_5:
330         case TEGRA30_I2S_LCOEF_2_4_0:
331         case TEGRA30_I2S_LCOEF_2_4_1:
332         case TEGRA30_I2S_LCOEF_2_4_2:
333                 return true;
334         default:
335                 return false;
336         }
337 }
338 
339 static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
340 {
341         switch (reg) {
342         case TEGRA30_I2S_FLOW_STATUS:
343         case TEGRA30_I2S_FLOW_TOTAL:
344         case TEGRA30_I2S_FLOW_OVER:
345         case TEGRA30_I2S_FLOW_UNDER:
346                 return true;
347         default:
348                 return false;
349         }
350 }
351 
352 static const struct regmap_config tegra30_i2s_regmap_config = {
353         .reg_bits = 32,
354         .reg_stride = 4,
355         .val_bits = 32,
356         .max_register = TEGRA30_I2S_LCOEF_2_4_2,
357         .writeable_reg = tegra30_i2s_wr_rd_reg,
358         .readable_reg = tegra30_i2s_wr_rd_reg,
359         .volatile_reg = tegra30_i2s_volatile_reg,
360         .cache_type = REGCACHE_FLAT,
361 };
362 
363 static const struct tegra30_i2s_soc_data tegra30_i2s_config = {
364         .set_audio_cif = tegra30_ahub_set_cif,
365 };
366 
367 static const struct tegra30_i2s_soc_data tegra124_i2s_config = {
368         .set_audio_cif = tegra124_ahub_set_cif,
369 };
370 
371 static const struct of_device_id tegra30_i2s_of_match[] = {
372         { .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
373         { .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
374         {},
375 };
376 
377 static int tegra30_i2s_platform_probe(struct platform_device *pdev)
378 {
379         struct tegra30_i2s *i2s;
380         const struct of_device_id *match;
381         u32 cif_ids[2];
382         struct resource *mem, *memregion;
383         void __iomem *regs;
384         int ret;
385 
386         i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
387         if (!i2s) {
388                 dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n");
389                 ret = -ENOMEM;
390                 goto err;
391         }
392         dev_set_drvdata(&pdev->dev, i2s);
393 
394         match = of_match_device(tegra30_i2s_of_match, &pdev->dev);
395         if (!match) {
396                 dev_err(&pdev->dev, "Error: No device match found\n");
397                 ret = -ENODEV;
398                 goto err;
399         }
400         i2s->soc_data = (struct tegra30_i2s_soc_data *)match->data;
401 
402         i2s->dai = tegra30_i2s_dai_template;
403         i2s->dai.name = dev_name(&pdev->dev);
404 
405         ret = of_property_read_u32_array(pdev->dev.of_node,
406                                          "nvidia,ahub-cif-ids", cif_ids,
407                                          ARRAY_SIZE(cif_ids));
408         if (ret < 0)
409                 goto err;
410 
411         i2s->playback_i2s_cif = cif_ids[0];
412         i2s->capture_i2s_cif = cif_ids[1];
413 
414         i2s->clk_i2s = clk_get(&pdev->dev, NULL);
415         if (IS_ERR(i2s->clk_i2s)) {
416                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
417                 ret = PTR_ERR(i2s->clk_i2s);
418                 goto err;
419         }
420 
421         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
422         if (!mem) {
423                 dev_err(&pdev->dev, "No memory resource\n");
424                 ret = -ENODEV;
425                 goto err_clk_put;
426         }
427 
428         memregion = devm_request_mem_region(&pdev->dev, mem->start,
429                                             resource_size(mem), DRV_NAME);
430         if (!memregion) {
431                 dev_err(&pdev->dev, "Memory region already claimed\n");
432                 ret = -EBUSY;
433                 goto err_clk_put;
434         }
435 
436         regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
437         if (!regs) {
438                 dev_err(&pdev->dev, "ioremap failed\n");
439                 ret = -ENOMEM;
440                 goto err_clk_put;
441         }
442 
443         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
444                                             &tegra30_i2s_regmap_config);
445         if (IS_ERR(i2s->regmap)) {
446                 dev_err(&pdev->dev, "regmap init failed\n");
447                 ret = PTR_ERR(i2s->regmap);
448                 goto err_clk_put;
449         }
450         regcache_cache_only(i2s->regmap, true);
451 
452         pm_runtime_enable(&pdev->dev);
453         if (!pm_runtime_enabled(&pdev->dev)) {
454                 ret = tegra30_i2s_runtime_resume(&pdev->dev);
455                 if (ret)
456                         goto err_pm_disable;
457         }
458 
459         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
460         i2s->playback_dma_data.maxburst = 4;
461         ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
462                                             i2s->playback_dma_chan,
463                                             sizeof(i2s->playback_dma_chan),
464                                             &i2s->playback_dma_data.addr);
465         if (ret) {
466                 dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
467                 goto err_suspend;
468         }
469         ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
470                                              i2s->playback_fifo_cif);
471         if (ret) {
472                 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
473                 goto err_free_tx_fifo;
474         }
475 
476         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
477         i2s->capture_dma_data.maxburst = 4;
478         ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
479                                             i2s->capture_dma_chan,
480                                             sizeof(i2s->capture_dma_chan),
481                                             &i2s->capture_dma_data.addr);
482         if (ret) {
483                 dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
484                 goto err_unroute_tx_fifo;
485         }
486         ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
487                                              i2s->capture_i2s_cif);
488         if (ret) {
489                 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
490                 goto err_free_rx_fifo;
491         }
492 
493         ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
494                                    &i2s->dai, 1);
495         if (ret) {
496                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
497                 ret = -ENOMEM;
498                 goto err_unroute_rx_fifo;
499         }
500 
501         ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
502                                 &i2s->dma_config, i2s->playback_dma_chan,
503                                 i2s->capture_dma_chan);
504         if (ret) {
505                 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
506                 goto err_unregister_component;
507         }
508 
509         return 0;
510 
511 err_unregister_component:
512         snd_soc_unregister_component(&pdev->dev);
513 err_unroute_rx_fifo:
514         tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
515 err_free_rx_fifo:
516         tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
517 err_unroute_tx_fifo:
518         tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
519 err_free_tx_fifo:
520         tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
521 err_suspend:
522         if (!pm_runtime_status_suspended(&pdev->dev))
523                 tegra30_i2s_runtime_suspend(&pdev->dev);
524 err_pm_disable:
525         pm_runtime_disable(&pdev->dev);
526 err_clk_put:
527         clk_put(i2s->clk_i2s);
528 err:
529         return ret;
530 }
531 
532 static int tegra30_i2s_platform_remove(struct platform_device *pdev)
533 {
534         struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
535 
536         pm_runtime_disable(&pdev->dev);
537         if (!pm_runtime_status_suspended(&pdev->dev))
538                 tegra30_i2s_runtime_suspend(&pdev->dev);
539 
540         tegra_pcm_platform_unregister(&pdev->dev);
541         snd_soc_unregister_component(&pdev->dev);
542 
543         tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
544         tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
545 
546         tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
547         tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
548 
549         clk_put(i2s->clk_i2s);
550 
551         return 0;
552 }
553 
554 #ifdef CONFIG_PM_SLEEP
555 static int tegra30_i2s_suspend(struct device *dev)
556 {
557         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
558 
559         regcache_mark_dirty(i2s->regmap);
560 
561         return 0;
562 }
563 
564 static int tegra30_i2s_resume(struct device *dev)
565 {
566         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
567         int ret;
568 
569         ret = pm_runtime_get_sync(dev);
570         if (ret < 0)
571                 return ret;
572         ret = regcache_sync(i2s->regmap);
573         pm_runtime_put(dev);
574 
575         return ret;
576 }
577 #endif
578 
579 static const struct dev_pm_ops tegra30_i2s_pm_ops = {
580         SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
581                            tegra30_i2s_runtime_resume, NULL)
582         SET_SYSTEM_SLEEP_PM_OPS(tegra30_i2s_suspend, tegra30_i2s_resume)
583 };
584 
585 static struct platform_driver tegra30_i2s_driver = {
586         .driver = {
587                 .name = DRV_NAME,
588                 .owner = THIS_MODULE,
589                 .of_match_table = tegra30_i2s_of_match,
590                 .pm = &tegra30_i2s_pm_ops,
591         },
592         .probe = tegra30_i2s_platform_probe,
593         .remove = tegra30_i2s_platform_remove,
594 };
595 module_platform_driver(tegra30_i2s_driver);
596 
597 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
598 MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
599 MODULE_LICENSE("GPL");
600 MODULE_ALIAS("platform:" DRV_NAME);
601 MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);
602 

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