Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/sound/soc/sh/fsi.c

  1 /*
  2  * Fifo-attached Serial Interface (FSI) support for SH7724
  3  *
  4  * Copyright (C) 2009 Renesas Solutions Corp.
  5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6  *
  7  * Based on ssi.c
  8  * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License version 2 as
 12  * published by the Free Software Foundation.
 13  */
 14 
 15 #include <linux/delay.h>
 16 #include <linux/dma-mapping.h>
 17 #include <linux/pm_runtime.h>
 18 #include <linux/io.h>
 19 #include <linux/of.h>
 20 #include <linux/of_device.h>
 21 #include <linux/scatterlist.h>
 22 #include <linux/sh_dma.h>
 23 #include <linux/slab.h>
 24 #include <linux/module.h>
 25 #include <linux/workqueue.h>
 26 #include <sound/soc.h>
 27 #include <sound/pcm_params.h>
 28 #include <sound/sh_fsi.h>
 29 
 30 /* PortA/PortB register */
 31 #define REG_DO_FMT      0x0000
 32 #define REG_DOFF_CTL    0x0004
 33 #define REG_DOFF_ST     0x0008
 34 #define REG_DI_FMT      0x000C
 35 #define REG_DIFF_CTL    0x0010
 36 #define REG_DIFF_ST     0x0014
 37 #define REG_CKG1        0x0018
 38 #define REG_CKG2        0x001C
 39 #define REG_DIDT        0x0020
 40 #define REG_DODT        0x0024
 41 #define REG_MUTE_ST     0x0028
 42 #define REG_OUT_DMAC    0x002C
 43 #define REG_OUT_SEL     0x0030
 44 #define REG_IN_DMAC     0x0038
 45 
 46 /* master register */
 47 #define MST_CLK_RST     0x0210
 48 #define MST_SOFT_RST    0x0214
 49 #define MST_FIFO_SZ     0x0218
 50 
 51 /* core register (depend on FSI version) */
 52 #define A_MST_CTLR      0x0180
 53 #define B_MST_CTLR      0x01A0
 54 #define CPU_INT_ST      0x01F4
 55 #define CPU_IEMSK       0x01F8
 56 #define CPU_IMSK        0x01FC
 57 #define INT_ST          0x0200
 58 #define IEMSK           0x0204
 59 #define IMSK            0x0208
 60 
 61 /* DO_FMT */
 62 /* DI_FMT */
 63 #define CR_BWS_MASK     (0x3 << 20) /* FSI2 */
 64 #define CR_BWS_24       (0x0 << 20) /* FSI2 */
 65 #define CR_BWS_16       (0x1 << 20) /* FSI2 */
 66 #define CR_BWS_20       (0x2 << 20) /* FSI2 */
 67 
 68 #define CR_DTMD_PCM             (0x0 << 8) /* FSI2 */
 69 #define CR_DTMD_SPDIF_PCM       (0x1 << 8) /* FSI2 */
 70 #define CR_DTMD_SPDIF_STREAM    (0x2 << 8) /* FSI2 */
 71 
 72 #define CR_MONO         (0x0 << 4)
 73 #define CR_MONO_D       (0x1 << 4)
 74 #define CR_PCM          (0x2 << 4)
 75 #define CR_I2S          (0x3 << 4)
 76 #define CR_TDM          (0x4 << 4)
 77 #define CR_TDM_D        (0x5 << 4)
 78 
 79 /* OUT_DMAC */
 80 /* IN_DMAC */
 81 #define VDMD_MASK       (0x3 << 4)
 82 #define VDMD_FRONT      (0x0 << 4) /* Package in front */
 83 #define VDMD_BACK       (0x1 << 4) /* Package in back */
 84 #define VDMD_STREAM     (0x2 << 4) /* Stream mode(16bit * 2) */
 85 
 86 #define DMA_ON          (0x1 << 0)
 87 
 88 /* DOFF_CTL */
 89 /* DIFF_CTL */
 90 #define IRQ_HALF        0x00100000
 91 #define FIFO_CLR        0x00000001
 92 
 93 /* DOFF_ST */
 94 #define ERR_OVER        0x00000010
 95 #define ERR_UNDER       0x00000001
 96 #define ST_ERR          (ERR_OVER | ERR_UNDER)
 97 
 98 /* CKG1 */
 99 #define ACKMD_MASK      0x00007000
100 #define BPFMD_MASK      0x00000700
101 #define DIMD            (1 << 4)
102 #define DOMD            (1 << 0)
103 
104 /* A/B MST_CTLR */
105 #define BP      (1 << 4)        /* Fix the signal of Biphase output */
106 #define SE      (1 << 0)        /* Fix the master clock */
107 
108 /* CLK_RST */
109 #define CRB     (1 << 4)
110 #define CRA     (1 << 0)
111 
112 /* IO SHIFT / MACRO */
113 #define BI_SHIFT        12
114 #define BO_SHIFT        8
115 #define AI_SHIFT        4
116 #define AO_SHIFT        0
117 #define AB_IO(param, shift)     (param << shift)
118 
119 /* SOFT_RST */
120 #define PBSR            (1 << 12) /* Port B Software Reset */
121 #define PASR            (1 <<  8) /* Port A Software Reset */
122 #define IR              (1 <<  4) /* Interrupt Reset */
123 #define FSISR           (1 <<  0) /* Software Reset */
124 
125 /* OUT_SEL (FSI2) */
126 #define DMMD            (1 << 4) /* SPDIF output timing 0: Biphase only */
127                                  /*                     1: Biphase and serial */
128 
129 /* FIFO_SZ */
130 #define FIFO_SZ_MASK    0x7
131 
132 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
133 
134 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
135 
136 /*
137  * bus options
138  *
139  * 0x000000BA
140  *
141  * A : sample widtht 16bit setting
142  * B : sample widtht 24bit setting
143  */
144 
145 #define SHIFT_16DATA            0
146 #define SHIFT_24DATA            4
147 
148 #define PACKAGE_24BITBUS_BACK           0
149 #define PACKAGE_24BITBUS_FRONT          1
150 #define PACKAGE_16BITBUS_STREAM         2
151 
152 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
153 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
154 
155 /*
156  * FSI driver use below type name for variable
157  *
158  * xxx_num      : number of data
159  * xxx_pos      : position of data
160  * xxx_capa     : capacity of data
161  */
162 
163 /*
164  *      period/frame/sample image
165  *
166  * ex) PCM (2ch)
167  *
168  * period pos                                      period pos
169  *   [n]                                             [n + 1]
170  *   |<-------------------- period--------------------->|
171  * ==|============================================ ... =|==
172  *   |                                                  |
173  *   ||<-----  frame ----->|<------ frame ----->|  ...  |
174  *   |+--------------------+--------------------+- ...  |
175  *   ||[ sample ][ sample ]|[ sample ][ sample ]|  ...  |
176  *   |+--------------------+--------------------+- ...  |
177  * ==|============================================ ... =|==
178  */
179 
180 /*
181  *      FSI FIFO image
182  *
183  *      |            |
184  *      |            |
185  *      | [ sample ] |
186  *      | [ sample ] |
187  *      | [ sample ] |
188  *      | [ sample ] |
189  *              --> go to codecs
190  */
191 
192 /*
193  *      FSI clock
194  *
195  * FSIxCLK [CPG] (ick) -------> |
196  *                              |-> FSI_DIV (div)-> FSI2
197  * FSIxCK [external] (xck) ---> |
198  */
199 
200 /*
201  *              struct
202  */
203 
204 struct fsi_stream_handler;
205 struct fsi_stream {
206 
207         /*
208          * these are initialized by fsi_stream_init()
209          */
210         struct snd_pcm_substream *substream;
211         int fifo_sample_capa;   /* sample capacity of FSI FIFO */
212         int buff_sample_capa;   /* sample capacity of ALSA buffer */
213         int buff_sample_pos;    /* sample position of ALSA buffer */
214         int period_samples;     /* sample number / 1 period */
215         int period_pos;         /* current period position */
216         int sample_width;       /* sample width */
217         int uerr_num;
218         int oerr_num;
219 
220         /*
221          * bus options
222          */
223         u32 bus_option;
224 
225         /*
226          * thse are initialized by fsi_handler_init()
227          */
228         struct fsi_stream_handler *handler;
229         struct fsi_priv         *priv;
230 
231         /*
232          * these are for DMAEngine
233          */
234         struct dma_chan         *chan;
235         int                     dma_id;
236 };
237 
238 struct fsi_clk {
239         /* see [FSI clock] */
240         struct clk *own;
241         struct clk *xck;
242         struct clk *ick;
243         struct clk *div;
244         int (*set_rate)(struct device *dev,
245                         struct fsi_priv *fsi);
246 
247         unsigned long rate;
248         unsigned int count;
249 };
250 
251 struct fsi_priv {
252         void __iomem *base;
253         struct fsi_master *master;
254 
255         struct fsi_stream playback;
256         struct fsi_stream capture;
257 
258         struct fsi_clk clock;
259 
260         u32 fmt;
261 
262         int chan_num:16;
263         unsigned int clk_master:1;
264         unsigned int clk_cpg:1;
265         unsigned int spdif:1;
266         unsigned int enable_stream:1;
267         unsigned int bit_clk_inv:1;
268         unsigned int lr_clk_inv:1;
269 };
270 
271 struct fsi_stream_handler {
272         int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
273         int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
274         int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
275         int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
276         int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
277         int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
278                            int enable);
279 };
280 #define fsi_stream_handler_call(io, func, args...)      \
281         (!(io) ? -ENODEV :                              \
282          !((io)->handler->func) ? 0 :                   \
283          (io)->handler->func(args))
284 
285 struct fsi_core {
286         int ver;
287 
288         u32 int_st;
289         u32 iemsk;
290         u32 imsk;
291         u32 a_mclk;
292         u32 b_mclk;
293 };
294 
295 struct fsi_master {
296         void __iomem *base;
297         struct fsi_priv fsia;
298         struct fsi_priv fsib;
299         const struct fsi_core *core;
300         spinlock_t lock;
301 };
302 
303 static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io);
304 
305 /*
306  *              basic read write function
307  */
308 
309 static void __fsi_reg_write(u32 __iomem *reg, u32 data)
310 {
311         /* valid data area is 24bit */
312         data &= 0x00ffffff;
313 
314         __raw_writel(data, reg);
315 }
316 
317 static u32 __fsi_reg_read(u32 __iomem *reg)
318 {
319         return __raw_readl(reg);
320 }
321 
322 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
323 {
324         u32 val = __fsi_reg_read(reg);
325 
326         val &= ~mask;
327         val |= data & mask;
328 
329         __fsi_reg_write(reg, val);
330 }
331 
332 #define fsi_reg_write(p, r, d)\
333         __fsi_reg_write((p->base + REG_##r), d)
334 
335 #define fsi_reg_read(p, r)\
336         __fsi_reg_read((p->base + REG_##r))
337 
338 #define fsi_reg_mask_set(p, r, m, d)\
339         __fsi_reg_mask_set((p->base + REG_##r), m, d)
340 
341 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
342 #define fsi_core_read(p, r)   _fsi_master_read(p, p->core->r)
343 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
344 {
345         u32 ret;
346         unsigned long flags;
347 
348         spin_lock_irqsave(&master->lock, flags);
349         ret = __fsi_reg_read(master->base + reg);
350         spin_unlock_irqrestore(&master->lock, flags);
351 
352         return ret;
353 }
354 
355 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
356 #define fsi_core_mask_set(p, r, m, d)  _fsi_master_mask_set(p, p->core->r, m, d)
357 static void _fsi_master_mask_set(struct fsi_master *master,
358                                u32 reg, u32 mask, u32 data)
359 {
360         unsigned long flags;
361 
362         spin_lock_irqsave(&master->lock, flags);
363         __fsi_reg_mask_set(master->base + reg, mask, data);
364         spin_unlock_irqrestore(&master->lock, flags);
365 }
366 
367 /*
368  *              basic function
369  */
370 static int fsi_version(struct fsi_master *master)
371 {
372         return master->core->ver;
373 }
374 
375 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
376 {
377         return fsi->master;
378 }
379 
380 static int fsi_is_clk_master(struct fsi_priv *fsi)
381 {
382         return fsi->clk_master;
383 }
384 
385 static int fsi_is_port_a(struct fsi_priv *fsi)
386 {
387         return fsi->master->base == fsi->base;
388 }
389 
390 static int fsi_is_spdif(struct fsi_priv *fsi)
391 {
392         return fsi->spdif;
393 }
394 
395 static int fsi_is_enable_stream(struct fsi_priv *fsi)
396 {
397         return fsi->enable_stream;
398 }
399 
400 static int fsi_is_play(struct snd_pcm_substream *substream)
401 {
402         return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
403 }
404 
405 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
406 {
407         struct snd_soc_pcm_runtime *rtd = substream->private_data;
408 
409         return  rtd->cpu_dai;
410 }
411 
412 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
413 {
414         struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
415 
416         if (dai->id == 0)
417                 return &master->fsia;
418         else
419                 return &master->fsib;
420 }
421 
422 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
423 {
424         return fsi_get_priv_frm_dai(fsi_get_dai(substream));
425 }
426 
427 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
428 {
429         int is_play = fsi_stream_is_play(fsi, io);
430         int is_porta = fsi_is_port_a(fsi);
431         u32 shift;
432 
433         if (is_porta)
434                 shift = is_play ? AO_SHIFT : AI_SHIFT;
435         else
436                 shift = is_play ? BO_SHIFT : BI_SHIFT;
437 
438         return shift;
439 }
440 
441 static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
442 {
443         return frames * fsi->chan_num;
444 }
445 
446 static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
447 {
448         return samples / fsi->chan_num;
449 }
450 
451 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
452                                         struct fsi_stream *io)
453 {
454         int is_play = fsi_stream_is_play(fsi, io);
455         u32 status;
456         int frames;
457 
458         status = is_play ?
459                 fsi_reg_read(fsi, DOFF_ST) :
460                 fsi_reg_read(fsi, DIFF_ST);
461 
462         frames = 0x1ff & (status >> 8);
463 
464         return fsi_frame2sample(fsi, frames);
465 }
466 
467 static void fsi_count_fifo_err(struct fsi_priv *fsi)
468 {
469         u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
470         u32 istatus = fsi_reg_read(fsi, DIFF_ST);
471 
472         if (ostatus & ERR_OVER)
473                 fsi->playback.oerr_num++;
474 
475         if (ostatus & ERR_UNDER)
476                 fsi->playback.uerr_num++;
477 
478         if (istatus & ERR_OVER)
479                 fsi->capture.oerr_num++;
480 
481         if (istatus & ERR_UNDER)
482                 fsi->capture.uerr_num++;
483 
484         fsi_reg_write(fsi, DOFF_ST, 0);
485         fsi_reg_write(fsi, DIFF_ST, 0);
486 }
487 
488 /*
489  *              fsi_stream_xx() function
490  */
491 static inline int fsi_stream_is_play(struct fsi_priv *fsi,
492                                      struct fsi_stream *io)
493 {
494         return &fsi->playback == io;
495 }
496 
497 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
498                                         struct snd_pcm_substream *substream)
499 {
500         return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
501 }
502 
503 static int fsi_stream_is_working(struct fsi_priv *fsi,
504                                  struct fsi_stream *io)
505 {
506         struct fsi_master *master = fsi_get_master(fsi);
507         unsigned long flags;
508         int ret;
509 
510         spin_lock_irqsave(&master->lock, flags);
511         ret = !!(io->substream && io->substream->runtime);
512         spin_unlock_irqrestore(&master->lock, flags);
513 
514         return ret;
515 }
516 
517 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
518 {
519         return io->priv;
520 }
521 
522 static void fsi_stream_init(struct fsi_priv *fsi,
523                             struct fsi_stream *io,
524                             struct snd_pcm_substream *substream)
525 {
526         struct snd_pcm_runtime *runtime = substream->runtime;
527         struct fsi_master *master = fsi_get_master(fsi);
528         unsigned long flags;
529 
530         spin_lock_irqsave(&master->lock, flags);
531         io->substream   = substream;
532         io->buff_sample_capa    = fsi_frame2sample(fsi, runtime->buffer_size);
533         io->buff_sample_pos     = 0;
534         io->period_samples      = fsi_frame2sample(fsi, runtime->period_size);
535         io->period_pos          = 0;
536         io->sample_width        = samples_to_bytes(runtime, 1);
537         io->bus_option          = 0;
538         io->oerr_num    = -1; /* ignore 1st err */
539         io->uerr_num    = -1; /* ignore 1st err */
540         fsi_stream_handler_call(io, init, fsi, io);
541         spin_unlock_irqrestore(&master->lock, flags);
542 }
543 
544 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
545 {
546         struct snd_soc_dai *dai = fsi_get_dai(io->substream);
547         struct fsi_master *master = fsi_get_master(fsi);
548         unsigned long flags;
549 
550         spin_lock_irqsave(&master->lock, flags);
551 
552         if (io->oerr_num > 0)
553                 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
554 
555         if (io->uerr_num > 0)
556                 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
557 
558         fsi_stream_handler_call(io, quit, fsi, io);
559         io->substream   = NULL;
560         io->buff_sample_capa    = 0;
561         io->buff_sample_pos     = 0;
562         io->period_samples      = 0;
563         io->period_pos          = 0;
564         io->sample_width        = 0;
565         io->bus_option          = 0;
566         io->oerr_num    = 0;
567         io->uerr_num    = 0;
568         spin_unlock_irqrestore(&master->lock, flags);
569 }
570 
571 static int fsi_stream_transfer(struct fsi_stream *io)
572 {
573         struct fsi_priv *fsi = fsi_stream_to_priv(io);
574         if (!fsi)
575                 return -EIO;
576 
577         return fsi_stream_handler_call(io, transfer, fsi, io);
578 }
579 
580 #define fsi_stream_start(fsi, io)\
581         fsi_stream_handler_call(io, start_stop, fsi, io, 1)
582 
583 #define fsi_stream_stop(fsi, io)\
584         fsi_stream_handler_call(io, start_stop, fsi, io, 0)
585 
586 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
587 {
588         struct fsi_stream *io;
589         int ret1, ret2;
590 
591         io = &fsi->playback;
592         ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
593 
594         io = &fsi->capture;
595         ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
596 
597         if (ret1 < 0)
598                 return ret1;
599         if (ret2 < 0)
600                 return ret2;
601 
602         return 0;
603 }
604 
605 static int fsi_stream_remove(struct fsi_priv *fsi)
606 {
607         struct fsi_stream *io;
608         int ret1, ret2;
609 
610         io = &fsi->playback;
611         ret1 = fsi_stream_handler_call(io, remove, fsi, io);
612 
613         io = &fsi->capture;
614         ret2 = fsi_stream_handler_call(io, remove, fsi, io);
615 
616         if (ret1 < 0)
617                 return ret1;
618         if (ret2 < 0)
619                 return ret2;
620 
621         return 0;
622 }
623 
624 /*
625  *      format/bus/dma setting
626  */
627 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
628                                  u32 bus, struct device *dev)
629 {
630         struct fsi_master *master = fsi_get_master(fsi);
631         int is_play = fsi_stream_is_play(fsi, io);
632         u32 fmt = fsi->fmt;
633 
634         if (fsi_version(master) >= 2) {
635                 u32 dma = 0;
636 
637                 /*
638                  * FSI2 needs DMA/Bus setting
639                  */
640                 switch (bus) {
641                 case PACKAGE_24BITBUS_FRONT:
642                         fmt |= CR_BWS_24;
643                         dma |= VDMD_FRONT;
644                         dev_dbg(dev, "24bit bus / package in front\n");
645                         break;
646                 case PACKAGE_16BITBUS_STREAM:
647                         fmt |= CR_BWS_16;
648                         dma |= VDMD_STREAM;
649                         dev_dbg(dev, "16bit bus / stream mode\n");
650                         break;
651                 case PACKAGE_24BITBUS_BACK:
652                 default:
653                         fmt |= CR_BWS_24;
654                         dma |= VDMD_BACK;
655                         dev_dbg(dev, "24bit bus / package in back\n");
656                         break;
657                 }
658 
659                 if (is_play)
660                         fsi_reg_write(fsi, OUT_DMAC,    dma);
661                 else
662                         fsi_reg_write(fsi, IN_DMAC,     dma);
663         }
664 
665         if (is_play)
666                 fsi_reg_write(fsi, DO_FMT, fmt);
667         else
668                 fsi_reg_write(fsi, DI_FMT, fmt);
669 }
670 
671 /*
672  *              irq function
673  */
674 
675 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
676 {
677         u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
678         struct fsi_master *master = fsi_get_master(fsi);
679 
680         fsi_core_mask_set(master, imsk,  data, data);
681         fsi_core_mask_set(master, iemsk, data, data);
682 }
683 
684 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
685 {
686         u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
687         struct fsi_master *master = fsi_get_master(fsi);
688 
689         fsi_core_mask_set(master, imsk,  data, 0);
690         fsi_core_mask_set(master, iemsk, data, 0);
691 }
692 
693 static u32 fsi_irq_get_status(struct fsi_master *master)
694 {
695         return fsi_core_read(master, int_st);
696 }
697 
698 static void fsi_irq_clear_status(struct fsi_priv *fsi)
699 {
700         u32 data = 0;
701         struct fsi_master *master = fsi_get_master(fsi);
702 
703         data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
704         data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
705 
706         /* clear interrupt factor */
707         fsi_core_mask_set(master, int_st, data, 0);
708 }
709 
710 /*
711  *              SPDIF master clock function
712  *
713  * These functions are used later FSI2
714  */
715 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
716 {
717         struct fsi_master *master = fsi_get_master(fsi);
718         u32 mask, val;
719 
720         mask = BP | SE;
721         val = enable ? mask : 0;
722 
723         fsi_is_port_a(fsi) ?
724                 fsi_core_mask_set(master, a_mclk, mask, val) :
725                 fsi_core_mask_set(master, b_mclk, mask, val);
726 }
727 
728 /*
729  *              clock function
730  */
731 static int fsi_clk_init(struct device *dev,
732                         struct fsi_priv *fsi,
733                         int xck,
734                         int ick,
735                         int div,
736                         int (*set_rate)(struct device *dev,
737                                         struct fsi_priv *fsi))
738 {
739         struct fsi_clk *clock = &fsi->clock;
740         int is_porta = fsi_is_port_a(fsi);
741 
742         clock->xck      = NULL;
743         clock->ick      = NULL;
744         clock->div      = NULL;
745         clock->rate     = 0;
746         clock->count    = 0;
747         clock->set_rate = set_rate;
748 
749         clock->own = devm_clk_get(dev, NULL);
750         if (IS_ERR(clock->own))
751                 return -EINVAL;
752 
753         /* external clock */
754         if (xck) {
755                 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
756                 if (IS_ERR(clock->xck)) {
757                         dev_err(dev, "can't get xck clock\n");
758                         return -EINVAL;
759                 }
760                 if (clock->xck == clock->own) {
761                         dev_err(dev, "cpu doesn't support xck clock\n");
762                         return -EINVAL;
763                 }
764         }
765 
766         /* FSIACLK/FSIBCLK */
767         if (ick) {
768                 clock->ick = devm_clk_get(dev,  is_porta ? "icka" : "ickb");
769                 if (IS_ERR(clock->ick)) {
770                         dev_err(dev, "can't get ick clock\n");
771                         return -EINVAL;
772                 }
773                 if (clock->ick == clock->own) {
774                         dev_err(dev, "cpu doesn't support ick clock\n");
775                         return -EINVAL;
776                 }
777         }
778 
779         /* FSI-DIV */
780         if (div) {
781                 clock->div = devm_clk_get(dev,  is_porta ? "diva" : "divb");
782                 if (IS_ERR(clock->div)) {
783                         dev_err(dev, "can't get div clock\n");
784                         return -EINVAL;
785                 }
786                 if (clock->div == clock->own) {
787                         dev_err(dev, "cpu doens't support div clock\n");
788                         return -EINVAL;
789                 }
790         }
791 
792         return 0;
793 }
794 
795 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
796 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
797 {
798         fsi->clock.rate = rate;
799 }
800 
801 static int fsi_clk_is_valid(struct fsi_priv *fsi)
802 {
803         return  fsi->clock.set_rate &&
804                 fsi->clock.rate;
805 }
806 
807 static int fsi_clk_enable(struct device *dev,
808                           struct fsi_priv *fsi)
809 {
810         struct fsi_clk *clock = &fsi->clock;
811         int ret = -EINVAL;
812 
813         if (!fsi_clk_is_valid(fsi))
814                 return ret;
815 
816         if (0 == clock->count) {
817                 ret = clock->set_rate(dev, fsi);
818                 if (ret < 0) {
819                         fsi_clk_invalid(fsi);
820                         return ret;
821                 }
822 
823                 clk_enable(clock->xck);
824                 clk_enable(clock->ick);
825                 clk_enable(clock->div);
826 
827                 clock->count++;
828         }
829 
830         return ret;
831 }
832 
833 static int fsi_clk_disable(struct device *dev,
834                             struct fsi_priv *fsi)
835 {
836         struct fsi_clk *clock = &fsi->clock;
837 
838         if (!fsi_clk_is_valid(fsi))
839                 return -EINVAL;
840 
841         if (1 == clock->count--) {
842                 clk_disable(clock->xck);
843                 clk_disable(clock->ick);
844                 clk_disable(clock->div);
845         }
846 
847         return 0;
848 }
849 
850 static int fsi_clk_set_ackbpf(struct device *dev,
851                               struct fsi_priv *fsi,
852                               int ackmd, int bpfmd)
853 {
854         u32 data = 0;
855 
856         /* check ackmd/bpfmd relationship */
857         if (bpfmd > ackmd) {
858                 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
859                 return -EINVAL;
860         }
861 
862         /*  ACKMD */
863         switch (ackmd) {
864         case 512:
865                 data |= (0x0 << 12);
866                 break;
867         case 256:
868                 data |= (0x1 << 12);
869                 break;
870         case 128:
871                 data |= (0x2 << 12);
872                 break;
873         case 64:
874                 data |= (0x3 << 12);
875                 break;
876         case 32:
877                 data |= (0x4 << 12);
878                 break;
879         default:
880                 dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
881                 return -EINVAL;
882         }
883 
884         /* BPFMD */
885         switch (bpfmd) {
886         case 32:
887                 data |= (0x0 << 8);
888                 break;
889         case 64:
890                 data |= (0x1 << 8);
891                 break;
892         case 128:
893                 data |= (0x2 << 8);
894                 break;
895         case 256:
896                 data |= (0x3 << 8);
897                 break;
898         case 512:
899                 data |= (0x4 << 8);
900                 break;
901         case 16:
902                 data |= (0x7 << 8);
903                 break;
904         default:
905                 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
906                 return -EINVAL;
907         }
908 
909         dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
910 
911         fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
912         udelay(10);
913 
914         return 0;
915 }
916 
917 static int fsi_clk_set_rate_external(struct device *dev,
918                                      struct fsi_priv *fsi)
919 {
920         struct clk *xck = fsi->clock.xck;
921         struct clk *ick = fsi->clock.ick;
922         unsigned long rate = fsi->clock.rate;
923         unsigned long xrate;
924         int ackmd, bpfmd;
925         int ret = 0;
926 
927         /* check clock rate */
928         xrate = clk_get_rate(xck);
929         if (xrate % rate) {
930                 dev_err(dev, "unsupported clock rate\n");
931                 return -EINVAL;
932         }
933 
934         clk_set_parent(ick, xck);
935         clk_set_rate(ick, xrate);
936 
937         bpfmd = fsi->chan_num * 32;
938         ackmd = xrate / rate;
939 
940         dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
941 
942         ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
943         if (ret < 0)
944                 dev_err(dev, "%s failed", __func__);
945 
946         return ret;
947 }
948 
949 static int fsi_clk_set_rate_cpg(struct device *dev,
950                                 struct fsi_priv *fsi)
951 {
952         struct clk *ick = fsi->clock.ick;
953         struct clk *div = fsi->clock.div;
954         unsigned long rate = fsi->clock.rate;
955         unsigned long target = 0; /* 12288000 or 11289600 */
956         unsigned long actual, cout;
957         unsigned long diff, min;
958         unsigned long best_cout, best_act;
959         int adj;
960         int ackmd, bpfmd;
961         int ret = -EINVAL;
962 
963         if (!(12288000 % rate))
964                 target = 12288000;
965         if (!(11289600 % rate))
966                 target = 11289600;
967         if (!target) {
968                 dev_err(dev, "unsupported rate\n");
969                 return ret;
970         }
971 
972         bpfmd = fsi->chan_num * 32;
973         ackmd = target / rate;
974         ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
975         if (ret < 0) {
976                 dev_err(dev, "%s failed", __func__);
977                 return ret;
978         }
979 
980         /*
981          * The clock flow is
982          *
983          * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
984          *
985          * But, it needs to find best match of CPG and FSI_DIV
986          * combination, since it is difficult to generate correct
987          * frequency of audio clock from ick clock only.
988          * Because ick is created from its parent clock.
989          *
990          * target       = rate x [512/256/128/64]fs
991          * cout         = round(target x adjustment)
992          * actual       = cout / adjustment (by FSI-DIV) ~= target
993          * audio        = actual
994          */
995         min = ~0;
996         best_cout = 0;
997         best_act = 0;
998         for (adj = 1; adj < 0xffff; adj++) {
999 
1000                 cout = target * adj;
1001                 if (cout > 100000000) /* max clock = 100MHz */
1002                         break;
1003 
1004                 /* cout/actual audio clock */
1005                 cout    = clk_round_rate(ick, cout);
1006                 actual  = cout / adj;
1007 
1008                 /* find best frequency */
1009                 diff = abs(actual - target);
1010                 if (diff < min) {
1011                         min             = diff;
1012                         best_cout       = cout;
1013                         best_act        = actual;
1014                 }
1015         }
1016 
1017         ret = clk_set_rate(ick, best_cout);
1018         if (ret < 0) {
1019                 dev_err(dev, "ick clock failed\n");
1020                 return -EIO;
1021         }
1022 
1023         ret = clk_set_rate(div, clk_round_rate(div, best_act));
1024         if (ret < 0) {
1025                 dev_err(dev, "div clock failed\n");
1026                 return -EIO;
1027         }
1028 
1029         dev_dbg(dev, "ick/div = %ld/%ld\n",
1030                 clk_get_rate(ick), clk_get_rate(div));
1031 
1032         return ret;
1033 }
1034 
1035 static void fsi_pointer_update(struct fsi_stream *io, int size)
1036 {
1037         io->buff_sample_pos += size;
1038 
1039         if (io->buff_sample_pos >=
1040             io->period_samples * (io->period_pos + 1)) {
1041                 struct snd_pcm_substream *substream = io->substream;
1042                 struct snd_pcm_runtime *runtime = substream->runtime;
1043 
1044                 io->period_pos++;
1045 
1046                 if (io->period_pos >= runtime->periods) {
1047                         io->buff_sample_pos = 0;
1048                         io->period_pos = 0;
1049                 }
1050 
1051                 snd_pcm_period_elapsed(substream);
1052         }
1053 }
1054 
1055 /*
1056  *              pio data transfer handler
1057  */
1058 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
1059 {
1060         int i;
1061 
1062         if (fsi_is_enable_stream(fsi)) {
1063                 /*
1064                  * stream mode
1065                  * see
1066                  *      fsi_pio_push_init()
1067                  */
1068                 u32 *buf = (u32 *)_buf;
1069 
1070                 for (i = 0; i < samples / 2; i++)
1071                         fsi_reg_write(fsi, DODT, buf[i]);
1072         } else {
1073                 /* normal mode */
1074                 u16 *buf = (u16 *)_buf;
1075 
1076                 for (i = 0; i < samples; i++)
1077                         fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
1078         }
1079 }
1080 
1081 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
1082 {
1083         u16 *buf = (u16 *)_buf;
1084         int i;
1085 
1086         for (i = 0; i < samples; i++)
1087                 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
1088 }
1089 
1090 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
1091 {
1092         u32 *buf = (u32 *)_buf;
1093         int i;
1094 
1095         for (i = 0; i < samples; i++)
1096                 fsi_reg_write(fsi, DODT, *(buf + i));
1097 }
1098 
1099 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
1100 {
1101         u32 *buf = (u32 *)_buf;
1102         int i;
1103 
1104         for (i = 0; i < samples; i++)
1105                 *(buf + i) = fsi_reg_read(fsi, DIDT);
1106 }
1107 
1108 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
1109 {
1110         struct snd_pcm_runtime *runtime = io->substream->runtime;
1111 
1112         return runtime->dma_area +
1113                 samples_to_bytes(runtime, io->buff_sample_pos);
1114 }
1115 
1116 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
1117                 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
1118                 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
1119                 int samples)
1120 {
1121         u8 *buf;
1122 
1123         if (!fsi_stream_is_working(fsi, io))
1124                 return -EINVAL;
1125 
1126         buf = fsi_pio_get_area(fsi, io);
1127 
1128         switch (io->sample_width) {
1129         case 2:
1130                 run16(fsi, buf, samples);
1131                 break;
1132         case 4:
1133                 run32(fsi, buf, samples);
1134                 break;
1135         default:
1136                 return -EINVAL;
1137         }
1138 
1139         fsi_pointer_update(io, samples);
1140 
1141         return 0;
1142 }
1143 
1144 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
1145 {
1146         int sample_residues;    /* samples in FSI fifo */
1147         int sample_space;       /* ALSA free samples space */
1148         int samples;
1149 
1150         sample_residues = fsi_get_current_fifo_samples(fsi, io);
1151         sample_space    = io->buff_sample_capa - io->buff_sample_pos;
1152 
1153         samples = min(sample_residues, sample_space);
1154 
1155         return fsi_pio_transfer(fsi, io,
1156                                   fsi_pio_pop16,
1157                                   fsi_pio_pop32,
1158                                   samples);
1159 }
1160 
1161 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
1162 {
1163         int sample_residues;    /* ALSA residue samples */
1164         int sample_space;       /* FSI fifo free samples space */
1165         int samples;
1166 
1167         sample_residues = io->buff_sample_capa - io->buff_sample_pos;
1168         sample_space    = io->fifo_sample_capa -
1169                 fsi_get_current_fifo_samples(fsi, io);
1170 
1171         samples = min(sample_residues, sample_space);
1172 
1173         return fsi_pio_transfer(fsi, io,
1174                                   fsi_pio_push16,
1175                                   fsi_pio_push32,
1176                                   samples);
1177 }
1178 
1179 static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1180                                int enable)
1181 {
1182         struct fsi_master *master = fsi_get_master(fsi);
1183         u32 clk  = fsi_is_port_a(fsi) ? CRA  : CRB;
1184 
1185         if (enable)
1186                 fsi_irq_enable(fsi, io);
1187         else
1188                 fsi_irq_disable(fsi, io);
1189 
1190         if (fsi_is_clk_master(fsi))
1191                 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1192 
1193         return 0;
1194 }
1195 
1196 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
1197 {
1198         /*
1199          * we can use 16bit stream mode
1200          * when "playback" and "16bit data"
1201          * and platform allows "stream mode"
1202          * see
1203          *      fsi_pio_push16()
1204          */
1205         if (fsi_is_enable_stream(fsi))
1206                 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1207                                  BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1208         else
1209                 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1210                                  BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1211         return 0;
1212 }
1213 
1214 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
1215 {
1216         /*
1217          * always 24bit bus, package back when "capture"
1218          */
1219         io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1220                          BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1221         return 0;
1222 }
1223 
1224 static struct fsi_stream_handler fsi_pio_push_handler = {
1225         .init           = fsi_pio_push_init,
1226         .transfer       = fsi_pio_push,
1227         .start_stop     = fsi_pio_start_stop,
1228 };
1229 
1230 static struct fsi_stream_handler fsi_pio_pop_handler = {
1231         .init           = fsi_pio_pop_init,
1232         .transfer       = fsi_pio_pop,
1233         .start_stop     = fsi_pio_start_stop,
1234 };
1235 
1236 static irqreturn_t fsi_interrupt(int irq, void *data)
1237 {
1238         struct fsi_master *master = data;
1239         u32 int_st = fsi_irq_get_status(master);
1240 
1241         /* clear irq status */
1242         fsi_master_mask_set(master, SOFT_RST, IR, 0);
1243         fsi_master_mask_set(master, SOFT_RST, IR, IR);
1244 
1245         if (int_st & AB_IO(1, AO_SHIFT))
1246                 fsi_stream_transfer(&master->fsia.playback);
1247         if (int_st & AB_IO(1, BO_SHIFT))
1248                 fsi_stream_transfer(&master->fsib.playback);
1249         if (int_st & AB_IO(1, AI_SHIFT))
1250                 fsi_stream_transfer(&master->fsia.capture);
1251         if (int_st & AB_IO(1, BI_SHIFT))
1252                 fsi_stream_transfer(&master->fsib.capture);
1253 
1254         fsi_count_fifo_err(&master->fsia);
1255         fsi_count_fifo_err(&master->fsib);
1256 
1257         fsi_irq_clear_status(&master->fsia);
1258         fsi_irq_clear_status(&master->fsib);
1259 
1260         return IRQ_HANDLED;
1261 }
1262 
1263 /*
1264  *              dma data transfer handler
1265  */
1266 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
1267 {
1268         /*
1269          * 24bit data : 24bit bus / package in back
1270          * 16bit data : 16bit bus / stream mode
1271          */
1272         io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1273                          BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1274 
1275         return 0;
1276 }
1277 
1278 static void fsi_dma_complete(void *data)
1279 {
1280         struct fsi_stream *io = (struct fsi_stream *)data;
1281         struct fsi_priv *fsi = fsi_stream_to_priv(io);
1282 
1283         fsi_pointer_update(io, io->period_samples);
1284 
1285         fsi_count_fifo_err(fsi);
1286 }
1287 
1288 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
1289 {
1290         struct snd_soc_dai *dai = fsi_get_dai(io->substream);
1291         struct snd_pcm_substream *substream = io->substream;
1292         struct dma_async_tx_descriptor *desc;
1293         int is_play = fsi_stream_is_play(fsi, io);
1294         enum dma_transfer_direction dir;
1295         int ret = -EIO;
1296 
1297         if (is_play)
1298                 dir = DMA_MEM_TO_DEV;
1299         else
1300                 dir = DMA_DEV_TO_MEM;
1301 
1302         desc = dmaengine_prep_dma_cyclic(io->chan,
1303                                          substream->runtime->dma_addr,
1304                                          snd_pcm_lib_buffer_bytes(substream),
1305                                          snd_pcm_lib_period_bytes(substream),
1306                                          dir,
1307                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1308         if (!desc) {
1309                 dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n");
1310                 goto fsi_dma_transfer_err;
1311         }
1312 
1313         desc->callback          = fsi_dma_complete;
1314         desc->callback_param    = io;
1315 
1316         if (dmaengine_submit(desc) < 0) {
1317                 dev_err(dai->dev, "tx_submit() fail\n");
1318                 goto fsi_dma_transfer_err;
1319         }
1320 
1321         dma_async_issue_pending(io->chan);
1322 
1323         /*
1324          * FIXME
1325          *
1326          * In DMAEngine case, codec and FSI cannot be started simultaneously
1327          * since FSI is using the scheduler work queue.
1328          * Therefore, in capture case, probably FSI FIFO will have got
1329          * overflow error in this point.
1330          * in that case, DMA cannot start transfer until error was cleared.
1331          */
1332         if (!is_play) {
1333                 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
1334                         fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1335                         fsi_reg_write(fsi, DIFF_ST, 0);
1336                 }
1337         }
1338 
1339         ret = 0;
1340 
1341 fsi_dma_transfer_err:
1342         return ret;
1343 }
1344 
1345 static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1346                                  int start)
1347 {
1348         struct fsi_master *master = fsi_get_master(fsi);
1349         u32 clk  = fsi_is_port_a(fsi) ? CRA  : CRB;
1350         u32 enable = start ? DMA_ON : 0;
1351 
1352         fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
1353 
1354         dmaengine_terminate_all(io->chan);
1355 
1356         if (fsi_is_clk_master(fsi))
1357                 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1358 
1359         return 0;
1360 }
1361 
1362 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
1363 {
1364         dma_cap_mask_t mask;
1365         int is_play = fsi_stream_is_play(fsi, io);
1366 
1367         dma_cap_zero(mask);
1368         dma_cap_set(DMA_SLAVE, mask);
1369 
1370         io->chan = dma_request_slave_channel_compat(mask,
1371                                 shdma_chan_filter, (void *)io->dma_id,
1372                                 dev, is_play ? "tx" : "rx");
1373         if (io->chan) {
1374                 struct dma_slave_config cfg;
1375                 int ret;
1376 
1377                 cfg.slave_id    = io->dma_id;
1378                 cfg.dst_addr    = 0; /* use default addr */
1379                 cfg.src_addr    = 0; /* use default addr */
1380                 cfg.direction   = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1381 
1382                 ret = dmaengine_slave_config(io->chan, &cfg);
1383                 if (ret < 0) {
1384                         dma_release_channel(io->chan);
1385                         io->chan = NULL;
1386                 }
1387         }
1388 
1389         if (!io->chan) {
1390 
1391                 /* switch to PIO handler */
1392                 if (is_play)
1393                         fsi->playback.handler   = &fsi_pio_push_handler;
1394                 else
1395                         fsi->capture.handler    = &fsi_pio_pop_handler;
1396 
1397                 dev_info(dev, "switch handler (dma => pio)\n");
1398 
1399                 /* probe again */
1400                 return fsi_stream_probe(fsi, dev);
1401         }
1402 
1403         return 0;
1404 }
1405 
1406 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
1407 {
1408         fsi_stream_stop(fsi, io);
1409 
1410         if (io->chan)
1411                 dma_release_channel(io->chan);
1412 
1413         io->chan = NULL;
1414         return 0;
1415 }
1416 
1417 static struct fsi_stream_handler fsi_dma_push_handler = {
1418         .init           = fsi_dma_init,
1419         .probe          = fsi_dma_probe,
1420         .transfer       = fsi_dma_transfer,
1421         .remove         = fsi_dma_remove,
1422         .start_stop     = fsi_dma_push_start_stop,
1423 };
1424 
1425 /*
1426  *              dai ops
1427  */
1428 static void fsi_fifo_init(struct fsi_priv *fsi,
1429                           struct fsi_stream *io,
1430                           struct device *dev)
1431 {
1432         struct fsi_master *master = fsi_get_master(fsi);
1433         int is_play = fsi_stream_is_play(fsi, io);
1434         u32 shift, i;
1435         int frame_capa;
1436 
1437         /* get on-chip RAM capacity */
1438         shift = fsi_master_read(master, FIFO_SZ);
1439         shift >>= fsi_get_port_shift(fsi, io);
1440         shift &= FIFO_SZ_MASK;
1441         frame_capa = 256 << shift;
1442         dev_dbg(dev, "fifo = %d words\n", frame_capa);
1443 
1444         /*
1445          * The maximum number of sample data varies depending
1446          * on the number of channels selected for the format.
1447          *
1448          * FIFOs are used in 4-channel units in 3-channel mode
1449          * and in 8-channel units in 5- to 7-channel mode
1450          * meaning that more FIFOs than the required size of DPRAM
1451          * are used.
1452          *
1453          * ex) if 256 words of DP-RAM is connected
1454          * 1 channel:  256 (256 x 1 = 256)
1455          * 2 channels: 128 (128 x 2 = 256)
1456          * 3 channels:  64 ( 64 x 3 = 192)
1457          * 4 channels:  64 ( 64 x 4 = 256)
1458          * 5 channels:  32 ( 32 x 5 = 160)
1459          * 6 channels:  32 ( 32 x 6 = 192)
1460          * 7 channels:  32 ( 32 x 7 = 224)
1461          * 8 channels:  32 ( 32 x 8 = 256)
1462          */
1463         for (i = 1; i < fsi->chan_num; i <<= 1)
1464                 frame_capa >>= 1;
1465         dev_dbg(dev, "%d channel %d store\n",
1466                 fsi->chan_num, frame_capa);
1467 
1468         io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
1469 
1470         /*
1471          * set interrupt generation factor
1472          * clear FIFO
1473          */
1474         if (is_play) {
1475                 fsi_reg_write(fsi,      DOFF_CTL, IRQ_HALF);
1476                 fsi_reg_mask_set(fsi,   DOFF_CTL, FIFO_CLR, FIFO_CLR);
1477         } else {
1478                 fsi_reg_write(fsi,      DIFF_CTL, IRQ_HALF);
1479                 fsi_reg_mask_set(fsi,   DIFF_CTL, FIFO_CLR, FIFO_CLR);
1480         }
1481 }
1482 
1483 static int fsi_hw_startup(struct fsi_priv *fsi,
1484                           struct fsi_stream *io,
1485                           struct device *dev)
1486 {
1487         u32 data = 0;
1488 
1489         /* clock setting */
1490         if (fsi_is_clk_master(fsi))
1491                 data = DIMD | DOMD;
1492 
1493         fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
1494 
1495         /* clock inversion (CKG2) */
1496         data = 0;
1497         if (fsi->bit_clk_inv)
1498                 data |= (1 << 0);
1499         if (fsi->lr_clk_inv)
1500                 data |= (1 << 4);
1501         if (fsi_is_clk_master(fsi))
1502                 data <<= 8;
1503         fsi_reg_write(fsi, CKG2, data);
1504 
1505         /* spdif ? */
1506         if (fsi_is_spdif(fsi)) {
1507                 fsi_spdif_clk_ctrl(fsi, 1);
1508                 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
1509         }
1510 
1511         /*
1512          * get bus settings
1513          */
1514         data = 0;
1515         switch (io->sample_width) {
1516         case 2:
1517                 data = BUSOP_GET(16, io->bus_option);
1518                 break;
1519         case 4:
1520                 data = BUSOP_GET(24, io->bus_option);
1521                 break;
1522         }
1523         fsi_format_bus_setup(fsi, io, data, dev);
1524 
1525         /* irq clear */
1526         fsi_irq_disable(fsi, io);
1527         fsi_irq_clear_status(fsi);
1528 
1529         /* fifo init */
1530         fsi_fifo_init(fsi, io, dev);
1531 
1532         /* start master clock */
1533         if (fsi_is_clk_master(fsi))
1534                 return fsi_clk_enable(dev, fsi);
1535 
1536         return 0;
1537 }
1538 
1539 static int fsi_hw_shutdown(struct fsi_priv *fsi,
1540                             struct device *dev)
1541 {
1542         /* stop master clock */
1543         if (fsi_is_clk_master(fsi))
1544                 return fsi_clk_disable(dev, fsi);
1545 
1546         return 0;
1547 }
1548 
1549 static int fsi_dai_startup(struct snd_pcm_substream *substream,
1550                            struct snd_soc_dai *dai)
1551 {
1552         struct fsi_priv *fsi = fsi_get_priv(substream);
1553 
1554         fsi_clk_invalid(fsi);
1555 
1556         return 0;
1557 }
1558 
1559 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
1560                              struct snd_soc_dai *dai)
1561 {
1562         struct fsi_priv *fsi = fsi_get_priv(substream);
1563 
1564         fsi_clk_invalid(fsi);
1565 }
1566 
1567 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
1568                            struct snd_soc_dai *dai)
1569 {
1570         struct fsi_priv *fsi = fsi_get_priv(substream);
1571         struct fsi_stream *io = fsi_stream_get(fsi, substream);
1572         int ret = 0;
1573 
1574         switch (cmd) {
1575         case SNDRV_PCM_TRIGGER_START:
1576                 fsi_stream_init(fsi, io, substream);
1577                 if (!ret)
1578                         ret = fsi_hw_startup(fsi, io, dai->dev);
1579                 if (!ret)
1580                         ret = fsi_stream_start(fsi, io);
1581                 if (!ret)
1582                         ret = fsi_stream_transfer(io);
1583                 break;
1584         case SNDRV_PCM_TRIGGER_STOP:
1585                 if (!ret)
1586                         ret = fsi_hw_shutdown(fsi, dai->dev);
1587                 fsi_stream_stop(fsi, io);
1588                 fsi_stream_quit(fsi, io);
1589                 break;
1590         }
1591 
1592         return ret;
1593 }
1594 
1595 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
1596 {
1597         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1598         case SND_SOC_DAIFMT_I2S:
1599                 fsi->fmt = CR_I2S;
1600                 fsi->chan_num = 2;
1601                 break;
1602         case SND_SOC_DAIFMT_LEFT_J:
1603                 fsi->fmt = CR_PCM;
1604                 fsi->chan_num = 2;
1605                 break;
1606         default:
1607                 return -EINVAL;
1608         }
1609 
1610         return 0;
1611 }
1612 
1613 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1614 {
1615         struct fsi_master *master = fsi_get_master(fsi);
1616 
1617         if (fsi_version(master) < 2)
1618                 return -EINVAL;
1619 
1620         fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
1621         fsi->chan_num = 2;
1622 
1623         return 0;
1624 }
1625 
1626 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1627 {
1628         struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1629         int ret;
1630 
1631         /* set master/slave audio interface */
1632         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1633         case SND_SOC_DAIFMT_CBM_CFM:
1634                 break;
1635         case SND_SOC_DAIFMT_CBS_CFS:
1636                 fsi->clk_master = 1; /* codec is slave, cpu is master */
1637                 break;
1638         default:
1639                 return -EINVAL;
1640         }
1641 
1642         /* set clock inversion */
1643         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1644         case SND_SOC_DAIFMT_NB_IF:
1645                 fsi->bit_clk_inv = 0;
1646                 fsi->lr_clk_inv = 1;
1647                 break;
1648         case SND_SOC_DAIFMT_IB_NF:
1649                 fsi->bit_clk_inv = 1;
1650                 fsi->lr_clk_inv = 0;
1651                 break;
1652         case SND_SOC_DAIFMT_IB_IF:
1653                 fsi->bit_clk_inv = 1;
1654                 fsi->lr_clk_inv = 1;
1655                 break;
1656         case SND_SOC_DAIFMT_NB_NF:
1657         default:
1658                 fsi->bit_clk_inv = 0;
1659                 fsi->lr_clk_inv = 0;
1660                 break;
1661         }
1662 
1663         if (fsi_is_clk_master(fsi)) {
1664                 if (fsi->clk_cpg)
1665                         fsi_clk_init(dai->dev, fsi, 0, 1, 1,
1666                                      fsi_clk_set_rate_cpg);
1667                 else
1668                         fsi_clk_init(dai->dev, fsi, 1, 1, 0,
1669                                      fsi_clk_set_rate_external);
1670         }
1671 
1672         /* set format */
1673         if (fsi_is_spdif(fsi))
1674                 ret = fsi_set_fmt_spdif(fsi);
1675         else
1676                 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1677 
1678         return ret;
1679 }
1680 
1681 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1682                              struct snd_pcm_hw_params *params,
1683                              struct snd_soc_dai *dai)
1684 {
1685         struct fsi_priv *fsi = fsi_get_priv(substream);
1686 
1687         if (fsi_is_clk_master(fsi))
1688                 fsi_clk_valid(fsi, params_rate(params));
1689 
1690         return 0;
1691 }
1692 
1693 static const struct snd_soc_dai_ops fsi_dai_ops = {
1694         .startup        = fsi_dai_startup,
1695         .shutdown       = fsi_dai_shutdown,
1696         .trigger        = fsi_dai_trigger,
1697         .set_fmt        = fsi_dai_set_fmt,
1698         .hw_params      = fsi_dai_hw_params,
1699 };
1700 
1701 /*
1702  *              pcm ops
1703  */
1704 
1705 static struct snd_pcm_hardware fsi_pcm_hardware = {
1706         .info =         SNDRV_PCM_INFO_INTERLEAVED      |
1707                         SNDRV_PCM_INFO_MMAP             |
1708                         SNDRV_PCM_INFO_MMAP_VALID,
1709         .buffer_bytes_max       = 64 * 1024,
1710         .period_bytes_min       = 32,
1711         .period_bytes_max       = 8192,
1712         .periods_min            = 1,
1713         .periods_max            = 32,
1714         .fifo_size              = 256,
1715 };
1716 
1717 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1718 {
1719         struct snd_pcm_runtime *runtime = substream->runtime;
1720         int ret = 0;
1721 
1722         snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1723 
1724         ret = snd_pcm_hw_constraint_integer(runtime,
1725                                             SNDRV_PCM_HW_PARAM_PERIODS);
1726 
1727         return ret;
1728 }
1729 
1730 static int fsi_hw_params(struct snd_pcm_substream *substream,
1731                          struct snd_pcm_hw_params *hw_params)
1732 {
1733         return snd_pcm_lib_malloc_pages(substream,
1734                                         params_buffer_bytes(hw_params));
1735 }
1736 
1737 static int fsi_hw_free(struct snd_pcm_substream *substream)
1738 {
1739         return snd_pcm_lib_free_pages(substream);
1740 }
1741 
1742 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1743 {
1744         struct fsi_priv *fsi = fsi_get_priv(substream);
1745         struct fsi_stream *io = fsi_stream_get(fsi, substream);
1746 
1747         return fsi_sample2frame(fsi, io->buff_sample_pos);
1748 }
1749 
1750 static struct snd_pcm_ops fsi_pcm_ops = {
1751         .open           = fsi_pcm_open,
1752         .ioctl          = snd_pcm_lib_ioctl,
1753         .hw_params      = fsi_hw_params,
1754         .hw_free        = fsi_hw_free,
1755         .pointer        = fsi_pointer,
1756 };
1757 
1758 /*
1759  *              snd_soc_platform
1760  */
1761 
1762 #define PREALLOC_BUFFER         (32 * 1024)
1763 #define PREALLOC_BUFFER_MAX     (32 * 1024)
1764 
1765 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
1766 {
1767         return snd_pcm_lib_preallocate_pages_for_all(
1768                 rtd->pcm,
1769                 SNDRV_DMA_TYPE_DEV,
1770                 rtd->card->snd_card->dev,
1771                 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1772 }
1773 
1774 /*
1775  *              alsa struct
1776  */
1777 
1778 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1779         {
1780                 .name                   = "fsia-dai",
1781                 .playback = {
1782                         .rates          = FSI_RATES,
1783                         .formats        = FSI_FMTS,
1784                         .channels_min   = 2,
1785                         .channels_max   = 2,
1786                 },
1787                 .capture = {
1788                         .rates          = FSI_RATES,
1789                         .formats        = FSI_FMTS,
1790                         .channels_min   = 2,
1791                         .channels_max   = 2,
1792                 },
1793                 .ops = &fsi_dai_ops,
1794         },
1795         {
1796                 .name                   = "fsib-dai",
1797                 .playback = {
1798                         .rates          = FSI_RATES,
1799                         .formats        = FSI_FMTS,
1800                         .channels_min   = 2,
1801                         .channels_max   = 2,
1802                 },
1803                 .capture = {
1804                         .rates          = FSI_RATES,
1805                         .formats        = FSI_FMTS,
1806                         .channels_min   = 2,
1807                         .channels_max   = 2,
1808                 },
1809                 .ops = &fsi_dai_ops,
1810         },
1811 };
1812 
1813 static struct snd_soc_platform_driver fsi_soc_platform = {
1814         .ops            = &fsi_pcm_ops,
1815         .pcm_new        = fsi_pcm_new,
1816 };
1817 
1818 static const struct snd_soc_component_driver fsi_soc_component = {
1819         .name           = "fsi",
1820 };
1821 
1822 /*
1823  *              platform function
1824  */
1825 static void fsi_of_parse(char *name,
1826                          struct device_node *np,
1827                          struct sh_fsi_port_info *info,
1828                          struct device *dev)
1829 {
1830         int i;
1831         char prop[128];
1832         unsigned long flags = 0;
1833         struct {
1834                 char *name;
1835                 unsigned int val;
1836         } of_parse_property[] = {
1837                 { "spdif-connection",           SH_FSI_FMT_SPDIF },
1838                 { "stream-mode-support",        SH_FSI_ENABLE_STREAM_MODE },
1839                 { "use-internal-clock",         SH_FSI_CLK_CPG },
1840         };
1841 
1842         for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
1843                 sprintf(prop, "%s,%s", name, of_parse_property[i].name);
1844                 if (of_get_property(np, prop, NULL))
1845                         flags |= of_parse_property[i].val;
1846         }
1847         info->flags = flags;
1848 
1849         dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
1850 }
1851 
1852 static void fsi_port_info_init(struct fsi_priv *fsi,
1853                                struct sh_fsi_port_info *info)
1854 {
1855         if (info->flags & SH_FSI_FMT_SPDIF)
1856                 fsi->spdif = 1;
1857 
1858         if (info->flags & SH_FSI_CLK_CPG)
1859                 fsi->clk_cpg = 1;
1860 
1861         if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
1862                 fsi->enable_stream = 1;
1863 }
1864 
1865 static void fsi_handler_init(struct fsi_priv *fsi,
1866                              struct sh_fsi_port_info *info)
1867 {
1868         fsi->playback.handler   = &fsi_pio_push_handler; /* default PIO */
1869         fsi->playback.priv      = fsi;
1870         fsi->capture.handler    = &fsi_pio_pop_handler;  /* default PIO */
1871         fsi->capture.priv       = fsi;
1872 
1873         if (info->tx_id) {
1874                 fsi->playback.dma_id  = info->tx_id;
1875                 fsi->playback.handler = &fsi_dma_push_handler;
1876         }
1877 }
1878 
1879 static struct of_device_id fsi_of_match[];
1880 static int fsi_probe(struct platform_device *pdev)
1881 {
1882         struct fsi_master *master;
1883         struct device_node *np = pdev->dev.of_node;
1884         struct sh_fsi_platform_info info;
1885         const struct fsi_core *core;
1886         struct fsi_priv *fsi;
1887         struct resource *res;
1888         unsigned int irq;
1889         int ret;
1890 
1891         memset(&info, 0, sizeof(info));
1892 
1893         core = NULL;
1894         if (np) {
1895                 const struct of_device_id *of_id;
1896 
1897                 of_id = of_match_device(fsi_of_match, &pdev->dev);
1898                 if (of_id) {
1899                         core = of_id->data;
1900                         fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
1901                         fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
1902                 }
1903         } else {
1904                 const struct platform_device_id *id_entry = pdev->id_entry;
1905                 if (id_entry)
1906                         core = (struct fsi_core *)id_entry->driver_data;
1907 
1908                 if (pdev->dev.platform_data)
1909                         memcpy(&info, pdev->dev.platform_data, sizeof(info));
1910         }
1911 
1912         if (!core) {
1913                 dev_err(&pdev->dev, "unknown fsi device\n");
1914                 return -ENODEV;
1915         }
1916 
1917         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1918         irq = platform_get_irq(pdev, 0);
1919         if (!res || (int)irq <= 0) {
1920                 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1921                 return -ENODEV;
1922         }
1923 
1924         master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1925         if (!master) {
1926                 dev_err(&pdev->dev, "Could not allocate master\n");
1927                 return -ENOMEM;
1928         }
1929 
1930         master->base = devm_ioremap_nocache(&pdev->dev,
1931                                             res->start, resource_size(res));
1932         if (!master->base) {
1933                 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1934                 return -ENXIO;
1935         }
1936 
1937         /* master setting */
1938         master->core            = core;
1939         spin_lock_init(&master->lock);
1940 
1941         /* FSI A setting */
1942         fsi             = &master->fsia;
1943         fsi->base       = master->base;
1944         fsi->master     = master;
1945         fsi_port_info_init(fsi, &info.port_a);
1946         fsi_handler_init(fsi, &info.port_a);
1947         ret = fsi_stream_probe(fsi, &pdev->dev);
1948         if (ret < 0) {
1949                 dev_err(&pdev->dev, "FSIA stream probe failed\n");
1950                 return ret;
1951         }
1952 
1953         /* FSI B setting */
1954         fsi             = &master->fsib;
1955         fsi->base       = master->base + 0x40;
1956         fsi->master     = master;
1957         fsi_port_info_init(fsi, &info.port_b);
1958         fsi_handler_init(fsi, &info.port_b);
1959         ret = fsi_stream_probe(fsi, &pdev->dev);
1960         if (ret < 0) {
1961                 dev_err(&pdev->dev, "FSIB stream probe failed\n");
1962                 goto exit_fsia;
1963         }
1964 
1965         pm_runtime_enable(&pdev->dev);
1966         dev_set_drvdata(&pdev->dev, master);
1967 
1968         ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
1969                                dev_name(&pdev->dev), master);
1970         if (ret) {
1971                 dev_err(&pdev->dev, "irq request err\n");
1972                 goto exit_fsib;
1973         }
1974 
1975         ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1976         if (ret < 0) {
1977                 dev_err(&pdev->dev, "cannot snd soc register\n");
1978                 goto exit_fsib;
1979         }
1980 
1981         ret = snd_soc_register_component(&pdev->dev, &fsi_soc_component,
1982                                     fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1983         if (ret < 0) {
1984                 dev_err(&pdev->dev, "cannot snd component register\n");
1985                 goto exit_snd_soc;
1986         }
1987 
1988         return ret;
1989 
1990 exit_snd_soc:
1991         snd_soc_unregister_platform(&pdev->dev);
1992 exit_fsib:
1993         pm_runtime_disable(&pdev->dev);
1994         fsi_stream_remove(&master->fsib);
1995 exit_fsia:
1996         fsi_stream_remove(&master->fsia);
1997 
1998         return ret;
1999 }
2000 
2001 static int fsi_remove(struct platform_device *pdev)
2002 {
2003         struct fsi_master *master;
2004 
2005         master = dev_get_drvdata(&pdev->dev);
2006 
2007         pm_runtime_disable(&pdev->dev);
2008 
2009         snd_soc_unregister_component(&pdev->dev);
2010         snd_soc_unregister_platform(&pdev->dev);
2011 
2012         fsi_stream_remove(&master->fsia);
2013         fsi_stream_remove(&master->fsib);
2014 
2015         return 0;
2016 }
2017 
2018 static void __fsi_suspend(struct fsi_priv *fsi,
2019                           struct fsi_stream *io,
2020                           struct device *dev)
2021 {
2022         if (!fsi_stream_is_working(fsi, io))
2023                 return;
2024 
2025         fsi_stream_stop(fsi, io);
2026         fsi_hw_shutdown(fsi, dev);
2027 }
2028 
2029 static void __fsi_resume(struct fsi_priv *fsi,
2030                          struct fsi_stream *io,
2031                          struct device *dev)
2032 {
2033         if (!fsi_stream_is_working(fsi, io))
2034                 return;
2035 
2036         fsi_hw_startup(fsi, io, dev);
2037         fsi_stream_start(fsi, io);
2038 }
2039 
2040 static int fsi_suspend(struct device *dev)
2041 {
2042         struct fsi_master *master = dev_get_drvdata(dev);
2043         struct fsi_priv *fsia = &master->fsia;
2044         struct fsi_priv *fsib = &master->fsib;
2045 
2046         __fsi_suspend(fsia, &fsia->playback, dev);
2047         __fsi_suspend(fsia, &fsia->capture, dev);
2048 
2049         __fsi_suspend(fsib, &fsib->playback, dev);
2050         __fsi_suspend(fsib, &fsib->capture, dev);
2051 
2052         return 0;
2053 }
2054 
2055 static int fsi_resume(struct device *dev)
2056 {
2057         struct fsi_master *master = dev_get_drvdata(dev);
2058         struct fsi_priv *fsia = &master->fsia;
2059         struct fsi_priv *fsib = &master->fsib;
2060 
2061         __fsi_resume(fsia, &fsia->playback, dev);
2062         __fsi_resume(fsia, &fsia->capture, dev);
2063 
2064         __fsi_resume(fsib, &fsib->playback, dev);
2065         __fsi_resume(fsib, &fsib->capture, dev);
2066 
2067         return 0;
2068 }
2069 
2070 static struct dev_pm_ops fsi_pm_ops = {
2071         .suspend                = fsi_suspend,
2072         .resume                 = fsi_resume,
2073 };
2074 
2075 static struct fsi_core fsi1_core = {
2076         .ver    = 1,
2077 
2078         /* Interrupt */
2079         .int_st = INT_ST,
2080         .iemsk  = IEMSK,
2081         .imsk   = IMSK,
2082 };
2083 
2084 static struct fsi_core fsi2_core = {
2085         .ver    = 2,
2086 
2087         /* Interrupt */
2088         .int_st = CPU_INT_ST,
2089         .iemsk  = CPU_IEMSK,
2090         .imsk   = CPU_IMSK,
2091         .a_mclk = A_MST_CTLR,
2092         .b_mclk = B_MST_CTLR,
2093 };
2094 
2095 static struct of_device_id fsi_of_match[] = {
2096         { .compatible = "renesas,sh_fsi",       .data = &fsi1_core},
2097         { .compatible = "renesas,sh_fsi2",      .data = &fsi2_core},
2098         {},
2099 };
2100 MODULE_DEVICE_TABLE(of, fsi_of_match);
2101 
2102 static struct platform_device_id fsi_id_table[] = {
2103         { "sh_fsi",     (kernel_ulong_t)&fsi1_core },
2104         { "sh_fsi2",    (kernel_ulong_t)&fsi2_core },
2105         {},
2106 };
2107 MODULE_DEVICE_TABLE(platform, fsi_id_table);
2108 
2109 static struct platform_driver fsi_driver = {
2110         .driver         = {
2111                 .name   = "fsi-pcm-audio",
2112                 .pm     = &fsi_pm_ops,
2113                 .of_match_table = fsi_of_match,
2114         },
2115         .probe          = fsi_probe,
2116         .remove         = fsi_remove,
2117         .id_table       = fsi_id_table,
2118 };
2119 
2120 module_platform_driver(fsi_driver);
2121 
2122 MODULE_LICENSE("GPL");
2123 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
2124 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
2125 MODULE_ALIAS("platform:fsi-pcm-audio");
2126 

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