Version:  2.0.40 2.2.26 2.4.37 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2

Linux/sound/soc/sh/fsi.c

  1 /*
  2  * Fifo-attached Serial Interface (FSI) support for SH7724
  3  *
  4  * Copyright (C) 2009 Renesas Solutions Corp.
  5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6  *
  7  * Based on ssi.c
  8  * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License version 2 as
 12  * published by the Free Software Foundation.
 13  */
 14 
 15 #include <linux/delay.h>
 16 #include <linux/dma-mapping.h>
 17 #include <linux/pm_runtime.h>
 18 #include <linux/io.h>
 19 #include <linux/of.h>
 20 #include <linux/of_device.h>
 21 #include <linux/scatterlist.h>
 22 #include <linux/sh_dma.h>
 23 #include <linux/slab.h>
 24 #include <linux/module.h>
 25 #include <linux/workqueue.h>
 26 #include <sound/soc.h>
 27 #include <sound/pcm_params.h>
 28 #include <sound/sh_fsi.h>
 29 
 30 /* PortA/PortB register */
 31 #define REG_DO_FMT      0x0000
 32 #define REG_DOFF_CTL    0x0004
 33 #define REG_DOFF_ST     0x0008
 34 #define REG_DI_FMT      0x000C
 35 #define REG_DIFF_CTL    0x0010
 36 #define REG_DIFF_ST     0x0014
 37 #define REG_CKG1        0x0018
 38 #define REG_CKG2        0x001C
 39 #define REG_DIDT        0x0020
 40 #define REG_DODT        0x0024
 41 #define REG_MUTE_ST     0x0028
 42 #define REG_OUT_DMAC    0x002C
 43 #define REG_OUT_SEL     0x0030
 44 #define REG_IN_DMAC     0x0038
 45 
 46 /* master register */
 47 #define MST_CLK_RST     0x0210
 48 #define MST_SOFT_RST    0x0214
 49 #define MST_FIFO_SZ     0x0218
 50 
 51 /* core register (depend on FSI version) */
 52 #define A_MST_CTLR      0x0180
 53 #define B_MST_CTLR      0x01A0
 54 #define CPU_INT_ST      0x01F4
 55 #define CPU_IEMSK       0x01F8
 56 #define CPU_IMSK        0x01FC
 57 #define INT_ST          0x0200
 58 #define IEMSK           0x0204
 59 #define IMSK            0x0208
 60 
 61 /* DO_FMT */
 62 /* DI_FMT */
 63 #define CR_BWS_MASK     (0x3 << 20) /* FSI2 */
 64 #define CR_BWS_24       (0x0 << 20) /* FSI2 */
 65 #define CR_BWS_16       (0x1 << 20) /* FSI2 */
 66 #define CR_BWS_20       (0x2 << 20) /* FSI2 */
 67 
 68 #define CR_DTMD_PCM             (0x0 << 8) /* FSI2 */
 69 #define CR_DTMD_SPDIF_PCM       (0x1 << 8) /* FSI2 */
 70 #define CR_DTMD_SPDIF_STREAM    (0x2 << 8) /* FSI2 */
 71 
 72 #define CR_MONO         (0x0 << 4)
 73 #define CR_MONO_D       (0x1 << 4)
 74 #define CR_PCM          (0x2 << 4)
 75 #define CR_I2S          (0x3 << 4)
 76 #define CR_TDM          (0x4 << 4)
 77 #define CR_TDM_D        (0x5 << 4)
 78 
 79 /* OUT_DMAC */
 80 /* IN_DMAC */
 81 #define VDMD_MASK       (0x3 << 4)
 82 #define VDMD_FRONT      (0x0 << 4) /* Package in front */
 83 #define VDMD_BACK       (0x1 << 4) /* Package in back */
 84 #define VDMD_STREAM     (0x2 << 4) /* Stream mode(16bit * 2) */
 85 
 86 #define DMA_ON          (0x1 << 0)
 87 
 88 /* DOFF_CTL */
 89 /* DIFF_CTL */
 90 #define IRQ_HALF        0x00100000
 91 #define FIFO_CLR        0x00000001
 92 
 93 /* DOFF_ST */
 94 #define ERR_OVER        0x00000010
 95 #define ERR_UNDER       0x00000001
 96 #define ST_ERR          (ERR_OVER | ERR_UNDER)
 97 
 98 /* CKG1 */
 99 #define ACKMD_MASK      0x00007000
100 #define BPFMD_MASK      0x00000700
101 #define DIMD            (1 << 4)
102 #define DOMD            (1 << 0)
103 
104 /* A/B MST_CTLR */
105 #define BP      (1 << 4)        /* Fix the signal of Biphase output */
106 #define SE      (1 << 0)        /* Fix the master clock */
107 
108 /* CLK_RST */
109 #define CRB     (1 << 4)
110 #define CRA     (1 << 0)
111 
112 /* IO SHIFT / MACRO */
113 #define BI_SHIFT        12
114 #define BO_SHIFT        8
115 #define AI_SHIFT        4
116 #define AO_SHIFT        0
117 #define AB_IO(param, shift)     (param << shift)
118 
119 /* SOFT_RST */
120 #define PBSR            (1 << 12) /* Port B Software Reset */
121 #define PASR            (1 <<  8) /* Port A Software Reset */
122 #define IR              (1 <<  4) /* Interrupt Reset */
123 #define FSISR           (1 <<  0) /* Software Reset */
124 
125 /* OUT_SEL (FSI2) */
126 #define DMMD            (1 << 4) /* SPDIF output timing 0: Biphase only */
127                                  /*                     1: Biphase and serial */
128 
129 /* FIFO_SZ */
130 #define FIFO_SZ_MASK    0x7
131 
132 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
133 
134 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
135 
136 /*
137  * bus options
138  *
139  * 0x000000BA
140  *
141  * A : sample widtht 16bit setting
142  * B : sample widtht 24bit setting
143  */
144 
145 #define SHIFT_16DATA            0
146 #define SHIFT_24DATA            4
147 
148 #define PACKAGE_24BITBUS_BACK           0
149 #define PACKAGE_24BITBUS_FRONT          1
150 #define PACKAGE_16BITBUS_STREAM         2
151 
152 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
153 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
154 
155 /*
156  * FSI driver use below type name for variable
157  *
158  * xxx_num      : number of data
159  * xxx_pos      : position of data
160  * xxx_capa     : capacity of data
161  */
162 
163 /*
164  *      period/frame/sample image
165  *
166  * ex) PCM (2ch)
167  *
168  * period pos                                      period pos
169  *   [n]                                             [n + 1]
170  *   |<-------------------- period--------------------->|
171  * ==|============================================ ... =|==
172  *   |                                                  |
173  *   ||<-----  frame ----->|<------ frame ----->|  ...  |
174  *   |+--------------------+--------------------+- ...  |
175  *   ||[ sample ][ sample ]|[ sample ][ sample ]|  ...  |
176  *   |+--------------------+--------------------+- ...  |
177  * ==|============================================ ... =|==
178  */
179 
180 /*
181  *      FSI FIFO image
182  *
183  *      |            |
184  *      |            |
185  *      | [ sample ] |
186  *      | [ sample ] |
187  *      | [ sample ] |
188  *      | [ sample ] |
189  *              --> go to codecs
190  */
191 
192 /*
193  *      FSI clock
194  *
195  * FSIxCLK [CPG] (ick) -------> |
196  *                              |-> FSI_DIV (div)-> FSI2
197  * FSIxCK [external] (xck) ---> |
198  */
199 
200 /*
201  *              struct
202  */
203 
204 struct fsi_stream_handler;
205 struct fsi_stream {
206 
207         /*
208          * these are initialized by fsi_stream_init()
209          */
210         struct snd_pcm_substream *substream;
211         int fifo_sample_capa;   /* sample capacity of FSI FIFO */
212         int buff_sample_capa;   /* sample capacity of ALSA buffer */
213         int buff_sample_pos;    /* sample position of ALSA buffer */
214         int period_samples;     /* sample number / 1 period */
215         int period_pos;         /* current period position */
216         int sample_width;       /* sample width */
217         int uerr_num;
218         int oerr_num;
219 
220         /*
221          * bus options
222          */
223         u32 bus_option;
224 
225         /*
226          * thse are initialized by fsi_handler_init()
227          */
228         struct fsi_stream_handler *handler;
229         struct fsi_priv         *priv;
230 
231         /*
232          * these are for DMAEngine
233          */
234         struct dma_chan         *chan;
235         int                     dma_id;
236 };
237 
238 struct fsi_clk {
239         /* see [FSI clock] */
240         struct clk *own;
241         struct clk *xck;
242         struct clk *ick;
243         struct clk *div;
244         int (*set_rate)(struct device *dev,
245                         struct fsi_priv *fsi);
246 
247         unsigned long rate;
248         unsigned int count;
249 };
250 
251 struct fsi_priv {
252         void __iomem *base;
253         phys_addr_t phys;
254         struct fsi_master *master;
255 
256         struct fsi_stream playback;
257         struct fsi_stream capture;
258 
259         struct fsi_clk clock;
260 
261         u32 fmt;
262 
263         int chan_num:16;
264         unsigned int clk_master:1;
265         unsigned int clk_cpg:1;
266         unsigned int spdif:1;
267         unsigned int enable_stream:1;
268         unsigned int bit_clk_inv:1;
269         unsigned int lr_clk_inv:1;
270 };
271 
272 struct fsi_stream_handler {
273         int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
274         int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
275         int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
276         int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
277         int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
278         int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
279                            int enable);
280 };
281 #define fsi_stream_handler_call(io, func, args...)      \
282         (!(io) ? -ENODEV :                              \
283          !((io)->handler->func) ? 0 :                   \
284          (io)->handler->func(args))
285 
286 struct fsi_core {
287         int ver;
288 
289         u32 int_st;
290         u32 iemsk;
291         u32 imsk;
292         u32 a_mclk;
293         u32 b_mclk;
294 };
295 
296 struct fsi_master {
297         void __iomem *base;
298         struct fsi_priv fsia;
299         struct fsi_priv fsib;
300         const struct fsi_core *core;
301         spinlock_t lock;
302 };
303 
304 static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io);
305 
306 /*
307  *              basic read write function
308  */
309 
310 static void __fsi_reg_write(u32 __iomem *reg, u32 data)
311 {
312         /* valid data area is 24bit */
313         data &= 0x00ffffff;
314 
315         __raw_writel(data, reg);
316 }
317 
318 static u32 __fsi_reg_read(u32 __iomem *reg)
319 {
320         return __raw_readl(reg);
321 }
322 
323 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
324 {
325         u32 val = __fsi_reg_read(reg);
326 
327         val &= ~mask;
328         val |= data & mask;
329 
330         __fsi_reg_write(reg, val);
331 }
332 
333 #define fsi_reg_write(p, r, d)\
334         __fsi_reg_write((p->base + REG_##r), d)
335 
336 #define fsi_reg_read(p, r)\
337         __fsi_reg_read((p->base + REG_##r))
338 
339 #define fsi_reg_mask_set(p, r, m, d)\
340         __fsi_reg_mask_set((p->base + REG_##r), m, d)
341 
342 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
343 #define fsi_core_read(p, r)   _fsi_master_read(p, p->core->r)
344 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
345 {
346         u32 ret;
347         unsigned long flags;
348 
349         spin_lock_irqsave(&master->lock, flags);
350         ret = __fsi_reg_read(master->base + reg);
351         spin_unlock_irqrestore(&master->lock, flags);
352 
353         return ret;
354 }
355 
356 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
357 #define fsi_core_mask_set(p, r, m, d)  _fsi_master_mask_set(p, p->core->r, m, d)
358 static void _fsi_master_mask_set(struct fsi_master *master,
359                                u32 reg, u32 mask, u32 data)
360 {
361         unsigned long flags;
362 
363         spin_lock_irqsave(&master->lock, flags);
364         __fsi_reg_mask_set(master->base + reg, mask, data);
365         spin_unlock_irqrestore(&master->lock, flags);
366 }
367 
368 /*
369  *              basic function
370  */
371 static int fsi_version(struct fsi_master *master)
372 {
373         return master->core->ver;
374 }
375 
376 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
377 {
378         return fsi->master;
379 }
380 
381 static int fsi_is_clk_master(struct fsi_priv *fsi)
382 {
383         return fsi->clk_master;
384 }
385 
386 static int fsi_is_port_a(struct fsi_priv *fsi)
387 {
388         return fsi->master->base == fsi->base;
389 }
390 
391 static int fsi_is_spdif(struct fsi_priv *fsi)
392 {
393         return fsi->spdif;
394 }
395 
396 static int fsi_is_enable_stream(struct fsi_priv *fsi)
397 {
398         return fsi->enable_stream;
399 }
400 
401 static int fsi_is_play(struct snd_pcm_substream *substream)
402 {
403         return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
404 }
405 
406 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
407 {
408         struct snd_soc_pcm_runtime *rtd = substream->private_data;
409 
410         return  rtd->cpu_dai;
411 }
412 
413 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
414 {
415         struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
416 
417         if (dai->id == 0)
418                 return &master->fsia;
419         else
420                 return &master->fsib;
421 }
422 
423 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
424 {
425         return fsi_get_priv_frm_dai(fsi_get_dai(substream));
426 }
427 
428 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
429 {
430         int is_play = fsi_stream_is_play(fsi, io);
431         int is_porta = fsi_is_port_a(fsi);
432         u32 shift;
433 
434         if (is_porta)
435                 shift = is_play ? AO_SHIFT : AI_SHIFT;
436         else
437                 shift = is_play ? BO_SHIFT : BI_SHIFT;
438 
439         return shift;
440 }
441 
442 static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
443 {
444         return frames * fsi->chan_num;
445 }
446 
447 static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
448 {
449         return samples / fsi->chan_num;
450 }
451 
452 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
453                                         struct fsi_stream *io)
454 {
455         int is_play = fsi_stream_is_play(fsi, io);
456         u32 status;
457         int frames;
458 
459         status = is_play ?
460                 fsi_reg_read(fsi, DOFF_ST) :
461                 fsi_reg_read(fsi, DIFF_ST);
462 
463         frames = 0x1ff & (status >> 8);
464 
465         return fsi_frame2sample(fsi, frames);
466 }
467 
468 static void fsi_count_fifo_err(struct fsi_priv *fsi)
469 {
470         u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
471         u32 istatus = fsi_reg_read(fsi, DIFF_ST);
472 
473         if (ostatus & ERR_OVER)
474                 fsi->playback.oerr_num++;
475 
476         if (ostatus & ERR_UNDER)
477                 fsi->playback.uerr_num++;
478 
479         if (istatus & ERR_OVER)
480                 fsi->capture.oerr_num++;
481 
482         if (istatus & ERR_UNDER)
483                 fsi->capture.uerr_num++;
484 
485         fsi_reg_write(fsi, DOFF_ST, 0);
486         fsi_reg_write(fsi, DIFF_ST, 0);
487 }
488 
489 /*
490  *              fsi_stream_xx() function
491  */
492 static inline int fsi_stream_is_play(struct fsi_priv *fsi,
493                                      struct fsi_stream *io)
494 {
495         return &fsi->playback == io;
496 }
497 
498 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
499                                         struct snd_pcm_substream *substream)
500 {
501         return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
502 }
503 
504 static int fsi_stream_is_working(struct fsi_priv *fsi,
505                                  struct fsi_stream *io)
506 {
507         struct fsi_master *master = fsi_get_master(fsi);
508         unsigned long flags;
509         int ret;
510 
511         spin_lock_irqsave(&master->lock, flags);
512         ret = !!(io->substream && io->substream->runtime);
513         spin_unlock_irqrestore(&master->lock, flags);
514 
515         return ret;
516 }
517 
518 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
519 {
520         return io->priv;
521 }
522 
523 static void fsi_stream_init(struct fsi_priv *fsi,
524                             struct fsi_stream *io,
525                             struct snd_pcm_substream *substream)
526 {
527         struct snd_pcm_runtime *runtime = substream->runtime;
528         struct fsi_master *master = fsi_get_master(fsi);
529         unsigned long flags;
530 
531         spin_lock_irqsave(&master->lock, flags);
532         io->substream   = substream;
533         io->buff_sample_capa    = fsi_frame2sample(fsi, runtime->buffer_size);
534         io->buff_sample_pos     = 0;
535         io->period_samples      = fsi_frame2sample(fsi, runtime->period_size);
536         io->period_pos          = 0;
537         io->sample_width        = samples_to_bytes(runtime, 1);
538         io->bus_option          = 0;
539         io->oerr_num    = -1; /* ignore 1st err */
540         io->uerr_num    = -1; /* ignore 1st err */
541         fsi_stream_handler_call(io, init, fsi, io);
542         spin_unlock_irqrestore(&master->lock, flags);
543 }
544 
545 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
546 {
547         struct snd_soc_dai *dai = fsi_get_dai(io->substream);
548         struct fsi_master *master = fsi_get_master(fsi);
549         unsigned long flags;
550 
551         spin_lock_irqsave(&master->lock, flags);
552 
553         if (io->oerr_num > 0)
554                 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
555 
556         if (io->uerr_num > 0)
557                 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
558 
559         fsi_stream_handler_call(io, quit, fsi, io);
560         io->substream   = NULL;
561         io->buff_sample_capa    = 0;
562         io->buff_sample_pos     = 0;
563         io->period_samples      = 0;
564         io->period_pos          = 0;
565         io->sample_width        = 0;
566         io->bus_option          = 0;
567         io->oerr_num    = 0;
568         io->uerr_num    = 0;
569         spin_unlock_irqrestore(&master->lock, flags);
570 }
571 
572 static int fsi_stream_transfer(struct fsi_stream *io)
573 {
574         struct fsi_priv *fsi = fsi_stream_to_priv(io);
575         if (!fsi)
576                 return -EIO;
577 
578         return fsi_stream_handler_call(io, transfer, fsi, io);
579 }
580 
581 #define fsi_stream_start(fsi, io)\
582         fsi_stream_handler_call(io, start_stop, fsi, io, 1)
583 
584 #define fsi_stream_stop(fsi, io)\
585         fsi_stream_handler_call(io, start_stop, fsi, io, 0)
586 
587 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
588 {
589         struct fsi_stream *io;
590         int ret1, ret2;
591 
592         io = &fsi->playback;
593         ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
594 
595         io = &fsi->capture;
596         ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
597 
598         if (ret1 < 0)
599                 return ret1;
600         if (ret2 < 0)
601                 return ret2;
602 
603         return 0;
604 }
605 
606 static int fsi_stream_remove(struct fsi_priv *fsi)
607 {
608         struct fsi_stream *io;
609         int ret1, ret2;
610 
611         io = &fsi->playback;
612         ret1 = fsi_stream_handler_call(io, remove, fsi, io);
613 
614         io = &fsi->capture;
615         ret2 = fsi_stream_handler_call(io, remove, fsi, io);
616 
617         if (ret1 < 0)
618                 return ret1;
619         if (ret2 < 0)
620                 return ret2;
621 
622         return 0;
623 }
624 
625 /*
626  *      format/bus/dma setting
627  */
628 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
629                                  u32 bus, struct device *dev)
630 {
631         struct fsi_master *master = fsi_get_master(fsi);
632         int is_play = fsi_stream_is_play(fsi, io);
633         u32 fmt = fsi->fmt;
634 
635         if (fsi_version(master) >= 2) {
636                 u32 dma = 0;
637 
638                 /*
639                  * FSI2 needs DMA/Bus setting
640                  */
641                 switch (bus) {
642                 case PACKAGE_24BITBUS_FRONT:
643                         fmt |= CR_BWS_24;
644                         dma |= VDMD_FRONT;
645                         dev_dbg(dev, "24bit bus / package in front\n");
646                         break;
647                 case PACKAGE_16BITBUS_STREAM:
648                         fmt |= CR_BWS_16;
649                         dma |= VDMD_STREAM;
650                         dev_dbg(dev, "16bit bus / stream mode\n");
651                         break;
652                 case PACKAGE_24BITBUS_BACK:
653                 default:
654                         fmt |= CR_BWS_24;
655                         dma |= VDMD_BACK;
656                         dev_dbg(dev, "24bit bus / package in back\n");
657                         break;
658                 }
659 
660                 if (is_play)
661                         fsi_reg_write(fsi, OUT_DMAC,    dma);
662                 else
663                         fsi_reg_write(fsi, IN_DMAC,     dma);
664         }
665 
666         if (is_play)
667                 fsi_reg_write(fsi, DO_FMT, fmt);
668         else
669                 fsi_reg_write(fsi, DI_FMT, fmt);
670 }
671 
672 /*
673  *              irq function
674  */
675 
676 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
677 {
678         u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
679         struct fsi_master *master = fsi_get_master(fsi);
680 
681         fsi_core_mask_set(master, imsk,  data, data);
682         fsi_core_mask_set(master, iemsk, data, data);
683 }
684 
685 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
686 {
687         u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
688         struct fsi_master *master = fsi_get_master(fsi);
689 
690         fsi_core_mask_set(master, imsk,  data, 0);
691         fsi_core_mask_set(master, iemsk, data, 0);
692 }
693 
694 static u32 fsi_irq_get_status(struct fsi_master *master)
695 {
696         return fsi_core_read(master, int_st);
697 }
698 
699 static void fsi_irq_clear_status(struct fsi_priv *fsi)
700 {
701         u32 data = 0;
702         struct fsi_master *master = fsi_get_master(fsi);
703 
704         data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
705         data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
706 
707         /* clear interrupt factor */
708         fsi_core_mask_set(master, int_st, data, 0);
709 }
710 
711 /*
712  *              SPDIF master clock function
713  *
714  * These functions are used later FSI2
715  */
716 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
717 {
718         struct fsi_master *master = fsi_get_master(fsi);
719         u32 mask, val;
720 
721         mask = BP | SE;
722         val = enable ? mask : 0;
723 
724         fsi_is_port_a(fsi) ?
725                 fsi_core_mask_set(master, a_mclk, mask, val) :
726                 fsi_core_mask_set(master, b_mclk, mask, val);
727 }
728 
729 /*
730  *              clock function
731  */
732 static int fsi_clk_init(struct device *dev,
733                         struct fsi_priv *fsi,
734                         int xck,
735                         int ick,
736                         int div,
737                         int (*set_rate)(struct device *dev,
738                                         struct fsi_priv *fsi))
739 {
740         struct fsi_clk *clock = &fsi->clock;
741         int is_porta = fsi_is_port_a(fsi);
742 
743         clock->xck      = NULL;
744         clock->ick      = NULL;
745         clock->div      = NULL;
746         clock->rate     = 0;
747         clock->count    = 0;
748         clock->set_rate = set_rate;
749 
750         clock->own = devm_clk_get(dev, NULL);
751         if (IS_ERR(clock->own))
752                 return -EINVAL;
753 
754         /* external clock */
755         if (xck) {
756                 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
757                 if (IS_ERR(clock->xck)) {
758                         dev_err(dev, "can't get xck clock\n");
759                         return -EINVAL;
760                 }
761                 if (clock->xck == clock->own) {
762                         dev_err(dev, "cpu doesn't support xck clock\n");
763                         return -EINVAL;
764                 }
765         }
766 
767         /* FSIACLK/FSIBCLK */
768         if (ick) {
769                 clock->ick = devm_clk_get(dev,  is_porta ? "icka" : "ickb");
770                 if (IS_ERR(clock->ick)) {
771                         dev_err(dev, "can't get ick clock\n");
772                         return -EINVAL;
773                 }
774                 if (clock->ick == clock->own) {
775                         dev_err(dev, "cpu doesn't support ick clock\n");
776                         return -EINVAL;
777                 }
778         }
779 
780         /* FSI-DIV */
781         if (div) {
782                 clock->div = devm_clk_get(dev,  is_porta ? "diva" : "divb");
783                 if (IS_ERR(clock->div)) {
784                         dev_err(dev, "can't get div clock\n");
785                         return -EINVAL;
786                 }
787                 if (clock->div == clock->own) {
788                         dev_err(dev, "cpu doens't support div clock\n");
789                         return -EINVAL;
790                 }
791         }
792 
793         return 0;
794 }
795 
796 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
797 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
798 {
799         fsi->clock.rate = rate;
800 }
801 
802 static int fsi_clk_is_valid(struct fsi_priv *fsi)
803 {
804         return  fsi->clock.set_rate &&
805                 fsi->clock.rate;
806 }
807 
808 static int fsi_clk_enable(struct device *dev,
809                           struct fsi_priv *fsi)
810 {
811         struct fsi_clk *clock = &fsi->clock;
812         int ret = -EINVAL;
813 
814         if (!fsi_clk_is_valid(fsi))
815                 return ret;
816 
817         if (0 == clock->count) {
818                 ret = clock->set_rate(dev, fsi);
819                 if (ret < 0) {
820                         fsi_clk_invalid(fsi);
821                         return ret;
822                 }
823 
824                 clk_enable(clock->xck);
825                 clk_enable(clock->ick);
826                 clk_enable(clock->div);
827 
828                 clock->count++;
829         }
830 
831         return ret;
832 }
833 
834 static int fsi_clk_disable(struct device *dev,
835                             struct fsi_priv *fsi)
836 {
837         struct fsi_clk *clock = &fsi->clock;
838 
839         if (!fsi_clk_is_valid(fsi))
840                 return -EINVAL;
841 
842         if (1 == clock->count--) {
843                 clk_disable(clock->xck);
844                 clk_disable(clock->ick);
845                 clk_disable(clock->div);
846         }
847 
848         return 0;
849 }
850 
851 static int fsi_clk_set_ackbpf(struct device *dev,
852                               struct fsi_priv *fsi,
853                               int ackmd, int bpfmd)
854 {
855         u32 data = 0;
856 
857         /* check ackmd/bpfmd relationship */
858         if (bpfmd > ackmd) {
859                 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
860                 return -EINVAL;
861         }
862 
863         /*  ACKMD */
864         switch (ackmd) {
865         case 512:
866                 data |= (0x0 << 12);
867                 break;
868         case 256:
869                 data |= (0x1 << 12);
870                 break;
871         case 128:
872                 data |= (0x2 << 12);
873                 break;
874         case 64:
875                 data |= (0x3 << 12);
876                 break;
877         case 32:
878                 data |= (0x4 << 12);
879                 break;
880         default:
881                 dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
882                 return -EINVAL;
883         }
884 
885         /* BPFMD */
886         switch (bpfmd) {
887         case 32:
888                 data |= (0x0 << 8);
889                 break;
890         case 64:
891                 data |= (0x1 << 8);
892                 break;
893         case 128:
894                 data |= (0x2 << 8);
895                 break;
896         case 256:
897                 data |= (0x3 << 8);
898                 break;
899         case 512:
900                 data |= (0x4 << 8);
901                 break;
902         case 16:
903                 data |= (0x7 << 8);
904                 break;
905         default:
906                 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
907                 return -EINVAL;
908         }
909 
910         dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
911 
912         fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
913         udelay(10);
914 
915         return 0;
916 }
917 
918 static int fsi_clk_set_rate_external(struct device *dev,
919                                      struct fsi_priv *fsi)
920 {
921         struct clk *xck = fsi->clock.xck;
922         struct clk *ick = fsi->clock.ick;
923         unsigned long rate = fsi->clock.rate;
924         unsigned long xrate;
925         int ackmd, bpfmd;
926         int ret = 0;
927 
928         /* check clock rate */
929         xrate = clk_get_rate(xck);
930         if (xrate % rate) {
931                 dev_err(dev, "unsupported clock rate\n");
932                 return -EINVAL;
933         }
934 
935         clk_set_parent(ick, xck);
936         clk_set_rate(ick, xrate);
937 
938         bpfmd = fsi->chan_num * 32;
939         ackmd = xrate / rate;
940 
941         dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
942 
943         ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
944         if (ret < 0)
945                 dev_err(dev, "%s failed", __func__);
946 
947         return ret;
948 }
949 
950 static int fsi_clk_set_rate_cpg(struct device *dev,
951                                 struct fsi_priv *fsi)
952 {
953         struct clk *ick = fsi->clock.ick;
954         struct clk *div = fsi->clock.div;
955         unsigned long rate = fsi->clock.rate;
956         unsigned long target = 0; /* 12288000 or 11289600 */
957         unsigned long actual, cout;
958         unsigned long diff, min;
959         unsigned long best_cout, best_act;
960         int adj;
961         int ackmd, bpfmd;
962         int ret = -EINVAL;
963 
964         if (!(12288000 % rate))
965                 target = 12288000;
966         if (!(11289600 % rate))
967                 target = 11289600;
968         if (!target) {
969                 dev_err(dev, "unsupported rate\n");
970                 return ret;
971         }
972 
973         bpfmd = fsi->chan_num * 32;
974         ackmd = target / rate;
975         ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
976         if (ret < 0) {
977                 dev_err(dev, "%s failed", __func__);
978                 return ret;
979         }
980 
981         /*
982          * The clock flow is
983          *
984          * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
985          *
986          * But, it needs to find best match of CPG and FSI_DIV
987          * combination, since it is difficult to generate correct
988          * frequency of audio clock from ick clock only.
989          * Because ick is created from its parent clock.
990          *
991          * target       = rate x [512/256/128/64]fs
992          * cout         = round(target x adjustment)
993          * actual       = cout / adjustment (by FSI-DIV) ~= target
994          * audio        = actual
995          */
996         min = ~0;
997         best_cout = 0;
998         best_act = 0;
999         for (adj = 1; adj < 0xffff; adj++) {
1000 
1001                 cout = target * adj;
1002                 if (cout > 100000000) /* max clock = 100MHz */
1003                         break;
1004 
1005                 /* cout/actual audio clock */
1006                 cout    = clk_round_rate(ick, cout);
1007                 actual  = cout / adj;
1008 
1009                 /* find best frequency */
1010                 diff = abs(actual - target);
1011                 if (diff < min) {
1012                         min             = diff;
1013                         best_cout       = cout;
1014                         best_act        = actual;
1015                 }
1016         }
1017 
1018         ret = clk_set_rate(ick, best_cout);
1019         if (ret < 0) {
1020                 dev_err(dev, "ick clock failed\n");
1021                 return -EIO;
1022         }
1023 
1024         ret = clk_set_rate(div, clk_round_rate(div, best_act));
1025         if (ret < 0) {
1026                 dev_err(dev, "div clock failed\n");
1027                 return -EIO;
1028         }
1029 
1030         dev_dbg(dev, "ick/div = %ld/%ld\n",
1031                 clk_get_rate(ick), clk_get_rate(div));
1032 
1033         return ret;
1034 }
1035 
1036 static void fsi_pointer_update(struct fsi_stream *io, int size)
1037 {
1038         io->buff_sample_pos += size;
1039 
1040         if (io->buff_sample_pos >=
1041             io->period_samples * (io->period_pos + 1)) {
1042                 struct snd_pcm_substream *substream = io->substream;
1043                 struct snd_pcm_runtime *runtime = substream->runtime;
1044 
1045                 io->period_pos++;
1046 
1047                 if (io->period_pos >= runtime->periods) {
1048                         io->buff_sample_pos = 0;
1049                         io->period_pos = 0;
1050                 }
1051 
1052                 snd_pcm_period_elapsed(substream);
1053         }
1054 }
1055 
1056 /*
1057  *              pio data transfer handler
1058  */
1059 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
1060 {
1061         int i;
1062 
1063         if (fsi_is_enable_stream(fsi)) {
1064                 /*
1065                  * stream mode
1066                  * see
1067                  *      fsi_pio_push_init()
1068                  */
1069                 u32 *buf = (u32 *)_buf;
1070 
1071                 for (i = 0; i < samples / 2; i++)
1072                         fsi_reg_write(fsi, DODT, buf[i]);
1073         } else {
1074                 /* normal mode */
1075                 u16 *buf = (u16 *)_buf;
1076 
1077                 for (i = 0; i < samples; i++)
1078                         fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
1079         }
1080 }
1081 
1082 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
1083 {
1084         u16 *buf = (u16 *)_buf;
1085         int i;
1086 
1087         for (i = 0; i < samples; i++)
1088                 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
1089 }
1090 
1091 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
1092 {
1093         u32 *buf = (u32 *)_buf;
1094         int i;
1095 
1096         for (i = 0; i < samples; i++)
1097                 fsi_reg_write(fsi, DODT, *(buf + i));
1098 }
1099 
1100 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
1101 {
1102         u32 *buf = (u32 *)_buf;
1103         int i;
1104 
1105         for (i = 0; i < samples; i++)
1106                 *(buf + i) = fsi_reg_read(fsi, DIDT);
1107 }
1108 
1109 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
1110 {
1111         struct snd_pcm_runtime *runtime = io->substream->runtime;
1112 
1113         return runtime->dma_area +
1114                 samples_to_bytes(runtime, io->buff_sample_pos);
1115 }
1116 
1117 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
1118                 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
1119                 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
1120                 int samples)
1121 {
1122         u8 *buf;
1123 
1124         if (!fsi_stream_is_working(fsi, io))
1125                 return -EINVAL;
1126 
1127         buf = fsi_pio_get_area(fsi, io);
1128 
1129         switch (io->sample_width) {
1130         case 2:
1131                 run16(fsi, buf, samples);
1132                 break;
1133         case 4:
1134                 run32(fsi, buf, samples);
1135                 break;
1136         default:
1137                 return -EINVAL;
1138         }
1139 
1140         fsi_pointer_update(io, samples);
1141 
1142         return 0;
1143 }
1144 
1145 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
1146 {
1147         int sample_residues;    /* samples in FSI fifo */
1148         int sample_space;       /* ALSA free samples space */
1149         int samples;
1150 
1151         sample_residues = fsi_get_current_fifo_samples(fsi, io);
1152         sample_space    = io->buff_sample_capa - io->buff_sample_pos;
1153 
1154         samples = min(sample_residues, sample_space);
1155 
1156         return fsi_pio_transfer(fsi, io,
1157                                   fsi_pio_pop16,
1158                                   fsi_pio_pop32,
1159                                   samples);
1160 }
1161 
1162 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
1163 {
1164         int sample_residues;    /* ALSA residue samples */
1165         int sample_space;       /* FSI fifo free samples space */
1166         int samples;
1167 
1168         sample_residues = io->buff_sample_capa - io->buff_sample_pos;
1169         sample_space    = io->fifo_sample_capa -
1170                 fsi_get_current_fifo_samples(fsi, io);
1171 
1172         samples = min(sample_residues, sample_space);
1173 
1174         return fsi_pio_transfer(fsi, io,
1175                                   fsi_pio_push16,
1176                                   fsi_pio_push32,
1177                                   samples);
1178 }
1179 
1180 static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1181                                int enable)
1182 {
1183         struct fsi_master *master = fsi_get_master(fsi);
1184         u32 clk  = fsi_is_port_a(fsi) ? CRA  : CRB;
1185 
1186         if (enable)
1187                 fsi_irq_enable(fsi, io);
1188         else
1189                 fsi_irq_disable(fsi, io);
1190 
1191         if (fsi_is_clk_master(fsi))
1192                 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1193 
1194         return 0;
1195 }
1196 
1197 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
1198 {
1199         /*
1200          * we can use 16bit stream mode
1201          * when "playback" and "16bit data"
1202          * and platform allows "stream mode"
1203          * see
1204          *      fsi_pio_push16()
1205          */
1206         if (fsi_is_enable_stream(fsi))
1207                 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1208                                  BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1209         else
1210                 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1211                                  BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1212         return 0;
1213 }
1214 
1215 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
1216 {
1217         /*
1218          * always 24bit bus, package back when "capture"
1219          */
1220         io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1221                          BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1222         return 0;
1223 }
1224 
1225 static struct fsi_stream_handler fsi_pio_push_handler = {
1226         .init           = fsi_pio_push_init,
1227         .transfer       = fsi_pio_push,
1228         .start_stop     = fsi_pio_start_stop,
1229 };
1230 
1231 static struct fsi_stream_handler fsi_pio_pop_handler = {
1232         .init           = fsi_pio_pop_init,
1233         .transfer       = fsi_pio_pop,
1234         .start_stop     = fsi_pio_start_stop,
1235 };
1236 
1237 static irqreturn_t fsi_interrupt(int irq, void *data)
1238 {
1239         struct fsi_master *master = data;
1240         u32 int_st = fsi_irq_get_status(master);
1241 
1242         /* clear irq status */
1243         fsi_master_mask_set(master, SOFT_RST, IR, 0);
1244         fsi_master_mask_set(master, SOFT_RST, IR, IR);
1245 
1246         if (int_st & AB_IO(1, AO_SHIFT))
1247                 fsi_stream_transfer(&master->fsia.playback);
1248         if (int_st & AB_IO(1, BO_SHIFT))
1249                 fsi_stream_transfer(&master->fsib.playback);
1250         if (int_st & AB_IO(1, AI_SHIFT))
1251                 fsi_stream_transfer(&master->fsia.capture);
1252         if (int_st & AB_IO(1, BI_SHIFT))
1253                 fsi_stream_transfer(&master->fsib.capture);
1254 
1255         fsi_count_fifo_err(&master->fsia);
1256         fsi_count_fifo_err(&master->fsib);
1257 
1258         fsi_irq_clear_status(&master->fsia);
1259         fsi_irq_clear_status(&master->fsib);
1260 
1261         return IRQ_HANDLED;
1262 }
1263 
1264 /*
1265  *              dma data transfer handler
1266  */
1267 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
1268 {
1269         /*
1270          * 24bit data : 24bit bus / package in back
1271          * 16bit data : 16bit bus / stream mode
1272          */
1273         io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1274                          BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1275 
1276         return 0;
1277 }
1278 
1279 static void fsi_dma_complete(void *data)
1280 {
1281         struct fsi_stream *io = (struct fsi_stream *)data;
1282         struct fsi_priv *fsi = fsi_stream_to_priv(io);
1283 
1284         fsi_pointer_update(io, io->period_samples);
1285 
1286         fsi_count_fifo_err(fsi);
1287 }
1288 
1289 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
1290 {
1291         struct snd_soc_dai *dai = fsi_get_dai(io->substream);
1292         struct snd_pcm_substream *substream = io->substream;
1293         struct dma_async_tx_descriptor *desc;
1294         int is_play = fsi_stream_is_play(fsi, io);
1295         enum dma_transfer_direction dir;
1296         int ret = -EIO;
1297 
1298         if (is_play)
1299                 dir = DMA_MEM_TO_DEV;
1300         else
1301                 dir = DMA_DEV_TO_MEM;
1302 
1303         desc = dmaengine_prep_dma_cyclic(io->chan,
1304                                          substream->runtime->dma_addr,
1305                                          snd_pcm_lib_buffer_bytes(substream),
1306                                          snd_pcm_lib_period_bytes(substream),
1307                                          dir,
1308                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1309         if (!desc) {
1310                 dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n");
1311                 goto fsi_dma_transfer_err;
1312         }
1313 
1314         desc->callback          = fsi_dma_complete;
1315         desc->callback_param    = io;
1316 
1317         if (dmaengine_submit(desc) < 0) {
1318                 dev_err(dai->dev, "tx_submit() fail\n");
1319                 goto fsi_dma_transfer_err;
1320         }
1321 
1322         dma_async_issue_pending(io->chan);
1323 
1324         /*
1325          * FIXME
1326          *
1327          * In DMAEngine case, codec and FSI cannot be started simultaneously
1328          * since FSI is using the scheduler work queue.
1329          * Therefore, in capture case, probably FSI FIFO will have got
1330          * overflow error in this point.
1331          * in that case, DMA cannot start transfer until error was cleared.
1332          */
1333         if (!is_play) {
1334                 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
1335                         fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1336                         fsi_reg_write(fsi, DIFF_ST, 0);
1337                 }
1338         }
1339 
1340         ret = 0;
1341 
1342 fsi_dma_transfer_err:
1343         return ret;
1344 }
1345 
1346 static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1347                                  int start)
1348 {
1349         struct fsi_master *master = fsi_get_master(fsi);
1350         u32 clk  = fsi_is_port_a(fsi) ? CRA  : CRB;
1351         u32 enable = start ? DMA_ON : 0;
1352 
1353         fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
1354 
1355         dmaengine_terminate_all(io->chan);
1356 
1357         if (fsi_is_clk_master(fsi))
1358                 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1359 
1360         return 0;
1361 }
1362 
1363 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
1364 {
1365         dma_cap_mask_t mask;
1366         int is_play = fsi_stream_is_play(fsi, io);
1367 
1368         dma_cap_zero(mask);
1369         dma_cap_set(DMA_SLAVE, mask);
1370 
1371         io->chan = dma_request_slave_channel_compat(mask,
1372                                 shdma_chan_filter, (void *)io->dma_id,
1373                                 dev, is_play ? "tx" : "rx");
1374         if (io->chan) {
1375                 struct dma_slave_config cfg = {};
1376                 int ret;
1377 
1378                 if (is_play) {
1379                         cfg.dst_addr            = fsi->phys + REG_DODT;
1380                         cfg.dst_addr_width      = DMA_SLAVE_BUSWIDTH_4_BYTES;
1381                         cfg.direction           = DMA_MEM_TO_DEV;
1382                 } else {
1383                         cfg.src_addr            = fsi->phys + REG_DIDT;
1384                         cfg.src_addr_width      = DMA_SLAVE_BUSWIDTH_4_BYTES;
1385                         cfg.direction           = DMA_DEV_TO_MEM;
1386                 }
1387 
1388                 ret = dmaengine_slave_config(io->chan, &cfg);
1389                 if (ret < 0) {
1390                         dma_release_channel(io->chan);
1391                         io->chan = NULL;
1392                 }
1393         }
1394 
1395         if (!io->chan) {
1396 
1397                 /* switch to PIO handler */
1398                 if (is_play)
1399                         fsi->playback.handler   = &fsi_pio_push_handler;
1400                 else
1401                         fsi->capture.handler    = &fsi_pio_pop_handler;
1402 
1403                 dev_info(dev, "switch handler (dma => pio)\n");
1404 
1405                 /* probe again */
1406                 return fsi_stream_probe(fsi, dev);
1407         }
1408 
1409         return 0;
1410 }
1411 
1412 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
1413 {
1414         fsi_stream_stop(fsi, io);
1415 
1416         if (io->chan)
1417                 dma_release_channel(io->chan);
1418 
1419         io->chan = NULL;
1420         return 0;
1421 }
1422 
1423 static struct fsi_stream_handler fsi_dma_push_handler = {
1424         .init           = fsi_dma_init,
1425         .probe          = fsi_dma_probe,
1426         .transfer       = fsi_dma_transfer,
1427         .remove         = fsi_dma_remove,
1428         .start_stop     = fsi_dma_push_start_stop,
1429 };
1430 
1431 /*
1432  *              dai ops
1433  */
1434 static void fsi_fifo_init(struct fsi_priv *fsi,
1435                           struct fsi_stream *io,
1436                           struct device *dev)
1437 {
1438         struct fsi_master *master = fsi_get_master(fsi);
1439         int is_play = fsi_stream_is_play(fsi, io);
1440         u32 shift, i;
1441         int frame_capa;
1442 
1443         /* get on-chip RAM capacity */
1444         shift = fsi_master_read(master, FIFO_SZ);
1445         shift >>= fsi_get_port_shift(fsi, io);
1446         shift &= FIFO_SZ_MASK;
1447         frame_capa = 256 << shift;
1448         dev_dbg(dev, "fifo = %d words\n", frame_capa);
1449 
1450         /*
1451          * The maximum number of sample data varies depending
1452          * on the number of channels selected for the format.
1453          *
1454          * FIFOs are used in 4-channel units in 3-channel mode
1455          * and in 8-channel units in 5- to 7-channel mode
1456          * meaning that more FIFOs than the required size of DPRAM
1457          * are used.
1458          *
1459          * ex) if 256 words of DP-RAM is connected
1460          * 1 channel:  256 (256 x 1 = 256)
1461          * 2 channels: 128 (128 x 2 = 256)
1462          * 3 channels:  64 ( 64 x 3 = 192)
1463          * 4 channels:  64 ( 64 x 4 = 256)
1464          * 5 channels:  32 ( 32 x 5 = 160)
1465          * 6 channels:  32 ( 32 x 6 = 192)
1466          * 7 channels:  32 ( 32 x 7 = 224)
1467          * 8 channels:  32 ( 32 x 8 = 256)
1468          */
1469         for (i = 1; i < fsi->chan_num; i <<= 1)
1470                 frame_capa >>= 1;
1471         dev_dbg(dev, "%d channel %d store\n",
1472                 fsi->chan_num, frame_capa);
1473 
1474         io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
1475 
1476         /*
1477          * set interrupt generation factor
1478          * clear FIFO
1479          */
1480         if (is_play) {
1481                 fsi_reg_write(fsi,      DOFF_CTL, IRQ_HALF);
1482                 fsi_reg_mask_set(fsi,   DOFF_CTL, FIFO_CLR, FIFO_CLR);
1483         } else {
1484                 fsi_reg_write(fsi,      DIFF_CTL, IRQ_HALF);
1485                 fsi_reg_mask_set(fsi,   DIFF_CTL, FIFO_CLR, FIFO_CLR);
1486         }
1487 }
1488 
1489 static int fsi_hw_startup(struct fsi_priv *fsi,
1490                           struct fsi_stream *io,
1491                           struct device *dev)
1492 {
1493         u32 data = 0;
1494 
1495         /* clock setting */
1496         if (fsi_is_clk_master(fsi))
1497                 data = DIMD | DOMD;
1498 
1499         fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
1500 
1501         /* clock inversion (CKG2) */
1502         data = 0;
1503         if (fsi->bit_clk_inv)
1504                 data |= (1 << 0);
1505         if (fsi->lr_clk_inv)
1506                 data |= (1 << 4);
1507         if (fsi_is_clk_master(fsi))
1508                 data <<= 8;
1509         fsi_reg_write(fsi, CKG2, data);
1510 
1511         /* spdif ? */
1512         if (fsi_is_spdif(fsi)) {
1513                 fsi_spdif_clk_ctrl(fsi, 1);
1514                 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
1515         }
1516 
1517         /*
1518          * get bus settings
1519          */
1520         data = 0;
1521         switch (io->sample_width) {
1522         case 2:
1523                 data = BUSOP_GET(16, io->bus_option);
1524                 break;
1525         case 4:
1526                 data = BUSOP_GET(24, io->bus_option);
1527                 break;
1528         }
1529         fsi_format_bus_setup(fsi, io, data, dev);
1530 
1531         /* irq clear */
1532         fsi_irq_disable(fsi, io);
1533         fsi_irq_clear_status(fsi);
1534 
1535         /* fifo init */
1536         fsi_fifo_init(fsi, io, dev);
1537 
1538         /* start master clock */
1539         if (fsi_is_clk_master(fsi))
1540                 return fsi_clk_enable(dev, fsi);
1541 
1542         return 0;
1543 }
1544 
1545 static int fsi_hw_shutdown(struct fsi_priv *fsi,
1546                             struct device *dev)
1547 {
1548         /* stop master clock */
1549         if (fsi_is_clk_master(fsi))
1550                 return fsi_clk_disable(dev, fsi);
1551 
1552         return 0;
1553 }
1554 
1555 static int fsi_dai_startup(struct snd_pcm_substream *substream,
1556                            struct snd_soc_dai *dai)
1557 {
1558         struct fsi_priv *fsi = fsi_get_priv(substream);
1559 
1560         fsi_clk_invalid(fsi);
1561 
1562         return 0;
1563 }
1564 
1565 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
1566                              struct snd_soc_dai *dai)
1567 {
1568         struct fsi_priv *fsi = fsi_get_priv(substream);
1569 
1570         fsi_clk_invalid(fsi);
1571 }
1572 
1573 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
1574                            struct snd_soc_dai *dai)
1575 {
1576         struct fsi_priv *fsi = fsi_get_priv(substream);
1577         struct fsi_stream *io = fsi_stream_get(fsi, substream);
1578         int ret = 0;
1579 
1580         switch (cmd) {
1581         case SNDRV_PCM_TRIGGER_START:
1582                 fsi_stream_init(fsi, io, substream);
1583                 if (!ret)
1584                         ret = fsi_hw_startup(fsi, io, dai->dev);
1585                 if (!ret)
1586                         ret = fsi_stream_start(fsi, io);
1587                 if (!ret)
1588                         ret = fsi_stream_transfer(io);
1589                 break;
1590         case SNDRV_PCM_TRIGGER_STOP:
1591                 if (!ret)
1592                         ret = fsi_hw_shutdown(fsi, dai->dev);
1593                 fsi_stream_stop(fsi, io);
1594                 fsi_stream_quit(fsi, io);
1595                 break;
1596         }
1597 
1598         return ret;
1599 }
1600 
1601 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
1602 {
1603         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1604         case SND_SOC_DAIFMT_I2S:
1605                 fsi->fmt = CR_I2S;
1606                 fsi->chan_num = 2;
1607                 break;
1608         case SND_SOC_DAIFMT_LEFT_J:
1609                 fsi->fmt = CR_PCM;
1610                 fsi->chan_num = 2;
1611                 break;
1612         default:
1613                 return -EINVAL;
1614         }
1615 
1616         return 0;
1617 }
1618 
1619 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1620 {
1621         struct fsi_master *master = fsi_get_master(fsi);
1622 
1623         if (fsi_version(master) < 2)
1624                 return -EINVAL;
1625 
1626         fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
1627         fsi->chan_num = 2;
1628 
1629         return 0;
1630 }
1631 
1632 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1633 {
1634         struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1635         int ret;
1636 
1637         /* set master/slave audio interface */
1638         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1639         case SND_SOC_DAIFMT_CBM_CFM:
1640                 break;
1641         case SND_SOC_DAIFMT_CBS_CFS:
1642                 fsi->clk_master = 1; /* codec is slave, cpu is master */
1643                 break;
1644         default:
1645                 return -EINVAL;
1646         }
1647 
1648         /* set clock inversion */
1649         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1650         case SND_SOC_DAIFMT_NB_IF:
1651                 fsi->bit_clk_inv = 0;
1652                 fsi->lr_clk_inv = 1;
1653                 break;
1654         case SND_SOC_DAIFMT_IB_NF:
1655                 fsi->bit_clk_inv = 1;
1656                 fsi->lr_clk_inv = 0;
1657                 break;
1658         case SND_SOC_DAIFMT_IB_IF:
1659                 fsi->bit_clk_inv = 1;
1660                 fsi->lr_clk_inv = 1;
1661                 break;
1662         case SND_SOC_DAIFMT_NB_NF:
1663         default:
1664                 fsi->bit_clk_inv = 0;
1665                 fsi->lr_clk_inv = 0;
1666                 break;
1667         }
1668 
1669         if (fsi_is_clk_master(fsi)) {
1670                 if (fsi->clk_cpg)
1671                         fsi_clk_init(dai->dev, fsi, 0, 1, 1,
1672                                      fsi_clk_set_rate_cpg);
1673                 else
1674                         fsi_clk_init(dai->dev, fsi, 1, 1, 0,
1675                                      fsi_clk_set_rate_external);
1676         }
1677 
1678         /* set format */
1679         if (fsi_is_spdif(fsi))
1680                 ret = fsi_set_fmt_spdif(fsi);
1681         else
1682                 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1683 
1684         return ret;
1685 }
1686 
1687 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1688                              struct snd_pcm_hw_params *params,
1689                              struct snd_soc_dai *dai)
1690 {
1691         struct fsi_priv *fsi = fsi_get_priv(substream);
1692 
1693         if (fsi_is_clk_master(fsi))
1694                 fsi_clk_valid(fsi, params_rate(params));
1695 
1696         return 0;
1697 }
1698 
1699 static const struct snd_soc_dai_ops fsi_dai_ops = {
1700         .startup        = fsi_dai_startup,
1701         .shutdown       = fsi_dai_shutdown,
1702         .trigger        = fsi_dai_trigger,
1703         .set_fmt        = fsi_dai_set_fmt,
1704         .hw_params      = fsi_dai_hw_params,
1705 };
1706 
1707 /*
1708  *              pcm ops
1709  */
1710 
1711 static struct snd_pcm_hardware fsi_pcm_hardware = {
1712         .info =         SNDRV_PCM_INFO_INTERLEAVED      |
1713                         SNDRV_PCM_INFO_MMAP             |
1714                         SNDRV_PCM_INFO_MMAP_VALID,
1715         .buffer_bytes_max       = 64 * 1024,
1716         .period_bytes_min       = 32,
1717         .period_bytes_max       = 8192,
1718         .periods_min            = 1,
1719         .periods_max            = 32,
1720         .fifo_size              = 256,
1721 };
1722 
1723 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1724 {
1725         struct snd_pcm_runtime *runtime = substream->runtime;
1726         int ret = 0;
1727 
1728         snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1729 
1730         ret = snd_pcm_hw_constraint_integer(runtime,
1731                                             SNDRV_PCM_HW_PARAM_PERIODS);
1732 
1733         return ret;
1734 }
1735 
1736 static int fsi_hw_params(struct snd_pcm_substream *substream,
1737                          struct snd_pcm_hw_params *hw_params)
1738 {
1739         return snd_pcm_lib_malloc_pages(substream,
1740                                         params_buffer_bytes(hw_params));
1741 }
1742 
1743 static int fsi_hw_free(struct snd_pcm_substream *substream)
1744 {
1745         return snd_pcm_lib_free_pages(substream);
1746 }
1747 
1748 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1749 {
1750         struct fsi_priv *fsi = fsi_get_priv(substream);
1751         struct fsi_stream *io = fsi_stream_get(fsi, substream);
1752 
1753         return fsi_sample2frame(fsi, io->buff_sample_pos);
1754 }
1755 
1756 static struct snd_pcm_ops fsi_pcm_ops = {
1757         .open           = fsi_pcm_open,
1758         .ioctl          = snd_pcm_lib_ioctl,
1759         .hw_params      = fsi_hw_params,
1760         .hw_free        = fsi_hw_free,
1761         .pointer        = fsi_pointer,
1762 };
1763 
1764 /*
1765  *              snd_soc_platform
1766  */
1767 
1768 #define PREALLOC_BUFFER         (32 * 1024)
1769 #define PREALLOC_BUFFER_MAX     (32 * 1024)
1770 
1771 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
1772 {
1773         return snd_pcm_lib_preallocate_pages_for_all(
1774                 rtd->pcm,
1775                 SNDRV_DMA_TYPE_DEV,
1776                 rtd->card->snd_card->dev,
1777                 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1778 }
1779 
1780 /*
1781  *              alsa struct
1782  */
1783 
1784 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1785         {
1786                 .name                   = "fsia-dai",
1787                 .playback = {
1788                         .rates          = FSI_RATES,
1789                         .formats        = FSI_FMTS,
1790                         .channels_min   = 2,
1791                         .channels_max   = 2,
1792                 },
1793                 .capture = {
1794                         .rates          = FSI_RATES,
1795                         .formats        = FSI_FMTS,
1796                         .channels_min   = 2,
1797                         .channels_max   = 2,
1798                 },
1799                 .ops = &fsi_dai_ops,
1800         },
1801         {
1802                 .name                   = "fsib-dai",
1803                 .playback = {
1804                         .rates          = FSI_RATES,
1805                         .formats        = FSI_FMTS,
1806                         .channels_min   = 2,
1807                         .channels_max   = 2,
1808                 },
1809                 .capture = {
1810                         .rates          = FSI_RATES,
1811                         .formats        = FSI_FMTS,
1812                         .channels_min   = 2,
1813                         .channels_max   = 2,
1814                 },
1815                 .ops = &fsi_dai_ops,
1816         },
1817 };
1818 
1819 static struct snd_soc_platform_driver fsi_soc_platform = {
1820         .ops            = &fsi_pcm_ops,
1821         .pcm_new        = fsi_pcm_new,
1822 };
1823 
1824 static const struct snd_soc_component_driver fsi_soc_component = {
1825         .name           = "fsi",
1826 };
1827 
1828 /*
1829  *              platform function
1830  */
1831 static void fsi_of_parse(char *name,
1832                          struct device_node *np,
1833                          struct sh_fsi_port_info *info,
1834                          struct device *dev)
1835 {
1836         int i;
1837         char prop[128];
1838         unsigned long flags = 0;
1839         struct {
1840                 char *name;
1841                 unsigned int val;
1842         } of_parse_property[] = {
1843                 { "spdif-connection",           SH_FSI_FMT_SPDIF },
1844                 { "stream-mode-support",        SH_FSI_ENABLE_STREAM_MODE },
1845                 { "use-internal-clock",         SH_FSI_CLK_CPG },
1846         };
1847 
1848         for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
1849                 sprintf(prop, "%s,%s", name, of_parse_property[i].name);
1850                 if (of_get_property(np, prop, NULL))
1851                         flags |= of_parse_property[i].val;
1852         }
1853         info->flags = flags;
1854 
1855         dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
1856 }
1857 
1858 static void fsi_port_info_init(struct fsi_priv *fsi,
1859                                struct sh_fsi_port_info *info)
1860 {
1861         if (info->flags & SH_FSI_FMT_SPDIF)
1862                 fsi->spdif = 1;
1863 
1864         if (info->flags & SH_FSI_CLK_CPG)
1865                 fsi->clk_cpg = 1;
1866 
1867         if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
1868                 fsi->enable_stream = 1;
1869 }
1870 
1871 static void fsi_handler_init(struct fsi_priv *fsi,
1872                              struct sh_fsi_port_info *info)
1873 {
1874         fsi->playback.handler   = &fsi_pio_push_handler; /* default PIO */
1875         fsi->playback.priv      = fsi;
1876         fsi->capture.handler    = &fsi_pio_pop_handler;  /* default PIO */
1877         fsi->capture.priv       = fsi;
1878 
1879         if (info->tx_id) {
1880                 fsi->playback.dma_id  = info->tx_id;
1881                 fsi->playback.handler = &fsi_dma_push_handler;
1882         }
1883 }
1884 
1885 static const struct fsi_core fsi1_core = {
1886         .ver    = 1,
1887 
1888         /* Interrupt */
1889         .int_st = INT_ST,
1890         .iemsk  = IEMSK,
1891         .imsk   = IMSK,
1892 };
1893 
1894 static const struct fsi_core fsi2_core = {
1895         .ver    = 2,
1896 
1897         /* Interrupt */
1898         .int_st = CPU_INT_ST,
1899         .iemsk  = CPU_IEMSK,
1900         .imsk   = CPU_IMSK,
1901         .a_mclk = A_MST_CTLR,
1902         .b_mclk = B_MST_CTLR,
1903 };
1904 
1905 static const struct of_device_id fsi_of_match[] = {
1906         { .compatible = "renesas,sh_fsi",       .data = &fsi1_core},
1907         { .compatible = "renesas,sh_fsi2",      .data = &fsi2_core},
1908         {},
1909 };
1910 MODULE_DEVICE_TABLE(of, fsi_of_match);
1911 
1912 static const struct platform_device_id fsi_id_table[] = {
1913         { "sh_fsi",     (kernel_ulong_t)&fsi1_core },
1914         { "sh_fsi2",    (kernel_ulong_t)&fsi2_core },
1915         {},
1916 };
1917 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1918 
1919 static int fsi_probe(struct platform_device *pdev)
1920 {
1921         struct fsi_master *master;
1922         struct device_node *np = pdev->dev.of_node;
1923         struct sh_fsi_platform_info info;
1924         const struct fsi_core *core;
1925         struct fsi_priv *fsi;
1926         struct resource *res;
1927         unsigned int irq;
1928         int ret;
1929 
1930         memset(&info, 0, sizeof(info));
1931 
1932         core = NULL;
1933         if (np) {
1934                 const struct of_device_id *of_id;
1935 
1936                 of_id = of_match_device(fsi_of_match, &pdev->dev);
1937                 if (of_id) {
1938                         core = of_id->data;
1939                         fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
1940                         fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
1941                 }
1942         } else {
1943                 const struct platform_device_id *id_entry = pdev->id_entry;
1944                 if (id_entry)
1945                         core = (struct fsi_core *)id_entry->driver_data;
1946 
1947                 if (pdev->dev.platform_data)
1948                         memcpy(&info, pdev->dev.platform_data, sizeof(info));
1949         }
1950 
1951         if (!core) {
1952                 dev_err(&pdev->dev, "unknown fsi device\n");
1953                 return -ENODEV;
1954         }
1955 
1956         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1957         irq = platform_get_irq(pdev, 0);
1958         if (!res || (int)irq <= 0) {
1959                 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1960                 return -ENODEV;
1961         }
1962 
1963         master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1964         if (!master) {
1965                 dev_err(&pdev->dev, "Could not allocate master\n");
1966                 return -ENOMEM;
1967         }
1968 
1969         master->base = devm_ioremap_nocache(&pdev->dev,
1970                                             res->start, resource_size(res));
1971         if (!master->base) {
1972                 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1973                 return -ENXIO;
1974         }
1975 
1976         /* master setting */
1977         master->core            = core;
1978         spin_lock_init(&master->lock);
1979 
1980         /* FSI A setting */
1981         fsi             = &master->fsia;
1982         fsi->base       = master->base;
1983         fsi->phys       = res->start;
1984         fsi->master     = master;
1985         fsi_port_info_init(fsi, &info.port_a);
1986         fsi_handler_init(fsi, &info.port_a);
1987         ret = fsi_stream_probe(fsi, &pdev->dev);
1988         if (ret < 0) {
1989                 dev_err(&pdev->dev, "FSIA stream probe failed\n");
1990                 return ret;
1991         }
1992 
1993         /* FSI B setting */
1994         fsi             = &master->fsib;
1995         fsi->base       = master->base + 0x40;
1996         fsi->phys       = res->start + 0x40;
1997         fsi->master     = master;
1998         fsi_port_info_init(fsi, &info.port_b);
1999         fsi_handler_init(fsi, &info.port_b);
2000         ret = fsi_stream_probe(fsi, &pdev->dev);
2001         if (ret < 0) {
2002                 dev_err(&pdev->dev, "FSIB stream probe failed\n");
2003                 goto exit_fsia;
2004         }
2005 
2006         pm_runtime_enable(&pdev->dev);
2007         dev_set_drvdata(&pdev->dev, master);
2008 
2009         ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
2010                                dev_name(&pdev->dev), master);
2011         if (ret) {
2012                 dev_err(&pdev->dev, "irq request err\n");
2013                 goto exit_fsib;
2014         }
2015 
2016         ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
2017         if (ret < 0) {
2018                 dev_err(&pdev->dev, "cannot snd soc register\n");
2019                 goto exit_fsib;
2020         }
2021 
2022         ret = snd_soc_register_component(&pdev->dev, &fsi_soc_component,
2023                                     fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
2024         if (ret < 0) {
2025                 dev_err(&pdev->dev, "cannot snd component register\n");
2026                 goto exit_snd_soc;
2027         }
2028 
2029         return ret;
2030 
2031 exit_snd_soc:
2032         snd_soc_unregister_platform(&pdev->dev);
2033 exit_fsib:
2034         pm_runtime_disable(&pdev->dev);
2035         fsi_stream_remove(&master->fsib);
2036 exit_fsia:
2037         fsi_stream_remove(&master->fsia);
2038 
2039         return ret;
2040 }
2041 
2042 static int fsi_remove(struct platform_device *pdev)
2043 {
2044         struct fsi_master *master;
2045 
2046         master = dev_get_drvdata(&pdev->dev);
2047 
2048         pm_runtime_disable(&pdev->dev);
2049 
2050         snd_soc_unregister_component(&pdev->dev);
2051         snd_soc_unregister_platform(&pdev->dev);
2052 
2053         fsi_stream_remove(&master->fsia);
2054         fsi_stream_remove(&master->fsib);
2055 
2056         return 0;
2057 }
2058 
2059 static void __fsi_suspend(struct fsi_priv *fsi,
2060                           struct fsi_stream *io,
2061                           struct device *dev)
2062 {
2063         if (!fsi_stream_is_working(fsi, io))
2064                 return;
2065 
2066         fsi_stream_stop(fsi, io);
2067         fsi_hw_shutdown(fsi, dev);
2068 }
2069 
2070 static void __fsi_resume(struct fsi_priv *fsi,
2071                          struct fsi_stream *io,
2072                          struct device *dev)
2073 {
2074         if (!fsi_stream_is_working(fsi, io))
2075                 return;
2076 
2077         fsi_hw_startup(fsi, io, dev);
2078         fsi_stream_start(fsi, io);
2079 }
2080 
2081 static int fsi_suspend(struct device *dev)
2082 {
2083         struct fsi_master *master = dev_get_drvdata(dev);
2084         struct fsi_priv *fsia = &master->fsia;
2085         struct fsi_priv *fsib = &master->fsib;
2086 
2087         __fsi_suspend(fsia, &fsia->playback, dev);
2088         __fsi_suspend(fsia, &fsia->capture, dev);
2089 
2090         __fsi_suspend(fsib, &fsib->playback, dev);
2091         __fsi_suspend(fsib, &fsib->capture, dev);
2092 
2093         return 0;
2094 }
2095 
2096 static int fsi_resume(struct device *dev)
2097 {
2098         struct fsi_master *master = dev_get_drvdata(dev);
2099         struct fsi_priv *fsia = &master->fsia;
2100         struct fsi_priv *fsib = &master->fsib;
2101 
2102         __fsi_resume(fsia, &fsia->playback, dev);
2103         __fsi_resume(fsia, &fsia->capture, dev);
2104 
2105         __fsi_resume(fsib, &fsib->playback, dev);
2106         __fsi_resume(fsib, &fsib->capture, dev);
2107 
2108         return 0;
2109 }
2110 
2111 static struct dev_pm_ops fsi_pm_ops = {
2112         .suspend                = fsi_suspend,
2113         .resume                 = fsi_resume,
2114 };
2115 
2116 static struct platform_driver fsi_driver = {
2117         .driver         = {
2118                 .name   = "fsi-pcm-audio",
2119                 .pm     = &fsi_pm_ops,
2120                 .of_match_table = fsi_of_match,
2121         },
2122         .probe          = fsi_probe,
2123         .remove         = fsi_remove,
2124         .id_table       = fsi_id_table,
2125 };
2126 
2127 module_platform_driver(fsi_driver);
2128 
2129 MODULE_LICENSE("GPL v2");
2130 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
2131 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
2132 MODULE_ALIAS("platform:fsi-pcm-audio");
2133 

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