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Linux/sound/soc/samsung/s3c24xx-i2s.c

  1 /*
  2  * s3c24xx-i2s.c  --  ALSA Soc Audio Layer
  3  *
  4  * (c) 2006 Wolfson Microelectronics PLC.
  5  * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
  6  *
  7  * Copyright 2004-2005 Simtec Electronics
  8  *      http://armlinux.simtec.co.uk/
  9  *      Ben Dooks <ben@simtec.co.uk>
 10  *
 11  *  This program is free software; you can redistribute  it and/or modify it
 12  *  under  the terms of  the GNU General  Public License as published by the
 13  *  Free Software Foundation;  either version 2 of the  License, or (at your
 14  *  option) any later version.
 15  */
 16 
 17 #include <linux/delay.h>
 18 #include <linux/clk.h>
 19 #include <linux/io.h>
 20 #include <linux/gpio.h>
 21 #include <linux/module.h>
 22 
 23 #include <sound/soc.h>
 24 #include <sound/pcm_params.h>
 25 
 26 #include <mach/dma.h>
 27 #include <mach/gpio-samsung.h>
 28 #include <plat/gpio-cfg.h>
 29 #include "regs-iis.h"
 30 
 31 #include "dma.h"
 32 #include "s3c24xx-i2s.h"
 33 
 34 static struct s3c2410_dma_client s3c24xx_dma_client_out = {
 35         .name = "I2S PCM Stereo out"
 36 };
 37 
 38 static struct s3c2410_dma_client s3c24xx_dma_client_in = {
 39         .name = "I2S PCM Stereo in"
 40 };
 41 
 42 static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_out = {
 43         .client         = &s3c24xx_dma_client_out,
 44         .channel        = DMACH_I2S_OUT,
 45         .dma_addr       = S3C2410_PA_IIS + S3C2410_IISFIFO,
 46         .dma_size       = 2,
 47 };
 48 
 49 static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_in = {
 50         .client         = &s3c24xx_dma_client_in,
 51         .channel        = DMACH_I2S_IN,
 52         .dma_addr       = S3C2410_PA_IIS + S3C2410_IISFIFO,
 53         .dma_size       = 2,
 54 };
 55 
 56 struct s3c24xx_i2s_info {
 57         void __iomem    *regs;
 58         struct clk      *iis_clk;
 59         u32             iiscon;
 60         u32             iismod;
 61         u32             iisfcon;
 62         u32             iispsr;
 63 };
 64 static struct s3c24xx_i2s_info s3c24xx_i2s;
 65 
 66 static void s3c24xx_snd_txctrl(int on)
 67 {
 68         u32 iisfcon;
 69         u32 iiscon;
 70         u32 iismod;
 71 
 72         pr_debug("Entered %s\n", __func__);
 73 
 74         iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
 75         iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
 76         iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
 77 
 78         pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
 79 
 80         if (on) {
 81                 iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
 82                 iiscon  |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
 83                 iiscon  &= ~S3C2410_IISCON_TXIDLE;
 84                 iismod  |= S3C2410_IISMOD_TXMODE;
 85 
 86                 writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
 87                 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
 88                 writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
 89         } else {
 90                 /* note, we have to disable the FIFOs otherwise bad things
 91                  * seem to happen when the DMA stops. According to the
 92                  * Samsung supplied kernel, this should allow the DMA
 93                  * engine and FIFOs to reset. If this isn't allowed, the
 94                  * DMA engine will simply freeze randomly.
 95                  */
 96 
 97                 iisfcon &= ~S3C2410_IISFCON_TXENABLE;
 98                 iisfcon &= ~S3C2410_IISFCON_TXDMA;
 99                 iiscon  |=  S3C2410_IISCON_TXIDLE;
100                 iiscon  &= ~S3C2410_IISCON_TXDMAEN;
101                 iismod  &= ~S3C2410_IISMOD_TXMODE;
102 
103                 writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
104                 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
105                 writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
106         }
107 
108         pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
109 }
110 
111 static void s3c24xx_snd_rxctrl(int on)
112 {
113         u32 iisfcon;
114         u32 iiscon;
115         u32 iismod;
116 
117         pr_debug("Entered %s\n", __func__);
118 
119         iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
120         iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
121         iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
122 
123         pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
124 
125         if (on) {
126                 iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
127                 iiscon  |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
128                 iiscon  &= ~S3C2410_IISCON_RXIDLE;
129                 iismod  |= S3C2410_IISMOD_RXMODE;
130 
131                 writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
132                 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
133                 writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
134         } else {
135                 /* note, we have to disable the FIFOs otherwise bad things
136                  * seem to happen when the DMA stops. According to the
137                  * Samsung supplied kernel, this should allow the DMA
138                  * engine and FIFOs to reset. If this isn't allowed, the
139                  * DMA engine will simply freeze randomly.
140                  */
141 
142                 iisfcon &= ~S3C2410_IISFCON_RXENABLE;
143                 iisfcon &= ~S3C2410_IISFCON_RXDMA;
144                 iiscon  |= S3C2410_IISCON_RXIDLE;
145                 iiscon  &= ~S3C2410_IISCON_RXDMAEN;
146                 iismod  &= ~S3C2410_IISMOD_RXMODE;
147 
148                 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
149                 writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
150                 writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
151         }
152 
153         pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
154 }
155 
156 /*
157  * Wait for the LR signal to allow synchronisation to the L/R clock
158  * from the codec. May only be needed for slave mode.
159  */
160 static int s3c24xx_snd_lrsync(void)
161 {
162         u32 iiscon;
163         int timeout = 50; /* 5ms */
164 
165         pr_debug("Entered %s\n", __func__);
166 
167         while (1) {
168                 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
169                 if (iiscon & S3C2410_IISCON_LRINDEX)
170                         break;
171 
172                 if (!timeout--)
173                         return -ETIMEDOUT;
174                 udelay(100);
175         }
176 
177         return 0;
178 }
179 
180 /*
181  * Check whether CPU is the master or slave
182  */
183 static inline int s3c24xx_snd_is_clkmaster(void)
184 {
185         pr_debug("Entered %s\n", __func__);
186 
187         return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
188 }
189 
190 /*
191  * Set S3C24xx I2S DAI format
192  */
193 static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
194                 unsigned int fmt)
195 {
196         u32 iismod;
197 
198         pr_debug("Entered %s\n", __func__);
199 
200         iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
201         pr_debug("hw_params r: IISMOD: %x \n", iismod);
202 
203         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
204         case SND_SOC_DAIFMT_CBM_CFM:
205                 iismod |= S3C2410_IISMOD_SLAVE;
206                 break;
207         case SND_SOC_DAIFMT_CBS_CFS:
208                 iismod &= ~S3C2410_IISMOD_SLAVE;
209                 break;
210         default:
211                 return -EINVAL;
212         }
213 
214         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
215         case SND_SOC_DAIFMT_LEFT_J:
216                 iismod |= S3C2410_IISMOD_MSB;
217                 break;
218         case SND_SOC_DAIFMT_I2S:
219                 iismod &= ~S3C2410_IISMOD_MSB;
220                 break;
221         default:
222                 return -EINVAL;
223         }
224 
225         writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
226         pr_debug("hw_params w: IISMOD: %x \n", iismod);
227         return 0;
228 }
229 
230 static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
231                                  struct snd_pcm_hw_params *params,
232                                  struct snd_soc_dai *dai)
233 {
234         struct snd_soc_pcm_runtime *rtd = substream->private_data;
235         struct s3c_dma_params *dma_data;
236         u32 iismod;
237 
238         pr_debug("Entered %s\n", __func__);
239 
240         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
241                 dma_data = &s3c24xx_i2s_pcm_stereo_out;
242         else
243                 dma_data = &s3c24xx_i2s_pcm_stereo_in;
244 
245         snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_data);
246 
247         /* Working copies of register */
248         iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
249         pr_debug("hw_params r: IISMOD: %x\n", iismod);
250 
251         switch (params_format(params)) {
252         case SNDRV_PCM_FORMAT_S8:
253                 iismod &= ~S3C2410_IISMOD_16BIT;
254                 dma_data->dma_size = 1;
255                 break;
256         case SNDRV_PCM_FORMAT_S16_LE:
257                 iismod |= S3C2410_IISMOD_16BIT;
258                 dma_data->dma_size = 2;
259                 break;
260         default:
261                 return -EINVAL;
262         }
263 
264         writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
265         pr_debug("hw_params w: IISMOD: %x\n", iismod);
266         return 0;
267 }
268 
269 static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
270                                struct snd_soc_dai *dai)
271 {
272         int ret = 0;
273         struct s3c_dma_params *dma_data =
274                 snd_soc_dai_get_dma_data(dai, substream);
275 
276         pr_debug("Entered %s\n", __func__);
277 
278         switch (cmd) {
279         case SNDRV_PCM_TRIGGER_START:
280         case SNDRV_PCM_TRIGGER_RESUME:
281         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
282                 if (!s3c24xx_snd_is_clkmaster()) {
283                         ret = s3c24xx_snd_lrsync();
284                         if (ret)
285                                 goto exit_err;
286                 }
287 
288                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
289                         s3c24xx_snd_rxctrl(1);
290                 else
291                         s3c24xx_snd_txctrl(1);
292 
293                 s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
294                 break;
295         case SNDRV_PCM_TRIGGER_STOP:
296         case SNDRV_PCM_TRIGGER_SUSPEND:
297         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
298                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
299                         s3c24xx_snd_rxctrl(0);
300                 else
301                         s3c24xx_snd_txctrl(0);
302                 break;
303         default:
304                 ret = -EINVAL;
305                 break;
306         }
307 
308 exit_err:
309         return ret;
310 }
311 
312 /*
313  * Set S3C24xx Clock source
314  */
315 static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
316         int clk_id, unsigned int freq, int dir)
317 {
318         u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
319 
320         pr_debug("Entered %s\n", __func__);
321 
322         iismod &= ~S3C2440_IISMOD_MPLL;
323 
324         switch (clk_id) {
325         case S3C24XX_CLKSRC_PCLK:
326                 break;
327         case S3C24XX_CLKSRC_MPLL:
328                 iismod |= S3C2440_IISMOD_MPLL;
329                 break;
330         default:
331                 return -EINVAL;
332         }
333 
334         writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
335         return 0;
336 }
337 
338 /*
339  * Set S3C24xx Clock dividers
340  */
341 static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
342         int div_id, int div)
343 {
344         u32 reg;
345 
346         pr_debug("Entered %s\n", __func__);
347 
348         switch (div_id) {
349         case S3C24XX_DIV_BCLK:
350                 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
351                 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
352                 break;
353         case S3C24XX_DIV_MCLK:
354                 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
355                 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
356                 break;
357         case S3C24XX_DIV_PRESCALER:
358                 writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
359                 reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
360                 writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
361                 break;
362         default:
363                 return -EINVAL;
364         }
365 
366         return 0;
367 }
368 
369 /*
370  * To avoid duplicating clock code, allow machine driver to
371  * get the clockrate from here.
372  */
373 u32 s3c24xx_i2s_get_clockrate(void)
374 {
375         return clk_get_rate(s3c24xx_i2s.iis_clk);
376 }
377 EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
378 
379 static int s3c24xx_i2s_probe(struct snd_soc_dai *dai)
380 {
381         pr_debug("Entered %s\n", __func__);
382 
383         s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
384         if (s3c24xx_i2s.regs == NULL)
385                 return -ENXIO;
386 
387         s3c24xx_i2s.iis_clk = clk_get(dai->dev, "iis");
388         if (IS_ERR(s3c24xx_i2s.iis_clk)) {
389                 pr_err("failed to get iis_clock\n");
390                 iounmap(s3c24xx_i2s.regs);
391                 return PTR_ERR(s3c24xx_i2s.iis_clk);
392         }
393         clk_enable(s3c24xx_i2s.iis_clk);
394 
395         /* Configure the I2S pins (GPE0...GPE4) in correct mode */
396         s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
397                               S3C_GPIO_PULL_NONE);
398 
399         writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
400 
401         s3c24xx_snd_txctrl(0);
402         s3c24xx_snd_rxctrl(0);
403 
404         return 0;
405 }
406 
407 #ifdef CONFIG_PM
408 static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
409 {
410         pr_debug("Entered %s\n", __func__);
411 
412         s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
413         s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
414         s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
415         s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
416 
417         clk_disable(s3c24xx_i2s.iis_clk);
418 
419         return 0;
420 }
421 
422 static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
423 {
424         pr_debug("Entered %s\n", __func__);
425         clk_enable(s3c24xx_i2s.iis_clk);
426 
427         writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
428         writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
429         writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
430         writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);
431 
432         return 0;
433 }
434 #else
435 #define s3c24xx_i2s_suspend NULL
436 #define s3c24xx_i2s_resume NULL
437 #endif
438 
439 
440 #define S3C24XX_I2S_RATES \
441         (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
442         SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
443         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
444 
445 static const struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
446         .trigger        = s3c24xx_i2s_trigger,
447         .hw_params      = s3c24xx_i2s_hw_params,
448         .set_fmt        = s3c24xx_i2s_set_fmt,
449         .set_clkdiv     = s3c24xx_i2s_set_clkdiv,
450         .set_sysclk     = s3c24xx_i2s_set_sysclk,
451 };
452 
453 static struct snd_soc_dai_driver s3c24xx_i2s_dai = {
454         .probe = s3c24xx_i2s_probe,
455         .suspend = s3c24xx_i2s_suspend,
456         .resume = s3c24xx_i2s_resume,
457         .playback = {
458                 .channels_min = 2,
459                 .channels_max = 2,
460                 .rates = S3C24XX_I2S_RATES,
461                 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
462         .capture = {
463                 .channels_min = 2,
464                 .channels_max = 2,
465                 .rates = S3C24XX_I2S_RATES,
466                 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
467         .ops = &s3c24xx_i2s_dai_ops,
468 };
469 
470 static const struct snd_soc_component_driver s3c24xx_i2s_component = {
471         .name           = "s3c24xx-i2s",
472 };
473 
474 static int s3c24xx_iis_dev_probe(struct platform_device *pdev)
475 {
476         int ret = 0;
477 
478         ret = snd_soc_register_component(&pdev->dev, &s3c24xx_i2s_component,
479                                          &s3c24xx_i2s_dai, 1);
480         if (ret) {
481                 pr_err("failed to register the dai\n");
482                 return ret;
483         }
484 
485         ret = samsung_asoc_dma_platform_register(&pdev->dev);
486         if (ret) {
487                 pr_err("failed to register the dma: %d\n", ret);
488                 goto err;
489         }
490 
491         return 0;
492 err:
493         snd_soc_unregister_component(&pdev->dev);
494         return ret;
495 }
496 
497 static int s3c24xx_iis_dev_remove(struct platform_device *pdev)
498 {
499         samsung_asoc_dma_platform_unregister(&pdev->dev);
500         snd_soc_unregister_component(&pdev->dev);
501         return 0;
502 }
503 
504 static struct platform_driver s3c24xx_iis_driver = {
505         .probe  = s3c24xx_iis_dev_probe,
506         .remove = s3c24xx_iis_dev_remove,
507         .driver = {
508                 .name = "s3c24xx-iis",
509                 .owner = THIS_MODULE,
510         },
511 };
512 
513 module_platform_driver(s3c24xx_iis_driver);
514 
515 /* Module information */
516 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
517 MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
518 MODULE_LICENSE("GPL");
519 MODULE_ALIAS("platform:s3c24xx-iis");
520 

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