Version:  2.6.34 2.6.35 2.6.36 2.6.37 2.6.38 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14

Linux/sound/soc/samsung/pcm.c

  1 /* sound/soc/samsung/pcm.c
  2  *
  3  * ALSA SoC Audio Layer - S3C PCM-Controller driver
  4  *
  5  * Copyright (c) 2009 Samsung Electronics Co. Ltd
  6  * Author: Jaswinder Singh <jassisinghbrar@gmail.com>
  7  * based upon I2S drivers by Ben Dooks.
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 
 14 #include <linux/clk.h>
 15 #include <linux/io.h>
 16 #include <linux/module.h>
 17 #include <linux/pm_runtime.h>
 18 
 19 #include <sound/soc.h>
 20 #include <sound/pcm_params.h>
 21 
 22 #include <linux/platform_data/asoc-s3c.h>
 23 #include <mach/dma.h>
 24 
 25 #include "dma.h"
 26 #include "pcm.h"
 27 
 28 /*Register Offsets */
 29 #define S3C_PCM_CTL             0x00
 30 #define S3C_PCM_CLKCTL          0x04
 31 #define S3C_PCM_TXFIFO          0x08
 32 #define S3C_PCM_RXFIFO          0x0C
 33 #define S3C_PCM_IRQCTL          0x10
 34 #define S3C_PCM_IRQSTAT         0x14
 35 #define S3C_PCM_FIFOSTAT        0x18
 36 #define S3C_PCM_CLRINT          0x20
 37 
 38 /* PCM_CTL Bit-Fields */
 39 #define S3C_PCM_CTL_TXDIPSTICK_MASK     0x3f
 40 #define S3C_PCM_CTL_TXDIPSTICK_SHIFT    13
 41 #define S3C_PCM_CTL_RXDIPSTICK_MASK     0x3f
 42 #define S3C_PCM_CTL_RXDIPSTICK_SHIFT    7
 43 #define S3C_PCM_CTL_TXDMA_EN            (0x1 << 6)
 44 #define S3C_PCM_CTL_RXDMA_EN            (0x1 << 5)
 45 #define S3C_PCM_CTL_TXMSB_AFTER_FSYNC   (0x1 << 4)
 46 #define S3C_PCM_CTL_RXMSB_AFTER_FSYNC   (0x1 << 3)
 47 #define S3C_PCM_CTL_TXFIFO_EN           (0x1 << 2)
 48 #define S3C_PCM_CTL_RXFIFO_EN           (0x1 << 1)
 49 #define S3C_PCM_CTL_ENABLE              (0x1 << 0)
 50 
 51 /* PCM_CLKCTL Bit-Fields */
 52 #define S3C_PCM_CLKCTL_SERCLK_EN        (0x1 << 19)
 53 #define S3C_PCM_CLKCTL_SERCLKSEL_PCLK   (0x1 << 18)
 54 #define S3C_PCM_CLKCTL_SCLKDIV_MASK     0x1ff
 55 #define S3C_PCM_CLKCTL_SYNCDIV_MASK     0x1ff
 56 #define S3C_PCM_CLKCTL_SCLKDIV_SHIFT    9
 57 #define S3C_PCM_CLKCTL_SYNCDIV_SHIFT    0
 58 
 59 /* PCM_TXFIFO Bit-Fields */
 60 #define S3C_PCM_TXFIFO_DVALID   (0x1 << 16)
 61 #define S3C_PCM_TXFIFO_DATA_MSK (0xffff << 0)
 62 
 63 /* PCM_RXFIFO Bit-Fields */
 64 #define S3C_PCM_RXFIFO_DVALID   (0x1 << 16)
 65 #define S3C_PCM_RXFIFO_DATA_MSK (0xffff << 0)
 66 
 67 /* PCM_IRQCTL Bit-Fields */
 68 #define S3C_PCM_IRQCTL_IRQEN            (0x1 << 14)
 69 #define S3C_PCM_IRQCTL_WRDEN            (0x1 << 12)
 70 #define S3C_PCM_IRQCTL_TXEMPTYEN        (0x1 << 11)
 71 #define S3C_PCM_IRQCTL_TXALMSTEMPTYEN   (0x1 << 10)
 72 #define S3C_PCM_IRQCTL_TXFULLEN         (0x1 << 9)
 73 #define S3C_PCM_IRQCTL_TXALMSTFULLEN    (0x1 << 8)
 74 #define S3C_PCM_IRQCTL_TXSTARVEN        (0x1 << 7)
 75 #define S3C_PCM_IRQCTL_TXERROVRFLEN     (0x1 << 6)
 76 #define S3C_PCM_IRQCTL_RXEMPTEN         (0x1 << 5)
 77 #define S3C_PCM_IRQCTL_RXALMSTEMPTEN    (0x1 << 4)
 78 #define S3C_PCM_IRQCTL_RXFULLEN         (0x1 << 3)
 79 #define S3C_PCM_IRQCTL_RXALMSTFULLEN    (0x1 << 2)
 80 #define S3C_PCM_IRQCTL_RXSTARVEN        (0x1 << 1)
 81 #define S3C_PCM_IRQCTL_RXERROVRFLEN     (0x1 << 0)
 82 
 83 /* PCM_IRQSTAT Bit-Fields */
 84 #define S3C_PCM_IRQSTAT_IRQPND          (0x1 << 13)
 85 #define S3C_PCM_IRQSTAT_WRD_XFER        (0x1 << 12)
 86 #define S3C_PCM_IRQSTAT_TXEMPTY         (0x1 << 11)
 87 #define S3C_PCM_IRQSTAT_TXALMSTEMPTY    (0x1 << 10)
 88 #define S3C_PCM_IRQSTAT_TXFULL          (0x1 << 9)
 89 #define S3C_PCM_IRQSTAT_TXALMSTFULL     (0x1 << 8)
 90 #define S3C_PCM_IRQSTAT_TXSTARV         (0x1 << 7)
 91 #define S3C_PCM_IRQSTAT_TXERROVRFL      (0x1 << 6)
 92 #define S3C_PCM_IRQSTAT_RXEMPT          (0x1 << 5)
 93 #define S3C_PCM_IRQSTAT_RXALMSTEMPT     (0x1 << 4)
 94 #define S3C_PCM_IRQSTAT_RXFULL          (0x1 << 3)
 95 #define S3C_PCM_IRQSTAT_RXALMSTFULL     (0x1 << 2)
 96 #define S3C_PCM_IRQSTAT_RXSTARV         (0x1 << 1)
 97 #define S3C_PCM_IRQSTAT_RXERROVRFL      (0x1 << 0)
 98 
 99 /* PCM_FIFOSTAT Bit-Fields */
100 #define S3C_PCM_FIFOSTAT_TXCNT_MSK              (0x3f << 14)
101 #define S3C_PCM_FIFOSTAT_TXFIFOEMPTY            (0x1 << 13)
102 #define S3C_PCM_FIFOSTAT_TXFIFOALMSTEMPTY       (0x1 << 12)
103 #define S3C_PCM_FIFOSTAT_TXFIFOFULL             (0x1 << 11)
104 #define S3C_PCM_FIFOSTAT_TXFIFOALMSTFULL        (0x1 << 10)
105 #define S3C_PCM_FIFOSTAT_RXCNT_MSK              (0x3f << 4)
106 #define S3C_PCM_FIFOSTAT_RXFIFOEMPTY            (0x1 << 3)
107 #define S3C_PCM_FIFOSTAT_RXFIFOALMSTEMPTY       (0x1 << 2)
108 #define S3C_PCM_FIFOSTAT_RXFIFOFULL             (0x1 << 1)
109 #define S3C_PCM_FIFOSTAT_RXFIFOALMSTFULL        (0x1 << 0)
110 
111 /**
112  * struct s3c_pcm_info - S3C PCM Controller information
113  * @dev: The parent device passed to use from the probe.
114  * @regs: The pointer to the device register block.
115  * @dma_playback: DMA information for playback channel.
116  * @dma_capture: DMA information for capture channel.
117  */
118 struct s3c_pcm_info {
119         spinlock_t lock;
120         struct device   *dev;
121         void __iomem    *regs;
122 
123         unsigned int sclk_per_fs;
124 
125         /* Whether to keep PCMSCLK enabled even when idle(no active xfer) */
126         unsigned int idleclk;
127 
128         struct clk      *pclk;
129         struct clk      *cclk;
130 
131         struct s3c_dma_params   *dma_playback;
132         struct s3c_dma_params   *dma_capture;
133 };
134 
135 static struct s3c2410_dma_client s3c_pcm_dma_client_out = {
136         .name           = "PCM Stereo out"
137 };
138 
139 static struct s3c2410_dma_client s3c_pcm_dma_client_in = {
140         .name           = "PCM Stereo in"
141 };
142 
143 static struct s3c_dma_params s3c_pcm_stereo_out[] = {
144         [0] = {
145                 .client         = &s3c_pcm_dma_client_out,
146                 .dma_size       = 4,
147         },
148         [1] = {
149                 .client         = &s3c_pcm_dma_client_out,
150                 .dma_size       = 4,
151         },
152 };
153 
154 static struct s3c_dma_params s3c_pcm_stereo_in[] = {
155         [0] = {
156                 .client         = &s3c_pcm_dma_client_in,
157                 .dma_size       = 4,
158         },
159         [1] = {
160                 .client         = &s3c_pcm_dma_client_in,
161                 .dma_size       = 4,
162         },
163 };
164 
165 static struct s3c_pcm_info s3c_pcm[2];
166 
167 static void s3c_pcm_snd_txctrl(struct s3c_pcm_info *pcm, int on)
168 {
169         void __iomem *regs = pcm->regs;
170         u32 ctl, clkctl;
171 
172         clkctl = readl(regs + S3C_PCM_CLKCTL);
173         ctl = readl(regs + S3C_PCM_CTL);
174         ctl &= ~(S3C_PCM_CTL_TXDIPSTICK_MASK
175                          << S3C_PCM_CTL_TXDIPSTICK_SHIFT);
176 
177         if (on) {
178                 ctl |= S3C_PCM_CTL_TXDMA_EN;
179                 ctl |= S3C_PCM_CTL_TXFIFO_EN;
180                 ctl |= S3C_PCM_CTL_ENABLE;
181                 ctl |= (0x4<<S3C_PCM_CTL_TXDIPSTICK_SHIFT);
182                 clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
183         } else {
184                 ctl &= ~S3C_PCM_CTL_TXDMA_EN;
185                 ctl &= ~S3C_PCM_CTL_TXFIFO_EN;
186 
187                 if (!(ctl & S3C_PCM_CTL_RXFIFO_EN)) {
188                         ctl &= ~S3C_PCM_CTL_ENABLE;
189                         if (!pcm->idleclk)
190                                 clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
191                 }
192         }
193 
194         writel(clkctl, regs + S3C_PCM_CLKCTL);
195         writel(ctl, regs + S3C_PCM_CTL);
196 }
197 
198 static void s3c_pcm_snd_rxctrl(struct s3c_pcm_info *pcm, int on)
199 {
200         void __iomem *regs = pcm->regs;
201         u32 ctl, clkctl;
202 
203         ctl = readl(regs + S3C_PCM_CTL);
204         clkctl = readl(regs + S3C_PCM_CLKCTL);
205         ctl &= ~(S3C_PCM_CTL_RXDIPSTICK_MASK
206                          << S3C_PCM_CTL_RXDIPSTICK_SHIFT);
207 
208         if (on) {
209                 ctl |= S3C_PCM_CTL_RXDMA_EN;
210                 ctl |= S3C_PCM_CTL_RXFIFO_EN;
211                 ctl |= S3C_PCM_CTL_ENABLE;
212                 ctl |= (0x20<<S3C_PCM_CTL_RXDIPSTICK_SHIFT);
213                 clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
214         } else {
215                 ctl &= ~S3C_PCM_CTL_RXDMA_EN;
216                 ctl &= ~S3C_PCM_CTL_RXFIFO_EN;
217 
218                 if (!(ctl & S3C_PCM_CTL_TXFIFO_EN)) {
219                         ctl &= ~S3C_PCM_CTL_ENABLE;
220                         if (!pcm->idleclk)
221                                 clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
222                 }
223         }
224 
225         writel(clkctl, regs + S3C_PCM_CLKCTL);
226         writel(ctl, regs + S3C_PCM_CTL);
227 }
228 
229 static int s3c_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
230                                struct snd_soc_dai *dai)
231 {
232         struct snd_soc_pcm_runtime *rtd = substream->private_data;
233         struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
234         unsigned long flags;
235 
236         dev_dbg(pcm->dev, "Entered %s\n", __func__);
237 
238         switch (cmd) {
239         case SNDRV_PCM_TRIGGER_START:
240         case SNDRV_PCM_TRIGGER_RESUME:
241         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
242                 spin_lock_irqsave(&pcm->lock, flags);
243 
244                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
245                         s3c_pcm_snd_rxctrl(pcm, 1);
246                 else
247                         s3c_pcm_snd_txctrl(pcm, 1);
248 
249                 spin_unlock_irqrestore(&pcm->lock, flags);
250                 break;
251 
252         case SNDRV_PCM_TRIGGER_STOP:
253         case SNDRV_PCM_TRIGGER_SUSPEND:
254         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
255                 spin_lock_irqsave(&pcm->lock, flags);
256 
257                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
258                         s3c_pcm_snd_rxctrl(pcm, 0);
259                 else
260                         s3c_pcm_snd_txctrl(pcm, 0);
261 
262                 spin_unlock_irqrestore(&pcm->lock, flags);
263                 break;
264 
265         default:
266                 return -EINVAL;
267         }
268 
269         return 0;
270 }
271 
272 static int s3c_pcm_hw_params(struct snd_pcm_substream *substream,
273                                  struct snd_pcm_hw_params *params,
274                                  struct snd_soc_dai *socdai)
275 {
276         struct snd_soc_pcm_runtime *rtd = substream->private_data;
277         struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
278         void __iomem *regs = pcm->regs;
279         struct clk *clk;
280         int sclk_div, sync_div;
281         unsigned long flags;
282         u32 clkctl;
283 
284         dev_dbg(pcm->dev, "Entered %s\n", __func__);
285 
286         /* Strictly check for sample size */
287         switch (params_format(params)) {
288         case SNDRV_PCM_FORMAT_S16_LE:
289                 break;
290         default:
291                 return -EINVAL;
292         }
293 
294         spin_lock_irqsave(&pcm->lock, flags);
295 
296         /* Get hold of the PCMSOURCE_CLK */
297         clkctl = readl(regs + S3C_PCM_CLKCTL);
298         if (clkctl & S3C_PCM_CLKCTL_SERCLKSEL_PCLK)
299                 clk = pcm->pclk;
300         else
301                 clk = pcm->cclk;
302 
303         /* Set the SCLK divider */
304         sclk_div = clk_get_rate(clk) / pcm->sclk_per_fs /
305                                         params_rate(params) / 2 - 1;
306 
307         clkctl &= ~(S3C_PCM_CLKCTL_SCLKDIV_MASK
308                         << S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
309         clkctl |= ((sclk_div & S3C_PCM_CLKCTL_SCLKDIV_MASK)
310                         << S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
311 
312         /* Set the SYNC divider */
313         sync_div = pcm->sclk_per_fs - 1;
314 
315         clkctl &= ~(S3C_PCM_CLKCTL_SYNCDIV_MASK
316                                 << S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
317         clkctl |= ((sync_div & S3C_PCM_CLKCTL_SYNCDIV_MASK)
318                                 << S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
319 
320         writel(clkctl, regs + S3C_PCM_CLKCTL);
321 
322         spin_unlock_irqrestore(&pcm->lock, flags);
323 
324         dev_dbg(pcm->dev, "PCMSOURCE_CLK-%lu SCLK=%ufs SCLK_DIV=%d SYNC_DIV=%d\n",
325                                 clk_get_rate(clk), pcm->sclk_per_fs,
326                                 sclk_div, sync_div);
327 
328         return 0;
329 }
330 
331 static int s3c_pcm_set_fmt(struct snd_soc_dai *cpu_dai,
332                                unsigned int fmt)
333 {
334         struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
335         void __iomem *regs = pcm->regs;
336         unsigned long flags;
337         int ret = 0;
338         u32 ctl;
339 
340         dev_dbg(pcm->dev, "Entered %s\n", __func__);
341 
342         spin_lock_irqsave(&pcm->lock, flags);
343 
344         ctl = readl(regs + S3C_PCM_CTL);
345 
346         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
347         case SND_SOC_DAIFMT_IB_NF:
348                 /* Nothing to do, IB_NF by default */
349                 break;
350         default:
351                 dev_err(pcm->dev, "Unsupported clock inversion!\n");
352                 ret = -EINVAL;
353                 goto exit;
354         }
355 
356         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
357         case SND_SOC_DAIFMT_CBS_CFS:
358                 /* Nothing to do, Master by default */
359                 break;
360         default:
361                 dev_err(pcm->dev, "Unsupported master/slave format!\n");
362                 ret = -EINVAL;
363                 goto exit;
364         }
365 
366         switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
367         case SND_SOC_DAIFMT_CONT:
368                 pcm->idleclk = 1;
369                 break;
370         case SND_SOC_DAIFMT_GATED:
371                 pcm->idleclk = 0;
372                 break;
373         default:
374                 dev_err(pcm->dev, "Invalid Clock gating request!\n");
375                 ret = -EINVAL;
376                 goto exit;
377         }
378 
379         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
380         case SND_SOC_DAIFMT_DSP_A:
381                 ctl |= S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
382                 ctl |= S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
383                 break;
384         case SND_SOC_DAIFMT_DSP_B:
385                 ctl &= ~S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
386                 ctl &= ~S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
387                 break;
388         default:
389                 dev_err(pcm->dev, "Unsupported data format!\n");
390                 ret = -EINVAL;
391                 goto exit;
392         }
393 
394         writel(ctl, regs + S3C_PCM_CTL);
395 
396 exit:
397         spin_unlock_irqrestore(&pcm->lock, flags);
398 
399         return ret;
400 }
401 
402 static int s3c_pcm_set_clkdiv(struct snd_soc_dai *cpu_dai,
403                                                 int div_id, int div)
404 {
405         struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
406 
407         switch (div_id) {
408         case S3C_PCM_SCLK_PER_FS:
409                 pcm->sclk_per_fs = div;
410                 break;
411 
412         default:
413                 return -EINVAL;
414         }
415 
416         return 0;
417 }
418 
419 static int s3c_pcm_set_sysclk(struct snd_soc_dai *cpu_dai,
420                                   int clk_id, unsigned int freq, int dir)
421 {
422         struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
423         void __iomem *regs = pcm->regs;
424         u32 clkctl = readl(regs + S3C_PCM_CLKCTL);
425 
426         switch (clk_id) {
427         case S3C_PCM_CLKSRC_PCLK:
428                 clkctl |= S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
429                 break;
430 
431         case S3C_PCM_CLKSRC_MUX:
432                 clkctl &= ~S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
433 
434                 if (clk_get_rate(pcm->cclk) != freq)
435                         clk_set_rate(pcm->cclk, freq);
436 
437                 break;
438 
439         default:
440                 return -EINVAL;
441         }
442 
443         writel(clkctl, regs + S3C_PCM_CLKCTL);
444 
445         return 0;
446 }
447 
448 static const struct snd_soc_dai_ops s3c_pcm_dai_ops = {
449         .set_sysclk     = s3c_pcm_set_sysclk,
450         .set_clkdiv     = s3c_pcm_set_clkdiv,
451         .trigger        = s3c_pcm_trigger,
452         .hw_params      = s3c_pcm_hw_params,
453         .set_fmt        = s3c_pcm_set_fmt,
454 };
455 
456 static int s3c_pcm_dai_probe(struct snd_soc_dai *dai)
457 {
458         struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(dai);
459 
460         snd_soc_dai_init_dma_data(dai, pcm->dma_playback, pcm->dma_capture);
461 
462         return 0;
463 }
464 
465 #define S3C_PCM_RATES  SNDRV_PCM_RATE_8000_96000
466 
467 #define S3C_PCM_DAI_DECLARE                     \
468         .symmetric_rates = 1,                                   \
469         .probe = s3c_pcm_dai_probe,                             \
470         .ops = &s3c_pcm_dai_ops,                                \
471         .playback = {                                           \
472                 .channels_min   = 2,                            \
473                 .channels_max   = 2,                            \
474                 .rates          = S3C_PCM_RATES,                \
475                 .formats        = SNDRV_PCM_FMTBIT_S16_LE,      \
476         },                                                      \
477         .capture = {                                            \
478                 .channels_min   = 2,                            \
479                 .channels_max   = 2,                            \
480                 .rates          = S3C_PCM_RATES,                \
481                 .formats        = SNDRV_PCM_FMTBIT_S16_LE,      \
482         }
483 
484 static struct snd_soc_dai_driver s3c_pcm_dai[] = {
485         [0] = {
486                 .name   = "samsung-pcm.0",
487                 S3C_PCM_DAI_DECLARE,
488         },
489         [1] = {
490                 .name   = "samsung-pcm.1",
491                 S3C_PCM_DAI_DECLARE,
492         },
493 };
494 
495 static const struct snd_soc_component_driver s3c_pcm_component = {
496         .name           = "s3c-pcm",
497 };
498 
499 static int s3c_pcm_dev_probe(struct platform_device *pdev)
500 {
501         struct s3c_pcm_info *pcm;
502         struct resource *mem_res, *dmatx_res, *dmarx_res;
503         struct s3c_audio_pdata *pcm_pdata;
504         int ret;
505 
506         /* Check for valid device index */
507         if ((pdev->id < 0) || pdev->id >= ARRAY_SIZE(s3c_pcm)) {
508                 dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
509                 return -EINVAL;
510         }
511 
512         pcm_pdata = pdev->dev.platform_data;
513 
514         /* Check for availability of necessary resource */
515         dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
516         if (!dmatx_res) {
517                 dev_err(&pdev->dev, "Unable to get PCM-TX dma resource\n");
518                 return -ENXIO;
519         }
520 
521         dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
522         if (!dmarx_res) {
523                 dev_err(&pdev->dev, "Unable to get PCM-RX dma resource\n");
524                 return -ENXIO;
525         }
526 
527         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
528         if (!mem_res) {
529                 dev_err(&pdev->dev, "Unable to get register resource\n");
530                 return -ENXIO;
531         }
532 
533         if (pcm_pdata && pcm_pdata->cfg_gpio && pcm_pdata->cfg_gpio(pdev)) {
534                 dev_err(&pdev->dev, "Unable to configure gpio\n");
535                 return -EINVAL;
536         }
537 
538         pcm = &s3c_pcm[pdev->id];
539         pcm->dev = &pdev->dev;
540 
541         spin_lock_init(&pcm->lock);
542 
543         /* Default is 128fs */
544         pcm->sclk_per_fs = 128;
545 
546         pcm->cclk = clk_get(&pdev->dev, "audio-bus");
547         if (IS_ERR(pcm->cclk)) {
548                 dev_err(&pdev->dev, "failed to get audio-bus\n");
549                 ret = PTR_ERR(pcm->cclk);
550                 goto err1;
551         }
552         clk_prepare_enable(pcm->cclk);
553 
554         /* record our pcm structure for later use in the callbacks */
555         dev_set_drvdata(&pdev->dev, pcm);
556 
557         if (!request_mem_region(mem_res->start,
558                                 resource_size(mem_res), "samsung-pcm")) {
559                 dev_err(&pdev->dev, "Unable to request register region\n");
560                 ret = -EBUSY;
561                 goto err2;
562         }
563 
564         pcm->regs = ioremap(mem_res->start, 0x100);
565         if (pcm->regs == NULL) {
566                 dev_err(&pdev->dev, "cannot ioremap registers\n");
567                 ret = -ENXIO;
568                 goto err3;
569         }
570 
571         pcm->pclk = clk_get(&pdev->dev, "pcm");
572         if (IS_ERR(pcm->pclk)) {
573                 dev_err(&pdev->dev, "failed to get pcm_clock\n");
574                 ret = -ENOENT;
575                 goto err4;
576         }
577         clk_prepare_enable(pcm->pclk);
578 
579         s3c_pcm_stereo_in[pdev->id].dma_addr = mem_res->start
580                                                         + S3C_PCM_RXFIFO;
581         s3c_pcm_stereo_out[pdev->id].dma_addr = mem_res->start
582                                                         + S3C_PCM_TXFIFO;
583 
584         s3c_pcm_stereo_in[pdev->id].channel = dmarx_res->start;
585         s3c_pcm_stereo_out[pdev->id].channel = dmatx_res->start;
586 
587         pcm->dma_capture = &s3c_pcm_stereo_in[pdev->id];
588         pcm->dma_playback = &s3c_pcm_stereo_out[pdev->id];
589 
590         pm_runtime_enable(&pdev->dev);
591 
592         ret = snd_soc_register_component(&pdev->dev, &s3c_pcm_component,
593                                          &s3c_pcm_dai[pdev->id], 1);
594         if (ret != 0) {
595                 dev_err(&pdev->dev, "failed to get register DAI: %d\n", ret);
596                 goto err5;
597         }
598 
599         ret = samsung_asoc_dma_platform_register(&pdev->dev);
600         if (ret) {
601                 dev_err(&pdev->dev, "failed to get register DMA: %d\n", ret);
602                 goto err6;
603         }
604 
605         return 0;
606 
607 err6:
608         snd_soc_unregister_component(&pdev->dev);
609 err5:
610         clk_disable_unprepare(pcm->pclk);
611         clk_put(pcm->pclk);
612 err4:
613         iounmap(pcm->regs);
614 err3:
615         release_mem_region(mem_res->start, resource_size(mem_res));
616 err2:
617         clk_disable_unprepare(pcm->cclk);
618         clk_put(pcm->cclk);
619 err1:
620         return ret;
621 }
622 
623 static int s3c_pcm_dev_remove(struct platform_device *pdev)
624 {
625         struct s3c_pcm_info *pcm = &s3c_pcm[pdev->id];
626         struct resource *mem_res;
627 
628         samsung_asoc_dma_platform_unregister(&pdev->dev);
629         snd_soc_unregister_component(&pdev->dev);
630 
631         pm_runtime_disable(&pdev->dev);
632 
633         iounmap(pcm->regs);
634 
635         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
636         release_mem_region(mem_res->start, resource_size(mem_res));
637 
638         clk_disable_unprepare(pcm->cclk);
639         clk_disable_unprepare(pcm->pclk);
640         clk_put(pcm->pclk);
641         clk_put(pcm->cclk);
642 
643         return 0;
644 }
645 
646 static struct platform_driver s3c_pcm_driver = {
647         .probe  = s3c_pcm_dev_probe,
648         .remove = s3c_pcm_dev_remove,
649         .driver = {
650                 .name = "samsung-pcm",
651                 .owner = THIS_MODULE,
652         },
653 };
654 
655 module_platform_driver(s3c_pcm_driver);
656 
657 /* Module information */
658 MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
659 MODULE_DESCRIPTION("S3C PCM Controller Driver");
660 MODULE_LICENSE("GPL");
661 MODULE_ALIAS("platform:samsung-pcm");
662 

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