Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/sound/soc/omap/omap-mcbsp.c

  1 /*
  2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
  3  *
  4  * Copyright (C) 2008 Nokia Corporation
  5  *
  6  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
  7  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
  8  *
  9  * This program is free software; you can redistribute it and/or
 10  * modify it under the terms of the GNU General Public License
 11  * version 2 as published by the Free Software Foundation.
 12  *
 13  * This program is distributed in the hope that it will be useful, but
 14  * WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 16  * General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program; if not, write to the Free Software
 20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 21  * 02110-1301 USA
 22  *
 23  */
 24 
 25 #include <linux/init.h>
 26 #include <linux/module.h>
 27 #include <linux/device.h>
 28 #include <linux/pm_runtime.h>
 29 #include <linux/of.h>
 30 #include <linux/of_device.h>
 31 #include <sound/core.h>
 32 #include <sound/pcm.h>
 33 #include <sound/pcm_params.h>
 34 #include <sound/initval.h>
 35 #include <sound/soc.h>
 36 #include <sound/dmaengine_pcm.h>
 37 #include <sound/omap-pcm.h>
 38 
 39 #include <linux/platform_data/asoc-ti-mcbsp.h>
 40 #include "mcbsp.h"
 41 #include "omap-mcbsp.h"
 42 
 43 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
 44 
 45 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
 46         xhandler_get, xhandler_put) \
 47 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 48         .info = omap_mcbsp_st_info_volsw, \
 49         .get = xhandler_get, .put = xhandler_put, \
 50         .private_value = (unsigned long) &(struct soc_mixer_control) \
 51         {.min = xmin, .max = xmax} }
 52 
 53 enum {
 54         OMAP_MCBSP_WORD_8 = 0,
 55         OMAP_MCBSP_WORD_12,
 56         OMAP_MCBSP_WORD_16,
 57         OMAP_MCBSP_WORD_20,
 58         OMAP_MCBSP_WORD_24,
 59         OMAP_MCBSP_WORD_32,
 60 };
 61 
 62 /*
 63  * Stream DMA parameters. DMA request line and port address are set runtime
 64  * since they are different between OMAP1 and later OMAPs
 65  */
 66 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
 67                 unsigned int packet_size)
 68 {
 69         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 70         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 71         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 72         int words;
 73 
 74         /*
 75          * Configure McBSP threshold based on either:
 76          * packet_size, when the sDMA is in packet mode, or based on the
 77          * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
 78          * for mono streams.
 79          */
 80         if (packet_size)
 81                 words = packet_size;
 82         else
 83                 words = 1;
 84 
 85         /* Configure McBSP internal buffer usage */
 86         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 87                 omap_mcbsp_set_tx_threshold(mcbsp, words);
 88         else
 89                 omap_mcbsp_set_rx_threshold(mcbsp, words);
 90 }
 91 
 92 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
 93                                     struct snd_pcm_hw_rule *rule)
 94 {
 95         struct snd_interval *buffer_size = hw_param_interval(params,
 96                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 97         struct snd_interval *channels = hw_param_interval(params,
 98                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 99         struct omap_mcbsp *mcbsp = rule->private;
100         struct snd_interval frames;
101         int size;
102 
103         snd_interval_any(&frames);
104         size = mcbsp->pdata->buffer_size;
105 
106         frames.min = size / channels->min;
107         frames.integer = 1;
108         return snd_interval_refine(buffer_size, &frames);
109 }
110 
111 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
112                                   struct snd_soc_dai *cpu_dai)
113 {
114         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
115         int err = 0;
116 
117         if (!cpu_dai->active)
118                 err = omap_mcbsp_request(mcbsp);
119 
120         /*
121          * OMAP3 McBSP FIFO is word structured.
122          * McBSP2 has 1024 + 256 = 1280 word long buffer,
123          * McBSP1,3,4,5 has 128 word long buffer
124          * This means that the size of the FIFO depends on the sample format.
125          * For example on McBSP3:
126          * 16bit samples: size is 128 * 2 = 256 bytes
127          * 32bit samples: size is 128 * 4 = 512 bytes
128          * It is simpler to place constraint for buffer and period based on
129          * channels.
130          * McBSP3 as example again (16 or 32 bit samples):
131          * 1 channel (mono): size is 128 frames (128 words)
132          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
133          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
134          */
135         if (mcbsp->pdata->buffer_size) {
136                 /*
137                 * Rule for the buffer size. We should not allow
138                 * smaller buffer than the FIFO size to avoid underruns.
139                 * This applies only for the playback stream.
140                 */
141                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
142                         snd_pcm_hw_rule_add(substream->runtime, 0,
143                                             SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
144                                             omap_mcbsp_hwrule_min_buffersize,
145                                             mcbsp,
146                                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
147 
148                 /* Make sure, that the period size is always even */
149                 snd_pcm_hw_constraint_step(substream->runtime, 0,
150                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
151         }
152 
153         return err;
154 }
155 
156 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
157                                     struct snd_soc_dai *cpu_dai)
158 {
159         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
160 
161         if (!cpu_dai->active) {
162                 omap_mcbsp_free(mcbsp);
163                 mcbsp->configured = 0;
164         }
165 }
166 
167 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
168                                   struct snd_soc_dai *cpu_dai)
169 {
170         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
171         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
172 
173         switch (cmd) {
174         case SNDRV_PCM_TRIGGER_START:
175         case SNDRV_PCM_TRIGGER_RESUME:
176         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
177                 mcbsp->active++;
178                 omap_mcbsp_start(mcbsp, play, !play);
179                 break;
180 
181         case SNDRV_PCM_TRIGGER_STOP:
182         case SNDRV_PCM_TRIGGER_SUSPEND:
183         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
184                 omap_mcbsp_stop(mcbsp, play, !play);
185                 mcbsp->active--;
186                 break;
187         default:
188                 err = -EINVAL;
189         }
190 
191         return err;
192 }
193 
194 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
195                         struct snd_pcm_substream *substream,
196                         struct snd_soc_dai *dai)
197 {
198         struct snd_soc_pcm_runtime *rtd = substream->private_data;
199         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
200         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
201         u16 fifo_use;
202         snd_pcm_sframes_t delay;
203 
204         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
205                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
206         else
207                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
208 
209         /*
210          * Divide the used locations with the channel count to get the
211          * FIFO usage in samples (don't care about partial samples in the
212          * buffer).
213          */
214         delay = fifo_use / substream->runtime->channels;
215 
216         return delay;
217 }
218 
219 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
220                                     struct snd_pcm_hw_params *params,
221                                     struct snd_soc_dai *cpu_dai)
222 {
223         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
224         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
225         struct snd_dmaengine_dai_dma_data *dma_data;
226         int wlen, channels, wpf;
227         int pkt_size = 0;
228         unsigned int format, div, framesize, master;
229 
230         dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
231         channels = params_channels(params);
232 
233         switch (params_format(params)) {
234         case SNDRV_PCM_FORMAT_S16_LE:
235                 wlen = 16;
236                 break;
237         case SNDRV_PCM_FORMAT_S32_LE:
238                 wlen = 32;
239                 break;
240         default:
241                 return -EINVAL;
242         }
243         if (mcbsp->pdata->buffer_size) {
244                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
245                         int period_words, max_thrsh;
246                         int divider = 0;
247 
248                         period_words = params_period_bytes(params) / (wlen / 8);
249                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
250                                 max_thrsh = mcbsp->max_tx_thres;
251                         else
252                                 max_thrsh = mcbsp->max_rx_thres;
253                         /*
254                          * Use sDMA packet mode if McBSP is in threshold mode:
255                          * If period words less than the FIFO size the packet
256                          * size is set to the number of period words, otherwise
257                          * Look for the biggest threshold value which divides
258                          * the period size evenly.
259                          */
260                         divider = period_words / max_thrsh;
261                         if (period_words % max_thrsh)
262                                 divider++;
263                         while (period_words % divider &&
264                                 divider < period_words)
265                                 divider++;
266                         if (divider == period_words)
267                                 return -EINVAL;
268 
269                         pkt_size = period_words / divider;
270                 } else if (channels > 1) {
271                         /* Use packet mode for non mono streams */
272                         pkt_size = channels;
273                 }
274                 omap_mcbsp_set_threshold(substream, pkt_size);
275         }
276 
277         dma_data->maxburst = pkt_size;
278 
279         if (mcbsp->configured) {
280                 /* McBSP already configured by another stream */
281                 return 0;
282         }
283 
284         regs->rcr2      &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
285         regs->xcr2      &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
286         regs->rcr1      &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
287         regs->xcr1      &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
288         format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
289         wpf = channels;
290         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
291                               format == SND_SOC_DAIFMT_LEFT_J)) {
292                 /* Use dual-phase frames */
293                 regs->rcr2      |= RPHASE;
294                 regs->xcr2      |= XPHASE;
295                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
296                 wpf--;
297                 regs->rcr2      |= RFRLEN2(wpf - 1);
298                 regs->xcr2      |= XFRLEN2(wpf - 1);
299         }
300 
301         regs->rcr1      |= RFRLEN1(wpf - 1);
302         regs->xcr1      |= XFRLEN1(wpf - 1);
303 
304         switch (params_format(params)) {
305         case SNDRV_PCM_FORMAT_S16_LE:
306                 /* Set word lengths */
307                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
308                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
309                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
310                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
311                 break;
312         case SNDRV_PCM_FORMAT_S32_LE:
313                 /* Set word lengths */
314                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
315                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
316                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
317                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
318                 break;
319         default:
320                 /* Unsupported PCM format */
321                 return -EINVAL;
322         }
323 
324         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
325          * by _counting_ BCLKs. Calculate frame size in BCLKs */
326         master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
327         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
328                 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
329                 framesize = (mcbsp->in_freq / div) / params_rate(params);
330 
331                 if (framesize < wlen * channels) {
332                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
333                                         "channels\n", __func__);
334                         return -EINVAL;
335                 }
336         } else
337                 framesize = wlen * channels;
338 
339         /* Set FS period and length in terms of bit clock periods */
340         regs->srgr2     &= ~FPER(0xfff);
341         regs->srgr1     &= ~FWID(0xff);
342         switch (format) {
343         case SND_SOC_DAIFMT_I2S:
344         case SND_SOC_DAIFMT_LEFT_J:
345                 regs->srgr2     |= FPER(framesize - 1);
346                 regs->srgr1     |= FWID((framesize >> 1) - 1);
347                 break;
348         case SND_SOC_DAIFMT_DSP_A:
349         case SND_SOC_DAIFMT_DSP_B:
350                 regs->srgr2     |= FPER(framesize - 1);
351                 regs->srgr1     |= FWID(0);
352                 break;
353         }
354 
355         omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
356         mcbsp->wlen = wlen;
357         mcbsp->configured = 1;
358 
359         return 0;
360 }
361 
362 /*
363  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
364  * cache is initialized here
365  */
366 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
367                                       unsigned int fmt)
368 {
369         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
370         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
371         bool inv_fs = false;
372 
373         if (mcbsp->configured)
374                 return 0;
375 
376         mcbsp->fmt = fmt;
377         memset(regs, 0, sizeof(*regs));
378         /* Generic McBSP register settings */
379         regs->spcr2     |= XINTM(3) | FREE;
380         regs->spcr1     |= RINTM(3);
381         /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
382         if (!mcbsp->pdata->has_ccr) {
383                 regs->rcr2      |= RFIG;
384                 regs->xcr2      |= XFIG;
385         }
386 
387         /* Configure XCCR/RCCR only for revisions which have ccr registers */
388         if (mcbsp->pdata->has_ccr) {
389                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
390                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
391         }
392 
393         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
394         case SND_SOC_DAIFMT_I2S:
395                 /* 1-bit data delay */
396                 regs->rcr2      |= RDATDLY(1);
397                 regs->xcr2      |= XDATDLY(1);
398                 break;
399         case SND_SOC_DAIFMT_LEFT_J:
400                 /* 0-bit data delay */
401                 regs->rcr2      |= RDATDLY(0);
402                 regs->xcr2      |= XDATDLY(0);
403                 regs->spcr1     |= RJUST(2);
404                 /* Invert FS polarity configuration */
405                 inv_fs = true;
406                 break;
407         case SND_SOC_DAIFMT_DSP_A:
408                 /* 1-bit data delay */
409                 regs->rcr2      |= RDATDLY(1);
410                 regs->xcr2      |= XDATDLY(1);
411                 /* Invert FS polarity configuration */
412                 inv_fs = true;
413                 break;
414         case SND_SOC_DAIFMT_DSP_B:
415                 /* 0-bit data delay */
416                 regs->rcr2      |= RDATDLY(0);
417                 regs->xcr2      |= XDATDLY(0);
418                 /* Invert FS polarity configuration */
419                 inv_fs = true;
420                 break;
421         default:
422                 /* Unsupported data format */
423                 return -EINVAL;
424         }
425 
426         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
427         case SND_SOC_DAIFMT_CBS_CFS:
428                 /* McBSP master. Set FS and bit clocks as outputs */
429                 regs->pcr0      |= FSXM | FSRM |
430                                    CLKXM | CLKRM;
431                 /* Sample rate generator drives the FS */
432                 regs->srgr2     |= FSGM;
433                 break;
434         case SND_SOC_DAIFMT_CBM_CFS:
435                 /* McBSP slave. FS clock as output */
436                 regs->srgr2     |= FSGM;
437                 regs->pcr0      |= FSXM;
438                 break;
439         case SND_SOC_DAIFMT_CBM_CFM:
440                 /* McBSP slave */
441                 break;
442         default:
443                 /* Unsupported master/slave configuration */
444                 return -EINVAL;
445         }
446 
447         /* Set bit clock (CLKX/CLKR) and FS polarities */
448         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
449         case SND_SOC_DAIFMT_NB_NF:
450                 /*
451                  * Normal BCLK + FS.
452                  * FS active low. TX data driven on falling edge of bit clock
453                  * and RX data sampled on rising edge of bit clock.
454                  */
455                 regs->pcr0      |= FSXP | FSRP |
456                                    CLKXP | CLKRP;
457                 break;
458         case SND_SOC_DAIFMT_NB_IF:
459                 regs->pcr0      |= CLKXP | CLKRP;
460                 break;
461         case SND_SOC_DAIFMT_IB_NF:
462                 regs->pcr0      |= FSXP | FSRP;
463                 break;
464         case SND_SOC_DAIFMT_IB_IF:
465                 break;
466         default:
467                 return -EINVAL;
468         }
469         if (inv_fs == true)
470                 regs->pcr0 ^= FSXP | FSRP;
471 
472         return 0;
473 }
474 
475 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
476                                      int div_id, int div)
477 {
478         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
479         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
480 
481         if (div_id != OMAP_MCBSP_CLKGDV)
482                 return -ENODEV;
483 
484         mcbsp->clk_div = div;
485         regs->srgr1     &= ~CLKGDV(0xff);
486         regs->srgr1     |= CLKGDV(div - 1);
487 
488         return 0;
489 }
490 
491 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
492                                          int clk_id, unsigned int freq,
493                                          int dir)
494 {
495         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
496         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
497         int err = 0;
498 
499         if (mcbsp->active) {
500                 if (freq == mcbsp->in_freq)
501                         return 0;
502                 else
503                         return -EBUSY;
504         }
505 
506         mcbsp->in_freq = freq;
507         regs->srgr2 &= ~CLKSM;
508         regs->pcr0 &= ~SCLKME;
509 
510         switch (clk_id) {
511         case OMAP_MCBSP_SYSCLK_CLK:
512                 regs->srgr2     |= CLKSM;
513                 break;
514         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
515                 if (mcbsp_omap1()) {
516                         err = -EINVAL;
517                         break;
518                 }
519                 err = omap2_mcbsp_set_clks_src(mcbsp,
520                                                MCBSP_CLKS_PRCM_SRC);
521                 break;
522         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
523                 if (mcbsp_omap1()) {
524                         err = 0;
525                         break;
526                 }
527                 err = omap2_mcbsp_set_clks_src(mcbsp,
528                                                MCBSP_CLKS_PAD_SRC);
529                 break;
530 
531         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
532                 regs->srgr2     |= CLKSM;
533         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
534                 regs->pcr0      |= SCLKME;
535                 break;
536         default:
537                 err = -ENODEV;
538         }
539 
540         return err;
541 }
542 
543 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
544         .startup        = omap_mcbsp_dai_startup,
545         .shutdown       = omap_mcbsp_dai_shutdown,
546         .trigger        = omap_mcbsp_dai_trigger,
547         .delay          = omap_mcbsp_dai_delay,
548         .hw_params      = omap_mcbsp_dai_hw_params,
549         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
550         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
551         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
552 };
553 
554 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
555 {
556         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
557 
558         pm_runtime_enable(mcbsp->dev);
559 
560         snd_soc_dai_init_dma_data(dai,
561                                   &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
562                                   &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
563 
564         return 0;
565 }
566 
567 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
568 {
569         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
570 
571         pm_runtime_disable(mcbsp->dev);
572 
573         return 0;
574 }
575 
576 static struct snd_soc_dai_driver omap_mcbsp_dai = {
577         .probe = omap_mcbsp_probe,
578         .remove = omap_mcbsp_remove,
579         .playback = {
580                 .channels_min = 1,
581                 .channels_max = 16,
582                 .rates = OMAP_MCBSP_RATES,
583                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
584         },
585         .capture = {
586                 .channels_min = 1,
587                 .channels_max = 16,
588                 .rates = OMAP_MCBSP_RATES,
589                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
590         },
591         .ops = &mcbsp_dai_ops,
592 };
593 
594 static const struct snd_soc_component_driver omap_mcbsp_component = {
595         .name           = "omap-mcbsp",
596 };
597 
598 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
599                         struct snd_ctl_elem_info *uinfo)
600 {
601         struct soc_mixer_control *mc =
602                 (struct soc_mixer_control *)kcontrol->private_value;
603         int max = mc->max;
604         int min = mc->min;
605 
606         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
607         uinfo->count = 1;
608         uinfo->value.integer.min = min;
609         uinfo->value.integer.max = max;
610         return 0;
611 }
612 
613 #define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel)                           \
614 static int                                                              \
615 omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc,         \
616                                         struct snd_ctl_elem_value *uc)  \
617 {                                                                       \
618         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
619         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
620         struct soc_mixer_control *mc =                                  \
621                 (struct soc_mixer_control *)kc->private_value;          \
622         int max = mc->max;                                              \
623         int min = mc->min;                                              \
624         int val = uc->value.integer.value[0];                           \
625                                                                         \
626         if (val < min || val > max)                                     \
627                 return -EINVAL;                                         \
628                                                                         \
629         /* OMAP McBSP implementation uses index values 0..4 */          \
630         return omap_st_set_chgain(mcbsp, channel, val);                 \
631 }                                                                       \
632                                                                         \
633 static int                                                              \
634 omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc,         \
635                                         struct snd_ctl_elem_value *uc)  \
636 {                                                                       \
637         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
638         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
639         s16 chgain;                                                     \
640                                                                         \
641         if (omap_st_get_chgain(mcbsp, channel, &chgain))                \
642                 return -EAGAIN;                                         \
643                                                                         \
644         uc->value.integer.value[0] = chgain;                            \
645         return 0;                                                       \
646 }
647 
648 OMAP_MCBSP_ST_CHANNEL_VOLUME(0)
649 OMAP_MCBSP_ST_CHANNEL_VOLUME(1)
650 
651 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
652                                 struct snd_ctl_elem_value *ucontrol)
653 {
654         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
655         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
656         u8 value = ucontrol->value.integer.value[0];
657 
658         if (value == omap_st_is_enabled(mcbsp))
659                 return 0;
660 
661         if (value)
662                 omap_st_enable(mcbsp);
663         else
664                 omap_st_disable(mcbsp);
665 
666         return 1;
667 }
668 
669 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
670                                 struct snd_ctl_elem_value *ucontrol)
671 {
672         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
673         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
674 
675         ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
676         return 0;
677 }
678 
679 #define OMAP_MCBSP_ST_CONTROLS(port)                                      \
680 static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \
681 SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0,              \
682                omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),           \
683 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \
684                               -32768, 32767,                              \
685                               omap_mcbsp_get_st_ch0_volume,               \
686                               omap_mcbsp_set_st_ch0_volume),              \
687 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \
688                               -32768, 32767,                              \
689                               omap_mcbsp_get_st_ch1_volume,               \
690                               omap_mcbsp_set_st_ch1_volume),              \
691 }
692 
693 OMAP_MCBSP_ST_CONTROLS(2);
694 OMAP_MCBSP_ST_CONTROLS(3);
695 
696 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd, int port_id)
697 {
698         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
699         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
700 
701         if (!mcbsp->st_data) {
702                 dev_warn(mcbsp->dev, "No sidetone data for port\n");
703                 return 0;
704         }
705 
706         switch (port_id) {
707         case 2: /* McBSP 2 */
708                 return snd_soc_add_dai_controls(cpu_dai,
709                                         omap_mcbsp2_st_controls,
710                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
711         case 3: /* McBSP 3 */
712                 return snd_soc_add_dai_controls(cpu_dai,
713                                         omap_mcbsp3_st_controls,
714                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
715         default:
716                 dev_err(mcbsp->dev, "Port %d not supported\n", port_id);
717                 break;
718         }
719 
720         return -EINVAL;
721 }
722 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
723 
724 static struct omap_mcbsp_platform_data omap2420_pdata = {
725         .reg_step = 4,
726         .reg_size = 2,
727 };
728 
729 static struct omap_mcbsp_platform_data omap2430_pdata = {
730         .reg_step = 4,
731         .reg_size = 4,
732         .has_ccr = true,
733 };
734 
735 static struct omap_mcbsp_platform_data omap3_pdata = {
736         .reg_step = 4,
737         .reg_size = 4,
738         .has_ccr = true,
739         .has_wakeup = true,
740 };
741 
742 static struct omap_mcbsp_platform_data omap4_pdata = {
743         .reg_step = 4,
744         .reg_size = 4,
745         .has_ccr = true,
746         .has_wakeup = true,
747 };
748 
749 static const struct of_device_id omap_mcbsp_of_match[] = {
750         {
751                 .compatible = "ti,omap2420-mcbsp",
752                 .data = &omap2420_pdata,
753         },
754         {
755                 .compatible = "ti,omap2430-mcbsp",
756                 .data = &omap2430_pdata,
757         },
758         {
759                 .compatible = "ti,omap3-mcbsp",
760                 .data = &omap3_pdata,
761         },
762         {
763                 .compatible = "ti,omap4-mcbsp",
764                 .data = &omap4_pdata,
765         },
766         { },
767 };
768 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
769 
770 static int asoc_mcbsp_probe(struct platform_device *pdev)
771 {
772         struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
773         struct omap_mcbsp *mcbsp;
774         const struct of_device_id *match;
775         int ret;
776 
777         match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
778         if (match) {
779                 struct device_node *node = pdev->dev.of_node;
780                 int buffer_size;
781 
782                 pdata = devm_kzalloc(&pdev->dev,
783                                      sizeof(struct omap_mcbsp_platform_data),
784                                      GFP_KERNEL);
785                 if (!pdata)
786                         return -ENOMEM;
787 
788                 memcpy(pdata, match->data, sizeof(*pdata));
789                 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
790                         pdata->buffer_size = buffer_size;
791         } else if (!pdata) {
792                 dev_err(&pdev->dev, "missing platform data.\n");
793                 return -EINVAL;
794         }
795         mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
796         if (!mcbsp)
797                 return -ENOMEM;
798 
799         mcbsp->id = pdev->id;
800         mcbsp->pdata = pdata;
801         mcbsp->dev = &pdev->dev;
802         platform_set_drvdata(pdev, mcbsp);
803 
804         ret = omap_mcbsp_init(pdev);
805         if (ret)
806                 return ret;
807 
808         ret = snd_soc_register_component(&pdev->dev, &omap_mcbsp_component,
809                                          &omap_mcbsp_dai, 1);
810         if (ret)
811                 return ret;
812 
813         return omap_pcm_platform_register(&pdev->dev);
814 }
815 
816 static int asoc_mcbsp_remove(struct platform_device *pdev)
817 {
818         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
819 
820         snd_soc_unregister_component(&pdev->dev);
821 
822         if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
823                 mcbsp->pdata->ops->free(mcbsp->id);
824 
825         omap_mcbsp_sysfs_remove(mcbsp);
826 
827         clk_put(mcbsp->fclk);
828 
829         return 0;
830 }
831 
832 static struct platform_driver asoc_mcbsp_driver = {
833         .driver = {
834                         .name = "omap-mcbsp",
835                         .owner = THIS_MODULE,
836                         .of_match_table = omap_mcbsp_of_match,
837         },
838 
839         .probe = asoc_mcbsp_probe,
840         .remove = asoc_mcbsp_remove,
841 };
842 
843 module_platform_driver(asoc_mcbsp_driver);
844 
845 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
846 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
847 MODULE_LICENSE("GPL");
848 MODULE_ALIAS("platform:omap-mcbsp");
849 

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