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Linux/sound/soc/jz4740/jz4740-i2s.c

  1 /*
  2  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  3  *
  4  *  This program is free software; you can redistribute it and/or modify it
  5  *  under  the terms of the GNU General  Public License as published by the
  6  *  Free Software Foundation;  either version 2 of the License, or (at your
  7  *  option) any later version.
  8  *
  9  *  You should have received a copy of the GNU General Public License along
 10  *  with this program; if not, write to the Free Software Foundation, Inc.,
 11  *  675 Mass Ave, Cambridge, MA 02139, USA.
 12  *
 13  */
 14 
 15 #include <linux/init.h>
 16 #include <linux/io.h>
 17 #include <linux/kernel.h>
 18 #include <linux/module.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/slab.h>
 21 
 22 #include <linux/clk.h>
 23 #include <linux/delay.h>
 24 
 25 #include <linux/dma-mapping.h>
 26 
 27 #include <sound/core.h>
 28 #include <sound/pcm.h>
 29 #include <sound/pcm_params.h>
 30 #include <sound/soc.h>
 31 #include <sound/initval.h>
 32 #include <sound/dmaengine_pcm.h>
 33 
 34 #include <asm/mach-jz4740/dma.h>
 35 
 36 #include "jz4740-i2s.h"
 37 
 38 #define JZ_REG_AIC_CONF         0x00
 39 #define JZ_REG_AIC_CTRL         0x04
 40 #define JZ_REG_AIC_I2S_FMT      0x10
 41 #define JZ_REG_AIC_FIFO_STATUS  0x14
 42 #define JZ_REG_AIC_I2S_STATUS   0x1c
 43 #define JZ_REG_AIC_CLK_DIV      0x30
 44 #define JZ_REG_AIC_FIFO         0x34
 45 
 46 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
 47 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf <<  8)
 48 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
 49 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
 50 #define JZ_AIC_CONF_I2S BIT(4)
 51 #define JZ_AIC_CONF_RESET BIT(3)
 52 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
 53 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
 54 #define JZ_AIC_CONF_ENABLE BIT(0)
 55 
 56 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
 57 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
 58 
 59 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
 60 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
 61 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
 62 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
 63 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
 64 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
 65 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
 66 #define JZ_AIC_CTRL_FLUSH               BIT(8)
 67 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
 68 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
 69 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
 70 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
 71 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
 72 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
 73 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
 74 
 75 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
 76 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET  16
 77 
 78 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
 79 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
 80 #define JZ_AIC_I2S_FMT_MSB BIT(0)
 81 
 82 #define JZ_AIC_I2S_STATUS_BUSY BIT(2)
 83 
 84 #define JZ_AIC_CLK_DIV_MASK 0xf
 85 
 86 struct jz4740_i2s {
 87         struct resource *mem;
 88         void __iomem *base;
 89         dma_addr_t phys_base;
 90 
 91         struct clk *clk_aic;
 92         struct clk *clk_i2s;
 93 
 94         struct snd_dmaengine_dai_dma_data playback_dma_data;
 95         struct snd_dmaengine_dai_dma_data capture_dma_data;
 96 };
 97 
 98 static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
 99         unsigned int reg)
100 {
101         return readl(i2s->base + reg);
102 }
103 
104 static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
105         unsigned int reg, uint32_t value)
106 {
107         writel(value, i2s->base + reg);
108 }
109 
110 static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
111         struct snd_soc_dai *dai)
112 {
113         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
114         uint32_t conf, ctrl;
115 
116         if (dai->active)
117                 return 0;
118 
119         ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
120         ctrl |= JZ_AIC_CTRL_FLUSH;
121         jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
122 
123         clk_prepare_enable(i2s->clk_i2s);
124 
125         conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
126         conf |= JZ_AIC_CONF_ENABLE;
127         jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
128 
129         return 0;
130 }
131 
132 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
133         struct snd_soc_dai *dai)
134 {
135         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
136         uint32_t conf;
137 
138         if (dai->active)
139                 return;
140 
141         conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
142         conf &= ~JZ_AIC_CONF_ENABLE;
143         jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
144 
145         clk_disable_unprepare(i2s->clk_i2s);
146 }
147 
148 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
149         struct snd_soc_dai *dai)
150 {
151         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
152 
153         uint32_t ctrl;
154         uint32_t mask;
155 
156         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
157                 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
158         else
159                 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
160 
161         ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
162 
163         switch (cmd) {
164         case SNDRV_PCM_TRIGGER_START:
165         case SNDRV_PCM_TRIGGER_RESUME:
166         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
167                 ctrl |= mask;
168                 break;
169         case SNDRV_PCM_TRIGGER_STOP:
170         case SNDRV_PCM_TRIGGER_SUSPEND:
171         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
172                 ctrl &= ~mask;
173                 break;
174         default:
175                 return -EINVAL;
176         }
177 
178         jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
179 
180         return 0;
181 }
182 
183 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
184 {
185         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
186 
187         uint32_t format = 0;
188         uint32_t conf;
189 
190         conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
191 
192         conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
193 
194         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
195         case SND_SOC_DAIFMT_CBS_CFS:
196                 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
197                 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
198                 break;
199         case SND_SOC_DAIFMT_CBM_CFS:
200                 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
201                 break;
202         case SND_SOC_DAIFMT_CBS_CFM:
203                 conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
204                 break;
205         case SND_SOC_DAIFMT_CBM_CFM:
206                 break;
207         default:
208                 return -EINVAL;
209         }
210 
211         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
212         case SND_SOC_DAIFMT_MSB:
213                 format |= JZ_AIC_I2S_FMT_MSB;
214                 break;
215         case SND_SOC_DAIFMT_I2S:
216                 break;
217         default:
218                 return -EINVAL;
219         }
220 
221         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
222         case SND_SOC_DAIFMT_NB_NF:
223                 break;
224         default:
225                 return -EINVAL;
226         }
227 
228         jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
229         jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
230 
231         return 0;
232 }
233 
234 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
235         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
236 {
237         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
238         unsigned int sample_size;
239         uint32_t ctrl;
240 
241         ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
242 
243         switch (params_format(params)) {
244         case SNDRV_PCM_FORMAT_S8:
245                 sample_size = 0;
246                 break;
247         case SNDRV_PCM_FORMAT_S16:
248                 sample_size = 1;
249                 break;
250         default:
251                 return -EINVAL;
252         }
253 
254         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
255                 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
256                 ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
257                 if (params_channels(params) == 1)
258                         ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
259                 else
260                         ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
261         } else {
262                 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
263                 ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
264         }
265 
266         jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
267 
268         return 0;
269 }
270 
271 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
272         unsigned int freq, int dir)
273 {
274         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
275         struct clk *parent;
276         int ret = 0;
277 
278         switch (clk_id) {
279         case JZ4740_I2S_CLKSRC_EXT:
280                 parent = clk_get(NULL, "ext");
281                 clk_set_parent(i2s->clk_i2s, parent);
282                 break;
283         case JZ4740_I2S_CLKSRC_PLL:
284                 parent = clk_get(NULL, "pll half");
285                 clk_set_parent(i2s->clk_i2s, parent);
286                 ret = clk_set_rate(i2s->clk_i2s, freq);
287                 break;
288         default:
289                 return -EINVAL;
290         }
291         clk_put(parent);
292 
293         return ret;
294 }
295 
296 static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
297 {
298         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
299         uint32_t conf;
300 
301         if (dai->active) {
302                 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
303                 conf &= ~JZ_AIC_CONF_ENABLE;
304                 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
305 
306                 clk_disable_unprepare(i2s->clk_i2s);
307         }
308 
309         clk_disable_unprepare(i2s->clk_aic);
310 
311         return 0;
312 }
313 
314 static int jz4740_i2s_resume(struct snd_soc_dai *dai)
315 {
316         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
317         uint32_t conf;
318 
319         clk_prepare_enable(i2s->clk_aic);
320 
321         if (dai->active) {
322                 clk_prepare_enable(i2s->clk_i2s);
323 
324                 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
325                 conf |= JZ_AIC_CONF_ENABLE;
326                 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
327         }
328 
329         return 0;
330 }
331 
332 static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
333 {
334         struct snd_dmaengine_dai_dma_data *dma_data;
335 
336         /* Playback */
337         dma_data = &i2s->playback_dma_data;
338         dma_data->maxburst = 16;
339         dma_data->slave_id = JZ4740_DMA_TYPE_AIC_TRANSMIT;
340         dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
341 
342         /* Capture */
343         dma_data = &i2s->capture_dma_data;
344         dma_data->maxburst = 16;
345         dma_data->slave_id = JZ4740_DMA_TYPE_AIC_RECEIVE;
346         dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
347 }
348 
349 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
350 {
351         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
352         uint32_t conf;
353 
354         clk_prepare_enable(i2s->clk_aic);
355 
356         jz4740_i2c_init_pcm_config(i2s);
357         snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
358                 &i2s->capture_dma_data);
359 
360         conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
361                 (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
362                 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
363                 JZ_AIC_CONF_I2S |
364                 JZ_AIC_CONF_INTERNAL_CODEC;
365 
366         jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
367         jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
368 
369         return 0;
370 }
371 
372 static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
373 {
374         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
375 
376         clk_disable_unprepare(i2s->clk_aic);
377         return 0;
378 }
379 
380 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
381         .startup = jz4740_i2s_startup,
382         .shutdown = jz4740_i2s_shutdown,
383         .trigger = jz4740_i2s_trigger,
384         .hw_params = jz4740_i2s_hw_params,
385         .set_fmt = jz4740_i2s_set_fmt,
386         .set_sysclk = jz4740_i2s_set_sysclk,
387 };
388 
389 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
390                 SNDRV_PCM_FMTBIT_S16_LE)
391 
392 static struct snd_soc_dai_driver jz4740_i2s_dai = {
393         .probe = jz4740_i2s_dai_probe,
394         .remove = jz4740_i2s_dai_remove,
395         .playback = {
396                 .channels_min = 1,
397                 .channels_max = 2,
398                 .rates = SNDRV_PCM_RATE_8000_48000,
399                 .formats = JZ4740_I2S_FMTS,
400         },
401         .capture = {
402                 .channels_min = 2,
403                 .channels_max = 2,
404                 .rates = SNDRV_PCM_RATE_8000_48000,
405                 .formats = JZ4740_I2S_FMTS,
406         },
407         .symmetric_rates = 1,
408         .ops = &jz4740_i2s_dai_ops,
409         .suspend = jz4740_i2s_suspend,
410         .resume = jz4740_i2s_resume,
411 };
412 
413 static const struct snd_soc_component_driver jz4740_i2s_component = {
414         .name           = "jz4740-i2s",
415 };
416 
417 static int jz4740_i2s_dev_probe(struct platform_device *pdev)
418 {
419         struct jz4740_i2s *i2s;
420         struct resource *mem;
421         int ret;
422 
423         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
424         if (!i2s)
425                 return -ENOMEM;
426 
427         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
428         i2s->base = devm_ioremap_resource(&pdev->dev, mem);
429         if (IS_ERR(i2s->base))
430                 return PTR_ERR(i2s->base);
431 
432         i2s->phys_base = mem->start;
433 
434         i2s->clk_aic = devm_clk_get(&pdev->dev, "aic");
435         if (IS_ERR(i2s->clk_aic))
436                 return PTR_ERR(i2s->clk_aic);
437 
438         i2s->clk_i2s = devm_clk_get(&pdev->dev, "i2s");
439         if (IS_ERR(i2s->clk_i2s))
440                 return PTR_ERR(i2s->clk_i2s);
441 
442         platform_set_drvdata(pdev, i2s);
443 
444         ret = devm_snd_soc_register_component(&pdev->dev,
445                 &jz4740_i2s_component, &jz4740_i2s_dai, 1);
446         if (ret)
447                 return ret;
448 
449         return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
450                 SND_DMAENGINE_PCM_FLAG_COMPAT);
451 }
452 
453 static struct platform_driver jz4740_i2s_driver = {
454         .probe = jz4740_i2s_dev_probe,
455         .driver = {
456                 .name = "jz4740-i2s",
457                 .owner = THIS_MODULE,
458         },
459 };
460 
461 module_platform_driver(jz4740_i2s_driver);
462 
463 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
464 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
465 MODULE_LICENSE("GPL");
466 MODULE_ALIAS("platform:jz4740-i2s");
467 

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