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Linux/sound/soc/fsl/imx-ssi.c

  1 /*
  2  * imx-ssi.c  --  ALSA Soc Audio Layer
  3  *
  4  * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
  5  *
  6  * This code is based on code copyrighted by Freescale,
  7  * Liam Girdwood, Javier Martin and probably others.
  8  *
  9  *  This program is free software; you can redistribute  it and/or modify it
 10  *  under  the terms of  the GNU General  Public License as published by the
 11  *  Free Software Foundation;  either version 2 of the  License, or (at your
 12  *  option) any later version.
 13  *
 14  *
 15  * The i.MX SSI core has some nasty limitations in AC97 mode. While most
 16  * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
 17  * one FIFO which combines all valid receive slots. We cannot even select
 18  * which slots we want to receive. The WM9712 with which this driver
 19  * was developed with always sends GPIO status data in slot 12 which
 20  * we receive in our (PCM-) data stream. The only chance we have is to
 21  * manually skip this data in the FIQ handler. With sampling rates different
 22  * from 48000Hz not every frame has valid receive data, so the ratio
 23  * between pcm data and GPIO status data changes. Our FIQ handler is not
 24  * able to handle this, hence this driver only works with 48000Hz sampling
 25  * rate.
 26  * Reading and writing AC97 registers is another challenge. The core
 27  * provides us status bits when the read register is updated with *another*
 28  * value. When we read the same register two times (and the register still
 29  * contains the same value) these status bits are not set. We work
 30  * around this by not polling these bits but only wait a fixed delay.
 31  *
 32  */
 33 
 34 #include <linux/clk.h>
 35 #include <linux/delay.h>
 36 #include <linux/device.h>
 37 #include <linux/dma-mapping.h>
 38 #include <linux/init.h>
 39 #include <linux/interrupt.h>
 40 #include <linux/module.h>
 41 #include <linux/platform_device.h>
 42 #include <linux/slab.h>
 43 
 44 #include <sound/core.h>
 45 #include <sound/initval.h>
 46 #include <sound/pcm.h>
 47 #include <sound/pcm_params.h>
 48 #include <sound/soc.h>
 49 
 50 #include <linux/platform_data/asoc-imx-ssi.h>
 51 
 52 #include "imx-ssi.h"
 53 
 54 #define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
 55 
 56 /*
 57  * SSI Network Mode or TDM slots configuration.
 58  * Should only be called when port is inactive (i.e. SSIEN = 0).
 59  */
 60 static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
 61         unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
 62 {
 63         struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
 64         u32 sccr;
 65 
 66         sccr = readl(ssi->base + SSI_STCCR);
 67         sccr &= ~SSI_STCCR_DC_MASK;
 68         sccr |= SSI_STCCR_DC(slots - 1);
 69         writel(sccr, ssi->base + SSI_STCCR);
 70 
 71         sccr = readl(ssi->base + SSI_SRCCR);
 72         sccr &= ~SSI_STCCR_DC_MASK;
 73         sccr |= SSI_STCCR_DC(slots - 1);
 74         writel(sccr, ssi->base + SSI_SRCCR);
 75 
 76         writel(tx_mask, ssi->base + SSI_STMSK);
 77         writel(rx_mask, ssi->base + SSI_SRMSK);
 78 
 79         return 0;
 80 }
 81 
 82 /*
 83  * SSI DAI format configuration.
 84  * Should only be called when port is inactive (i.e. SSIEN = 0).
 85  */
 86 static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 87 {
 88         struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
 89         u32 strcr = 0, scr;
 90 
 91         scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
 92 
 93         /* DAI mode */
 94         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 95         case SND_SOC_DAIFMT_I2S:
 96                 /* data on rising edge of bclk, frame low 1clk before data */
 97                 strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
 98                 scr |= SSI_SCR_NET;
 99                 if (ssi->flags & IMX_SSI_USE_I2S_SLAVE) {
100                         scr &= ~SSI_I2S_MODE_MASK;
101                         scr |= SSI_SCR_I2S_MODE_SLAVE;
102                 }
103                 break;
104         case SND_SOC_DAIFMT_LEFT_J:
105                 /* data on rising edge of bclk, frame high with data */
106                 strcr |= SSI_STCR_TXBIT0;
107                 break;
108         case SND_SOC_DAIFMT_DSP_B:
109                 /* data on rising edge of bclk, frame high with data */
110                 strcr |= SSI_STCR_TFSL | SSI_STCR_TXBIT0;
111                 break;
112         case SND_SOC_DAIFMT_DSP_A:
113                 /* data on rising edge of bclk, frame high 1clk before data */
114                 strcr |= SSI_STCR_TFSL | SSI_STCR_TXBIT0 | SSI_STCR_TEFS;
115                 break;
116         }
117 
118         /* DAI clock inversion */
119         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
120         case SND_SOC_DAIFMT_IB_IF:
121                 strcr |= SSI_STCR_TFSI;
122                 strcr &= ~SSI_STCR_TSCKP;
123                 break;
124         case SND_SOC_DAIFMT_IB_NF:
125                 strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
126                 break;
127         case SND_SOC_DAIFMT_NB_IF:
128                 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
129                 break;
130         case SND_SOC_DAIFMT_NB_NF:
131                 strcr &= ~SSI_STCR_TFSI;
132                 strcr |= SSI_STCR_TSCKP;
133                 break;
134         }
135 
136         /* DAI clock master masks */
137         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
138         case SND_SOC_DAIFMT_CBM_CFM:
139                 break;
140         default:
141                 /* Master mode not implemented, needs handling of clocks. */
142                 return -EINVAL;
143         }
144 
145         strcr |= SSI_STCR_TFEN0;
146 
147         if (ssi->flags & IMX_SSI_NET)
148                 scr |= SSI_SCR_NET;
149         if (ssi->flags & IMX_SSI_SYN)
150                 scr |= SSI_SCR_SYN;
151 
152         writel(strcr, ssi->base + SSI_STCR);
153         writel(strcr, ssi->base + SSI_SRCR);
154         writel(scr, ssi->base + SSI_SCR);
155 
156         return 0;
157 }
158 
159 /*
160  * SSI system clock configuration.
161  * Should only be called when port is inactive (i.e. SSIEN = 0).
162  */
163 static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
164                                   int clk_id, unsigned int freq, int dir)
165 {
166         struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
167         u32 scr;
168 
169         scr = readl(ssi->base + SSI_SCR);
170 
171         switch (clk_id) {
172         case IMX_SSP_SYS_CLK:
173                 if (dir == SND_SOC_CLOCK_OUT)
174                         scr |= SSI_SCR_SYS_CLK_EN;
175                 else
176                         scr &= ~SSI_SCR_SYS_CLK_EN;
177                 break;
178         default:
179                 return -EINVAL;
180         }
181 
182         writel(scr, ssi->base + SSI_SCR);
183 
184         return 0;
185 }
186 
187 /*
188  * SSI Clock dividers
189  * Should only be called when port is inactive (i.e. SSIEN = 0).
190  */
191 static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
192                                   int div_id, int div)
193 {
194         struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
195         u32 stccr, srccr;
196 
197         stccr = readl(ssi->base + SSI_STCCR);
198         srccr = readl(ssi->base + SSI_SRCCR);
199 
200         switch (div_id) {
201         case IMX_SSI_TX_DIV_2:
202                 stccr &= ~SSI_STCCR_DIV2;
203                 stccr |= div;
204                 break;
205         case IMX_SSI_TX_DIV_PSR:
206                 stccr &= ~SSI_STCCR_PSR;
207                 stccr |= div;
208                 break;
209         case IMX_SSI_TX_DIV_PM:
210                 stccr &= ~0xff;
211                 stccr |= SSI_STCCR_PM(div);
212                 break;
213         case IMX_SSI_RX_DIV_2:
214                 stccr &= ~SSI_STCCR_DIV2;
215                 stccr |= div;
216                 break;
217         case IMX_SSI_RX_DIV_PSR:
218                 stccr &= ~SSI_STCCR_PSR;
219                 stccr |= div;
220                 break;
221         case IMX_SSI_RX_DIV_PM:
222                 stccr &= ~0xff;
223                 stccr |= SSI_STCCR_PM(div);
224                 break;
225         default:
226                 return -EINVAL;
227         }
228 
229         writel(stccr, ssi->base + SSI_STCCR);
230         writel(srccr, ssi->base + SSI_SRCCR);
231 
232         return 0;
233 }
234 
235 /*
236  * Should only be called when port is inactive (i.e. SSIEN = 0),
237  * although can be called multiple times by upper layers.
238  */
239 static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
240                              struct snd_pcm_hw_params *params,
241                              struct snd_soc_dai *cpu_dai)
242 {
243         struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
244         u32 reg, sccr;
245 
246         /* Tx/Rx config */
247         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
248                 reg = SSI_STCCR;
249         else
250                 reg = SSI_SRCCR;
251 
252         if (ssi->flags & IMX_SSI_SYN)
253                 reg = SSI_STCCR;
254 
255         sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
256 
257         /* DAI data (word) size */
258         switch (params_format(params)) {
259         case SNDRV_PCM_FORMAT_S16_LE:
260                 sccr |= SSI_SRCCR_WL(16);
261                 break;
262         case SNDRV_PCM_FORMAT_S20_3LE:
263                 sccr |= SSI_SRCCR_WL(20);
264                 break;
265         case SNDRV_PCM_FORMAT_S24_LE:
266                 sccr |= SSI_SRCCR_WL(24);
267                 break;
268         }
269 
270         writel(sccr, ssi->base + reg);
271 
272         return 0;
273 }
274 
275 static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
276                 struct snd_soc_dai *dai)
277 {
278         struct imx_ssi *ssi = snd_soc_dai_get_drvdata(dai);
279         unsigned int sier_bits, sier;
280         unsigned int scr;
281 
282         scr = readl(ssi->base + SSI_SCR);
283         sier = readl(ssi->base + SSI_SIER);
284 
285         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
286                 if (ssi->flags & IMX_SSI_DMA)
287                         sier_bits = SSI_SIER_TDMAE;
288                 else
289                         sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
290         } else {
291                 if (ssi->flags & IMX_SSI_DMA)
292                         sier_bits = SSI_SIER_RDMAE;
293                 else
294                         sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
295         }
296 
297         switch (cmd) {
298         case SNDRV_PCM_TRIGGER_START:
299         case SNDRV_PCM_TRIGGER_RESUME:
300         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
301                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
302                         scr |= SSI_SCR_TE;
303                 else
304                         scr |= SSI_SCR_RE;
305                 sier |= sier_bits;
306 
307                 scr |= SSI_SCR_SSIEN;
308 
309                 break;
310 
311         case SNDRV_PCM_TRIGGER_STOP:
312         case SNDRV_PCM_TRIGGER_SUSPEND:
313         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
314                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
315                         scr &= ~SSI_SCR_TE;
316                 else
317                         scr &= ~SSI_SCR_RE;
318                 sier &= ~sier_bits;
319 
320                 if (!(scr & (SSI_SCR_TE | SSI_SCR_RE)))
321                         scr &= ~SSI_SCR_SSIEN;
322 
323                 break;
324         default:
325                 return -EINVAL;
326         }
327 
328         if (!(ssi->flags & IMX_SSI_USE_AC97))
329                 /* rx/tx are always enabled to access ac97 registers */
330                 writel(scr, ssi->base + SSI_SCR);
331 
332         writel(sier, ssi->base + SSI_SIER);
333 
334         return 0;
335 }
336 
337 static const struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
338         .hw_params      = imx_ssi_hw_params,
339         .set_fmt        = imx_ssi_set_dai_fmt,
340         .set_clkdiv     = imx_ssi_set_dai_clkdiv,
341         .set_sysclk     = imx_ssi_set_dai_sysclk,
342         .set_tdm_slot   = imx_ssi_set_dai_tdm_slot,
343         .trigger        = imx_ssi_trigger,
344 };
345 
346 static int imx_ssi_dai_probe(struct snd_soc_dai *dai)
347 {
348         struct imx_ssi *ssi = dev_get_drvdata(dai->dev);
349         uint32_t val;
350 
351         snd_soc_dai_set_drvdata(dai, ssi);
352 
353         val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.maxburst) |
354                 SSI_SFCSR_RFWM0(ssi->dma_params_rx.maxburst);
355         writel(val, ssi->base + SSI_SFCSR);
356 
357         /* Tx/Rx config */
358         dai->playback_dma_data = &ssi->dma_params_tx;
359         dai->capture_dma_data = &ssi->dma_params_rx;
360 
361         return 0;
362 }
363 
364 static struct snd_soc_dai_driver imx_ssi_dai = {
365         .probe = imx_ssi_dai_probe,
366         .playback = {
367                 .channels_min = 1,
368                 .channels_max = 2,
369                 .rates = SNDRV_PCM_RATE_8000_96000,
370                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
371         },
372         .capture = {
373                 .channels_min = 1,
374                 .channels_max = 2,
375                 .rates = SNDRV_PCM_RATE_8000_96000,
376                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
377         },
378         .ops = &imx_ssi_pcm_dai_ops,
379 };
380 
381 static struct snd_soc_dai_driver imx_ac97_dai = {
382         .probe = imx_ssi_dai_probe,
383         .ac97_control = 1,
384         .playback = {
385                 .stream_name = "AC97 Playback",
386                 .channels_min = 2,
387                 .channels_max = 2,
388                 .rates = SNDRV_PCM_RATE_8000_48000,
389                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
390         },
391         .capture = {
392                 .stream_name = "AC97 Capture",
393                 .channels_min = 2,
394                 .channels_max = 2,
395                 .rates = SNDRV_PCM_RATE_48000,
396                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
397         },
398         .ops = &imx_ssi_pcm_dai_ops,
399 };
400 
401 static const struct snd_soc_component_driver imx_component = {
402         .name           = DRV_NAME,
403 };
404 
405 static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
406 {
407         void __iomem *base = imx_ssi->base;
408 
409         writel(0x0, base + SSI_SCR);
410         writel(0x0, base + SSI_STCR);
411         writel(0x0, base + SSI_SRCR);
412 
413         writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
414 
415         writel(SSI_SFCSR_RFWM0(8) |
416                 SSI_SFCSR_TFWM0(8) |
417                 SSI_SFCSR_RFWM1(8) |
418                 SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
419 
420         writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
421         writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
422 
423         writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
424         writel(SSI_SOR_WAIT(3), base + SSI_SOR);
425 
426         writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
427                         SSI_SCR_TE | SSI_SCR_RE,
428                         base + SSI_SCR);
429 
430         writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
431         writel(0xff, base + SSI_SACCDIS);
432         writel(0x300, base + SSI_SACCEN);
433 }
434 
435 static struct imx_ssi *ac97_ssi;
436 
437 static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
438                 unsigned short val)
439 {
440         struct imx_ssi *imx_ssi = ac97_ssi;
441         void __iomem *base = imx_ssi->base;
442         unsigned int lreg;
443         unsigned int lval;
444 
445         if (reg > 0x7f)
446                 return;
447 
448         pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
449 
450         lreg = reg <<  12;
451         writel(lreg, base + SSI_SACADD);
452 
453         lval = val << 4;
454         writel(lval , base + SSI_SACDAT);
455 
456         writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
457         udelay(100);
458 }
459 
460 static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
461                 unsigned short reg)
462 {
463         struct imx_ssi *imx_ssi = ac97_ssi;
464         void __iomem *base = imx_ssi->base;
465 
466         unsigned short val = -1;
467         unsigned int lreg;
468 
469         lreg = (reg & 0x7f) <<  12 ;
470         writel(lreg, base + SSI_SACADD);
471         writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
472 
473         udelay(100);
474 
475         val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
476 
477         pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
478 
479         return val;
480 }
481 
482 static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
483 {
484         struct imx_ssi *imx_ssi = ac97_ssi;
485 
486         if (imx_ssi->ac97_reset)
487                 imx_ssi->ac97_reset(ac97);
488         /* First read sometimes fails, do a dummy read */
489         imx_ssi_ac97_read(ac97, 0);
490 }
491 
492 static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
493 {
494         struct imx_ssi *imx_ssi = ac97_ssi;
495 
496         if (imx_ssi->ac97_warm_reset)
497                 imx_ssi->ac97_warm_reset(ac97);
498 
499         /* First read sometimes fails, do a dummy read */
500         imx_ssi_ac97_read(ac97, 0);
501 }
502 
503 static struct snd_ac97_bus_ops imx_ssi_ac97_ops = {
504         .read           = imx_ssi_ac97_read,
505         .write          = imx_ssi_ac97_write,
506         .reset          = imx_ssi_ac97_reset,
507         .warm_reset     = imx_ssi_ac97_warm_reset
508 };
509 
510 static int imx_ssi_probe(struct platform_device *pdev)
511 {
512         struct resource *res;
513         struct imx_ssi *ssi;
514         struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
515         int ret = 0;
516         struct snd_soc_dai_driver *dai;
517 
518         ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
519         if (!ssi)
520                 return -ENOMEM;
521         dev_set_drvdata(&pdev->dev, ssi);
522 
523         if (pdata) {
524                 ssi->ac97_reset = pdata->ac97_reset;
525                 ssi->ac97_warm_reset = pdata->ac97_warm_reset;
526                 ssi->flags = pdata->flags;
527         }
528 
529         ssi->irq = platform_get_irq(pdev, 0);
530 
531         ssi->clk = devm_clk_get(&pdev->dev, NULL);
532         if (IS_ERR(ssi->clk)) {
533                 ret = PTR_ERR(ssi->clk);
534                 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
535                         ret);
536                 goto failed_clk;
537         }
538         ret = clk_prepare_enable(ssi->clk);
539         if (ret)
540                 goto failed_clk;
541 
542         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
543         ssi->base = devm_ioremap_resource(&pdev->dev, res);
544         if (IS_ERR(ssi->base)) {
545                 ret = PTR_ERR(ssi->base);
546                 goto failed_register;
547         }
548 
549         if (ssi->flags & IMX_SSI_USE_AC97) {
550                 if (ac97_ssi) {
551                         dev_err(&pdev->dev, "AC'97 SSI already registered\n");
552                         ret = -EBUSY;
553                         goto failed_register;
554                 }
555                 ac97_ssi = ssi;
556                 setup_channel_to_ac97(ssi);
557                 dai = &imx_ac97_dai;
558         } else
559                 dai = &imx_ssi_dai;
560 
561         writel(0x0, ssi->base + SSI_SIER);
562 
563         ssi->dma_params_rx.addr = res->start + SSI_SRX0;
564         ssi->dma_params_tx.addr = res->start + SSI_STX0;
565 
566         ssi->dma_params_tx.maxburst = 6;
567         ssi->dma_params_rx.maxburst = 4;
568 
569         ssi->dma_params_tx.filter_data = &ssi->filter_data_tx;
570         ssi->dma_params_rx.filter_data = &ssi->filter_data_rx;
571 
572         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
573         if (res) {
574                 imx_pcm_dma_params_init_data(&ssi->filter_data_tx, res->start,
575                         IMX_DMATYPE_SSI);
576         }
577 
578         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
579         if (res) {
580                 imx_pcm_dma_params_init_data(&ssi->filter_data_rx, res->start,
581                         IMX_DMATYPE_SSI);
582         }
583 
584         platform_set_drvdata(pdev, ssi);
585 
586         ret = snd_soc_set_ac97_ops(&imx_ssi_ac97_ops);
587         if (ret != 0) {
588                 dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
589                 goto failed_register;
590         }
591 
592         ret = snd_soc_register_component(&pdev->dev, &imx_component,
593                                          dai, 1);
594         if (ret) {
595                 dev_err(&pdev->dev, "register DAI failed\n");
596                 goto failed_register;
597         }
598 
599         ssi->fiq_params.irq = ssi->irq;
600         ssi->fiq_params.base = ssi->base;
601         ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
602         ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
603 
604         ssi->fiq_init = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
605         ssi->dma_init = imx_pcm_dma_init(pdev);
606 
607         if (ssi->fiq_init && ssi->dma_init) {
608                 ret = ssi->fiq_init;
609                 goto failed_pcm;
610         }
611 
612         return 0;
613 
614 failed_pcm:
615         snd_soc_unregister_component(&pdev->dev);
616 failed_register:
617         clk_disable_unprepare(ssi->clk);
618 failed_clk:
619         snd_soc_set_ac97_ops(NULL);
620 
621         return ret;
622 }
623 
624 static int imx_ssi_remove(struct platform_device *pdev)
625 {
626         struct imx_ssi *ssi = platform_get_drvdata(pdev);
627 
628         if (!ssi->fiq_init)
629                 imx_pcm_fiq_exit(pdev);
630 
631         snd_soc_unregister_component(&pdev->dev);
632 
633         if (ssi->flags & IMX_SSI_USE_AC97)
634                 ac97_ssi = NULL;
635 
636         clk_disable_unprepare(ssi->clk);
637         snd_soc_set_ac97_ops(NULL);
638 
639         return 0;
640 }
641 
642 static struct platform_driver imx_ssi_driver = {
643         .probe = imx_ssi_probe,
644         .remove = imx_ssi_remove,
645 
646         .driver = {
647                 .name = "imx-ssi",
648                 .owner = THIS_MODULE,
649         },
650 };
651 
652 module_platform_driver(imx_ssi_driver);
653 
654 /* Module information */
655 MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
656 MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
657 MODULE_LICENSE("GPL");
658 MODULE_ALIAS("platform:imx-ssi");
659 

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