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Linux/sound/soc/fsl/fsl_ssi.c

  1 /*
  2  * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
  3  *
  4  * Author: Timur Tabi <timur@freescale.com>
  5  *
  6  * Copyright 2007-2010 Freescale Semiconductor, Inc.
  7  *
  8  * This file is licensed under the terms of the GNU General Public License
  9  * version 2.  This program is licensed "as is" without any warranty of any
 10  * kind, whether express or implied.
 11  *
 12  *
 13  * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
 14  *
 15  * The i.MX SSI core has some nasty limitations in AC97 mode. While most
 16  * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
 17  * one FIFO which combines all valid receive slots. We cannot even select
 18  * which slots we want to receive. The WM9712 with which this driver
 19  * was developed with always sends GPIO status data in slot 12 which
 20  * we receive in our (PCM-) data stream. The only chance we have is to
 21  * manually skip this data in the FIQ handler. With sampling rates different
 22  * from 48000Hz not every frame has valid receive data, so the ratio
 23  * between pcm data and GPIO status data changes. Our FIQ handler is not
 24  * able to handle this, hence this driver only works with 48000Hz sampling
 25  * rate.
 26  * Reading and writing AC97 registers is another challenge. The core
 27  * provides us status bits when the read register is updated with *another*
 28  * value. When we read the same register two times (and the register still
 29  * contains the same value) these status bits are not set. We work
 30  * around this by not polling these bits but only wait a fixed delay.
 31  */
 32 
 33 #include <linux/init.h>
 34 #include <linux/io.h>
 35 #include <linux/module.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/clk.h>
 38 #include <linux/debugfs.h>
 39 #include <linux/device.h>
 40 #include <linux/delay.h>
 41 #include <linux/slab.h>
 42 #include <linux/spinlock.h>
 43 #include <linux/of_address.h>
 44 #include <linux/of_irq.h>
 45 #include <linux/of_platform.h>
 46 
 47 #include <sound/core.h>
 48 #include <sound/pcm.h>
 49 #include <sound/pcm_params.h>
 50 #include <sound/initval.h>
 51 #include <sound/soc.h>
 52 #include <sound/dmaengine_pcm.h>
 53 
 54 #include "fsl_ssi.h"
 55 #include "imx-pcm.h"
 56 
 57 #ifdef PPC
 58 #define read_ssi(addr)                   in_be32(addr)
 59 #define write_ssi(val, addr)             out_be32(addr, val)
 60 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
 61 #else
 62 #define read_ssi(addr)                   readl(addr)
 63 #define write_ssi(val, addr)             writel(val, addr)
 64 /*
 65  * FIXME: Proper locking should be added at write_ssi_mask caller level
 66  * to ensure this register read/modify/write sequence is race free.
 67  */
 68 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
 69 {
 70         u32 val = readl(addr);
 71         val = (val & ~clear) | set;
 72         writel(val, addr);
 73 }
 74 #endif
 75 
 76 /**
 77  * FSLSSI_I2S_RATES: sample rates supported by the I2S
 78  *
 79  * This driver currently only supports the SSI running in I2S slave mode,
 80  * which means the codec determines the sample rate.  Therefore, we tell
 81  * ALSA that we support all rates and let the codec driver decide what rates
 82  * are really supported.
 83  */
 84 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
 85 
 86 /**
 87  * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
 88  *
 89  * This driver currently only supports the SSI running in I2S slave mode.
 90  *
 91  * The SSI has a limitation in that the samples must be in the same byte
 92  * order as the host CPU.  This is because when multiple bytes are written
 93  * to the STX register, the bytes and bits must be written in the same
 94  * order.  The STX is a shift register, so all the bits need to be aligned
 95  * (bit-endianness must match byte-endianness).  Processors typically write
 96  * the bits within a byte in the same order that the bytes of a word are
 97  * written in.  So if the host CPU is big-endian, then only big-endian
 98  * samples will be written to STX properly.
 99  */
100 #ifdef __BIG_ENDIAN
101 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
102          SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
103          SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
104 #else
105 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
106          SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
107          SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
108 #endif
109 
110 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
111                 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
112                 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
113 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
114                 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
115                 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
116 #define FSLSSI_SISR_MASK (FSLSSI_SIER_DBG_RX_FLAGS | FSLSSI_SIER_DBG_TX_FLAGS)
117 
118 
119 enum fsl_ssi_type {
120         FSL_SSI_MCP8610,
121         FSL_SSI_MX21,
122         FSL_SSI_MX35,
123         FSL_SSI_MX51,
124 };
125 
126 struct fsl_ssi_reg_val {
127         u32 sier;
128         u32 srcr;
129         u32 stcr;
130         u32 scr;
131 };
132 
133 struct fsl_ssi_rxtx_reg_val {
134         struct fsl_ssi_reg_val rx;
135         struct fsl_ssi_reg_val tx;
136 };
137 
138 /**
139  * fsl_ssi_private: per-SSI private data
140  *
141  * @ssi: pointer to the SSI's registers
142  * @ssi_phys: physical address of the SSI registers
143  * @irq: IRQ of this SSI
144  * @playback: the number of playback streams opened
145  * @capture: the number of capture streams opened
146  * @cpu_dai: the CPU DAI for this device
147  * @dev_attr: the sysfs device attribute structure
148  * @stats: SSI statistics
149  * @name: name for this device
150  */
151 struct fsl_ssi_private {
152         struct ccsr_ssi __iomem *ssi;
153         dma_addr_t ssi_phys;
154         unsigned int irq;
155         unsigned int fifo_depth;
156         struct snd_soc_dai_driver cpu_dai_drv;
157         struct platform_device *pdev;
158 
159         enum fsl_ssi_type hw_type;
160         bool new_binding;
161         bool ssi_on_imx;
162         bool imx_ac97;
163         bool use_dma;
164         bool baudclk_locked;
165         bool irq_stats;
166         bool offline_config;
167         bool use_dual_fifo;
168         u8 i2s_mode;
169         spinlock_t baudclk_lock;
170         struct clk *baudclk;
171         struct clk *clk;
172         struct snd_dmaengine_dai_dma_data dma_params_tx;
173         struct snd_dmaengine_dai_dma_data dma_params_rx;
174         struct imx_dma_data filter_data_tx;
175         struct imx_dma_data filter_data_rx;
176         struct imx_pcm_fiq_params fiq_params;
177         /* Register values for rx/tx configuration */
178         struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
179 
180         struct {
181                 unsigned int rfrc;
182                 unsigned int tfrc;
183                 unsigned int cmdau;
184                 unsigned int cmddu;
185                 unsigned int rxt;
186                 unsigned int rdr1;
187                 unsigned int rdr0;
188                 unsigned int tde1;
189                 unsigned int tde0;
190                 unsigned int roe1;
191                 unsigned int roe0;
192                 unsigned int tue1;
193                 unsigned int tue0;
194                 unsigned int tfs;
195                 unsigned int rfs;
196                 unsigned int tls;
197                 unsigned int rls;
198                 unsigned int rff1;
199                 unsigned int rff0;
200                 unsigned int tfe1;
201                 unsigned int tfe0;
202         } stats;
203         struct dentry *dbg_dir;
204         struct dentry *dbg_stats;
205 
206         char name[1];
207 };
208 
209 static const struct of_device_id fsl_ssi_ids[] = {
210         { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610},
211         { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51},
212         { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35},
213         { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21},
214         {}
215 };
216 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
217 
218 /**
219  * fsl_ssi_isr: SSI interrupt handler
220  *
221  * Although it's possible to use the interrupt handler to send and receive
222  * data to/from the SSI, we use the DMA instead.  Programming is more
223  * complicated, but the performance is much better.
224  *
225  * This interrupt handler is used only to gather statistics.
226  *
227  * @irq: IRQ of the SSI device
228  * @dev_id: pointer to the ssi_private structure for this SSI device
229  */
230 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
231 {
232         struct fsl_ssi_private *ssi_private = dev_id;
233         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
234         irqreturn_t ret = IRQ_NONE;
235         __be32 sisr;
236         __be32 sisr2;
237         __be32 sisr_write_mask = 0;
238 
239         switch (ssi_private->hw_type) {
240         case FSL_SSI_MX21:
241                 sisr_write_mask = 0;
242                 break;
243 
244         case FSL_SSI_MCP8610:
245         case FSL_SSI_MX35:
246                 sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
247                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
248                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
249                 break;
250 
251         case FSL_SSI_MX51:
252                 sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
253                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
254                 break;
255         }
256 
257         /* We got an interrupt, so read the status register to see what we
258            were interrupted for.  We mask it with the Interrupt Enable register
259            so that we only check for events that we're interested in.
260          */
261         sisr = read_ssi(&ssi->sisr) & FSLSSI_SISR_MASK;
262 
263         if (sisr & CCSR_SSI_SISR_RFRC) {
264                 ssi_private->stats.rfrc++;
265                 ret = IRQ_HANDLED;
266         }
267 
268         if (sisr & CCSR_SSI_SISR_TFRC) {
269                 ssi_private->stats.tfrc++;
270                 ret = IRQ_HANDLED;
271         }
272 
273         if (sisr & CCSR_SSI_SISR_CMDAU) {
274                 ssi_private->stats.cmdau++;
275                 ret = IRQ_HANDLED;
276         }
277 
278         if (sisr & CCSR_SSI_SISR_CMDDU) {
279                 ssi_private->stats.cmddu++;
280                 ret = IRQ_HANDLED;
281         }
282 
283         if (sisr & CCSR_SSI_SISR_RXT) {
284                 ssi_private->stats.rxt++;
285                 ret = IRQ_HANDLED;
286         }
287 
288         if (sisr & CCSR_SSI_SISR_RDR1) {
289                 ssi_private->stats.rdr1++;
290                 ret = IRQ_HANDLED;
291         }
292 
293         if (sisr & CCSR_SSI_SISR_RDR0) {
294                 ssi_private->stats.rdr0++;
295                 ret = IRQ_HANDLED;
296         }
297 
298         if (sisr & CCSR_SSI_SISR_TDE1) {
299                 ssi_private->stats.tde1++;
300                 ret = IRQ_HANDLED;
301         }
302 
303         if (sisr & CCSR_SSI_SISR_TDE0) {
304                 ssi_private->stats.tde0++;
305                 ret = IRQ_HANDLED;
306         }
307 
308         if (sisr & CCSR_SSI_SISR_ROE1) {
309                 ssi_private->stats.roe1++;
310                 ret = IRQ_HANDLED;
311         }
312 
313         if (sisr & CCSR_SSI_SISR_ROE0) {
314                 ssi_private->stats.roe0++;
315                 ret = IRQ_HANDLED;
316         }
317 
318         if (sisr & CCSR_SSI_SISR_TUE1) {
319                 ssi_private->stats.tue1++;
320                 ret = IRQ_HANDLED;
321         }
322 
323         if (sisr & CCSR_SSI_SISR_TUE0) {
324                 ssi_private->stats.tue0++;
325                 ret = IRQ_HANDLED;
326         }
327 
328         if (sisr & CCSR_SSI_SISR_TFS) {
329                 ssi_private->stats.tfs++;
330                 ret = IRQ_HANDLED;
331         }
332 
333         if (sisr & CCSR_SSI_SISR_RFS) {
334                 ssi_private->stats.rfs++;
335                 ret = IRQ_HANDLED;
336         }
337 
338         if (sisr & CCSR_SSI_SISR_TLS) {
339                 ssi_private->stats.tls++;
340                 ret = IRQ_HANDLED;
341         }
342 
343         if (sisr & CCSR_SSI_SISR_RLS) {
344                 ssi_private->stats.rls++;
345                 ret = IRQ_HANDLED;
346         }
347 
348         if (sisr & CCSR_SSI_SISR_RFF1) {
349                 ssi_private->stats.rff1++;
350                 ret = IRQ_HANDLED;
351         }
352 
353         if (sisr & CCSR_SSI_SISR_RFF0) {
354                 ssi_private->stats.rff0++;
355                 ret = IRQ_HANDLED;
356         }
357 
358         if (sisr & CCSR_SSI_SISR_TFE1) {
359                 ssi_private->stats.tfe1++;
360                 ret = IRQ_HANDLED;
361         }
362 
363         if (sisr & CCSR_SSI_SISR_TFE0) {
364                 ssi_private->stats.tfe0++;
365                 ret = IRQ_HANDLED;
366         }
367 
368         sisr2 = sisr & sisr_write_mask;
369         /* Clear the bits that we set */
370         if (sisr2)
371                 write_ssi(sisr2, &ssi->sisr);
372 
373         return ret;
374 }
375 
376 #if IS_ENABLED(CONFIG_DEBUG_FS)
377 /* Show the statistics of a flag only if its interrupt is enabled.  The
378  * compiler will optimze this code to a no-op if the interrupt is not
379  * enabled.
380  */
381 #define SIER_SHOW(flag, name) \
382         do { \
383                 if (FSLSSI_SISR_MASK & CCSR_SSI_SIER_##flag) \
384                         seq_printf(s, #name "=%u\n", ssi_private->stats.name); \
385         } while (0)
386 
387 
388 /**
389  * fsl_sysfs_ssi_show: display SSI statistics
390  *
391  * Display the statistics for the current SSI device.  To avoid confusion,
392  * we only show those counts that are enabled.
393  */
394 static int fsl_ssi_stats_show(struct seq_file *s, void *unused)
395 {
396         struct fsl_ssi_private *ssi_private = s->private;
397 
398         SIER_SHOW(RFRC_EN, rfrc);
399         SIER_SHOW(TFRC_EN, tfrc);
400         SIER_SHOW(CMDAU_EN, cmdau);
401         SIER_SHOW(CMDDU_EN, cmddu);
402         SIER_SHOW(RXT_EN, rxt);
403         SIER_SHOW(RDR1_EN, rdr1);
404         SIER_SHOW(RDR0_EN, rdr0);
405         SIER_SHOW(TDE1_EN, tde1);
406         SIER_SHOW(TDE0_EN, tde0);
407         SIER_SHOW(ROE1_EN, roe1);
408         SIER_SHOW(ROE0_EN, roe0);
409         SIER_SHOW(TUE1_EN, tue1);
410         SIER_SHOW(TUE0_EN, tue0);
411         SIER_SHOW(TFS_EN, tfs);
412         SIER_SHOW(RFS_EN, rfs);
413         SIER_SHOW(TLS_EN, tls);
414         SIER_SHOW(RLS_EN, rls);
415         SIER_SHOW(RFF1_EN, rff1);
416         SIER_SHOW(RFF0_EN, rff0);
417         SIER_SHOW(TFE1_EN, tfe1);
418         SIER_SHOW(TFE0_EN, tfe0);
419 
420         return 0;
421 }
422 
423 static int fsl_ssi_stats_open(struct inode *inode, struct file *file)
424 {
425         return single_open(file, fsl_ssi_stats_show, inode->i_private);
426 }
427 
428 static const struct file_operations fsl_ssi_stats_ops = {
429         .open = fsl_ssi_stats_open,
430         .read = seq_read,
431         .llseek = seq_lseek,
432         .release = single_release,
433 };
434 
435 static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
436                 struct device *dev)
437 {
438         ssi_private->dbg_dir = debugfs_create_dir(dev_name(dev), NULL);
439         if (!ssi_private->dbg_dir)
440                 return -ENOMEM;
441 
442         ssi_private->dbg_stats = debugfs_create_file("stats", S_IRUGO,
443                         ssi_private->dbg_dir, ssi_private, &fsl_ssi_stats_ops);
444         if (!ssi_private->dbg_stats) {
445                 debugfs_remove(ssi_private->dbg_dir);
446                 return -ENOMEM;
447         }
448 
449         return 0;
450 }
451 
452 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
453 {
454         debugfs_remove(ssi_private->dbg_stats);
455         debugfs_remove(ssi_private->dbg_dir);
456 }
457 
458 #else
459 
460 static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
461                 struct device *dev)
462 {
463         return 0;
464 }
465 
466 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
467 {
468 }
469 
470 #endif /* IS_ENABLED(CONFIG_DEBUG_FS) */
471 
472 /*
473  * Enable/Disable all rx/tx config flags at once.
474  */
475 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
476                 bool enable)
477 {
478         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
479         struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
480 
481         if (enable) {
482                 write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier);
483                 write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr);
484                 write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr);
485         } else {
486                 write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0);
487                 write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0);
488                 write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0);
489         }
490 }
491 
492 /*
493  * Enable/Disable a ssi configuration. You have to pass either
494  * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
495  */
496 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
497                 struct fsl_ssi_reg_val *vals)
498 {
499         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
500         struct fsl_ssi_reg_val *avals;
501         u32 scr_val = read_ssi(&ssi->scr);
502         int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
503                                 !!(scr_val & CCSR_SSI_SCR_RE);
504 
505         /* Find the other direction values rx or tx which we do not want to
506          * modify */
507         if (&ssi_private->rxtx_reg_val.rx == vals)
508                 avals = &ssi_private->rxtx_reg_val.tx;
509         else
510                 avals = &ssi_private->rxtx_reg_val.rx;
511 
512         /* If vals should be disabled, start with disabling the unit */
513         if (!enable) {
514                 u32 scr = vals->scr & (vals->scr ^ avals->scr);
515                 write_ssi_mask(&ssi->scr, scr, 0);
516         }
517 
518         /*
519          * We are running on a SoC which does not support online SSI
520          * reconfiguration, so we have to enable all necessary flags at once
521          * even if we do not use them later (capture and playback configuration)
522          */
523         if (ssi_private->offline_config) {
524                 if ((enable && !nr_active_streams) ||
525                                 (!enable && nr_active_streams == 1))
526                         fsl_ssi_rxtx_config(ssi_private, enable);
527 
528                 goto config_done;
529         }
530 
531         /*
532          * Configure single direction units while the SSI unit is running
533          * (online configuration)
534          */
535         if (enable) {
536                 write_ssi_mask(&ssi->sier, 0, vals->sier);
537                 write_ssi_mask(&ssi->srcr, 0, vals->srcr);
538                 write_ssi_mask(&ssi->stcr, 0, vals->stcr);
539         } else {
540                 u32 sier;
541                 u32 srcr;
542                 u32 stcr;
543 
544                 /*
545                  * Disabling the necessary flags for one of rx/tx while the
546                  * other stream is active is a little bit more difficult. We
547                  * have to disable only those flags that differ between both
548                  * streams (rx XOR tx) and that are set in the stream that is
549                  * disabled now. Otherwise we could alter flags of the other
550                  * stream
551                  */
552 
553                 /* These assignments are simply vals without bits set in avals*/
554                 sier = vals->sier & (vals->sier ^ avals->sier);
555                 srcr = vals->srcr & (vals->srcr ^ avals->srcr);
556                 stcr = vals->stcr & (vals->stcr ^ avals->stcr);
557 
558                 write_ssi_mask(&ssi->srcr, srcr, 0);
559                 write_ssi_mask(&ssi->stcr, stcr, 0);
560                 write_ssi_mask(&ssi->sier, sier, 0);
561         }
562 
563 config_done:
564         /* Enabling of subunits is done after configuration */
565         if (enable)
566                 write_ssi_mask(&ssi->scr, 0, vals->scr);
567 }
568 
569 
570 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
571 {
572         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
573 }
574 
575 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
576 {
577         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
578 }
579 
580 /*
581  * Setup rx/tx register values used to enable/disable the streams. These will
582  * be used later in fsl_ssi_config to setup the streams without the need to
583  * check for all different SSI modes.
584  */
585 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
586 {
587         struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
588 
589         reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
590         reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
591         reg->rx.scr = 0;
592         reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
593         reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
594         reg->tx.scr = 0;
595 
596         if (!ssi_private->imx_ac97) {
597                 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
598                 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
599                 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
600                 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
601         }
602 
603         if (ssi_private->use_dma) {
604                 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
605                 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
606         } else {
607                 reg->rx.sier |= CCSR_SSI_SIER_RIE;
608                 reg->tx.sier |= CCSR_SSI_SIER_TIE;
609         }
610 
611         reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
612         reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
613 }
614 
615 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
616 {
617         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
618 
619         /*
620          * Setup the clock control register
621          */
622         write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
623                         &ssi->stccr);
624         write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
625                         &ssi->srccr);
626 
627         /*
628          * Enable AC97 mode and startup the SSI
629          */
630         write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
631                         &ssi->sacnt);
632         write_ssi(0xff, &ssi->saccdis);
633         write_ssi(0x300, &ssi->saccen);
634 
635         /*
636          * Enable SSI, Transmit and Receive. AC97 has to communicate with the
637          * codec before a stream is started.
638          */
639         write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
640                         CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
641 
642         write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
643 }
644 
645 static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
646 {
647         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
648         u8 wm;
649         int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
650 
651         fsl_ssi_setup_reg_vals(ssi_private);
652 
653         if (ssi_private->imx_ac97)
654                 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
655         else
656                 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
657 
658         /*
659          * Section 16.5 of the MPC8610 reference manual says that the SSI needs
660          * to be disabled before updating the registers we set here.
661          */
662         write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
663 
664         /*
665          * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
666          * enable the transmit and receive FIFO.
667          *
668          * FIXME: Little-endian samples require a different shift dir
669          */
670         write_ssi_mask(&ssi->scr,
671                 CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
672                 CCSR_SSI_SCR_TFR_CLK_DIS |
673                 ssi_private->i2s_mode |
674                 (synchronous ? CCSR_SSI_SCR_SYN : 0));
675 
676         write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFSI |
677                         CCSR_SSI_STCR_TEFS | CCSR_SSI_STCR_TSCKP, &ssi->stcr);
678 
679         write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFSI |
680                         CCSR_SSI_SRCR_REFS | CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
681 
682         /*
683          * The DC and PM bits are only used if the SSI is the clock master.
684          */
685 
686         /*
687          * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
688          * use FIFO 1. We program the transmit water to signal a DMA transfer
689          * if there are only two (or fewer) elements left in the FIFO. Two
690          * elements equals one frame (left channel, right channel). This value,
691          * however, depends on the depth of the transmit buffer.
692          *
693          * We set the watermark on the same level as the DMA burstsize.  For
694          * fiq it is probably better to use the biggest possible watermark
695          * size.
696          */
697         if (ssi_private->use_dma)
698                 wm = ssi_private->fifo_depth - 2;
699         else
700                 wm = ssi_private->fifo_depth;
701 
702         write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
703                 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
704                 &ssi->sfcsr);
705 
706         /*
707          * For ac97 interrupts are enabled with the startup of the substream
708          * because it is also running without an active substream. Normally SSI
709          * is only enabled when there is a substream.
710          */
711         if (ssi_private->imx_ac97)
712                 fsl_ssi_setup_ac97(ssi_private);
713 
714         /*
715          * Set a default slot number so that there is no need for those common
716          * cases like I2S mode to call the extra set_tdm_slot() any more.
717          */
718         if (!ssi_private->imx_ac97) {
719                 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
720                                 CCSR_SSI_SxCCR_DC(2));
721                 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
722                                 CCSR_SSI_SxCCR_DC(2));
723         }
724 
725         if (ssi_private->use_dual_fifo) {
726                 write_ssi_mask(&ssi->srcr, 0, CCSR_SSI_SRCR_RFEN1);
727                 write_ssi_mask(&ssi->stcr, 0, CCSR_SSI_STCR_TFEN1);
728                 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_TCH_EN);
729         }
730 
731         return 0;
732 }
733 
734 
735 /**
736  * fsl_ssi_startup: create a new substream
737  *
738  * This is the first function called when a stream is opened.
739  *
740  * If this is the first stream open, then grab the IRQ and program most of
741  * the SSI registers.
742  */
743 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
744                            struct snd_soc_dai *dai)
745 {
746         struct snd_soc_pcm_runtime *rtd = substream->private_data;
747         struct fsl_ssi_private *ssi_private =
748                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
749         unsigned long flags;
750 
751         /* First, we only do fsl_ssi_setup() when SSI is going to be active.
752          * Second, fsl_ssi_setup was already called by ac97_init earlier if
753          * the driver is in ac97 mode.
754          */
755         if (!dai->active && !ssi_private->imx_ac97) {
756                 fsl_ssi_setup(ssi_private);
757                 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
758                 ssi_private->baudclk_locked = false;
759                 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
760         }
761 
762         /* When using dual fifo mode, it is safer to ensure an even period
763          * size. If appearing to an odd number while DMA always starts its
764          * task from fifo0, fifo1 would be neglected at the end of each
765          * period. But SSI would still access fifo1 with an invalid data.
766          */
767         if (ssi_private->use_dual_fifo)
768                 snd_pcm_hw_constraint_step(substream->runtime, 0,
769                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
770 
771         return 0;
772 }
773 
774 /**
775  * fsl_ssi_hw_params - program the sample size
776  *
777  * Most of the SSI registers have been programmed in the startup function,
778  * but the word length must be programmed here.  Unfortunately, programming
779  * the SxCCR.WL bits requires the SSI to be temporarily disabled.  This can
780  * cause a problem with supporting simultaneous playback and capture.  If
781  * the SSI is already playing a stream, then that stream may be temporarily
782  * stopped when you start capture.
783  *
784  * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
785  * clock master.
786  */
787 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
788         struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
789 {
790         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
791         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
792         unsigned int channels = params_channels(hw_params);
793         unsigned int sample_size =
794                 snd_pcm_format_width(params_format(hw_params));
795         u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
796         int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
797 
798         /*
799          * If we're in synchronous mode, and the SSI is already enabled,
800          * then STCCR is already set properly.
801          */
802         if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
803                 return 0;
804 
805         /*
806          * FIXME: The documentation says that SxCCR[WL] should not be
807          * modified while the SSI is enabled.  The only time this can
808          * happen is if we're trying to do simultaneous playback and
809          * capture in asynchronous mode.  Unfortunately, I have been enable
810          * to get that to work at all on the P1022DS.  Therefore, we don't
811          * bother to disable/enable the SSI when setting SxCCR[WL], because
812          * the SSI will stop anyway.  Maybe one day, this will get fixed.
813          */
814 
815         /* In synchronous mode, the SSI uses STCCR for capture */
816         if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
817             ssi_private->cpu_dai_drv.symmetric_rates)
818                 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
819         else
820                 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
821 
822         if (!ssi_private->imx_ac97)
823                 write_ssi_mask(&ssi->scr,
824                                 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
825                                 channels == 1 ? 0 : ssi_private->i2s_mode);
826 
827         return 0;
828 }
829 
830 /**
831  * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
832  */
833 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
834 {
835         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
836         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
837         u32 strcr = 0, stcr, srcr, scr, mask;
838 
839         scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
840         scr |= CCSR_SSI_SCR_NET;
841 
842         mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
843                 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
844                 CCSR_SSI_STCR_TEFS;
845         stcr = read_ssi(&ssi->stcr) & ~mask;
846         srcr = read_ssi(&ssi->srcr) & ~mask;
847 
848         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
849         case SND_SOC_DAIFMT_I2S:
850                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
851                 case SND_SOC_DAIFMT_CBS_CFS:
852                         ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_MASTER;
853                         break;
854                 case SND_SOC_DAIFMT_CBM_CFM:
855                         ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
856                         break;
857                 default:
858                         return -EINVAL;
859                 }
860                 scr |= ssi_private->i2s_mode;
861 
862                 /* Data on rising edge of bclk, frame low, 1clk before data */
863                 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
864                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
865                 break;
866         case SND_SOC_DAIFMT_LEFT_J:
867                 /* Data on rising edge of bclk, frame high */
868                 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
869                 break;
870         case SND_SOC_DAIFMT_DSP_A:
871                 /* Data on rising edge of bclk, frame high, 1clk before data */
872                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
873                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
874                 break;
875         case SND_SOC_DAIFMT_DSP_B:
876                 /* Data on rising edge of bclk, frame high */
877                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
878                         CCSR_SSI_STCR_TXBIT0;
879                 break;
880         default:
881                 return -EINVAL;
882         }
883 
884         /* DAI clock inversion */
885         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
886         case SND_SOC_DAIFMT_NB_NF:
887                 /* Nothing to do for both normal cases */
888                 break;
889         case SND_SOC_DAIFMT_IB_NF:
890                 /* Invert bit clock */
891                 strcr ^= CCSR_SSI_STCR_TSCKP;
892                 break;
893         case SND_SOC_DAIFMT_NB_IF:
894                 /* Invert frame clock */
895                 strcr ^= CCSR_SSI_STCR_TFSI;
896                 break;
897         case SND_SOC_DAIFMT_IB_IF:
898                 /* Invert both clocks */
899                 strcr ^= CCSR_SSI_STCR_TSCKP;
900                 strcr ^= CCSR_SSI_STCR_TFSI;
901                 break;
902         default:
903                 return -EINVAL;
904         }
905 
906         /* DAI clock master masks */
907         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
908         case SND_SOC_DAIFMT_CBS_CFS:
909                 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
910                 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
911                 break;
912         case SND_SOC_DAIFMT_CBM_CFM:
913                 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
914                 break;
915         default:
916                 return -EINVAL;
917         }
918 
919         stcr |= strcr;
920         srcr |= strcr;
921 
922         if (ssi_private->cpu_dai_drv.symmetric_rates) {
923                 /* Need to clear RXDIR when using SYNC mode */
924                 srcr &= ~CCSR_SSI_SRCR_RXDIR;
925                 scr |= CCSR_SSI_SCR_SYN;
926         }
927 
928         write_ssi(stcr, &ssi->stcr);
929         write_ssi(srcr, &ssi->srcr);
930         write_ssi(scr, &ssi->scr);
931 
932         return 0;
933 }
934 
935 /**
936  * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
937  *
938  * Note: This function can be only called when using SSI as DAI master
939  *
940  * Quick instruction for parameters:
941  * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
942  * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
943  */
944 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
945                                   int clk_id, unsigned int freq, int dir)
946 {
947         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
948         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
949         int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
950         u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
951         unsigned long flags, clkrate, baudrate, tmprate;
952         u64 sub, savesub = 100000;
953 
954         /* Don't apply it to any non-baudclk circumstance */
955         if (IS_ERR(ssi_private->baudclk))
956                 return -EINVAL;
957 
958         /* It should be already enough to divide clock by setting pm alone */
959         psr = 0;
960         div2 = 0;
961 
962         factor = (div2 + 1) * (7 * psr + 1) * 2;
963 
964         for (i = 0; i < 255; i++) {
965                 /* The bclk rate must be smaller than 1/5 sysclk rate */
966                 if (factor * (i + 1) < 5)
967                         continue;
968 
969                 tmprate = freq * factor * (i + 2);
970                 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
971 
972                 do_div(clkrate, factor);
973                 afreq = (u32)clkrate / (i + 1);
974 
975                 if (freq == afreq)
976                         sub = 0;
977                 else if (freq / afreq == 1)
978                         sub = freq - afreq;
979                 else if (afreq / freq == 1)
980                         sub = afreq - freq;
981                 else
982                         continue;
983 
984                 /* Calculate the fraction */
985                 sub *= 100000;
986                 do_div(sub, freq);
987 
988                 if (sub < savesub) {
989                         baudrate = tmprate;
990                         savesub = sub;
991                         pm = i;
992                 }
993 
994                 /* We are lucky */
995                 if (savesub == 0)
996                         break;
997         }
998 
999         /* No proper pm found if it is still remaining the initial value */
1000         if (pm == 999) {
1001                 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
1002                 return -EINVAL;
1003         }
1004 
1005         stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
1006                 (psr ? CCSR_SSI_SxCCR_PSR : 0);
1007         mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR;
1008 
1009         if (dir == SND_SOC_CLOCK_OUT || synchronous)
1010                 write_ssi_mask(&ssi->stccr, mask, stccr);
1011         else
1012                 write_ssi_mask(&ssi->srccr, mask, stccr);
1013 
1014         spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
1015         if (!ssi_private->baudclk_locked) {
1016                 ret = clk_set_rate(ssi_private->baudclk, baudrate);
1017                 if (ret) {
1018                         spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
1019                         dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
1020                         return -EINVAL;
1021                 }
1022                 ssi_private->baudclk_locked = true;
1023         }
1024         spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
1025 
1026         return 0;
1027 }
1028 
1029 /**
1030  * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1031  *
1032  * Note: This function can be only called when using SSI as DAI master
1033  */
1034 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1035                                 u32 rx_mask, int slots, int slot_width)
1036 {
1037         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1038         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
1039         u32 val;
1040 
1041         /* The slot number should be >= 2 if using Network mode or I2S mode */
1042         val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
1043         if (val && slots < 2) {
1044                 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1045                 return -EINVAL;
1046         }
1047 
1048         write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
1049                         CCSR_SSI_SxCCR_DC(slots));
1050         write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
1051                         CCSR_SSI_SxCCR_DC(slots));
1052 
1053         /* The register SxMSKs needs SSI to provide essential clock due to
1054          * hardware design. So we here temporarily enable SSI to set them.
1055          */
1056         val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
1057         write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
1058 
1059         write_ssi(tx_mask, &ssi->stmsk);
1060         write_ssi(rx_mask, &ssi->srmsk);
1061 
1062         write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);
1063 
1064         return 0;
1065 }
1066 
1067 /**
1068  * fsl_ssi_trigger: start and stop the DMA transfer.
1069  *
1070  * This function is called by ALSA to start, stop, pause, and resume the DMA
1071  * transfer of data.
1072  *
1073  * The DMA channel is in external master start and pause mode, which
1074  * means the SSI completely controls the flow of data.
1075  */
1076 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1077                            struct snd_soc_dai *dai)
1078 {
1079         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1080         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1081         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
1082         unsigned long flags;
1083 
1084         switch (cmd) {
1085         case SNDRV_PCM_TRIGGER_START:
1086         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1087                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1088                         fsl_ssi_tx_config(ssi_private, true);
1089                 else
1090                         fsl_ssi_rx_config(ssi_private, true);
1091                 break;
1092 
1093         case SNDRV_PCM_TRIGGER_STOP:
1094         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1095                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1096                         fsl_ssi_tx_config(ssi_private, false);
1097                 else
1098                         fsl_ssi_rx_config(ssi_private, false);
1099 
1100                 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
1101                                         (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
1102                         spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
1103                         ssi_private->baudclk_locked = false;
1104                         spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
1105                 }
1106                 break;
1107 
1108         default:
1109                 return -EINVAL;
1110         }
1111 
1112         if (ssi_private->imx_ac97) {
1113                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1114                         write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
1115                 else
1116                         write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
1117         }
1118 
1119         return 0;
1120 }
1121 
1122 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1123 {
1124         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1125 
1126         if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
1127                 dai->playback_dma_data = &ssi_private->dma_params_tx;
1128                 dai->capture_dma_data = &ssi_private->dma_params_rx;
1129         }
1130 
1131         return 0;
1132 }
1133 
1134 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1135         .startup        = fsl_ssi_startup,
1136         .hw_params      = fsl_ssi_hw_params,
1137         .set_fmt        = fsl_ssi_set_dai_fmt,
1138         .set_sysclk     = fsl_ssi_set_dai_sysclk,
1139         .set_tdm_slot   = fsl_ssi_set_dai_tdm_slot,
1140         .trigger        = fsl_ssi_trigger,
1141 };
1142 
1143 /* Template for the CPU dai driver structure */
1144 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1145         .probe = fsl_ssi_dai_probe,
1146         .playback = {
1147                 .channels_min = 1,
1148                 .channels_max = 2,
1149                 .rates = FSLSSI_I2S_RATES,
1150                 .formats = FSLSSI_I2S_FORMATS,
1151         },
1152         .capture = {
1153                 .channels_min = 1,
1154                 .channels_max = 2,
1155                 .rates = FSLSSI_I2S_RATES,
1156                 .formats = FSLSSI_I2S_FORMATS,
1157         },
1158         .ops = &fsl_ssi_dai_ops,
1159 };
1160 
1161 static const struct snd_soc_component_driver fsl_ssi_component = {
1162         .name           = "fsl-ssi",
1163 };
1164 
1165 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1166         .ac97_control = 1,
1167         .playback = {
1168                 .stream_name = "AC97 Playback",
1169                 .channels_min = 2,
1170                 .channels_max = 2,
1171                 .rates = SNDRV_PCM_RATE_8000_48000,
1172                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1173         },
1174         .capture = {
1175                 .stream_name = "AC97 Capture",
1176                 .channels_min = 2,
1177                 .channels_max = 2,
1178                 .rates = SNDRV_PCM_RATE_48000,
1179                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1180         },
1181         .ops = &fsl_ssi_dai_ops,
1182 };
1183 
1184 
1185 static struct fsl_ssi_private *fsl_ac97_data;
1186 
1187 static void fsl_ssi_ac97_init(void)
1188 {
1189         fsl_ssi_setup(fsl_ac97_data);
1190 }
1191 
1192 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1193                 unsigned short val)
1194 {
1195         struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1196         unsigned int lreg;
1197         unsigned int lval;
1198 
1199         if (reg > 0x7f)
1200                 return;
1201 
1202 
1203         lreg = reg <<  12;
1204         write_ssi(lreg, &ssi->sacadd);
1205 
1206         lval = val << 4;
1207         write_ssi(lval , &ssi->sacdat);
1208 
1209         write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1210                         CCSR_SSI_SACNT_WR);
1211         udelay(100);
1212 }
1213 
1214 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1215                 unsigned short reg)
1216 {
1217         struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1218 
1219         unsigned short val = -1;
1220         unsigned int lreg;
1221 
1222         lreg = (reg & 0x7f) <<  12;
1223         write_ssi(lreg, &ssi->sacadd);
1224         write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1225                         CCSR_SSI_SACNT_RD);
1226 
1227         udelay(100);
1228 
1229         val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
1230 
1231         return val;
1232 }
1233 
1234 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1235         .read           = fsl_ssi_ac97_read,
1236         .write          = fsl_ssi_ac97_write,
1237 };
1238 
1239 /**
1240  * Make every character in a string lower-case
1241  */
1242 static void make_lowercase(char *s)
1243 {
1244         char *p = s;
1245         char c;
1246 
1247         while ((c = *p)) {
1248                 if ((c >= 'A') && (c <= 'Z'))
1249                         *p = c + ('a' - 'A');
1250                 p++;
1251         }
1252 }
1253 
1254 static int fsl_ssi_probe(struct platform_device *pdev)
1255 {
1256         struct fsl_ssi_private *ssi_private;
1257         int ret = 0;
1258         struct device_attribute *dev_attr = NULL;
1259         struct device_node *np = pdev->dev.of_node;
1260         const struct of_device_id *of_id;
1261         enum fsl_ssi_type hw_type;
1262         const char *p, *sprop;
1263         const uint32_t *iprop;
1264         struct resource res;
1265         char name[64];
1266         bool shared;
1267         bool ac97 = false;
1268 
1269         /* SSIs that are not connected on the board should have a
1270          *      status = "disabled"
1271          * property in their device tree nodes.
1272          */
1273         if (!of_device_is_available(np))
1274                 return -ENODEV;
1275 
1276         of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1277         if (!of_id)
1278                 return -EINVAL;
1279         hw_type = (enum fsl_ssi_type) of_id->data;
1280 
1281         sprop = of_get_property(np, "fsl,mode", NULL);
1282         if (!sprop) {
1283                 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
1284                 return -EINVAL;
1285         }
1286         if (!strcmp(sprop, "ac97-slave"))
1287                 ac97 = true;
1288 
1289         /* The DAI name is the last part of the full name of the node. */
1290         p = strrchr(np->full_name, '/') + 1;
1291         ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
1292                               GFP_KERNEL);
1293         if (!ssi_private) {
1294                 dev_err(&pdev->dev, "could not allocate DAI object\n");
1295                 return -ENOMEM;
1296         }
1297 
1298         strcpy(ssi_private->name, p);
1299 
1300         ssi_private->use_dma = !of_property_read_bool(np,
1301                         "fsl,fiq-stream-filter");
1302         ssi_private->hw_type = hw_type;
1303 
1304         if (ac97) {
1305                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1306                                 sizeof(fsl_ssi_ac97_dai));
1307 
1308                 fsl_ac97_data = ssi_private;
1309                 ssi_private->imx_ac97 = true;
1310 
1311                 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1312         } else {
1313                 /* Initialize this copy of the CPU DAI driver structure */
1314                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1315                        sizeof(fsl_ssi_dai_template));
1316         }
1317         ssi_private->cpu_dai_drv.name = ssi_private->name;
1318 
1319         /* Get the addresses and IRQ */
1320         ret = of_address_to_resource(np, 0, &res);
1321         if (ret) {
1322                 dev_err(&pdev->dev, "could not determine device resources\n");
1323                 return ret;
1324         }
1325         ssi_private->ssi = of_iomap(np, 0);
1326         if (!ssi_private->ssi) {
1327                 dev_err(&pdev->dev, "could not map device resources\n");
1328                 return -ENOMEM;
1329         }
1330         ssi_private->ssi_phys = res.start;
1331 
1332         ssi_private->irq = irq_of_parse_and_map(np, 0);
1333         if (!ssi_private->irq) {
1334                 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1335                 return -ENXIO;
1336         }
1337 
1338         /* Are the RX and the TX clocks locked? */
1339         if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1340                 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1341                 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1342                 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1343         }
1344 
1345         /* Determine the FIFO depth. */
1346         iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1347         if (iprop)
1348                 ssi_private->fifo_depth = be32_to_cpup(iprop);
1349         else
1350                 /* Older 8610 DTs didn't have the fifo-depth property */
1351                 ssi_private->fifo_depth = 8;
1352 
1353         ssi_private->baudclk_locked = false;
1354         spin_lock_init(&ssi_private->baudclk_lock);
1355 
1356         /*
1357          * imx51 and later SoCs have a slightly different IP that allows the
1358          * SSI configuration while the SSI unit is running.
1359          *
1360          * More important, it is necessary on those SoCs to configure the
1361          * sperate TX/RX DMA bits just before starting the stream
1362          * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
1363          * sends any DMA requests to the SDMA unit, otherwise it is not defined
1364          * how the SDMA unit handles the DMA request.
1365          *
1366          * SDMA units are present on devices starting at imx35 but the imx35
1367          * reference manual states that the DMA bits should not be changed
1368          * while the SSI unit is running (SSIEN). So we support the necessary
1369          * online configuration of fsl-ssi starting at imx51.
1370          */
1371         switch (hw_type) {
1372         case FSL_SSI_MCP8610:
1373         case FSL_SSI_MX21:
1374         case FSL_SSI_MX35:
1375                 ssi_private->offline_config = true;
1376                 break;
1377         case FSL_SSI_MX51:
1378                 ssi_private->offline_config = false;
1379                 break;
1380         }
1381 
1382         if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 ||
1383                         hw_type == FSL_SSI_MX35) {
1384                 u32 dma_events[2], dmas[4];
1385                 ssi_private->ssi_on_imx = true;
1386 
1387                 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1388                 if (IS_ERR(ssi_private->clk)) {
1389                         ret = PTR_ERR(ssi_private->clk);
1390                         dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1391                         goto error_irqmap;
1392                 }
1393                 ret = clk_prepare_enable(ssi_private->clk);
1394                 if (ret) {
1395                         dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
1396                                 ret);
1397                         goto error_irqmap;
1398                 }
1399 
1400                 /* For those SLAVE implementations, we ingore non-baudclk cases
1401                  * and, instead, abandon MASTER mode that needs baud clock.
1402                  */
1403                 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1404                 if (IS_ERR(ssi_private->baudclk))
1405                         dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1406                                  PTR_ERR(ssi_private->baudclk));
1407                 else
1408                         clk_prepare_enable(ssi_private->baudclk);
1409 
1410                 /*
1411                  * We have burstsize be "fifo_depth - 2" to match the SSI
1412                  * watermark setting in fsl_ssi_startup().
1413                  */
1414                 ssi_private->dma_params_tx.maxburst =
1415                         ssi_private->fifo_depth - 2;
1416                 ssi_private->dma_params_rx.maxburst =
1417                         ssi_private->fifo_depth - 2;
1418                 ssi_private->dma_params_tx.addr =
1419                         ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
1420                 ssi_private->dma_params_rx.addr =
1421                         ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
1422                 ssi_private->dma_params_tx.filter_data =
1423                         &ssi_private->filter_data_tx;
1424                 ssi_private->dma_params_rx.filter_data =
1425                         &ssi_private->filter_data_rx;
1426                 if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
1427                                 ssi_private->use_dma) {
1428                         /*
1429                          * FIXME: This is a temporary solution until all
1430                          * necessary dma drivers support the generic dma
1431                          * bindings.
1432                          */
1433                         ret = of_property_read_u32_array(pdev->dev.of_node,
1434                                         "fsl,ssi-dma-events", dma_events, 2);
1435                         if (ret && ssi_private->use_dma) {
1436                                 dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
1437                                 goto error_clk;
1438                         }
1439                 }
1440                 /* Should this be merge with the above? */
1441                 if (!of_property_read_u32_array(pdev->dev.of_node, "dmas", dmas, 4)
1442                                 && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1443                         ssi_private->use_dual_fifo = true;
1444                         /* When using dual fifo mode, we need to keep watermark
1445                          * as even numbers due to dma script limitation.
1446                          */
1447                         ssi_private->dma_params_tx.maxburst &= ~0x1;
1448                         ssi_private->dma_params_rx.maxburst &= ~0x1;
1449                 }
1450 
1451                 shared = of_device_is_compatible(of_get_parent(np),
1452                             "fsl,spba-bus");
1453 
1454                 imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1455                         dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1456                 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1457                         dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1458         }
1459 
1460         /*
1461          * Enable interrupts only for MCP8610 and MX51. The other MXs have
1462          * different writeable interrupt status registers.
1463          */
1464         if (ssi_private->use_dma) {
1465                 /* The 'name' should not have any slashes in it. */
1466                 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1467                                         fsl_ssi_isr, 0, ssi_private->name,
1468                                         ssi_private);
1469                 ssi_private->irq_stats = true;
1470                 if (ret < 0) {
1471                         dev_err(&pdev->dev, "could not claim irq %u\n",
1472                                         ssi_private->irq);
1473                         goto error_clk;
1474                 }
1475         }
1476 
1477         /* Register with ASoC */
1478         dev_set_drvdata(&pdev->dev, ssi_private);
1479 
1480         ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1481                                          &ssi_private->cpu_dai_drv, 1);
1482         if (ret) {
1483                 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1484                 goto error_dev;
1485         }
1486 
1487         ret = fsl_ssi_debugfs_create(ssi_private, &pdev->dev);
1488         if (ret)
1489                 goto error_dbgfs;
1490 
1491         if (ssi_private->ssi_on_imx) {
1492                 if (!ssi_private->use_dma) {
1493 
1494                         /*
1495                          * Some boards use an incompatible codec. To get it
1496                          * working, we are using imx-fiq-pcm-audio, that
1497                          * can handle those codecs. DMA is not possible in this
1498                          * situation.
1499                          */
1500 
1501                         ssi_private->fiq_params.irq = ssi_private->irq;
1502                         ssi_private->fiq_params.base = ssi_private->ssi;
1503                         ssi_private->fiq_params.dma_params_rx =
1504                                 &ssi_private->dma_params_rx;
1505                         ssi_private->fiq_params.dma_params_tx =
1506                                 &ssi_private->dma_params_tx;
1507 
1508                         ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1509                         if (ret)
1510                                 goto error_pcm;
1511                 } else {
1512                         ret = imx_pcm_dma_init(pdev);
1513                         if (ret)
1514                                 goto error_pcm;
1515                 }
1516         }
1517 
1518         /*
1519          * If codec-handle property is missing from SSI node, we assume
1520          * that the machine driver uses new binding which does not require
1521          * SSI driver to trigger machine driver's probe.
1522          */
1523         if (!of_get_property(np, "codec-handle", NULL)) {
1524                 ssi_private->new_binding = true;
1525                 goto done;
1526         }
1527 
1528         /* Trigger the machine driver's probe function.  The platform driver
1529          * name of the machine driver is taken from /compatible property of the
1530          * device tree.  We also pass the address of the CPU DAI driver
1531          * structure.
1532          */
1533         sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1534         /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1535         p = strrchr(sprop, ',');
1536         if (p)
1537                 sprop = p + 1;
1538         snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1539         make_lowercase(name);
1540 
1541         ssi_private->pdev =
1542                 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1543         if (IS_ERR(ssi_private->pdev)) {
1544                 ret = PTR_ERR(ssi_private->pdev);
1545                 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1546                 goto error_dai;
1547         }
1548 
1549 done:
1550         if (ssi_private->imx_ac97)
1551                 fsl_ssi_ac97_init();
1552 
1553         return 0;
1554 
1555 error_dai:
1556         if (ssi_private->ssi_on_imx && !ssi_private->use_dma)
1557                 imx_pcm_fiq_exit(pdev);
1558 
1559 error_pcm:
1560         fsl_ssi_debugfs_remove(ssi_private);
1561 
1562 error_dbgfs:
1563         snd_soc_unregister_component(&pdev->dev);
1564 
1565 error_dev:
1566         device_remove_file(&pdev->dev, dev_attr);
1567 
1568 error_clk:
1569         if (ssi_private->ssi_on_imx) {
1570                 if (!IS_ERR(ssi_private->baudclk))
1571                         clk_disable_unprepare(ssi_private->baudclk);
1572                 clk_disable_unprepare(ssi_private->clk);
1573         }
1574 
1575 error_irqmap:
1576         if (ssi_private->irq_stats)
1577                 irq_dispose_mapping(ssi_private->irq);
1578 
1579         return ret;
1580 }
1581 
1582 static int fsl_ssi_remove(struct platform_device *pdev)
1583 {
1584         struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1585 
1586         fsl_ssi_debugfs_remove(ssi_private);
1587 
1588         if (!ssi_private->new_binding)
1589                 platform_device_unregister(ssi_private->pdev);
1590         snd_soc_unregister_component(&pdev->dev);
1591         if (ssi_private->ssi_on_imx) {
1592                 if (!IS_ERR(ssi_private->baudclk))
1593                         clk_disable_unprepare(ssi_private->baudclk);
1594                 clk_disable_unprepare(ssi_private->clk);
1595         }
1596         if (ssi_private->irq_stats)
1597                 irq_dispose_mapping(ssi_private->irq);
1598 
1599         return 0;
1600 }
1601 
1602 static struct platform_driver fsl_ssi_driver = {
1603         .driver = {
1604                 .name = "fsl-ssi-dai",
1605                 .owner = THIS_MODULE,
1606                 .of_match_table = fsl_ssi_ids,
1607         },
1608         .probe = fsl_ssi_probe,
1609         .remove = fsl_ssi_remove,
1610 };
1611 
1612 module_platform_driver(fsl_ssi_driver);
1613 
1614 MODULE_ALIAS("platform:fsl-ssi-dai");
1615 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1616 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1617 MODULE_LICENSE("GPL v2");
1618 

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