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Linux/sound/soc/fsl/fsl_ssi.c

  1 /*
  2  * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
  3  *
  4  * Author: Timur Tabi <timur@freescale.com>
  5  *
  6  * Copyright 2007-2010 Freescale Semiconductor, Inc.
  7  *
  8  * This file is licensed under the terms of the GNU General Public License
  9  * version 2.  This program is licensed "as is" without any warranty of any
 10  * kind, whether express or implied.
 11  *
 12  *
 13  * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
 14  *
 15  * The i.MX SSI core has some nasty limitations in AC97 mode. While most
 16  * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
 17  * one FIFO which combines all valid receive slots. We cannot even select
 18  * which slots we want to receive. The WM9712 with which this driver
 19  * was developed with always sends GPIO status data in slot 12 which
 20  * we receive in our (PCM-) data stream. The only chance we have is to
 21  * manually skip this data in the FIQ handler. With sampling rates different
 22  * from 48000Hz not every frame has valid receive data, so the ratio
 23  * between pcm data and GPIO status data changes. Our FIQ handler is not
 24  * able to handle this, hence this driver only works with 48000Hz sampling
 25  * rate.
 26  * Reading and writing AC97 registers is another challenge. The core
 27  * provides us status bits when the read register is updated with *another*
 28  * value. When we read the same register two times (and the register still
 29  * contains the same value) these status bits are not set. We work
 30  * around this by not polling these bits but only wait a fixed delay.
 31  */
 32 
 33 #include <linux/init.h>
 34 #include <linux/io.h>
 35 #include <linux/module.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/clk.h>
 38 #include <linux/device.h>
 39 #include <linux/delay.h>
 40 #include <linux/slab.h>
 41 #include <linux/spinlock.h>
 42 #include <linux/of.h>
 43 #include <linux/of_address.h>
 44 #include <linux/of_irq.h>
 45 #include <linux/of_platform.h>
 46 
 47 #include <sound/core.h>
 48 #include <sound/pcm.h>
 49 #include <sound/pcm_params.h>
 50 #include <sound/initval.h>
 51 #include <sound/soc.h>
 52 #include <sound/dmaengine_pcm.h>
 53 
 54 #include "fsl_ssi.h"
 55 #include "imx-pcm.h"
 56 
 57 /**
 58  * FSLSSI_I2S_RATES: sample rates supported by the I2S
 59  *
 60  * This driver currently only supports the SSI running in I2S slave mode,
 61  * which means the codec determines the sample rate.  Therefore, we tell
 62  * ALSA that we support all rates and let the codec driver decide what rates
 63  * are really supported.
 64  */
 65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
 66 
 67 /**
 68  * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
 69  *
 70  * This driver currently only supports the SSI running in I2S slave mode.
 71  *
 72  * The SSI has a limitation in that the samples must be in the same byte
 73  * order as the host CPU.  This is because when multiple bytes are written
 74  * to the STX register, the bytes and bits must be written in the same
 75  * order.  The STX is a shift register, so all the bits need to be aligned
 76  * (bit-endianness must match byte-endianness).  Processors typically write
 77  * the bits within a byte in the same order that the bytes of a word are
 78  * written in.  So if the host CPU is big-endian, then only big-endian
 79  * samples will be written to STX properly.
 80  */
 81 #ifdef __BIG_ENDIAN
 82 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
 83          SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
 84          SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
 85 #else
 86 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
 87          SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 88          SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
 89 #endif
 90 
 91 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
 92                 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
 93                 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
 94 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
 95                 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
 96                 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
 97 
 98 enum fsl_ssi_type {
 99         FSL_SSI_MCP8610,
100         FSL_SSI_MX21,
101         FSL_SSI_MX35,
102         FSL_SSI_MX51,
103 };
104 
105 struct fsl_ssi_reg_val {
106         u32 sier;
107         u32 srcr;
108         u32 stcr;
109         u32 scr;
110 };
111 
112 struct fsl_ssi_rxtx_reg_val {
113         struct fsl_ssi_reg_val rx;
114         struct fsl_ssi_reg_val tx;
115 };
116 static const struct regmap_config fsl_ssi_regconfig = {
117         .max_register = CCSR_SSI_SACCDIS,
118         .reg_bits = 32,
119         .val_bits = 32,
120         .reg_stride = 4,
121         .val_format_endian = REGMAP_ENDIAN_NATIVE,
122 };
123 
124 struct fsl_ssi_soc_data {
125         bool imx;
126         bool offline_config;
127         u32 sisr_write_mask;
128 };
129 
130 /**
131  * fsl_ssi_private: per-SSI private data
132  *
133  * @reg: Pointer to the regmap registers
134  * @irq: IRQ of this SSI
135  * @cpu_dai_drv: CPU DAI driver for this device
136  *
137  * @dai_fmt: DAI configuration this device is currently used with
138  * @i2s_mode: i2s and network mode configuration of the device. Is used to
139  * switch between normal and i2s/network mode
140  * mode depending on the number of channels
141  * @use_dma: DMA is used or FIQ with stream filter
142  * @use_dual_fifo: DMA with support for both FIFOs used
143  * @fifo_deph: Depth of the SSI FIFOs
144  * @rxtx_reg_val: Specific register settings for receive/transmit configuration
145  *
146  * @clk: SSI clock
147  * @baudclk: SSI baud clock for master mode
148  * @baudclk_streams: Active streams that are using baudclk
149  * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
150  *
151  * @dma_params_tx: DMA transmit parameters
152  * @dma_params_rx: DMA receive parameters
153  * @ssi_phys: physical address of the SSI registers
154  *
155  * @fiq_params: FIQ stream filtering parameters
156  *
157  * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
158  *
159  * @dbg_stats: Debugging statistics
160  *
161  * @soc: SoC specifc data
162  */
163 struct fsl_ssi_private {
164         struct regmap *regs;
165         unsigned int irq;
166         struct snd_soc_dai_driver cpu_dai_drv;
167 
168         unsigned int dai_fmt;
169         u8 i2s_mode;
170         bool use_dma;
171         bool use_dual_fifo;
172         bool has_ipg_clk_name;
173         unsigned int fifo_depth;
174         struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
175 
176         struct clk *clk;
177         struct clk *baudclk;
178         unsigned int baudclk_streams;
179         unsigned int bitclk_freq;
180 
181         /* DMA params */
182         struct snd_dmaengine_dai_dma_data dma_params_tx;
183         struct snd_dmaengine_dai_dma_data dma_params_rx;
184         dma_addr_t ssi_phys;
185 
186         /* params for non-dma FIQ stream filtered mode */
187         struct imx_pcm_fiq_params fiq_params;
188 
189         /* Used when using fsl-ssi as sound-card. This is only used by ppc and
190          * should be replaced with simple-sound-card. */
191         struct platform_device *pdev;
192 
193         struct fsl_ssi_dbg dbg_stats;
194 
195         const struct fsl_ssi_soc_data *soc;
196 };
197 
198 /*
199  * imx51 and later SoCs have a slightly different IP that allows the
200  * SSI configuration while the SSI unit is running.
201  *
202  * More important, it is necessary on those SoCs to configure the
203  * sperate TX/RX DMA bits just before starting the stream
204  * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
205  * sends any DMA requests to the SDMA unit, otherwise it is not defined
206  * how the SDMA unit handles the DMA request.
207  *
208  * SDMA units are present on devices starting at imx35 but the imx35
209  * reference manual states that the DMA bits should not be changed
210  * while the SSI unit is running (SSIEN). So we support the necessary
211  * online configuration of fsl-ssi starting at imx51.
212  */
213 
214 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
215         .imx = false,
216         .offline_config = true,
217         .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
218                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
219                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
220 };
221 
222 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
223         .imx = true,
224         .offline_config = true,
225         .sisr_write_mask = 0,
226 };
227 
228 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
229         .imx = true,
230         .offline_config = true,
231         .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
232                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
233                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
234 };
235 
236 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
237         .imx = true,
238         .offline_config = false,
239         .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
240                 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
241 };
242 
243 static const struct of_device_id fsl_ssi_ids[] = {
244         { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
245         { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
246         { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
247         { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
248         {}
249 };
250 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
251 
252 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
253 {
254         return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97);
255 }
256 
257 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
258 {
259         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
260                 SND_SOC_DAIFMT_CBS_CFS;
261 }
262 
263 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private)
264 {
265         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
266                 SND_SOC_DAIFMT_CBM_CFS;
267 }
268 /**
269  * fsl_ssi_isr: SSI interrupt handler
270  *
271  * Although it's possible to use the interrupt handler to send and receive
272  * data to/from the SSI, we use the DMA instead.  Programming is more
273  * complicated, but the performance is much better.
274  *
275  * This interrupt handler is used only to gather statistics.
276  *
277  * @irq: IRQ of the SSI device
278  * @dev_id: pointer to the ssi_private structure for this SSI device
279  */
280 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
281 {
282         struct fsl_ssi_private *ssi_private = dev_id;
283         struct regmap *regs = ssi_private->regs;
284         __be32 sisr;
285         __be32 sisr2;
286 
287         /* We got an interrupt, so read the status register to see what we
288            were interrupted for.  We mask it with the Interrupt Enable register
289            so that we only check for events that we're interested in.
290          */
291         regmap_read(regs, CCSR_SSI_SISR, &sisr);
292 
293         sisr2 = sisr & ssi_private->soc->sisr_write_mask;
294         /* Clear the bits that we set */
295         if (sisr2)
296                 regmap_write(regs, CCSR_SSI_SISR, sisr2);
297 
298         fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
299 
300         return IRQ_HANDLED;
301 }
302 
303 /*
304  * Enable/Disable all rx/tx config flags at once.
305  */
306 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
307                 bool enable)
308 {
309         struct regmap *regs = ssi_private->regs;
310         struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
311 
312         if (enable) {
313                 regmap_update_bits(regs, CCSR_SSI_SIER,
314                                 vals->rx.sier | vals->tx.sier,
315                                 vals->rx.sier | vals->tx.sier);
316                 regmap_update_bits(regs, CCSR_SSI_SRCR,
317                                 vals->rx.srcr | vals->tx.srcr,
318                                 vals->rx.srcr | vals->tx.srcr);
319                 regmap_update_bits(regs, CCSR_SSI_STCR,
320                                 vals->rx.stcr | vals->tx.stcr,
321                                 vals->rx.stcr | vals->tx.stcr);
322         } else {
323                 regmap_update_bits(regs, CCSR_SSI_SRCR,
324                                 vals->rx.srcr | vals->tx.srcr, 0);
325                 regmap_update_bits(regs, CCSR_SSI_STCR,
326                                 vals->rx.stcr | vals->tx.stcr, 0);
327                 regmap_update_bits(regs, CCSR_SSI_SIER,
328                                 vals->rx.sier | vals->tx.sier, 0);
329         }
330 }
331 
332 /*
333  * Calculate the bits that have to be disabled for the current stream that is
334  * getting disabled. This keeps the bits enabled that are necessary for the
335  * second stream to work if 'stream_active' is true.
336  *
337  * Detailed calculation:
338  * These are the values that need to be active after disabling. For non-active
339  * second stream, this is 0:
340  *      vals_stream * !!stream_active
341  *
342  * The following computes the overall differences between the setup for the
343  * to-disable stream and the active stream, a simple XOR:
344  *      vals_disable ^ (vals_stream * !!(stream_active))
345  *
346  * The full expression adds a mask on all values we care about
347  */
348 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
349         ((vals_disable) & \
350          ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
351 
352 /*
353  * Enable/Disable a ssi configuration. You have to pass either
354  * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
355  */
356 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
357                 struct fsl_ssi_reg_val *vals)
358 {
359         struct regmap *regs = ssi_private->regs;
360         struct fsl_ssi_reg_val *avals;
361         int nr_active_streams;
362         u32 scr_val;
363         int keep_active;
364 
365         regmap_read(regs, CCSR_SSI_SCR, &scr_val);
366 
367         nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
368                                 !!(scr_val & CCSR_SSI_SCR_RE);
369 
370         if (nr_active_streams - 1 > 0)
371                 keep_active = 1;
372         else
373                 keep_active = 0;
374 
375         /* Find the other direction values rx or tx which we do not want to
376          * modify */
377         if (&ssi_private->rxtx_reg_val.rx == vals)
378                 avals = &ssi_private->rxtx_reg_val.tx;
379         else
380                 avals = &ssi_private->rxtx_reg_val.rx;
381 
382         /* If vals should be disabled, start with disabling the unit */
383         if (!enable) {
384                 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
385                                 keep_active);
386                 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
387         }
388 
389         /*
390          * We are running on a SoC which does not support online SSI
391          * reconfiguration, so we have to enable all necessary flags at once
392          * even if we do not use them later (capture and playback configuration)
393          */
394         if (ssi_private->soc->offline_config) {
395                 if ((enable && !nr_active_streams) ||
396                                 (!enable && !keep_active))
397                         fsl_ssi_rxtx_config(ssi_private, enable);
398 
399                 goto config_done;
400         }
401 
402         /*
403          * Configure single direction units while the SSI unit is running
404          * (online configuration)
405          */
406         if (enable) {
407                 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
408                 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
409                 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
410         } else {
411                 u32 sier;
412                 u32 srcr;
413                 u32 stcr;
414 
415                 /*
416                  * Disabling the necessary flags for one of rx/tx while the
417                  * other stream is active is a little bit more difficult. We
418                  * have to disable only those flags that differ between both
419                  * streams (rx XOR tx) and that are set in the stream that is
420                  * disabled now. Otherwise we could alter flags of the other
421                  * stream
422                  */
423 
424                 /* These assignments are simply vals without bits set in avals*/
425                 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
426                                 keep_active);
427                 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
428                                 keep_active);
429                 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
430                                 keep_active);
431 
432                 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
433                 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
434                 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
435         }
436 
437 config_done:
438         /* Enabling of subunits is done after configuration */
439         if (enable)
440                 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
441 }
442 
443 
444 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
445 {
446         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
447 }
448 
449 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
450 {
451         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
452 }
453 
454 /*
455  * Setup rx/tx register values used to enable/disable the streams. These will
456  * be used later in fsl_ssi_config to setup the streams without the need to
457  * check for all different SSI modes.
458  */
459 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
460 {
461         struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
462 
463         reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
464         reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
465         reg->rx.scr = 0;
466         reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
467         reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
468         reg->tx.scr = 0;
469 
470         if (!fsl_ssi_is_ac97(ssi_private)) {
471                 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
472                 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
473                 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
474                 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
475         }
476 
477         if (ssi_private->use_dma) {
478                 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
479                 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
480         } else {
481                 reg->rx.sier |= CCSR_SSI_SIER_RIE;
482                 reg->tx.sier |= CCSR_SSI_SIER_TIE;
483         }
484 
485         reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
486         reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
487 }
488 
489 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
490 {
491         struct regmap *regs = ssi_private->regs;
492 
493         /*
494          * Setup the clock control register
495          */
496         regmap_write(regs, CCSR_SSI_STCCR,
497                         CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
498         regmap_write(regs, CCSR_SSI_SRCCR,
499                         CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
500 
501         /*
502          * Enable AC97 mode and startup the SSI
503          */
504         regmap_write(regs, CCSR_SSI_SACNT,
505                         CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
506         regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
507         regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
508 
509         /*
510          * Enable SSI, Transmit and Receive. AC97 has to communicate with the
511          * codec before a stream is started.
512          */
513         regmap_update_bits(regs, CCSR_SSI_SCR,
514                         CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
515                         CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
516 
517         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
518 }
519 
520 /**
521  * fsl_ssi_startup: create a new substream
522  *
523  * This is the first function called when a stream is opened.
524  *
525  * If this is the first stream open, then grab the IRQ and program most of
526  * the SSI registers.
527  */
528 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
529                            struct snd_soc_dai *dai)
530 {
531         struct snd_soc_pcm_runtime *rtd = substream->private_data;
532         struct fsl_ssi_private *ssi_private =
533                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
534         int ret;
535 
536         ret = clk_prepare_enable(ssi_private->clk);
537         if (ret)
538                 return ret;
539 
540         /* When using dual fifo mode, it is safer to ensure an even period
541          * size. If appearing to an odd number while DMA always starts its
542          * task from fifo0, fifo1 would be neglected at the end of each
543          * period. But SSI would still access fifo1 with an invalid data.
544          */
545         if (ssi_private->use_dual_fifo)
546                 snd_pcm_hw_constraint_step(substream->runtime, 0,
547                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
548 
549         return 0;
550 }
551 
552 /**
553  * fsl_ssi_shutdown: shutdown the SSI
554  *
555  */
556 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
557                                 struct snd_soc_dai *dai)
558 {
559         struct snd_soc_pcm_runtime *rtd = substream->private_data;
560         struct fsl_ssi_private *ssi_private =
561                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
562 
563         clk_disable_unprepare(ssi_private->clk);
564 
565 }
566 
567 /**
568  * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
569  *
570  * Note: This function can be only called when using SSI as DAI master
571  *
572  * Quick instruction for parameters:
573  * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
574  * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
575  */
576 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
577                 struct snd_soc_dai *cpu_dai,
578                 struct snd_pcm_hw_params *hw_params)
579 {
580         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
581         struct regmap *regs = ssi_private->regs;
582         int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
583         u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
584         unsigned long clkrate, baudrate, tmprate;
585         u64 sub, savesub = 100000;
586         unsigned int freq;
587         bool baudclk_is_used;
588 
589         /* Prefer the explicitly set bitclock frequency */
590         if (ssi_private->bitclk_freq)
591                 freq = ssi_private->bitclk_freq;
592         else
593                 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
594 
595         /* Don't apply it to any non-baudclk circumstance */
596         if (IS_ERR(ssi_private->baudclk))
597                 return -EINVAL;
598 
599         baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
600 
601         /* It should be already enough to divide clock by setting pm alone */
602         psr = 0;
603         div2 = 0;
604 
605         factor = (div2 + 1) * (7 * psr + 1) * 2;
606 
607         for (i = 0; i < 255; i++) {
608                 /* The bclk rate must be smaller than 1/5 sysclk rate */
609                 if (factor * (i + 1) < 5)
610                         continue;
611 
612                 tmprate = freq * factor * (i + 2);
613 
614                 if (baudclk_is_used)
615                         clkrate = clk_get_rate(ssi_private->baudclk);
616                 else
617                         clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
618 
619                 clkrate /= factor;
620                 afreq = clkrate / (i + 1);
621 
622                 if (freq == afreq)
623                         sub = 0;
624                 else if (freq / afreq == 1)
625                         sub = freq - afreq;
626                 else if (afreq / freq == 1)
627                         sub = afreq - freq;
628                 else
629                         continue;
630 
631                 /* Calculate the fraction */
632                 sub *= 100000;
633                 do_div(sub, freq);
634 
635                 if (sub < savesub) {
636                         baudrate = tmprate;
637                         savesub = sub;
638                         pm = i;
639                 }
640 
641                 /* We are lucky */
642                 if (savesub == 0)
643                         break;
644         }
645 
646         /* No proper pm found if it is still remaining the initial value */
647         if (pm == 999) {
648                 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
649                 return -EINVAL;
650         }
651 
652         stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
653                 (psr ? CCSR_SSI_SxCCR_PSR : 0);
654         mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
655                 CCSR_SSI_SxCCR_PSR;
656 
657         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
658                 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
659         else
660                 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
661 
662         if (!baudclk_is_used) {
663                 ret = clk_set_rate(ssi_private->baudclk, baudrate);
664                 if (ret) {
665                         dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
666                         return -EINVAL;
667                 }
668         }
669 
670         return 0;
671 }
672 
673 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
674                 int clk_id, unsigned int freq, int dir)
675 {
676         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
677 
678         ssi_private->bitclk_freq = freq;
679 
680         return 0;
681 }
682 
683 /**
684  * fsl_ssi_hw_params - program the sample size
685  *
686  * Most of the SSI registers have been programmed in the startup function,
687  * but the word length must be programmed here.  Unfortunately, programming
688  * the SxCCR.WL bits requires the SSI to be temporarily disabled.  This can
689  * cause a problem with supporting simultaneous playback and capture.  If
690  * the SSI is already playing a stream, then that stream may be temporarily
691  * stopped when you start capture.
692  *
693  * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
694  * clock master.
695  */
696 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
697         struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
698 {
699         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
700         struct regmap *regs = ssi_private->regs;
701         unsigned int channels = params_channels(hw_params);
702         unsigned int sample_size =
703                 snd_pcm_format_width(params_format(hw_params));
704         u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
705         int ret;
706         u32 scr_val;
707         int enabled;
708 
709         regmap_read(regs, CCSR_SSI_SCR, &scr_val);
710         enabled = scr_val & CCSR_SSI_SCR_SSIEN;
711 
712         /*
713          * If we're in synchronous mode, and the SSI is already enabled,
714          * then STCCR is already set properly.
715          */
716         if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
717                 return 0;
718 
719         if (fsl_ssi_is_i2s_master(ssi_private)) {
720                 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
721                 if (ret)
722                         return ret;
723 
724                 /* Do not enable the clock if it is already enabled */
725                 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
726                         ret = clk_prepare_enable(ssi_private->baudclk);
727                         if (ret)
728                                 return ret;
729 
730                         ssi_private->baudclk_streams |= BIT(substream->stream);
731                 }
732         }
733 
734         if (!fsl_ssi_is_ac97(ssi_private)) {
735                 u8 i2smode;
736                 /*
737                  * Switch to normal net mode in order to have a frame sync
738                  * signal every 32 bits instead of 16 bits
739                  */
740                 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16)
741                         i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL |
742                                 CCSR_SSI_SCR_NET;
743                 else
744                         i2smode = ssi_private->i2s_mode;
745 
746                 regmap_update_bits(regs, CCSR_SSI_SCR,
747                                 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
748                                 channels == 1 ? 0 : i2smode);
749         }
750 
751         /*
752          * FIXME: The documentation says that SxCCR[WL] should not be
753          * modified while the SSI is enabled.  The only time this can
754          * happen is if we're trying to do simultaneous playback and
755          * capture in asynchronous mode.  Unfortunately, I have been enable
756          * to get that to work at all on the P1022DS.  Therefore, we don't
757          * bother to disable/enable the SSI when setting SxCCR[WL], because
758          * the SSI will stop anyway.  Maybe one day, this will get fixed.
759          */
760 
761         /* In synchronous mode, the SSI uses STCCR for capture */
762         if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
763             ssi_private->cpu_dai_drv.symmetric_rates)
764                 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
765                                 wl);
766         else
767                 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
768                                 wl);
769 
770         return 0;
771 }
772 
773 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
774                 struct snd_soc_dai *cpu_dai)
775 {
776         struct snd_soc_pcm_runtime *rtd = substream->private_data;
777         struct fsl_ssi_private *ssi_private =
778                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
779 
780         if (fsl_ssi_is_i2s_master(ssi_private) &&
781                         ssi_private->baudclk_streams & BIT(substream->stream)) {
782                 clk_disable_unprepare(ssi_private->baudclk);
783                 ssi_private->baudclk_streams &= ~BIT(substream->stream);
784         }
785 
786         return 0;
787 }
788 
789 static int _fsl_ssi_set_dai_fmt(struct device *dev,
790                                 struct fsl_ssi_private *ssi_private,
791                                 unsigned int fmt)
792 {
793         struct regmap *regs = ssi_private->regs;
794         u32 strcr = 0, stcr, srcr, scr, mask;
795         u8 wm;
796 
797         ssi_private->dai_fmt = fmt;
798 
799         if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
800                 dev_err(dev, "baudclk is missing which is necessary for master mode\n");
801                 return -EINVAL;
802         }
803 
804         fsl_ssi_setup_reg_vals(ssi_private);
805 
806         regmap_read(regs, CCSR_SSI_SCR, &scr);
807         scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
808         scr |= CCSR_SSI_SCR_SYNC_TX_FS;
809 
810         mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
811                 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
812                 CCSR_SSI_STCR_TEFS;
813         regmap_read(regs, CCSR_SSI_STCR, &stcr);
814         regmap_read(regs, CCSR_SSI_SRCR, &srcr);
815         stcr &= ~mask;
816         srcr &= ~mask;
817 
818         ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
819         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
820         case SND_SOC_DAIFMT_I2S:
821                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
822                 case SND_SOC_DAIFMT_CBM_CFS:
823                 case SND_SOC_DAIFMT_CBS_CFS:
824                         ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
825                         regmap_update_bits(regs, CCSR_SSI_STCCR,
826                                         CCSR_SSI_SxCCR_DC_MASK,
827                                         CCSR_SSI_SxCCR_DC(2));
828                         regmap_update_bits(regs, CCSR_SSI_SRCCR,
829                                         CCSR_SSI_SxCCR_DC_MASK,
830                                         CCSR_SSI_SxCCR_DC(2));
831                         break;
832                 case SND_SOC_DAIFMT_CBM_CFM:
833                         ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
834                         break;
835                 default:
836                         return -EINVAL;
837                 }
838 
839                 /* Data on rising edge of bclk, frame low, 1clk before data */
840                 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
841                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
842                 break;
843         case SND_SOC_DAIFMT_LEFT_J:
844                 /* Data on rising edge of bclk, frame high */
845                 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
846                 break;
847         case SND_SOC_DAIFMT_DSP_A:
848                 /* Data on rising edge of bclk, frame high, 1clk before data */
849                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
850                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
851                 break;
852         case SND_SOC_DAIFMT_DSP_B:
853                 /* Data on rising edge of bclk, frame high */
854                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
855                         CCSR_SSI_STCR_TXBIT0;
856                 break;
857         case SND_SOC_DAIFMT_AC97:
858                 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
859                 break;
860         default:
861                 return -EINVAL;
862         }
863         scr |= ssi_private->i2s_mode;
864 
865         /* DAI clock inversion */
866         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
867         case SND_SOC_DAIFMT_NB_NF:
868                 /* Nothing to do for both normal cases */
869                 break;
870         case SND_SOC_DAIFMT_IB_NF:
871                 /* Invert bit clock */
872                 strcr ^= CCSR_SSI_STCR_TSCKP;
873                 break;
874         case SND_SOC_DAIFMT_NB_IF:
875                 /* Invert frame clock */
876                 strcr ^= CCSR_SSI_STCR_TFSI;
877                 break;
878         case SND_SOC_DAIFMT_IB_IF:
879                 /* Invert both clocks */
880                 strcr ^= CCSR_SSI_STCR_TSCKP;
881                 strcr ^= CCSR_SSI_STCR_TFSI;
882                 break;
883         default:
884                 return -EINVAL;
885         }
886 
887         /* DAI clock master masks */
888         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
889         case SND_SOC_DAIFMT_CBS_CFS:
890                 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
891                 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
892                 break;
893         case SND_SOC_DAIFMT_CBM_CFM:
894                 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
895                 break;
896         case SND_SOC_DAIFMT_CBM_CFS:
897                 strcr &= ~CCSR_SSI_STCR_TXDIR;
898                 strcr |= CCSR_SSI_STCR_TFDIR;
899                 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
900                 break;
901         default:
902                 return -EINVAL;
903         }
904 
905         stcr |= strcr;
906         srcr |= strcr;
907 
908         if (ssi_private->cpu_dai_drv.symmetric_rates) {
909                 /* Need to clear RXDIR when using SYNC mode */
910                 srcr &= ~CCSR_SSI_SRCR_RXDIR;
911                 scr |= CCSR_SSI_SCR_SYN;
912         }
913 
914         regmap_write(regs, CCSR_SSI_STCR, stcr);
915         regmap_write(regs, CCSR_SSI_SRCR, srcr);
916         regmap_write(regs, CCSR_SSI_SCR, scr);
917 
918         /*
919          * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
920          * use FIFO 1. We program the transmit water to signal a DMA transfer
921          * if there are only two (or fewer) elements left in the FIFO. Two
922          * elements equals one frame (left channel, right channel). This value,
923          * however, depends on the depth of the transmit buffer.
924          *
925          * We set the watermark on the same level as the DMA burstsize.  For
926          * fiq it is probably better to use the biggest possible watermark
927          * size.
928          */
929         if (ssi_private->use_dma)
930                 wm = ssi_private->fifo_depth - 2;
931         else
932                 wm = ssi_private->fifo_depth;
933 
934         regmap_write(regs, CCSR_SSI_SFCSR,
935                         CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
936                         CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
937 
938         if (ssi_private->use_dual_fifo) {
939                 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
940                                 CCSR_SSI_SRCR_RFEN1);
941                 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
942                                 CCSR_SSI_STCR_TFEN1);
943                 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
944                                 CCSR_SSI_SCR_TCH_EN);
945         }
946 
947         if (fmt & SND_SOC_DAIFMT_AC97)
948                 fsl_ssi_setup_ac97(ssi_private);
949 
950         return 0;
951 
952 }
953 
954 /**
955  * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
956  */
957 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
958 {
959         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
960 
961         return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
962 }
963 
964 /**
965  * fsl_ssi_set_dai_tdm_slot - set TDM slot number
966  *
967  * Note: This function can be only called when using SSI as DAI master
968  */
969 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
970                                 u32 rx_mask, int slots, int slot_width)
971 {
972         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
973         struct regmap *regs = ssi_private->regs;
974         u32 val;
975 
976         /* The slot number should be >= 2 if using Network mode or I2S mode */
977         regmap_read(regs, CCSR_SSI_SCR, &val);
978         val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
979         if (val && slots < 2) {
980                 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
981                 return -EINVAL;
982         }
983 
984         regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
985                         CCSR_SSI_SxCCR_DC(slots));
986         regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
987                         CCSR_SSI_SxCCR_DC(slots));
988 
989         /* The register SxMSKs needs SSI to provide essential clock due to
990          * hardware design. So we here temporarily enable SSI to set them.
991          */
992         regmap_read(regs, CCSR_SSI_SCR, &val);
993         val &= CCSR_SSI_SCR_SSIEN;
994         regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
995                         CCSR_SSI_SCR_SSIEN);
996 
997         regmap_write(regs, CCSR_SSI_STMSK, tx_mask);
998         regmap_write(regs, CCSR_SSI_SRMSK, rx_mask);
999 
1000         regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
1001 
1002         return 0;
1003 }
1004 
1005 /**
1006  * fsl_ssi_trigger: start and stop the DMA transfer.
1007  *
1008  * This function is called by ALSA to start, stop, pause, and resume the DMA
1009  * transfer of data.
1010  *
1011  * The DMA channel is in external master start and pause mode, which
1012  * means the SSI completely controls the flow of data.
1013  */
1014 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1015                            struct snd_soc_dai *dai)
1016 {
1017         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1018         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1019         struct regmap *regs = ssi_private->regs;
1020 
1021         switch (cmd) {
1022         case SNDRV_PCM_TRIGGER_START:
1023         case SNDRV_PCM_TRIGGER_RESUME:
1024         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1025                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1026                         fsl_ssi_tx_config(ssi_private, true);
1027                 else
1028                         fsl_ssi_rx_config(ssi_private, true);
1029                 break;
1030 
1031         case SNDRV_PCM_TRIGGER_STOP:
1032         case SNDRV_PCM_TRIGGER_SUSPEND:
1033         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1034                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1035                         fsl_ssi_tx_config(ssi_private, false);
1036                 else
1037                         fsl_ssi_rx_config(ssi_private, false);
1038                 break;
1039 
1040         default:
1041                 return -EINVAL;
1042         }
1043 
1044         if (fsl_ssi_is_ac97(ssi_private)) {
1045                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1046                         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1047                 else
1048                         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1049         }
1050 
1051         return 0;
1052 }
1053 
1054 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1055 {
1056         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1057 
1058         if (ssi_private->soc->imx && ssi_private->use_dma) {
1059                 dai->playback_dma_data = &ssi_private->dma_params_tx;
1060                 dai->capture_dma_data = &ssi_private->dma_params_rx;
1061         }
1062 
1063         return 0;
1064 }
1065 
1066 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1067         .startup        = fsl_ssi_startup,
1068         .shutdown       = fsl_ssi_shutdown,
1069         .hw_params      = fsl_ssi_hw_params,
1070         .hw_free        = fsl_ssi_hw_free,
1071         .set_fmt        = fsl_ssi_set_dai_fmt,
1072         .set_sysclk     = fsl_ssi_set_dai_sysclk,
1073         .set_tdm_slot   = fsl_ssi_set_dai_tdm_slot,
1074         .trigger        = fsl_ssi_trigger,
1075 };
1076 
1077 /* Template for the CPU dai driver structure */
1078 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1079         .probe = fsl_ssi_dai_probe,
1080         .playback = {
1081                 .stream_name = "CPU-Playback",
1082                 .channels_min = 1,
1083                 .channels_max = 2,
1084                 .rates = FSLSSI_I2S_RATES,
1085                 .formats = FSLSSI_I2S_FORMATS,
1086         },
1087         .capture = {
1088                 .stream_name = "CPU-Capture",
1089                 .channels_min = 1,
1090                 .channels_max = 2,
1091                 .rates = FSLSSI_I2S_RATES,
1092                 .formats = FSLSSI_I2S_FORMATS,
1093         },
1094         .ops = &fsl_ssi_dai_ops,
1095 };
1096 
1097 static const struct snd_soc_component_driver fsl_ssi_component = {
1098         .name           = "fsl-ssi",
1099 };
1100 
1101 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1102         .ac97_control = 1,
1103         .playback = {
1104                 .stream_name = "AC97 Playback",
1105                 .channels_min = 2,
1106                 .channels_max = 2,
1107                 .rates = SNDRV_PCM_RATE_8000_48000,
1108                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1109         },
1110         .capture = {
1111                 .stream_name = "AC97 Capture",
1112                 .channels_min = 2,
1113                 .channels_max = 2,
1114                 .rates = SNDRV_PCM_RATE_48000,
1115                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1116         },
1117         .ops = &fsl_ssi_dai_ops,
1118 };
1119 
1120 
1121 static struct fsl_ssi_private *fsl_ac97_data;
1122 
1123 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1124                 unsigned short val)
1125 {
1126         struct regmap *regs = fsl_ac97_data->regs;
1127         unsigned int lreg;
1128         unsigned int lval;
1129 
1130         if (reg > 0x7f)
1131                 return;
1132 
1133 
1134         lreg = reg <<  12;
1135         regmap_write(regs, CCSR_SSI_SACADD, lreg);
1136 
1137         lval = val << 4;
1138         regmap_write(regs, CCSR_SSI_SACDAT, lval);
1139 
1140         regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1141                         CCSR_SSI_SACNT_WR);
1142         udelay(100);
1143 }
1144 
1145 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1146                 unsigned short reg)
1147 {
1148         struct regmap *regs = fsl_ac97_data->regs;
1149 
1150         unsigned short val = -1;
1151         u32 reg_val;
1152         unsigned int lreg;
1153 
1154         lreg = (reg & 0x7f) <<  12;
1155         regmap_write(regs, CCSR_SSI_SACADD, lreg);
1156         regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1157                         CCSR_SSI_SACNT_RD);
1158 
1159         udelay(100);
1160 
1161         regmap_read(regs, CCSR_SSI_SACDAT, &reg_val);
1162         val = (reg_val >> 4) & 0xffff;
1163 
1164         return val;
1165 }
1166 
1167 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1168         .read           = fsl_ssi_ac97_read,
1169         .write          = fsl_ssi_ac97_write,
1170 };
1171 
1172 /**
1173  * Make every character in a string lower-case
1174  */
1175 static void make_lowercase(char *s)
1176 {
1177         char *p = s;
1178         char c;
1179 
1180         while ((c = *p)) {
1181                 if ((c >= 'A') && (c <= 'Z'))
1182                         *p = c + ('a' - 'A');
1183                 p++;
1184         }
1185 }
1186 
1187 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1188                 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1189 {
1190         struct device_node *np = pdev->dev.of_node;
1191         u32 dmas[4];
1192         int ret;
1193 
1194         if (ssi_private->has_ipg_clk_name)
1195                 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
1196         else
1197                 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1198         if (IS_ERR(ssi_private->clk)) {
1199                 ret = PTR_ERR(ssi_private->clk);
1200                 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1201                 return ret;
1202         }
1203 
1204         if (!ssi_private->has_ipg_clk_name) {
1205                 ret = clk_prepare_enable(ssi_private->clk);
1206                 if (ret) {
1207                         dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1208                         return ret;
1209                 }
1210         }
1211 
1212         /* For those SLAVE implementations, we ingore non-baudclk cases
1213          * and, instead, abandon MASTER mode that needs baud clock.
1214          */
1215         ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1216         if (IS_ERR(ssi_private->baudclk))
1217                 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1218                          PTR_ERR(ssi_private->baudclk));
1219 
1220         /*
1221          * We have burstsize be "fifo_depth - 2" to match the SSI
1222          * watermark setting in fsl_ssi_startup().
1223          */
1224         ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1225         ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1226         ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1227         ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1228 
1229         ret = !of_property_read_u32_array(np, "dmas", dmas, 4);
1230         if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1231                 ssi_private->use_dual_fifo = true;
1232                 /* When using dual fifo mode, we need to keep watermark
1233                  * as even numbers due to dma script limitation.
1234                  */
1235                 ssi_private->dma_params_tx.maxburst &= ~0x1;
1236                 ssi_private->dma_params_rx.maxburst &= ~0x1;
1237         }
1238 
1239         if (!ssi_private->use_dma) {
1240 
1241                 /*
1242                  * Some boards use an incompatible codec. To get it
1243                  * working, we are using imx-fiq-pcm-audio, that
1244                  * can handle those codecs. DMA is not possible in this
1245                  * situation.
1246                  */
1247 
1248                 ssi_private->fiq_params.irq = ssi_private->irq;
1249                 ssi_private->fiq_params.base = iomem;
1250                 ssi_private->fiq_params.dma_params_rx =
1251                         &ssi_private->dma_params_rx;
1252                 ssi_private->fiq_params.dma_params_tx =
1253                         &ssi_private->dma_params_tx;
1254 
1255                 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1256                 if (ret)
1257                         goto error_pcm;
1258         } else {
1259                 ret = imx_pcm_dma_init(pdev);
1260                 if (ret)
1261                         goto error_pcm;
1262         }
1263 
1264         return 0;
1265 
1266 error_pcm:
1267 
1268         if (!ssi_private->has_ipg_clk_name)
1269                 clk_disable_unprepare(ssi_private->clk);
1270         return ret;
1271 }
1272 
1273 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1274                 struct fsl_ssi_private *ssi_private)
1275 {
1276         if (!ssi_private->use_dma)
1277                 imx_pcm_fiq_exit(pdev);
1278         if (!ssi_private->has_ipg_clk_name)
1279                 clk_disable_unprepare(ssi_private->clk);
1280 }
1281 
1282 static int fsl_ssi_probe(struct platform_device *pdev)
1283 {
1284         struct fsl_ssi_private *ssi_private;
1285         int ret = 0;
1286         struct device_node *np = pdev->dev.of_node;
1287         const struct of_device_id *of_id;
1288         const char *p, *sprop;
1289         const uint32_t *iprop;
1290         struct resource res;
1291         void __iomem *iomem;
1292         char name[64];
1293 
1294         /* SSIs that are not connected on the board should have a
1295          *      status = "disabled"
1296          * property in their device tree nodes.
1297          */
1298         if (!of_device_is_available(np))
1299                 return -ENODEV;
1300 
1301         of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1302         if (!of_id || !of_id->data)
1303                 return -EINVAL;
1304 
1305         ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1306                         GFP_KERNEL);
1307         if (!ssi_private) {
1308                 dev_err(&pdev->dev, "could not allocate DAI object\n");
1309                 return -ENOMEM;
1310         }
1311 
1312         ssi_private->soc = of_id->data;
1313 
1314         sprop = of_get_property(np, "fsl,mode", NULL);
1315         if (sprop) {
1316                 if (!strcmp(sprop, "ac97-slave"))
1317                         ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1318         }
1319 
1320         ssi_private->use_dma = !of_property_read_bool(np,
1321                         "fsl,fiq-stream-filter");
1322 
1323         if (fsl_ssi_is_ac97(ssi_private)) {
1324                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1325                                 sizeof(fsl_ssi_ac97_dai));
1326 
1327                 fsl_ac97_data = ssi_private;
1328 
1329                 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1330         } else {
1331                 /* Initialize this copy of the CPU DAI driver structure */
1332                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1333                        sizeof(fsl_ssi_dai_template));
1334         }
1335         ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1336 
1337         /* Get the addresses and IRQ */
1338         ret = of_address_to_resource(np, 0, &res);
1339         if (ret) {
1340                 dev_err(&pdev->dev, "could not determine device resources\n");
1341                 return ret;
1342         }
1343         ssi_private->ssi_phys = res.start;
1344 
1345         iomem = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
1346         if (!iomem) {
1347                 dev_err(&pdev->dev, "could not map device resources\n");
1348                 return -ENOMEM;
1349         }
1350 
1351         ret = of_property_match_string(np, "clock-names", "ipg");
1352         if (ret < 0) {
1353                 ssi_private->has_ipg_clk_name = false;
1354                 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1355                         &fsl_ssi_regconfig);
1356         } else {
1357                 ssi_private->has_ipg_clk_name = true;
1358                 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
1359                         "ipg", iomem, &fsl_ssi_regconfig);
1360         }
1361         if (IS_ERR(ssi_private->regs)) {
1362                 dev_err(&pdev->dev, "Failed to init register map\n");
1363                 return PTR_ERR(ssi_private->regs);
1364         }
1365 
1366         ssi_private->irq = irq_of_parse_and_map(np, 0);
1367         if (!ssi_private->irq) {
1368                 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1369                 return -ENXIO;
1370         }
1371 
1372         /* Are the RX and the TX clocks locked? */
1373         if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1374                 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1375                 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1376                 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1377         }
1378 
1379         /* Determine the FIFO depth. */
1380         iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1381         if (iprop)
1382                 ssi_private->fifo_depth = be32_to_cpup(iprop);
1383         else
1384                 /* Older 8610 DTs didn't have the fifo-depth property */
1385                 ssi_private->fifo_depth = 8;
1386 
1387         dev_set_drvdata(&pdev->dev, ssi_private);
1388 
1389         if (ssi_private->soc->imx) {
1390                 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1391                 if (ret)
1392                         goto error_irqmap;
1393         }
1394 
1395         ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1396                                          &ssi_private->cpu_dai_drv, 1);
1397         if (ret) {
1398                 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1399                 goto error_asoc_register;
1400         }
1401 
1402         if (ssi_private->use_dma) {
1403                 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1404                                         fsl_ssi_isr, 0, dev_name(&pdev->dev),
1405                                         ssi_private);
1406                 if (ret < 0) {
1407                         dev_err(&pdev->dev, "could not claim irq %u\n",
1408                                         ssi_private->irq);
1409                         goto error_irq;
1410                 }
1411         }
1412 
1413         ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1414         if (ret)
1415                 goto error_asoc_register;
1416 
1417         /*
1418          * If codec-handle property is missing from SSI node, we assume
1419          * that the machine driver uses new binding which does not require
1420          * SSI driver to trigger machine driver's probe.
1421          */
1422         if (!of_get_property(np, "codec-handle", NULL))
1423                 goto done;
1424 
1425         /* Trigger the machine driver's probe function.  The platform driver
1426          * name of the machine driver is taken from /compatible property of the
1427          * device tree.  We also pass the address of the CPU DAI driver
1428          * structure.
1429          */
1430         sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1431         /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1432         p = strrchr(sprop, ',');
1433         if (p)
1434                 sprop = p + 1;
1435         snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1436         make_lowercase(name);
1437 
1438         ssi_private->pdev =
1439                 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1440         if (IS_ERR(ssi_private->pdev)) {
1441                 ret = PTR_ERR(ssi_private->pdev);
1442                 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1443                 goto error_sound_card;
1444         }
1445 
1446 done:
1447         if (ssi_private->dai_fmt)
1448                 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
1449                                      ssi_private->dai_fmt);
1450 
1451         return 0;
1452 
1453 error_sound_card:
1454         fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1455 
1456 error_irq:
1457         snd_soc_unregister_component(&pdev->dev);
1458 
1459 error_asoc_register:
1460         if (ssi_private->soc->imx)
1461                 fsl_ssi_imx_clean(pdev, ssi_private);
1462 
1463 error_irqmap:
1464         if (ssi_private->use_dma)
1465                 irq_dispose_mapping(ssi_private->irq);
1466 
1467         return ret;
1468 }
1469 
1470 static int fsl_ssi_remove(struct platform_device *pdev)
1471 {
1472         struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1473 
1474         fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1475 
1476         if (ssi_private->pdev)
1477                 platform_device_unregister(ssi_private->pdev);
1478         snd_soc_unregister_component(&pdev->dev);
1479 
1480         if (ssi_private->soc->imx)
1481                 fsl_ssi_imx_clean(pdev, ssi_private);
1482 
1483         if (ssi_private->use_dma)
1484                 irq_dispose_mapping(ssi_private->irq);
1485 
1486         return 0;
1487 }
1488 
1489 static struct platform_driver fsl_ssi_driver = {
1490         .driver = {
1491                 .name = "fsl-ssi-dai",
1492                 .owner = THIS_MODULE,
1493                 .of_match_table = fsl_ssi_ids,
1494         },
1495         .probe = fsl_ssi_probe,
1496         .remove = fsl_ssi_remove,
1497 };
1498 
1499 module_platform_driver(fsl_ssi_driver);
1500 
1501 MODULE_ALIAS("platform:fsl-ssi-dai");
1502 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1503 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1504 MODULE_LICENSE("GPL v2");
1505 

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