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Linux/sound/soc/fsl/fsl_ssi.c

  1 /*
  2  * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
  3  *
  4  * Author: Timur Tabi <timur@freescale.com>
  5  *
  6  * Copyright 2007-2010 Freescale Semiconductor, Inc.
  7  *
  8  * This file is licensed under the terms of the GNU General Public License
  9  * version 2.  This program is licensed "as is" without any warranty of any
 10  * kind, whether express or implied.
 11  *
 12  *
 13  * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
 14  *
 15  * The i.MX SSI core has some nasty limitations in AC97 mode. While most
 16  * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
 17  * one FIFO which combines all valid receive slots. We cannot even select
 18  * which slots we want to receive. The WM9712 with which this driver
 19  * was developed with always sends GPIO status data in slot 12 which
 20  * we receive in our (PCM-) data stream. The only chance we have is to
 21  * manually skip this data in the FIQ handler. With sampling rates different
 22  * from 48000Hz not every frame has valid receive data, so the ratio
 23  * between pcm data and GPIO status data changes. Our FIQ handler is not
 24  * able to handle this, hence this driver only works with 48000Hz sampling
 25  * rate.
 26  * Reading and writing AC97 registers is another challenge. The core
 27  * provides us status bits when the read register is updated with *another*
 28  * value. When we read the same register two times (and the register still
 29  * contains the same value) these status bits are not set. We work
 30  * around this by not polling these bits but only wait a fixed delay.
 31  */
 32 
 33 #include <linux/init.h>
 34 #include <linux/io.h>
 35 #include <linux/module.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/clk.h>
 38 #include <linux/device.h>
 39 #include <linux/delay.h>
 40 #include <linux/slab.h>
 41 #include <linux/spinlock.h>
 42 #include <linux/of.h>
 43 #include <linux/of_address.h>
 44 #include <linux/of_irq.h>
 45 #include <linux/of_platform.h>
 46 
 47 #include <sound/core.h>
 48 #include <sound/pcm.h>
 49 #include <sound/pcm_params.h>
 50 #include <sound/initval.h>
 51 #include <sound/soc.h>
 52 #include <sound/dmaengine_pcm.h>
 53 
 54 #include "fsl_ssi.h"
 55 #include "imx-pcm.h"
 56 
 57 /**
 58  * FSLSSI_I2S_RATES: sample rates supported by the I2S
 59  *
 60  * This driver currently only supports the SSI running in I2S slave mode,
 61  * which means the codec determines the sample rate.  Therefore, we tell
 62  * ALSA that we support all rates and let the codec driver decide what rates
 63  * are really supported.
 64  */
 65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
 66 
 67 /**
 68  * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
 69  *
 70  * This driver currently only supports the SSI running in I2S slave mode.
 71  *
 72  * The SSI has a limitation in that the samples must be in the same byte
 73  * order as the host CPU.  This is because when multiple bytes are written
 74  * to the STX register, the bytes and bits must be written in the same
 75  * order.  The STX is a shift register, so all the bits need to be aligned
 76  * (bit-endianness must match byte-endianness).  Processors typically write
 77  * the bits within a byte in the same order that the bytes of a word are
 78  * written in.  So if the host CPU is big-endian, then only big-endian
 79  * samples will be written to STX properly.
 80  */
 81 #ifdef __BIG_ENDIAN
 82 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
 83          SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
 84          SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
 85 #else
 86 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
 87          SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 88          SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
 89 #endif
 90 
 91 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
 92                 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
 93                 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
 94 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
 95                 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
 96                 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
 97 
 98 enum fsl_ssi_type {
 99         FSL_SSI_MCP8610,
100         FSL_SSI_MX21,
101         FSL_SSI_MX35,
102         FSL_SSI_MX51,
103 };
104 
105 struct fsl_ssi_reg_val {
106         u32 sier;
107         u32 srcr;
108         u32 stcr;
109         u32 scr;
110 };
111 
112 struct fsl_ssi_rxtx_reg_val {
113         struct fsl_ssi_reg_val rx;
114         struct fsl_ssi_reg_val tx;
115 };
116 static const struct regmap_config fsl_ssi_regconfig = {
117         .max_register = CCSR_SSI_SACCDIS,
118         .reg_bits = 32,
119         .val_bits = 32,
120         .reg_stride = 4,
121         .val_format_endian = REGMAP_ENDIAN_NATIVE,
122 };
123 
124 struct fsl_ssi_soc_data {
125         bool imx;
126         bool offline_config;
127         u32 sisr_write_mask;
128 };
129 
130 /**
131  * fsl_ssi_private: per-SSI private data
132  *
133  * @reg: Pointer to the regmap registers
134  * @irq: IRQ of this SSI
135  * @cpu_dai_drv: CPU DAI driver for this device
136  *
137  * @dai_fmt: DAI configuration this device is currently used with
138  * @i2s_mode: i2s and network mode configuration of the device. Is used to
139  * switch between normal and i2s/network mode
140  * mode depending on the number of channels
141  * @use_dma: DMA is used or FIQ with stream filter
142  * @use_dual_fifo: DMA with support for both FIFOs used
143  * @fifo_deph: Depth of the SSI FIFOs
144  * @rxtx_reg_val: Specific register settings for receive/transmit configuration
145  *
146  * @clk: SSI clock
147  * @baudclk: SSI baud clock for master mode
148  * @baudclk_streams: Active streams that are using baudclk
149  * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
150  *
151  * @dma_params_tx: DMA transmit parameters
152  * @dma_params_rx: DMA receive parameters
153  * @ssi_phys: physical address of the SSI registers
154  *
155  * @fiq_params: FIQ stream filtering parameters
156  *
157  * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
158  *
159  * @dbg_stats: Debugging statistics
160  *
161  * @soc: SoC specifc data
162  */
163 struct fsl_ssi_private {
164         struct regmap *regs;
165         unsigned int irq;
166         struct snd_soc_dai_driver cpu_dai_drv;
167 
168         unsigned int dai_fmt;
169         u8 i2s_mode;
170         bool use_dma;
171         bool use_dual_fifo;
172         unsigned int fifo_depth;
173         struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
174 
175         struct clk *clk;
176         struct clk *baudclk;
177         unsigned int baudclk_streams;
178         unsigned int bitclk_freq;
179 
180         /* DMA params */
181         struct snd_dmaengine_dai_dma_data dma_params_tx;
182         struct snd_dmaengine_dai_dma_data dma_params_rx;
183         dma_addr_t ssi_phys;
184 
185         /* params for non-dma FIQ stream filtered mode */
186         struct imx_pcm_fiq_params fiq_params;
187 
188         /* Used when using fsl-ssi as sound-card. This is only used by ppc and
189          * should be replaced with simple-sound-card. */
190         struct platform_device *pdev;
191 
192         struct fsl_ssi_dbg dbg_stats;
193 
194         const struct fsl_ssi_soc_data *soc;
195 };
196 
197 /*
198  * imx51 and later SoCs have a slightly different IP that allows the
199  * SSI configuration while the SSI unit is running.
200  *
201  * More important, it is necessary on those SoCs to configure the
202  * sperate TX/RX DMA bits just before starting the stream
203  * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
204  * sends any DMA requests to the SDMA unit, otherwise it is not defined
205  * how the SDMA unit handles the DMA request.
206  *
207  * SDMA units are present on devices starting at imx35 but the imx35
208  * reference manual states that the DMA bits should not be changed
209  * while the SSI unit is running (SSIEN). So we support the necessary
210  * online configuration of fsl-ssi starting at imx51.
211  */
212 
213 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
214         .imx = false,
215         .offline_config = true,
216         .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
217                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
218                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
219 };
220 
221 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
222         .imx = true,
223         .offline_config = true,
224         .sisr_write_mask = 0,
225 };
226 
227 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
228         .imx = true,
229         .offline_config = true,
230         .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
231                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
232                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
233 };
234 
235 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
236         .imx = true,
237         .offline_config = false,
238         .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
239                 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
240 };
241 
242 static const struct of_device_id fsl_ssi_ids[] = {
243         { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
244         { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
245         { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
246         { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
247         {}
248 };
249 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
250 
251 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
252 {
253         return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97);
254 }
255 
256 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
257 {
258         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
259                 SND_SOC_DAIFMT_CBS_CFS;
260 }
261 
262 /**
263  * fsl_ssi_isr: SSI interrupt handler
264  *
265  * Although it's possible to use the interrupt handler to send and receive
266  * data to/from the SSI, we use the DMA instead.  Programming is more
267  * complicated, but the performance is much better.
268  *
269  * This interrupt handler is used only to gather statistics.
270  *
271  * @irq: IRQ of the SSI device
272  * @dev_id: pointer to the ssi_private structure for this SSI device
273  */
274 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
275 {
276         struct fsl_ssi_private *ssi_private = dev_id;
277         struct regmap *regs = ssi_private->regs;
278         __be32 sisr;
279         __be32 sisr2;
280 
281         /* We got an interrupt, so read the status register to see what we
282            were interrupted for.  We mask it with the Interrupt Enable register
283            so that we only check for events that we're interested in.
284          */
285         regmap_read(regs, CCSR_SSI_SISR, &sisr);
286 
287         sisr2 = sisr & ssi_private->soc->sisr_write_mask;
288         /* Clear the bits that we set */
289         if (sisr2)
290                 regmap_write(regs, CCSR_SSI_SISR, sisr2);
291 
292         fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
293 
294         return IRQ_HANDLED;
295 }
296 
297 /*
298  * Enable/Disable all rx/tx config flags at once.
299  */
300 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
301                 bool enable)
302 {
303         struct regmap *regs = ssi_private->regs;
304         struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
305 
306         if (enable) {
307                 regmap_update_bits(regs, CCSR_SSI_SIER,
308                                 vals->rx.sier | vals->tx.sier,
309                                 vals->rx.sier | vals->tx.sier);
310                 regmap_update_bits(regs, CCSR_SSI_SRCR,
311                                 vals->rx.srcr | vals->tx.srcr,
312                                 vals->rx.srcr | vals->tx.srcr);
313                 regmap_update_bits(regs, CCSR_SSI_STCR,
314                                 vals->rx.stcr | vals->tx.stcr,
315                                 vals->rx.stcr | vals->tx.stcr);
316         } else {
317                 regmap_update_bits(regs, CCSR_SSI_SRCR,
318                                 vals->rx.srcr | vals->tx.srcr, 0);
319                 regmap_update_bits(regs, CCSR_SSI_STCR,
320                                 vals->rx.stcr | vals->tx.stcr, 0);
321                 regmap_update_bits(regs, CCSR_SSI_SIER,
322                                 vals->rx.sier | vals->tx.sier, 0);
323         }
324 }
325 
326 /*
327  * Calculate the bits that have to be disabled for the current stream that is
328  * getting disabled. This keeps the bits enabled that are necessary for the
329  * second stream to work if 'stream_active' is true.
330  *
331  * Detailed calculation:
332  * These are the values that need to be active after disabling. For non-active
333  * second stream, this is 0:
334  *      vals_stream * !!stream_active
335  *
336  * The following computes the overall differences between the setup for the
337  * to-disable stream and the active stream, a simple XOR:
338  *      vals_disable ^ (vals_stream * !!(stream_active))
339  *
340  * The full expression adds a mask on all values we care about
341  */
342 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
343         ((vals_disable) & \
344          ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
345 
346 /*
347  * Enable/Disable a ssi configuration. You have to pass either
348  * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
349  */
350 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
351                 struct fsl_ssi_reg_val *vals)
352 {
353         struct regmap *regs = ssi_private->regs;
354         struct fsl_ssi_reg_val *avals;
355         int nr_active_streams;
356         u32 scr_val;
357         int keep_active;
358 
359         regmap_read(regs, CCSR_SSI_SCR, &scr_val);
360 
361         nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
362                                 !!(scr_val & CCSR_SSI_SCR_RE);
363 
364         if (nr_active_streams - 1 > 0)
365                 keep_active = 1;
366         else
367                 keep_active = 0;
368 
369         /* Find the other direction values rx or tx which we do not want to
370          * modify */
371         if (&ssi_private->rxtx_reg_val.rx == vals)
372                 avals = &ssi_private->rxtx_reg_val.tx;
373         else
374                 avals = &ssi_private->rxtx_reg_val.rx;
375 
376         /* If vals should be disabled, start with disabling the unit */
377         if (!enable) {
378                 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
379                                 keep_active);
380                 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
381         }
382 
383         /*
384          * We are running on a SoC which does not support online SSI
385          * reconfiguration, so we have to enable all necessary flags at once
386          * even if we do not use them later (capture and playback configuration)
387          */
388         if (ssi_private->soc->offline_config) {
389                 if ((enable && !nr_active_streams) ||
390                                 (!enable && !keep_active))
391                         fsl_ssi_rxtx_config(ssi_private, enable);
392 
393                 goto config_done;
394         }
395 
396         /*
397          * Configure single direction units while the SSI unit is running
398          * (online configuration)
399          */
400         if (enable) {
401                 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
402                 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
403                 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
404         } else {
405                 u32 sier;
406                 u32 srcr;
407                 u32 stcr;
408 
409                 /*
410                  * Disabling the necessary flags for one of rx/tx while the
411                  * other stream is active is a little bit more difficult. We
412                  * have to disable only those flags that differ between both
413                  * streams (rx XOR tx) and that are set in the stream that is
414                  * disabled now. Otherwise we could alter flags of the other
415                  * stream
416                  */
417 
418                 /* These assignments are simply vals without bits set in avals*/
419                 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
420                                 keep_active);
421                 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
422                                 keep_active);
423                 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
424                                 keep_active);
425 
426                 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
427                 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
428                 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
429         }
430 
431 config_done:
432         /* Enabling of subunits is done after configuration */
433         if (enable)
434                 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
435 }
436 
437 
438 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
439 {
440         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
441 }
442 
443 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
444 {
445         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
446 }
447 
448 /*
449  * Setup rx/tx register values used to enable/disable the streams. These will
450  * be used later in fsl_ssi_config to setup the streams without the need to
451  * check for all different SSI modes.
452  */
453 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
454 {
455         struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
456 
457         reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
458         reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
459         reg->rx.scr = 0;
460         reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
461         reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
462         reg->tx.scr = 0;
463 
464         if (!fsl_ssi_is_ac97(ssi_private)) {
465                 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
466                 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
467                 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
468                 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
469         }
470 
471         if (ssi_private->use_dma) {
472                 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
473                 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
474         } else {
475                 reg->rx.sier |= CCSR_SSI_SIER_RIE;
476                 reg->tx.sier |= CCSR_SSI_SIER_TIE;
477         }
478 
479         reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
480         reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
481 }
482 
483 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
484 {
485         struct regmap *regs = ssi_private->regs;
486 
487         /*
488          * Setup the clock control register
489          */
490         regmap_write(regs, CCSR_SSI_STCCR,
491                         CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
492         regmap_write(regs, CCSR_SSI_SRCCR,
493                         CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
494 
495         /*
496          * Enable AC97 mode and startup the SSI
497          */
498         regmap_write(regs, CCSR_SSI_SACNT,
499                         CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
500         regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
501         regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
502 
503         /*
504          * Enable SSI, Transmit and Receive. AC97 has to communicate with the
505          * codec before a stream is started.
506          */
507         regmap_update_bits(regs, CCSR_SSI_SCR,
508                         CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
509                         CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
510 
511         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
512 }
513 
514 /**
515  * fsl_ssi_startup: create a new substream
516  *
517  * This is the first function called when a stream is opened.
518  *
519  * If this is the first stream open, then grab the IRQ and program most of
520  * the SSI registers.
521  */
522 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
523                            struct snd_soc_dai *dai)
524 {
525         struct snd_soc_pcm_runtime *rtd = substream->private_data;
526         struct fsl_ssi_private *ssi_private =
527                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
528 
529         /* When using dual fifo mode, it is safer to ensure an even period
530          * size. If appearing to an odd number while DMA always starts its
531          * task from fifo0, fifo1 would be neglected at the end of each
532          * period. But SSI would still access fifo1 with an invalid data.
533          */
534         if (ssi_private->use_dual_fifo)
535                 snd_pcm_hw_constraint_step(substream->runtime, 0,
536                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
537 
538         return 0;
539 }
540 
541 /**
542  * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
543  *
544  * Note: This function can be only called when using SSI as DAI master
545  *
546  * Quick instruction for parameters:
547  * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
548  * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
549  */
550 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
551                 struct snd_soc_dai *cpu_dai,
552                 struct snd_pcm_hw_params *hw_params)
553 {
554         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
555         struct regmap *regs = ssi_private->regs;
556         int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
557         u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
558         unsigned long clkrate, baudrate, tmprate;
559         u64 sub, savesub = 100000;
560         unsigned int freq;
561         bool baudclk_is_used;
562 
563         /* Prefer the explicitly set bitclock frequency */
564         if (ssi_private->bitclk_freq)
565                 freq = ssi_private->bitclk_freq;
566         else
567                 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
568 
569         /* Don't apply it to any non-baudclk circumstance */
570         if (IS_ERR(ssi_private->baudclk))
571                 return -EINVAL;
572 
573         baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
574 
575         /* It should be already enough to divide clock by setting pm alone */
576         psr = 0;
577         div2 = 0;
578 
579         factor = (div2 + 1) * (7 * psr + 1) * 2;
580 
581         for (i = 0; i < 255; i++) {
582                 /* The bclk rate must be smaller than 1/5 sysclk rate */
583                 if (factor * (i + 1) < 5)
584                         continue;
585 
586                 tmprate = freq * factor * (i + 2);
587 
588                 if (baudclk_is_used)
589                         clkrate = clk_get_rate(ssi_private->baudclk);
590                 else
591                         clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
592 
593                 do_div(clkrate, factor);
594                 afreq = (u32)clkrate / (i + 1);
595 
596                 if (freq == afreq)
597                         sub = 0;
598                 else if (freq / afreq == 1)
599                         sub = freq - afreq;
600                 else if (afreq / freq == 1)
601                         sub = afreq - freq;
602                 else
603                         continue;
604 
605                 /* Calculate the fraction */
606                 sub *= 100000;
607                 do_div(sub, freq);
608 
609                 if (sub < savesub) {
610                         baudrate = tmprate;
611                         savesub = sub;
612                         pm = i;
613                 }
614 
615                 /* We are lucky */
616                 if (savesub == 0)
617                         break;
618         }
619 
620         /* No proper pm found if it is still remaining the initial value */
621         if (pm == 999) {
622                 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
623                 return -EINVAL;
624         }
625 
626         stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
627                 (psr ? CCSR_SSI_SxCCR_PSR : 0);
628         mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
629                 CCSR_SSI_SxCCR_PSR;
630 
631         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
632                 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
633         else
634                 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
635 
636         if (!baudclk_is_used) {
637                 ret = clk_set_rate(ssi_private->baudclk, baudrate);
638                 if (ret) {
639                         dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
640                         return -EINVAL;
641                 }
642         }
643 
644         return 0;
645 }
646 
647 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
648                 int clk_id, unsigned int freq, int dir)
649 {
650         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
651 
652         ssi_private->bitclk_freq = freq;
653 
654         return 0;
655 }
656 
657 /**
658  * fsl_ssi_hw_params - program the sample size
659  *
660  * Most of the SSI registers have been programmed in the startup function,
661  * but the word length must be programmed here.  Unfortunately, programming
662  * the SxCCR.WL bits requires the SSI to be temporarily disabled.  This can
663  * cause a problem with supporting simultaneous playback and capture.  If
664  * the SSI is already playing a stream, then that stream may be temporarily
665  * stopped when you start capture.
666  *
667  * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
668  * clock master.
669  */
670 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
671         struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
672 {
673         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
674         struct regmap *regs = ssi_private->regs;
675         unsigned int channels = params_channels(hw_params);
676         unsigned int sample_size =
677                 snd_pcm_format_width(params_format(hw_params));
678         u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
679         int ret;
680         u32 scr_val;
681         int enabled;
682 
683         regmap_read(regs, CCSR_SSI_SCR, &scr_val);
684         enabled = scr_val & CCSR_SSI_SCR_SSIEN;
685 
686         /*
687          * If we're in synchronous mode, and the SSI is already enabled,
688          * then STCCR is already set properly.
689          */
690         if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
691                 return 0;
692 
693         if (fsl_ssi_is_i2s_master(ssi_private)) {
694                 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
695                 if (ret)
696                         return ret;
697 
698                 /* Do not enable the clock if it is already enabled */
699                 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
700                         ret = clk_prepare_enable(ssi_private->baudclk);
701                         if (ret)
702                                 return ret;
703 
704                         ssi_private->baudclk_streams |= BIT(substream->stream);
705                 }
706         }
707 
708         /*
709          * FIXME: The documentation says that SxCCR[WL] should not be
710          * modified while the SSI is enabled.  The only time this can
711          * happen is if we're trying to do simultaneous playback and
712          * capture in asynchronous mode.  Unfortunately, I have been enable
713          * to get that to work at all on the P1022DS.  Therefore, we don't
714          * bother to disable/enable the SSI when setting SxCCR[WL], because
715          * the SSI will stop anyway.  Maybe one day, this will get fixed.
716          */
717 
718         /* In synchronous mode, the SSI uses STCCR for capture */
719         if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
720             ssi_private->cpu_dai_drv.symmetric_rates)
721                 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
722                                 wl);
723         else
724                 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
725                                 wl);
726 
727         if (!fsl_ssi_is_ac97(ssi_private))
728                 regmap_update_bits(regs, CCSR_SSI_SCR,
729                                 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
730                                 channels == 1 ? 0 : ssi_private->i2s_mode);
731 
732         return 0;
733 }
734 
735 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
736                 struct snd_soc_dai *cpu_dai)
737 {
738         struct snd_soc_pcm_runtime *rtd = substream->private_data;
739         struct fsl_ssi_private *ssi_private =
740                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
741 
742         if (fsl_ssi_is_i2s_master(ssi_private) &&
743                         ssi_private->baudclk_streams & BIT(substream->stream)) {
744                 clk_disable_unprepare(ssi_private->baudclk);
745                 ssi_private->baudclk_streams &= ~BIT(substream->stream);
746         }
747 
748         return 0;
749 }
750 
751 static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private,
752                 unsigned int fmt)
753 {
754         struct regmap *regs = ssi_private->regs;
755         u32 strcr = 0, stcr, srcr, scr, mask;
756         u8 wm;
757 
758         ssi_private->dai_fmt = fmt;
759 
760         if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
761                 dev_err(&ssi_private->pdev->dev, "baudclk is missing which is necessary for master mode\n");
762                 return -EINVAL;
763         }
764 
765         fsl_ssi_setup_reg_vals(ssi_private);
766 
767         regmap_read(regs, CCSR_SSI_SCR, &scr);
768         scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
769         scr |= CCSR_SSI_SCR_SYNC_TX_FS;
770 
771         mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
772                 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
773                 CCSR_SSI_STCR_TEFS;
774         regmap_read(regs, CCSR_SSI_STCR, &stcr);
775         regmap_read(regs, CCSR_SSI_SRCR, &srcr);
776         stcr &= ~mask;
777         srcr &= ~mask;
778 
779         ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
780         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
781         case SND_SOC_DAIFMT_I2S:
782                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
783                 case SND_SOC_DAIFMT_CBS_CFS:
784                         ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
785                         regmap_update_bits(regs, CCSR_SSI_STCCR,
786                                         CCSR_SSI_SxCCR_DC_MASK,
787                                         CCSR_SSI_SxCCR_DC(2));
788                         regmap_update_bits(regs, CCSR_SSI_SRCCR,
789                                         CCSR_SSI_SxCCR_DC_MASK,
790                                         CCSR_SSI_SxCCR_DC(2));
791                         break;
792                 case SND_SOC_DAIFMT_CBM_CFM:
793                         ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
794                         break;
795                 default:
796                         return -EINVAL;
797                 }
798 
799                 /* Data on rising edge of bclk, frame low, 1clk before data */
800                 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
801                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
802                 break;
803         case SND_SOC_DAIFMT_LEFT_J:
804                 /* Data on rising edge of bclk, frame high */
805                 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
806                 break;
807         case SND_SOC_DAIFMT_DSP_A:
808                 /* Data on rising edge of bclk, frame high, 1clk before data */
809                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
810                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
811                 break;
812         case SND_SOC_DAIFMT_DSP_B:
813                 /* Data on rising edge of bclk, frame high */
814                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
815                         CCSR_SSI_STCR_TXBIT0;
816                 break;
817         case SND_SOC_DAIFMT_AC97:
818                 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
819                 break;
820         default:
821                 return -EINVAL;
822         }
823         scr |= ssi_private->i2s_mode;
824 
825         /* DAI clock inversion */
826         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
827         case SND_SOC_DAIFMT_NB_NF:
828                 /* Nothing to do for both normal cases */
829                 break;
830         case SND_SOC_DAIFMT_IB_NF:
831                 /* Invert bit clock */
832                 strcr ^= CCSR_SSI_STCR_TSCKP;
833                 break;
834         case SND_SOC_DAIFMT_NB_IF:
835                 /* Invert frame clock */
836                 strcr ^= CCSR_SSI_STCR_TFSI;
837                 break;
838         case SND_SOC_DAIFMT_IB_IF:
839                 /* Invert both clocks */
840                 strcr ^= CCSR_SSI_STCR_TSCKP;
841                 strcr ^= CCSR_SSI_STCR_TFSI;
842                 break;
843         default:
844                 return -EINVAL;
845         }
846 
847         /* DAI clock master masks */
848         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
849         case SND_SOC_DAIFMT_CBS_CFS:
850                 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
851                 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
852                 break;
853         case SND_SOC_DAIFMT_CBM_CFM:
854                 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
855                 break;
856         default:
857                 return -EINVAL;
858         }
859 
860         stcr |= strcr;
861         srcr |= strcr;
862 
863         if (ssi_private->cpu_dai_drv.symmetric_rates) {
864                 /* Need to clear RXDIR when using SYNC mode */
865                 srcr &= ~CCSR_SSI_SRCR_RXDIR;
866                 scr |= CCSR_SSI_SCR_SYN;
867         }
868 
869         regmap_write(regs, CCSR_SSI_STCR, stcr);
870         regmap_write(regs, CCSR_SSI_SRCR, srcr);
871         regmap_write(regs, CCSR_SSI_SCR, scr);
872 
873         /*
874          * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
875          * use FIFO 1. We program the transmit water to signal a DMA transfer
876          * if there are only two (or fewer) elements left in the FIFO. Two
877          * elements equals one frame (left channel, right channel). This value,
878          * however, depends on the depth of the transmit buffer.
879          *
880          * We set the watermark on the same level as the DMA burstsize.  For
881          * fiq it is probably better to use the biggest possible watermark
882          * size.
883          */
884         if (ssi_private->use_dma)
885                 wm = ssi_private->fifo_depth - 2;
886         else
887                 wm = ssi_private->fifo_depth;
888 
889         regmap_write(regs, CCSR_SSI_SFCSR,
890                         CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
891                         CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
892 
893         if (ssi_private->use_dual_fifo) {
894                 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
895                                 CCSR_SSI_SRCR_RFEN1);
896                 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
897                                 CCSR_SSI_STCR_TFEN1);
898                 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
899                                 CCSR_SSI_SCR_TCH_EN);
900         }
901 
902         if (fmt & SND_SOC_DAIFMT_AC97)
903                 fsl_ssi_setup_ac97(ssi_private);
904 
905         return 0;
906 
907 }
908 
909 /**
910  * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
911  */
912 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
913 {
914         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
915 
916         return _fsl_ssi_set_dai_fmt(ssi_private, fmt);
917 }
918 
919 /**
920  * fsl_ssi_set_dai_tdm_slot - set TDM slot number
921  *
922  * Note: This function can be only called when using SSI as DAI master
923  */
924 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
925                                 u32 rx_mask, int slots, int slot_width)
926 {
927         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
928         struct regmap *regs = ssi_private->regs;
929         u32 val;
930 
931         /* The slot number should be >= 2 if using Network mode or I2S mode */
932         regmap_read(regs, CCSR_SSI_SCR, &val);
933         val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
934         if (val && slots < 2) {
935                 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
936                 return -EINVAL;
937         }
938 
939         regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
940                         CCSR_SSI_SxCCR_DC(slots));
941         regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
942                         CCSR_SSI_SxCCR_DC(slots));
943 
944         /* The register SxMSKs needs SSI to provide essential clock due to
945          * hardware design. So we here temporarily enable SSI to set them.
946          */
947         regmap_read(regs, CCSR_SSI_SCR, &val);
948         val &= CCSR_SSI_SCR_SSIEN;
949         regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
950                         CCSR_SSI_SCR_SSIEN);
951 
952         regmap_write(regs, CCSR_SSI_STMSK, tx_mask);
953         regmap_write(regs, CCSR_SSI_SRMSK, rx_mask);
954 
955         regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
956 
957         return 0;
958 }
959 
960 /**
961  * fsl_ssi_trigger: start and stop the DMA transfer.
962  *
963  * This function is called by ALSA to start, stop, pause, and resume the DMA
964  * transfer of data.
965  *
966  * The DMA channel is in external master start and pause mode, which
967  * means the SSI completely controls the flow of data.
968  */
969 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
970                            struct snd_soc_dai *dai)
971 {
972         struct snd_soc_pcm_runtime *rtd = substream->private_data;
973         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
974         struct regmap *regs = ssi_private->regs;
975 
976         switch (cmd) {
977         case SNDRV_PCM_TRIGGER_START:
978         case SNDRV_PCM_TRIGGER_RESUME:
979         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
980                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
981                         fsl_ssi_tx_config(ssi_private, true);
982                 else
983                         fsl_ssi_rx_config(ssi_private, true);
984                 break;
985 
986         case SNDRV_PCM_TRIGGER_STOP:
987         case SNDRV_PCM_TRIGGER_SUSPEND:
988         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
989                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
990                         fsl_ssi_tx_config(ssi_private, false);
991                 else
992                         fsl_ssi_rx_config(ssi_private, false);
993                 break;
994 
995         default:
996                 return -EINVAL;
997         }
998 
999         if (fsl_ssi_is_ac97(ssi_private)) {
1000                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1001                         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1002                 else
1003                         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1004         }
1005 
1006         return 0;
1007 }
1008 
1009 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1010 {
1011         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1012 
1013         if (ssi_private->soc->imx && ssi_private->use_dma) {
1014                 dai->playback_dma_data = &ssi_private->dma_params_tx;
1015                 dai->capture_dma_data = &ssi_private->dma_params_rx;
1016         }
1017 
1018         return 0;
1019 }
1020 
1021 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1022         .startup        = fsl_ssi_startup,
1023         .hw_params      = fsl_ssi_hw_params,
1024         .hw_free        = fsl_ssi_hw_free,
1025         .set_fmt        = fsl_ssi_set_dai_fmt,
1026         .set_sysclk     = fsl_ssi_set_dai_sysclk,
1027         .set_tdm_slot   = fsl_ssi_set_dai_tdm_slot,
1028         .trigger        = fsl_ssi_trigger,
1029 };
1030 
1031 /* Template for the CPU dai driver structure */
1032 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1033         .probe = fsl_ssi_dai_probe,
1034         .playback = {
1035                 .channels_min = 1,
1036                 .channels_max = 2,
1037                 .rates = FSLSSI_I2S_RATES,
1038                 .formats = FSLSSI_I2S_FORMATS,
1039         },
1040         .capture = {
1041                 .channels_min = 1,
1042                 .channels_max = 2,
1043                 .rates = FSLSSI_I2S_RATES,
1044                 .formats = FSLSSI_I2S_FORMATS,
1045         },
1046         .ops = &fsl_ssi_dai_ops,
1047 };
1048 
1049 static const struct snd_soc_component_driver fsl_ssi_component = {
1050         .name           = "fsl-ssi",
1051 };
1052 
1053 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1054         .ac97_control = 1,
1055         .playback = {
1056                 .stream_name = "AC97 Playback",
1057                 .channels_min = 2,
1058                 .channels_max = 2,
1059                 .rates = SNDRV_PCM_RATE_8000_48000,
1060                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1061         },
1062         .capture = {
1063                 .stream_name = "AC97 Capture",
1064                 .channels_min = 2,
1065                 .channels_max = 2,
1066                 .rates = SNDRV_PCM_RATE_48000,
1067                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1068         },
1069         .ops = &fsl_ssi_dai_ops,
1070 };
1071 
1072 
1073 static struct fsl_ssi_private *fsl_ac97_data;
1074 
1075 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1076                 unsigned short val)
1077 {
1078         struct regmap *regs = fsl_ac97_data->regs;
1079         unsigned int lreg;
1080         unsigned int lval;
1081 
1082         if (reg > 0x7f)
1083                 return;
1084 
1085 
1086         lreg = reg <<  12;
1087         regmap_write(regs, CCSR_SSI_SACADD, lreg);
1088 
1089         lval = val << 4;
1090         regmap_write(regs, CCSR_SSI_SACDAT, lval);
1091 
1092         regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1093                         CCSR_SSI_SACNT_WR);
1094         udelay(100);
1095 }
1096 
1097 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1098                 unsigned short reg)
1099 {
1100         struct regmap *regs = fsl_ac97_data->regs;
1101 
1102         unsigned short val = -1;
1103         u32 reg_val;
1104         unsigned int lreg;
1105 
1106         lreg = (reg & 0x7f) <<  12;
1107         regmap_write(regs, CCSR_SSI_SACADD, lreg);
1108         regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1109                         CCSR_SSI_SACNT_RD);
1110 
1111         udelay(100);
1112 
1113         regmap_read(regs, CCSR_SSI_SACDAT, &reg_val);
1114         val = (reg_val >> 4) & 0xffff;
1115 
1116         return val;
1117 }
1118 
1119 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1120         .read           = fsl_ssi_ac97_read,
1121         .write          = fsl_ssi_ac97_write,
1122 };
1123 
1124 /**
1125  * Make every character in a string lower-case
1126  */
1127 static void make_lowercase(char *s)
1128 {
1129         char *p = s;
1130         char c;
1131 
1132         while ((c = *p)) {
1133                 if ((c >= 'A') && (c <= 'Z'))
1134                         *p = c + ('a' - 'A');
1135                 p++;
1136         }
1137 }
1138 
1139 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1140                 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1141 {
1142         struct device_node *np = pdev->dev.of_node;
1143         u32 dmas[4];
1144         int ret;
1145 
1146         ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1147         if (IS_ERR(ssi_private->clk)) {
1148                 ret = PTR_ERR(ssi_private->clk);
1149                 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1150                 return ret;
1151         }
1152 
1153         ret = clk_prepare_enable(ssi_private->clk);
1154         if (ret) {
1155                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1156                 return ret;
1157         }
1158 
1159         /* For those SLAVE implementations, we ingore non-baudclk cases
1160          * and, instead, abandon MASTER mode that needs baud clock.
1161          */
1162         ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1163         if (IS_ERR(ssi_private->baudclk))
1164                 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1165                          PTR_ERR(ssi_private->baudclk));
1166 
1167         /*
1168          * We have burstsize be "fifo_depth - 2" to match the SSI
1169          * watermark setting in fsl_ssi_startup().
1170          */
1171         ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1172         ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1173         ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1174         ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1175 
1176         ret = !of_property_read_u32_array(np, "dmas", dmas, 4);
1177         if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1178                 ssi_private->use_dual_fifo = true;
1179                 /* When using dual fifo mode, we need to keep watermark
1180                  * as even numbers due to dma script limitation.
1181                  */
1182                 ssi_private->dma_params_tx.maxburst &= ~0x1;
1183                 ssi_private->dma_params_rx.maxburst &= ~0x1;
1184         }
1185 
1186         if (!ssi_private->use_dma) {
1187 
1188                 /*
1189                  * Some boards use an incompatible codec. To get it
1190                  * working, we are using imx-fiq-pcm-audio, that
1191                  * can handle those codecs. DMA is not possible in this
1192                  * situation.
1193                  */
1194 
1195                 ssi_private->fiq_params.irq = ssi_private->irq;
1196                 ssi_private->fiq_params.base = iomem;
1197                 ssi_private->fiq_params.dma_params_rx =
1198                         &ssi_private->dma_params_rx;
1199                 ssi_private->fiq_params.dma_params_tx =
1200                         &ssi_private->dma_params_tx;
1201 
1202                 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1203                 if (ret)
1204                         goto error_pcm;
1205         } else {
1206                 ret = imx_pcm_dma_init(pdev);
1207                 if (ret)
1208                         goto error_pcm;
1209         }
1210 
1211         return 0;
1212 
1213 error_pcm:
1214         clk_disable_unprepare(ssi_private->clk);
1215 
1216         return ret;
1217 }
1218 
1219 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1220                 struct fsl_ssi_private *ssi_private)
1221 {
1222         if (!ssi_private->use_dma)
1223                 imx_pcm_fiq_exit(pdev);
1224         clk_disable_unprepare(ssi_private->clk);
1225 }
1226 
1227 static int fsl_ssi_probe(struct platform_device *pdev)
1228 {
1229         struct fsl_ssi_private *ssi_private;
1230         int ret = 0;
1231         struct device_node *np = pdev->dev.of_node;
1232         const struct of_device_id *of_id;
1233         const char *p, *sprop;
1234         const uint32_t *iprop;
1235         struct resource res;
1236         void __iomem *iomem;
1237         char name[64];
1238 
1239         /* SSIs that are not connected on the board should have a
1240          *      status = "disabled"
1241          * property in their device tree nodes.
1242          */
1243         if (!of_device_is_available(np))
1244                 return -ENODEV;
1245 
1246         of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1247         if (!of_id || !of_id->data)
1248                 return -EINVAL;
1249 
1250         ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1251                         GFP_KERNEL);
1252         if (!ssi_private) {
1253                 dev_err(&pdev->dev, "could not allocate DAI object\n");
1254                 return -ENOMEM;
1255         }
1256 
1257         ssi_private->soc = of_id->data;
1258 
1259         sprop = of_get_property(np, "fsl,mode", NULL);
1260         if (sprop) {
1261                 if (!strcmp(sprop, "ac97-slave"))
1262                         ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1263                 else if (!strcmp(sprop, "i2s-slave"))
1264                         ssi_private->dai_fmt = SND_SOC_DAIFMT_I2S |
1265                                 SND_SOC_DAIFMT_CBM_CFM;
1266         }
1267 
1268         ssi_private->use_dma = !of_property_read_bool(np,
1269                         "fsl,fiq-stream-filter");
1270 
1271         if (fsl_ssi_is_ac97(ssi_private)) {
1272                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1273                                 sizeof(fsl_ssi_ac97_dai));
1274 
1275                 fsl_ac97_data = ssi_private;
1276 
1277                 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1278         } else {
1279                 /* Initialize this copy of the CPU DAI driver structure */
1280                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1281                        sizeof(fsl_ssi_dai_template));
1282         }
1283         ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1284 
1285         /* Get the addresses and IRQ */
1286         ret = of_address_to_resource(np, 0, &res);
1287         if (ret) {
1288                 dev_err(&pdev->dev, "could not determine device resources\n");
1289                 return ret;
1290         }
1291         ssi_private->ssi_phys = res.start;
1292 
1293         iomem = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
1294         if (!iomem) {
1295                 dev_err(&pdev->dev, "could not map device resources\n");
1296                 return -ENOMEM;
1297         }
1298 
1299         ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1300                         &fsl_ssi_regconfig);
1301         if (IS_ERR(ssi_private->regs)) {
1302                 dev_err(&pdev->dev, "Failed to init register map\n");
1303                 return PTR_ERR(ssi_private->regs);
1304         }
1305 
1306         ssi_private->irq = irq_of_parse_and_map(np, 0);
1307         if (!ssi_private->irq) {
1308                 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1309                 return -ENXIO;
1310         }
1311 
1312         /* Are the RX and the TX clocks locked? */
1313         if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1314                 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1315                 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1316                 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1317         }
1318 
1319         /* Determine the FIFO depth. */
1320         iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1321         if (iprop)
1322                 ssi_private->fifo_depth = be32_to_cpup(iprop);
1323         else
1324                 /* Older 8610 DTs didn't have the fifo-depth property */
1325                 ssi_private->fifo_depth = 8;
1326 
1327         dev_set_drvdata(&pdev->dev, ssi_private);
1328 
1329         if (ssi_private->soc->imx) {
1330                 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1331                 if (ret)
1332                         goto error_irqmap;
1333         }
1334 
1335         ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1336                                          &ssi_private->cpu_dai_drv, 1);
1337         if (ret) {
1338                 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1339                 goto error_asoc_register;
1340         }
1341 
1342         if (ssi_private->use_dma) {
1343                 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1344                                         fsl_ssi_isr, 0, dev_name(&pdev->dev),
1345                                         ssi_private);
1346                 if (ret < 0) {
1347                         dev_err(&pdev->dev, "could not claim irq %u\n",
1348                                         ssi_private->irq);
1349                         goto error_irq;
1350                 }
1351         }
1352 
1353         ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1354         if (ret)
1355                 goto error_asoc_register;
1356 
1357         /*
1358          * If codec-handle property is missing from SSI node, we assume
1359          * that the machine driver uses new binding which does not require
1360          * SSI driver to trigger machine driver's probe.
1361          */
1362         if (!of_get_property(np, "codec-handle", NULL))
1363                 goto done;
1364 
1365         /* Trigger the machine driver's probe function.  The platform driver
1366          * name of the machine driver is taken from /compatible property of the
1367          * device tree.  We also pass the address of the CPU DAI driver
1368          * structure.
1369          */
1370         sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1371         /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1372         p = strrchr(sprop, ',');
1373         if (p)
1374                 sprop = p + 1;
1375         snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1376         make_lowercase(name);
1377 
1378         ssi_private->pdev =
1379                 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1380         if (IS_ERR(ssi_private->pdev)) {
1381                 ret = PTR_ERR(ssi_private->pdev);
1382                 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1383                 goto error_sound_card;
1384         }
1385 
1386 done:
1387         if (ssi_private->dai_fmt)
1388                 _fsl_ssi_set_dai_fmt(ssi_private, ssi_private->dai_fmt);
1389 
1390         return 0;
1391 
1392 error_sound_card:
1393         fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1394 
1395 error_irq:
1396         snd_soc_unregister_component(&pdev->dev);
1397 
1398 error_asoc_register:
1399         if (ssi_private->soc->imx)
1400                 fsl_ssi_imx_clean(pdev, ssi_private);
1401 
1402 error_irqmap:
1403         if (ssi_private->use_dma)
1404                 irq_dispose_mapping(ssi_private->irq);
1405 
1406         return ret;
1407 }
1408 
1409 static int fsl_ssi_remove(struct platform_device *pdev)
1410 {
1411         struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1412 
1413         fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1414 
1415         if (ssi_private->pdev)
1416                 platform_device_unregister(ssi_private->pdev);
1417         snd_soc_unregister_component(&pdev->dev);
1418 
1419         if (ssi_private->soc->imx)
1420                 fsl_ssi_imx_clean(pdev, ssi_private);
1421 
1422         if (ssi_private->use_dma)
1423                 irq_dispose_mapping(ssi_private->irq);
1424 
1425         return 0;
1426 }
1427 
1428 static struct platform_driver fsl_ssi_driver = {
1429         .driver = {
1430                 .name = "fsl-ssi-dai",
1431                 .owner = THIS_MODULE,
1432                 .of_match_table = fsl_ssi_ids,
1433         },
1434         .probe = fsl_ssi_probe,
1435         .remove = fsl_ssi_remove,
1436 };
1437 
1438 module_platform_driver(fsl_ssi_driver);
1439 
1440 MODULE_ALIAS("platform:fsl-ssi-dai");
1441 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1442 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1443 MODULE_LICENSE("GPL v2");
1444 

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