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Linux/sound/soc/fsl/fsl_ssi.c

  1 /*
  2  * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
  3  *
  4  * Author: Timur Tabi <timur@freescale.com>
  5  *
  6  * Copyright 2007-2010 Freescale Semiconductor, Inc.
  7  *
  8  * This file is licensed under the terms of the GNU General Public License
  9  * version 2.  This program is licensed "as is" without any warranty of any
 10  * kind, whether express or implied.
 11  *
 12  *
 13  * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
 14  *
 15  * The i.MX SSI core has some nasty limitations in AC97 mode. While most
 16  * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
 17  * one FIFO which combines all valid receive slots. We cannot even select
 18  * which slots we want to receive. The WM9712 with which this driver
 19  * was developed with always sends GPIO status data in slot 12 which
 20  * we receive in our (PCM-) data stream. The only chance we have is to
 21  * manually skip this data in the FIQ handler. With sampling rates different
 22  * from 48000Hz not every frame has valid receive data, so the ratio
 23  * between pcm data and GPIO status data changes. Our FIQ handler is not
 24  * able to handle this, hence this driver only works with 48000Hz sampling
 25  * rate.
 26  * Reading and writing AC97 registers is another challenge. The core
 27  * provides us status bits when the read register is updated with *another*
 28  * value. When we read the same register two times (and the register still
 29  * contains the same value) these status bits are not set. We work
 30  * around this by not polling these bits but only wait a fixed delay.
 31  */
 32 
 33 #include <linux/init.h>
 34 #include <linux/io.h>
 35 #include <linux/module.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/clk.h>
 38 #include <linux/device.h>
 39 #include <linux/delay.h>
 40 #include <linux/slab.h>
 41 #include <linux/spinlock.h>
 42 #include <linux/of.h>
 43 #include <linux/of_address.h>
 44 #include <linux/of_irq.h>
 45 #include <linux/of_platform.h>
 46 
 47 #include <sound/core.h>
 48 #include <sound/pcm.h>
 49 #include <sound/pcm_params.h>
 50 #include <sound/initval.h>
 51 #include <sound/soc.h>
 52 #include <sound/dmaengine_pcm.h>
 53 
 54 #include "fsl_ssi.h"
 55 #include "imx-pcm.h"
 56 
 57 /**
 58  * FSLSSI_I2S_RATES: sample rates supported by the I2S
 59  *
 60  * This driver currently only supports the SSI running in I2S slave mode,
 61  * which means the codec determines the sample rate.  Therefore, we tell
 62  * ALSA that we support all rates and let the codec driver decide what rates
 63  * are really supported.
 64  */
 65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
 66 
 67 /**
 68  * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
 69  *
 70  * The SSI has a limitation in that the samples must be in the same byte
 71  * order as the host CPU.  This is because when multiple bytes are written
 72  * to the STX register, the bytes and bits must be written in the same
 73  * order.  The STX is a shift register, so all the bits need to be aligned
 74  * (bit-endianness must match byte-endianness).  Processors typically write
 75  * the bits within a byte in the same order that the bytes of a word are
 76  * written in.  So if the host CPU is big-endian, then only big-endian
 77  * samples will be written to STX properly.
 78  */
 79 #ifdef __BIG_ENDIAN
 80 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
 81          SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
 82          SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
 83 #else
 84 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
 85          SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 86          SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
 87 #endif
 88 
 89 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
 90                 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
 91                 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
 92 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
 93                 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
 94                 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
 95 
 96 enum fsl_ssi_type {
 97         FSL_SSI_MCP8610,
 98         FSL_SSI_MX21,
 99         FSL_SSI_MX35,
100         FSL_SSI_MX51,
101 };
102 
103 struct fsl_ssi_reg_val {
104         u32 sier;
105         u32 srcr;
106         u32 stcr;
107         u32 scr;
108 };
109 
110 struct fsl_ssi_rxtx_reg_val {
111         struct fsl_ssi_reg_val rx;
112         struct fsl_ssi_reg_val tx;
113 };
114 
115 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
116 {
117         switch (reg) {
118         case CCSR_SSI_SACCEN:
119         case CCSR_SSI_SACCDIS:
120                 return false;
121         default:
122                 return true;
123         }
124 }
125 
126 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
127 {
128         switch (reg) {
129         case CCSR_SSI_STX0:
130         case CCSR_SSI_STX1:
131         case CCSR_SSI_SRX0:
132         case CCSR_SSI_SRX1:
133         case CCSR_SSI_SISR:
134         case CCSR_SSI_SFCSR:
135         case CCSR_SSI_SACNT:
136         case CCSR_SSI_SACADD:
137         case CCSR_SSI_SACDAT:
138         case CCSR_SSI_SATAG:
139         case CCSR_SSI_SACCST:
140         case CCSR_SSI_SOR:
141                 return true;
142         default:
143                 return false;
144         }
145 }
146 
147 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
148 {
149         switch (reg) {
150         case CCSR_SSI_SRX0:
151         case CCSR_SSI_SRX1:
152         case CCSR_SSI_SISR:
153         case CCSR_SSI_SACADD:
154         case CCSR_SSI_SACDAT:
155         case CCSR_SSI_SATAG:
156                 return true;
157         default:
158                 return false;
159         }
160 }
161 
162 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
163 {
164         switch (reg) {
165         case CCSR_SSI_SRX0:
166         case CCSR_SSI_SRX1:
167         case CCSR_SSI_SACCST:
168                 return false;
169         default:
170                 return true;
171         }
172 }
173 
174 static const struct regmap_config fsl_ssi_regconfig = {
175         .max_register = CCSR_SSI_SACCDIS,
176         .reg_bits = 32,
177         .val_bits = 32,
178         .reg_stride = 4,
179         .val_format_endian = REGMAP_ENDIAN_NATIVE,
180         .num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1,
181         .readable_reg = fsl_ssi_readable_reg,
182         .volatile_reg = fsl_ssi_volatile_reg,
183         .precious_reg = fsl_ssi_precious_reg,
184         .writeable_reg = fsl_ssi_writeable_reg,
185         .cache_type = REGCACHE_RBTREE,
186 };
187 
188 struct fsl_ssi_soc_data {
189         bool imx;
190         bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
191         bool offline_config;
192         u32 sisr_write_mask;
193 };
194 
195 /**
196  * fsl_ssi_private: per-SSI private data
197  *
198  * @reg: Pointer to the regmap registers
199  * @irq: IRQ of this SSI
200  * @cpu_dai_drv: CPU DAI driver for this device
201  *
202  * @dai_fmt: DAI configuration this device is currently used with
203  * @i2s_mode: i2s and network mode configuration of the device. Is used to
204  * switch between normal and i2s/network mode
205  * mode depending on the number of channels
206  * @use_dma: DMA is used or FIQ with stream filter
207  * @use_dual_fifo: DMA with support for both FIFOs used
208  * @fifo_deph: Depth of the SSI FIFOs
209  * @rxtx_reg_val: Specific register settings for receive/transmit configuration
210  *
211  * @clk: SSI clock
212  * @baudclk: SSI baud clock for master mode
213  * @baudclk_streams: Active streams that are using baudclk
214  * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
215  *
216  * @dma_params_tx: DMA transmit parameters
217  * @dma_params_rx: DMA receive parameters
218  * @ssi_phys: physical address of the SSI registers
219  *
220  * @fiq_params: FIQ stream filtering parameters
221  *
222  * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
223  *
224  * @dbg_stats: Debugging statistics
225  *
226  * @soc: SoC specific data
227  */
228 struct fsl_ssi_private {
229         struct regmap *regs;
230         int irq;
231         struct snd_soc_dai_driver cpu_dai_drv;
232 
233         unsigned int dai_fmt;
234         u8 i2s_mode;
235         bool use_dma;
236         bool use_dual_fifo;
237         bool has_ipg_clk_name;
238         unsigned int fifo_depth;
239         struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
240 
241         struct clk *clk;
242         struct clk *baudclk;
243         unsigned int baudclk_streams;
244         unsigned int bitclk_freq;
245 
246         /* regcache for volatile regs */
247         u32 regcache_sfcsr;
248         u32 regcache_sacnt;
249 
250         /* DMA params */
251         struct snd_dmaengine_dai_dma_data dma_params_tx;
252         struct snd_dmaengine_dai_dma_data dma_params_rx;
253         dma_addr_t ssi_phys;
254 
255         /* params for non-dma FIQ stream filtered mode */
256         struct imx_pcm_fiq_params fiq_params;
257 
258         /* Used when using fsl-ssi as sound-card. This is only used by ppc and
259          * should be replaced with simple-sound-card. */
260         struct platform_device *pdev;
261 
262         struct fsl_ssi_dbg dbg_stats;
263 
264         const struct fsl_ssi_soc_data *soc;
265         struct device *dev;
266 };
267 
268 /*
269  * imx51 and later SoCs have a slightly different IP that allows the
270  * SSI configuration while the SSI unit is running.
271  *
272  * More important, it is necessary on those SoCs to configure the
273  * sperate TX/RX DMA bits just before starting the stream
274  * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
275  * sends any DMA requests to the SDMA unit, otherwise it is not defined
276  * how the SDMA unit handles the DMA request.
277  *
278  * SDMA units are present on devices starting at imx35 but the imx35
279  * reference manual states that the DMA bits should not be changed
280  * while the SSI unit is running (SSIEN). So we support the necessary
281  * online configuration of fsl-ssi starting at imx51.
282  */
283 
284 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
285         .imx = false,
286         .offline_config = true,
287         .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
288                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
289                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
290 };
291 
292 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
293         .imx = true,
294         .imx21regs = true,
295         .offline_config = true,
296         .sisr_write_mask = 0,
297 };
298 
299 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
300         .imx = true,
301         .offline_config = true,
302         .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
303                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
304                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
305 };
306 
307 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
308         .imx = true,
309         .offline_config = false,
310         .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
311                 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
312 };
313 
314 static const struct of_device_id fsl_ssi_ids[] = {
315         { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
316         { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
317         { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
318         { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
319         {}
320 };
321 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
322 
323 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
324 {
325         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
326                 SND_SOC_DAIFMT_AC97;
327 }
328 
329 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
330 {
331         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
332                 SND_SOC_DAIFMT_CBS_CFS;
333 }
334 
335 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private)
336 {
337         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
338                 SND_SOC_DAIFMT_CBM_CFS;
339 }
340 /**
341  * fsl_ssi_isr: SSI interrupt handler
342  *
343  * Although it's possible to use the interrupt handler to send and receive
344  * data to/from the SSI, we use the DMA instead.  Programming is more
345  * complicated, but the performance is much better.
346  *
347  * This interrupt handler is used only to gather statistics.
348  *
349  * @irq: IRQ of the SSI device
350  * @dev_id: pointer to the ssi_private structure for this SSI device
351  */
352 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
353 {
354         struct fsl_ssi_private *ssi_private = dev_id;
355         struct regmap *regs = ssi_private->regs;
356         __be32 sisr;
357         __be32 sisr2;
358 
359         /* We got an interrupt, so read the status register to see what we
360            were interrupted for.  We mask it with the Interrupt Enable register
361            so that we only check for events that we're interested in.
362          */
363         regmap_read(regs, CCSR_SSI_SISR, &sisr);
364 
365         sisr2 = sisr & ssi_private->soc->sisr_write_mask;
366         /* Clear the bits that we set */
367         if (sisr2)
368                 regmap_write(regs, CCSR_SSI_SISR, sisr2);
369 
370         fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
371 
372         return IRQ_HANDLED;
373 }
374 
375 /*
376  * Enable/Disable all rx/tx config flags at once.
377  */
378 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
379                 bool enable)
380 {
381         struct regmap *regs = ssi_private->regs;
382         struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
383 
384         if (enable) {
385                 regmap_update_bits(regs, CCSR_SSI_SIER,
386                                 vals->rx.sier | vals->tx.sier,
387                                 vals->rx.sier | vals->tx.sier);
388                 regmap_update_bits(regs, CCSR_SSI_SRCR,
389                                 vals->rx.srcr | vals->tx.srcr,
390                                 vals->rx.srcr | vals->tx.srcr);
391                 regmap_update_bits(regs, CCSR_SSI_STCR,
392                                 vals->rx.stcr | vals->tx.stcr,
393                                 vals->rx.stcr | vals->tx.stcr);
394         } else {
395                 regmap_update_bits(regs, CCSR_SSI_SRCR,
396                                 vals->rx.srcr | vals->tx.srcr, 0);
397                 regmap_update_bits(regs, CCSR_SSI_STCR,
398                                 vals->rx.stcr | vals->tx.stcr, 0);
399                 regmap_update_bits(regs, CCSR_SSI_SIER,
400                                 vals->rx.sier | vals->tx.sier, 0);
401         }
402 }
403 
404 /*
405  * Clear RX or TX FIFO to remove samples from the previous
406  * stream session which may be still present in the FIFO and
407  * may introduce bad samples and/or channel slipping.
408  *
409  * Note: The SOR is not documented in recent IMX datasheet, but
410  * is described in IMX51 reference manual at section 56.3.3.15.
411  */
412 static void fsl_ssi_fifo_clear(struct fsl_ssi_private *ssi_private,
413                 bool is_rx)
414 {
415         if (is_rx) {
416                 regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR,
417                         CCSR_SSI_SOR_RX_CLR, CCSR_SSI_SOR_RX_CLR);
418         } else {
419                 regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR,
420                         CCSR_SSI_SOR_TX_CLR, CCSR_SSI_SOR_TX_CLR);
421         }
422 }
423 
424 /*
425  * Calculate the bits that have to be disabled for the current stream that is
426  * getting disabled. This keeps the bits enabled that are necessary for the
427  * second stream to work if 'stream_active' is true.
428  *
429  * Detailed calculation:
430  * These are the values that need to be active after disabling. For non-active
431  * second stream, this is 0:
432  *      vals_stream * !!stream_active
433  *
434  * The following computes the overall differences between the setup for the
435  * to-disable stream and the active stream, a simple XOR:
436  *      vals_disable ^ (vals_stream * !!(stream_active))
437  *
438  * The full expression adds a mask on all values we care about
439  */
440 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
441         ((vals_disable) & \
442          ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
443 
444 /*
445  * Enable/Disable a ssi configuration. You have to pass either
446  * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
447  */
448 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
449                 struct fsl_ssi_reg_val *vals)
450 {
451         struct regmap *regs = ssi_private->regs;
452         struct fsl_ssi_reg_val *avals;
453         int nr_active_streams;
454         u32 scr_val;
455         int keep_active;
456 
457         regmap_read(regs, CCSR_SSI_SCR, &scr_val);
458 
459         nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
460                                 !!(scr_val & CCSR_SSI_SCR_RE);
461 
462         if (nr_active_streams - 1 > 0)
463                 keep_active = 1;
464         else
465                 keep_active = 0;
466 
467         /* Find the other direction values rx or tx which we do not want to
468          * modify */
469         if (&ssi_private->rxtx_reg_val.rx == vals)
470                 avals = &ssi_private->rxtx_reg_val.tx;
471         else
472                 avals = &ssi_private->rxtx_reg_val.rx;
473 
474         /* If vals should be disabled, start with disabling the unit */
475         if (!enable) {
476                 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
477                                 keep_active);
478                 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
479         }
480 
481         /*
482          * We are running on a SoC which does not support online SSI
483          * reconfiguration, so we have to enable all necessary flags at once
484          * even if we do not use them later (capture and playback configuration)
485          */
486         if (ssi_private->soc->offline_config) {
487                 if ((enable && !nr_active_streams) ||
488                                 (!enable && !keep_active))
489                         fsl_ssi_rxtx_config(ssi_private, enable);
490 
491                 goto config_done;
492         }
493 
494         /*
495          * Configure single direction units while the SSI unit is running
496          * (online configuration)
497          */
498         if (enable) {
499                 fsl_ssi_fifo_clear(ssi_private, vals->scr & CCSR_SSI_SCR_RE);
500 
501                 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
502                 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
503                 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
504         } else {
505                 u32 sier;
506                 u32 srcr;
507                 u32 stcr;
508 
509                 /*
510                  * Disabling the necessary flags for one of rx/tx while the
511                  * other stream is active is a little bit more difficult. We
512                  * have to disable only those flags that differ between both
513                  * streams (rx XOR tx) and that are set in the stream that is
514                  * disabled now. Otherwise we could alter flags of the other
515                  * stream
516                  */
517 
518                 /* These assignments are simply vals without bits set in avals*/
519                 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
520                                 keep_active);
521                 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
522                                 keep_active);
523                 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
524                                 keep_active);
525 
526                 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
527                 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
528                 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
529         }
530 
531 config_done:
532         /* Enabling of subunits is done after configuration */
533         if (enable) {
534                 if (ssi_private->use_dma && (vals->scr & CCSR_SSI_SCR_TE)) {
535                         /*
536                          * Be sure the Tx FIFO is filled when TE is set.
537                          * Otherwise, there are some chances to start the
538                          * playback with some void samples inserted first,
539                          * generating a channel slip.
540                          *
541                          * First, SSIEN must be set, to let the FIFO be filled.
542                          *
543                          * Notes:
544                          * - Limit this fix to the DMA case until FIQ cases can
545                          *   be tested.
546                          * - Limit the length of the busy loop to not lock the
547                          *   system too long, even if 1-2 loops are sufficient
548                          *   in general.
549                          */
550                         int i;
551                         int max_loop = 100;
552                         regmap_update_bits(regs, CCSR_SSI_SCR,
553                                         CCSR_SSI_SCR_SSIEN, CCSR_SSI_SCR_SSIEN);
554                         for (i = 0; i < max_loop; i++) {
555                                 u32 sfcsr;
556                                 regmap_read(regs, CCSR_SSI_SFCSR, &sfcsr);
557                                 if (CCSR_SSI_SFCSR_TFCNT0(sfcsr))
558                                         break;
559                         }
560                         if (i == max_loop) {
561                                 dev_err(ssi_private->dev,
562                                         "Timeout waiting TX FIFO filling\n");
563                         }
564                 }
565                 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
566         }
567 }
568 
569 
570 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
571 {
572         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
573 }
574 
575 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
576 {
577         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
578 }
579 
580 /*
581  * Setup rx/tx register values used to enable/disable the streams. These will
582  * be used later in fsl_ssi_config to setup the streams without the need to
583  * check for all different SSI modes.
584  */
585 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
586 {
587         struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
588 
589         reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
590         reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
591         reg->rx.scr = 0;
592         reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
593         reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
594         reg->tx.scr = 0;
595 
596         if (!fsl_ssi_is_ac97(ssi_private)) {
597                 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
598                 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
599                 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
600                 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
601         }
602 
603         if (ssi_private->use_dma) {
604                 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
605                 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
606         } else {
607                 reg->rx.sier |= CCSR_SSI_SIER_RIE;
608                 reg->tx.sier |= CCSR_SSI_SIER_TIE;
609         }
610 
611         reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
612         reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
613 }
614 
615 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
616 {
617         struct regmap *regs = ssi_private->regs;
618 
619         /*
620          * Setup the clock control register
621          */
622         regmap_write(regs, CCSR_SSI_STCCR,
623                         CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
624         regmap_write(regs, CCSR_SSI_SRCCR,
625                         CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
626 
627         /*
628          * Enable AC97 mode and startup the SSI
629          */
630         regmap_write(regs, CCSR_SSI_SACNT,
631                         CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
632 
633         /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
634         if (!ssi_private->soc->imx21regs) {
635                 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
636                 regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
637         }
638 
639         /*
640          * Enable SSI, Transmit and Receive. AC97 has to communicate with the
641          * codec before a stream is started.
642          */
643         regmap_update_bits(regs, CCSR_SSI_SCR,
644                         CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
645                         CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
646 
647         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
648 }
649 
650 /**
651  * fsl_ssi_startup: create a new substream
652  *
653  * This is the first function called when a stream is opened.
654  *
655  * If this is the first stream open, then grab the IRQ and program most of
656  * the SSI registers.
657  */
658 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
659                            struct snd_soc_dai *dai)
660 {
661         struct snd_soc_pcm_runtime *rtd = substream->private_data;
662         struct fsl_ssi_private *ssi_private =
663                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
664         int ret;
665 
666         ret = clk_prepare_enable(ssi_private->clk);
667         if (ret)
668                 return ret;
669 
670         /* When using dual fifo mode, it is safer to ensure an even period
671          * size. If appearing to an odd number while DMA always starts its
672          * task from fifo0, fifo1 would be neglected at the end of each
673          * period. But SSI would still access fifo1 with an invalid data.
674          */
675         if (ssi_private->use_dual_fifo)
676                 snd_pcm_hw_constraint_step(substream->runtime, 0,
677                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
678 
679         return 0;
680 }
681 
682 /**
683  * fsl_ssi_shutdown: shutdown the SSI
684  *
685  */
686 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
687                                 struct snd_soc_dai *dai)
688 {
689         struct snd_soc_pcm_runtime *rtd = substream->private_data;
690         struct fsl_ssi_private *ssi_private =
691                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
692 
693         clk_disable_unprepare(ssi_private->clk);
694 
695 }
696 
697 /**
698  * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
699  *
700  * Note: This function can be only called when using SSI as DAI master
701  *
702  * Quick instruction for parameters:
703  * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
704  * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
705  */
706 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
707                 struct snd_soc_dai *cpu_dai,
708                 struct snd_pcm_hw_params *hw_params)
709 {
710         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
711         struct regmap *regs = ssi_private->regs;
712         int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
713         u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
714         unsigned long clkrate, baudrate, tmprate;
715         u64 sub, savesub = 100000;
716         unsigned int freq;
717         bool baudclk_is_used;
718 
719         /* Prefer the explicitly set bitclock frequency */
720         if (ssi_private->bitclk_freq)
721                 freq = ssi_private->bitclk_freq;
722         else
723                 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
724 
725         /* Don't apply it to any non-baudclk circumstance */
726         if (IS_ERR(ssi_private->baudclk))
727                 return -EINVAL;
728 
729         /*
730          * Hardware limitation: The bclk rate must be
731          * never greater than 1/5 IPG clock rate
732          */
733         if (freq * 5 > clk_get_rate(ssi_private->clk)) {
734                 dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n");
735                 return -EINVAL;
736         }
737 
738         baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
739 
740         /* It should be already enough to divide clock by setting pm alone */
741         psr = 0;
742         div2 = 0;
743 
744         factor = (div2 + 1) * (7 * psr + 1) * 2;
745 
746         for (i = 0; i < 255; i++) {
747                 tmprate = freq * factor * (i + 1);
748 
749                 if (baudclk_is_used)
750                         clkrate = clk_get_rate(ssi_private->baudclk);
751                 else
752                         clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
753 
754                 clkrate /= factor;
755                 afreq = clkrate / (i + 1);
756 
757                 if (freq == afreq)
758                         sub = 0;
759                 else if (freq / afreq == 1)
760                         sub = freq - afreq;
761                 else if (afreq / freq == 1)
762                         sub = afreq - freq;
763                 else
764                         continue;
765 
766                 /* Calculate the fraction */
767                 sub *= 100000;
768                 do_div(sub, freq);
769 
770                 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
771                         baudrate = tmprate;
772                         savesub = sub;
773                         pm = i;
774                 }
775 
776                 /* We are lucky */
777                 if (savesub == 0)
778                         break;
779         }
780 
781         /* No proper pm found if it is still remaining the initial value */
782         if (pm == 999) {
783                 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
784                 return -EINVAL;
785         }
786 
787         stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
788                 (psr ? CCSR_SSI_SxCCR_PSR : 0);
789         mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
790                 CCSR_SSI_SxCCR_PSR;
791 
792         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
793                 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
794         else
795                 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
796 
797         if (!baudclk_is_used) {
798                 ret = clk_set_rate(ssi_private->baudclk, baudrate);
799                 if (ret) {
800                         dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
801                         return -EINVAL;
802                 }
803         }
804 
805         return 0;
806 }
807 
808 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
809                 int clk_id, unsigned int freq, int dir)
810 {
811         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
812 
813         ssi_private->bitclk_freq = freq;
814 
815         return 0;
816 }
817 
818 /**
819  * fsl_ssi_hw_params - program the sample size
820  *
821  * Most of the SSI registers have been programmed in the startup function,
822  * but the word length must be programmed here.  Unfortunately, programming
823  * the SxCCR.WL bits requires the SSI to be temporarily disabled.  This can
824  * cause a problem with supporting simultaneous playback and capture.  If
825  * the SSI is already playing a stream, then that stream may be temporarily
826  * stopped when you start capture.
827  *
828  * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
829  * clock master.
830  */
831 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
832         struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
833 {
834         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
835         struct regmap *regs = ssi_private->regs;
836         unsigned int channels = params_channels(hw_params);
837         unsigned int sample_size = params_width(hw_params);
838         u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
839         int ret;
840         u32 scr_val;
841         int enabled;
842 
843         regmap_read(regs, CCSR_SSI_SCR, &scr_val);
844         enabled = scr_val & CCSR_SSI_SCR_SSIEN;
845 
846         /*
847          * If we're in synchronous mode, and the SSI is already enabled,
848          * then STCCR is already set properly.
849          */
850         if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
851                 return 0;
852 
853         if (fsl_ssi_is_i2s_master(ssi_private)) {
854                 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
855                 if (ret)
856                         return ret;
857 
858                 /* Do not enable the clock if it is already enabled */
859                 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
860                         ret = clk_prepare_enable(ssi_private->baudclk);
861                         if (ret)
862                                 return ret;
863 
864                         ssi_private->baudclk_streams |= BIT(substream->stream);
865                 }
866         }
867 
868         if (!fsl_ssi_is_ac97(ssi_private)) {
869                 u8 i2smode;
870                 /*
871                  * Switch to normal net mode in order to have a frame sync
872                  * signal every 32 bits instead of 16 bits
873                  */
874                 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16)
875                         i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL |
876                                 CCSR_SSI_SCR_NET;
877                 else
878                         i2smode = ssi_private->i2s_mode;
879 
880                 regmap_update_bits(regs, CCSR_SSI_SCR,
881                                 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
882                                 channels == 1 ? 0 : i2smode);
883         }
884 
885         /*
886          * FIXME: The documentation says that SxCCR[WL] should not be
887          * modified while the SSI is enabled.  The only time this can
888          * happen is if we're trying to do simultaneous playback and
889          * capture in asynchronous mode.  Unfortunately, I have been enable
890          * to get that to work at all on the P1022DS.  Therefore, we don't
891          * bother to disable/enable the SSI when setting SxCCR[WL], because
892          * the SSI will stop anyway.  Maybe one day, this will get fixed.
893          */
894 
895         /* In synchronous mode, the SSI uses STCCR for capture */
896         if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
897             ssi_private->cpu_dai_drv.symmetric_rates)
898                 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
899                                 wl);
900         else
901                 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
902                                 wl);
903 
904         return 0;
905 }
906 
907 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
908                 struct snd_soc_dai *cpu_dai)
909 {
910         struct snd_soc_pcm_runtime *rtd = substream->private_data;
911         struct fsl_ssi_private *ssi_private =
912                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
913 
914         if (fsl_ssi_is_i2s_master(ssi_private) &&
915                         ssi_private->baudclk_streams & BIT(substream->stream)) {
916                 clk_disable_unprepare(ssi_private->baudclk);
917                 ssi_private->baudclk_streams &= ~BIT(substream->stream);
918         }
919 
920         return 0;
921 }
922 
923 static int _fsl_ssi_set_dai_fmt(struct device *dev,
924                                 struct fsl_ssi_private *ssi_private,
925                                 unsigned int fmt)
926 {
927         struct regmap *regs = ssi_private->regs;
928         u32 strcr = 0, stcr, srcr, scr, mask;
929         u8 wm;
930 
931         ssi_private->dai_fmt = fmt;
932 
933         if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
934                 dev_err(dev, "baudclk is missing which is necessary for master mode\n");
935                 return -EINVAL;
936         }
937 
938         fsl_ssi_setup_reg_vals(ssi_private);
939 
940         regmap_read(regs, CCSR_SSI_SCR, &scr);
941         scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
942         scr |= CCSR_SSI_SCR_SYNC_TX_FS;
943 
944         mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
945                 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
946                 CCSR_SSI_STCR_TEFS;
947         regmap_read(regs, CCSR_SSI_STCR, &stcr);
948         regmap_read(regs, CCSR_SSI_SRCR, &srcr);
949         stcr &= ~mask;
950         srcr &= ~mask;
951 
952         ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
953         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
954         case SND_SOC_DAIFMT_I2S:
955                 regmap_update_bits(regs, CCSR_SSI_STCCR,
956                                    CCSR_SSI_SxCCR_DC_MASK,
957                                    CCSR_SSI_SxCCR_DC(2));
958                 regmap_update_bits(regs, CCSR_SSI_SRCCR,
959                                    CCSR_SSI_SxCCR_DC_MASK,
960                                    CCSR_SSI_SxCCR_DC(2));
961                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
962                 case SND_SOC_DAIFMT_CBM_CFS:
963                 case SND_SOC_DAIFMT_CBS_CFS:
964                         ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
965                         break;
966                 case SND_SOC_DAIFMT_CBM_CFM:
967                         ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
968                         break;
969                 default:
970                         return -EINVAL;
971                 }
972 
973                 /* Data on rising edge of bclk, frame low, 1clk before data */
974                 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
975                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
976                 break;
977         case SND_SOC_DAIFMT_LEFT_J:
978                 /* Data on rising edge of bclk, frame high */
979                 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
980                 break;
981         case SND_SOC_DAIFMT_DSP_A:
982                 /* Data on rising edge of bclk, frame high, 1clk before data */
983                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
984                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
985                 break;
986         case SND_SOC_DAIFMT_DSP_B:
987                 /* Data on rising edge of bclk, frame high */
988                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
989                         CCSR_SSI_STCR_TXBIT0;
990                 break;
991         case SND_SOC_DAIFMT_AC97:
992                 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
993                 break;
994         default:
995                 return -EINVAL;
996         }
997         scr |= ssi_private->i2s_mode;
998 
999         /* DAI clock inversion */
1000         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1001         case SND_SOC_DAIFMT_NB_NF:
1002                 /* Nothing to do for both normal cases */
1003                 break;
1004         case SND_SOC_DAIFMT_IB_NF:
1005                 /* Invert bit clock */
1006                 strcr ^= CCSR_SSI_STCR_TSCKP;
1007                 break;
1008         case SND_SOC_DAIFMT_NB_IF:
1009                 /* Invert frame clock */
1010                 strcr ^= CCSR_SSI_STCR_TFSI;
1011                 break;
1012         case SND_SOC_DAIFMT_IB_IF:
1013                 /* Invert both clocks */
1014                 strcr ^= CCSR_SSI_STCR_TSCKP;
1015                 strcr ^= CCSR_SSI_STCR_TFSI;
1016                 break;
1017         default:
1018                 return -EINVAL;
1019         }
1020 
1021         /* DAI clock master masks */
1022         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1023         case SND_SOC_DAIFMT_CBS_CFS:
1024                 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
1025                 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
1026                 break;
1027         case SND_SOC_DAIFMT_CBM_CFM:
1028                 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
1029                 break;
1030         case SND_SOC_DAIFMT_CBM_CFS:
1031                 strcr &= ~CCSR_SSI_STCR_TXDIR;
1032                 strcr |= CCSR_SSI_STCR_TFDIR;
1033                 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
1034                 break;
1035         default:
1036                 if (!fsl_ssi_is_ac97(ssi_private))
1037                         return -EINVAL;
1038         }
1039 
1040         stcr |= strcr;
1041         srcr |= strcr;
1042 
1043         if (ssi_private->cpu_dai_drv.symmetric_rates
1044                         || fsl_ssi_is_ac97(ssi_private)) {
1045                 /* Need to clear RXDIR when using SYNC or AC97 mode */
1046                 srcr &= ~CCSR_SSI_SRCR_RXDIR;
1047                 scr |= CCSR_SSI_SCR_SYN;
1048         }
1049 
1050         regmap_write(regs, CCSR_SSI_STCR, stcr);
1051         regmap_write(regs, CCSR_SSI_SRCR, srcr);
1052         regmap_write(regs, CCSR_SSI_SCR, scr);
1053 
1054         /*
1055          * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
1056          * use FIFO 1. We program the transmit water to signal a DMA transfer
1057          * if there are only two (or fewer) elements left in the FIFO. Two
1058          * elements equals one frame (left channel, right channel). This value,
1059          * however, depends on the depth of the transmit buffer.
1060          *
1061          * We set the watermark on the same level as the DMA burstsize.  For
1062          * fiq it is probably better to use the biggest possible watermark
1063          * size.
1064          */
1065         if (ssi_private->use_dma)
1066                 wm = ssi_private->fifo_depth - 2;
1067         else
1068                 wm = ssi_private->fifo_depth;
1069 
1070         regmap_write(regs, CCSR_SSI_SFCSR,
1071                         CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
1072                         CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
1073 
1074         if (ssi_private->use_dual_fifo) {
1075                 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
1076                                 CCSR_SSI_SRCR_RFEN1);
1077                 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
1078                                 CCSR_SSI_STCR_TFEN1);
1079                 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
1080                                 CCSR_SSI_SCR_TCH_EN);
1081         }
1082 
1083         if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)
1084                 fsl_ssi_setup_ac97(ssi_private);
1085 
1086         return 0;
1087 
1088 }
1089 
1090 /**
1091  * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
1092  */
1093 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
1094 {
1095         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1096 
1097         return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
1098 }
1099 
1100 /**
1101  * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1102  *
1103  * Note: This function can be only called when using SSI as DAI master
1104  */
1105 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1106                                 u32 rx_mask, int slots, int slot_width)
1107 {
1108         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1109         struct regmap *regs = ssi_private->regs;
1110         u32 val;
1111 
1112         /* The slot number should be >= 2 if using Network mode or I2S mode */
1113         regmap_read(regs, CCSR_SSI_SCR, &val);
1114         val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
1115         if (val && slots < 2) {
1116                 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1117                 return -EINVAL;
1118         }
1119 
1120         regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
1121                         CCSR_SSI_SxCCR_DC(slots));
1122         regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
1123                         CCSR_SSI_SxCCR_DC(slots));
1124 
1125         /* The register SxMSKs needs SSI to provide essential clock due to
1126          * hardware design. So we here temporarily enable SSI to set them.
1127          */
1128         regmap_read(regs, CCSR_SSI_SCR, &val);
1129         val &= CCSR_SSI_SCR_SSIEN;
1130         regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
1131                         CCSR_SSI_SCR_SSIEN);
1132 
1133         regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask);
1134         regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask);
1135 
1136         regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
1137 
1138         return 0;
1139 }
1140 
1141 /**
1142  * fsl_ssi_trigger: start and stop the DMA transfer.
1143  *
1144  * This function is called by ALSA to start, stop, pause, and resume the DMA
1145  * transfer of data.
1146  *
1147  * The DMA channel is in external master start and pause mode, which
1148  * means the SSI completely controls the flow of data.
1149  */
1150 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1151                            struct snd_soc_dai *dai)
1152 {
1153         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1154         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1155         struct regmap *regs = ssi_private->regs;
1156 
1157         switch (cmd) {
1158         case SNDRV_PCM_TRIGGER_START:
1159         case SNDRV_PCM_TRIGGER_RESUME:
1160         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1161                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1162                         fsl_ssi_tx_config(ssi_private, true);
1163                 else
1164                         fsl_ssi_rx_config(ssi_private, true);
1165                 break;
1166 
1167         case SNDRV_PCM_TRIGGER_STOP:
1168         case SNDRV_PCM_TRIGGER_SUSPEND:
1169         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1170                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1171                         fsl_ssi_tx_config(ssi_private, false);
1172                 else
1173                         fsl_ssi_rx_config(ssi_private, false);
1174                 break;
1175 
1176         default:
1177                 return -EINVAL;
1178         }
1179 
1180         if (fsl_ssi_is_ac97(ssi_private)) {
1181                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1182                         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1183                 else
1184                         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1185         }
1186 
1187         return 0;
1188 }
1189 
1190 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1191 {
1192         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1193 
1194         if (ssi_private->soc->imx && ssi_private->use_dma) {
1195                 dai->playback_dma_data = &ssi_private->dma_params_tx;
1196                 dai->capture_dma_data = &ssi_private->dma_params_rx;
1197         }
1198 
1199         return 0;
1200 }
1201 
1202 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1203         .startup        = fsl_ssi_startup,
1204         .shutdown       = fsl_ssi_shutdown,
1205         .hw_params      = fsl_ssi_hw_params,
1206         .hw_free        = fsl_ssi_hw_free,
1207         .set_fmt        = fsl_ssi_set_dai_fmt,
1208         .set_sysclk     = fsl_ssi_set_dai_sysclk,
1209         .set_tdm_slot   = fsl_ssi_set_dai_tdm_slot,
1210         .trigger        = fsl_ssi_trigger,
1211 };
1212 
1213 /* Template for the CPU dai driver structure */
1214 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1215         .probe = fsl_ssi_dai_probe,
1216         .playback = {
1217                 .stream_name = "CPU-Playback",
1218                 .channels_min = 1,
1219                 .channels_max = 32,
1220                 .rates = FSLSSI_I2S_RATES,
1221                 .formats = FSLSSI_I2S_FORMATS,
1222         },
1223         .capture = {
1224                 .stream_name = "CPU-Capture",
1225                 .channels_min = 1,
1226                 .channels_max = 32,
1227                 .rates = FSLSSI_I2S_RATES,
1228                 .formats = FSLSSI_I2S_FORMATS,
1229         },
1230         .ops = &fsl_ssi_dai_ops,
1231 };
1232 
1233 static const struct snd_soc_component_driver fsl_ssi_component = {
1234         .name           = "fsl-ssi",
1235 };
1236 
1237 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1238         .bus_control = true,
1239         .probe = fsl_ssi_dai_probe,
1240         .playback = {
1241                 .stream_name = "AC97 Playback",
1242                 .channels_min = 2,
1243                 .channels_max = 2,
1244                 .rates = SNDRV_PCM_RATE_8000_48000,
1245                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1246         },
1247         .capture = {
1248                 .stream_name = "AC97 Capture",
1249                 .channels_min = 2,
1250                 .channels_max = 2,
1251                 .rates = SNDRV_PCM_RATE_48000,
1252                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1253         },
1254         .ops = &fsl_ssi_dai_ops,
1255 };
1256 
1257 
1258 static struct fsl_ssi_private *fsl_ac97_data;
1259 
1260 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1261                 unsigned short val)
1262 {
1263         struct regmap *regs = fsl_ac97_data->regs;
1264         unsigned int lreg;
1265         unsigned int lval;
1266         int ret;
1267 
1268         if (reg > 0x7f)
1269                 return;
1270 
1271         ret = clk_prepare_enable(fsl_ac97_data->clk);
1272         if (ret) {
1273                 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1274                         ret);
1275                 return;
1276         }
1277 
1278         lreg = reg <<  12;
1279         regmap_write(regs, CCSR_SSI_SACADD, lreg);
1280 
1281         lval = val << 4;
1282         regmap_write(regs, CCSR_SSI_SACDAT, lval);
1283 
1284         regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1285                         CCSR_SSI_SACNT_WR);
1286         udelay(100);
1287 
1288         clk_disable_unprepare(fsl_ac97_data->clk);
1289 }
1290 
1291 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1292                 unsigned short reg)
1293 {
1294         struct regmap *regs = fsl_ac97_data->regs;
1295 
1296         unsigned short val = -1;
1297         u32 reg_val;
1298         unsigned int lreg;
1299         int ret;
1300 
1301         ret = clk_prepare_enable(fsl_ac97_data->clk);
1302         if (ret) {
1303                 pr_err("ac97 read clk_prepare_enable failed: %d\n",
1304                         ret);
1305                 return -1;
1306         }
1307 
1308         lreg = (reg & 0x7f) <<  12;
1309         regmap_write(regs, CCSR_SSI_SACADD, lreg);
1310         regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1311                         CCSR_SSI_SACNT_RD);
1312 
1313         udelay(100);
1314 
1315         regmap_read(regs, CCSR_SSI_SACDAT, &reg_val);
1316         val = (reg_val >> 4) & 0xffff;
1317 
1318         clk_disable_unprepare(fsl_ac97_data->clk);
1319 
1320         return val;
1321 }
1322 
1323 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1324         .read           = fsl_ssi_ac97_read,
1325         .write          = fsl_ssi_ac97_write,
1326 };
1327 
1328 /**
1329  * Make every character in a string lower-case
1330  */
1331 static void make_lowercase(char *s)
1332 {
1333         char *p = s;
1334         char c;
1335 
1336         while ((c = *p)) {
1337                 if ((c >= 'A') && (c <= 'Z'))
1338                         *p = c + ('a' - 'A');
1339                 p++;
1340         }
1341 }
1342 
1343 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1344                 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1345 {
1346         struct device_node *np = pdev->dev.of_node;
1347         u32 dmas[4];
1348         int ret;
1349 
1350         if (ssi_private->has_ipg_clk_name)
1351                 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
1352         else
1353                 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1354         if (IS_ERR(ssi_private->clk)) {
1355                 ret = PTR_ERR(ssi_private->clk);
1356                 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1357                 return ret;
1358         }
1359 
1360         if (!ssi_private->has_ipg_clk_name) {
1361                 ret = clk_prepare_enable(ssi_private->clk);
1362                 if (ret) {
1363                         dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1364                         return ret;
1365                 }
1366         }
1367 
1368         /* For those SLAVE implementations, we ignore non-baudclk cases
1369          * and, instead, abandon MASTER mode that needs baud clock.
1370          */
1371         ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1372         if (IS_ERR(ssi_private->baudclk))
1373                 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1374                          PTR_ERR(ssi_private->baudclk));
1375 
1376         /*
1377          * We have burstsize be "fifo_depth - 2" to match the SSI
1378          * watermark setting in fsl_ssi_startup().
1379          */
1380         ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1381         ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1382         ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1383         ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1384 
1385         ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1386         if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1387                 ssi_private->use_dual_fifo = true;
1388                 /* When using dual fifo mode, we need to keep watermark
1389                  * as even numbers due to dma script limitation.
1390                  */
1391                 ssi_private->dma_params_tx.maxburst &= ~0x1;
1392                 ssi_private->dma_params_rx.maxburst &= ~0x1;
1393         }
1394 
1395         if (!ssi_private->use_dma) {
1396 
1397                 /*
1398                  * Some boards use an incompatible codec. To get it
1399                  * working, we are using imx-fiq-pcm-audio, that
1400                  * can handle those codecs. DMA is not possible in this
1401                  * situation.
1402                  */
1403 
1404                 ssi_private->fiq_params.irq = ssi_private->irq;
1405                 ssi_private->fiq_params.base = iomem;
1406                 ssi_private->fiq_params.dma_params_rx =
1407                         &ssi_private->dma_params_rx;
1408                 ssi_private->fiq_params.dma_params_tx =
1409                         &ssi_private->dma_params_tx;
1410 
1411                 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1412                 if (ret)
1413                         goto error_pcm;
1414         } else {
1415                 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
1416                 if (ret)
1417                         goto error_pcm;
1418         }
1419 
1420         return 0;
1421 
1422 error_pcm:
1423 
1424         if (!ssi_private->has_ipg_clk_name)
1425                 clk_disable_unprepare(ssi_private->clk);
1426         return ret;
1427 }
1428 
1429 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1430                 struct fsl_ssi_private *ssi_private)
1431 {
1432         if (!ssi_private->use_dma)
1433                 imx_pcm_fiq_exit(pdev);
1434         if (!ssi_private->has_ipg_clk_name)
1435                 clk_disable_unprepare(ssi_private->clk);
1436 }
1437 
1438 static int fsl_ssi_probe(struct platform_device *pdev)
1439 {
1440         struct fsl_ssi_private *ssi_private;
1441         int ret = 0;
1442         struct device_node *np = pdev->dev.of_node;
1443         const struct of_device_id *of_id;
1444         const char *p, *sprop;
1445         const uint32_t *iprop;
1446         struct resource *res;
1447         void __iomem *iomem;
1448         char name[64];
1449         struct regmap_config regconfig = fsl_ssi_regconfig;
1450 
1451         of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1452         if (!of_id || !of_id->data)
1453                 return -EINVAL;
1454 
1455         ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1456                         GFP_KERNEL);
1457         if (!ssi_private) {
1458                 dev_err(&pdev->dev, "could not allocate DAI object\n");
1459                 return -ENOMEM;
1460         }
1461 
1462         ssi_private->soc = of_id->data;
1463         ssi_private->dev = &pdev->dev;
1464 
1465         sprop = of_get_property(np, "fsl,mode", NULL);
1466         if (sprop) {
1467                 if (!strcmp(sprop, "ac97-slave"))
1468                         ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1469         }
1470 
1471         ssi_private->use_dma = !of_property_read_bool(np,
1472                         "fsl,fiq-stream-filter");
1473 
1474         if (fsl_ssi_is_ac97(ssi_private)) {
1475                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1476                                 sizeof(fsl_ssi_ac97_dai));
1477 
1478                 fsl_ac97_data = ssi_private;
1479 
1480                 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1481                 if (ret) {
1482                         dev_err(&pdev->dev, "could not set AC'97 ops\n");
1483                         return ret;
1484                 }
1485         } else {
1486                 /* Initialize this copy of the CPU DAI driver structure */
1487                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1488                        sizeof(fsl_ssi_dai_template));
1489         }
1490         ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1491 
1492         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1493         iomem = devm_ioremap_resource(&pdev->dev, res);
1494         if (IS_ERR(iomem))
1495                 return PTR_ERR(iomem);
1496         ssi_private->ssi_phys = res->start;
1497 
1498         if (ssi_private->soc->imx21regs) {
1499                 /*
1500                  * According to datasheet imx21-class SSI
1501                  * don't have SACC{ST,EN,DIS} regs.
1502                  */
1503                 regconfig.max_register = CCSR_SSI_SRMSK;
1504                 regconfig.num_reg_defaults_raw =
1505                         CCSR_SSI_SRMSK / sizeof(uint32_t) + 1;
1506         }
1507 
1508         ret = of_property_match_string(np, "clock-names", "ipg");
1509         if (ret < 0) {
1510                 ssi_private->has_ipg_clk_name = false;
1511                 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1512                         &regconfig);
1513         } else {
1514                 ssi_private->has_ipg_clk_name = true;
1515                 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
1516                         "ipg", iomem, &regconfig);
1517         }
1518         if (IS_ERR(ssi_private->regs)) {
1519                 dev_err(&pdev->dev, "Failed to init register map\n");
1520                 return PTR_ERR(ssi_private->regs);
1521         }
1522 
1523         ssi_private->irq = platform_get_irq(pdev, 0);
1524         if (ssi_private->irq < 0) {
1525                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1526                 return ssi_private->irq;
1527         }
1528 
1529         /* Are the RX and the TX clocks locked? */
1530         if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1531                 if (!fsl_ssi_is_ac97(ssi_private))
1532                         ssi_private->cpu_dai_drv.symmetric_rates = 1;
1533 
1534                 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1535                 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1536         }
1537 
1538         /* Determine the FIFO depth. */
1539         iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1540         if (iprop)
1541                 ssi_private->fifo_depth = be32_to_cpup(iprop);
1542         else
1543                 /* Older 8610 DTs didn't have the fifo-depth property */
1544                 ssi_private->fifo_depth = 8;
1545 
1546         dev_set_drvdata(&pdev->dev, ssi_private);
1547 
1548         if (ssi_private->soc->imx) {
1549                 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1550                 if (ret)
1551                         return ret;
1552         }
1553 
1554         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1555                                               &ssi_private->cpu_dai_drv, 1);
1556         if (ret) {
1557                 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1558                 goto error_asoc_register;
1559         }
1560 
1561         if (ssi_private->use_dma) {
1562                 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1563                                         fsl_ssi_isr, 0, dev_name(&pdev->dev),
1564                                         ssi_private);
1565                 if (ret < 0) {
1566                         dev_err(&pdev->dev, "could not claim irq %u\n",
1567                                         ssi_private->irq);
1568                         goto error_asoc_register;
1569                 }
1570         }
1571 
1572         ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1573         if (ret)
1574                 goto error_asoc_register;
1575 
1576         /*
1577          * If codec-handle property is missing from SSI node, we assume
1578          * that the machine driver uses new binding which does not require
1579          * SSI driver to trigger machine driver's probe.
1580          */
1581         if (!of_get_property(np, "codec-handle", NULL))
1582                 goto done;
1583 
1584         /* Trigger the machine driver's probe function.  The platform driver
1585          * name of the machine driver is taken from /compatible property of the
1586          * device tree.  We also pass the address of the CPU DAI driver
1587          * structure.
1588          */
1589         sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1590         /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1591         p = strrchr(sprop, ',');
1592         if (p)
1593                 sprop = p + 1;
1594         snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1595         make_lowercase(name);
1596 
1597         ssi_private->pdev =
1598                 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1599         if (IS_ERR(ssi_private->pdev)) {
1600                 ret = PTR_ERR(ssi_private->pdev);
1601                 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1602                 goto error_sound_card;
1603         }
1604 
1605 done:
1606         if (ssi_private->dai_fmt)
1607                 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
1608                                      ssi_private->dai_fmt);
1609 
1610         if (fsl_ssi_is_ac97(ssi_private)) {
1611                 u32 ssi_idx;
1612 
1613                 ret = of_property_read_u32(np, "cell-index", &ssi_idx);
1614                 if (ret) {
1615                         dev_err(&pdev->dev, "cannot get SSI index property\n");
1616                         goto error_sound_card;
1617                 }
1618 
1619                 ssi_private->pdev =
1620                         platform_device_register_data(NULL,
1621                                         "ac97-codec", ssi_idx, NULL, 0);
1622                 if (IS_ERR(ssi_private->pdev)) {
1623                         ret = PTR_ERR(ssi_private->pdev);
1624                         dev_err(&pdev->dev,
1625                                 "failed to register AC97 codec platform: %d\n",
1626                                 ret);
1627                         goto error_sound_card;
1628                 }
1629         }
1630 
1631         return 0;
1632 
1633 error_sound_card:
1634         fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1635 
1636 error_asoc_register:
1637         if (ssi_private->soc->imx)
1638                 fsl_ssi_imx_clean(pdev, ssi_private);
1639 
1640         return ret;
1641 }
1642 
1643 static int fsl_ssi_remove(struct platform_device *pdev)
1644 {
1645         struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1646 
1647         fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1648 
1649         if (ssi_private->pdev)
1650                 platform_device_unregister(ssi_private->pdev);
1651 
1652         if (ssi_private->soc->imx)
1653                 fsl_ssi_imx_clean(pdev, ssi_private);
1654 
1655         if (fsl_ssi_is_ac97(ssi_private))
1656                 snd_soc_set_ac97_ops(NULL);
1657 
1658         return 0;
1659 }
1660 
1661 #ifdef CONFIG_PM_SLEEP
1662 static int fsl_ssi_suspend(struct device *dev)
1663 {
1664         struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1665         struct regmap *regs = ssi_private->regs;
1666 
1667         regmap_read(regs, CCSR_SSI_SFCSR,
1668                         &ssi_private->regcache_sfcsr);
1669         regmap_read(regs, CCSR_SSI_SACNT,
1670                         &ssi_private->regcache_sacnt);
1671 
1672         regcache_cache_only(regs, true);
1673         regcache_mark_dirty(regs);
1674 
1675         return 0;
1676 }
1677 
1678 static int fsl_ssi_resume(struct device *dev)
1679 {
1680         struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1681         struct regmap *regs = ssi_private->regs;
1682 
1683         regcache_cache_only(regs, false);
1684 
1685         regmap_update_bits(regs, CCSR_SSI_SFCSR,
1686                         CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
1687                         CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
1688                         ssi_private->regcache_sfcsr);
1689         regmap_write(regs, CCSR_SSI_SACNT,
1690                         ssi_private->regcache_sacnt);
1691 
1692         return regcache_sync(regs);
1693 }
1694 #endif /* CONFIG_PM_SLEEP */
1695 
1696 static const struct dev_pm_ops fsl_ssi_pm = {
1697         SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1698 };
1699 
1700 static struct platform_driver fsl_ssi_driver = {
1701         .driver = {
1702                 .name = "fsl-ssi-dai",
1703                 .of_match_table = fsl_ssi_ids,
1704                 .pm = &fsl_ssi_pm,
1705         },
1706         .probe = fsl_ssi_probe,
1707         .remove = fsl_ssi_remove,
1708 };
1709 
1710 module_platform_driver(fsl_ssi_driver);
1711 
1712 MODULE_ALIAS("platform:fsl-ssi-dai");
1713 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1714 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1715 MODULE_LICENSE("GPL v2");
1716 

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