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Linux/sound/soc/fsl/fsl_ssi.c

  1 /*
  2  * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
  3  *
  4  * Author: Timur Tabi <timur@freescale.com>
  5  *
  6  * Copyright 2007-2010 Freescale Semiconductor, Inc.
  7  *
  8  * This file is licensed under the terms of the GNU General Public License
  9  * version 2.  This program is licensed "as is" without any warranty of any
 10  * kind, whether express or implied.
 11  *
 12  *
 13  * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
 14  *
 15  * The i.MX SSI core has some nasty limitations in AC97 mode. While most
 16  * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
 17  * one FIFO which combines all valid receive slots. We cannot even select
 18  * which slots we want to receive. The WM9712 with which this driver
 19  * was developed with always sends GPIO status data in slot 12 which
 20  * we receive in our (PCM-) data stream. The only chance we have is to
 21  * manually skip this data in the FIQ handler. With sampling rates different
 22  * from 48000Hz not every frame has valid receive data, so the ratio
 23  * between pcm data and GPIO status data changes. Our FIQ handler is not
 24  * able to handle this, hence this driver only works with 48000Hz sampling
 25  * rate.
 26  * Reading and writing AC97 registers is another challenge. The core
 27  * provides us status bits when the read register is updated with *another*
 28  * value. When we read the same register two times (and the register still
 29  * contains the same value) these status bits are not set. We work
 30  * around this by not polling these bits but only wait a fixed delay.
 31  */
 32 
 33 #include <linux/init.h>
 34 #include <linux/io.h>
 35 #include <linux/module.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/clk.h>
 38 #include <linux/device.h>
 39 #include <linux/delay.h>
 40 #include <linux/slab.h>
 41 #include <linux/spinlock.h>
 42 #include <linux/of.h>
 43 #include <linux/of_address.h>
 44 #include <linux/of_irq.h>
 45 #include <linux/of_platform.h>
 46 
 47 #include <sound/core.h>
 48 #include <sound/pcm.h>
 49 #include <sound/pcm_params.h>
 50 #include <sound/initval.h>
 51 #include <sound/soc.h>
 52 #include <sound/dmaengine_pcm.h>
 53 
 54 #include "fsl_ssi.h"
 55 #include "imx-pcm.h"
 56 
 57 /**
 58  * FSLSSI_I2S_RATES: sample rates supported by the I2S
 59  *
 60  * This driver currently only supports the SSI running in I2S slave mode,
 61  * which means the codec determines the sample rate.  Therefore, we tell
 62  * ALSA that we support all rates and let the codec driver decide what rates
 63  * are really supported.
 64  */
 65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
 66 
 67 /**
 68  * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
 69  *
 70  * The SSI has a limitation in that the samples must be in the same byte
 71  * order as the host CPU.  This is because when multiple bytes are written
 72  * to the STX register, the bytes and bits must be written in the same
 73  * order.  The STX is a shift register, so all the bits need to be aligned
 74  * (bit-endianness must match byte-endianness).  Processors typically write
 75  * the bits within a byte in the same order that the bytes of a word are
 76  * written in.  So if the host CPU is big-endian, then only big-endian
 77  * samples will be written to STX properly.
 78  */
 79 #ifdef __BIG_ENDIAN
 80 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
 81          SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
 82          SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
 83 #else
 84 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
 85          SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 86          SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
 87 #endif
 88 
 89 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
 90                 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
 91                 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
 92 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
 93                 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
 94                 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
 95 
 96 enum fsl_ssi_type {
 97         FSL_SSI_MCP8610,
 98         FSL_SSI_MX21,
 99         FSL_SSI_MX35,
100         FSL_SSI_MX51,
101 };
102 
103 struct fsl_ssi_reg_val {
104         u32 sier;
105         u32 srcr;
106         u32 stcr;
107         u32 scr;
108 };
109 
110 struct fsl_ssi_rxtx_reg_val {
111         struct fsl_ssi_reg_val rx;
112         struct fsl_ssi_reg_val tx;
113 };
114 
115 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
116 {
117         switch (reg) {
118         case CCSR_SSI_SACCEN:
119         case CCSR_SSI_SACCDIS:
120                 return false;
121         default:
122                 return true;
123         }
124 }
125 
126 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
127 {
128         switch (reg) {
129         case CCSR_SSI_STX0:
130         case CCSR_SSI_STX1:
131         case CCSR_SSI_SRX0:
132         case CCSR_SSI_SRX1:
133         case CCSR_SSI_SISR:
134         case CCSR_SSI_SFCSR:
135         case CCSR_SSI_SACNT:
136         case CCSR_SSI_SACADD:
137         case CCSR_SSI_SACDAT:
138         case CCSR_SSI_SATAG:
139         case CCSR_SSI_SACCST:
140                 return true;
141         default:
142                 return false;
143         }
144 }
145 
146 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
147 {
148         switch (reg) {
149         case CCSR_SSI_SRX0:
150         case CCSR_SSI_SRX1:
151         case CCSR_SSI_SISR:
152         case CCSR_SSI_SACADD:
153         case CCSR_SSI_SACDAT:
154         case CCSR_SSI_SATAG:
155                 return true;
156         default:
157                 return false;
158         }
159 }
160 
161 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
162 {
163         switch (reg) {
164         case CCSR_SSI_SRX0:
165         case CCSR_SSI_SRX1:
166         case CCSR_SSI_SACCST:
167                 return false;
168         default:
169                 return true;
170         }
171 }
172 
173 static const struct regmap_config fsl_ssi_regconfig = {
174         .max_register = CCSR_SSI_SACCDIS,
175         .reg_bits = 32,
176         .val_bits = 32,
177         .reg_stride = 4,
178         .val_format_endian = REGMAP_ENDIAN_NATIVE,
179         .num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1,
180         .readable_reg = fsl_ssi_readable_reg,
181         .volatile_reg = fsl_ssi_volatile_reg,
182         .precious_reg = fsl_ssi_precious_reg,
183         .writeable_reg = fsl_ssi_writeable_reg,
184         .cache_type = REGCACHE_RBTREE,
185 };
186 
187 struct fsl_ssi_soc_data {
188         bool imx;
189         bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
190         bool offline_config;
191         u32 sisr_write_mask;
192 };
193 
194 /**
195  * fsl_ssi_private: per-SSI private data
196  *
197  * @reg: Pointer to the regmap registers
198  * @irq: IRQ of this SSI
199  * @cpu_dai_drv: CPU DAI driver for this device
200  *
201  * @dai_fmt: DAI configuration this device is currently used with
202  * @i2s_mode: i2s and network mode configuration of the device. Is used to
203  * switch between normal and i2s/network mode
204  * mode depending on the number of channels
205  * @use_dma: DMA is used or FIQ with stream filter
206  * @use_dual_fifo: DMA with support for both FIFOs used
207  * @fifo_deph: Depth of the SSI FIFOs
208  * @rxtx_reg_val: Specific register settings for receive/transmit configuration
209  *
210  * @clk: SSI clock
211  * @baudclk: SSI baud clock for master mode
212  * @baudclk_streams: Active streams that are using baudclk
213  * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
214  *
215  * @dma_params_tx: DMA transmit parameters
216  * @dma_params_rx: DMA receive parameters
217  * @ssi_phys: physical address of the SSI registers
218  *
219  * @fiq_params: FIQ stream filtering parameters
220  *
221  * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
222  *
223  * @dbg_stats: Debugging statistics
224  *
225  * @soc: SoC specific data
226  */
227 struct fsl_ssi_private {
228         struct regmap *regs;
229         int irq;
230         struct snd_soc_dai_driver cpu_dai_drv;
231 
232         unsigned int dai_fmt;
233         u8 i2s_mode;
234         bool use_dma;
235         bool use_dual_fifo;
236         bool has_ipg_clk_name;
237         unsigned int fifo_depth;
238         struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
239 
240         struct clk *clk;
241         struct clk *baudclk;
242         unsigned int baudclk_streams;
243         unsigned int bitclk_freq;
244 
245         /* regcache for volatile regs */
246         u32 regcache_sfcsr;
247         u32 regcache_sacnt;
248 
249         /* DMA params */
250         struct snd_dmaengine_dai_dma_data dma_params_tx;
251         struct snd_dmaengine_dai_dma_data dma_params_rx;
252         dma_addr_t ssi_phys;
253 
254         /* params for non-dma FIQ stream filtered mode */
255         struct imx_pcm_fiq_params fiq_params;
256 
257         /* Used when using fsl-ssi as sound-card. This is only used by ppc and
258          * should be replaced with simple-sound-card. */
259         struct platform_device *pdev;
260 
261         struct fsl_ssi_dbg dbg_stats;
262 
263         const struct fsl_ssi_soc_data *soc;
264 };
265 
266 /*
267  * imx51 and later SoCs have a slightly different IP that allows the
268  * SSI configuration while the SSI unit is running.
269  *
270  * More important, it is necessary on those SoCs to configure the
271  * sperate TX/RX DMA bits just before starting the stream
272  * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
273  * sends any DMA requests to the SDMA unit, otherwise it is not defined
274  * how the SDMA unit handles the DMA request.
275  *
276  * SDMA units are present on devices starting at imx35 but the imx35
277  * reference manual states that the DMA bits should not be changed
278  * while the SSI unit is running (SSIEN). So we support the necessary
279  * online configuration of fsl-ssi starting at imx51.
280  */
281 
282 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
283         .imx = false,
284         .offline_config = true,
285         .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
286                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
287                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
288 };
289 
290 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
291         .imx = true,
292         .imx21regs = true,
293         .offline_config = true,
294         .sisr_write_mask = 0,
295 };
296 
297 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
298         .imx = true,
299         .offline_config = true,
300         .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
301                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
302                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
303 };
304 
305 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
306         .imx = true,
307         .offline_config = false,
308         .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
309                 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
310 };
311 
312 static const struct of_device_id fsl_ssi_ids[] = {
313         { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
314         { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
315         { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
316         { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
317         {}
318 };
319 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
320 
321 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
322 {
323         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
324                 SND_SOC_DAIFMT_AC97;
325 }
326 
327 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
328 {
329         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
330                 SND_SOC_DAIFMT_CBS_CFS;
331 }
332 
333 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private)
334 {
335         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
336                 SND_SOC_DAIFMT_CBM_CFS;
337 }
338 /**
339  * fsl_ssi_isr: SSI interrupt handler
340  *
341  * Although it's possible to use the interrupt handler to send and receive
342  * data to/from the SSI, we use the DMA instead.  Programming is more
343  * complicated, but the performance is much better.
344  *
345  * This interrupt handler is used only to gather statistics.
346  *
347  * @irq: IRQ of the SSI device
348  * @dev_id: pointer to the ssi_private structure for this SSI device
349  */
350 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
351 {
352         struct fsl_ssi_private *ssi_private = dev_id;
353         struct regmap *regs = ssi_private->regs;
354         __be32 sisr;
355         __be32 sisr2;
356 
357         /* We got an interrupt, so read the status register to see what we
358            were interrupted for.  We mask it with the Interrupt Enable register
359            so that we only check for events that we're interested in.
360          */
361         regmap_read(regs, CCSR_SSI_SISR, &sisr);
362 
363         sisr2 = sisr & ssi_private->soc->sisr_write_mask;
364         /* Clear the bits that we set */
365         if (sisr2)
366                 regmap_write(regs, CCSR_SSI_SISR, sisr2);
367 
368         fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
369 
370         return IRQ_HANDLED;
371 }
372 
373 /*
374  * Enable/Disable all rx/tx config flags at once.
375  */
376 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
377                 bool enable)
378 {
379         struct regmap *regs = ssi_private->regs;
380         struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
381 
382         if (enable) {
383                 regmap_update_bits(regs, CCSR_SSI_SIER,
384                                 vals->rx.sier | vals->tx.sier,
385                                 vals->rx.sier | vals->tx.sier);
386                 regmap_update_bits(regs, CCSR_SSI_SRCR,
387                                 vals->rx.srcr | vals->tx.srcr,
388                                 vals->rx.srcr | vals->tx.srcr);
389                 regmap_update_bits(regs, CCSR_SSI_STCR,
390                                 vals->rx.stcr | vals->tx.stcr,
391                                 vals->rx.stcr | vals->tx.stcr);
392         } else {
393                 regmap_update_bits(regs, CCSR_SSI_SRCR,
394                                 vals->rx.srcr | vals->tx.srcr, 0);
395                 regmap_update_bits(regs, CCSR_SSI_STCR,
396                                 vals->rx.stcr | vals->tx.stcr, 0);
397                 regmap_update_bits(regs, CCSR_SSI_SIER,
398                                 vals->rx.sier | vals->tx.sier, 0);
399         }
400 }
401 
402 /*
403  * Calculate the bits that have to be disabled for the current stream that is
404  * getting disabled. This keeps the bits enabled that are necessary for the
405  * second stream to work if 'stream_active' is true.
406  *
407  * Detailed calculation:
408  * These are the values that need to be active after disabling. For non-active
409  * second stream, this is 0:
410  *      vals_stream * !!stream_active
411  *
412  * The following computes the overall differences between the setup for the
413  * to-disable stream and the active stream, a simple XOR:
414  *      vals_disable ^ (vals_stream * !!(stream_active))
415  *
416  * The full expression adds a mask on all values we care about
417  */
418 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
419         ((vals_disable) & \
420          ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
421 
422 /*
423  * Enable/Disable a ssi configuration. You have to pass either
424  * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
425  */
426 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
427                 struct fsl_ssi_reg_val *vals)
428 {
429         struct regmap *regs = ssi_private->regs;
430         struct fsl_ssi_reg_val *avals;
431         int nr_active_streams;
432         u32 scr_val;
433         int keep_active;
434 
435         regmap_read(regs, CCSR_SSI_SCR, &scr_val);
436 
437         nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
438                                 !!(scr_val & CCSR_SSI_SCR_RE);
439 
440         if (nr_active_streams - 1 > 0)
441                 keep_active = 1;
442         else
443                 keep_active = 0;
444 
445         /* Find the other direction values rx or tx which we do not want to
446          * modify */
447         if (&ssi_private->rxtx_reg_val.rx == vals)
448                 avals = &ssi_private->rxtx_reg_val.tx;
449         else
450                 avals = &ssi_private->rxtx_reg_val.rx;
451 
452         /* If vals should be disabled, start with disabling the unit */
453         if (!enable) {
454                 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
455                                 keep_active);
456                 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
457         }
458 
459         /*
460          * We are running on a SoC which does not support online SSI
461          * reconfiguration, so we have to enable all necessary flags at once
462          * even if we do not use them later (capture and playback configuration)
463          */
464         if (ssi_private->soc->offline_config) {
465                 if ((enable && !nr_active_streams) ||
466                                 (!enable && !keep_active))
467                         fsl_ssi_rxtx_config(ssi_private, enable);
468 
469                 goto config_done;
470         }
471 
472         /*
473          * Configure single direction units while the SSI unit is running
474          * (online configuration)
475          */
476         if (enable) {
477                 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
478                 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
479                 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
480         } else {
481                 u32 sier;
482                 u32 srcr;
483                 u32 stcr;
484 
485                 /*
486                  * Disabling the necessary flags for one of rx/tx while the
487                  * other stream is active is a little bit more difficult. We
488                  * have to disable only those flags that differ between both
489                  * streams (rx XOR tx) and that are set in the stream that is
490                  * disabled now. Otherwise we could alter flags of the other
491                  * stream
492                  */
493 
494                 /* These assignments are simply vals without bits set in avals*/
495                 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
496                                 keep_active);
497                 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
498                                 keep_active);
499                 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
500                                 keep_active);
501 
502                 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
503                 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
504                 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
505         }
506 
507 config_done:
508         /* Enabling of subunits is done after configuration */
509         if (enable)
510                 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
511 }
512 
513 
514 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
515 {
516         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
517 }
518 
519 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
520 {
521         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
522 }
523 
524 /*
525  * Setup rx/tx register values used to enable/disable the streams. These will
526  * be used later in fsl_ssi_config to setup the streams without the need to
527  * check for all different SSI modes.
528  */
529 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
530 {
531         struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
532 
533         reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
534         reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
535         reg->rx.scr = 0;
536         reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
537         reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
538         reg->tx.scr = 0;
539 
540         if (!fsl_ssi_is_ac97(ssi_private)) {
541                 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
542                 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
543                 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
544                 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
545         }
546 
547         if (ssi_private->use_dma) {
548                 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
549                 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
550         } else {
551                 reg->rx.sier |= CCSR_SSI_SIER_RIE;
552                 reg->tx.sier |= CCSR_SSI_SIER_TIE;
553         }
554 
555         reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
556         reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
557 }
558 
559 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
560 {
561         struct regmap *regs = ssi_private->regs;
562 
563         /*
564          * Setup the clock control register
565          */
566         regmap_write(regs, CCSR_SSI_STCCR,
567                         CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
568         regmap_write(regs, CCSR_SSI_SRCCR,
569                         CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
570 
571         /*
572          * Enable AC97 mode and startup the SSI
573          */
574         regmap_write(regs, CCSR_SSI_SACNT,
575                         CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
576 
577         /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
578         if (!ssi_private->soc->imx21regs) {
579                 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
580                 regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
581         }
582 
583         /*
584          * Enable SSI, Transmit and Receive. AC97 has to communicate with the
585          * codec before a stream is started.
586          */
587         regmap_update_bits(regs, CCSR_SSI_SCR,
588                         CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
589                         CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
590 
591         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
592 }
593 
594 /**
595  * fsl_ssi_startup: create a new substream
596  *
597  * This is the first function called when a stream is opened.
598  *
599  * If this is the first stream open, then grab the IRQ and program most of
600  * the SSI registers.
601  */
602 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
603                            struct snd_soc_dai *dai)
604 {
605         struct snd_soc_pcm_runtime *rtd = substream->private_data;
606         struct fsl_ssi_private *ssi_private =
607                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
608         int ret;
609 
610         ret = clk_prepare_enable(ssi_private->clk);
611         if (ret)
612                 return ret;
613 
614         /* When using dual fifo mode, it is safer to ensure an even period
615          * size. If appearing to an odd number while DMA always starts its
616          * task from fifo0, fifo1 would be neglected at the end of each
617          * period. But SSI would still access fifo1 with an invalid data.
618          */
619         if (ssi_private->use_dual_fifo)
620                 snd_pcm_hw_constraint_step(substream->runtime, 0,
621                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
622 
623         return 0;
624 }
625 
626 /**
627  * fsl_ssi_shutdown: shutdown the SSI
628  *
629  */
630 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
631                                 struct snd_soc_dai *dai)
632 {
633         struct snd_soc_pcm_runtime *rtd = substream->private_data;
634         struct fsl_ssi_private *ssi_private =
635                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
636 
637         clk_disable_unprepare(ssi_private->clk);
638 
639 }
640 
641 /**
642  * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
643  *
644  * Note: This function can be only called when using SSI as DAI master
645  *
646  * Quick instruction for parameters:
647  * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
648  * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
649  */
650 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
651                 struct snd_soc_dai *cpu_dai,
652                 struct snd_pcm_hw_params *hw_params)
653 {
654         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
655         struct regmap *regs = ssi_private->regs;
656         int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
657         u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
658         unsigned long clkrate, baudrate, tmprate;
659         u64 sub, savesub = 100000;
660         unsigned int freq;
661         bool baudclk_is_used;
662 
663         /* Prefer the explicitly set bitclock frequency */
664         if (ssi_private->bitclk_freq)
665                 freq = ssi_private->bitclk_freq;
666         else
667                 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
668 
669         /* Don't apply it to any non-baudclk circumstance */
670         if (IS_ERR(ssi_private->baudclk))
671                 return -EINVAL;
672 
673         baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
674 
675         /* It should be already enough to divide clock by setting pm alone */
676         psr = 0;
677         div2 = 0;
678 
679         factor = (div2 + 1) * (7 * psr + 1) * 2;
680 
681         for (i = 0; i < 255; i++) {
682                 tmprate = freq * factor * (i + 1);
683 
684                 if (baudclk_is_used)
685                         clkrate = clk_get_rate(ssi_private->baudclk);
686                 else
687                         clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
688 
689                 /*
690                  * Hardware limitation: The bclk rate must be
691                  * never greater than 1/5 IPG clock rate
692                  */
693                 if (clkrate * 5 > clk_get_rate(ssi_private->clk))
694                         continue;
695 
696                 clkrate /= factor;
697                 afreq = clkrate / (i + 1);
698 
699                 if (freq == afreq)
700                         sub = 0;
701                 else if (freq / afreq == 1)
702                         sub = freq - afreq;
703                 else if (afreq / freq == 1)
704                         sub = afreq - freq;
705                 else
706                         continue;
707 
708                 /* Calculate the fraction */
709                 sub *= 100000;
710                 do_div(sub, freq);
711 
712                 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
713                         baudrate = tmprate;
714                         savesub = sub;
715                         pm = i;
716                 }
717 
718                 /* We are lucky */
719                 if (savesub == 0)
720                         break;
721         }
722 
723         /* No proper pm found if it is still remaining the initial value */
724         if (pm == 999) {
725                 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
726                 return -EINVAL;
727         }
728 
729         stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
730                 (psr ? CCSR_SSI_SxCCR_PSR : 0);
731         mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
732                 CCSR_SSI_SxCCR_PSR;
733 
734         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
735                 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
736         else
737                 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
738 
739         if (!baudclk_is_used) {
740                 ret = clk_set_rate(ssi_private->baudclk, baudrate);
741                 if (ret) {
742                         dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
743                         return -EINVAL;
744                 }
745         }
746 
747         return 0;
748 }
749 
750 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
751                 int clk_id, unsigned int freq, int dir)
752 {
753         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
754 
755         ssi_private->bitclk_freq = freq;
756 
757         return 0;
758 }
759 
760 /**
761  * fsl_ssi_hw_params - program the sample size
762  *
763  * Most of the SSI registers have been programmed in the startup function,
764  * but the word length must be programmed here.  Unfortunately, programming
765  * the SxCCR.WL bits requires the SSI to be temporarily disabled.  This can
766  * cause a problem with supporting simultaneous playback and capture.  If
767  * the SSI is already playing a stream, then that stream may be temporarily
768  * stopped when you start capture.
769  *
770  * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
771  * clock master.
772  */
773 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
774         struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
775 {
776         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
777         struct regmap *regs = ssi_private->regs;
778         unsigned int channels = params_channels(hw_params);
779         unsigned int sample_size = params_width(hw_params);
780         u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
781         int ret;
782         u32 scr_val;
783         int enabled;
784 
785         regmap_read(regs, CCSR_SSI_SCR, &scr_val);
786         enabled = scr_val & CCSR_SSI_SCR_SSIEN;
787 
788         /*
789          * If we're in synchronous mode, and the SSI is already enabled,
790          * then STCCR is already set properly.
791          */
792         if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
793                 return 0;
794 
795         if (fsl_ssi_is_i2s_master(ssi_private)) {
796                 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
797                 if (ret)
798                         return ret;
799 
800                 /* Do not enable the clock if it is already enabled */
801                 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
802                         ret = clk_prepare_enable(ssi_private->baudclk);
803                         if (ret)
804                                 return ret;
805 
806                         ssi_private->baudclk_streams |= BIT(substream->stream);
807                 }
808         }
809 
810         if (!fsl_ssi_is_ac97(ssi_private)) {
811                 u8 i2smode;
812                 /*
813                  * Switch to normal net mode in order to have a frame sync
814                  * signal every 32 bits instead of 16 bits
815                  */
816                 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16)
817                         i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL |
818                                 CCSR_SSI_SCR_NET;
819                 else
820                         i2smode = ssi_private->i2s_mode;
821 
822                 regmap_update_bits(regs, CCSR_SSI_SCR,
823                                 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
824                                 channels == 1 ? 0 : i2smode);
825         }
826 
827         /*
828          * FIXME: The documentation says that SxCCR[WL] should not be
829          * modified while the SSI is enabled.  The only time this can
830          * happen is if we're trying to do simultaneous playback and
831          * capture in asynchronous mode.  Unfortunately, I have been enable
832          * to get that to work at all on the P1022DS.  Therefore, we don't
833          * bother to disable/enable the SSI when setting SxCCR[WL], because
834          * the SSI will stop anyway.  Maybe one day, this will get fixed.
835          */
836 
837         /* In synchronous mode, the SSI uses STCCR for capture */
838         if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
839             ssi_private->cpu_dai_drv.symmetric_rates)
840                 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
841                                 wl);
842         else
843                 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
844                                 wl);
845 
846         return 0;
847 }
848 
849 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
850                 struct snd_soc_dai *cpu_dai)
851 {
852         struct snd_soc_pcm_runtime *rtd = substream->private_data;
853         struct fsl_ssi_private *ssi_private =
854                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
855 
856         if (fsl_ssi_is_i2s_master(ssi_private) &&
857                         ssi_private->baudclk_streams & BIT(substream->stream)) {
858                 clk_disable_unprepare(ssi_private->baudclk);
859                 ssi_private->baudclk_streams &= ~BIT(substream->stream);
860         }
861 
862         return 0;
863 }
864 
865 static int _fsl_ssi_set_dai_fmt(struct device *dev,
866                                 struct fsl_ssi_private *ssi_private,
867                                 unsigned int fmt)
868 {
869         struct regmap *regs = ssi_private->regs;
870         u32 strcr = 0, stcr, srcr, scr, mask;
871         u8 wm;
872 
873         ssi_private->dai_fmt = fmt;
874 
875         if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
876                 dev_err(dev, "baudclk is missing which is necessary for master mode\n");
877                 return -EINVAL;
878         }
879 
880         fsl_ssi_setup_reg_vals(ssi_private);
881 
882         regmap_read(regs, CCSR_SSI_SCR, &scr);
883         scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
884         scr |= CCSR_SSI_SCR_SYNC_TX_FS;
885 
886         mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
887                 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
888                 CCSR_SSI_STCR_TEFS;
889         regmap_read(regs, CCSR_SSI_STCR, &stcr);
890         regmap_read(regs, CCSR_SSI_SRCR, &srcr);
891         stcr &= ~mask;
892         srcr &= ~mask;
893 
894         ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
895         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
896         case SND_SOC_DAIFMT_I2S:
897                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
898                 case SND_SOC_DAIFMT_CBM_CFS:
899                 case SND_SOC_DAIFMT_CBS_CFS:
900                         ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
901                         regmap_update_bits(regs, CCSR_SSI_STCCR,
902                                         CCSR_SSI_SxCCR_DC_MASK,
903                                         CCSR_SSI_SxCCR_DC(2));
904                         regmap_update_bits(regs, CCSR_SSI_SRCCR,
905                                         CCSR_SSI_SxCCR_DC_MASK,
906                                         CCSR_SSI_SxCCR_DC(2));
907                         break;
908                 case SND_SOC_DAIFMT_CBM_CFM:
909                         ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
910                         break;
911                 default:
912                         return -EINVAL;
913                 }
914 
915                 /* Data on rising edge of bclk, frame low, 1clk before data */
916                 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
917                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
918                 break;
919         case SND_SOC_DAIFMT_LEFT_J:
920                 /* Data on rising edge of bclk, frame high */
921                 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
922                 break;
923         case SND_SOC_DAIFMT_DSP_A:
924                 /* Data on rising edge of bclk, frame high, 1clk before data */
925                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
926                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
927                 break;
928         case SND_SOC_DAIFMT_DSP_B:
929                 /* Data on rising edge of bclk, frame high */
930                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
931                         CCSR_SSI_STCR_TXBIT0;
932                 break;
933         case SND_SOC_DAIFMT_AC97:
934                 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
935                 break;
936         default:
937                 return -EINVAL;
938         }
939         scr |= ssi_private->i2s_mode;
940 
941         /* DAI clock inversion */
942         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
943         case SND_SOC_DAIFMT_NB_NF:
944                 /* Nothing to do for both normal cases */
945                 break;
946         case SND_SOC_DAIFMT_IB_NF:
947                 /* Invert bit clock */
948                 strcr ^= CCSR_SSI_STCR_TSCKP;
949                 break;
950         case SND_SOC_DAIFMT_NB_IF:
951                 /* Invert frame clock */
952                 strcr ^= CCSR_SSI_STCR_TFSI;
953                 break;
954         case SND_SOC_DAIFMT_IB_IF:
955                 /* Invert both clocks */
956                 strcr ^= CCSR_SSI_STCR_TSCKP;
957                 strcr ^= CCSR_SSI_STCR_TFSI;
958                 break;
959         default:
960                 return -EINVAL;
961         }
962 
963         /* DAI clock master masks */
964         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
965         case SND_SOC_DAIFMT_CBS_CFS:
966                 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
967                 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
968                 break;
969         case SND_SOC_DAIFMT_CBM_CFM:
970                 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
971                 break;
972         case SND_SOC_DAIFMT_CBM_CFS:
973                 strcr &= ~CCSR_SSI_STCR_TXDIR;
974                 strcr |= CCSR_SSI_STCR_TFDIR;
975                 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
976                 break;
977         default:
978                 if (!fsl_ssi_is_ac97(ssi_private))
979                         return -EINVAL;
980         }
981 
982         stcr |= strcr;
983         srcr |= strcr;
984 
985         if (ssi_private->cpu_dai_drv.symmetric_rates
986                         || fsl_ssi_is_ac97(ssi_private)) {
987                 /* Need to clear RXDIR when using SYNC or AC97 mode */
988                 srcr &= ~CCSR_SSI_SRCR_RXDIR;
989                 scr |= CCSR_SSI_SCR_SYN;
990         }
991 
992         regmap_write(regs, CCSR_SSI_STCR, stcr);
993         regmap_write(regs, CCSR_SSI_SRCR, srcr);
994         regmap_write(regs, CCSR_SSI_SCR, scr);
995 
996         /*
997          * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
998          * use FIFO 1. We program the transmit water to signal a DMA transfer
999          * if there are only two (or fewer) elements left in the FIFO. Two
1000          * elements equals one frame (left channel, right channel). This value,
1001          * however, depends on the depth of the transmit buffer.
1002          *
1003          * We set the watermark on the same level as the DMA burstsize.  For
1004          * fiq it is probably better to use the biggest possible watermark
1005          * size.
1006          */
1007         if (ssi_private->use_dma)
1008                 wm = ssi_private->fifo_depth - 2;
1009         else
1010                 wm = ssi_private->fifo_depth;
1011 
1012         regmap_write(regs, CCSR_SSI_SFCSR,
1013                         CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
1014                         CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
1015 
1016         if (ssi_private->use_dual_fifo) {
1017                 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
1018                                 CCSR_SSI_SRCR_RFEN1);
1019                 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
1020                                 CCSR_SSI_STCR_TFEN1);
1021                 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
1022                                 CCSR_SSI_SCR_TCH_EN);
1023         }
1024 
1025         if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)
1026                 fsl_ssi_setup_ac97(ssi_private);
1027 
1028         return 0;
1029 
1030 }
1031 
1032 /**
1033  * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
1034  */
1035 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
1036 {
1037         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1038 
1039         return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
1040 }
1041 
1042 /**
1043  * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1044  *
1045  * Note: This function can be only called when using SSI as DAI master
1046  */
1047 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1048                                 u32 rx_mask, int slots, int slot_width)
1049 {
1050         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1051         struct regmap *regs = ssi_private->regs;
1052         u32 val;
1053 
1054         /* The slot number should be >= 2 if using Network mode or I2S mode */
1055         regmap_read(regs, CCSR_SSI_SCR, &val);
1056         val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
1057         if (val && slots < 2) {
1058                 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1059                 return -EINVAL;
1060         }
1061 
1062         regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
1063                         CCSR_SSI_SxCCR_DC(slots));
1064         regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
1065                         CCSR_SSI_SxCCR_DC(slots));
1066 
1067         /* The register SxMSKs needs SSI to provide essential clock due to
1068          * hardware design. So we here temporarily enable SSI to set them.
1069          */
1070         regmap_read(regs, CCSR_SSI_SCR, &val);
1071         val &= CCSR_SSI_SCR_SSIEN;
1072         regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
1073                         CCSR_SSI_SCR_SSIEN);
1074 
1075         regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask);
1076         regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask);
1077 
1078         regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
1079 
1080         return 0;
1081 }
1082 
1083 /**
1084  * fsl_ssi_trigger: start and stop the DMA transfer.
1085  *
1086  * This function is called by ALSA to start, stop, pause, and resume the DMA
1087  * transfer of data.
1088  *
1089  * The DMA channel is in external master start and pause mode, which
1090  * means the SSI completely controls the flow of data.
1091  */
1092 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1093                            struct snd_soc_dai *dai)
1094 {
1095         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1096         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1097         struct regmap *regs = ssi_private->regs;
1098 
1099         switch (cmd) {
1100         case SNDRV_PCM_TRIGGER_START:
1101         case SNDRV_PCM_TRIGGER_RESUME:
1102         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1103                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1104                         fsl_ssi_tx_config(ssi_private, true);
1105                 else
1106                         fsl_ssi_rx_config(ssi_private, true);
1107                 break;
1108 
1109         case SNDRV_PCM_TRIGGER_STOP:
1110         case SNDRV_PCM_TRIGGER_SUSPEND:
1111         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1112                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1113                         fsl_ssi_tx_config(ssi_private, false);
1114                 else
1115                         fsl_ssi_rx_config(ssi_private, false);
1116                 break;
1117 
1118         default:
1119                 return -EINVAL;
1120         }
1121 
1122         if (fsl_ssi_is_ac97(ssi_private)) {
1123                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1124                         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1125                 else
1126                         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1127         }
1128 
1129         return 0;
1130 }
1131 
1132 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1133 {
1134         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1135 
1136         if (ssi_private->soc->imx && ssi_private->use_dma) {
1137                 dai->playback_dma_data = &ssi_private->dma_params_tx;
1138                 dai->capture_dma_data = &ssi_private->dma_params_rx;
1139         }
1140 
1141         return 0;
1142 }
1143 
1144 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1145         .startup        = fsl_ssi_startup,
1146         .shutdown       = fsl_ssi_shutdown,
1147         .hw_params      = fsl_ssi_hw_params,
1148         .hw_free        = fsl_ssi_hw_free,
1149         .set_fmt        = fsl_ssi_set_dai_fmt,
1150         .set_sysclk     = fsl_ssi_set_dai_sysclk,
1151         .set_tdm_slot   = fsl_ssi_set_dai_tdm_slot,
1152         .trigger        = fsl_ssi_trigger,
1153 };
1154 
1155 /* Template for the CPU dai driver structure */
1156 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1157         .probe = fsl_ssi_dai_probe,
1158         .playback = {
1159                 .stream_name = "CPU-Playback",
1160                 .channels_min = 1,
1161                 .channels_max = 2,
1162                 .rates = FSLSSI_I2S_RATES,
1163                 .formats = FSLSSI_I2S_FORMATS,
1164         },
1165         .capture = {
1166                 .stream_name = "CPU-Capture",
1167                 .channels_min = 1,
1168                 .channels_max = 2,
1169                 .rates = FSLSSI_I2S_RATES,
1170                 .formats = FSLSSI_I2S_FORMATS,
1171         },
1172         .ops = &fsl_ssi_dai_ops,
1173 };
1174 
1175 static const struct snd_soc_component_driver fsl_ssi_component = {
1176         .name           = "fsl-ssi",
1177 };
1178 
1179 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1180         .bus_control = true,
1181         .probe = fsl_ssi_dai_probe,
1182         .playback = {
1183                 .stream_name = "AC97 Playback",
1184                 .channels_min = 2,
1185                 .channels_max = 2,
1186                 .rates = SNDRV_PCM_RATE_8000_48000,
1187                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1188         },
1189         .capture = {
1190                 .stream_name = "AC97 Capture",
1191                 .channels_min = 2,
1192                 .channels_max = 2,
1193                 .rates = SNDRV_PCM_RATE_48000,
1194                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1195         },
1196         .ops = &fsl_ssi_dai_ops,
1197 };
1198 
1199 
1200 static struct fsl_ssi_private *fsl_ac97_data;
1201 
1202 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1203                 unsigned short val)
1204 {
1205         struct regmap *regs = fsl_ac97_data->regs;
1206         unsigned int lreg;
1207         unsigned int lval;
1208         int ret;
1209 
1210         if (reg > 0x7f)
1211                 return;
1212 
1213         ret = clk_prepare_enable(fsl_ac97_data->clk);
1214         if (ret) {
1215                 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1216                         ret);
1217                 return;
1218         }
1219 
1220         lreg = reg <<  12;
1221         regmap_write(regs, CCSR_SSI_SACADD, lreg);
1222 
1223         lval = val << 4;
1224         regmap_write(regs, CCSR_SSI_SACDAT, lval);
1225 
1226         regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1227                         CCSR_SSI_SACNT_WR);
1228         udelay(100);
1229 
1230         clk_disable_unprepare(fsl_ac97_data->clk);
1231 }
1232 
1233 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1234                 unsigned short reg)
1235 {
1236         struct regmap *regs = fsl_ac97_data->regs;
1237 
1238         unsigned short val = -1;
1239         u32 reg_val;
1240         unsigned int lreg;
1241         int ret;
1242 
1243         ret = clk_prepare_enable(fsl_ac97_data->clk);
1244         if (ret) {
1245                 pr_err("ac97 read clk_prepare_enable failed: %d\n",
1246                         ret);
1247                 return -1;
1248         }
1249 
1250         lreg = (reg & 0x7f) <<  12;
1251         regmap_write(regs, CCSR_SSI_SACADD, lreg);
1252         regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1253                         CCSR_SSI_SACNT_RD);
1254 
1255         udelay(100);
1256 
1257         regmap_read(regs, CCSR_SSI_SACDAT, &reg_val);
1258         val = (reg_val >> 4) & 0xffff;
1259 
1260         clk_disable_unprepare(fsl_ac97_data->clk);
1261 
1262         return val;
1263 }
1264 
1265 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1266         .read           = fsl_ssi_ac97_read,
1267         .write          = fsl_ssi_ac97_write,
1268 };
1269 
1270 /**
1271  * Make every character in a string lower-case
1272  */
1273 static void make_lowercase(char *s)
1274 {
1275         char *p = s;
1276         char c;
1277 
1278         while ((c = *p)) {
1279                 if ((c >= 'A') && (c <= 'Z'))
1280                         *p = c + ('a' - 'A');
1281                 p++;
1282         }
1283 }
1284 
1285 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1286                 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1287 {
1288         struct device_node *np = pdev->dev.of_node;
1289         u32 dmas[4];
1290         int ret;
1291 
1292         if (ssi_private->has_ipg_clk_name)
1293                 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
1294         else
1295                 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1296         if (IS_ERR(ssi_private->clk)) {
1297                 ret = PTR_ERR(ssi_private->clk);
1298                 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1299                 return ret;
1300         }
1301 
1302         if (!ssi_private->has_ipg_clk_name) {
1303                 ret = clk_prepare_enable(ssi_private->clk);
1304                 if (ret) {
1305                         dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1306                         return ret;
1307                 }
1308         }
1309 
1310         /* For those SLAVE implementations, we ignore non-baudclk cases
1311          * and, instead, abandon MASTER mode that needs baud clock.
1312          */
1313         ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1314         if (IS_ERR(ssi_private->baudclk))
1315                 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1316                          PTR_ERR(ssi_private->baudclk));
1317 
1318         /*
1319          * We have burstsize be "fifo_depth - 2" to match the SSI
1320          * watermark setting in fsl_ssi_startup().
1321          */
1322         ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1323         ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1324         ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1325         ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1326 
1327         ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1328         if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1329                 ssi_private->use_dual_fifo = true;
1330                 /* When using dual fifo mode, we need to keep watermark
1331                  * as even numbers due to dma script limitation.
1332                  */
1333                 ssi_private->dma_params_tx.maxburst &= ~0x1;
1334                 ssi_private->dma_params_rx.maxburst &= ~0x1;
1335         }
1336 
1337         if (!ssi_private->use_dma) {
1338 
1339                 /*
1340                  * Some boards use an incompatible codec. To get it
1341                  * working, we are using imx-fiq-pcm-audio, that
1342                  * can handle those codecs. DMA is not possible in this
1343                  * situation.
1344                  */
1345 
1346                 ssi_private->fiq_params.irq = ssi_private->irq;
1347                 ssi_private->fiq_params.base = iomem;
1348                 ssi_private->fiq_params.dma_params_rx =
1349                         &ssi_private->dma_params_rx;
1350                 ssi_private->fiq_params.dma_params_tx =
1351                         &ssi_private->dma_params_tx;
1352 
1353                 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1354                 if (ret)
1355                         goto error_pcm;
1356         } else {
1357                 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
1358                 if (ret)
1359                         goto error_pcm;
1360         }
1361 
1362         return 0;
1363 
1364 error_pcm:
1365 
1366         if (!ssi_private->has_ipg_clk_name)
1367                 clk_disable_unprepare(ssi_private->clk);
1368         return ret;
1369 }
1370 
1371 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1372                 struct fsl_ssi_private *ssi_private)
1373 {
1374         if (!ssi_private->use_dma)
1375                 imx_pcm_fiq_exit(pdev);
1376         if (!ssi_private->has_ipg_clk_name)
1377                 clk_disable_unprepare(ssi_private->clk);
1378 }
1379 
1380 static int fsl_ssi_probe(struct platform_device *pdev)
1381 {
1382         struct fsl_ssi_private *ssi_private;
1383         int ret = 0;
1384         struct device_node *np = pdev->dev.of_node;
1385         const struct of_device_id *of_id;
1386         const char *p, *sprop;
1387         const uint32_t *iprop;
1388         struct resource *res;
1389         void __iomem *iomem;
1390         char name[64];
1391         struct regmap_config regconfig = fsl_ssi_regconfig;
1392 
1393         of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1394         if (!of_id || !of_id->data)
1395                 return -EINVAL;
1396 
1397         ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1398                         GFP_KERNEL);
1399         if (!ssi_private) {
1400                 dev_err(&pdev->dev, "could not allocate DAI object\n");
1401                 return -ENOMEM;
1402         }
1403 
1404         ssi_private->soc = of_id->data;
1405 
1406         sprop = of_get_property(np, "fsl,mode", NULL);
1407         if (sprop) {
1408                 if (!strcmp(sprop, "ac97-slave"))
1409                         ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1410         }
1411 
1412         ssi_private->use_dma = !of_property_read_bool(np,
1413                         "fsl,fiq-stream-filter");
1414 
1415         if (fsl_ssi_is_ac97(ssi_private)) {
1416                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1417                                 sizeof(fsl_ssi_ac97_dai));
1418 
1419                 fsl_ac97_data = ssi_private;
1420 
1421                 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1422                 if (ret) {
1423                         dev_err(&pdev->dev, "could not set AC'97 ops\n");
1424                         return ret;
1425                 }
1426         } else {
1427                 /* Initialize this copy of the CPU DAI driver structure */
1428                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1429                        sizeof(fsl_ssi_dai_template));
1430         }
1431         ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1432 
1433         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1434         iomem = devm_ioremap_resource(&pdev->dev, res);
1435         if (IS_ERR(iomem))
1436                 return PTR_ERR(iomem);
1437         ssi_private->ssi_phys = res->start;
1438 
1439         if (ssi_private->soc->imx21regs) {
1440                 /*
1441                  * According to datasheet imx21-class SSI
1442                  * don't have SACC{ST,EN,DIS} regs.
1443                  */
1444                 regconfig.max_register = CCSR_SSI_SRMSK;
1445                 regconfig.num_reg_defaults_raw =
1446                         CCSR_SSI_SRMSK / sizeof(uint32_t) + 1;
1447         }
1448 
1449         ret = of_property_match_string(np, "clock-names", "ipg");
1450         if (ret < 0) {
1451                 ssi_private->has_ipg_clk_name = false;
1452                 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1453                         &regconfig);
1454         } else {
1455                 ssi_private->has_ipg_clk_name = true;
1456                 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
1457                         "ipg", iomem, &regconfig);
1458         }
1459         if (IS_ERR(ssi_private->regs)) {
1460                 dev_err(&pdev->dev, "Failed to init register map\n");
1461                 return PTR_ERR(ssi_private->regs);
1462         }
1463 
1464         ssi_private->irq = platform_get_irq(pdev, 0);
1465         if (ssi_private->irq < 0) {
1466                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1467                 return ssi_private->irq;
1468         }
1469 
1470         /* Are the RX and the TX clocks locked? */
1471         if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1472                 if (!fsl_ssi_is_ac97(ssi_private))
1473                         ssi_private->cpu_dai_drv.symmetric_rates = 1;
1474 
1475                 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1476                 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1477         }
1478 
1479         /* Determine the FIFO depth. */
1480         iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1481         if (iprop)
1482                 ssi_private->fifo_depth = be32_to_cpup(iprop);
1483         else
1484                 /* Older 8610 DTs didn't have the fifo-depth property */
1485                 ssi_private->fifo_depth = 8;
1486 
1487         dev_set_drvdata(&pdev->dev, ssi_private);
1488 
1489         if (ssi_private->soc->imx) {
1490                 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1491                 if (ret)
1492                         return ret;
1493         }
1494 
1495         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1496                                               &ssi_private->cpu_dai_drv, 1);
1497         if (ret) {
1498                 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1499                 goto error_asoc_register;
1500         }
1501 
1502         if (ssi_private->use_dma) {
1503                 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1504                                         fsl_ssi_isr, 0, dev_name(&pdev->dev),
1505                                         ssi_private);
1506                 if (ret < 0) {
1507                         dev_err(&pdev->dev, "could not claim irq %u\n",
1508                                         ssi_private->irq);
1509                         goto error_asoc_register;
1510                 }
1511         }
1512 
1513         ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1514         if (ret)
1515                 goto error_asoc_register;
1516 
1517         /*
1518          * If codec-handle property is missing from SSI node, we assume
1519          * that the machine driver uses new binding which does not require
1520          * SSI driver to trigger machine driver's probe.
1521          */
1522         if (!of_get_property(np, "codec-handle", NULL))
1523                 goto done;
1524 
1525         /* Trigger the machine driver's probe function.  The platform driver
1526          * name of the machine driver is taken from /compatible property of the
1527          * device tree.  We also pass the address of the CPU DAI driver
1528          * structure.
1529          */
1530         sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1531         /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1532         p = strrchr(sprop, ',');
1533         if (p)
1534                 sprop = p + 1;
1535         snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1536         make_lowercase(name);
1537 
1538         ssi_private->pdev =
1539                 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1540         if (IS_ERR(ssi_private->pdev)) {
1541                 ret = PTR_ERR(ssi_private->pdev);
1542                 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1543                 goto error_sound_card;
1544         }
1545 
1546 done:
1547         if (ssi_private->dai_fmt)
1548                 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
1549                                      ssi_private->dai_fmt);
1550 
1551         if (fsl_ssi_is_ac97(ssi_private)) {
1552                 u32 ssi_idx;
1553 
1554                 ret = of_property_read_u32(np, "cell-index", &ssi_idx);
1555                 if (ret) {
1556                         dev_err(&pdev->dev, "cannot get SSI index property\n");
1557                         goto error_sound_card;
1558                 }
1559 
1560                 ssi_private->pdev =
1561                         platform_device_register_data(NULL,
1562                                         "ac97-codec", ssi_idx, NULL, 0);
1563                 if (IS_ERR(ssi_private->pdev)) {
1564                         ret = PTR_ERR(ssi_private->pdev);
1565                         dev_err(&pdev->dev,
1566                                 "failed to register AC97 codec platform: %d\n",
1567                                 ret);
1568                         goto error_sound_card;
1569                 }
1570         }
1571 
1572         return 0;
1573 
1574 error_sound_card:
1575         fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1576 
1577 error_asoc_register:
1578         if (ssi_private->soc->imx)
1579                 fsl_ssi_imx_clean(pdev, ssi_private);
1580 
1581         return ret;
1582 }
1583 
1584 static int fsl_ssi_remove(struct platform_device *pdev)
1585 {
1586         struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1587 
1588         fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1589 
1590         if (ssi_private->pdev)
1591                 platform_device_unregister(ssi_private->pdev);
1592 
1593         if (ssi_private->soc->imx)
1594                 fsl_ssi_imx_clean(pdev, ssi_private);
1595 
1596         if (fsl_ssi_is_ac97(ssi_private))
1597                 snd_soc_set_ac97_ops(NULL);
1598 
1599         return 0;
1600 }
1601 
1602 #ifdef CONFIG_PM_SLEEP
1603 static int fsl_ssi_suspend(struct device *dev)
1604 {
1605         struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1606         struct regmap *regs = ssi_private->regs;
1607 
1608         regmap_read(regs, CCSR_SSI_SFCSR,
1609                         &ssi_private->regcache_sfcsr);
1610         regmap_read(regs, CCSR_SSI_SACNT,
1611                         &ssi_private->regcache_sacnt);
1612 
1613         regcache_cache_only(regs, true);
1614         regcache_mark_dirty(regs);
1615 
1616         return 0;
1617 }
1618 
1619 static int fsl_ssi_resume(struct device *dev)
1620 {
1621         struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1622         struct regmap *regs = ssi_private->regs;
1623 
1624         regcache_cache_only(regs, false);
1625 
1626         regmap_update_bits(regs, CCSR_SSI_SFCSR,
1627                         CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
1628                         CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
1629                         ssi_private->regcache_sfcsr);
1630         regmap_write(regs, CCSR_SSI_SACNT,
1631                         ssi_private->regcache_sacnt);
1632 
1633         return regcache_sync(regs);
1634 }
1635 #endif /* CONFIG_PM_SLEEP */
1636 
1637 static const struct dev_pm_ops fsl_ssi_pm = {
1638         SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1639 };
1640 
1641 static struct platform_driver fsl_ssi_driver = {
1642         .driver = {
1643                 .name = "fsl-ssi-dai",
1644                 .of_match_table = fsl_ssi_ids,
1645                 .pm = &fsl_ssi_pm,
1646         },
1647         .probe = fsl_ssi_probe,
1648         .remove = fsl_ssi_remove,
1649 };
1650 
1651 module_platform_driver(fsl_ssi_driver);
1652 
1653 MODULE_ALIAS("platform:fsl-ssi-dai");
1654 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1655 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1656 MODULE_LICENSE("GPL v2");
1657 

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