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Linux/sound/soc/fsl/fsl_ssi.c

  1 /*
  2  * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
  3  *
  4  * Author: Timur Tabi <timur@freescale.com>
  5  *
  6  * Copyright 2007-2010 Freescale Semiconductor, Inc.
  7  *
  8  * This file is licensed under the terms of the GNU General Public License
  9  * version 2.  This program is licensed "as is" without any warranty of any
 10  * kind, whether express or implied.
 11  *
 12  *
 13  * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
 14  *
 15  * The i.MX SSI core has some nasty limitations in AC97 mode. While most
 16  * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
 17  * one FIFO which combines all valid receive slots. We cannot even select
 18  * which slots we want to receive. The WM9712 with which this driver
 19  * was developed with always sends GPIO status data in slot 12 which
 20  * we receive in our (PCM-) data stream. The only chance we have is to
 21  * manually skip this data in the FIQ handler. With sampling rates different
 22  * from 48000Hz not every frame has valid receive data, so the ratio
 23  * between pcm data and GPIO status data changes. Our FIQ handler is not
 24  * able to handle this, hence this driver only works with 48000Hz sampling
 25  * rate.
 26  * Reading and writing AC97 registers is another challenge. The core
 27  * provides us status bits when the read register is updated with *another*
 28  * value. When we read the same register two times (and the register still
 29  * contains the same value) these status bits are not set. We work
 30  * around this by not polling these bits but only wait a fixed delay.
 31  */
 32 
 33 #include <linux/init.h>
 34 #include <linux/io.h>
 35 #include <linux/module.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/clk.h>
 38 #include <linux/device.h>
 39 #include <linux/delay.h>
 40 #include <linux/slab.h>
 41 #include <linux/spinlock.h>
 42 #include <linux/of.h>
 43 #include <linux/of_address.h>
 44 #include <linux/of_irq.h>
 45 #include <linux/of_platform.h>
 46 
 47 #include <sound/core.h>
 48 #include <sound/pcm.h>
 49 #include <sound/pcm_params.h>
 50 #include <sound/initval.h>
 51 #include <sound/soc.h>
 52 #include <sound/dmaengine_pcm.h>
 53 
 54 #include "fsl_ssi.h"
 55 #include "imx-pcm.h"
 56 
 57 /**
 58  * FSLSSI_I2S_RATES: sample rates supported by the I2S
 59  *
 60  * This driver currently only supports the SSI running in I2S slave mode,
 61  * which means the codec determines the sample rate.  Therefore, we tell
 62  * ALSA that we support all rates and let the codec driver decide what rates
 63  * are really supported.
 64  */
 65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
 66 
 67 /**
 68  * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
 69  *
 70  * The SSI has a limitation in that the samples must be in the same byte
 71  * order as the host CPU.  This is because when multiple bytes are written
 72  * to the STX register, the bytes and bits must be written in the same
 73  * order.  The STX is a shift register, so all the bits need to be aligned
 74  * (bit-endianness must match byte-endianness).  Processors typically write
 75  * the bits within a byte in the same order that the bytes of a word are
 76  * written in.  So if the host CPU is big-endian, then only big-endian
 77  * samples will be written to STX properly.
 78  */
 79 #ifdef __BIG_ENDIAN
 80 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
 81          SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
 82          SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
 83 #else
 84 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
 85          SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 86          SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
 87 #endif
 88 
 89 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
 90                 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
 91                 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
 92 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
 93                 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
 94                 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
 95 
 96 enum fsl_ssi_type {
 97         FSL_SSI_MCP8610,
 98         FSL_SSI_MX21,
 99         FSL_SSI_MX35,
100         FSL_SSI_MX51,
101 };
102 
103 struct fsl_ssi_reg_val {
104         u32 sier;
105         u32 srcr;
106         u32 stcr;
107         u32 scr;
108 };
109 
110 struct fsl_ssi_rxtx_reg_val {
111         struct fsl_ssi_reg_val rx;
112         struct fsl_ssi_reg_val tx;
113 };
114 static const struct regmap_config fsl_ssi_regconfig = {
115         .max_register = CCSR_SSI_SACCDIS,
116         .reg_bits = 32,
117         .val_bits = 32,
118         .reg_stride = 4,
119         .val_format_endian = REGMAP_ENDIAN_NATIVE,
120 };
121 
122 struct fsl_ssi_soc_data {
123         bool imx;
124         bool offline_config;
125         u32 sisr_write_mask;
126 };
127 
128 /**
129  * fsl_ssi_private: per-SSI private data
130  *
131  * @reg: Pointer to the regmap registers
132  * @irq: IRQ of this SSI
133  * @cpu_dai_drv: CPU DAI driver for this device
134  *
135  * @dai_fmt: DAI configuration this device is currently used with
136  * @i2s_mode: i2s and network mode configuration of the device. Is used to
137  * switch between normal and i2s/network mode
138  * mode depending on the number of channels
139  * @use_dma: DMA is used or FIQ with stream filter
140  * @use_dual_fifo: DMA with support for both FIFOs used
141  * @fifo_deph: Depth of the SSI FIFOs
142  * @rxtx_reg_val: Specific register settings for receive/transmit configuration
143  *
144  * @clk: SSI clock
145  * @baudclk: SSI baud clock for master mode
146  * @baudclk_streams: Active streams that are using baudclk
147  * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
148  *
149  * @dma_params_tx: DMA transmit parameters
150  * @dma_params_rx: DMA receive parameters
151  * @ssi_phys: physical address of the SSI registers
152  *
153  * @fiq_params: FIQ stream filtering parameters
154  *
155  * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
156  *
157  * @dbg_stats: Debugging statistics
158  *
159  * @soc: SoC specifc data
160  */
161 struct fsl_ssi_private {
162         struct regmap *regs;
163         int irq;
164         struct snd_soc_dai_driver cpu_dai_drv;
165 
166         unsigned int dai_fmt;
167         u8 i2s_mode;
168         bool use_dma;
169         bool use_dual_fifo;
170         bool has_ipg_clk_name;
171         unsigned int fifo_depth;
172         struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
173 
174         struct clk *clk;
175         struct clk *baudclk;
176         unsigned int baudclk_streams;
177         unsigned int bitclk_freq;
178 
179         /* DMA params */
180         struct snd_dmaengine_dai_dma_data dma_params_tx;
181         struct snd_dmaengine_dai_dma_data dma_params_rx;
182         dma_addr_t ssi_phys;
183 
184         /* params for non-dma FIQ stream filtered mode */
185         struct imx_pcm_fiq_params fiq_params;
186 
187         /* Used when using fsl-ssi as sound-card. This is only used by ppc and
188          * should be replaced with simple-sound-card. */
189         struct platform_device *pdev;
190 
191         struct fsl_ssi_dbg dbg_stats;
192 
193         const struct fsl_ssi_soc_data *soc;
194 };
195 
196 /*
197  * imx51 and later SoCs have a slightly different IP that allows the
198  * SSI configuration while the SSI unit is running.
199  *
200  * More important, it is necessary on those SoCs to configure the
201  * sperate TX/RX DMA bits just before starting the stream
202  * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
203  * sends any DMA requests to the SDMA unit, otherwise it is not defined
204  * how the SDMA unit handles the DMA request.
205  *
206  * SDMA units are present on devices starting at imx35 but the imx35
207  * reference manual states that the DMA bits should not be changed
208  * while the SSI unit is running (SSIEN). So we support the necessary
209  * online configuration of fsl-ssi starting at imx51.
210  */
211 
212 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
213         .imx = false,
214         .offline_config = true,
215         .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
216                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
217                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
218 };
219 
220 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
221         .imx = true,
222         .offline_config = true,
223         .sisr_write_mask = 0,
224 };
225 
226 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
227         .imx = true,
228         .offline_config = true,
229         .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
230                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
231                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
232 };
233 
234 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
235         .imx = true,
236         .offline_config = false,
237         .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
238                 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
239 };
240 
241 static const struct of_device_id fsl_ssi_ids[] = {
242         { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
243         { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
244         { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
245         { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
246         {}
247 };
248 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
249 
250 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
251 {
252         return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97);
253 }
254 
255 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
256 {
257         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
258                 SND_SOC_DAIFMT_CBS_CFS;
259 }
260 
261 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private)
262 {
263         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
264                 SND_SOC_DAIFMT_CBM_CFS;
265 }
266 /**
267  * fsl_ssi_isr: SSI interrupt handler
268  *
269  * Although it's possible to use the interrupt handler to send and receive
270  * data to/from the SSI, we use the DMA instead.  Programming is more
271  * complicated, but the performance is much better.
272  *
273  * This interrupt handler is used only to gather statistics.
274  *
275  * @irq: IRQ of the SSI device
276  * @dev_id: pointer to the ssi_private structure for this SSI device
277  */
278 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
279 {
280         struct fsl_ssi_private *ssi_private = dev_id;
281         struct regmap *regs = ssi_private->regs;
282         __be32 sisr;
283         __be32 sisr2;
284 
285         /* We got an interrupt, so read the status register to see what we
286            were interrupted for.  We mask it with the Interrupt Enable register
287            so that we only check for events that we're interested in.
288          */
289         regmap_read(regs, CCSR_SSI_SISR, &sisr);
290 
291         sisr2 = sisr & ssi_private->soc->sisr_write_mask;
292         /* Clear the bits that we set */
293         if (sisr2)
294                 regmap_write(regs, CCSR_SSI_SISR, sisr2);
295 
296         fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
297 
298         return IRQ_HANDLED;
299 }
300 
301 /*
302  * Enable/Disable all rx/tx config flags at once.
303  */
304 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
305                 bool enable)
306 {
307         struct regmap *regs = ssi_private->regs;
308         struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
309 
310         if (enable) {
311                 regmap_update_bits(regs, CCSR_SSI_SIER,
312                                 vals->rx.sier | vals->tx.sier,
313                                 vals->rx.sier | vals->tx.sier);
314                 regmap_update_bits(regs, CCSR_SSI_SRCR,
315                                 vals->rx.srcr | vals->tx.srcr,
316                                 vals->rx.srcr | vals->tx.srcr);
317                 regmap_update_bits(regs, CCSR_SSI_STCR,
318                                 vals->rx.stcr | vals->tx.stcr,
319                                 vals->rx.stcr | vals->tx.stcr);
320         } else {
321                 regmap_update_bits(regs, CCSR_SSI_SRCR,
322                                 vals->rx.srcr | vals->tx.srcr, 0);
323                 regmap_update_bits(regs, CCSR_SSI_STCR,
324                                 vals->rx.stcr | vals->tx.stcr, 0);
325                 regmap_update_bits(regs, CCSR_SSI_SIER,
326                                 vals->rx.sier | vals->tx.sier, 0);
327         }
328 }
329 
330 /*
331  * Calculate the bits that have to be disabled for the current stream that is
332  * getting disabled. This keeps the bits enabled that are necessary for the
333  * second stream to work if 'stream_active' is true.
334  *
335  * Detailed calculation:
336  * These are the values that need to be active after disabling. For non-active
337  * second stream, this is 0:
338  *      vals_stream * !!stream_active
339  *
340  * The following computes the overall differences between the setup for the
341  * to-disable stream and the active stream, a simple XOR:
342  *      vals_disable ^ (vals_stream * !!(stream_active))
343  *
344  * The full expression adds a mask on all values we care about
345  */
346 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
347         ((vals_disable) & \
348          ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
349 
350 /*
351  * Enable/Disable a ssi configuration. You have to pass either
352  * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
353  */
354 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
355                 struct fsl_ssi_reg_val *vals)
356 {
357         struct regmap *regs = ssi_private->regs;
358         struct fsl_ssi_reg_val *avals;
359         int nr_active_streams;
360         u32 scr_val;
361         int keep_active;
362 
363         regmap_read(regs, CCSR_SSI_SCR, &scr_val);
364 
365         nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
366                                 !!(scr_val & CCSR_SSI_SCR_RE);
367 
368         if (nr_active_streams - 1 > 0)
369                 keep_active = 1;
370         else
371                 keep_active = 0;
372 
373         /* Find the other direction values rx or tx which we do not want to
374          * modify */
375         if (&ssi_private->rxtx_reg_val.rx == vals)
376                 avals = &ssi_private->rxtx_reg_val.tx;
377         else
378                 avals = &ssi_private->rxtx_reg_val.rx;
379 
380         /* If vals should be disabled, start with disabling the unit */
381         if (!enable) {
382                 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
383                                 keep_active);
384                 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
385         }
386 
387         /*
388          * We are running on a SoC which does not support online SSI
389          * reconfiguration, so we have to enable all necessary flags at once
390          * even if we do not use them later (capture and playback configuration)
391          */
392         if (ssi_private->soc->offline_config) {
393                 if ((enable && !nr_active_streams) ||
394                                 (!enable && !keep_active))
395                         fsl_ssi_rxtx_config(ssi_private, enable);
396 
397                 goto config_done;
398         }
399 
400         /*
401          * Configure single direction units while the SSI unit is running
402          * (online configuration)
403          */
404         if (enable) {
405                 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
406                 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
407                 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
408         } else {
409                 u32 sier;
410                 u32 srcr;
411                 u32 stcr;
412 
413                 /*
414                  * Disabling the necessary flags for one of rx/tx while the
415                  * other stream is active is a little bit more difficult. We
416                  * have to disable only those flags that differ between both
417                  * streams (rx XOR tx) and that are set in the stream that is
418                  * disabled now. Otherwise we could alter flags of the other
419                  * stream
420                  */
421 
422                 /* These assignments are simply vals without bits set in avals*/
423                 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
424                                 keep_active);
425                 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
426                                 keep_active);
427                 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
428                                 keep_active);
429 
430                 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
431                 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
432                 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
433         }
434 
435 config_done:
436         /* Enabling of subunits is done after configuration */
437         if (enable)
438                 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
439 }
440 
441 
442 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
443 {
444         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
445 }
446 
447 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
448 {
449         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
450 }
451 
452 /*
453  * Setup rx/tx register values used to enable/disable the streams. These will
454  * be used later in fsl_ssi_config to setup the streams without the need to
455  * check for all different SSI modes.
456  */
457 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
458 {
459         struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
460 
461         reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
462         reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
463         reg->rx.scr = 0;
464         reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
465         reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
466         reg->tx.scr = 0;
467 
468         if (!fsl_ssi_is_ac97(ssi_private)) {
469                 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
470                 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
471                 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
472                 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
473         }
474 
475         if (ssi_private->use_dma) {
476                 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
477                 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
478         } else {
479                 reg->rx.sier |= CCSR_SSI_SIER_RIE;
480                 reg->tx.sier |= CCSR_SSI_SIER_TIE;
481         }
482 
483         reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
484         reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
485 }
486 
487 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
488 {
489         struct regmap *regs = ssi_private->regs;
490 
491         /*
492          * Setup the clock control register
493          */
494         regmap_write(regs, CCSR_SSI_STCCR,
495                         CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
496         regmap_write(regs, CCSR_SSI_SRCCR,
497                         CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
498 
499         /*
500          * Enable AC97 mode and startup the SSI
501          */
502         regmap_write(regs, CCSR_SSI_SACNT,
503                         CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
504         regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
505         regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
506 
507         /*
508          * Enable SSI, Transmit and Receive. AC97 has to communicate with the
509          * codec before a stream is started.
510          */
511         regmap_update_bits(regs, CCSR_SSI_SCR,
512                         CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
513                         CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
514 
515         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
516 }
517 
518 /**
519  * fsl_ssi_startup: create a new substream
520  *
521  * This is the first function called when a stream is opened.
522  *
523  * If this is the first stream open, then grab the IRQ and program most of
524  * the SSI registers.
525  */
526 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
527                            struct snd_soc_dai *dai)
528 {
529         struct snd_soc_pcm_runtime *rtd = substream->private_data;
530         struct fsl_ssi_private *ssi_private =
531                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
532         int ret;
533 
534         ret = clk_prepare_enable(ssi_private->clk);
535         if (ret)
536                 return ret;
537 
538         /* When using dual fifo mode, it is safer to ensure an even period
539          * size. If appearing to an odd number while DMA always starts its
540          * task from fifo0, fifo1 would be neglected at the end of each
541          * period. But SSI would still access fifo1 with an invalid data.
542          */
543         if (ssi_private->use_dual_fifo)
544                 snd_pcm_hw_constraint_step(substream->runtime, 0,
545                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
546 
547         return 0;
548 }
549 
550 /**
551  * fsl_ssi_shutdown: shutdown the SSI
552  *
553  */
554 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
555                                 struct snd_soc_dai *dai)
556 {
557         struct snd_soc_pcm_runtime *rtd = substream->private_data;
558         struct fsl_ssi_private *ssi_private =
559                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
560 
561         clk_disable_unprepare(ssi_private->clk);
562 
563 }
564 
565 /**
566  * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
567  *
568  * Note: This function can be only called when using SSI as DAI master
569  *
570  * Quick instruction for parameters:
571  * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
572  * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
573  */
574 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
575                 struct snd_soc_dai *cpu_dai,
576                 struct snd_pcm_hw_params *hw_params)
577 {
578         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
579         struct regmap *regs = ssi_private->regs;
580         int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
581         u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
582         unsigned long clkrate, baudrate, tmprate;
583         u64 sub, savesub = 100000;
584         unsigned int freq;
585         bool baudclk_is_used;
586 
587         /* Prefer the explicitly set bitclock frequency */
588         if (ssi_private->bitclk_freq)
589                 freq = ssi_private->bitclk_freq;
590         else
591                 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
592 
593         /* Don't apply it to any non-baudclk circumstance */
594         if (IS_ERR(ssi_private->baudclk))
595                 return -EINVAL;
596 
597         baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
598 
599         /* It should be already enough to divide clock by setting pm alone */
600         psr = 0;
601         div2 = 0;
602 
603         factor = (div2 + 1) * (7 * psr + 1) * 2;
604 
605         for (i = 0; i < 255; i++) {
606                 tmprate = freq * factor * (i + 1);
607 
608                 if (baudclk_is_used)
609                         clkrate = clk_get_rate(ssi_private->baudclk);
610                 else
611                         clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
612 
613                 /*
614                  * Hardware limitation: The bclk rate must be
615                  * never greater than 1/5 IPG clock rate
616                  */
617                 if (clkrate * 5 > clk_get_rate(ssi_private->clk))
618                         continue;
619 
620                 clkrate /= factor;
621                 afreq = clkrate / (i + 1);
622 
623                 if (freq == afreq)
624                         sub = 0;
625                 else if (freq / afreq == 1)
626                         sub = freq - afreq;
627                 else if (afreq / freq == 1)
628                         sub = afreq - freq;
629                 else
630                         continue;
631 
632                 /* Calculate the fraction */
633                 sub *= 100000;
634                 do_div(sub, freq);
635 
636                 if (sub < savesub) {
637                         baudrate = tmprate;
638                         savesub = sub;
639                         pm = i;
640                 }
641 
642                 /* We are lucky */
643                 if (savesub == 0)
644                         break;
645         }
646 
647         /* No proper pm found if it is still remaining the initial value */
648         if (pm == 999) {
649                 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
650                 return -EINVAL;
651         }
652 
653         stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
654                 (psr ? CCSR_SSI_SxCCR_PSR : 0);
655         mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
656                 CCSR_SSI_SxCCR_PSR;
657 
658         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
659                 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
660         else
661                 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
662 
663         if (!baudclk_is_used) {
664                 ret = clk_set_rate(ssi_private->baudclk, baudrate);
665                 if (ret) {
666                         dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
667                         return -EINVAL;
668                 }
669         }
670 
671         return 0;
672 }
673 
674 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
675                 int clk_id, unsigned int freq, int dir)
676 {
677         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
678 
679         ssi_private->bitclk_freq = freq;
680 
681         return 0;
682 }
683 
684 /**
685  * fsl_ssi_hw_params - program the sample size
686  *
687  * Most of the SSI registers have been programmed in the startup function,
688  * but the word length must be programmed here.  Unfortunately, programming
689  * the SxCCR.WL bits requires the SSI to be temporarily disabled.  This can
690  * cause a problem with supporting simultaneous playback and capture.  If
691  * the SSI is already playing a stream, then that stream may be temporarily
692  * stopped when you start capture.
693  *
694  * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
695  * clock master.
696  */
697 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
698         struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
699 {
700         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
701         struct regmap *regs = ssi_private->regs;
702         unsigned int channels = params_channels(hw_params);
703         unsigned int sample_size =
704                 snd_pcm_format_width(params_format(hw_params));
705         u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
706         int ret;
707         u32 scr_val;
708         int enabled;
709 
710         regmap_read(regs, CCSR_SSI_SCR, &scr_val);
711         enabled = scr_val & CCSR_SSI_SCR_SSIEN;
712 
713         /*
714          * If we're in synchronous mode, and the SSI is already enabled,
715          * then STCCR is already set properly.
716          */
717         if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
718                 return 0;
719 
720         if (fsl_ssi_is_i2s_master(ssi_private)) {
721                 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
722                 if (ret)
723                         return ret;
724 
725                 /* Do not enable the clock if it is already enabled */
726                 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
727                         ret = clk_prepare_enable(ssi_private->baudclk);
728                         if (ret)
729                                 return ret;
730 
731                         ssi_private->baudclk_streams |= BIT(substream->stream);
732                 }
733         }
734 
735         if (!fsl_ssi_is_ac97(ssi_private)) {
736                 u8 i2smode;
737                 /*
738                  * Switch to normal net mode in order to have a frame sync
739                  * signal every 32 bits instead of 16 bits
740                  */
741                 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16)
742                         i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL |
743                                 CCSR_SSI_SCR_NET;
744                 else
745                         i2smode = ssi_private->i2s_mode;
746 
747                 regmap_update_bits(regs, CCSR_SSI_SCR,
748                                 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
749                                 channels == 1 ? 0 : i2smode);
750         }
751 
752         /*
753          * FIXME: The documentation says that SxCCR[WL] should not be
754          * modified while the SSI is enabled.  The only time this can
755          * happen is if we're trying to do simultaneous playback and
756          * capture in asynchronous mode.  Unfortunately, I have been enable
757          * to get that to work at all on the P1022DS.  Therefore, we don't
758          * bother to disable/enable the SSI when setting SxCCR[WL], because
759          * the SSI will stop anyway.  Maybe one day, this will get fixed.
760          */
761 
762         /* In synchronous mode, the SSI uses STCCR for capture */
763         if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
764             ssi_private->cpu_dai_drv.symmetric_rates)
765                 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
766                                 wl);
767         else
768                 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
769                                 wl);
770 
771         return 0;
772 }
773 
774 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
775                 struct snd_soc_dai *cpu_dai)
776 {
777         struct snd_soc_pcm_runtime *rtd = substream->private_data;
778         struct fsl_ssi_private *ssi_private =
779                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
780 
781         if (fsl_ssi_is_i2s_master(ssi_private) &&
782                         ssi_private->baudclk_streams & BIT(substream->stream)) {
783                 clk_disable_unprepare(ssi_private->baudclk);
784                 ssi_private->baudclk_streams &= ~BIT(substream->stream);
785         }
786 
787         return 0;
788 }
789 
790 static int _fsl_ssi_set_dai_fmt(struct device *dev,
791                                 struct fsl_ssi_private *ssi_private,
792                                 unsigned int fmt)
793 {
794         struct regmap *regs = ssi_private->regs;
795         u32 strcr = 0, stcr, srcr, scr, mask;
796         u8 wm;
797 
798         ssi_private->dai_fmt = fmt;
799 
800         if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
801                 dev_err(dev, "baudclk is missing which is necessary for master mode\n");
802                 return -EINVAL;
803         }
804 
805         fsl_ssi_setup_reg_vals(ssi_private);
806 
807         regmap_read(regs, CCSR_SSI_SCR, &scr);
808         scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
809         scr |= CCSR_SSI_SCR_SYNC_TX_FS;
810 
811         mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
812                 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
813                 CCSR_SSI_STCR_TEFS;
814         regmap_read(regs, CCSR_SSI_STCR, &stcr);
815         regmap_read(regs, CCSR_SSI_SRCR, &srcr);
816         stcr &= ~mask;
817         srcr &= ~mask;
818 
819         ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
820         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
821         case SND_SOC_DAIFMT_I2S:
822                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
823                 case SND_SOC_DAIFMT_CBM_CFS:
824                 case SND_SOC_DAIFMT_CBS_CFS:
825                         ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
826                         regmap_update_bits(regs, CCSR_SSI_STCCR,
827                                         CCSR_SSI_SxCCR_DC_MASK,
828                                         CCSR_SSI_SxCCR_DC(2));
829                         regmap_update_bits(regs, CCSR_SSI_SRCCR,
830                                         CCSR_SSI_SxCCR_DC_MASK,
831                                         CCSR_SSI_SxCCR_DC(2));
832                         break;
833                 case SND_SOC_DAIFMT_CBM_CFM:
834                         ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
835                         break;
836                 default:
837                         return -EINVAL;
838                 }
839 
840                 /* Data on rising edge of bclk, frame low, 1clk before data */
841                 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
842                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
843                 break;
844         case SND_SOC_DAIFMT_LEFT_J:
845                 /* Data on rising edge of bclk, frame high */
846                 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
847                 break;
848         case SND_SOC_DAIFMT_DSP_A:
849                 /* Data on rising edge of bclk, frame high, 1clk before data */
850                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
851                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
852                 break;
853         case SND_SOC_DAIFMT_DSP_B:
854                 /* Data on rising edge of bclk, frame high */
855                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
856                         CCSR_SSI_STCR_TXBIT0;
857                 break;
858         case SND_SOC_DAIFMT_AC97:
859                 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
860                 break;
861         default:
862                 return -EINVAL;
863         }
864         scr |= ssi_private->i2s_mode;
865 
866         /* DAI clock inversion */
867         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
868         case SND_SOC_DAIFMT_NB_NF:
869                 /* Nothing to do for both normal cases */
870                 break;
871         case SND_SOC_DAIFMT_IB_NF:
872                 /* Invert bit clock */
873                 strcr ^= CCSR_SSI_STCR_TSCKP;
874                 break;
875         case SND_SOC_DAIFMT_NB_IF:
876                 /* Invert frame clock */
877                 strcr ^= CCSR_SSI_STCR_TFSI;
878                 break;
879         case SND_SOC_DAIFMT_IB_IF:
880                 /* Invert both clocks */
881                 strcr ^= CCSR_SSI_STCR_TSCKP;
882                 strcr ^= CCSR_SSI_STCR_TFSI;
883                 break;
884         default:
885                 return -EINVAL;
886         }
887 
888         /* DAI clock master masks */
889         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
890         case SND_SOC_DAIFMT_CBS_CFS:
891                 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
892                 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
893                 break;
894         case SND_SOC_DAIFMT_CBM_CFM:
895                 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
896                 break;
897         case SND_SOC_DAIFMT_CBM_CFS:
898                 strcr &= ~CCSR_SSI_STCR_TXDIR;
899                 strcr |= CCSR_SSI_STCR_TFDIR;
900                 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
901                 break;
902         default:
903                 return -EINVAL;
904         }
905 
906         stcr |= strcr;
907         srcr |= strcr;
908 
909         if (ssi_private->cpu_dai_drv.symmetric_rates) {
910                 /* Need to clear RXDIR when using SYNC mode */
911                 srcr &= ~CCSR_SSI_SRCR_RXDIR;
912                 scr |= CCSR_SSI_SCR_SYN;
913         }
914 
915         regmap_write(regs, CCSR_SSI_STCR, stcr);
916         regmap_write(regs, CCSR_SSI_SRCR, srcr);
917         regmap_write(regs, CCSR_SSI_SCR, scr);
918 
919         /*
920          * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
921          * use FIFO 1. We program the transmit water to signal a DMA transfer
922          * if there are only two (or fewer) elements left in the FIFO. Two
923          * elements equals one frame (left channel, right channel). This value,
924          * however, depends on the depth of the transmit buffer.
925          *
926          * We set the watermark on the same level as the DMA burstsize.  For
927          * fiq it is probably better to use the biggest possible watermark
928          * size.
929          */
930         if (ssi_private->use_dma)
931                 wm = ssi_private->fifo_depth - 2;
932         else
933                 wm = ssi_private->fifo_depth;
934 
935         regmap_write(regs, CCSR_SSI_SFCSR,
936                         CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
937                         CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
938 
939         if (ssi_private->use_dual_fifo) {
940                 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
941                                 CCSR_SSI_SRCR_RFEN1);
942                 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
943                                 CCSR_SSI_STCR_TFEN1);
944                 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
945                                 CCSR_SSI_SCR_TCH_EN);
946         }
947 
948         if (fmt & SND_SOC_DAIFMT_AC97)
949                 fsl_ssi_setup_ac97(ssi_private);
950 
951         return 0;
952 
953 }
954 
955 /**
956  * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
957  */
958 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
959 {
960         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
961 
962         return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
963 }
964 
965 /**
966  * fsl_ssi_set_dai_tdm_slot - set TDM slot number
967  *
968  * Note: This function can be only called when using SSI as DAI master
969  */
970 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
971                                 u32 rx_mask, int slots, int slot_width)
972 {
973         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
974         struct regmap *regs = ssi_private->regs;
975         u32 val;
976 
977         /* The slot number should be >= 2 if using Network mode or I2S mode */
978         regmap_read(regs, CCSR_SSI_SCR, &val);
979         val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
980         if (val && slots < 2) {
981                 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
982                 return -EINVAL;
983         }
984 
985         regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
986                         CCSR_SSI_SxCCR_DC(slots));
987         regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
988                         CCSR_SSI_SxCCR_DC(slots));
989 
990         /* The register SxMSKs needs SSI to provide essential clock due to
991          * hardware design. So we here temporarily enable SSI to set them.
992          */
993         regmap_read(regs, CCSR_SSI_SCR, &val);
994         val &= CCSR_SSI_SCR_SSIEN;
995         regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
996                         CCSR_SSI_SCR_SSIEN);
997 
998         regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask);
999         regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask);
1000 
1001         regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
1002 
1003         return 0;
1004 }
1005 
1006 /**
1007  * fsl_ssi_trigger: start and stop the DMA transfer.
1008  *
1009  * This function is called by ALSA to start, stop, pause, and resume the DMA
1010  * transfer of data.
1011  *
1012  * The DMA channel is in external master start and pause mode, which
1013  * means the SSI completely controls the flow of data.
1014  */
1015 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1016                            struct snd_soc_dai *dai)
1017 {
1018         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1019         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1020         struct regmap *regs = ssi_private->regs;
1021 
1022         switch (cmd) {
1023         case SNDRV_PCM_TRIGGER_START:
1024         case SNDRV_PCM_TRIGGER_RESUME:
1025         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1026                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1027                         fsl_ssi_tx_config(ssi_private, true);
1028                 else
1029                         fsl_ssi_rx_config(ssi_private, true);
1030                 break;
1031 
1032         case SNDRV_PCM_TRIGGER_STOP:
1033         case SNDRV_PCM_TRIGGER_SUSPEND:
1034         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1035                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1036                         fsl_ssi_tx_config(ssi_private, false);
1037                 else
1038                         fsl_ssi_rx_config(ssi_private, false);
1039                 break;
1040 
1041         default:
1042                 return -EINVAL;
1043         }
1044 
1045         if (fsl_ssi_is_ac97(ssi_private)) {
1046                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1047                         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1048                 else
1049                         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1050         }
1051 
1052         return 0;
1053 }
1054 
1055 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1056 {
1057         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1058 
1059         if (ssi_private->soc->imx && ssi_private->use_dma) {
1060                 dai->playback_dma_data = &ssi_private->dma_params_tx;
1061                 dai->capture_dma_data = &ssi_private->dma_params_rx;
1062         }
1063 
1064         return 0;
1065 }
1066 
1067 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1068         .startup        = fsl_ssi_startup,
1069         .shutdown       = fsl_ssi_shutdown,
1070         .hw_params      = fsl_ssi_hw_params,
1071         .hw_free        = fsl_ssi_hw_free,
1072         .set_fmt        = fsl_ssi_set_dai_fmt,
1073         .set_sysclk     = fsl_ssi_set_dai_sysclk,
1074         .set_tdm_slot   = fsl_ssi_set_dai_tdm_slot,
1075         .trigger        = fsl_ssi_trigger,
1076 };
1077 
1078 /* Template for the CPU dai driver structure */
1079 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1080         .probe = fsl_ssi_dai_probe,
1081         .playback = {
1082                 .stream_name = "CPU-Playback",
1083                 .channels_min = 1,
1084                 .channels_max = 2,
1085                 .rates = FSLSSI_I2S_RATES,
1086                 .formats = FSLSSI_I2S_FORMATS,
1087         },
1088         .capture = {
1089                 .stream_name = "CPU-Capture",
1090                 .channels_min = 1,
1091                 .channels_max = 2,
1092                 .rates = FSLSSI_I2S_RATES,
1093                 .formats = FSLSSI_I2S_FORMATS,
1094         },
1095         .ops = &fsl_ssi_dai_ops,
1096 };
1097 
1098 static const struct snd_soc_component_driver fsl_ssi_component = {
1099         .name           = "fsl-ssi",
1100 };
1101 
1102 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1103         .bus_control = true,
1104         .playback = {
1105                 .stream_name = "AC97 Playback",
1106                 .channels_min = 2,
1107                 .channels_max = 2,
1108                 .rates = SNDRV_PCM_RATE_8000_48000,
1109                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1110         },
1111         .capture = {
1112                 .stream_name = "AC97 Capture",
1113                 .channels_min = 2,
1114                 .channels_max = 2,
1115                 .rates = SNDRV_PCM_RATE_48000,
1116                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1117         },
1118         .ops = &fsl_ssi_dai_ops,
1119 };
1120 
1121 
1122 static struct fsl_ssi_private *fsl_ac97_data;
1123 
1124 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1125                 unsigned short val)
1126 {
1127         struct regmap *regs = fsl_ac97_data->regs;
1128         unsigned int lreg;
1129         unsigned int lval;
1130 
1131         if (reg > 0x7f)
1132                 return;
1133 
1134 
1135         lreg = reg <<  12;
1136         regmap_write(regs, CCSR_SSI_SACADD, lreg);
1137 
1138         lval = val << 4;
1139         regmap_write(regs, CCSR_SSI_SACDAT, lval);
1140 
1141         regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1142                         CCSR_SSI_SACNT_WR);
1143         udelay(100);
1144 }
1145 
1146 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1147                 unsigned short reg)
1148 {
1149         struct regmap *regs = fsl_ac97_data->regs;
1150 
1151         unsigned short val = -1;
1152         u32 reg_val;
1153         unsigned int lreg;
1154 
1155         lreg = (reg & 0x7f) <<  12;
1156         regmap_write(regs, CCSR_SSI_SACADD, lreg);
1157         regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1158                         CCSR_SSI_SACNT_RD);
1159 
1160         udelay(100);
1161 
1162         regmap_read(regs, CCSR_SSI_SACDAT, &reg_val);
1163         val = (reg_val >> 4) & 0xffff;
1164 
1165         return val;
1166 }
1167 
1168 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1169         .read           = fsl_ssi_ac97_read,
1170         .write          = fsl_ssi_ac97_write,
1171 };
1172 
1173 /**
1174  * Make every character in a string lower-case
1175  */
1176 static void make_lowercase(char *s)
1177 {
1178         char *p = s;
1179         char c;
1180 
1181         while ((c = *p)) {
1182                 if ((c >= 'A') && (c <= 'Z'))
1183                         *p = c + ('a' - 'A');
1184                 p++;
1185         }
1186 }
1187 
1188 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1189                 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1190 {
1191         struct device_node *np = pdev->dev.of_node;
1192         u32 dmas[4];
1193         int ret;
1194 
1195         if (ssi_private->has_ipg_clk_name)
1196                 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
1197         else
1198                 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1199         if (IS_ERR(ssi_private->clk)) {
1200                 ret = PTR_ERR(ssi_private->clk);
1201                 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1202                 return ret;
1203         }
1204 
1205         if (!ssi_private->has_ipg_clk_name) {
1206                 ret = clk_prepare_enable(ssi_private->clk);
1207                 if (ret) {
1208                         dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1209                         return ret;
1210                 }
1211         }
1212 
1213         /* For those SLAVE implementations, we ingore non-baudclk cases
1214          * and, instead, abandon MASTER mode that needs baud clock.
1215          */
1216         ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1217         if (IS_ERR(ssi_private->baudclk))
1218                 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1219                          PTR_ERR(ssi_private->baudclk));
1220 
1221         /*
1222          * We have burstsize be "fifo_depth - 2" to match the SSI
1223          * watermark setting in fsl_ssi_startup().
1224          */
1225         ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1226         ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1227         ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1228         ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1229 
1230         ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1231         if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1232                 ssi_private->use_dual_fifo = true;
1233                 /* When using dual fifo mode, we need to keep watermark
1234                  * as even numbers due to dma script limitation.
1235                  */
1236                 ssi_private->dma_params_tx.maxburst &= ~0x1;
1237                 ssi_private->dma_params_rx.maxburst &= ~0x1;
1238         }
1239 
1240         if (!ssi_private->use_dma) {
1241 
1242                 /*
1243                  * Some boards use an incompatible codec. To get it
1244                  * working, we are using imx-fiq-pcm-audio, that
1245                  * can handle those codecs. DMA is not possible in this
1246                  * situation.
1247                  */
1248 
1249                 ssi_private->fiq_params.irq = ssi_private->irq;
1250                 ssi_private->fiq_params.base = iomem;
1251                 ssi_private->fiq_params.dma_params_rx =
1252                         &ssi_private->dma_params_rx;
1253                 ssi_private->fiq_params.dma_params_tx =
1254                         &ssi_private->dma_params_tx;
1255 
1256                 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1257                 if (ret)
1258                         goto error_pcm;
1259         } else {
1260                 ret = imx_pcm_dma_init(pdev);
1261                 if (ret)
1262                         goto error_pcm;
1263         }
1264 
1265         return 0;
1266 
1267 error_pcm:
1268 
1269         if (!ssi_private->has_ipg_clk_name)
1270                 clk_disable_unprepare(ssi_private->clk);
1271         return ret;
1272 }
1273 
1274 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1275                 struct fsl_ssi_private *ssi_private)
1276 {
1277         if (!ssi_private->use_dma)
1278                 imx_pcm_fiq_exit(pdev);
1279         if (!ssi_private->has_ipg_clk_name)
1280                 clk_disable_unprepare(ssi_private->clk);
1281 }
1282 
1283 static int fsl_ssi_probe(struct platform_device *pdev)
1284 {
1285         struct fsl_ssi_private *ssi_private;
1286         int ret = 0;
1287         struct device_node *np = pdev->dev.of_node;
1288         const struct of_device_id *of_id;
1289         const char *p, *sprop;
1290         const uint32_t *iprop;
1291         struct resource *res;
1292         void __iomem *iomem;
1293         char name[64];
1294 
1295         /* SSIs that are not connected on the board should have a
1296          *      status = "disabled"
1297          * property in their device tree nodes.
1298          */
1299         if (!of_device_is_available(np))
1300                 return -ENODEV;
1301 
1302         of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1303         if (!of_id || !of_id->data)
1304                 return -EINVAL;
1305 
1306         ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1307                         GFP_KERNEL);
1308         if (!ssi_private) {
1309                 dev_err(&pdev->dev, "could not allocate DAI object\n");
1310                 return -ENOMEM;
1311         }
1312 
1313         ssi_private->soc = of_id->data;
1314 
1315         sprop = of_get_property(np, "fsl,mode", NULL);
1316         if (sprop) {
1317                 if (!strcmp(sprop, "ac97-slave"))
1318                         ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1319         }
1320 
1321         ssi_private->use_dma = !of_property_read_bool(np,
1322                         "fsl,fiq-stream-filter");
1323 
1324         if (fsl_ssi_is_ac97(ssi_private)) {
1325                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1326                                 sizeof(fsl_ssi_ac97_dai));
1327 
1328                 fsl_ac97_data = ssi_private;
1329 
1330                 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1331         } else {
1332                 /* Initialize this copy of the CPU DAI driver structure */
1333                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1334                        sizeof(fsl_ssi_dai_template));
1335         }
1336         ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1337 
1338         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1339         iomem = devm_ioremap_resource(&pdev->dev, res);
1340         if (IS_ERR(iomem))
1341                 return PTR_ERR(iomem);
1342         ssi_private->ssi_phys = res->start;
1343 
1344         ret = of_property_match_string(np, "clock-names", "ipg");
1345         if (ret < 0) {
1346                 ssi_private->has_ipg_clk_name = false;
1347                 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1348                         &fsl_ssi_regconfig);
1349         } else {
1350                 ssi_private->has_ipg_clk_name = true;
1351                 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
1352                         "ipg", iomem, &fsl_ssi_regconfig);
1353         }
1354         if (IS_ERR(ssi_private->regs)) {
1355                 dev_err(&pdev->dev, "Failed to init register map\n");
1356                 return PTR_ERR(ssi_private->regs);
1357         }
1358 
1359         ssi_private->irq = platform_get_irq(pdev, 0);
1360         if (ssi_private->irq < 0) {
1361                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1362                 return ssi_private->irq;
1363         }
1364 
1365         /* Are the RX and the TX clocks locked? */
1366         if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1367                 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1368                 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1369                 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1370         }
1371 
1372         /* Determine the FIFO depth. */
1373         iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1374         if (iprop)
1375                 ssi_private->fifo_depth = be32_to_cpup(iprop);
1376         else
1377                 /* Older 8610 DTs didn't have the fifo-depth property */
1378                 ssi_private->fifo_depth = 8;
1379 
1380         dev_set_drvdata(&pdev->dev, ssi_private);
1381 
1382         if (ssi_private->soc->imx) {
1383                 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1384                 if (ret)
1385                         return ret;
1386         }
1387 
1388         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1389                                               &ssi_private->cpu_dai_drv, 1);
1390         if (ret) {
1391                 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1392                 goto error_asoc_register;
1393         }
1394 
1395         if (ssi_private->use_dma) {
1396                 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1397                                         fsl_ssi_isr, 0, dev_name(&pdev->dev),
1398                                         ssi_private);
1399                 if (ret < 0) {
1400                         dev_err(&pdev->dev, "could not claim irq %u\n",
1401                                         ssi_private->irq);
1402                         goto error_asoc_register;
1403                 }
1404         }
1405 
1406         ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1407         if (ret)
1408                 goto error_asoc_register;
1409 
1410         /*
1411          * If codec-handle property is missing from SSI node, we assume
1412          * that the machine driver uses new binding which does not require
1413          * SSI driver to trigger machine driver's probe.
1414          */
1415         if (!of_get_property(np, "codec-handle", NULL))
1416                 goto done;
1417 
1418         /* Trigger the machine driver's probe function.  The platform driver
1419          * name of the machine driver is taken from /compatible property of the
1420          * device tree.  We also pass the address of the CPU DAI driver
1421          * structure.
1422          */
1423         sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1424         /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1425         p = strrchr(sprop, ',');
1426         if (p)
1427                 sprop = p + 1;
1428         snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1429         make_lowercase(name);
1430 
1431         ssi_private->pdev =
1432                 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1433         if (IS_ERR(ssi_private->pdev)) {
1434                 ret = PTR_ERR(ssi_private->pdev);
1435                 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1436                 goto error_sound_card;
1437         }
1438 
1439 done:
1440         if (ssi_private->dai_fmt)
1441                 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
1442                                      ssi_private->dai_fmt);
1443 
1444         return 0;
1445 
1446 error_sound_card:
1447         fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1448 
1449 error_asoc_register:
1450         if (ssi_private->soc->imx)
1451                 fsl_ssi_imx_clean(pdev, ssi_private);
1452 
1453         return ret;
1454 }
1455 
1456 static int fsl_ssi_remove(struct platform_device *pdev)
1457 {
1458         struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1459 
1460         fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1461 
1462         if (ssi_private->pdev)
1463                 platform_device_unregister(ssi_private->pdev);
1464 
1465         if (ssi_private->soc->imx)
1466                 fsl_ssi_imx_clean(pdev, ssi_private);
1467 
1468         return 0;
1469 }
1470 
1471 static struct platform_driver fsl_ssi_driver = {
1472         .driver = {
1473                 .name = "fsl-ssi-dai",
1474                 .of_match_table = fsl_ssi_ids,
1475         },
1476         .probe = fsl_ssi_probe,
1477         .remove = fsl_ssi_remove,
1478 };
1479 
1480 module_platform_driver(fsl_ssi_driver);
1481 
1482 MODULE_ALIAS("platform:fsl-ssi-dai");
1483 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1484 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1485 MODULE_LICENSE("GPL v2");
1486 

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