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Linux/sound/soc/fsl/fsl_ssi.c

  1 /*
  2  * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
  3  *
  4  * Author: Timur Tabi <timur@freescale.com>
  5  *
  6  * Copyright 2007-2010 Freescale Semiconductor, Inc.
  7  *
  8  * This file is licensed under the terms of the GNU General Public License
  9  * version 2.  This program is licensed "as is" without any warranty of any
 10  * kind, whether express or implied.
 11  *
 12  *
 13  * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
 14  *
 15  * The i.MX SSI core has some nasty limitations in AC97 mode. While most
 16  * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
 17  * one FIFO which combines all valid receive slots. We cannot even select
 18  * which slots we want to receive. The WM9712 with which this driver
 19  * was developed with always sends GPIO status data in slot 12 which
 20  * we receive in our (PCM-) data stream. The only chance we have is to
 21  * manually skip this data in the FIQ handler. With sampling rates different
 22  * from 48000Hz not every frame has valid receive data, so the ratio
 23  * between pcm data and GPIO status data changes. Our FIQ handler is not
 24  * able to handle this, hence this driver only works with 48000Hz sampling
 25  * rate.
 26  * Reading and writing AC97 registers is another challenge. The core
 27  * provides us status bits when the read register is updated with *another*
 28  * value. When we read the same register two times (and the register still
 29  * contains the same value) these status bits are not set. We work
 30  * around this by not polling these bits but only wait a fixed delay.
 31  */
 32 
 33 #include <linux/init.h>
 34 #include <linux/io.h>
 35 #include <linux/module.h>
 36 #include <linux/interrupt.h>
 37 #include <linux/clk.h>
 38 #include <linux/device.h>
 39 #include <linux/delay.h>
 40 #include <linux/slab.h>
 41 #include <linux/spinlock.h>
 42 #include <linux/of.h>
 43 #include <linux/of_address.h>
 44 #include <linux/of_irq.h>
 45 #include <linux/of_platform.h>
 46 
 47 #include <sound/core.h>
 48 #include <sound/pcm.h>
 49 #include <sound/pcm_params.h>
 50 #include <sound/initval.h>
 51 #include <sound/soc.h>
 52 #include <sound/dmaengine_pcm.h>
 53 
 54 #include "fsl_ssi.h"
 55 #include "imx-pcm.h"
 56 
 57 /**
 58  * FSLSSI_I2S_RATES: sample rates supported by the I2S
 59  *
 60  * This driver currently only supports the SSI running in I2S slave mode,
 61  * which means the codec determines the sample rate.  Therefore, we tell
 62  * ALSA that we support all rates and let the codec driver decide what rates
 63  * are really supported.
 64  */
 65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
 66 
 67 /**
 68  * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
 69  *
 70  * The SSI has a limitation in that the samples must be in the same byte
 71  * order as the host CPU.  This is because when multiple bytes are written
 72  * to the STX register, the bytes and bits must be written in the same
 73  * order.  The STX is a shift register, so all the bits need to be aligned
 74  * (bit-endianness must match byte-endianness).  Processors typically write
 75  * the bits within a byte in the same order that the bytes of a word are
 76  * written in.  So if the host CPU is big-endian, then only big-endian
 77  * samples will be written to STX properly.
 78  */
 79 #ifdef __BIG_ENDIAN
 80 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
 81          SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
 82          SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
 83 #else
 84 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
 85          SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 86          SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
 87 #endif
 88 
 89 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
 90                 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
 91                 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
 92 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
 93                 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
 94                 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
 95 
 96 enum fsl_ssi_type {
 97         FSL_SSI_MCP8610,
 98         FSL_SSI_MX21,
 99         FSL_SSI_MX35,
100         FSL_SSI_MX51,
101 };
102 
103 struct fsl_ssi_reg_val {
104         u32 sier;
105         u32 srcr;
106         u32 stcr;
107         u32 scr;
108 };
109 
110 struct fsl_ssi_rxtx_reg_val {
111         struct fsl_ssi_reg_val rx;
112         struct fsl_ssi_reg_val tx;
113 };
114 static const struct regmap_config fsl_ssi_regconfig = {
115         .max_register = CCSR_SSI_SACCDIS,
116         .reg_bits = 32,
117         .val_bits = 32,
118         .reg_stride = 4,
119         .val_format_endian = REGMAP_ENDIAN_NATIVE,
120 };
121 
122 struct fsl_ssi_soc_data {
123         bool imx;
124         bool offline_config;
125         u32 sisr_write_mask;
126 };
127 
128 /**
129  * fsl_ssi_private: per-SSI private data
130  *
131  * @reg: Pointer to the regmap registers
132  * @irq: IRQ of this SSI
133  * @cpu_dai_drv: CPU DAI driver for this device
134  *
135  * @dai_fmt: DAI configuration this device is currently used with
136  * @i2s_mode: i2s and network mode configuration of the device. Is used to
137  * switch between normal and i2s/network mode
138  * mode depending on the number of channels
139  * @use_dma: DMA is used or FIQ with stream filter
140  * @use_dual_fifo: DMA with support for both FIFOs used
141  * @fifo_deph: Depth of the SSI FIFOs
142  * @rxtx_reg_val: Specific register settings for receive/transmit configuration
143  *
144  * @clk: SSI clock
145  * @baudclk: SSI baud clock for master mode
146  * @baudclk_streams: Active streams that are using baudclk
147  * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
148  *
149  * @dma_params_tx: DMA transmit parameters
150  * @dma_params_rx: DMA receive parameters
151  * @ssi_phys: physical address of the SSI registers
152  *
153  * @fiq_params: FIQ stream filtering parameters
154  *
155  * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
156  *
157  * @dbg_stats: Debugging statistics
158  *
159  * @soc: SoC specifc data
160  */
161 struct fsl_ssi_private {
162         struct regmap *regs;
163         unsigned int irq;
164         struct snd_soc_dai_driver cpu_dai_drv;
165 
166         unsigned int dai_fmt;
167         u8 i2s_mode;
168         bool use_dma;
169         bool use_dual_fifo;
170         bool has_ipg_clk_name;
171         unsigned int fifo_depth;
172         struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
173 
174         struct clk *clk;
175         struct clk *baudclk;
176         unsigned int baudclk_streams;
177         unsigned int bitclk_freq;
178 
179         /* DMA params */
180         struct snd_dmaengine_dai_dma_data dma_params_tx;
181         struct snd_dmaengine_dai_dma_data dma_params_rx;
182         dma_addr_t ssi_phys;
183 
184         /* params for non-dma FIQ stream filtered mode */
185         struct imx_pcm_fiq_params fiq_params;
186 
187         /* Used when using fsl-ssi as sound-card. This is only used by ppc and
188          * should be replaced with simple-sound-card. */
189         struct platform_device *pdev;
190 
191         struct fsl_ssi_dbg dbg_stats;
192 
193         const struct fsl_ssi_soc_data *soc;
194 };
195 
196 /*
197  * imx51 and later SoCs have a slightly different IP that allows the
198  * SSI configuration while the SSI unit is running.
199  *
200  * More important, it is necessary on those SoCs to configure the
201  * sperate TX/RX DMA bits just before starting the stream
202  * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
203  * sends any DMA requests to the SDMA unit, otherwise it is not defined
204  * how the SDMA unit handles the DMA request.
205  *
206  * SDMA units are present on devices starting at imx35 but the imx35
207  * reference manual states that the DMA bits should not be changed
208  * while the SSI unit is running (SSIEN). So we support the necessary
209  * online configuration of fsl-ssi starting at imx51.
210  */
211 
212 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
213         .imx = false,
214         .offline_config = true,
215         .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
216                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
217                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
218 };
219 
220 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
221         .imx = true,
222         .offline_config = true,
223         .sisr_write_mask = 0,
224 };
225 
226 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
227         .imx = true,
228         .offline_config = true,
229         .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
230                         CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
231                         CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
232 };
233 
234 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
235         .imx = true,
236         .offline_config = false,
237         .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
238                 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
239 };
240 
241 static const struct of_device_id fsl_ssi_ids[] = {
242         { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
243         { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
244         { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
245         { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
246         {}
247 };
248 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
249 
250 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
251 {
252         return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97);
253 }
254 
255 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
256 {
257         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
258                 SND_SOC_DAIFMT_CBS_CFS;
259 }
260 
261 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private)
262 {
263         return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
264                 SND_SOC_DAIFMT_CBM_CFS;
265 }
266 /**
267  * fsl_ssi_isr: SSI interrupt handler
268  *
269  * Although it's possible to use the interrupt handler to send and receive
270  * data to/from the SSI, we use the DMA instead.  Programming is more
271  * complicated, but the performance is much better.
272  *
273  * This interrupt handler is used only to gather statistics.
274  *
275  * @irq: IRQ of the SSI device
276  * @dev_id: pointer to the ssi_private structure for this SSI device
277  */
278 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
279 {
280         struct fsl_ssi_private *ssi_private = dev_id;
281         struct regmap *regs = ssi_private->regs;
282         __be32 sisr;
283         __be32 sisr2;
284 
285         /* We got an interrupt, so read the status register to see what we
286            were interrupted for.  We mask it with the Interrupt Enable register
287            so that we only check for events that we're interested in.
288          */
289         regmap_read(regs, CCSR_SSI_SISR, &sisr);
290 
291         sisr2 = sisr & ssi_private->soc->sisr_write_mask;
292         /* Clear the bits that we set */
293         if (sisr2)
294                 regmap_write(regs, CCSR_SSI_SISR, sisr2);
295 
296         fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
297 
298         return IRQ_HANDLED;
299 }
300 
301 /*
302  * Enable/Disable all rx/tx config flags at once.
303  */
304 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
305                 bool enable)
306 {
307         struct regmap *regs = ssi_private->regs;
308         struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
309 
310         if (enable) {
311                 regmap_update_bits(regs, CCSR_SSI_SIER,
312                                 vals->rx.sier | vals->tx.sier,
313                                 vals->rx.sier | vals->tx.sier);
314                 regmap_update_bits(regs, CCSR_SSI_SRCR,
315                                 vals->rx.srcr | vals->tx.srcr,
316                                 vals->rx.srcr | vals->tx.srcr);
317                 regmap_update_bits(regs, CCSR_SSI_STCR,
318                                 vals->rx.stcr | vals->tx.stcr,
319                                 vals->rx.stcr | vals->tx.stcr);
320         } else {
321                 regmap_update_bits(regs, CCSR_SSI_SRCR,
322                                 vals->rx.srcr | vals->tx.srcr, 0);
323                 regmap_update_bits(regs, CCSR_SSI_STCR,
324                                 vals->rx.stcr | vals->tx.stcr, 0);
325                 regmap_update_bits(regs, CCSR_SSI_SIER,
326                                 vals->rx.sier | vals->tx.sier, 0);
327         }
328 }
329 
330 /*
331  * Calculate the bits that have to be disabled for the current stream that is
332  * getting disabled. This keeps the bits enabled that are necessary for the
333  * second stream to work if 'stream_active' is true.
334  *
335  * Detailed calculation:
336  * These are the values that need to be active after disabling. For non-active
337  * second stream, this is 0:
338  *      vals_stream * !!stream_active
339  *
340  * The following computes the overall differences between the setup for the
341  * to-disable stream and the active stream, a simple XOR:
342  *      vals_disable ^ (vals_stream * !!(stream_active))
343  *
344  * The full expression adds a mask on all values we care about
345  */
346 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
347         ((vals_disable) & \
348          ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
349 
350 /*
351  * Enable/Disable a ssi configuration. You have to pass either
352  * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
353  */
354 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
355                 struct fsl_ssi_reg_val *vals)
356 {
357         struct regmap *regs = ssi_private->regs;
358         struct fsl_ssi_reg_val *avals;
359         int nr_active_streams;
360         u32 scr_val;
361         int keep_active;
362 
363         regmap_read(regs, CCSR_SSI_SCR, &scr_val);
364 
365         nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
366                                 !!(scr_val & CCSR_SSI_SCR_RE);
367 
368         if (nr_active_streams - 1 > 0)
369                 keep_active = 1;
370         else
371                 keep_active = 0;
372 
373         /* Find the other direction values rx or tx which we do not want to
374          * modify */
375         if (&ssi_private->rxtx_reg_val.rx == vals)
376                 avals = &ssi_private->rxtx_reg_val.tx;
377         else
378                 avals = &ssi_private->rxtx_reg_val.rx;
379 
380         /* If vals should be disabled, start with disabling the unit */
381         if (!enable) {
382                 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
383                                 keep_active);
384                 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
385         }
386 
387         /*
388          * We are running on a SoC which does not support online SSI
389          * reconfiguration, so we have to enable all necessary flags at once
390          * even if we do not use them later (capture and playback configuration)
391          */
392         if (ssi_private->soc->offline_config) {
393                 if ((enable && !nr_active_streams) ||
394                                 (!enable && !keep_active))
395                         fsl_ssi_rxtx_config(ssi_private, enable);
396 
397                 goto config_done;
398         }
399 
400         /*
401          * Configure single direction units while the SSI unit is running
402          * (online configuration)
403          */
404         if (enable) {
405                 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
406                 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
407                 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
408         } else {
409                 u32 sier;
410                 u32 srcr;
411                 u32 stcr;
412 
413                 /*
414                  * Disabling the necessary flags for one of rx/tx while the
415                  * other stream is active is a little bit more difficult. We
416                  * have to disable only those flags that differ between both
417                  * streams (rx XOR tx) and that are set in the stream that is
418                  * disabled now. Otherwise we could alter flags of the other
419                  * stream
420                  */
421 
422                 /* These assignments are simply vals without bits set in avals*/
423                 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
424                                 keep_active);
425                 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
426                                 keep_active);
427                 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
428                                 keep_active);
429 
430                 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
431                 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
432                 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
433         }
434 
435 config_done:
436         /* Enabling of subunits is done after configuration */
437         if (enable)
438                 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
439 }
440 
441 
442 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
443 {
444         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
445 }
446 
447 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
448 {
449         fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
450 }
451 
452 /*
453  * Setup rx/tx register values used to enable/disable the streams. These will
454  * be used later in fsl_ssi_config to setup the streams without the need to
455  * check for all different SSI modes.
456  */
457 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
458 {
459         struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
460 
461         reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
462         reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
463         reg->rx.scr = 0;
464         reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
465         reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
466         reg->tx.scr = 0;
467 
468         if (!fsl_ssi_is_ac97(ssi_private)) {
469                 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
470                 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
471                 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
472                 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
473         }
474 
475         if (ssi_private->use_dma) {
476                 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
477                 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
478         } else {
479                 reg->rx.sier |= CCSR_SSI_SIER_RIE;
480                 reg->tx.sier |= CCSR_SSI_SIER_TIE;
481         }
482 
483         reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
484         reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
485 }
486 
487 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
488 {
489         struct regmap *regs = ssi_private->regs;
490 
491         /*
492          * Setup the clock control register
493          */
494         regmap_write(regs, CCSR_SSI_STCCR,
495                         CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
496         regmap_write(regs, CCSR_SSI_SRCCR,
497                         CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
498 
499         /*
500          * Enable AC97 mode and startup the SSI
501          */
502         regmap_write(regs, CCSR_SSI_SACNT,
503                         CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
504         regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
505         regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
506 
507         /*
508          * Enable SSI, Transmit and Receive. AC97 has to communicate with the
509          * codec before a stream is started.
510          */
511         regmap_update_bits(regs, CCSR_SSI_SCR,
512                         CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
513                         CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
514 
515         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
516 }
517 
518 /**
519  * fsl_ssi_startup: create a new substream
520  *
521  * This is the first function called when a stream is opened.
522  *
523  * If this is the first stream open, then grab the IRQ and program most of
524  * the SSI registers.
525  */
526 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
527                            struct snd_soc_dai *dai)
528 {
529         struct snd_soc_pcm_runtime *rtd = substream->private_data;
530         struct fsl_ssi_private *ssi_private =
531                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
532         int ret;
533 
534         ret = clk_prepare_enable(ssi_private->clk);
535         if (ret)
536                 return ret;
537 
538         /* When using dual fifo mode, it is safer to ensure an even period
539          * size. If appearing to an odd number while DMA always starts its
540          * task from fifo0, fifo1 would be neglected at the end of each
541          * period. But SSI would still access fifo1 with an invalid data.
542          */
543         if (ssi_private->use_dual_fifo)
544                 snd_pcm_hw_constraint_step(substream->runtime, 0,
545                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
546 
547         return 0;
548 }
549 
550 /**
551  * fsl_ssi_shutdown: shutdown the SSI
552  *
553  */
554 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
555                                 struct snd_soc_dai *dai)
556 {
557         struct snd_soc_pcm_runtime *rtd = substream->private_data;
558         struct fsl_ssi_private *ssi_private =
559                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
560 
561         clk_disable_unprepare(ssi_private->clk);
562 
563 }
564 
565 /**
566  * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
567  *
568  * Note: This function can be only called when using SSI as DAI master
569  *
570  * Quick instruction for parameters:
571  * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
572  * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
573  */
574 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
575                 struct snd_soc_dai *cpu_dai,
576                 struct snd_pcm_hw_params *hw_params)
577 {
578         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
579         struct regmap *regs = ssi_private->regs;
580         int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
581         u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
582         unsigned long clkrate, baudrate, tmprate;
583         u64 sub, savesub = 100000;
584         unsigned int freq;
585         bool baudclk_is_used;
586 
587         /* Prefer the explicitly set bitclock frequency */
588         if (ssi_private->bitclk_freq)
589                 freq = ssi_private->bitclk_freq;
590         else
591                 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
592 
593         /* Don't apply it to any non-baudclk circumstance */
594         if (IS_ERR(ssi_private->baudclk))
595                 return -EINVAL;
596 
597         baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
598 
599         /* It should be already enough to divide clock by setting pm alone */
600         psr = 0;
601         div2 = 0;
602 
603         factor = (div2 + 1) * (7 * psr + 1) * 2;
604 
605         for (i = 0; i < 255; i++) {
606                 /* The bclk rate must be smaller than 1/5 sysclk rate */
607                 if (factor * (i + 1) < 5)
608                         continue;
609 
610                 tmprate = freq * factor * (i + 2);
611 
612                 if (baudclk_is_used)
613                         clkrate = clk_get_rate(ssi_private->baudclk);
614                 else
615                         clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
616 
617                 clkrate /= factor;
618                 afreq = clkrate / (i + 1);
619 
620                 if (freq == afreq)
621                         sub = 0;
622                 else if (freq / afreq == 1)
623                         sub = freq - afreq;
624                 else if (afreq / freq == 1)
625                         sub = afreq - freq;
626                 else
627                         continue;
628 
629                 /* Calculate the fraction */
630                 sub *= 100000;
631                 do_div(sub, freq);
632 
633                 if (sub < savesub) {
634                         baudrate = tmprate;
635                         savesub = sub;
636                         pm = i;
637                 }
638 
639                 /* We are lucky */
640                 if (savesub == 0)
641                         break;
642         }
643 
644         /* No proper pm found if it is still remaining the initial value */
645         if (pm == 999) {
646                 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
647                 return -EINVAL;
648         }
649 
650         stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
651                 (psr ? CCSR_SSI_SxCCR_PSR : 0);
652         mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
653                 CCSR_SSI_SxCCR_PSR;
654 
655         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
656                 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
657         else
658                 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
659 
660         if (!baudclk_is_used) {
661                 ret = clk_set_rate(ssi_private->baudclk, baudrate);
662                 if (ret) {
663                         dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
664                         return -EINVAL;
665                 }
666         }
667 
668         return 0;
669 }
670 
671 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
672                 int clk_id, unsigned int freq, int dir)
673 {
674         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
675 
676         ssi_private->bitclk_freq = freq;
677 
678         return 0;
679 }
680 
681 /**
682  * fsl_ssi_hw_params - program the sample size
683  *
684  * Most of the SSI registers have been programmed in the startup function,
685  * but the word length must be programmed here.  Unfortunately, programming
686  * the SxCCR.WL bits requires the SSI to be temporarily disabled.  This can
687  * cause a problem with supporting simultaneous playback and capture.  If
688  * the SSI is already playing a stream, then that stream may be temporarily
689  * stopped when you start capture.
690  *
691  * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
692  * clock master.
693  */
694 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
695         struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
696 {
697         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
698         struct regmap *regs = ssi_private->regs;
699         unsigned int channels = params_channels(hw_params);
700         unsigned int sample_size =
701                 snd_pcm_format_width(params_format(hw_params));
702         u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
703         int ret;
704         u32 scr_val;
705         int enabled;
706 
707         regmap_read(regs, CCSR_SSI_SCR, &scr_val);
708         enabled = scr_val & CCSR_SSI_SCR_SSIEN;
709 
710         /*
711          * If we're in synchronous mode, and the SSI is already enabled,
712          * then STCCR is already set properly.
713          */
714         if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
715                 return 0;
716 
717         if (fsl_ssi_is_i2s_master(ssi_private)) {
718                 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
719                 if (ret)
720                         return ret;
721 
722                 /* Do not enable the clock if it is already enabled */
723                 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
724                         ret = clk_prepare_enable(ssi_private->baudclk);
725                         if (ret)
726                                 return ret;
727 
728                         ssi_private->baudclk_streams |= BIT(substream->stream);
729                 }
730         }
731 
732         if (!fsl_ssi_is_ac97(ssi_private)) {
733                 u8 i2smode;
734                 /*
735                  * Switch to normal net mode in order to have a frame sync
736                  * signal every 32 bits instead of 16 bits
737                  */
738                 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16)
739                         i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL |
740                                 CCSR_SSI_SCR_NET;
741                 else
742                         i2smode = ssi_private->i2s_mode;
743 
744                 regmap_update_bits(regs, CCSR_SSI_SCR,
745                                 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
746                                 channels == 1 ? 0 : i2smode);
747         }
748 
749         /*
750          * FIXME: The documentation says that SxCCR[WL] should not be
751          * modified while the SSI is enabled.  The only time this can
752          * happen is if we're trying to do simultaneous playback and
753          * capture in asynchronous mode.  Unfortunately, I have been enable
754          * to get that to work at all on the P1022DS.  Therefore, we don't
755          * bother to disable/enable the SSI when setting SxCCR[WL], because
756          * the SSI will stop anyway.  Maybe one day, this will get fixed.
757          */
758 
759         /* In synchronous mode, the SSI uses STCCR for capture */
760         if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
761             ssi_private->cpu_dai_drv.symmetric_rates)
762                 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
763                                 wl);
764         else
765                 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
766                                 wl);
767 
768         return 0;
769 }
770 
771 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
772                 struct snd_soc_dai *cpu_dai)
773 {
774         struct snd_soc_pcm_runtime *rtd = substream->private_data;
775         struct fsl_ssi_private *ssi_private =
776                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
777 
778         if (fsl_ssi_is_i2s_master(ssi_private) &&
779                         ssi_private->baudclk_streams & BIT(substream->stream)) {
780                 clk_disable_unprepare(ssi_private->baudclk);
781                 ssi_private->baudclk_streams &= ~BIT(substream->stream);
782         }
783 
784         return 0;
785 }
786 
787 static int _fsl_ssi_set_dai_fmt(struct device *dev,
788                                 struct fsl_ssi_private *ssi_private,
789                                 unsigned int fmt)
790 {
791         struct regmap *regs = ssi_private->regs;
792         u32 strcr = 0, stcr, srcr, scr, mask;
793         u8 wm;
794 
795         ssi_private->dai_fmt = fmt;
796 
797         if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
798                 dev_err(dev, "baudclk is missing which is necessary for master mode\n");
799                 return -EINVAL;
800         }
801 
802         fsl_ssi_setup_reg_vals(ssi_private);
803 
804         regmap_read(regs, CCSR_SSI_SCR, &scr);
805         scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
806         scr |= CCSR_SSI_SCR_SYNC_TX_FS;
807 
808         mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
809                 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
810                 CCSR_SSI_STCR_TEFS;
811         regmap_read(regs, CCSR_SSI_STCR, &stcr);
812         regmap_read(regs, CCSR_SSI_SRCR, &srcr);
813         stcr &= ~mask;
814         srcr &= ~mask;
815 
816         ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
817         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
818         case SND_SOC_DAIFMT_I2S:
819                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
820                 case SND_SOC_DAIFMT_CBM_CFS:
821                 case SND_SOC_DAIFMT_CBS_CFS:
822                         ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
823                         regmap_update_bits(regs, CCSR_SSI_STCCR,
824                                         CCSR_SSI_SxCCR_DC_MASK,
825                                         CCSR_SSI_SxCCR_DC(2));
826                         regmap_update_bits(regs, CCSR_SSI_SRCCR,
827                                         CCSR_SSI_SxCCR_DC_MASK,
828                                         CCSR_SSI_SxCCR_DC(2));
829                         break;
830                 case SND_SOC_DAIFMT_CBM_CFM:
831                         ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
832                         break;
833                 default:
834                         return -EINVAL;
835                 }
836 
837                 /* Data on rising edge of bclk, frame low, 1clk before data */
838                 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
839                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
840                 break;
841         case SND_SOC_DAIFMT_LEFT_J:
842                 /* Data on rising edge of bclk, frame high */
843                 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
844                 break;
845         case SND_SOC_DAIFMT_DSP_A:
846                 /* Data on rising edge of bclk, frame high, 1clk before data */
847                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
848                         CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
849                 break;
850         case SND_SOC_DAIFMT_DSP_B:
851                 /* Data on rising edge of bclk, frame high */
852                 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
853                         CCSR_SSI_STCR_TXBIT0;
854                 break;
855         case SND_SOC_DAIFMT_AC97:
856                 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
857                 break;
858         default:
859                 return -EINVAL;
860         }
861         scr |= ssi_private->i2s_mode;
862 
863         /* DAI clock inversion */
864         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
865         case SND_SOC_DAIFMT_NB_NF:
866                 /* Nothing to do for both normal cases */
867                 break;
868         case SND_SOC_DAIFMT_IB_NF:
869                 /* Invert bit clock */
870                 strcr ^= CCSR_SSI_STCR_TSCKP;
871                 break;
872         case SND_SOC_DAIFMT_NB_IF:
873                 /* Invert frame clock */
874                 strcr ^= CCSR_SSI_STCR_TFSI;
875                 break;
876         case SND_SOC_DAIFMT_IB_IF:
877                 /* Invert both clocks */
878                 strcr ^= CCSR_SSI_STCR_TSCKP;
879                 strcr ^= CCSR_SSI_STCR_TFSI;
880                 break;
881         default:
882                 return -EINVAL;
883         }
884 
885         /* DAI clock master masks */
886         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
887         case SND_SOC_DAIFMT_CBS_CFS:
888                 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
889                 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
890                 break;
891         case SND_SOC_DAIFMT_CBM_CFM:
892                 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
893                 break;
894         case SND_SOC_DAIFMT_CBM_CFS:
895                 strcr &= ~CCSR_SSI_STCR_TXDIR;
896                 strcr |= CCSR_SSI_STCR_TFDIR;
897                 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
898                 break;
899         default:
900                 return -EINVAL;
901         }
902 
903         stcr |= strcr;
904         srcr |= strcr;
905 
906         if (ssi_private->cpu_dai_drv.symmetric_rates) {
907                 /* Need to clear RXDIR when using SYNC mode */
908                 srcr &= ~CCSR_SSI_SRCR_RXDIR;
909                 scr |= CCSR_SSI_SCR_SYN;
910         }
911 
912         regmap_write(regs, CCSR_SSI_STCR, stcr);
913         regmap_write(regs, CCSR_SSI_SRCR, srcr);
914         regmap_write(regs, CCSR_SSI_SCR, scr);
915 
916         /*
917          * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
918          * use FIFO 1. We program the transmit water to signal a DMA transfer
919          * if there are only two (or fewer) elements left in the FIFO. Two
920          * elements equals one frame (left channel, right channel). This value,
921          * however, depends on the depth of the transmit buffer.
922          *
923          * We set the watermark on the same level as the DMA burstsize.  For
924          * fiq it is probably better to use the biggest possible watermark
925          * size.
926          */
927         if (ssi_private->use_dma)
928                 wm = ssi_private->fifo_depth - 2;
929         else
930                 wm = ssi_private->fifo_depth;
931 
932         regmap_write(regs, CCSR_SSI_SFCSR,
933                         CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
934                         CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
935 
936         if (ssi_private->use_dual_fifo) {
937                 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
938                                 CCSR_SSI_SRCR_RFEN1);
939                 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
940                                 CCSR_SSI_STCR_TFEN1);
941                 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
942                                 CCSR_SSI_SCR_TCH_EN);
943         }
944 
945         if (fmt & SND_SOC_DAIFMT_AC97)
946                 fsl_ssi_setup_ac97(ssi_private);
947 
948         return 0;
949 
950 }
951 
952 /**
953  * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
954  */
955 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
956 {
957         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
958 
959         return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
960 }
961 
962 /**
963  * fsl_ssi_set_dai_tdm_slot - set TDM slot number
964  *
965  * Note: This function can be only called when using SSI as DAI master
966  */
967 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
968                                 u32 rx_mask, int slots, int slot_width)
969 {
970         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
971         struct regmap *regs = ssi_private->regs;
972         u32 val;
973 
974         /* The slot number should be >= 2 if using Network mode or I2S mode */
975         regmap_read(regs, CCSR_SSI_SCR, &val);
976         val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
977         if (val && slots < 2) {
978                 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
979                 return -EINVAL;
980         }
981 
982         regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
983                         CCSR_SSI_SxCCR_DC(slots));
984         regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
985                         CCSR_SSI_SxCCR_DC(slots));
986 
987         /* The register SxMSKs needs SSI to provide essential clock due to
988          * hardware design. So we here temporarily enable SSI to set them.
989          */
990         regmap_read(regs, CCSR_SSI_SCR, &val);
991         val &= CCSR_SSI_SCR_SSIEN;
992         regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
993                         CCSR_SSI_SCR_SSIEN);
994 
995         regmap_write(regs, CCSR_SSI_STMSK, tx_mask);
996         regmap_write(regs, CCSR_SSI_SRMSK, rx_mask);
997 
998         regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
999 
1000         return 0;
1001 }
1002 
1003 /**
1004  * fsl_ssi_trigger: start and stop the DMA transfer.
1005  *
1006  * This function is called by ALSA to start, stop, pause, and resume the DMA
1007  * transfer of data.
1008  *
1009  * The DMA channel is in external master start and pause mode, which
1010  * means the SSI completely controls the flow of data.
1011  */
1012 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1013                            struct snd_soc_dai *dai)
1014 {
1015         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1016         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1017         struct regmap *regs = ssi_private->regs;
1018 
1019         switch (cmd) {
1020         case SNDRV_PCM_TRIGGER_START:
1021         case SNDRV_PCM_TRIGGER_RESUME:
1022         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1023                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1024                         fsl_ssi_tx_config(ssi_private, true);
1025                 else
1026                         fsl_ssi_rx_config(ssi_private, true);
1027                 break;
1028 
1029         case SNDRV_PCM_TRIGGER_STOP:
1030         case SNDRV_PCM_TRIGGER_SUSPEND:
1031         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1032                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1033                         fsl_ssi_tx_config(ssi_private, false);
1034                 else
1035                         fsl_ssi_rx_config(ssi_private, false);
1036                 break;
1037 
1038         default:
1039                 return -EINVAL;
1040         }
1041 
1042         if (fsl_ssi_is_ac97(ssi_private)) {
1043                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1044                         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1045                 else
1046                         regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1047         }
1048 
1049         return 0;
1050 }
1051 
1052 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1053 {
1054         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1055 
1056         if (ssi_private->soc->imx && ssi_private->use_dma) {
1057                 dai->playback_dma_data = &ssi_private->dma_params_tx;
1058                 dai->capture_dma_data = &ssi_private->dma_params_rx;
1059         }
1060 
1061         return 0;
1062 }
1063 
1064 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1065         .startup        = fsl_ssi_startup,
1066         .shutdown       = fsl_ssi_shutdown,
1067         .hw_params      = fsl_ssi_hw_params,
1068         .hw_free        = fsl_ssi_hw_free,
1069         .set_fmt        = fsl_ssi_set_dai_fmt,
1070         .set_sysclk     = fsl_ssi_set_dai_sysclk,
1071         .set_tdm_slot   = fsl_ssi_set_dai_tdm_slot,
1072         .trigger        = fsl_ssi_trigger,
1073 };
1074 
1075 /* Template for the CPU dai driver structure */
1076 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1077         .probe = fsl_ssi_dai_probe,
1078         .playback = {
1079                 .stream_name = "CPU-Playback",
1080                 .channels_min = 1,
1081                 .channels_max = 2,
1082                 .rates = FSLSSI_I2S_RATES,
1083                 .formats = FSLSSI_I2S_FORMATS,
1084         },
1085         .capture = {
1086                 .stream_name = "CPU-Capture",
1087                 .channels_min = 1,
1088                 .channels_max = 2,
1089                 .rates = FSLSSI_I2S_RATES,
1090                 .formats = FSLSSI_I2S_FORMATS,
1091         },
1092         .ops = &fsl_ssi_dai_ops,
1093 };
1094 
1095 static const struct snd_soc_component_driver fsl_ssi_component = {
1096         .name           = "fsl-ssi",
1097 };
1098 
1099 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1100         .bus_control = true,
1101         .playback = {
1102                 .stream_name = "AC97 Playback",
1103                 .channels_min = 2,
1104                 .channels_max = 2,
1105                 .rates = SNDRV_PCM_RATE_8000_48000,
1106                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1107         },
1108         .capture = {
1109                 .stream_name = "AC97 Capture",
1110                 .channels_min = 2,
1111                 .channels_max = 2,
1112                 .rates = SNDRV_PCM_RATE_48000,
1113                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1114         },
1115         .ops = &fsl_ssi_dai_ops,
1116 };
1117 
1118 
1119 static struct fsl_ssi_private *fsl_ac97_data;
1120 
1121 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1122                 unsigned short val)
1123 {
1124         struct regmap *regs = fsl_ac97_data->regs;
1125         unsigned int lreg;
1126         unsigned int lval;
1127 
1128         if (reg > 0x7f)
1129                 return;
1130 
1131 
1132         lreg = reg <<  12;
1133         regmap_write(regs, CCSR_SSI_SACADD, lreg);
1134 
1135         lval = val << 4;
1136         regmap_write(regs, CCSR_SSI_SACDAT, lval);
1137 
1138         regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1139                         CCSR_SSI_SACNT_WR);
1140         udelay(100);
1141 }
1142 
1143 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1144                 unsigned short reg)
1145 {
1146         struct regmap *regs = fsl_ac97_data->regs;
1147 
1148         unsigned short val = -1;
1149         u32 reg_val;
1150         unsigned int lreg;
1151 
1152         lreg = (reg & 0x7f) <<  12;
1153         regmap_write(regs, CCSR_SSI_SACADD, lreg);
1154         regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1155                         CCSR_SSI_SACNT_RD);
1156 
1157         udelay(100);
1158 
1159         regmap_read(regs, CCSR_SSI_SACDAT, &reg_val);
1160         val = (reg_val >> 4) & 0xffff;
1161 
1162         return val;
1163 }
1164 
1165 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1166         .read           = fsl_ssi_ac97_read,
1167         .write          = fsl_ssi_ac97_write,
1168 };
1169 
1170 /**
1171  * Make every character in a string lower-case
1172  */
1173 static void make_lowercase(char *s)
1174 {
1175         char *p = s;
1176         char c;
1177 
1178         while ((c = *p)) {
1179                 if ((c >= 'A') && (c <= 'Z'))
1180                         *p = c + ('a' - 'A');
1181                 p++;
1182         }
1183 }
1184 
1185 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1186                 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1187 {
1188         struct device_node *np = pdev->dev.of_node;
1189         u32 dmas[4];
1190         int ret;
1191 
1192         if (ssi_private->has_ipg_clk_name)
1193                 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
1194         else
1195                 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1196         if (IS_ERR(ssi_private->clk)) {
1197                 ret = PTR_ERR(ssi_private->clk);
1198                 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1199                 return ret;
1200         }
1201 
1202         if (!ssi_private->has_ipg_clk_name) {
1203                 ret = clk_prepare_enable(ssi_private->clk);
1204                 if (ret) {
1205                         dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1206                         return ret;
1207                 }
1208         }
1209 
1210         /* For those SLAVE implementations, we ingore non-baudclk cases
1211          * and, instead, abandon MASTER mode that needs baud clock.
1212          */
1213         ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1214         if (IS_ERR(ssi_private->baudclk))
1215                 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1216                          PTR_ERR(ssi_private->baudclk));
1217 
1218         /*
1219          * We have burstsize be "fifo_depth - 2" to match the SSI
1220          * watermark setting in fsl_ssi_startup().
1221          */
1222         ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1223         ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1224         ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1225         ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1226 
1227         ret = !of_property_read_u32_array(np, "dmas", dmas, 4);
1228         if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1229                 ssi_private->use_dual_fifo = true;
1230                 /* When using dual fifo mode, we need to keep watermark
1231                  * as even numbers due to dma script limitation.
1232                  */
1233                 ssi_private->dma_params_tx.maxburst &= ~0x1;
1234                 ssi_private->dma_params_rx.maxburst &= ~0x1;
1235         }
1236 
1237         if (!ssi_private->use_dma) {
1238 
1239                 /*
1240                  * Some boards use an incompatible codec. To get it
1241                  * working, we are using imx-fiq-pcm-audio, that
1242                  * can handle those codecs. DMA is not possible in this
1243                  * situation.
1244                  */
1245 
1246                 ssi_private->fiq_params.irq = ssi_private->irq;
1247                 ssi_private->fiq_params.base = iomem;
1248                 ssi_private->fiq_params.dma_params_rx =
1249                         &ssi_private->dma_params_rx;
1250                 ssi_private->fiq_params.dma_params_tx =
1251                         &ssi_private->dma_params_tx;
1252 
1253                 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1254                 if (ret)
1255                         goto error_pcm;
1256         } else {
1257                 ret = imx_pcm_dma_init(pdev);
1258                 if (ret)
1259                         goto error_pcm;
1260         }
1261 
1262         return 0;
1263 
1264 error_pcm:
1265 
1266         if (!ssi_private->has_ipg_clk_name)
1267                 clk_disable_unprepare(ssi_private->clk);
1268         return ret;
1269 }
1270 
1271 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1272                 struct fsl_ssi_private *ssi_private)
1273 {
1274         if (!ssi_private->use_dma)
1275                 imx_pcm_fiq_exit(pdev);
1276         if (!ssi_private->has_ipg_clk_name)
1277                 clk_disable_unprepare(ssi_private->clk);
1278 }
1279 
1280 static int fsl_ssi_probe(struct platform_device *pdev)
1281 {
1282         struct fsl_ssi_private *ssi_private;
1283         int ret = 0;
1284         struct device_node *np = pdev->dev.of_node;
1285         const struct of_device_id *of_id;
1286         const char *p, *sprop;
1287         const uint32_t *iprop;
1288         struct resource res;
1289         void __iomem *iomem;
1290         char name[64];
1291 
1292         /* SSIs that are not connected on the board should have a
1293          *      status = "disabled"
1294          * property in their device tree nodes.
1295          */
1296         if (!of_device_is_available(np))
1297                 return -ENODEV;
1298 
1299         of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1300         if (!of_id || !of_id->data)
1301                 return -EINVAL;
1302 
1303         ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1304                         GFP_KERNEL);
1305         if (!ssi_private) {
1306                 dev_err(&pdev->dev, "could not allocate DAI object\n");
1307                 return -ENOMEM;
1308         }
1309 
1310         ssi_private->soc = of_id->data;
1311 
1312         sprop = of_get_property(np, "fsl,mode", NULL);
1313         if (sprop) {
1314                 if (!strcmp(sprop, "ac97-slave"))
1315                         ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1316         }
1317 
1318         ssi_private->use_dma = !of_property_read_bool(np,
1319                         "fsl,fiq-stream-filter");
1320 
1321         if (fsl_ssi_is_ac97(ssi_private)) {
1322                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1323                                 sizeof(fsl_ssi_ac97_dai));
1324 
1325                 fsl_ac97_data = ssi_private;
1326 
1327                 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1328         } else {
1329                 /* Initialize this copy of the CPU DAI driver structure */
1330                 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1331                        sizeof(fsl_ssi_dai_template));
1332         }
1333         ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1334 
1335         /* Get the addresses and IRQ */
1336         ret = of_address_to_resource(np, 0, &res);
1337         if (ret) {
1338                 dev_err(&pdev->dev, "could not determine device resources\n");
1339                 return ret;
1340         }
1341         ssi_private->ssi_phys = res.start;
1342 
1343         iomem = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
1344         if (!iomem) {
1345                 dev_err(&pdev->dev, "could not map device resources\n");
1346                 return -ENOMEM;
1347         }
1348 
1349         ret = of_property_match_string(np, "clock-names", "ipg");
1350         if (ret < 0) {
1351                 ssi_private->has_ipg_clk_name = false;
1352                 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1353                         &fsl_ssi_regconfig);
1354         } else {
1355                 ssi_private->has_ipg_clk_name = true;
1356                 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
1357                         "ipg", iomem, &fsl_ssi_regconfig);
1358         }
1359         if (IS_ERR(ssi_private->regs)) {
1360                 dev_err(&pdev->dev, "Failed to init register map\n");
1361                 return PTR_ERR(ssi_private->regs);
1362         }
1363 
1364         ssi_private->irq = platform_get_irq(pdev, 0);
1365         if (ssi_private->irq < 0) {
1366                 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1367                 return ssi_private->irq;
1368         }
1369 
1370         /* Are the RX and the TX clocks locked? */
1371         if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1372                 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1373                 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1374                 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1375         }
1376 
1377         /* Determine the FIFO depth. */
1378         iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1379         if (iprop)
1380                 ssi_private->fifo_depth = be32_to_cpup(iprop);
1381         else
1382                 /* Older 8610 DTs didn't have the fifo-depth property */
1383                 ssi_private->fifo_depth = 8;
1384 
1385         dev_set_drvdata(&pdev->dev, ssi_private);
1386 
1387         if (ssi_private->soc->imx) {
1388                 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1389                 if (ret)
1390                         return ret;
1391         }
1392 
1393         ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1394                                          &ssi_private->cpu_dai_drv, 1);
1395         if (ret) {
1396                 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1397                 goto error_asoc_register;
1398         }
1399 
1400         if (ssi_private->use_dma) {
1401                 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1402                                         fsl_ssi_isr, 0, dev_name(&pdev->dev),
1403                                         ssi_private);
1404                 if (ret < 0) {
1405                         dev_err(&pdev->dev, "could not claim irq %u\n",
1406                                         ssi_private->irq);
1407                         goto error_irq;
1408                 }
1409         }
1410 
1411         ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1412         if (ret)
1413                 goto error_irq;
1414 
1415         /*
1416          * If codec-handle property is missing from SSI node, we assume
1417          * that the machine driver uses new binding which does not require
1418          * SSI driver to trigger machine driver's probe.
1419          */
1420         if (!of_get_property(np, "codec-handle", NULL))
1421                 goto done;
1422 
1423         /* Trigger the machine driver's probe function.  The platform driver
1424          * name of the machine driver is taken from /compatible property of the
1425          * device tree.  We also pass the address of the CPU DAI driver
1426          * structure.
1427          */
1428         sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1429         /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1430         p = strrchr(sprop, ',');
1431         if (p)
1432                 sprop = p + 1;
1433         snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1434         make_lowercase(name);
1435 
1436         ssi_private->pdev =
1437                 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1438         if (IS_ERR(ssi_private->pdev)) {
1439                 ret = PTR_ERR(ssi_private->pdev);
1440                 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1441                 goto error_sound_card;
1442         }
1443 
1444 done:
1445         if (ssi_private->dai_fmt)
1446                 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
1447                                      ssi_private->dai_fmt);
1448 
1449         return 0;
1450 
1451 error_sound_card:
1452         fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1453 
1454 error_irq:
1455         snd_soc_unregister_component(&pdev->dev);
1456 
1457 error_asoc_register:
1458         if (ssi_private->soc->imx)
1459                 fsl_ssi_imx_clean(pdev, ssi_private);
1460 
1461         return ret;
1462 }
1463 
1464 static int fsl_ssi_remove(struct platform_device *pdev)
1465 {
1466         struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1467 
1468         fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1469 
1470         if (ssi_private->pdev)
1471                 platform_device_unregister(ssi_private->pdev);
1472         snd_soc_unregister_component(&pdev->dev);
1473 
1474         if (ssi_private->soc->imx)
1475                 fsl_ssi_imx_clean(pdev, ssi_private);
1476 
1477         return 0;
1478 }
1479 
1480 static struct platform_driver fsl_ssi_driver = {
1481         .driver = {
1482                 .name = "fsl-ssi-dai",
1483                 .of_match_table = fsl_ssi_ids,
1484         },
1485         .probe = fsl_ssi_probe,
1486         .remove = fsl_ssi_remove,
1487 };
1488 
1489 module_platform_driver(fsl_ssi_driver);
1490 
1491 MODULE_ALIAS("platform:fsl-ssi-dai");
1492 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1493 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1494 MODULE_LICENSE("GPL v2");
1495 

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