Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/sound/soc/fsl/fsl_spdif.c

  1 /*
  2  * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
  3  *
  4  * Copyright (C) 2013 Freescale Semiconductor, Inc.
  5  *
  6  * Based on stmp3xxx_spdif_dai.c
  7  * Vladimir Barinov <vbarinov@embeddedalley.com>
  8  * Copyright 2008 SigmaTel, Inc
  9  * Copyright 2008 Embedded Alley Solutions, Inc
 10  *
 11  * This file is licensed under the terms of the GNU General Public License
 12  * version 2.  This program  is licensed "as is" without any warranty of any
 13  * kind, whether express or implied.
 14  */
 15 
 16 #include <linux/bitrev.h>
 17 #include <linux/clk.h>
 18 #include <linux/module.h>
 19 #include <linux/of_address.h>
 20 #include <linux/of_device.h>
 21 #include <linux/of_irq.h>
 22 #include <linux/regmap.h>
 23 
 24 #include <sound/asoundef.h>
 25 #include <sound/dmaengine_pcm.h>
 26 #include <sound/soc.h>
 27 
 28 #include "fsl_spdif.h"
 29 #include "imx-pcm.h"
 30 
 31 #define FSL_SPDIF_TXFIFO_WML    0x8
 32 #define FSL_SPDIF_RXFIFO_WML    0x8
 33 
 34 #define INTR_FOR_PLAYBACK       (INT_TXFIFO_RESYNC)
 35 #define INTR_FOR_CAPTURE        (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
 36                                 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
 37                                 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
 38                                 INT_LOSS_LOCK | INT_DPLL_LOCKED)
 39 
 40 #define SIE_INTR_FOR(tx)        (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
 41 
 42 /* Index list for the values that has if (DPLL Locked) condition */
 43 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
 44 #define SRPC_NODPLL_START1      0x5
 45 #define SRPC_NODPLL_START2      0xc
 46 
 47 #define DEFAULT_RXCLK_SRC       1
 48 
 49 /*
 50  * SPDIF control structure
 51  * Defines channel status, subcode and Q sub
 52  */
 53 struct spdif_mixer_control {
 54         /* spinlock to access control data */
 55         spinlock_t ctl_lock;
 56 
 57         /* IEC958 channel tx status bit */
 58         unsigned char ch_status[4];
 59 
 60         /* User bits */
 61         unsigned char subcode[2 * SPDIF_UBITS_SIZE];
 62 
 63         /* Q subcode part of user bits */
 64         unsigned char qsub[2 * SPDIF_QSUB_SIZE];
 65 
 66         /* Buffer offset for U/Q */
 67         u32 upos;
 68         u32 qpos;
 69 
 70         /* Ready buffer index of the two buffers */
 71         u32 ready_buf;
 72 };
 73 
 74 /**
 75  * fsl_spdif_priv: Freescale SPDIF private data
 76  *
 77  * @fsl_spdif_control: SPDIF control data
 78  * @cpu_dai_drv: cpu dai driver
 79  * @pdev: platform device pointer
 80  * @regmap: regmap handler
 81  * @dpll_locked: dpll lock flag
 82  * @txrate: the best rates for playback
 83  * @txclk_df: STC_TXCLK_DF dividers value for playback
 84  * @sysclk_df: STC_SYSCLK_DF dividers value for playback
 85  * @txclk_src: STC_TXCLK_SRC values for playback
 86  * @rxclk_src: SRPC_CLKSRC_SEL values for capture
 87  * @txclk: tx clock sources for playback
 88  * @rxclk: rx clock sources for capture
 89  * @coreclk: core clock for register access via DMA
 90  * @sysclk: system clock for rx clock rate measurement
 91  * @dma_params_tx: DMA parameters for transmit channel
 92  * @dma_params_rx: DMA parameters for receive channel
 93  */
 94 struct fsl_spdif_priv {
 95         struct spdif_mixer_control fsl_spdif_control;
 96         struct snd_soc_dai_driver cpu_dai_drv;
 97         struct platform_device *pdev;
 98         struct regmap *regmap;
 99         bool dpll_locked;
100         u32 txrate[SPDIF_TXRATE_MAX];
101         u8 txclk_df[SPDIF_TXRATE_MAX];
102         u8 sysclk_df[SPDIF_TXRATE_MAX];
103         u8 txclk_src[SPDIF_TXRATE_MAX];
104         u8 rxclk_src;
105         struct clk *txclk[SPDIF_TXRATE_MAX];
106         struct clk *rxclk;
107         struct clk *coreclk;
108         struct clk *sysclk;
109         struct snd_dmaengine_dai_dma_data dma_params_tx;
110         struct snd_dmaengine_dai_dma_data dma_params_rx;
111         /* regcache for SRPC */
112         u32 regcache_srpc;
113 };
114 
115 /* DPLL locked and lock loss interrupt handler */
116 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
117 {
118         struct regmap *regmap = spdif_priv->regmap;
119         struct platform_device *pdev = spdif_priv->pdev;
120         u32 locked;
121 
122         regmap_read(regmap, REG_SPDIF_SRPC, &locked);
123         locked &= SRPC_DPLL_LOCKED;
124 
125         dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
126                         locked ? "locked" : "loss lock");
127 
128         spdif_priv->dpll_locked = locked ? true : false;
129 }
130 
131 /* Receiver found illegal symbol interrupt handler */
132 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
133 {
134         struct regmap *regmap = spdif_priv->regmap;
135         struct platform_device *pdev = spdif_priv->pdev;
136 
137         dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
138 
139         /* Clear illegal symbol if DPLL unlocked since no audio stream */
140         if (!spdif_priv->dpll_locked)
141                 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
142 }
143 
144 /* U/Q Channel receive register full */
145 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
146 {
147         struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
148         struct regmap *regmap = spdif_priv->regmap;
149         struct platform_device *pdev = spdif_priv->pdev;
150         u32 *pos, size, val, reg;
151 
152         switch (name) {
153         case 'U':
154                 pos = &ctrl->upos;
155                 size = SPDIF_UBITS_SIZE;
156                 reg = REG_SPDIF_SRU;
157                 break;
158         case 'Q':
159                 pos = &ctrl->qpos;
160                 size = SPDIF_QSUB_SIZE;
161                 reg = REG_SPDIF_SRQ;
162                 break;
163         default:
164                 dev_err(&pdev->dev, "unsupported channel name\n");
165                 return;
166         }
167 
168         dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
169 
170         if (*pos >= size * 2) {
171                 *pos = 0;
172         } else if (unlikely((*pos % size) + 3 > size)) {
173                 dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
174                 return;
175         }
176 
177         regmap_read(regmap, reg, &val);
178         ctrl->subcode[*pos++] = val >> 16;
179         ctrl->subcode[*pos++] = val >> 8;
180         ctrl->subcode[*pos++] = val;
181 }
182 
183 /* U/Q Channel sync found */
184 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
185 {
186         struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
187         struct platform_device *pdev = spdif_priv->pdev;
188 
189         dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
190 
191         /* U/Q buffer reset */
192         if (ctrl->qpos == 0)
193                 return;
194 
195         /* Set ready to this buffer */
196         ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
197 }
198 
199 /* U/Q Channel framing error */
200 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
201 {
202         struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
203         struct regmap *regmap = spdif_priv->regmap;
204         struct platform_device *pdev = spdif_priv->pdev;
205         u32 val;
206 
207         dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
208 
209         /* Read U/Q data to clear the irq and do buffer reset */
210         regmap_read(regmap, REG_SPDIF_SRU, &val);
211         regmap_read(regmap, REG_SPDIF_SRQ, &val);
212 
213         /* Drop this U/Q buffer */
214         ctrl->ready_buf = 0;
215         ctrl->upos = 0;
216         ctrl->qpos = 0;
217 }
218 
219 /* Get spdif interrupt status and clear the interrupt */
220 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
221 {
222         struct regmap *regmap = spdif_priv->regmap;
223         u32 val, val2;
224 
225         regmap_read(regmap, REG_SPDIF_SIS, &val);
226         regmap_read(regmap, REG_SPDIF_SIE, &val2);
227 
228         regmap_write(regmap, REG_SPDIF_SIC, val & val2);
229 
230         return val;
231 }
232 
233 static irqreturn_t spdif_isr(int irq, void *devid)
234 {
235         struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
236         struct platform_device *pdev = spdif_priv->pdev;
237         u32 sis;
238 
239         sis = spdif_intr_status_clear(spdif_priv);
240 
241         if (sis & INT_DPLL_LOCKED)
242                 spdif_irq_dpll_lock(spdif_priv);
243 
244         if (sis & INT_TXFIFO_UNOV)
245                 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
246 
247         if (sis & INT_TXFIFO_RESYNC)
248                 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
249 
250         if (sis & INT_CNEW)
251                 dev_dbg(&pdev->dev, "isr: cstatus new\n");
252 
253         if (sis & INT_VAL_NOGOOD)
254                 dev_dbg(&pdev->dev, "isr: validity flag no good\n");
255 
256         if (sis & INT_SYM_ERR)
257                 spdif_irq_sym_error(spdif_priv);
258 
259         if (sis & INT_BIT_ERR)
260                 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
261 
262         if (sis & INT_URX_FUL)
263                 spdif_irq_uqrx_full(spdif_priv, 'U');
264 
265         if (sis & INT_URX_OV)
266                 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
267 
268         if (sis & INT_QRX_FUL)
269                 spdif_irq_uqrx_full(spdif_priv, 'Q');
270 
271         if (sis & INT_QRX_OV)
272                 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
273 
274         if (sis & INT_UQ_SYNC)
275                 spdif_irq_uq_sync(spdif_priv);
276 
277         if (sis & INT_UQ_ERR)
278                 spdif_irq_uq_err(spdif_priv);
279 
280         if (sis & INT_RXFIFO_UNOV)
281                 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
282 
283         if (sis & INT_RXFIFO_RESYNC)
284                 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
285 
286         if (sis & INT_LOSS_LOCK)
287                 spdif_irq_dpll_lock(spdif_priv);
288 
289         /* FIXME: Write Tx FIFO to clear TxEm */
290         if (sis & INT_TX_EM)
291                 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
292 
293         /* FIXME: Read Rx FIFO to clear RxFIFOFul */
294         if (sis & INT_RXFIFO_FUL)
295                 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
296 
297         return IRQ_HANDLED;
298 }
299 
300 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
301 {
302         struct regmap *regmap = spdif_priv->regmap;
303         u32 val, cycle = 1000;
304 
305         regcache_cache_bypass(regmap, true);
306 
307         regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
308 
309         /*
310          * RESET bit would be cleared after finishing its reset procedure,
311          * which typically lasts 8 cycles. 1000 cycles will keep it safe.
312          */
313         do {
314                 regmap_read(regmap, REG_SPDIF_SCR, &val);
315         } while ((val & SCR_SOFT_RESET) && cycle--);
316 
317         regcache_cache_bypass(regmap, false);
318         regcache_mark_dirty(regmap);
319         regcache_sync(regmap);
320 
321         if (cycle)
322                 return 0;
323         else
324                 return -EBUSY;
325 }
326 
327 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
328                                 u8 mask, u8 cstatus)
329 {
330         ctrl->ch_status[3] &= ~mask;
331         ctrl->ch_status[3] |= cstatus & mask;
332 }
333 
334 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
335 {
336         struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
337         struct regmap *regmap = spdif_priv->regmap;
338         struct platform_device *pdev = spdif_priv->pdev;
339         u32 ch_status;
340 
341         ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
342                     (bitrev8(ctrl->ch_status[1]) << 8) |
343                     bitrev8(ctrl->ch_status[2]);
344         regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
345 
346         dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
347 
348         ch_status = bitrev8(ctrl->ch_status[3]) << 16;
349         regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
350 
351         dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
352 }
353 
354 /* Set SPDIF PhaseConfig register for rx clock */
355 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
356                                 enum spdif_gainsel gainsel, int dpll_locked)
357 {
358         struct regmap *regmap = spdif_priv->regmap;
359         u8 clksrc = spdif_priv->rxclk_src;
360 
361         if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
362                 return -EINVAL;
363 
364         regmap_update_bits(regmap, REG_SPDIF_SRPC,
365                         SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
366                         SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
367 
368         return 0;
369 }
370 
371 static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
372                                 int sample_rate)
373 {
374         struct snd_soc_pcm_runtime *rtd = substream->private_data;
375         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
376         struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
377         struct regmap *regmap = spdif_priv->regmap;
378         struct platform_device *pdev = spdif_priv->pdev;
379         unsigned long csfs = 0;
380         u32 stc, mask, rate;
381         u8 clk, txclk_df, sysclk_df;
382         int ret;
383 
384         switch (sample_rate) {
385         case 32000:
386                 rate = SPDIF_TXRATE_32000;
387                 csfs = IEC958_AES3_CON_FS_32000;
388                 break;
389         case 44100:
390                 rate = SPDIF_TXRATE_44100;
391                 csfs = IEC958_AES3_CON_FS_44100;
392                 break;
393         case 48000:
394                 rate = SPDIF_TXRATE_48000;
395                 csfs = IEC958_AES3_CON_FS_48000;
396                 break;
397         case 96000:
398                 rate = SPDIF_TXRATE_96000;
399                 csfs = IEC958_AES3_CON_FS_96000;
400                 break;
401         case 192000:
402                 rate = SPDIF_TXRATE_192000;
403                 csfs = IEC958_AES3_CON_FS_192000;
404                 break;
405         default:
406                 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
407                 return -EINVAL;
408         }
409 
410         clk = spdif_priv->txclk_src[rate];
411         if (clk >= STC_TXCLK_SRC_MAX) {
412                 dev_err(&pdev->dev, "tx clock source is out of range\n");
413                 return -EINVAL;
414         }
415 
416         txclk_df = spdif_priv->txclk_df[rate];
417         if (txclk_df == 0) {
418                 dev_err(&pdev->dev, "the txclk_df can't be zero\n");
419                 return -EINVAL;
420         }
421 
422         sysclk_df = spdif_priv->sysclk_df[rate];
423 
424         /* Don't mess up the clocks from other modules */
425         if (clk != STC_TXCLK_SPDIF_ROOT)
426                 goto clk_set_bypass;
427 
428         /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
429         ret = clk_set_rate(spdif_priv->txclk[rate],
430                            64 * sample_rate * txclk_df);
431         if (ret) {
432                 dev_err(&pdev->dev, "failed to set tx clock rate\n");
433                 return ret;
434         }
435 
436 clk_set_bypass:
437         dev_dbg(&pdev->dev, "expected clock rate = %d\n",
438                         (64 * sample_rate * txclk_df * sysclk_df));
439         dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
440                         clk_get_rate(spdif_priv->txclk[rate]));
441 
442         /* set fs field in consumer channel status */
443         spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
444 
445         /* select clock source and divisor */
446         stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
447               STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
448         mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
449                STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
450         regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
451 
452         dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
453                         spdif_priv->txrate[rate], sample_rate);
454 
455         return 0;
456 }
457 
458 static int fsl_spdif_startup(struct snd_pcm_substream *substream,
459                              struct snd_soc_dai *cpu_dai)
460 {
461         struct snd_soc_pcm_runtime *rtd = substream->private_data;
462         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
463         struct platform_device *pdev = spdif_priv->pdev;
464         struct regmap *regmap = spdif_priv->regmap;
465         u32 scr, mask;
466         int i;
467         int ret;
468 
469         /* Reset module and interrupts only for first initialization */
470         if (!cpu_dai->active) {
471                 ret = clk_prepare_enable(spdif_priv->coreclk);
472                 if (ret) {
473                         dev_err(&pdev->dev, "failed to enable core clock\n");
474                         return ret;
475                 }
476 
477                 ret = spdif_softreset(spdif_priv);
478                 if (ret) {
479                         dev_err(&pdev->dev, "failed to soft reset\n");
480                         goto err;
481                 }
482 
483                 /* Disable all the interrupts */
484                 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
485         }
486 
487         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
488                 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
489                         SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
490                         SCR_TXFIFO_FSEL_IF8;
491                 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
492                         SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
493                         SCR_TXFIFO_FSEL_MASK;
494                 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
495                         ret = clk_prepare_enable(spdif_priv->txclk[i]);
496                         if (ret)
497                                 goto disable_txclk;
498                 }
499         } else {
500                 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
501                 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
502                         SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
503                 ret = clk_prepare_enable(spdif_priv->rxclk);
504                 if (ret)
505                         goto err;
506         }
507         regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
508 
509         /* Power up SPDIF module */
510         regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
511 
512         return 0;
513 
514 disable_txclk:
515         for (i--; i >= 0; i--)
516                 clk_disable_unprepare(spdif_priv->txclk[i]);
517 err:
518         clk_disable_unprepare(spdif_priv->coreclk);
519 
520         return ret;
521 }
522 
523 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
524                                 struct snd_soc_dai *cpu_dai)
525 {
526         struct snd_soc_pcm_runtime *rtd = substream->private_data;
527         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
528         struct regmap *regmap = spdif_priv->regmap;
529         u32 scr, mask, i;
530 
531         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
532                 scr = 0;
533                 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
534                         SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
535                         SCR_TXFIFO_FSEL_MASK;
536                 for (i = 0; i < SPDIF_TXRATE_MAX; i++)
537                         clk_disable_unprepare(spdif_priv->txclk[i]);
538         } else {
539                 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
540                 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
541                         SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
542                 clk_disable_unprepare(spdif_priv->rxclk);
543         }
544         regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
545 
546         /* Power down SPDIF module only if tx&rx are both inactive */
547         if (!cpu_dai->active) {
548                 spdif_intr_status_clear(spdif_priv);
549                 regmap_update_bits(regmap, REG_SPDIF_SCR,
550                                 SCR_LOW_POWER, SCR_LOW_POWER);
551                 clk_disable_unprepare(spdif_priv->coreclk);
552         }
553 }
554 
555 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
556                                 struct snd_pcm_hw_params *params,
557                                 struct snd_soc_dai *dai)
558 {
559         struct snd_soc_pcm_runtime *rtd = substream->private_data;
560         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
561         struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
562         struct platform_device *pdev = spdif_priv->pdev;
563         u32 sample_rate = params_rate(params);
564         int ret = 0;
565 
566         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
567                 ret  = spdif_set_sample_rate(substream, sample_rate);
568                 if (ret) {
569                         dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
570                                         __func__, sample_rate);
571                         return ret;
572                 }
573                 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
574                                   IEC958_AES3_CON_CLOCK_1000PPM);
575                 spdif_write_channel_status(spdif_priv);
576         } else {
577                 /* Setup rx clock source */
578                 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
579         }
580 
581         return ret;
582 }
583 
584 static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
585                                 int cmd, struct snd_soc_dai *dai)
586 {
587         struct snd_soc_pcm_runtime *rtd = substream->private_data;
588         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
589         struct regmap *regmap = spdif_priv->regmap;
590         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
591         u32 intr = SIE_INTR_FOR(tx);
592         u32 dmaen = SCR_DMA_xX_EN(tx);
593 
594         switch (cmd) {
595         case SNDRV_PCM_TRIGGER_START:
596         case SNDRV_PCM_TRIGGER_RESUME:
597         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
598                 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
599                 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
600                 break;
601         case SNDRV_PCM_TRIGGER_STOP:
602         case SNDRV_PCM_TRIGGER_SUSPEND:
603         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
604                 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
605                 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
606                 break;
607         default:
608                 return -EINVAL;
609         }
610 
611         return 0;
612 }
613 
614 static struct snd_soc_dai_ops fsl_spdif_dai_ops = {
615         .startup = fsl_spdif_startup,
616         .hw_params = fsl_spdif_hw_params,
617         .trigger = fsl_spdif_trigger,
618         .shutdown = fsl_spdif_shutdown,
619 };
620 
621 
622 /*
623  * FSL SPDIF IEC958 controller(mixer) functions
624  *
625  *      Channel status get/put control
626  *      User bit value get/put control
627  *      Valid bit value get control
628  *      DPLL lock status get control
629  *      User bit sync mode selection control
630  */
631 
632 static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
633                                 struct snd_ctl_elem_info *uinfo)
634 {
635         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
636         uinfo->count = 1;
637 
638         return 0;
639 }
640 
641 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
642                                 struct snd_ctl_elem_value *uvalue)
643 {
644         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
645         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
646         struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
647 
648         uvalue->value.iec958.status[0] = ctrl->ch_status[0];
649         uvalue->value.iec958.status[1] = ctrl->ch_status[1];
650         uvalue->value.iec958.status[2] = ctrl->ch_status[2];
651         uvalue->value.iec958.status[3] = ctrl->ch_status[3];
652 
653         return 0;
654 }
655 
656 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
657                                 struct snd_ctl_elem_value *uvalue)
658 {
659         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
660         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
661         struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
662 
663         ctrl->ch_status[0] = uvalue->value.iec958.status[0];
664         ctrl->ch_status[1] = uvalue->value.iec958.status[1];
665         ctrl->ch_status[2] = uvalue->value.iec958.status[2];
666         ctrl->ch_status[3] = uvalue->value.iec958.status[3];
667 
668         spdif_write_channel_status(spdif_priv);
669 
670         return 0;
671 }
672 
673 /* Get channel status from SPDIF_RX_CCHAN register */
674 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
675                                 struct snd_ctl_elem_value *ucontrol)
676 {
677         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
678         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
679         struct regmap *regmap = spdif_priv->regmap;
680         u32 cstatus, val;
681 
682         regmap_read(regmap, REG_SPDIF_SIS, &val);
683         if (!(val & INT_CNEW))
684                 return -EAGAIN;
685 
686         regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
687         ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
688         ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
689         ucontrol->value.iec958.status[2] = cstatus & 0xFF;
690 
691         regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
692         ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
693         ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
694         ucontrol->value.iec958.status[5] = cstatus & 0xFF;
695 
696         /* Clear intr */
697         regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
698 
699         return 0;
700 }
701 
702 /*
703  * Get User bits (subcode) from chip value which readed out
704  * in UChannel register.
705  */
706 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
707                                 struct snd_ctl_elem_value *ucontrol)
708 {
709         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
710         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
711         struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
712         unsigned long flags;
713         int ret = -EAGAIN;
714 
715         spin_lock_irqsave(&ctrl->ctl_lock, flags);
716         if (ctrl->ready_buf) {
717                 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
718                 memcpy(&ucontrol->value.iec958.subcode[0],
719                                 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
720                 ret = 0;
721         }
722         spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
723 
724         return ret;
725 }
726 
727 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
728 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
729                                 struct snd_ctl_elem_info *uinfo)
730 {
731         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
732         uinfo->count = SPDIF_QSUB_SIZE;
733 
734         return 0;
735 }
736 
737 /* Get Q subcode from chip value which readed out in QChannel register */
738 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
739                                 struct snd_ctl_elem_value *ucontrol)
740 {
741         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
742         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
743         struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
744         unsigned long flags;
745         int ret = -EAGAIN;
746 
747         spin_lock_irqsave(&ctrl->ctl_lock, flags);
748         if (ctrl->ready_buf) {
749                 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
750                 memcpy(&ucontrol->value.bytes.data[0],
751                                 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
752                 ret = 0;
753         }
754         spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
755 
756         return ret;
757 }
758 
759 /* Valid bit information */
760 static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
761                                 struct snd_ctl_elem_info *uinfo)
762 {
763         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
764         uinfo->count = 1;
765         uinfo->value.integer.min = 0;
766         uinfo->value.integer.max = 1;
767 
768         return 0;
769 }
770 
771 /* Get valid good bit from interrupt status register */
772 static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
773                                 struct snd_ctl_elem_value *ucontrol)
774 {
775         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
776         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
777         struct regmap *regmap = spdif_priv->regmap;
778         u32 val;
779 
780         regmap_read(regmap, REG_SPDIF_SIS, &val);
781         ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
782         regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
783 
784         return 0;
785 }
786 
787 /* DPLL lock information */
788 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
789                                 struct snd_ctl_elem_info *uinfo)
790 {
791         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
792         uinfo->count = 1;
793         uinfo->value.integer.min = 16000;
794         uinfo->value.integer.max = 96000;
795 
796         return 0;
797 }
798 
799 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
800         24, 16, 12, 8, 6, 4, 3,
801 };
802 
803 /* Get RX data clock rate given the SPDIF bus_clk */
804 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
805                                 enum spdif_gainsel gainsel)
806 {
807         struct regmap *regmap = spdif_priv->regmap;
808         struct platform_device *pdev = spdif_priv->pdev;
809         u64 tmpval64, busclk_freq = 0;
810         u32 freqmeas, phaseconf;
811         u8 clksrc;
812 
813         regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
814         regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
815 
816         clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
817 
818         /* Get bus clock from system */
819         if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
820                 busclk_freq = clk_get_rate(spdif_priv->sysclk);
821 
822         /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
823         tmpval64 = (u64) busclk_freq * freqmeas;
824         do_div(tmpval64, gainsel_multi[gainsel] * 1024);
825         do_div(tmpval64, 128 * 1024);
826 
827         dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
828         dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
829         dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
830 
831         return (int)tmpval64;
832 }
833 
834 /*
835  * Get DPLL lock or not info from stable interrupt status register.
836  * User application must use this control to get locked,
837  * then can do next PCM operation
838  */
839 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
840                                 struct snd_ctl_elem_value *ucontrol)
841 {
842         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
843         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
844         int rate = 0;
845 
846         if (spdif_priv->dpll_locked)
847                 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
848 
849         ucontrol->value.integer.value[0] = rate;
850 
851         return 0;
852 }
853 
854 /* User bit sync mode info */
855 static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
856                                 struct snd_ctl_elem_info *uinfo)
857 {
858         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
859         uinfo->count = 1;
860         uinfo->value.integer.min = 0;
861         uinfo->value.integer.max = 1;
862 
863         return 0;
864 }
865 
866 /*
867  * User bit sync mode:
868  * 1 CD User channel subcode
869  * 0 Non-CD data
870  */
871 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
872                                struct snd_ctl_elem_value *ucontrol)
873 {
874         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
875         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
876         struct regmap *regmap = spdif_priv->regmap;
877         u32 val;
878 
879         regmap_read(regmap, REG_SPDIF_SRCD, &val);
880         ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
881 
882         return 0;
883 }
884 
885 /*
886  * User bit sync mode:
887  * 1 CD User channel subcode
888  * 0 Non-CD data
889  */
890 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
891                                 struct snd_ctl_elem_value *ucontrol)
892 {
893         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
894         struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
895         struct regmap *regmap = spdif_priv->regmap;
896         u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
897 
898         regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
899 
900         return 0;
901 }
902 
903 /* FSL SPDIF IEC958 controller defines */
904 static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
905         /* Status cchanel controller */
906         {
907                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
908                 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
909                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
910                         SNDRV_CTL_ELEM_ACCESS_WRITE |
911                         SNDRV_CTL_ELEM_ACCESS_VOLATILE,
912                 .info = fsl_spdif_info,
913                 .get = fsl_spdif_pb_get,
914                 .put = fsl_spdif_pb_put,
915         },
916         {
917                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
918                 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
919                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
920                         SNDRV_CTL_ELEM_ACCESS_VOLATILE,
921                 .info = fsl_spdif_info,
922                 .get = fsl_spdif_capture_get,
923         },
924         /* User bits controller */
925         {
926                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
927                 .name = "IEC958 Subcode Capture Default",
928                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
929                         SNDRV_CTL_ELEM_ACCESS_VOLATILE,
930                 .info = fsl_spdif_info,
931                 .get = fsl_spdif_subcode_get,
932         },
933         {
934                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
935                 .name = "IEC958 Q-subcode Capture Default",
936                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
937                         SNDRV_CTL_ELEM_ACCESS_VOLATILE,
938                 .info = fsl_spdif_qinfo,
939                 .get = fsl_spdif_qget,
940         },
941         /* Valid bit error controller */
942         {
943                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
944                 .name = "IEC958 V-Bit Errors",
945                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
946                         SNDRV_CTL_ELEM_ACCESS_VOLATILE,
947                 .info = fsl_spdif_vbit_info,
948                 .get = fsl_spdif_vbit_get,
949         },
950         /* DPLL lock info get controller */
951         {
952                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
953                 .name = "RX Sample Rate",
954                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
955                         SNDRV_CTL_ELEM_ACCESS_VOLATILE,
956                 .info = fsl_spdif_rxrate_info,
957                 .get = fsl_spdif_rxrate_get,
958         },
959         /* User bit sync mode set/get controller */
960         {
961                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
962                 .name = "IEC958 USyncMode CDText",
963                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
964                         SNDRV_CTL_ELEM_ACCESS_WRITE |
965                         SNDRV_CTL_ELEM_ACCESS_VOLATILE,
966                 .info = fsl_spdif_usync_info,
967                 .get = fsl_spdif_usync_get,
968                 .put = fsl_spdif_usync_put,
969         },
970 };
971 
972 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
973 {
974         struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
975 
976         snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
977                                   &spdif_private->dma_params_rx);
978 
979         snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
980 
981         return 0;
982 }
983 
984 static struct snd_soc_dai_driver fsl_spdif_dai = {
985         .probe = &fsl_spdif_dai_probe,
986         .playback = {
987                 .stream_name = "CPU-Playback",
988                 .channels_min = 2,
989                 .channels_max = 2,
990                 .rates = FSL_SPDIF_RATES_PLAYBACK,
991                 .formats = FSL_SPDIF_FORMATS_PLAYBACK,
992         },
993         .capture = {
994                 .stream_name = "CPU-Capture",
995                 .channels_min = 2,
996                 .channels_max = 2,
997                 .rates = FSL_SPDIF_RATES_CAPTURE,
998                 .formats = FSL_SPDIF_FORMATS_CAPTURE,
999         },
1000         .ops = &fsl_spdif_dai_ops,
1001 };
1002 
1003 static const struct snd_soc_component_driver fsl_spdif_component = {
1004         .name           = "fsl-spdif",
1005 };
1006 
1007 /* FSL SPDIF REGMAP */
1008 static const struct reg_default fsl_spdif_reg_defaults[] = {
1009         {0x0,  0x00000400},
1010         {0x4,  0x00000000},
1011         {0xc,  0x00000000},
1012         {0x34, 0x00000000},
1013         {0x38, 0x00000000},
1014         {0x50, 0x00020f00},
1015 };
1016 
1017 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
1018 {
1019         switch (reg) {
1020         case REG_SPDIF_SCR:
1021         case REG_SPDIF_SRCD:
1022         case REG_SPDIF_SRPC:
1023         case REG_SPDIF_SIE:
1024         case REG_SPDIF_SIS:
1025         case REG_SPDIF_SRL:
1026         case REG_SPDIF_SRR:
1027         case REG_SPDIF_SRCSH:
1028         case REG_SPDIF_SRCSL:
1029         case REG_SPDIF_SRU:
1030         case REG_SPDIF_SRQ:
1031         case REG_SPDIF_STCSCH:
1032         case REG_SPDIF_STCSCL:
1033         case REG_SPDIF_SRFM:
1034         case REG_SPDIF_STC:
1035                 return true;
1036         default:
1037                 return false;
1038         }
1039 }
1040 
1041 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
1042 {
1043         switch (reg) {
1044         case REG_SPDIF_SRPC:
1045         case REG_SPDIF_SIS:
1046         case REG_SPDIF_SRL:
1047         case REG_SPDIF_SRR:
1048         case REG_SPDIF_SRCSH:
1049         case REG_SPDIF_SRCSL:
1050         case REG_SPDIF_SRU:
1051         case REG_SPDIF_SRQ:
1052         case REG_SPDIF_STL:
1053         case REG_SPDIF_STR:
1054         case REG_SPDIF_SRFM:
1055                 return true;
1056         default:
1057                 return false;
1058         }
1059 }
1060 
1061 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
1062 {
1063         switch (reg) {
1064         case REG_SPDIF_SCR:
1065         case REG_SPDIF_SRCD:
1066         case REG_SPDIF_SRPC:
1067         case REG_SPDIF_SIE:
1068         case REG_SPDIF_SIC:
1069         case REG_SPDIF_STL:
1070         case REG_SPDIF_STR:
1071         case REG_SPDIF_STCSCH:
1072         case REG_SPDIF_STCSCL:
1073         case REG_SPDIF_STC:
1074                 return true;
1075         default:
1076                 return false;
1077         }
1078 }
1079 
1080 static const struct regmap_config fsl_spdif_regmap_config = {
1081         .reg_bits = 32,
1082         .reg_stride = 4,
1083         .val_bits = 32,
1084 
1085         .max_register = REG_SPDIF_STC,
1086         .reg_defaults = fsl_spdif_reg_defaults,
1087         .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
1088         .readable_reg = fsl_spdif_readable_reg,
1089         .volatile_reg = fsl_spdif_volatile_reg,
1090         .writeable_reg = fsl_spdif_writeable_reg,
1091         .cache_type = REGCACHE_RBTREE,
1092 };
1093 
1094 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
1095                                 struct clk *clk, u64 savesub,
1096                                 enum spdif_txrate index, bool round)
1097 {
1098         const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1099         bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
1100         u64 rate_ideal, rate_actual, sub;
1101         u32 sysclk_dfmin, sysclk_dfmax;
1102         u32 txclk_df, sysclk_df, arate;
1103 
1104         /* The sysclk has an extra divisor [2, 512] */
1105         sysclk_dfmin = is_sysclk ? 2 : 1;
1106         sysclk_dfmax = is_sysclk ? 512 : 1;
1107 
1108         for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
1109                 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
1110                         rate_ideal = rate[index] * txclk_df * 64;
1111                         if (round)
1112                                 rate_actual = clk_round_rate(clk, rate_ideal);
1113                         else
1114                                 rate_actual = clk_get_rate(clk);
1115 
1116                         arate = rate_actual / 64;
1117                         arate /= txclk_df * sysclk_df;
1118 
1119                         if (arate == rate[index]) {
1120                                 /* We are lucky */
1121                                 savesub = 0;
1122                                 spdif_priv->txclk_df[index] = txclk_df;
1123                                 spdif_priv->sysclk_df[index] = sysclk_df;
1124                                 spdif_priv->txrate[index] = arate;
1125                                 goto out;
1126                         } else if (arate / rate[index] == 1) {
1127                                 /* A little bigger than expect */
1128                                 sub = (u64)(arate - rate[index]) * 100000;
1129                                 do_div(sub, rate[index]);
1130                                 if (sub >= savesub)
1131                                         continue;
1132                                 savesub = sub;
1133                                 spdif_priv->txclk_df[index] = txclk_df;
1134                                 spdif_priv->sysclk_df[index] = sysclk_df;
1135                                 spdif_priv->txrate[index] = arate;
1136                         } else if (rate[index] / arate == 1) {
1137                                 /* A little smaller than expect */
1138                                 sub = (u64)(rate[index] - arate) * 100000;
1139                                 do_div(sub, rate[index]);
1140                                 if (sub >= savesub)
1141                                         continue;
1142                                 savesub = sub;
1143                                 spdif_priv->txclk_df[index] = txclk_df;
1144                                 spdif_priv->sysclk_df[index] = sysclk_df;
1145                                 spdif_priv->txrate[index] = arate;
1146                         }
1147                 }
1148         }
1149 
1150 out:
1151         return savesub;
1152 }
1153 
1154 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
1155                                 enum spdif_txrate index)
1156 {
1157         const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1158         struct platform_device *pdev = spdif_priv->pdev;
1159         struct device *dev = &pdev->dev;
1160         u64 savesub = 100000, ret;
1161         struct clk *clk;
1162         char tmp[16];
1163         int i;
1164 
1165         for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1166                 sprintf(tmp, "rxtx%d", i);
1167                 clk = devm_clk_get(&pdev->dev, tmp);
1168                 if (IS_ERR(clk)) {
1169                         dev_err(dev, "no rxtx%d clock in devicetree\n", i);
1170                         return PTR_ERR(clk);
1171                 }
1172                 if (!clk_get_rate(clk))
1173                         continue;
1174 
1175                 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
1176                                              i == STC_TXCLK_SPDIF_ROOT);
1177                 if (savesub == ret)
1178                         continue;
1179 
1180                 savesub = ret;
1181                 spdif_priv->txclk[index] = clk;
1182                 spdif_priv->txclk_src[index] = i;
1183 
1184                 /* To quick catch a divisor, we allow a 0.1% deviation */
1185                 if (savesub < 100)
1186                         break;
1187         }
1188 
1189         dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
1190                         spdif_priv->txclk_src[index], rate[index]);
1191         dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n",
1192                         spdif_priv->txclk_df[index], rate[index]);
1193         if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk))
1194                 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n",
1195                                 spdif_priv->sysclk_df[index], rate[index]);
1196         dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n",
1197                         rate[index], spdif_priv->txrate[index]);
1198 
1199         return 0;
1200 }
1201 
1202 static int fsl_spdif_probe(struct platform_device *pdev)
1203 {
1204         struct device_node *np = pdev->dev.of_node;
1205         struct fsl_spdif_priv *spdif_priv;
1206         struct spdif_mixer_control *ctrl;
1207         struct resource *res;
1208         void __iomem *regs;
1209         int irq, ret, i;
1210 
1211         if (!np)
1212                 return -ENODEV;
1213 
1214         spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
1215         if (!spdif_priv)
1216                 return -ENOMEM;
1217 
1218         spdif_priv->pdev = pdev;
1219 
1220         /* Initialize this copy of the CPU DAI driver structure */
1221         memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
1222         spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
1223 
1224         /* Get the addresses and IRQ */
1225         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1226         regs = devm_ioremap_resource(&pdev->dev, res);
1227         if (IS_ERR(regs))
1228                 return PTR_ERR(regs);
1229 
1230         spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1231                         "core", regs, &fsl_spdif_regmap_config);
1232         if (IS_ERR(spdif_priv->regmap)) {
1233                 dev_err(&pdev->dev, "regmap init failed\n");
1234                 return PTR_ERR(spdif_priv->regmap);
1235         }
1236 
1237         irq = platform_get_irq(pdev, 0);
1238         if (irq < 0) {
1239                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1240                 return irq;
1241         }
1242 
1243         ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
1244                                dev_name(&pdev->dev), spdif_priv);
1245         if (ret) {
1246                 dev_err(&pdev->dev, "could not claim irq %u\n", irq);
1247                 return ret;
1248         }
1249 
1250         /* Get system clock for rx clock rate calculation */
1251         spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
1252         if (IS_ERR(spdif_priv->sysclk)) {
1253                 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
1254                 return PTR_ERR(spdif_priv->sysclk);
1255         }
1256 
1257         /* Get core clock for data register access via DMA */
1258         spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
1259         if (IS_ERR(spdif_priv->coreclk)) {
1260                 dev_err(&pdev->dev, "no core clock in devicetree\n");
1261                 return PTR_ERR(spdif_priv->coreclk);
1262         }
1263 
1264         /* Select clock source for rx/tx clock */
1265         spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
1266         if (IS_ERR(spdif_priv->rxclk)) {
1267                 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
1268                 return PTR_ERR(spdif_priv->rxclk);
1269         }
1270         spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
1271 
1272         for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1273                 ret = fsl_spdif_probe_txclk(spdif_priv, i);
1274                 if (ret)
1275                         return ret;
1276         }
1277 
1278         /* Initial spinlock for control data */
1279         ctrl = &spdif_priv->fsl_spdif_control;
1280         spin_lock_init(&ctrl->ctl_lock);
1281 
1282         /* Init tx channel status default value */
1283         ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
1284                              IEC958_AES0_CON_EMPHASIS_5015;
1285         ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
1286         ctrl->ch_status[2] = 0x00;
1287         ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
1288                              IEC958_AES3_CON_CLOCK_1000PPM;
1289 
1290         spdif_priv->dpll_locked = false;
1291 
1292         spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
1293         spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
1294         spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
1295         spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
1296 
1297         /* Register with ASoC */
1298         dev_set_drvdata(&pdev->dev, spdif_priv);
1299 
1300         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
1301                                               &spdif_priv->cpu_dai_drv, 1);
1302         if (ret) {
1303                 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1304                 return ret;
1305         }
1306 
1307         ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE);
1308         if (ret)
1309                 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
1310 
1311         return ret;
1312 }
1313 
1314 #ifdef CONFIG_PM_SLEEP
1315 static int fsl_spdif_suspend(struct device *dev)
1316 {
1317         struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1318 
1319         regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
1320                         &spdif_priv->regcache_srpc);
1321 
1322         regcache_cache_only(spdif_priv->regmap, true);
1323         regcache_mark_dirty(spdif_priv->regmap);
1324 
1325         return 0;
1326 }
1327 
1328 static int fsl_spdif_resume(struct device *dev)
1329 {
1330         struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1331 
1332         regcache_cache_only(spdif_priv->regmap, false);
1333 
1334         regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
1335                         SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
1336                         spdif_priv->regcache_srpc);
1337 
1338         return regcache_sync(spdif_priv->regmap);
1339 }
1340 #endif /* CONFIG_PM_SLEEP */
1341 
1342 static const struct dev_pm_ops fsl_spdif_pm = {
1343         SET_SYSTEM_SLEEP_PM_OPS(fsl_spdif_suspend, fsl_spdif_resume)
1344 };
1345 
1346 static const struct of_device_id fsl_spdif_dt_ids[] = {
1347         { .compatible = "fsl,imx35-spdif", },
1348         { .compatible = "fsl,vf610-spdif", },
1349         {}
1350 };
1351 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
1352 
1353 static struct platform_driver fsl_spdif_driver = {
1354         .driver = {
1355                 .name = "fsl-spdif-dai",
1356                 .of_match_table = fsl_spdif_dt_ids,
1357                 .pm = &fsl_spdif_pm,
1358         },
1359         .probe = fsl_spdif_probe,
1360 };
1361 
1362 module_platform_driver(fsl_spdif_driver);
1363 
1364 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1365 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1366 MODULE_LICENSE("GPL v2");
1367 MODULE_ALIAS("platform:fsl-spdif-dai");
1368 

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