Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/sound/soc/fsl/fsl_sai.c

  1 /*
  2  * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
  3  *
  4  * Copyright 2012-2013 Freescale Semiconductor, Inc.
  5  *
  6  * This program is free software, you can redistribute it and/or modify it
  7  * under the terms of the GNU General Public License as published by the
  8  * Free Software Foundation, either version 2 of the License, or(at your
  9  * option) any later version.
 10  *
 11  */
 12 
 13 #include <linux/clk.h>
 14 #include <linux/delay.h>
 15 #include <linux/dmaengine.h>
 16 #include <linux/module.h>
 17 #include <linux/of_address.h>
 18 #include <linux/regmap.h>
 19 #include <linux/slab.h>
 20 #include <sound/core.h>
 21 #include <sound/dmaengine_pcm.h>
 22 #include <sound/pcm_params.h>
 23 
 24 #include "fsl_sai.h"
 25 #include "imx-pcm.h"
 26 
 27 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
 28                        FSL_SAI_CSR_FEIE)
 29 
 30 static irqreturn_t fsl_sai_isr(int irq, void *devid)
 31 {
 32         struct fsl_sai *sai = (struct fsl_sai *)devid;
 33         struct device *dev = &sai->pdev->dev;
 34         u32 flags, xcsr, mask;
 35         bool irq_none = true;
 36 
 37         /*
 38          * Both IRQ status bits and IRQ mask bits are in the xCSR but
 39          * different shifts. And we here create a mask only for those
 40          * IRQs that we activated.
 41          */
 42         mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
 43 
 44         /* Tx IRQ */
 45         regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
 46         flags = xcsr & mask;
 47 
 48         if (flags)
 49                 irq_none = false;
 50         else
 51                 goto irq_rx;
 52 
 53         if (flags & FSL_SAI_CSR_WSF)
 54                 dev_dbg(dev, "isr: Start of Tx word detected\n");
 55 
 56         if (flags & FSL_SAI_CSR_SEF)
 57                 dev_warn(dev, "isr: Tx Frame sync error detected\n");
 58 
 59         if (flags & FSL_SAI_CSR_FEF) {
 60                 dev_warn(dev, "isr: Transmit underrun detected\n");
 61                 /* FIFO reset for safety */
 62                 xcsr |= FSL_SAI_CSR_FR;
 63         }
 64 
 65         if (flags & FSL_SAI_CSR_FWF)
 66                 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
 67 
 68         if (flags & FSL_SAI_CSR_FRF)
 69                 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
 70 
 71         flags &= FSL_SAI_CSR_xF_W_MASK;
 72         xcsr &= ~FSL_SAI_CSR_xF_MASK;
 73 
 74         if (flags)
 75                 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
 76 
 77 irq_rx:
 78         /* Rx IRQ */
 79         regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
 80         flags = xcsr & mask;
 81 
 82         if (flags)
 83                 irq_none = false;
 84         else
 85                 goto out;
 86 
 87         if (flags & FSL_SAI_CSR_WSF)
 88                 dev_dbg(dev, "isr: Start of Rx word detected\n");
 89 
 90         if (flags & FSL_SAI_CSR_SEF)
 91                 dev_warn(dev, "isr: Rx Frame sync error detected\n");
 92 
 93         if (flags & FSL_SAI_CSR_FEF) {
 94                 dev_warn(dev, "isr: Receive overflow detected\n");
 95                 /* FIFO reset for safety */
 96                 xcsr |= FSL_SAI_CSR_FR;
 97         }
 98 
 99         if (flags & FSL_SAI_CSR_FWF)
100                 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
101 
102         if (flags & FSL_SAI_CSR_FRF)
103                 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
104 
105         flags &= FSL_SAI_CSR_xF_W_MASK;
106         xcsr &= ~FSL_SAI_CSR_xF_MASK;
107 
108         if (flags)
109                 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
110 
111 out:
112         if (irq_none)
113                 return IRQ_NONE;
114         else
115                 return IRQ_HANDLED;
116 }
117 
118 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
119                 int clk_id, unsigned int freq, int fsl_dir)
120 {
121         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
122         bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
123         u32 val_cr2 = 0;
124 
125         switch (clk_id) {
126         case FSL_SAI_CLK_BUS:
127                 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
128                 break;
129         case FSL_SAI_CLK_MAST1:
130                 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
131                 break;
132         case FSL_SAI_CLK_MAST2:
133                 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
134                 break;
135         case FSL_SAI_CLK_MAST3:
136                 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
137                 break;
138         default:
139                 return -EINVAL;
140         }
141 
142         regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
143                            FSL_SAI_CR2_MSEL_MASK, val_cr2);
144 
145         return 0;
146 }
147 
148 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
149                 int clk_id, unsigned int freq, int dir)
150 {
151         int ret;
152 
153         if (dir == SND_SOC_CLOCK_IN)
154                 return 0;
155 
156         ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
157                                         FSL_FMT_TRANSMITTER);
158         if (ret) {
159                 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
160                 return ret;
161         }
162 
163         ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
164                                         FSL_FMT_RECEIVER);
165         if (ret)
166                 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
167 
168         return ret;
169 }
170 
171 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
172                                 unsigned int fmt, int fsl_dir)
173 {
174         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
175         bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
176         u32 val_cr2 = 0, val_cr4 = 0;
177 
178         if (!sai->big_endian_data)
179                 val_cr4 |= FSL_SAI_CR4_MF;
180 
181         /* DAI mode */
182         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
183         case SND_SOC_DAIFMT_I2S:
184                 /*
185                  * Frame low, 1clk before data, one word length for frame sync,
186                  * frame sync starts one serial clock cycle earlier,
187                  * that is, together with the last bit of the previous
188                  * data word.
189                  */
190                 val_cr2 |= FSL_SAI_CR2_BCP;
191                 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
192                 break;
193         case SND_SOC_DAIFMT_LEFT_J:
194                 /*
195                  * Frame high, one word length for frame sync,
196                  * frame sync asserts with the first bit of the frame.
197                  */
198                 val_cr2 |= FSL_SAI_CR2_BCP;
199                 break;
200         case SND_SOC_DAIFMT_DSP_A:
201                 /*
202                  * Frame high, 1clk before data, one bit for frame sync,
203                  * frame sync starts one serial clock cycle earlier,
204                  * that is, together with the last bit of the previous
205                  * data word.
206                  */
207                 val_cr2 |= FSL_SAI_CR2_BCP;
208                 val_cr4 |= FSL_SAI_CR4_FSE;
209                 sai->is_dsp_mode = true;
210                 break;
211         case SND_SOC_DAIFMT_DSP_B:
212                 /*
213                  * Frame high, one bit for frame sync,
214                  * frame sync asserts with the first bit of the frame.
215                  */
216                 val_cr2 |= FSL_SAI_CR2_BCP;
217                 sai->is_dsp_mode = true;
218                 break;
219         case SND_SOC_DAIFMT_RIGHT_J:
220                 /* To be done */
221         default:
222                 return -EINVAL;
223         }
224 
225         /* DAI clock inversion */
226         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
227         case SND_SOC_DAIFMT_IB_IF:
228                 /* Invert both clocks */
229                 val_cr2 ^= FSL_SAI_CR2_BCP;
230                 val_cr4 ^= FSL_SAI_CR4_FSP;
231                 break;
232         case SND_SOC_DAIFMT_IB_NF:
233                 /* Invert bit clock */
234                 val_cr2 ^= FSL_SAI_CR2_BCP;
235                 break;
236         case SND_SOC_DAIFMT_NB_IF:
237                 /* Invert frame clock */
238                 val_cr4 ^= FSL_SAI_CR4_FSP;
239                 break;
240         case SND_SOC_DAIFMT_NB_NF:
241                 /* Nothing to do for both normal cases */
242                 break;
243         default:
244                 return -EINVAL;
245         }
246 
247         /* DAI clock master masks */
248         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
249         case SND_SOC_DAIFMT_CBS_CFS:
250                 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
251                 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
252                 break;
253         case SND_SOC_DAIFMT_CBM_CFM:
254                 break;
255         case SND_SOC_DAIFMT_CBS_CFM:
256                 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
257                 break;
258         case SND_SOC_DAIFMT_CBM_CFS:
259                 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
260                 break;
261         default:
262                 return -EINVAL;
263         }
264 
265         regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
266                            FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
267         regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
268                            FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
269                            FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
270 
271         return 0;
272 }
273 
274 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
275 {
276         int ret;
277 
278         ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
279         if (ret) {
280                 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
281                 return ret;
282         }
283 
284         ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
285         if (ret)
286                 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
287 
288         return ret;
289 }
290 
291 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
292                 struct snd_pcm_hw_params *params,
293                 struct snd_soc_dai *cpu_dai)
294 {
295         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
296         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
297         unsigned int channels = params_channels(params);
298         u32 word_width = snd_pcm_format_width(params_format(params));
299         u32 val_cr4 = 0, val_cr5 = 0;
300 
301         if (!sai->is_dsp_mode)
302                 val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
303 
304         val_cr5 |= FSL_SAI_CR5_WNW(word_width);
305         val_cr5 |= FSL_SAI_CR5_W0W(word_width);
306 
307         if (sai->big_endian_data)
308                 val_cr5 |= FSL_SAI_CR5_FBT(0);
309         else
310                 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
311 
312         val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
313 
314         regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
315                            FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
316                            val_cr4);
317         regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
318                            FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
319                            FSL_SAI_CR5_FBT_MASK, val_cr5);
320         regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
321 
322         return 0;
323 }
324 
325 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
326                 struct snd_soc_dai *cpu_dai)
327 {
328         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
329         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
330         u32 tcsr, rcsr;
331 
332         /*
333          * The transmitter bit clock and frame sync are to be
334          * used by both the transmitter and receiver.
335          */
336         regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
337                            ~FSL_SAI_CR2_SYNC);
338         regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
339                            FSL_SAI_CR2_SYNC);
340 
341         regmap_read(sai->regmap, FSL_SAI_TCSR, &tcsr);
342         regmap_read(sai->regmap, FSL_SAI_RCSR, &rcsr);
343 
344         /*
345          * It is recommended that the transmitter is the last enabled
346          * and the first disabled.
347          */
348         switch (cmd) {
349         case SNDRV_PCM_TRIGGER_START:
350         case SNDRV_PCM_TRIGGER_RESUME:
351         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
352                 if (!(tcsr & FSL_SAI_CSR_FRDE || rcsr & FSL_SAI_CSR_FRDE)) {
353                         regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
354                                            FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
355                         regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
356                                            FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
357                 }
358 
359                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
360                                    FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
361                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
362                                    FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
363                 break;
364         case SNDRV_PCM_TRIGGER_STOP:
365         case SNDRV_PCM_TRIGGER_SUSPEND:
366         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
367                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
368                                    FSL_SAI_CSR_FRDE, 0);
369                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
370                                    FSL_SAI_CSR_xIE_MASK, 0);
371 
372                 /* Check if the opposite FRDE is also disabled */
373                 if (!(tx ? rcsr & FSL_SAI_CSR_FRDE : tcsr & FSL_SAI_CSR_FRDE)) {
374                         regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
375                                            FSL_SAI_CSR_TERE, 0);
376                         regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
377                                            FSL_SAI_CSR_TERE, 0);
378                 }
379                 break;
380         default:
381                 return -EINVAL;
382         }
383 
384         return 0;
385 }
386 
387 static int fsl_sai_startup(struct snd_pcm_substream *substream,
388                 struct snd_soc_dai *cpu_dai)
389 {
390         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
391         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
392         struct device *dev = &sai->pdev->dev;
393         int ret;
394 
395         ret = clk_prepare_enable(sai->bus_clk);
396         if (ret) {
397                 dev_err(dev, "failed to enable bus clock: %d\n", ret);
398                 return ret;
399         }
400 
401         regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
402                            FSL_SAI_CR3_TRCE);
403 
404         return 0;
405 }
406 
407 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
408                 struct snd_soc_dai *cpu_dai)
409 {
410         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
411         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
412 
413         regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
414 
415         clk_disable_unprepare(sai->bus_clk);
416 }
417 
418 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
419         .set_sysclk     = fsl_sai_set_dai_sysclk,
420         .set_fmt        = fsl_sai_set_dai_fmt,
421         .hw_params      = fsl_sai_hw_params,
422         .trigger        = fsl_sai_trigger,
423         .startup        = fsl_sai_startup,
424         .shutdown       = fsl_sai_shutdown,
425 };
426 
427 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
428 {
429         struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
430 
431         regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 0xffffffff, 0x0);
432         regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 0xffffffff, 0x0);
433         regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
434                            FSL_SAI_MAXBURST_TX * 2);
435         regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
436                            FSL_SAI_MAXBURST_RX - 1);
437 
438         snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
439                                 &sai->dma_params_rx);
440 
441         snd_soc_dai_set_drvdata(cpu_dai, sai);
442 
443         return 0;
444 }
445 
446 static struct snd_soc_dai_driver fsl_sai_dai = {
447         .probe = fsl_sai_dai_probe,
448         .playback = {
449                 .channels_min = 1,
450                 .channels_max = 2,
451                 .rates = SNDRV_PCM_RATE_8000_96000,
452                 .formats = FSL_SAI_FORMATS,
453         },
454         .capture = {
455                 .channels_min = 1,
456                 .channels_max = 2,
457                 .rates = SNDRV_PCM_RATE_8000_96000,
458                 .formats = FSL_SAI_FORMATS,
459         },
460         .ops = &fsl_sai_pcm_dai_ops,
461 };
462 
463 static const struct snd_soc_component_driver fsl_component = {
464         .name           = "fsl-sai",
465 };
466 
467 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
468 {
469         switch (reg) {
470         case FSL_SAI_TCSR:
471         case FSL_SAI_TCR1:
472         case FSL_SAI_TCR2:
473         case FSL_SAI_TCR3:
474         case FSL_SAI_TCR4:
475         case FSL_SAI_TCR5:
476         case FSL_SAI_TFR:
477         case FSL_SAI_TMR:
478         case FSL_SAI_RCSR:
479         case FSL_SAI_RCR1:
480         case FSL_SAI_RCR2:
481         case FSL_SAI_RCR3:
482         case FSL_SAI_RCR4:
483         case FSL_SAI_RCR5:
484         case FSL_SAI_RDR:
485         case FSL_SAI_RFR:
486         case FSL_SAI_RMR:
487                 return true;
488         default:
489                 return false;
490         }
491 }
492 
493 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
494 {
495         switch (reg) {
496         case FSL_SAI_TFR:
497         case FSL_SAI_RFR:
498         case FSL_SAI_TDR:
499         case FSL_SAI_RDR:
500                 return true;
501         default:
502                 return false;
503         }
504 
505 }
506 
507 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
508 {
509         switch (reg) {
510         case FSL_SAI_TCSR:
511         case FSL_SAI_TCR1:
512         case FSL_SAI_TCR2:
513         case FSL_SAI_TCR3:
514         case FSL_SAI_TCR4:
515         case FSL_SAI_TCR5:
516         case FSL_SAI_TDR:
517         case FSL_SAI_TMR:
518         case FSL_SAI_RCSR:
519         case FSL_SAI_RCR1:
520         case FSL_SAI_RCR2:
521         case FSL_SAI_RCR3:
522         case FSL_SAI_RCR4:
523         case FSL_SAI_RCR5:
524         case FSL_SAI_RMR:
525                 return true;
526         default:
527                 return false;
528         }
529 }
530 
531 static struct regmap_config fsl_sai_regmap_config = {
532         .reg_bits = 32,
533         .reg_stride = 4,
534         .val_bits = 32,
535 
536         .max_register = FSL_SAI_RMR,
537         .readable_reg = fsl_sai_readable_reg,
538         .volatile_reg = fsl_sai_volatile_reg,
539         .writeable_reg = fsl_sai_writeable_reg,
540 };
541 
542 static int fsl_sai_probe(struct platform_device *pdev)
543 {
544         struct device_node *np = pdev->dev.of_node;
545         struct fsl_sai *sai;
546         struct resource *res;
547         void __iomem *base;
548         char tmp[8];
549         int irq, ret, i;
550 
551         sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
552         if (!sai)
553                 return -ENOMEM;
554 
555         sai->pdev = pdev;
556 
557         if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
558                 sai->sai_on_imx = true;
559 
560         sai->big_endian_regs = of_property_read_bool(np, "big-endian-regs");
561         if (sai->big_endian_regs)
562                 fsl_sai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
563 
564         sai->big_endian_data = of_property_read_bool(np, "big-endian-data");
565 
566         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
567         base = devm_ioremap_resource(&pdev->dev, res);
568         if (IS_ERR(base))
569                 return PTR_ERR(base);
570 
571         sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
572                         "bus", base, &fsl_sai_regmap_config);
573 
574         /* Compatible with old DTB cases */
575         if (IS_ERR(sai->regmap))
576                 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
577                                 "sai", base, &fsl_sai_regmap_config);
578         if (IS_ERR(sai->regmap)) {
579                 dev_err(&pdev->dev, "regmap init failed\n");
580                 return PTR_ERR(sai->regmap);
581         }
582 
583         /* No error out for old DTB cases but only mark the clock NULL */
584         sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
585         if (IS_ERR(sai->bus_clk)) {
586                 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
587                                 PTR_ERR(sai->bus_clk));
588                 sai->bus_clk = NULL;
589         }
590 
591         for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
592                 sprintf(tmp, "mclk%d", i + 1);
593                 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
594                 if (IS_ERR(sai->mclk_clk[i])) {
595                         dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
596                                         i + 1, PTR_ERR(sai->mclk_clk[i]));
597                         sai->mclk_clk[i] = NULL;
598                 }
599         }
600 
601         irq = platform_get_irq(pdev, 0);
602         if (irq < 0) {
603                 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
604                 return irq;
605         }
606 
607         ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
608         if (ret) {
609                 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
610                 return ret;
611         }
612 
613         sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
614         sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
615         sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
616         sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
617 
618         platform_set_drvdata(pdev, sai);
619 
620         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
621                         &fsl_sai_dai, 1);
622         if (ret)
623                 return ret;
624 
625         if (sai->sai_on_imx)
626                 return imx_pcm_dma_init(pdev);
627         else
628                 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
629                                 SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
630 }
631 
632 static const struct of_device_id fsl_sai_ids[] = {
633         { .compatible = "fsl,vf610-sai", },
634         { .compatible = "fsl,imx6sx-sai", },
635         { /* sentinel */ }
636 };
637 
638 static struct platform_driver fsl_sai_driver = {
639         .probe = fsl_sai_probe,
640         .driver = {
641                 .name = "fsl-sai",
642                 .owner = THIS_MODULE,
643                 .of_match_table = fsl_sai_ids,
644         },
645 };
646 module_platform_driver(fsl_sai_driver);
647 
648 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
649 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
650 MODULE_ALIAS("platform:fsl-sai");
651 MODULE_LICENSE("GPL");
652 

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