Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/sound/soc/fsl/fsl_esai.c

  1 /*
  2  * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
  3  *
  4  * Copyright (C) 2014 Freescale Semiconductor, Inc.
  5  *
  6  * This file is licensed under the terms of the GNU General Public License
  7  * version 2. This program is licensed "as is" without any warranty of any
  8  * kind, whether express or implied.
  9  */
 10 
 11 #include <linux/clk.h>
 12 #include <linux/dmaengine.h>
 13 #include <linux/module.h>
 14 #include <linux/of_irq.h>
 15 #include <linux/of_platform.h>
 16 #include <sound/dmaengine_pcm.h>
 17 #include <sound/pcm_params.h>
 18 
 19 #include "fsl_esai.h"
 20 #include "imx-pcm.h"
 21 
 22 #define FSL_ESAI_RATES          SNDRV_PCM_RATE_8000_192000
 23 #define FSL_ESAI_FORMATS        (SNDRV_PCM_FMTBIT_S8 | \
 24                                 SNDRV_PCM_FMTBIT_S16_LE | \
 25                                 SNDRV_PCM_FMTBIT_S20_3LE | \
 26                                 SNDRV_PCM_FMTBIT_S24_LE)
 27 
 28 /**
 29  * fsl_esai: ESAI private data
 30  *
 31  * @dma_params_rx: DMA parameters for receive channel
 32  * @dma_params_tx: DMA parameters for transmit channel
 33  * @pdev: platform device pointer
 34  * @regmap: regmap handler
 35  * @coreclk: clock source to access register
 36  * @extalclk: esai clock source to derive HCK, SCK and FS
 37  * @fsysclk: system clock source to derive HCK, SCK and FS
 38  * @fifo_depth: depth of tx/rx FIFO
 39  * @slot_width: width of each DAI slot
 40  * @hck_rate: clock rate of desired HCKx clock
 41  * @sck_rate: clock rate of desired SCKx clock
 42  * @hck_dir: the direction of HCKx pads
 43  * @sck_div: if using PSR/PM dividers for SCKx clock
 44  * @slave_mode: if fully using DAI slave mode
 45  * @synchronous: if using tx/rx synchronous mode
 46  * @name: driver name
 47  */
 48 struct fsl_esai {
 49         struct snd_dmaengine_dai_dma_data dma_params_rx;
 50         struct snd_dmaengine_dai_dma_data dma_params_tx;
 51         struct platform_device *pdev;
 52         struct regmap *regmap;
 53         struct clk *coreclk;
 54         struct clk *extalclk;
 55         struct clk *fsysclk;
 56         u32 fifo_depth;
 57         u32 slot_width;
 58         u32 hck_rate[2];
 59         u32 sck_rate[2];
 60         bool hck_dir[2];
 61         bool sck_div[2];
 62         bool slave_mode;
 63         bool synchronous;
 64         char name[32];
 65 };
 66 
 67 static irqreturn_t esai_isr(int irq, void *devid)
 68 {
 69         struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
 70         struct platform_device *pdev = esai_priv->pdev;
 71         u32 esr;
 72 
 73         regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
 74 
 75         if (esr & ESAI_ESR_TINIT_MASK)
 76                 dev_dbg(&pdev->dev, "isr: Transmition Initialized\n");
 77 
 78         if (esr & ESAI_ESR_RFF_MASK)
 79                 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
 80 
 81         if (esr & ESAI_ESR_TFE_MASK)
 82                 dev_warn(&pdev->dev, "isr: Transmition underrun\n");
 83 
 84         if (esr & ESAI_ESR_TLS_MASK)
 85                 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
 86 
 87         if (esr & ESAI_ESR_TDE_MASK)
 88                 dev_dbg(&pdev->dev, "isr: Transmition data exception\n");
 89 
 90         if (esr & ESAI_ESR_TED_MASK)
 91                 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
 92 
 93         if (esr & ESAI_ESR_TD_MASK)
 94                 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
 95 
 96         if (esr & ESAI_ESR_RLS_MASK)
 97                 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
 98 
 99         if (esr & ESAI_ESR_RDE_MASK)
100                 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
101 
102         if (esr & ESAI_ESR_RED_MASK)
103                 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
104 
105         if (esr & ESAI_ESR_RD_MASK)
106                 dev_dbg(&pdev->dev, "isr: Receiving data\n");
107 
108         return IRQ_HANDLED;
109 }
110 
111 /**
112  * This function is used to calculate the divisors of psr, pm, fp and it is
113  * supposed to be called in set_dai_sysclk() and set_bclk().
114  *
115  * @ratio: desired overall ratio for the paticipating dividers
116  * @usefp: for HCK setting, there is no need to set fp divider
117  * @fp: bypass other dividers by setting fp directly if fp != 0
118  * @tx: current setting is for playback or capture
119  */
120 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
121                                 bool usefp, u32 fp)
122 {
123         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
124         u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
125 
126         maxfp = usefp ? 16 : 1;
127 
128         if (usefp && fp)
129                 goto out_fp;
130 
131         if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
132                 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
133                                 2 * 8 * 256 * maxfp);
134                 return -EINVAL;
135         } else if (ratio % 2) {
136                 dev_err(dai->dev, "the raio must be even if using upper divider\n");
137                 return -EINVAL;
138         }
139 
140         ratio /= 2;
141 
142         psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
143 
144         /* Set the max fluctuation -- 0.1% of the max devisor */
145         savesub = (psr ? 1 : 8)  * 256 * maxfp / 1000;
146 
147         /* Find the best value for PM */
148         for (i = 1; i <= 256; i++) {
149                 for (j = 1; j <= maxfp; j++) {
150                         /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
151                         prod = (psr ? 1 : 8) * i * j;
152 
153                         if (prod == ratio)
154                                 sub = 0;
155                         else if (prod / ratio == 1)
156                                 sub = prod - ratio;
157                         else if (ratio / prod == 1)
158                                 sub = ratio - prod;
159                         else
160                                 continue;
161 
162                         /* Calculate the fraction */
163                         sub = sub * 1000 / ratio;
164                         if (sub < savesub) {
165                                 savesub = sub;
166                                 pm = i;
167                                 fp = j;
168                         }
169 
170                         /* We are lucky */
171                         if (savesub == 0)
172                                 goto out;
173                 }
174         }
175 
176         if (pm == 999) {
177                 dev_err(dai->dev, "failed to calculate proper divisors\n");
178                 return -EINVAL;
179         }
180 
181 out:
182         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
183                            ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
184                            psr | ESAI_xCCR_xPM(pm));
185 
186 out_fp:
187         /* Bypass fp if not being required */
188         if (maxfp <= 1)
189                 return 0;
190 
191         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
192                            ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
193 
194         return 0;
195 }
196 
197 /**
198  * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
199  *
200  * @Parameters:
201  * clk_id: The clock source of HCKT/HCKR
202  *        (Input from outside; output from inside, FSYS or EXTAL)
203  * freq: The required clock rate of HCKT/HCKR
204  * dir: The clock direction of HCKT/HCKR
205  *
206  * Note: If the direction is input, we do not care about clk_id.
207  */
208 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
209                                    unsigned int freq, int dir)
210 {
211         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
212         struct clk *clksrc = esai_priv->extalclk;
213         bool tx = clk_id <= ESAI_HCKT_EXTAL;
214         bool in = dir == SND_SOC_CLOCK_IN;
215         u32 ratio, ecr = 0;
216         unsigned long clk_rate;
217         int ret;
218 
219         /* Bypass divider settings if the requirement doesn't change */
220         if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
221                 return 0;
222 
223         /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
224         esai_priv->sck_div[tx] = true;
225 
226         /* Set the direction of HCKT/HCKR pins */
227         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
228                            ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
229 
230         if (in)
231                 goto out;
232 
233         switch (clk_id) {
234         case ESAI_HCKT_FSYS:
235         case ESAI_HCKR_FSYS:
236                 clksrc = esai_priv->fsysclk;
237                 break;
238         case ESAI_HCKT_EXTAL:
239                 ecr |= ESAI_ECR_ETI;
240         case ESAI_HCKR_EXTAL:
241                 ecr |= ESAI_ECR_ERI;
242                 break;
243         default:
244                 return -EINVAL;
245         }
246 
247         if (IS_ERR(clksrc)) {
248                 dev_err(dai->dev, "no assigned %s clock\n",
249                                 clk_id % 2 ? "extal" : "fsys");
250                 return PTR_ERR(clksrc);
251         }
252         clk_rate = clk_get_rate(clksrc);
253 
254         ratio = clk_rate / freq;
255         if (ratio * freq > clk_rate)
256                 ret = ratio * freq - clk_rate;
257         else if (ratio * freq < clk_rate)
258                 ret = clk_rate - ratio * freq;
259         else
260                 ret = 0;
261 
262         /* Block if clock source can not be divided into the required rate */
263         if (ret != 0 && clk_rate / ret < 1000) {
264                 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
265                                 tx ? 'T' : 'R');
266                 return -EINVAL;
267         }
268 
269         /* Only EXTAL source can be output directly without using PSR and PM */
270         if (ratio == 1 && clksrc == esai_priv->extalclk) {
271                 /* Bypass all the dividers if not being needed */
272                 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
273                 goto out;
274         } else if (ratio < 2) {
275                 /* The ratio should be no less than 2 if using other sources */
276                 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
277                                 tx ? 'T' : 'R');
278                 return -EINVAL;
279         }
280 
281         ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
282         if (ret)
283                 return ret;
284 
285         esai_priv->sck_div[tx] = false;
286 
287 out:
288         esai_priv->hck_dir[tx] = dir;
289         esai_priv->hck_rate[tx] = freq;
290 
291         regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
292                            tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
293                            ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
294 
295         return 0;
296 }
297 
298 /**
299  * This function configures the related dividers according to the bclk rate
300  */
301 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
302 {
303         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
304         u32 hck_rate = esai_priv->hck_rate[tx];
305         u32 sub, ratio = hck_rate / freq;
306         int ret;
307 
308         /* Don't apply for fully slave mode or unchanged bclk */
309         if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
310                 return 0;
311 
312         if (ratio * freq > hck_rate)
313                 sub = ratio * freq - hck_rate;
314         else if (ratio * freq < hck_rate)
315                 sub = hck_rate - ratio * freq;
316         else
317                 sub = 0;
318 
319         /* Block if clock source can not be divided into the required rate */
320         if (sub != 0 && hck_rate / sub < 1000) {
321                 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
322                                 tx ? 'T' : 'R');
323                 return -EINVAL;
324         }
325 
326         /* The ratio should be contented by FP alone if bypassing PM and PSR */
327         if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
328                 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
329                 return -EINVAL;
330         }
331 
332         ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
333                         esai_priv->sck_div[tx] ? 0 : ratio);
334         if (ret)
335                 return ret;
336 
337         /* Save current bclk rate */
338         esai_priv->sck_rate[tx] = freq;
339 
340         return 0;
341 }
342 
343 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
344                                      u32 rx_mask, int slots, int slot_width)
345 {
346         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
347 
348         regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
349                            ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
350 
351         regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMA,
352                            ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(tx_mask));
353         regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMB,
354                            ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(tx_mask));
355 
356         regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
357                            ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
358 
359         regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMA,
360                            ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(rx_mask));
361         regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMB,
362                            ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask));
363 
364         esai_priv->slot_width = slot_width;
365 
366         return 0;
367 }
368 
369 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
370 {
371         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
372         u32 xcr = 0, xccr = 0, mask;
373 
374         /* DAI mode */
375         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
376         case SND_SOC_DAIFMT_I2S:
377                 /* Data on rising edge of bclk, frame low, 1clk before data */
378                 xcr |= ESAI_xCR_xFSR;
379                 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
380                 break;
381         case SND_SOC_DAIFMT_LEFT_J:
382                 /* Data on rising edge of bclk, frame high */
383                 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
384                 break;
385         case SND_SOC_DAIFMT_RIGHT_J:
386                 /* Data on rising edge of bclk, frame high, right aligned */
387                 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCR_xWA;
388                 break;
389         case SND_SOC_DAIFMT_DSP_A:
390                 /* Data on rising edge of bclk, frame high, 1clk before data */
391                 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
392                 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
393                 break;
394         case SND_SOC_DAIFMT_DSP_B:
395                 /* Data on rising edge of bclk, frame high */
396                 xcr |= ESAI_xCR_xFSL;
397                 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
398                 break;
399         default:
400                 return -EINVAL;
401         }
402 
403         /* DAI clock inversion */
404         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
405         case SND_SOC_DAIFMT_NB_NF:
406                 /* Nothing to do for both normal cases */
407                 break;
408         case SND_SOC_DAIFMT_IB_NF:
409                 /* Invert bit clock */
410                 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
411                 break;
412         case SND_SOC_DAIFMT_NB_IF:
413                 /* Invert frame clock */
414                 xccr ^= ESAI_xCCR_xFSP;
415                 break;
416         case SND_SOC_DAIFMT_IB_IF:
417                 /* Invert both clocks */
418                 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
419                 break;
420         default:
421                 return -EINVAL;
422         }
423 
424         esai_priv->slave_mode = false;
425 
426         /* DAI clock master masks */
427         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
428         case SND_SOC_DAIFMT_CBM_CFM:
429                 esai_priv->slave_mode = true;
430                 break;
431         case SND_SOC_DAIFMT_CBS_CFM:
432                 xccr |= ESAI_xCCR_xCKD;
433                 break;
434         case SND_SOC_DAIFMT_CBM_CFS:
435                 xccr |= ESAI_xCCR_xFSD;
436                 break;
437         case SND_SOC_DAIFMT_CBS_CFS:
438                 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
439                 break;
440         default:
441                 return -EINVAL;
442         }
443 
444         mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR;
445         regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
446         regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
447 
448         mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
449                 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD | ESAI_xCR_xWA;
450         regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
451         regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
452 
453         return 0;
454 }
455 
456 static int fsl_esai_startup(struct snd_pcm_substream *substream,
457                             struct snd_soc_dai *dai)
458 {
459         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
460         int ret;
461 
462         /*
463          * Some platforms might use the same bit to gate all three or two of
464          * clocks, so keep all clocks open/close at the same time for safety
465          */
466         ret = clk_prepare_enable(esai_priv->coreclk);
467         if (ret)
468                 return ret;
469         if (!IS_ERR(esai_priv->extalclk)) {
470                 ret = clk_prepare_enable(esai_priv->extalclk);
471                 if (ret)
472                         goto err_extalck;
473         }
474         if (!IS_ERR(esai_priv->fsysclk)) {
475                 ret = clk_prepare_enable(esai_priv->fsysclk);
476                 if (ret)
477                         goto err_fsysclk;
478         }
479 
480         if (!dai->active) {
481                 /* Set synchronous mode */
482                 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
483                                    ESAI_SAICR_SYNC, esai_priv->synchronous ?
484                                    ESAI_SAICR_SYNC : 0);
485 
486                 /* Set a default slot number -- 2 */
487                 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
488                                    ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
489                 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
490                                    ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
491         }
492 
493         return 0;
494 
495 err_fsysclk:
496         if (!IS_ERR(esai_priv->extalclk))
497                 clk_disable_unprepare(esai_priv->extalclk);
498 err_extalck:
499         clk_disable_unprepare(esai_priv->coreclk);
500 
501         return ret;
502 }
503 
504 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
505                               struct snd_pcm_hw_params *params,
506                               struct snd_soc_dai *dai)
507 {
508         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
509         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
510         u32 width = snd_pcm_format_width(params_format(params));
511         u32 channels = params_channels(params);
512         u32 bclk, mask, val;
513         int ret;
514 
515         bclk = params_rate(params) * esai_priv->slot_width * 2;
516 
517         ret = fsl_esai_set_bclk(dai, tx, bclk);
518         if (ret)
519                 return ret;
520 
521         /* Use Normal mode to support monaural audio */
522         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
523                            ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
524                            ESAI_xCR_xMOD_NETWORK : 0);
525 
526         regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
527                            ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
528 
529         mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
530               (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
531         val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
532              (tx ? ESAI_xFCR_TE(channels) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(channels));
533 
534         regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
535 
536         mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
537         val = ESAI_xCR_xSWS(esai_priv->slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
538 
539         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
540 
541         /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
542         regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
543                            ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
544         regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
545                            ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
546         return 0;
547 }
548 
549 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
550                               struct snd_soc_dai *dai)
551 {
552         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
553 
554         if (!IS_ERR(esai_priv->fsysclk))
555                 clk_disable_unprepare(esai_priv->fsysclk);
556         if (!IS_ERR(esai_priv->extalclk))
557                 clk_disable_unprepare(esai_priv->extalclk);
558         clk_disable_unprepare(esai_priv->coreclk);
559 }
560 
561 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
562                             struct snd_soc_dai *dai)
563 {
564         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
565         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
566         u8 i, channels = substream->runtime->channels;
567 
568         switch (cmd) {
569         case SNDRV_PCM_TRIGGER_START:
570         case SNDRV_PCM_TRIGGER_RESUME:
571         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
572                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
573                                    ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
574 
575                 /* Write initial words reqiured by ESAI as normal procedure */
576                 for (i = 0; tx && i < channels; i++)
577                         regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
578 
579                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
580                                    tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
581                                    tx ? ESAI_xCR_TE(channels) : ESAI_xCR_RE(channels));
582                 break;
583         case SNDRV_PCM_TRIGGER_SUSPEND:
584         case SNDRV_PCM_TRIGGER_STOP:
585         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
586                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
587                                    tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
588 
589                 /* Disable and reset FIFO */
590                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
591                                    ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
592                 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
593                                    ESAI_xFCR_xFR, 0);
594                 break;
595         default:
596                 return -EINVAL;
597         }
598 
599         return 0;
600 }
601 
602 static struct snd_soc_dai_ops fsl_esai_dai_ops = {
603         .startup = fsl_esai_startup,
604         .shutdown = fsl_esai_shutdown,
605         .trigger = fsl_esai_trigger,
606         .hw_params = fsl_esai_hw_params,
607         .set_sysclk = fsl_esai_set_dai_sysclk,
608         .set_fmt = fsl_esai_set_dai_fmt,
609         .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
610 };
611 
612 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
613 {
614         struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
615 
616         snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
617                                   &esai_priv->dma_params_rx);
618 
619         return 0;
620 }
621 
622 static struct snd_soc_dai_driver fsl_esai_dai = {
623         .probe = fsl_esai_dai_probe,
624         .playback = {
625                 .stream_name = "CPU-Playback",
626                 .channels_min = 1,
627                 .channels_max = 12,
628                 .rates = FSL_ESAI_RATES,
629                 .formats = FSL_ESAI_FORMATS,
630         },
631         .capture = {
632                 .stream_name = "CPU-Capture",
633                 .channels_min = 1,
634                 .channels_max = 8,
635                 .rates = FSL_ESAI_RATES,
636                 .formats = FSL_ESAI_FORMATS,
637         },
638         .ops = &fsl_esai_dai_ops,
639 };
640 
641 static const struct snd_soc_component_driver fsl_esai_component = {
642         .name           = "fsl-esai",
643 };
644 
645 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
646 {
647         switch (reg) {
648         case REG_ESAI_ERDR:
649         case REG_ESAI_ECR:
650         case REG_ESAI_ESR:
651         case REG_ESAI_TFCR:
652         case REG_ESAI_TFSR:
653         case REG_ESAI_RFCR:
654         case REG_ESAI_RFSR:
655         case REG_ESAI_RX0:
656         case REG_ESAI_RX1:
657         case REG_ESAI_RX2:
658         case REG_ESAI_RX3:
659         case REG_ESAI_SAISR:
660         case REG_ESAI_SAICR:
661         case REG_ESAI_TCR:
662         case REG_ESAI_TCCR:
663         case REG_ESAI_RCR:
664         case REG_ESAI_RCCR:
665         case REG_ESAI_TSMA:
666         case REG_ESAI_TSMB:
667         case REG_ESAI_RSMA:
668         case REG_ESAI_RSMB:
669         case REG_ESAI_PRRC:
670         case REG_ESAI_PCRC:
671                 return true;
672         default:
673                 return false;
674         }
675 }
676 
677 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
678 {
679         switch (reg) {
680         case REG_ESAI_ETDR:
681         case REG_ESAI_ECR:
682         case REG_ESAI_TFCR:
683         case REG_ESAI_RFCR:
684         case REG_ESAI_TX0:
685         case REG_ESAI_TX1:
686         case REG_ESAI_TX2:
687         case REG_ESAI_TX3:
688         case REG_ESAI_TX4:
689         case REG_ESAI_TX5:
690         case REG_ESAI_TSR:
691         case REG_ESAI_SAICR:
692         case REG_ESAI_TCR:
693         case REG_ESAI_TCCR:
694         case REG_ESAI_RCR:
695         case REG_ESAI_RCCR:
696         case REG_ESAI_TSMA:
697         case REG_ESAI_TSMB:
698         case REG_ESAI_RSMA:
699         case REG_ESAI_RSMB:
700         case REG_ESAI_PRRC:
701         case REG_ESAI_PCRC:
702                 return true;
703         default:
704                 return false;
705         }
706 }
707 
708 static struct regmap_config fsl_esai_regmap_config = {
709         .reg_bits = 32,
710         .reg_stride = 4,
711         .val_bits = 32,
712 
713         .max_register = REG_ESAI_PCRC,
714         .readable_reg = fsl_esai_readable_reg,
715         .writeable_reg = fsl_esai_writeable_reg,
716 };
717 
718 static int fsl_esai_probe(struct platform_device *pdev)
719 {
720         struct device_node *np = pdev->dev.of_node;
721         struct fsl_esai *esai_priv;
722         struct resource *res;
723         const uint32_t *iprop;
724         void __iomem *regs;
725         int irq, ret;
726 
727         esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
728         if (!esai_priv)
729                 return -ENOMEM;
730 
731         esai_priv->pdev = pdev;
732         strcpy(esai_priv->name, np->name);
733 
734         if (of_property_read_bool(np, "big-endian"))
735                 fsl_esai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
736 
737         /* Get the addresses and IRQ */
738         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
739         regs = devm_ioremap_resource(&pdev->dev, res);
740         if (IS_ERR(regs))
741                 return PTR_ERR(regs);
742 
743         esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
744                         "core", regs, &fsl_esai_regmap_config);
745         if (IS_ERR(esai_priv->regmap)) {
746                 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
747                                 PTR_ERR(esai_priv->regmap));
748                 return PTR_ERR(esai_priv->regmap);
749         }
750 
751         esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
752         if (IS_ERR(esai_priv->coreclk)) {
753                 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
754                                 PTR_ERR(esai_priv->coreclk));
755                 return PTR_ERR(esai_priv->coreclk);
756         }
757 
758         esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
759         if (IS_ERR(esai_priv->extalclk))
760                 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
761                                 PTR_ERR(esai_priv->extalclk));
762 
763         esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
764         if (IS_ERR(esai_priv->fsysclk))
765                 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
766                                 PTR_ERR(esai_priv->fsysclk));
767 
768         irq = platform_get_irq(pdev, 0);
769         if (irq < 0) {
770                 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
771                 return irq;
772         }
773 
774         ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
775                                esai_priv->name, esai_priv);
776         if (ret) {
777                 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
778                 return ret;
779         }
780 
781         /* Set a default slot size */
782         esai_priv->slot_width = 32;
783 
784         /* Set a default master/slave state */
785         esai_priv->slave_mode = true;
786 
787         /* Determine the FIFO depth */
788         iprop = of_get_property(np, "fsl,fifo-depth", NULL);
789         if (iprop)
790                 esai_priv->fifo_depth = be32_to_cpup(iprop);
791         else
792                 esai_priv->fifo_depth = 64;
793 
794         esai_priv->dma_params_tx.maxburst = 16;
795         esai_priv->dma_params_rx.maxburst = 16;
796         esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
797         esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
798 
799         esai_priv->synchronous =
800                 of_property_read_bool(np, "fsl,esai-synchronous");
801 
802         /* Implement full symmetry for synchronous mode */
803         if (esai_priv->synchronous) {
804                 fsl_esai_dai.symmetric_rates = 1;
805                 fsl_esai_dai.symmetric_channels = 1;
806                 fsl_esai_dai.symmetric_samplebits = 1;
807         }
808 
809         dev_set_drvdata(&pdev->dev, esai_priv);
810 
811         /* Reset ESAI unit */
812         ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
813         if (ret) {
814                 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
815                 return ret;
816         }
817 
818         /*
819          * We need to enable ESAI so as to access some of its registers.
820          * Otherwise, we would fail to dump regmap from user space.
821          */
822         ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
823         if (ret) {
824                 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
825                 return ret;
826         }
827 
828         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
829                                               &fsl_esai_dai, 1);
830         if (ret) {
831                 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
832                 return ret;
833         }
834 
835         ret = imx_pcm_dma_init(pdev);
836         if (ret)
837                 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
838 
839         return ret;
840 }
841 
842 static const struct of_device_id fsl_esai_dt_ids[] = {
843         { .compatible = "fsl,imx35-esai", },
844         { .compatible = "fsl,vf610-esai", },
845         {}
846 };
847 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
848 
849 static struct platform_driver fsl_esai_driver = {
850         .probe = fsl_esai_probe,
851         .driver = {
852                 .name = "fsl-esai-dai",
853                 .owner = THIS_MODULE,
854                 .of_match_table = fsl_esai_dt_ids,
855         },
856 };
857 
858 module_platform_driver(fsl_esai_driver);
859 
860 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
861 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
862 MODULE_LICENSE("GPL v2");
863 MODULE_ALIAS("platform:fsl-esai-dai");
864 

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