Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/sound/soc/davinci/davinci-mcasp.c

  1 /*
  2  * ALSA SoC McASP Audio Layer for TI DAVINCI processor
  3  *
  4  * Multi-channel Audio Serial Port Driver
  5  *
  6  * Author: Nirmal Pandey <n-pandey@ti.com>,
  7  *         Suresh Rajashekara <suresh.r@ti.com>
  8  *         Steve Chen <schen@.mvista.com>
  9  *
 10  * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
 11  * Copyright:   (C) 2009  Texas Instruments, India
 12  *
 13  * This program is free software; you can redistribute it and/or modify
 14  * it under the terms of the GNU General Public License version 2 as
 15  * published by the Free Software Foundation.
 16  */
 17 
 18 #include <linux/init.h>
 19 #include <linux/module.h>
 20 #include <linux/device.h>
 21 #include <linux/slab.h>
 22 #include <linux/delay.h>
 23 #include <linux/io.h>
 24 #include <linux/clk.h>
 25 #include <linux/pm_runtime.h>
 26 #include <linux/of.h>
 27 #include <linux/of_platform.h>
 28 #include <linux/of_device.h>
 29 
 30 #include <sound/asoundef.h>
 31 #include <sound/core.h>
 32 #include <sound/pcm.h>
 33 #include <sound/pcm_params.h>
 34 #include <sound/initval.h>
 35 #include <sound/soc.h>
 36 #include <sound/dmaengine_pcm.h>
 37 #include <sound/omap-pcm.h>
 38 
 39 #include "davinci-pcm.h"
 40 #include "edma-pcm.h"
 41 #include "davinci-mcasp.h"
 42 
 43 #define MCASP_MAX_AFIFO_DEPTH   64
 44 
 45 static u32 context_regs[] = {
 46         DAVINCI_MCASP_TXFMCTL_REG,
 47         DAVINCI_MCASP_RXFMCTL_REG,
 48         DAVINCI_MCASP_TXFMT_REG,
 49         DAVINCI_MCASP_RXFMT_REG,
 50         DAVINCI_MCASP_ACLKXCTL_REG,
 51         DAVINCI_MCASP_ACLKRCTL_REG,
 52         DAVINCI_MCASP_AHCLKXCTL_REG,
 53         DAVINCI_MCASP_AHCLKRCTL_REG,
 54         DAVINCI_MCASP_PDIR_REG,
 55         DAVINCI_MCASP_RXMASK_REG,
 56         DAVINCI_MCASP_TXMASK_REG,
 57         DAVINCI_MCASP_RXTDM_REG,
 58         DAVINCI_MCASP_TXTDM_REG,
 59 };
 60 
 61 struct davinci_mcasp_context {
 62         u32     config_regs[ARRAY_SIZE(context_regs)];
 63         u32     afifo_regs[2]; /* for read/write fifo control registers */
 64         u32     *xrsr_regs; /* for serializer configuration */
 65 };
 66 
 67 struct davinci_mcasp {
 68         struct davinci_pcm_dma_params dma_params[2];
 69         struct snd_dmaengine_dai_dma_data dma_data[2];
 70         void __iomem *base;
 71         u32 fifo_base;
 72         struct device *dev;
 73         struct snd_pcm_substream *substreams[2];
 74 
 75         /* McASP specific data */
 76         int     tdm_slots;
 77         u8      op_mode;
 78         u8      num_serializer;
 79         u8      *serial_dir;
 80         u8      version;
 81         u8      bclk_div;
 82         u16     bclk_lrclk_ratio;
 83         int     streams;
 84         u32     irq_request[2];
 85 
 86         int     sysclk_freq;
 87         bool    bclk_master;
 88 
 89         /* McASP FIFO related */
 90         u8      txnumevt;
 91         u8      rxnumevt;
 92 
 93         bool    dat_port;
 94 
 95         /* Used for comstraint setting on the second stream */
 96         u32     channels;
 97 
 98 #ifdef CONFIG_PM_SLEEP
 99         struct davinci_mcasp_context context;
100 #endif
101 };
102 
103 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
104                                   u32 val)
105 {
106         void __iomem *reg = mcasp->base + offset;
107         __raw_writel(__raw_readl(reg) | val, reg);
108 }
109 
110 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
111                                   u32 val)
112 {
113         void __iomem *reg = mcasp->base + offset;
114         __raw_writel((__raw_readl(reg) & ~(val)), reg);
115 }
116 
117 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
118                                   u32 val, u32 mask)
119 {
120         void __iomem *reg = mcasp->base + offset;
121         __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
122 }
123 
124 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
125                                  u32 val)
126 {
127         __raw_writel(val, mcasp->base + offset);
128 }
129 
130 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
131 {
132         return (u32)__raw_readl(mcasp->base + offset);
133 }
134 
135 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
136 {
137         int i = 0;
138 
139         mcasp_set_bits(mcasp, ctl_reg, val);
140 
141         /* programming GBLCTL needs to read back from GBLCTL and verfiy */
142         /* loop count is to avoid the lock-up */
143         for (i = 0; i < 1000; i++) {
144                 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
145                         break;
146         }
147 
148         if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
149                 printk(KERN_ERR "GBLCTL write error\n");
150 }
151 
152 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
153 {
154         u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
155         u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
156 
157         return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
158 }
159 
160 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
161 {
162         if (mcasp->rxnumevt) {  /* enable FIFO */
163                 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
164 
165                 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
166                 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
167         }
168 
169         /* Start clocks */
170         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
171         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
172         /*
173          * When ASYNC == 0 the transmit and receive sections operate
174          * synchronously from the transmit clock and frame sync. We need to make
175          * sure that the TX signlas are enabled when starting reception.
176          */
177         if (mcasp_is_synchronous(mcasp)) {
178                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
179                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
180         }
181 
182         /* Activate serializer(s) */
183         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
184         /* Release RX state machine */
185         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
186         /* Release Frame Sync generator */
187         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
188         if (mcasp_is_synchronous(mcasp))
189                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
190 
191         /* enable receive IRQs */
192         mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
193                        mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
194 }
195 
196 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
197 {
198         u32 cnt;
199 
200         if (mcasp->txnumevt) {  /* enable FIFO */
201                 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
202 
203                 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
204                 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
205         }
206 
207         /* Start clocks */
208         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
209         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
210         /* Activate serializer(s) */
211         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
212 
213         /* wait for XDATA to be cleared */
214         cnt = 0;
215         while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) &
216                  ~XRDATA) && (cnt < 100000))
217                 cnt++;
218 
219         /* Release TX state machine */
220         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
221         /* Release Frame Sync generator */
222         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
223 
224         /* enable transmit IRQs */
225         mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
226                        mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
227 }
228 
229 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
230 {
231         mcasp->streams++;
232 
233         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
234                 mcasp_start_tx(mcasp);
235         else
236                 mcasp_start_rx(mcasp);
237 }
238 
239 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
240 {
241         /* disable IRQ sources */
242         mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
243                        mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
244 
245         /*
246          * In synchronous mode stop the TX clocks if no other stream is
247          * running
248          */
249         if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
250                 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
251 
252         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
253         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
254 
255         if (mcasp->rxnumevt) {  /* disable FIFO */
256                 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
257 
258                 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
259         }
260 }
261 
262 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
263 {
264         u32 val = 0;
265 
266         /* disable IRQ sources */
267         mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
268                        mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
269 
270         /*
271          * In synchronous mode keep TX clocks running if the capture stream is
272          * still running.
273          */
274         if (mcasp_is_synchronous(mcasp) && mcasp->streams)
275                 val =  TXHCLKRST | TXCLKRST | TXFSRST;
276 
277         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
278         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
279 
280         if (mcasp->txnumevt) {  /* disable FIFO */
281                 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
282 
283                 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
284         }
285 }
286 
287 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
288 {
289         mcasp->streams--;
290 
291         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
292                 mcasp_stop_tx(mcasp);
293         else
294                 mcasp_stop_rx(mcasp);
295 }
296 
297 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
298 {
299         struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
300         struct snd_pcm_substream *substream;
301         u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
302         u32 handled_mask = 0;
303         u32 stat;
304 
305         stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
306         if (stat & XUNDRN & irq_mask) {
307                 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
308                 handled_mask |= XUNDRN;
309 
310                 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
311                 if (substream) {
312                         snd_pcm_stream_lock_irq(substream);
313                         if (snd_pcm_running(substream))
314                                 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
315                         snd_pcm_stream_unlock_irq(substream);
316                 }
317         }
318 
319         if (!handled_mask)
320                 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
321                          stat);
322 
323         if (stat & XRERR)
324                 handled_mask |= XRERR;
325 
326         /* Ack the handled event only */
327         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
328 
329         return IRQ_RETVAL(handled_mask);
330 }
331 
332 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
333 {
334         struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
335         struct snd_pcm_substream *substream;
336         u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
337         u32 handled_mask = 0;
338         u32 stat;
339 
340         stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
341         if (stat & ROVRN & irq_mask) {
342                 dev_warn(mcasp->dev, "Receive buffer overflow\n");
343                 handled_mask |= ROVRN;
344 
345                 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
346                 if (substream) {
347                         snd_pcm_stream_lock_irq(substream);
348                         if (snd_pcm_running(substream))
349                                 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
350                         snd_pcm_stream_unlock_irq(substream);
351                 }
352         }
353 
354         if (!handled_mask)
355                 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
356                          stat);
357 
358         if (stat & XRERR)
359                 handled_mask |= XRERR;
360 
361         /* Ack the handled event only */
362         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
363 
364         return IRQ_RETVAL(handled_mask);
365 }
366 
367 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
368 {
369         struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
370         irqreturn_t ret = IRQ_NONE;
371 
372         if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
373                 ret = davinci_mcasp_tx_irq_handler(irq, data);
374 
375         if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
376                 ret |= davinci_mcasp_rx_irq_handler(irq, data);
377 
378         return ret;
379 }
380 
381 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
382                                          unsigned int fmt)
383 {
384         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
385         int ret = 0;
386         u32 data_delay;
387         bool fs_pol_rising;
388         bool inv_fs = false;
389 
390         pm_runtime_get_sync(mcasp->dev);
391         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
392         case SND_SOC_DAIFMT_DSP_A:
393                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
394                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
395                 /* 1st data bit occur one ACLK cycle after the frame sync */
396                 data_delay = 1;
397                 break;
398         case SND_SOC_DAIFMT_DSP_B:
399         case SND_SOC_DAIFMT_AC97:
400                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
401                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
402                 /* No delay after FS */
403                 data_delay = 0;
404                 break;
405         case SND_SOC_DAIFMT_I2S:
406                 /* configure a full-word SYNC pulse (LRCLK) */
407                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
408                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
409                 /* 1st data bit occur one ACLK cycle after the frame sync */
410                 data_delay = 1;
411                 /* FS need to be inverted */
412                 inv_fs = true;
413                 break;
414         case SND_SOC_DAIFMT_LEFT_J:
415                 /* configure a full-word SYNC pulse (LRCLK) */
416                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
417                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
418                 /* No delay after FS */
419                 data_delay = 0;
420                 break;
421         default:
422                 ret = -EINVAL;
423                 goto out;
424         }
425 
426         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
427                        FSXDLY(3));
428         mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
429                        FSRDLY(3));
430 
431         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
432         case SND_SOC_DAIFMT_CBS_CFS:
433                 /* codec is clock and frame slave */
434                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
435                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
436 
437                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
438                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
439 
440                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
441                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
442                 mcasp->bclk_master = 1;
443                 break;
444         case SND_SOC_DAIFMT_CBM_CFS:
445                 /* codec is clock master and frame slave */
446                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
447                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
448 
449                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
450                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
451 
452                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
453                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
454                 mcasp->bclk_master = 0;
455                 break;
456         case SND_SOC_DAIFMT_CBM_CFM:
457                 /* codec is clock and frame master */
458                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
459                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
460 
461                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
462                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
463 
464                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
465                                ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
466                 mcasp->bclk_master = 0;
467                 break;
468         default:
469                 ret = -EINVAL;
470                 goto out;
471         }
472 
473         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
474         case SND_SOC_DAIFMT_IB_NF:
475                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
476                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
477                 fs_pol_rising = true;
478                 break;
479         case SND_SOC_DAIFMT_NB_IF:
480                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
481                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
482                 fs_pol_rising = false;
483                 break;
484         case SND_SOC_DAIFMT_IB_IF:
485                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
486                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
487                 fs_pol_rising = false;
488                 break;
489         case SND_SOC_DAIFMT_NB_NF:
490                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
491                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
492                 fs_pol_rising = true;
493                 break;
494         default:
495                 ret = -EINVAL;
496                 goto out;
497         }
498 
499         if (inv_fs)
500                 fs_pol_rising = !fs_pol_rising;
501 
502         if (fs_pol_rising) {
503                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
504                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
505         } else {
506                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
507                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
508         }
509 out:
510         pm_runtime_put_sync(mcasp->dev);
511         return ret;
512 }
513 
514 static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
515                                       int div, bool explicit)
516 {
517         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
518 
519         switch (div_id) {
520         case 0:         /* MCLK divider */
521                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
522                                AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
523                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
524                                AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
525                 break;
526 
527         case 1:         /* BCLK divider */
528                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
529                                ACLKXDIV(div - 1), ACLKXDIV_MASK);
530                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
531                                ACLKRDIV(div - 1), ACLKRDIV_MASK);
532                 if (explicit)
533                         mcasp->bclk_div = div;
534                 break;
535 
536         case 2:         /* BCLK/LRCLK ratio */
537                 mcasp->bclk_lrclk_ratio = div;
538                 break;
539 
540         default:
541                 return -EINVAL;
542         }
543 
544         return 0;
545 }
546 
547 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
548                                     int div)
549 {
550         return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
551 }
552 
553 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
554                                     unsigned int freq, int dir)
555 {
556         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
557 
558         if (dir == SND_SOC_CLOCK_OUT) {
559                 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
560                 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
561                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
562         } else {
563                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
564                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
565                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
566         }
567 
568         mcasp->sysclk_freq = freq;
569 
570         return 0;
571 }
572 
573 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
574                                        int word_length)
575 {
576         u32 fmt;
577         u32 tx_rotate = (word_length / 4) & 0x7;
578         u32 mask = (1ULL << word_length) - 1;
579         /*
580          * For captured data we should not rotate, inversion and masking is
581          * enoguh to get the data to the right position:
582          * Format         data from bus         after reverse (XRBUF)
583          * S16_LE:      |LSB|MSB|xxx|xxx|       |xxx|xxx|MSB|LSB|
584          * S24_3LE:     |LSB|DAT|MSB|xxx|       |xxx|MSB|DAT|LSB|
585          * S24_LE:      |LSB|DAT|MSB|xxx|       |xxx|MSB|DAT|LSB|
586          * S32_LE:      |LSB|DAT|DAT|MSB|       |MSB|DAT|DAT|LSB|
587          */
588         u32 rx_rotate = 0;
589 
590         /*
591          * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
592          * callback, take it into account here. That allows us to for example
593          * send 32 bits per channel to the codec, while only 16 of them carry
594          * audio payload.
595          * The clock ratio is given for a full period of data (for I2S format
596          * both left and right channels), so it has to be divided by number of
597          * tdm-slots (for I2S - divided by 2).
598          */
599         if (mcasp->bclk_lrclk_ratio) {
600                 u32 slot_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
601 
602                 /*
603                  * When we have more bclk then it is needed for the data, we
604                  * need to use the rotation to move the received samples to have
605                  * correct alignment.
606                  */
607                 rx_rotate = (slot_length - word_length) / 4;
608                 word_length = slot_length;
609         }
610 
611         /* mapping of the XSSZ bit-field as described in the datasheet */
612         fmt = (word_length >> 1) - 1;
613 
614         if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
615                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
616                                RXSSZ(0x0F));
617                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
618                                TXSSZ(0x0F));
619                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
620                                TXROT(7));
621                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
622                                RXROT(7));
623                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
624         }
625 
626         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
627 
628         return 0;
629 }
630 
631 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
632                                  int period_words, int channels)
633 {
634         struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream];
635         struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
636         int i;
637         u8 tx_ser = 0;
638         u8 rx_ser = 0;
639         u8 slots = mcasp->tdm_slots;
640         u8 max_active_serializers = (channels + slots - 1) / slots;
641         int active_serializers, numevt, n;
642         u32 reg;
643         /* Default configuration */
644         if (mcasp->version < MCASP_VERSION_3)
645                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
646 
647         /* All PINS as McASP */
648         mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
649 
650         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
651                 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
652                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
653         } else {
654                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
655                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
656         }
657 
658         for (i = 0; i < mcasp->num_serializer; i++) {
659                 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
660                                mcasp->serial_dir[i]);
661                 if (mcasp->serial_dir[i] == TX_MODE &&
662                                         tx_ser < max_active_serializers) {
663                         mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
664                         tx_ser++;
665                 } else if (mcasp->serial_dir[i] == RX_MODE &&
666                                         rx_ser < max_active_serializers) {
667                         mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
668                         rx_ser++;
669                 } else {
670                         mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
671                                        SRMOD_INACTIVE, SRMOD_MASK);
672                 }
673         }
674 
675         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
676                 active_serializers = tx_ser;
677                 numevt = mcasp->txnumevt;
678                 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
679         } else {
680                 active_serializers = rx_ser;
681                 numevt = mcasp->rxnumevt;
682                 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
683         }
684 
685         if (active_serializers < max_active_serializers) {
686                 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
687                          "enabled in mcasp (%d)\n", channels,
688                          active_serializers * slots);
689                 return -EINVAL;
690         }
691 
692         /* AFIFO is not in use */
693         if (!numevt) {
694                 /* Configure the burst size for platform drivers */
695                 if (active_serializers > 1) {
696                         /*
697                          * If more than one serializers are in use we have one
698                          * DMA request to provide data for all serializers.
699                          * For example if three serializers are enabled the DMA
700                          * need to transfer three words per DMA request.
701                          */
702                         dma_params->fifo_level = active_serializers;
703                         dma_data->maxburst = active_serializers;
704                 } else {
705                         dma_params->fifo_level = 0;
706                         dma_data->maxburst = 0;
707                 }
708                 return 0;
709         }
710 
711         if (period_words % active_serializers) {
712                 dev_err(mcasp->dev, "Invalid combination of period words and "
713                         "active serializers: %d, %d\n", period_words,
714                         active_serializers);
715                 return -EINVAL;
716         }
717 
718         /*
719          * Calculate the optimal AFIFO depth for platform side:
720          * The number of words for numevt need to be in steps of active
721          * serializers.
722          */
723         n = numevt % active_serializers;
724         if (n)
725                 numevt += (active_serializers - n);
726         while (period_words % numevt && numevt > 0)
727                 numevt -= active_serializers;
728         if (numevt <= 0)
729                 numevt = active_serializers;
730 
731         mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
732         mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
733 
734         /* Configure the burst size for platform drivers */
735         if (numevt == 1)
736                 numevt = 0;
737         dma_params->fifo_level = numevt;
738         dma_data->maxburst = numevt;
739 
740         return 0;
741 }
742 
743 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
744                               int channels)
745 {
746         int i, active_slots;
747         int total_slots;
748         int active_serializers;
749         u32 mask = 0;
750         u32 busel = 0;
751 
752         total_slots = mcasp->tdm_slots;
753 
754         /*
755          * If more than one serializer is needed, then use them with
756          * their specified tdm_slots count. Otherwise, one serializer
757          * can cope with the transaction using as many slots as channels
758          * in the stream, requires channels symmetry
759          */
760         active_serializers = (channels + total_slots - 1) / total_slots;
761         if (active_serializers == 1)
762                 active_slots = channels;
763         else
764                 active_slots = total_slots;
765 
766         for (i = 0; i < active_slots; i++)
767                 mask |= (1 << i);
768 
769         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
770 
771         if (!mcasp->dat_port)
772                 busel = TXSEL;
773 
774         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
775         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
776         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
777                        FSXMOD(total_slots), FSXMOD(0x1FF));
778 
779         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
780         mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
781         mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
782                        FSRMOD(total_slots), FSRMOD(0x1FF));
783 
784         return 0;
785 }
786 
787 /* S/PDIF */
788 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
789                               unsigned int rate)
790 {
791         u32 cs_value = 0;
792         u8 *cs_bytes = (u8*) &cs_value;
793 
794         /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
795            and LSB first */
796         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
797 
798         /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
799         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
800 
801         /* Set the TX tdm : for all the slots */
802         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
803 
804         /* Set the TX clock controls : div = 1 and internal */
805         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
806 
807         mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
808 
809         /* Only 44100 and 48000 are valid, both have the same setting */
810         mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
811 
812         /* Enable the DIT */
813         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
814 
815         /* Set S/PDIF channel status bits */
816         cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
817         cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
818 
819         switch (rate) {
820         case 22050:
821                 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
822                 break;
823         case 24000:
824                 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
825                 break;
826         case 32000:
827                 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
828                 break;
829         case 44100:
830                 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
831                 break;
832         case 48000:
833                 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
834                 break;
835         case 88200:
836                 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
837                 break;
838         case 96000:
839                 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
840                 break;
841         case 176400:
842                 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
843                 break;
844         case 192000:
845                 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
846                 break;
847         default:
848                 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
849                 return -EINVAL;
850         }
851 
852         mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
853         mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
854 
855         return 0;
856 }
857 
858 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
859                                         struct snd_pcm_hw_params *params,
860                                         struct snd_soc_dai *cpu_dai)
861 {
862         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
863         struct davinci_pcm_dma_params *dma_params =
864                                         &mcasp->dma_params[substream->stream];
865         int word_length;
866         int channels = params_channels(params);
867         int period_size = params_period_size(params);
868         int ret;
869 
870         /*
871          * If mcasp is BCLK master, and a BCLK divider was not provided by
872          * the machine driver, we need to calculate the ratio.
873          */
874         if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
875                 unsigned int bclk_freq = snd_soc_params_to_bclk(params);
876                 unsigned int div = mcasp->sysclk_freq / bclk_freq;
877                 if (mcasp->sysclk_freq % bclk_freq != 0) {
878                         if (((mcasp->sysclk_freq / div) - bclk_freq) >
879                             (bclk_freq - (mcasp->sysclk_freq / (div+1))))
880                                 div++;
881                         dev_warn(mcasp->dev,
882                                  "Inaccurate BCLK: %u Hz / %u != %u Hz\n",
883                                  mcasp->sysclk_freq, div, bclk_freq);
884                 }
885                 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
886         }
887 
888         ret = mcasp_common_hw_param(mcasp, substream->stream,
889                                     period_size * channels, channels);
890         if (ret)
891                 return ret;
892 
893         if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
894                 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
895         else
896                 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
897                                          channels);
898 
899         if (ret)
900                 return ret;
901 
902         switch (params_format(params)) {
903         case SNDRV_PCM_FORMAT_U8:
904         case SNDRV_PCM_FORMAT_S8:
905                 dma_params->data_type = 1;
906                 word_length = 8;
907                 break;
908 
909         case SNDRV_PCM_FORMAT_U16_LE:
910         case SNDRV_PCM_FORMAT_S16_LE:
911                 dma_params->data_type = 2;
912                 word_length = 16;
913                 break;
914 
915         case SNDRV_PCM_FORMAT_U24_3LE:
916         case SNDRV_PCM_FORMAT_S24_3LE:
917                 dma_params->data_type = 3;
918                 word_length = 24;
919                 break;
920 
921         case SNDRV_PCM_FORMAT_U24_LE:
922         case SNDRV_PCM_FORMAT_S24_LE:
923                 dma_params->data_type = 4;
924                 word_length = 24;
925                 break;
926 
927         case SNDRV_PCM_FORMAT_U32_LE:
928         case SNDRV_PCM_FORMAT_S32_LE:
929                 dma_params->data_type = 4;
930                 word_length = 32;
931                 break;
932 
933         default:
934                 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
935                 return -EINVAL;
936         }
937 
938         if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level)
939                 dma_params->acnt = 4;
940         else
941                 dma_params->acnt = dma_params->data_type;
942 
943         davinci_config_channel_size(mcasp, word_length);
944 
945         if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
946                 mcasp->channels = channels;
947 
948         return 0;
949 }
950 
951 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
952                                      int cmd, struct snd_soc_dai *cpu_dai)
953 {
954         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
955         int ret = 0;
956 
957         switch (cmd) {
958         case SNDRV_PCM_TRIGGER_RESUME:
959         case SNDRV_PCM_TRIGGER_START:
960         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
961                 davinci_mcasp_start(mcasp, substream->stream);
962                 break;
963         case SNDRV_PCM_TRIGGER_SUSPEND:
964         case SNDRV_PCM_TRIGGER_STOP:
965         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
966                 davinci_mcasp_stop(mcasp, substream->stream);
967                 break;
968 
969         default:
970                 ret = -EINVAL;
971         }
972 
973         return ret;
974 }
975 
976 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
977                                  struct snd_soc_dai *cpu_dai)
978 {
979         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
980         u32 max_channels = 0;
981         int i, dir;
982 
983         mcasp->substreams[substream->stream] = substream;
984 
985         if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
986                 return 0;
987 
988         /*
989          * Limit the maximum allowed channels for the first stream:
990          * number of serializers for the direction * tdm slots per serializer
991          */
992         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
993                 dir = TX_MODE;
994         else
995                 dir = RX_MODE;
996 
997         for (i = 0; i < mcasp->num_serializer; i++) {
998                 if (mcasp->serial_dir[i] == dir)
999                         max_channels++;
1000         }
1001         max_channels *= mcasp->tdm_slots;
1002         /*
1003          * If the already active stream has less channels than the calculated
1004          * limnit based on the seirializers * tdm_slots, we need to use that as
1005          * a constraint for the second stream.
1006          * Otherwise (first stream or less allowed channels) we use the
1007          * calculated constraint.
1008          */
1009         if (mcasp->channels && mcasp->channels < max_channels)
1010                 max_channels = mcasp->channels;
1011 
1012         snd_pcm_hw_constraint_minmax(substream->runtime,
1013                                      SNDRV_PCM_HW_PARAM_CHANNELS,
1014                                      2, max_channels);
1015         return 0;
1016 }
1017 
1018 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1019                                    struct snd_soc_dai *cpu_dai)
1020 {
1021         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1022 
1023         mcasp->substreams[substream->stream] = NULL;
1024 
1025         if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1026                 return;
1027 
1028         if (!cpu_dai->active)
1029                 mcasp->channels = 0;
1030 }
1031 
1032 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1033         .startup        = davinci_mcasp_startup,
1034         .shutdown       = davinci_mcasp_shutdown,
1035         .trigger        = davinci_mcasp_trigger,
1036         .hw_params      = davinci_mcasp_hw_params,
1037         .set_fmt        = davinci_mcasp_set_dai_fmt,
1038         .set_clkdiv     = davinci_mcasp_set_clkdiv,
1039         .set_sysclk     = davinci_mcasp_set_sysclk,
1040 };
1041 
1042 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1043 {
1044         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1045 
1046         if (mcasp->version >= MCASP_VERSION_3) {
1047                 /* Using dmaengine PCM */
1048                 dai->playback_dma_data =
1049                                 &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1050                 dai->capture_dma_data =
1051                                 &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1052         } else {
1053                 /* Using davinci-pcm */
1054                 dai->playback_dma_data = mcasp->dma_params;
1055                 dai->capture_dma_data = mcasp->dma_params;
1056         }
1057 
1058         return 0;
1059 }
1060 
1061 #ifdef CONFIG_PM_SLEEP
1062 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1063 {
1064         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1065         struct davinci_mcasp_context *context = &mcasp->context;
1066         u32 reg;
1067         int i;
1068 
1069         for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1070                 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1071 
1072         if (mcasp->txnumevt) {
1073                 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1074                 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1075         }
1076         if (mcasp->rxnumevt) {
1077                 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1078                 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1079         }
1080 
1081         for (i = 0; i < mcasp->num_serializer; i++)
1082                 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1083                                                 DAVINCI_MCASP_XRSRCTL_REG(i));
1084 
1085         return 0;
1086 }
1087 
1088 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1089 {
1090         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1091         struct davinci_mcasp_context *context = &mcasp->context;
1092         u32 reg;
1093         int i;
1094 
1095         for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1096                 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1097 
1098         if (mcasp->txnumevt) {
1099                 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1100                 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1101         }
1102         if (mcasp->rxnumevt) {
1103                 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1104                 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1105         }
1106 
1107         for (i = 0; i < mcasp->num_serializer; i++)
1108                 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1109                               context->xrsr_regs[i]);
1110 
1111         return 0;
1112 }
1113 #else
1114 #define davinci_mcasp_suspend NULL
1115 #define davinci_mcasp_resume NULL
1116 #endif
1117 
1118 #define DAVINCI_MCASP_RATES     SNDRV_PCM_RATE_8000_192000
1119 
1120 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1121                                 SNDRV_PCM_FMTBIT_U8 | \
1122                                 SNDRV_PCM_FMTBIT_S16_LE | \
1123                                 SNDRV_PCM_FMTBIT_U16_LE | \
1124                                 SNDRV_PCM_FMTBIT_S24_LE | \
1125                                 SNDRV_PCM_FMTBIT_U24_LE | \
1126                                 SNDRV_PCM_FMTBIT_S24_3LE | \
1127                                 SNDRV_PCM_FMTBIT_U24_3LE | \
1128                                 SNDRV_PCM_FMTBIT_S32_LE | \
1129                                 SNDRV_PCM_FMTBIT_U32_LE)
1130 
1131 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1132         {
1133                 .name           = "davinci-mcasp.0",
1134                 .probe          = davinci_mcasp_dai_probe,
1135                 .suspend        = davinci_mcasp_suspend,
1136                 .resume         = davinci_mcasp_resume,
1137                 .playback       = {
1138                         .channels_min   = 2,
1139                         .channels_max   = 32 * 16,
1140                         .rates          = DAVINCI_MCASP_RATES,
1141                         .formats        = DAVINCI_MCASP_PCM_FMTS,
1142                 },
1143                 .capture        = {
1144                         .channels_min   = 2,
1145                         .channels_max   = 32 * 16,
1146                         .rates          = DAVINCI_MCASP_RATES,
1147                         .formats        = DAVINCI_MCASP_PCM_FMTS,
1148                 },
1149                 .ops            = &davinci_mcasp_dai_ops,
1150 
1151                 .symmetric_samplebits   = 1,
1152         },
1153         {
1154                 .name           = "davinci-mcasp.1",
1155                 .probe          = davinci_mcasp_dai_probe,
1156                 .playback       = {
1157                         .channels_min   = 1,
1158                         .channels_max   = 384,
1159                         .rates          = DAVINCI_MCASP_RATES,
1160                         .formats        = DAVINCI_MCASP_PCM_FMTS,
1161                 },
1162                 .ops            = &davinci_mcasp_dai_ops,
1163         },
1164 
1165 };
1166 
1167 static const struct snd_soc_component_driver davinci_mcasp_component = {
1168         .name           = "davinci-mcasp",
1169 };
1170 
1171 /* Some HW specific values and defaults. The rest is filled in from DT. */
1172 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1173         .tx_dma_offset = 0x400,
1174         .rx_dma_offset = 0x400,
1175         .asp_chan_q = EVENTQ_0,
1176         .version = MCASP_VERSION_1,
1177 };
1178 
1179 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1180         .tx_dma_offset = 0x2000,
1181         .rx_dma_offset = 0x2000,
1182         .asp_chan_q = EVENTQ_0,
1183         .version = MCASP_VERSION_2,
1184 };
1185 
1186 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1187         .tx_dma_offset = 0,
1188         .rx_dma_offset = 0,
1189         .asp_chan_q = EVENTQ_0,
1190         .version = MCASP_VERSION_3,
1191 };
1192 
1193 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1194         .tx_dma_offset = 0x200,
1195         .rx_dma_offset = 0x284,
1196         .asp_chan_q = EVENTQ_0,
1197         .version = MCASP_VERSION_4,
1198 };
1199 
1200 static const struct of_device_id mcasp_dt_ids[] = {
1201         {
1202                 .compatible = "ti,dm646x-mcasp-audio",
1203                 .data = &dm646x_mcasp_pdata,
1204         },
1205         {
1206                 .compatible = "ti,da830-mcasp-audio",
1207                 .data = &da830_mcasp_pdata,
1208         },
1209         {
1210                 .compatible = "ti,am33xx-mcasp-audio",
1211                 .data = &am33xx_mcasp_pdata,
1212         },
1213         {
1214                 .compatible = "ti,dra7-mcasp-audio",
1215                 .data = &dra7_mcasp_pdata,
1216         },
1217         { /* sentinel */ }
1218 };
1219 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1220 
1221 static int mcasp_reparent_fck(struct platform_device *pdev)
1222 {
1223         struct device_node *node = pdev->dev.of_node;
1224         struct clk *gfclk, *parent_clk;
1225         const char *parent_name;
1226         int ret;
1227 
1228         if (!node)
1229                 return 0;
1230 
1231         parent_name = of_get_property(node, "fck_parent", NULL);
1232         if (!parent_name)
1233                 return 0;
1234 
1235         gfclk = clk_get(&pdev->dev, "fck");
1236         if (IS_ERR(gfclk)) {
1237                 dev_err(&pdev->dev, "failed to get fck\n");
1238                 return PTR_ERR(gfclk);
1239         }
1240 
1241         parent_clk = clk_get(NULL, parent_name);
1242         if (IS_ERR(parent_clk)) {
1243                 dev_err(&pdev->dev, "failed to get parent clock\n");
1244                 ret = PTR_ERR(parent_clk);
1245                 goto err1;
1246         }
1247 
1248         ret = clk_set_parent(gfclk, parent_clk);
1249         if (ret) {
1250                 dev_err(&pdev->dev, "failed to reparent fck\n");
1251                 goto err2;
1252         }
1253 
1254 err2:
1255         clk_put(parent_clk);
1256 err1:
1257         clk_put(gfclk);
1258         return ret;
1259 }
1260 
1261 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1262                                                 struct platform_device *pdev)
1263 {
1264         struct device_node *np = pdev->dev.of_node;
1265         struct davinci_mcasp_pdata *pdata = NULL;
1266         const struct of_device_id *match =
1267                         of_match_device(mcasp_dt_ids, &pdev->dev);
1268         struct of_phandle_args dma_spec;
1269 
1270         const u32 *of_serial_dir32;
1271         u32 val;
1272         int i, ret = 0;
1273 
1274         if (pdev->dev.platform_data) {
1275                 pdata = pdev->dev.platform_data;
1276                 return pdata;
1277         } else if (match) {
1278                 pdata = (struct davinci_mcasp_pdata*) match->data;
1279         } else {
1280                 /* control shouldn't reach here. something is wrong */
1281                 ret = -EINVAL;
1282                 goto nodata;
1283         }
1284 
1285         ret = of_property_read_u32(np, "op-mode", &val);
1286         if (ret >= 0)
1287                 pdata->op_mode = val;
1288 
1289         ret = of_property_read_u32(np, "tdm-slots", &val);
1290         if (ret >= 0) {
1291                 if (val < 2 || val > 32) {
1292                         dev_err(&pdev->dev,
1293                                 "tdm-slots must be in rage [2-32]\n");
1294                         ret = -EINVAL;
1295                         goto nodata;
1296                 }
1297 
1298                 pdata->tdm_slots = val;
1299         }
1300 
1301         of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1302         val /= sizeof(u32);
1303         if (of_serial_dir32) {
1304                 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1305                                                  (sizeof(*of_serial_dir) * val),
1306                                                  GFP_KERNEL);
1307                 if (!of_serial_dir) {
1308                         ret = -ENOMEM;
1309                         goto nodata;
1310                 }
1311 
1312                 for (i = 0; i < val; i++)
1313                         of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1314 
1315                 pdata->num_serializer = val;
1316                 pdata->serial_dir = of_serial_dir;
1317         }
1318 
1319         ret = of_property_match_string(np, "dma-names", "tx");
1320         if (ret < 0)
1321                 goto nodata;
1322 
1323         ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1324                                          &dma_spec);
1325         if (ret < 0)
1326                 goto nodata;
1327 
1328         pdata->tx_dma_channel = dma_spec.args[0];
1329 
1330         /* RX is not valid in DIT mode */
1331         if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1332                 ret = of_property_match_string(np, "dma-names", "rx");
1333                 if (ret < 0)
1334                         goto nodata;
1335 
1336                 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1337                                                  &dma_spec);
1338                 if (ret < 0)
1339                         goto nodata;
1340 
1341                 pdata->rx_dma_channel = dma_spec.args[0];
1342         }
1343 
1344         ret = of_property_read_u32(np, "tx-num-evt", &val);
1345         if (ret >= 0)
1346                 pdata->txnumevt = val;
1347 
1348         ret = of_property_read_u32(np, "rx-num-evt", &val);
1349         if (ret >= 0)
1350                 pdata->rxnumevt = val;
1351 
1352         ret = of_property_read_u32(np, "sram-size-playback", &val);
1353         if (ret >= 0)
1354                 pdata->sram_size_playback = val;
1355 
1356         ret = of_property_read_u32(np, "sram-size-capture", &val);
1357         if (ret >= 0)
1358                 pdata->sram_size_capture = val;
1359 
1360         return  pdata;
1361 
1362 nodata:
1363         if (ret < 0) {
1364                 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1365                         ret);
1366                 pdata = NULL;
1367         }
1368         return  pdata;
1369 }
1370 
1371 static int davinci_mcasp_probe(struct platform_device *pdev)
1372 {
1373         struct davinci_pcm_dma_params *dma_params;
1374         struct snd_dmaengine_dai_dma_data *dma_data;
1375         struct resource *mem, *ioarea, *res, *dat;
1376         struct davinci_mcasp_pdata *pdata;
1377         struct davinci_mcasp *mcasp;
1378         char *irq_name;
1379         int irq;
1380         int ret;
1381 
1382         if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1383                 dev_err(&pdev->dev, "No platform data supplied\n");
1384                 return -EINVAL;
1385         }
1386 
1387         mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1388                            GFP_KERNEL);
1389         if (!mcasp)
1390                 return  -ENOMEM;
1391 
1392         pdata = davinci_mcasp_set_pdata_from_of(pdev);
1393         if (!pdata) {
1394                 dev_err(&pdev->dev, "no platform data\n");
1395                 return -EINVAL;
1396         }
1397 
1398         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1399         if (!mem) {
1400                 dev_warn(mcasp->dev,
1401                          "\"mpu\" mem resource not found, using index 0\n");
1402                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1403                 if (!mem) {
1404                         dev_err(&pdev->dev, "no mem resource?\n");
1405                         return -ENODEV;
1406                 }
1407         }
1408 
1409         ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1410                         resource_size(mem), pdev->name);
1411         if (!ioarea) {
1412                 dev_err(&pdev->dev, "Audio region already claimed\n");
1413                 return -EBUSY;
1414         }
1415 
1416         pm_runtime_enable(&pdev->dev);
1417 
1418         ret = pm_runtime_get_sync(&pdev->dev);
1419         if (IS_ERR_VALUE(ret)) {
1420                 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1421                 pm_runtime_disable(&pdev->dev);
1422                 return ret;
1423         }
1424 
1425         mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1426         if (!mcasp->base) {
1427                 dev_err(&pdev->dev, "ioremap failed\n");
1428                 ret = -ENOMEM;
1429                 goto err;
1430         }
1431 
1432         mcasp->op_mode = pdata->op_mode;
1433         /* sanity check for tdm slots parameter */
1434         if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1435                 if (pdata->tdm_slots < 2) {
1436                         dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1437                                 pdata->tdm_slots);
1438                         mcasp->tdm_slots = 2;
1439                 } else if (pdata->tdm_slots > 32) {
1440                         dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1441                                 pdata->tdm_slots);
1442                         mcasp->tdm_slots = 32;
1443                 } else {
1444                         mcasp->tdm_slots = pdata->tdm_slots;
1445                 }
1446         }
1447 
1448         mcasp->num_serializer = pdata->num_serializer;
1449 #ifdef CONFIG_PM_SLEEP
1450         mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1451                                         sizeof(u32) * mcasp->num_serializer,
1452                                         GFP_KERNEL);
1453 #endif
1454         mcasp->serial_dir = pdata->serial_dir;
1455         mcasp->version = pdata->version;
1456         mcasp->txnumevt = pdata->txnumevt;
1457         mcasp->rxnumevt = pdata->rxnumevt;
1458 
1459         mcasp->dev = &pdev->dev;
1460 
1461         irq = platform_get_irq_byname(pdev, "common");
1462         if (irq >= 0) {
1463                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common\n",
1464                                           dev_name(&pdev->dev));
1465                 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1466                                                 davinci_mcasp_common_irq_handler,
1467                                                 IRQF_ONESHOT | IRQF_SHARED,
1468                                                 irq_name, mcasp);
1469                 if (ret) {
1470                         dev_err(&pdev->dev, "common IRQ request failed\n");
1471                         goto err;
1472                 }
1473 
1474                 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1475                 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1476         }
1477 
1478         irq = platform_get_irq_byname(pdev, "rx");
1479         if (irq >= 0) {
1480                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx\n",
1481                                           dev_name(&pdev->dev));
1482                 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1483                                                 davinci_mcasp_rx_irq_handler,
1484                                                 IRQF_ONESHOT, irq_name, mcasp);
1485                 if (ret) {
1486                         dev_err(&pdev->dev, "RX IRQ request failed\n");
1487                         goto err;
1488                 }
1489 
1490                 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1491         }
1492 
1493         irq = platform_get_irq_byname(pdev, "tx");
1494         if (irq >= 0) {
1495                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx\n",
1496                                           dev_name(&pdev->dev));
1497                 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1498                                                 davinci_mcasp_tx_irq_handler,
1499                                                 IRQF_ONESHOT, irq_name, mcasp);
1500                 if (ret) {
1501                         dev_err(&pdev->dev, "TX IRQ request failed\n");
1502                         goto err;
1503                 }
1504 
1505                 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1506         }
1507 
1508         dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1509         if (dat)
1510                 mcasp->dat_port = true;
1511 
1512         dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1513         dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1514         dma_params->asp_chan_q = pdata->asp_chan_q;
1515         dma_params->ram_chan_q = pdata->ram_chan_q;
1516         dma_params->sram_pool = pdata->sram_pool;
1517         dma_params->sram_size = pdata->sram_size_playback;
1518         if (dat)
1519                 dma_params->dma_addr = dat->start;
1520         else
1521                 dma_params->dma_addr = mem->start + pdata->tx_dma_offset;
1522 
1523         /* Unconditional dmaengine stuff */
1524         dma_data->addr = dma_params->dma_addr;
1525 
1526         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1527         if (res)
1528                 dma_params->channel = res->start;
1529         else
1530                 dma_params->channel = pdata->tx_dma_channel;
1531 
1532         /* dmaengine filter data for DT and non-DT boot */
1533         if (pdev->dev.of_node)
1534                 dma_data->filter_data = "tx";
1535         else
1536                 dma_data->filter_data = &dma_params->channel;
1537 
1538         /* RX is not valid in DIT mode */
1539         if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1540                 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1541                 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1542                 dma_params->asp_chan_q = pdata->asp_chan_q;
1543                 dma_params->ram_chan_q = pdata->ram_chan_q;
1544                 dma_params->sram_pool = pdata->sram_pool;
1545                 dma_params->sram_size = pdata->sram_size_capture;
1546                 if (dat)
1547                         dma_params->dma_addr = dat->start;
1548                 else
1549                         dma_params->dma_addr = mem->start + pdata->rx_dma_offset;
1550 
1551                 /* Unconditional dmaengine stuff */
1552                 dma_data->addr = dma_params->dma_addr;
1553 
1554                 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1555                 if (res)
1556                         dma_params->channel = res->start;
1557                 else
1558                         dma_params->channel = pdata->rx_dma_channel;
1559 
1560                 /* dmaengine filter data for DT and non-DT boot */
1561                 if (pdev->dev.of_node)
1562                         dma_data->filter_data = "rx";
1563                 else
1564                         dma_data->filter_data = &dma_params->channel;
1565         }
1566 
1567         if (mcasp->version < MCASP_VERSION_3) {
1568                 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1569                 /* dma_params->dma_addr is pointing to the data port address */
1570                 mcasp->dat_port = true;
1571         } else {
1572                 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1573         }
1574 
1575         dev_set_drvdata(&pdev->dev, mcasp);
1576 
1577         mcasp_reparent_fck(pdev);
1578 
1579         ret = devm_snd_soc_register_component(&pdev->dev,
1580                                         &davinci_mcasp_component,
1581                                         &davinci_mcasp_dai[pdata->op_mode], 1);
1582 
1583         if (ret != 0)
1584                 goto err;
1585 
1586         switch (mcasp->version) {
1587 #if IS_BUILTIN(CONFIG_SND_DAVINCI_SOC) || \
1588         (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1589          IS_MODULE(CONFIG_SND_DAVINCI_SOC))
1590         case MCASP_VERSION_1:
1591         case MCASP_VERSION_2:
1592                 ret = davinci_soc_platform_register(&pdev->dev);
1593                 break;
1594 #endif
1595 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1596         (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1597          IS_MODULE(CONFIG_SND_EDMA_SOC))
1598         case MCASP_VERSION_3:
1599                 ret = edma_pcm_platform_register(&pdev->dev);
1600                 break;
1601 #endif
1602 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1603         (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1604          IS_MODULE(CONFIG_SND_OMAP_SOC))
1605         case MCASP_VERSION_4:
1606                 ret = omap_pcm_platform_register(&pdev->dev);
1607                 break;
1608 #endif
1609         default:
1610                 dev_err(&pdev->dev, "Invalid McASP version: %d\n",
1611                         mcasp->version);
1612                 ret = -EINVAL;
1613                 break;
1614         }
1615 
1616         if (ret) {
1617                 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1618                 goto err;
1619         }
1620 
1621         return 0;
1622 
1623 err:
1624         pm_runtime_put_sync(&pdev->dev);
1625         pm_runtime_disable(&pdev->dev);
1626         return ret;
1627 }
1628 
1629 static int davinci_mcasp_remove(struct platform_device *pdev)
1630 {
1631         pm_runtime_put_sync(&pdev->dev);
1632         pm_runtime_disable(&pdev->dev);
1633 
1634         return 0;
1635 }
1636 
1637 static struct platform_driver davinci_mcasp_driver = {
1638         .probe          = davinci_mcasp_probe,
1639         .remove         = davinci_mcasp_remove,
1640         .driver         = {
1641                 .name   = "davinci-mcasp",
1642                 .of_match_table = mcasp_dt_ids,
1643         },
1644 };
1645 
1646 module_platform_driver(davinci_mcasp_driver);
1647 
1648 MODULE_AUTHOR("Steve Chen");
1649 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1650 MODULE_LICENSE("GPL");
1651 

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