Version:  2.6.34 2.6.35 2.6.36 2.6.37 2.6.38 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14

Linux/sound/soc/davinci/davinci-mcasp.c

  1 /*
  2  * ALSA SoC McASP Audio Layer for TI DAVINCI processor
  3  *
  4  * Multi-channel Audio Serial Port Driver
  5  *
  6  * Author: Nirmal Pandey <n-pandey@ti.com>,
  7  *         Suresh Rajashekara <suresh.r@ti.com>
  8  *         Steve Chen <schen@.mvista.com>
  9  *
 10  * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
 11  * Copyright:   (C) 2009  Texas Instruments, India
 12  *
 13  * This program is free software; you can redistribute it and/or modify
 14  * it under the terms of the GNU General Public License version 2 as
 15  * published by the Free Software Foundation.
 16  */
 17 
 18 #include <linux/init.h>
 19 #include <linux/module.h>
 20 #include <linux/device.h>
 21 #include <linux/slab.h>
 22 #include <linux/delay.h>
 23 #include <linux/io.h>
 24 #include <linux/clk.h>
 25 #include <linux/pm_runtime.h>
 26 #include <linux/of.h>
 27 #include <linux/of_platform.h>
 28 #include <linux/of_device.h>
 29 
 30 #include <sound/core.h>
 31 #include <sound/pcm.h>
 32 #include <sound/pcm_params.h>
 33 #include <sound/initval.h>
 34 #include <sound/soc.h>
 35 #include <sound/dmaengine_pcm.h>
 36 
 37 #include "davinci-pcm.h"
 38 #include "davinci-mcasp.h"
 39 
 40 struct davinci_mcasp {
 41         struct davinci_pcm_dma_params dma_params[2];
 42         struct snd_dmaengine_dai_dma_data dma_data[2];
 43         void __iomem *base;
 44         u32 fifo_base;
 45         struct device *dev;
 46 
 47         /* McASP specific data */
 48         int     tdm_slots;
 49         u8      op_mode;
 50         u8      num_serializer;
 51         u8      *serial_dir;
 52         u8      version;
 53         u16     bclk_lrclk_ratio;
 54         int     streams;
 55 
 56         /* McASP FIFO related */
 57         u8      txnumevt;
 58         u8      rxnumevt;
 59 
 60         bool    dat_port;
 61 
 62 #ifdef CONFIG_PM_SLEEP
 63         struct {
 64                 u32     txfmtctl;
 65                 u32     rxfmtctl;
 66                 u32     txfmt;
 67                 u32     rxfmt;
 68                 u32     aclkxctl;
 69                 u32     aclkrctl;
 70                 u32     pdir;
 71         } context;
 72 #endif
 73 };
 74 
 75 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
 76                                   u32 val)
 77 {
 78         void __iomem *reg = mcasp->base + offset;
 79         __raw_writel(__raw_readl(reg) | val, reg);
 80 }
 81 
 82 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
 83                                   u32 val)
 84 {
 85         void __iomem *reg = mcasp->base + offset;
 86         __raw_writel((__raw_readl(reg) & ~(val)), reg);
 87 }
 88 
 89 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
 90                                   u32 val, u32 mask)
 91 {
 92         void __iomem *reg = mcasp->base + offset;
 93         __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
 94 }
 95 
 96 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
 97                                  u32 val)
 98 {
 99         __raw_writel(val, mcasp->base + offset);
100 }
101 
102 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
103 {
104         return (u32)__raw_readl(mcasp->base + offset);
105 }
106 
107 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
108 {
109         int i = 0;
110 
111         mcasp_set_bits(mcasp, ctl_reg, val);
112 
113         /* programming GBLCTL needs to read back from GBLCTL and verfiy */
114         /* loop count is to avoid the lock-up */
115         for (i = 0; i < 1000; i++) {
116                 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
117                         break;
118         }
119 
120         if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
121                 printk(KERN_ERR "GBLCTL write error\n");
122 }
123 
124 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
125 {
126         u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
127         u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
128 
129         return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
130 }
131 
132 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
133 {
134         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
135         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
136 
137         /*
138          * When ASYNC == 0 the transmit and receive sections operate
139          * synchronously from the transmit clock and frame sync. We need to make
140          * sure that the TX signlas are enabled when starting reception.
141          */
142         if (mcasp_is_synchronous(mcasp)) {
143                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
144                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
145         }
146 
147         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
148         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
149 
150         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
151         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
152         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
153 
154         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
155         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
156 
157         if (mcasp_is_synchronous(mcasp))
158                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
159 }
160 
161 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
162 {
163         u8 offset = 0, i;
164         u32 cnt;
165 
166         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
167         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
168         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
169         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
170 
171         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
172         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
173         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
174         for (i = 0; i < mcasp->num_serializer; i++) {
175                 if (mcasp->serial_dir[i] == TX_MODE) {
176                         offset = i;
177                         break;
178                 }
179         }
180 
181         /* wait for TX ready */
182         cnt = 0;
183         while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
184                  TXSTATE) && (cnt < 100000))
185                 cnt++;
186 
187         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
188 }
189 
190 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
191 {
192         u32 reg;
193 
194         mcasp->streams++;
195 
196         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
197                 if (mcasp->txnumevt) {  /* enable FIFO */
198                         reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
199                         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
200                         mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
201                 }
202                 mcasp_start_tx(mcasp);
203         } else {
204                 if (mcasp->rxnumevt) {  /* enable FIFO */
205                         reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
206                         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
207                         mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
208                 }
209                 mcasp_start_rx(mcasp);
210         }
211 }
212 
213 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
214 {
215         /*
216          * In synchronous mode stop the TX clocks if no other stream is
217          * running
218          */
219         if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
220                 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
221 
222         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
223         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
224 }
225 
226 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
227 {
228         u32 val = 0;
229 
230         /*
231          * In synchronous mode keep TX clocks running if the capture stream is
232          * still running.
233          */
234         if (mcasp_is_synchronous(mcasp) && mcasp->streams)
235                 val =  TXHCLKRST | TXCLKRST | TXFSRST;
236 
237         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
238         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
239 }
240 
241 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
242 {
243         u32 reg;
244 
245         mcasp->streams--;
246 
247         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
248                 if (mcasp->txnumevt) {  /* disable FIFO */
249                         reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
250                         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
251                 }
252                 mcasp_stop_tx(mcasp);
253         } else {
254                 if (mcasp->rxnumevt) {  /* disable FIFO */
255                         reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
256                         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
257                 }
258                 mcasp_stop_rx(mcasp);
259         }
260 }
261 
262 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
263                                          unsigned int fmt)
264 {
265         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
266         int ret = 0;
267 
268         pm_runtime_get_sync(mcasp->dev);
269         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
270         case SND_SOC_DAIFMT_DSP_B:
271         case SND_SOC_DAIFMT_AC97:
272                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
273                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
274                 break;
275         default:
276                 /* configure a full-word SYNC pulse (LRCLK) */
277                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
278                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
279 
280                 /* make 1st data bit occur one ACLK cycle after the frame sync */
281                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
282                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
283                 break;
284         }
285 
286         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
287         case SND_SOC_DAIFMT_CBS_CFS:
288                 /* codec is clock and frame slave */
289                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
290                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
291 
292                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
293                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
294 
295                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
296                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
297                 break;
298         case SND_SOC_DAIFMT_CBM_CFS:
299                 /* codec is clock master and frame slave */
300                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
301                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
302 
303                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
304                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
305 
306                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
307                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
308                 break;
309         case SND_SOC_DAIFMT_CBM_CFM:
310                 /* codec is clock and frame master */
311                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
312                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
313 
314                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
315                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
316 
317                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
318                                ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
319                 break;
320 
321         default:
322                 ret = -EINVAL;
323                 goto out;
324         }
325 
326         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
327         case SND_SOC_DAIFMT_IB_NF:
328                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
329                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
330 
331                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
332                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
333                 break;
334 
335         case SND_SOC_DAIFMT_NB_IF:
336                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
337                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
338 
339                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
340                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
341                 break;
342 
343         case SND_SOC_DAIFMT_IB_IF:
344                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
345                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
346 
347                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
348                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
349                 break;
350 
351         case SND_SOC_DAIFMT_NB_NF:
352                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
353                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
354 
355                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
356                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
357                 break;
358 
359         default:
360                 ret = -EINVAL;
361                 break;
362         }
363 out:
364         pm_runtime_put_sync(mcasp->dev);
365         return ret;
366 }
367 
368 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
369 {
370         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
371 
372         switch (div_id) {
373         case 0:         /* MCLK divider */
374                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
375                                AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
376                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
377                                AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
378                 break;
379 
380         case 1:         /* BCLK divider */
381                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
382                                ACLKXDIV(div - 1), ACLKXDIV_MASK);
383                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
384                                ACLKRDIV(div - 1), ACLKRDIV_MASK);
385                 break;
386 
387         case 2:         /* BCLK/LRCLK ratio */
388                 mcasp->bclk_lrclk_ratio = div;
389                 break;
390 
391         default:
392                 return -EINVAL;
393         }
394 
395         return 0;
396 }
397 
398 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
399                                     unsigned int freq, int dir)
400 {
401         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
402 
403         if (dir == SND_SOC_CLOCK_OUT) {
404                 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
405                 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
406                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
407         } else {
408                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
409                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
410                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
411         }
412 
413         return 0;
414 }
415 
416 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
417                                        int word_length)
418 {
419         u32 fmt;
420         u32 tx_rotate = (word_length / 4) & 0x7;
421         u32 rx_rotate = (32 - word_length) / 4;
422         u32 mask = (1ULL << word_length) - 1;
423 
424         /*
425          * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
426          * callback, take it into account here. That allows us to for example
427          * send 32 bits per channel to the codec, while only 16 of them carry
428          * audio payload.
429          * The clock ratio is given for a full period of data (for I2S format
430          * both left and right channels), so it has to be divided by number of
431          * tdm-slots (for I2S - divided by 2).
432          */
433         if (mcasp->bclk_lrclk_ratio)
434                 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
435 
436         /* mapping of the XSSZ bit-field as described in the datasheet */
437         fmt = (word_length >> 1) - 1;
438 
439         if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
440                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
441                                RXSSZ(0x0F));
442                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
443                                TXSSZ(0x0F));
444                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
445                                TXROT(7));
446                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
447                                RXROT(7));
448                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
449         }
450 
451         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
452 
453         return 0;
454 }
455 
456 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
457                                     int channels)
458 {
459         int i;
460         u8 tx_ser = 0;
461         u8 rx_ser = 0;
462         u8 ser;
463         u8 slots = mcasp->tdm_slots;
464         u8 max_active_serializers = (channels + slots - 1) / slots;
465         u32 reg;
466         /* Default configuration */
467         if (mcasp->version != MCASP_VERSION_4)
468                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
469 
470         /* All PINS as McASP */
471         mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
472 
473         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
474                 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
475                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
476         } else {
477                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
478                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
479         }
480 
481         for (i = 0; i < mcasp->num_serializer; i++) {
482                 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
483                                mcasp->serial_dir[i]);
484                 if (mcasp->serial_dir[i] == TX_MODE &&
485                                         tx_ser < max_active_serializers) {
486                         mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
487                         tx_ser++;
488                 } else if (mcasp->serial_dir[i] == RX_MODE &&
489                                         rx_ser < max_active_serializers) {
490                         mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
491                         rx_ser++;
492                 } else {
493                         mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
494                                        SRMOD_INACTIVE, SRMOD_MASK);
495                 }
496         }
497 
498         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
499                 ser = tx_ser;
500         else
501                 ser = rx_ser;
502 
503         if (ser < max_active_serializers) {
504                 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
505                         "enabled in mcasp (%d)\n", channels, ser * slots);
506                 return -EINVAL;
507         }
508 
509         if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
510                 if (mcasp->txnumevt * tx_ser > 64)
511                         mcasp->txnumevt = 1;
512 
513                 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
514                 mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK);
515                 mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8),
516                                NUMEVT_MASK);
517         }
518 
519         if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
520                 if (mcasp->rxnumevt * rx_ser > 64)
521                         mcasp->rxnumevt = 1;
522 
523                 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
524                 mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK);
525                 mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8),
526                                NUMEVT_MASK);
527         }
528 
529         return 0;
530 }
531 
532 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
533 {
534         int i, active_slots;
535         u32 mask = 0;
536         u32 busel = 0;
537 
538         if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
539                 dev_err(mcasp->dev, "tdm slot %d not supported\n",
540                         mcasp->tdm_slots);
541                 return -EINVAL;
542         }
543 
544         active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
545         for (i = 0; i < active_slots; i++)
546                 mask |= (1 << i);
547 
548         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
549 
550         if (!mcasp->dat_port)
551                 busel = TXSEL;
552 
553         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
554         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
555         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
556                        FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
557 
558         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
559         mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
560         mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
561                        FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
562 
563         return 0;
564 }
565 
566 /* S/PDIF */
567 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
568 {
569         /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
570            and LSB first */
571         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
572 
573         /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
574         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
575 
576         /* Set the TX tdm : for all the slots */
577         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
578 
579         /* Set the TX clock controls : div = 1 and internal */
580         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
581 
582         mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
583 
584         /* Only 44100 and 48000 are valid, both have the same setting */
585         mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
586 
587         /* Enable the DIT */
588         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
589 
590         return 0;
591 }
592 
593 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
594                                         struct snd_pcm_hw_params *params,
595                                         struct snd_soc_dai *cpu_dai)
596 {
597         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
598         struct davinci_pcm_dma_params *dma_params =
599                                         &mcasp->dma_params[substream->stream];
600         struct snd_dmaengine_dai_dma_data *dma_data =
601                                         &mcasp->dma_data[substream->stream];
602         int word_length;
603         u8 fifo_level;
604         u8 slots = mcasp->tdm_slots;
605         u8 active_serializers;
606         int channels;
607         int ret;
608         struct snd_interval *pcm_channels = hw_param_interval(params,
609                                         SNDRV_PCM_HW_PARAM_CHANNELS);
610         channels = pcm_channels->min;
611 
612         active_serializers = (channels + slots - 1) / slots;
613 
614         if (mcasp_common_hw_param(mcasp, substream->stream, channels) == -EINVAL)
615                 return -EINVAL;
616         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
617                 fifo_level = mcasp->txnumevt * active_serializers;
618         else
619                 fifo_level = mcasp->rxnumevt * active_serializers;
620 
621         if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
622                 ret = mcasp_dit_hw_param(mcasp);
623         else
624                 ret = mcasp_i2s_hw_param(mcasp, substream->stream);
625 
626         if (ret)
627                 return ret;
628 
629         switch (params_format(params)) {
630         case SNDRV_PCM_FORMAT_U8:
631         case SNDRV_PCM_FORMAT_S8:
632                 dma_params->data_type = 1;
633                 word_length = 8;
634                 break;
635 
636         case SNDRV_PCM_FORMAT_U16_LE:
637         case SNDRV_PCM_FORMAT_S16_LE:
638                 dma_params->data_type = 2;
639                 word_length = 16;
640                 break;
641 
642         case SNDRV_PCM_FORMAT_U24_3LE:
643         case SNDRV_PCM_FORMAT_S24_3LE:
644                 dma_params->data_type = 3;
645                 word_length = 24;
646                 break;
647 
648         case SNDRV_PCM_FORMAT_U24_LE:
649         case SNDRV_PCM_FORMAT_S24_LE:
650         case SNDRV_PCM_FORMAT_U32_LE:
651         case SNDRV_PCM_FORMAT_S32_LE:
652                 dma_params->data_type = 4;
653                 word_length = 32;
654                 break;
655 
656         default:
657                 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
658                 return -EINVAL;
659         }
660 
661         if (mcasp->version == MCASP_VERSION_2 && !fifo_level)
662                 dma_params->acnt = 4;
663         else
664                 dma_params->acnt = dma_params->data_type;
665 
666         dma_params->fifo_level = fifo_level;
667         dma_data->maxburst = fifo_level;
668 
669         davinci_config_channel_size(mcasp, word_length);
670 
671         return 0;
672 }
673 
674 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
675                                      int cmd, struct snd_soc_dai *cpu_dai)
676 {
677         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
678         int ret = 0;
679 
680         switch (cmd) {
681         case SNDRV_PCM_TRIGGER_RESUME:
682         case SNDRV_PCM_TRIGGER_START:
683         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
684                 davinci_mcasp_start(mcasp, substream->stream);
685                 break;
686         case SNDRV_PCM_TRIGGER_SUSPEND:
687         case SNDRV_PCM_TRIGGER_STOP:
688         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
689                 davinci_mcasp_stop(mcasp, substream->stream);
690                 break;
691 
692         default:
693                 ret = -EINVAL;
694         }
695 
696         return ret;
697 }
698 
699 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
700                                  struct snd_soc_dai *dai)
701 {
702         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
703 
704         if (mcasp->version == MCASP_VERSION_4)
705                 snd_soc_dai_set_dma_data(dai, substream,
706                                         &mcasp->dma_data[substream->stream]);
707         else
708                 snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params);
709 
710         return 0;
711 }
712 
713 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
714         .startup        = davinci_mcasp_startup,
715         .trigger        = davinci_mcasp_trigger,
716         .hw_params      = davinci_mcasp_hw_params,
717         .set_fmt        = davinci_mcasp_set_dai_fmt,
718         .set_clkdiv     = davinci_mcasp_set_clkdiv,
719         .set_sysclk     = davinci_mcasp_set_sysclk,
720 };
721 
722 #define DAVINCI_MCASP_RATES     SNDRV_PCM_RATE_8000_192000
723 
724 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
725                                 SNDRV_PCM_FMTBIT_U8 | \
726                                 SNDRV_PCM_FMTBIT_S16_LE | \
727                                 SNDRV_PCM_FMTBIT_U16_LE | \
728                                 SNDRV_PCM_FMTBIT_S24_LE | \
729                                 SNDRV_PCM_FMTBIT_U24_LE | \
730                                 SNDRV_PCM_FMTBIT_S24_3LE | \
731                                 SNDRV_PCM_FMTBIT_U24_3LE | \
732                                 SNDRV_PCM_FMTBIT_S32_LE | \
733                                 SNDRV_PCM_FMTBIT_U32_LE)
734 
735 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
736         {
737                 .name           = "davinci-mcasp.0",
738                 .playback       = {
739                         .channels_min   = 2,
740                         .channels_max   = 32 * 16,
741                         .rates          = DAVINCI_MCASP_RATES,
742                         .formats        = DAVINCI_MCASP_PCM_FMTS,
743                 },
744                 .capture        = {
745                         .channels_min   = 2,
746                         .channels_max   = 32 * 16,
747                         .rates          = DAVINCI_MCASP_RATES,
748                         .formats        = DAVINCI_MCASP_PCM_FMTS,
749                 },
750                 .ops            = &davinci_mcasp_dai_ops,
751 
752         },
753         {
754                 .name           = "davinci-mcasp.1",
755                 .playback       = {
756                         .channels_min   = 1,
757                         .channels_max   = 384,
758                         .rates          = DAVINCI_MCASP_RATES,
759                         .formats        = DAVINCI_MCASP_PCM_FMTS,
760                 },
761                 .ops            = &davinci_mcasp_dai_ops,
762         },
763 
764 };
765 
766 static const struct snd_soc_component_driver davinci_mcasp_component = {
767         .name           = "davinci-mcasp",
768 };
769 
770 /* Some HW specific values and defaults. The rest is filled in from DT. */
771 static struct snd_platform_data dm646x_mcasp_pdata = {
772         .tx_dma_offset = 0x400,
773         .rx_dma_offset = 0x400,
774         .asp_chan_q = EVENTQ_0,
775         .version = MCASP_VERSION_1,
776 };
777 
778 static struct snd_platform_data da830_mcasp_pdata = {
779         .tx_dma_offset = 0x2000,
780         .rx_dma_offset = 0x2000,
781         .asp_chan_q = EVENTQ_0,
782         .version = MCASP_VERSION_2,
783 };
784 
785 static struct snd_platform_data am33xx_mcasp_pdata = {
786         .tx_dma_offset = 0,
787         .rx_dma_offset = 0,
788         .asp_chan_q = EVENTQ_0,
789         .version = MCASP_VERSION_3,
790 };
791 
792 static struct snd_platform_data dra7_mcasp_pdata = {
793         .tx_dma_offset = 0x200,
794         .rx_dma_offset = 0x284,
795         .asp_chan_q = EVENTQ_0,
796         .version = MCASP_VERSION_4,
797 };
798 
799 static const struct of_device_id mcasp_dt_ids[] = {
800         {
801                 .compatible = "ti,dm646x-mcasp-audio",
802                 .data = &dm646x_mcasp_pdata,
803         },
804         {
805                 .compatible = "ti,da830-mcasp-audio",
806                 .data = &da830_mcasp_pdata,
807         },
808         {
809                 .compatible = "ti,am33xx-mcasp-audio",
810                 .data = &am33xx_mcasp_pdata,
811         },
812         {
813                 .compatible = "ti,dra7-mcasp-audio",
814                 .data = &dra7_mcasp_pdata,
815         },
816         { /* sentinel */ }
817 };
818 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
819 
820 static int mcasp_reparent_fck(struct platform_device *pdev)
821 {
822         struct device_node *node = pdev->dev.of_node;
823         struct clk *gfclk, *parent_clk;
824         const char *parent_name;
825         int ret;
826 
827         if (!node)
828                 return 0;
829 
830         parent_name = of_get_property(node, "fck_parent", NULL);
831         if (!parent_name)
832                 return 0;
833 
834         gfclk = clk_get(&pdev->dev, "fck");
835         if (IS_ERR(gfclk)) {
836                 dev_err(&pdev->dev, "failed to get fck\n");
837                 return PTR_ERR(gfclk);
838         }
839 
840         parent_clk = clk_get(NULL, parent_name);
841         if (IS_ERR(parent_clk)) {
842                 dev_err(&pdev->dev, "failed to get parent clock\n");
843                 ret = PTR_ERR(parent_clk);
844                 goto err1;
845         }
846 
847         ret = clk_set_parent(gfclk, parent_clk);
848         if (ret) {
849                 dev_err(&pdev->dev, "failed to reparent fck\n");
850                 goto err2;
851         }
852 
853 err2:
854         clk_put(parent_clk);
855 err1:
856         clk_put(gfclk);
857         return ret;
858 }
859 
860 static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
861                                                 struct platform_device *pdev)
862 {
863         struct device_node *np = pdev->dev.of_node;
864         struct snd_platform_data *pdata = NULL;
865         const struct of_device_id *match =
866                         of_match_device(mcasp_dt_ids, &pdev->dev);
867         struct of_phandle_args dma_spec;
868 
869         const u32 *of_serial_dir32;
870         u32 val;
871         int i, ret = 0;
872 
873         if (pdev->dev.platform_data) {
874                 pdata = pdev->dev.platform_data;
875                 return pdata;
876         } else if (match) {
877                 pdata = (struct snd_platform_data *) match->data;
878         } else {
879                 /* control shouldn't reach here. something is wrong */
880                 ret = -EINVAL;
881                 goto nodata;
882         }
883 
884         ret = of_property_read_u32(np, "op-mode", &val);
885         if (ret >= 0)
886                 pdata->op_mode = val;
887 
888         ret = of_property_read_u32(np, "tdm-slots", &val);
889         if (ret >= 0) {
890                 if (val < 2 || val > 32) {
891                         dev_err(&pdev->dev,
892                                 "tdm-slots must be in rage [2-32]\n");
893                         ret = -EINVAL;
894                         goto nodata;
895                 }
896 
897                 pdata->tdm_slots = val;
898         }
899 
900         of_serial_dir32 = of_get_property(np, "serial-dir", &val);
901         val /= sizeof(u32);
902         if (of_serial_dir32) {
903                 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
904                                                  (sizeof(*of_serial_dir) * val),
905                                                  GFP_KERNEL);
906                 if (!of_serial_dir) {
907                         ret = -ENOMEM;
908                         goto nodata;
909                 }
910 
911                 for (i = 0; i < val; i++)
912                         of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
913 
914                 pdata->num_serializer = val;
915                 pdata->serial_dir = of_serial_dir;
916         }
917 
918         ret = of_property_match_string(np, "dma-names", "tx");
919         if (ret < 0)
920                 goto nodata;
921 
922         ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
923                                          &dma_spec);
924         if (ret < 0)
925                 goto nodata;
926 
927         pdata->tx_dma_channel = dma_spec.args[0];
928 
929         ret = of_property_match_string(np, "dma-names", "rx");
930         if (ret < 0)
931                 goto nodata;
932 
933         ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
934                                          &dma_spec);
935         if (ret < 0)
936                 goto nodata;
937 
938         pdata->rx_dma_channel = dma_spec.args[0];
939 
940         ret = of_property_read_u32(np, "tx-num-evt", &val);
941         if (ret >= 0)
942                 pdata->txnumevt = val;
943 
944         ret = of_property_read_u32(np, "rx-num-evt", &val);
945         if (ret >= 0)
946                 pdata->rxnumevt = val;
947 
948         ret = of_property_read_u32(np, "sram-size-playback", &val);
949         if (ret >= 0)
950                 pdata->sram_size_playback = val;
951 
952         ret = of_property_read_u32(np, "sram-size-capture", &val);
953         if (ret >= 0)
954                 pdata->sram_size_capture = val;
955 
956         return  pdata;
957 
958 nodata:
959         if (ret < 0) {
960                 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
961                         ret);
962                 pdata = NULL;
963         }
964         return  pdata;
965 }
966 
967 static int davinci_mcasp_probe(struct platform_device *pdev)
968 {
969         struct davinci_pcm_dma_params *dma_data;
970         struct resource *mem, *ioarea, *res, *dat;
971         struct snd_platform_data *pdata;
972         struct davinci_mcasp *mcasp;
973         int ret;
974 
975         if (!pdev->dev.platform_data && !pdev->dev.of_node) {
976                 dev_err(&pdev->dev, "No platform data supplied\n");
977                 return -EINVAL;
978         }
979 
980         mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
981                            GFP_KERNEL);
982         if (!mcasp)
983                 return  -ENOMEM;
984 
985         pdata = davinci_mcasp_set_pdata_from_of(pdev);
986         if (!pdata) {
987                 dev_err(&pdev->dev, "no platform data\n");
988                 return -EINVAL;
989         }
990 
991         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
992         if (!mem) {
993                 dev_warn(mcasp->dev,
994                          "\"mpu\" mem resource not found, using index 0\n");
995                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
996                 if (!mem) {
997                         dev_err(&pdev->dev, "no mem resource?\n");
998                         return -ENODEV;
999                 }
1000         }
1001 
1002         ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1003                         resource_size(mem), pdev->name);
1004         if (!ioarea) {
1005                 dev_err(&pdev->dev, "Audio region already claimed\n");
1006                 return -EBUSY;
1007         }
1008 
1009         pm_runtime_enable(&pdev->dev);
1010 
1011         ret = pm_runtime_get_sync(&pdev->dev);
1012         if (IS_ERR_VALUE(ret)) {
1013                 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1014                 return ret;
1015         }
1016 
1017         mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1018         if (!mcasp->base) {
1019                 dev_err(&pdev->dev, "ioremap failed\n");
1020                 ret = -ENOMEM;
1021                 goto err_release_clk;
1022         }
1023 
1024         mcasp->op_mode = pdata->op_mode;
1025         mcasp->tdm_slots = pdata->tdm_slots;
1026         mcasp->num_serializer = pdata->num_serializer;
1027         mcasp->serial_dir = pdata->serial_dir;
1028         mcasp->version = pdata->version;
1029         mcasp->txnumevt = pdata->txnumevt;
1030         mcasp->rxnumevt = pdata->rxnumevt;
1031 
1032         mcasp->dev = &pdev->dev;
1033 
1034         dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1035         if (dat)
1036                 mcasp->dat_port = true;
1037 
1038         dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1039         dma_data->asp_chan_q = pdata->asp_chan_q;
1040         dma_data->ram_chan_q = pdata->ram_chan_q;
1041         dma_data->sram_pool = pdata->sram_pool;
1042         dma_data->sram_size = pdata->sram_size_playback;
1043         if (dat)
1044                 dma_data->dma_addr = dat->start;
1045         else
1046                 dma_data->dma_addr = mem->start + pdata->tx_dma_offset;
1047 
1048         /* Unconditional dmaengine stuff */
1049         mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = dma_data->dma_addr;
1050 
1051         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1052         if (res)
1053                 dma_data->channel = res->start;
1054         else
1055                 dma_data->channel = pdata->tx_dma_channel;
1056 
1057         dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1058         dma_data->asp_chan_q = pdata->asp_chan_q;
1059         dma_data->ram_chan_q = pdata->ram_chan_q;
1060         dma_data->sram_pool = pdata->sram_pool;
1061         dma_data->sram_size = pdata->sram_size_capture;
1062         if (dat)
1063                 dma_data->dma_addr = dat->start;
1064         else
1065                 dma_data->dma_addr = mem->start + pdata->rx_dma_offset;
1066 
1067         /* Unconditional dmaengine stuff */
1068         mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = dma_data->dma_addr;
1069 
1070         if (mcasp->version < MCASP_VERSION_3) {
1071                 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1072                 /* dma_data->dma_addr is pointing to the data port address */
1073                 mcasp->dat_port = true;
1074         } else {
1075                 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1076         }
1077 
1078         res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1079         if (res)
1080                 dma_data->channel = res->start;
1081         else
1082                 dma_data->channel = pdata->rx_dma_channel;
1083 
1084         /* Unconditional dmaengine stuff */
1085         mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = "tx";
1086         mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data = "rx";
1087 
1088         dev_set_drvdata(&pdev->dev, mcasp);
1089 
1090         mcasp_reparent_fck(pdev);
1091 
1092         ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1093                                          &davinci_mcasp_dai[pdata->op_mode], 1);
1094 
1095         if (ret != 0)
1096                 goto err_release_clk;
1097 
1098         if (mcasp->version != MCASP_VERSION_4) {
1099                 ret = davinci_soc_platform_register(&pdev->dev);
1100                 if (ret) {
1101                         dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1102                         goto err_unregister_component;
1103                 }
1104         }
1105 
1106         return 0;
1107 
1108 err_unregister_component:
1109         snd_soc_unregister_component(&pdev->dev);
1110 err_release_clk:
1111         pm_runtime_put_sync(&pdev->dev);
1112         pm_runtime_disable(&pdev->dev);
1113         return ret;
1114 }
1115 
1116 static int davinci_mcasp_remove(struct platform_device *pdev)
1117 {
1118         struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
1119 
1120         snd_soc_unregister_component(&pdev->dev);
1121         if (mcasp->version != MCASP_VERSION_4)
1122                 davinci_soc_platform_unregister(&pdev->dev);
1123 
1124         pm_runtime_put_sync(&pdev->dev);
1125         pm_runtime_disable(&pdev->dev);
1126 
1127         return 0;
1128 }
1129 
1130 #ifdef CONFIG_PM_SLEEP
1131 static int davinci_mcasp_suspend(struct device *dev)
1132 {
1133         struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1134 
1135         mcasp->context.txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
1136         mcasp->context.rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
1137         mcasp->context.txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
1138         mcasp->context.rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
1139         mcasp->context.aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
1140         mcasp->context.aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
1141         mcasp->context.pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
1142 
1143         return 0;
1144 }
1145 
1146 static int davinci_mcasp_resume(struct device *dev)
1147 {
1148         struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1149 
1150         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
1151         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
1152         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
1153         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
1154         mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
1155         mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
1156         mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
1157 
1158         return 0;
1159 }
1160 #endif
1161 
1162 SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
1163                   davinci_mcasp_suspend,
1164                   davinci_mcasp_resume);
1165 
1166 static struct platform_driver davinci_mcasp_driver = {
1167         .probe          = davinci_mcasp_probe,
1168         .remove         = davinci_mcasp_remove,
1169         .driver         = {
1170                 .name   = "davinci-mcasp",
1171                 .owner  = THIS_MODULE,
1172                 .pm     = &davinci_mcasp_pm_ops,
1173                 .of_match_table = mcasp_dt_ids,
1174         },
1175 };
1176 
1177 module_platform_driver(davinci_mcasp_driver);
1178 
1179 MODULE_AUTHOR("Steve Chen");
1180 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1181 MODULE_LICENSE("GPL");
1182 

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