Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/sound/soc/davinci/davinci-mcasp.c

  1 /*
  2  * ALSA SoC McASP Audio Layer for TI DAVINCI processor
  3  *
  4  * Multi-channel Audio Serial Port Driver
  5  *
  6  * Author: Nirmal Pandey <n-pandey@ti.com>,
  7  *         Suresh Rajashekara <suresh.r@ti.com>
  8  *         Steve Chen <schen@.mvista.com>
  9  *
 10  * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
 11  * Copyright:   (C) 2009  Texas Instruments, India
 12  *
 13  * This program is free software; you can redistribute it and/or modify
 14  * it under the terms of the GNU General Public License version 2 as
 15  * published by the Free Software Foundation.
 16  */
 17 
 18 #include <linux/init.h>
 19 #include <linux/module.h>
 20 #include <linux/device.h>
 21 #include <linux/slab.h>
 22 #include <linux/delay.h>
 23 #include <linux/io.h>
 24 #include <linux/clk.h>
 25 #include <linux/pm_runtime.h>
 26 #include <linux/of.h>
 27 #include <linux/of_platform.h>
 28 #include <linux/of_device.h>
 29 #include <linux/platform_data/davinci_asp.h>
 30 #include <linux/math64.h>
 31 
 32 #include <sound/asoundef.h>
 33 #include <sound/core.h>
 34 #include <sound/pcm.h>
 35 #include <sound/pcm_params.h>
 36 #include <sound/initval.h>
 37 #include <sound/soc.h>
 38 #include <sound/dmaengine_pcm.h>
 39 #include <sound/omap-pcm.h>
 40 
 41 #include "edma-pcm.h"
 42 #include "davinci-mcasp.h"
 43 
 44 #define MCASP_MAX_AFIFO_DEPTH   64
 45 
 46 static u32 context_regs[] = {
 47         DAVINCI_MCASP_TXFMCTL_REG,
 48         DAVINCI_MCASP_RXFMCTL_REG,
 49         DAVINCI_MCASP_TXFMT_REG,
 50         DAVINCI_MCASP_RXFMT_REG,
 51         DAVINCI_MCASP_ACLKXCTL_REG,
 52         DAVINCI_MCASP_ACLKRCTL_REG,
 53         DAVINCI_MCASP_AHCLKXCTL_REG,
 54         DAVINCI_MCASP_AHCLKRCTL_REG,
 55         DAVINCI_MCASP_PDIR_REG,
 56         DAVINCI_MCASP_RXMASK_REG,
 57         DAVINCI_MCASP_TXMASK_REG,
 58         DAVINCI_MCASP_RXTDM_REG,
 59         DAVINCI_MCASP_TXTDM_REG,
 60 };
 61 
 62 struct davinci_mcasp_context {
 63         u32     config_regs[ARRAY_SIZE(context_regs)];
 64         u32     afifo_regs[2]; /* for read/write fifo control registers */
 65         u32     *xrsr_regs; /* for serializer configuration */
 66         bool    pm_state;
 67 };
 68 
 69 struct davinci_mcasp_ruledata {
 70         struct davinci_mcasp *mcasp;
 71         int serializers;
 72 };
 73 
 74 struct davinci_mcasp {
 75         struct snd_dmaengine_dai_dma_data dma_data[2];
 76         void __iomem *base;
 77         u32 fifo_base;
 78         struct device *dev;
 79         struct snd_pcm_substream *substreams[2];
 80         unsigned int dai_fmt;
 81 
 82         /* McASP specific data */
 83         int     tdm_slots;
 84         u32     tdm_mask[2];
 85         int     slot_width;
 86         u8      op_mode;
 87         u8      num_serializer;
 88         u8      *serial_dir;
 89         u8      version;
 90         u8      bclk_div;
 91         int     streams;
 92         u32     irq_request[2];
 93         int     dma_request[2];
 94 
 95         int     sysclk_freq;
 96         bool    bclk_master;
 97 
 98         /* McASP FIFO related */
 99         u8      txnumevt;
100         u8      rxnumevt;
101 
102         bool    dat_port;
103 
104         /* Used for comstraint setting on the second stream */
105         u32     channels;
106 
107 #ifdef CONFIG_PM_SLEEP
108         struct davinci_mcasp_context context;
109 #endif
110 
111         struct davinci_mcasp_ruledata ruledata[2];
112         struct snd_pcm_hw_constraint_list chconstr[2];
113 };
114 
115 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
116                                   u32 val)
117 {
118         void __iomem *reg = mcasp->base + offset;
119         __raw_writel(__raw_readl(reg) | val, reg);
120 }
121 
122 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
123                                   u32 val)
124 {
125         void __iomem *reg = mcasp->base + offset;
126         __raw_writel((__raw_readl(reg) & ~(val)), reg);
127 }
128 
129 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
130                                   u32 val, u32 mask)
131 {
132         void __iomem *reg = mcasp->base + offset;
133         __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
134 }
135 
136 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
137                                  u32 val)
138 {
139         __raw_writel(val, mcasp->base + offset);
140 }
141 
142 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
143 {
144         return (u32)__raw_readl(mcasp->base + offset);
145 }
146 
147 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
148 {
149         int i = 0;
150 
151         mcasp_set_bits(mcasp, ctl_reg, val);
152 
153         /* programming GBLCTL needs to read back from GBLCTL and verfiy */
154         /* loop count is to avoid the lock-up */
155         for (i = 0; i < 1000; i++) {
156                 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
157                         break;
158         }
159 
160         if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
161                 printk(KERN_ERR "GBLCTL write error\n");
162 }
163 
164 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
165 {
166         u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
167         u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
168 
169         return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
170 }
171 
172 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
173 {
174         if (mcasp->rxnumevt) {  /* enable FIFO */
175                 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
176 
177                 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
178                 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
179         }
180 
181         /* Start clocks */
182         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
183         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
184         /*
185          * When ASYNC == 0 the transmit and receive sections operate
186          * synchronously from the transmit clock and frame sync. We need to make
187          * sure that the TX signlas are enabled when starting reception.
188          */
189         if (mcasp_is_synchronous(mcasp)) {
190                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
191                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
192         }
193 
194         /* Activate serializer(s) */
195         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
196         /* Release RX state machine */
197         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
198         /* Release Frame Sync generator */
199         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
200         if (mcasp_is_synchronous(mcasp))
201                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
202 
203         /* enable receive IRQs */
204         mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
205                        mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
206 }
207 
208 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
209 {
210         u32 cnt;
211 
212         if (mcasp->txnumevt) {  /* enable FIFO */
213                 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
214 
215                 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
216                 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
217         }
218 
219         /* Start clocks */
220         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
221         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
222         /* Activate serializer(s) */
223         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
224 
225         /* wait for XDATA to be cleared */
226         cnt = 0;
227         while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
228                (cnt < 100000))
229                 cnt++;
230 
231         /* Release TX state machine */
232         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
233         /* Release Frame Sync generator */
234         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
235 
236         /* enable transmit IRQs */
237         mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
238                        mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
239 }
240 
241 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
242 {
243         mcasp->streams++;
244 
245         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
246                 mcasp_start_tx(mcasp);
247         else
248                 mcasp_start_rx(mcasp);
249 }
250 
251 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
252 {
253         /* disable IRQ sources */
254         mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
255                        mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
256 
257         /*
258          * In synchronous mode stop the TX clocks if no other stream is
259          * running
260          */
261         if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
262                 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
263 
264         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
265         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
266 
267         if (mcasp->rxnumevt) {  /* disable FIFO */
268                 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
269 
270                 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
271         }
272 }
273 
274 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
275 {
276         u32 val = 0;
277 
278         /* disable IRQ sources */
279         mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
280                        mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
281 
282         /*
283          * In synchronous mode keep TX clocks running if the capture stream is
284          * still running.
285          */
286         if (mcasp_is_synchronous(mcasp) && mcasp->streams)
287                 val =  TXHCLKRST | TXCLKRST | TXFSRST;
288 
289         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
290         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
291 
292         if (mcasp->txnumevt) {  /* disable FIFO */
293                 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
294 
295                 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
296         }
297 }
298 
299 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
300 {
301         mcasp->streams--;
302 
303         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
304                 mcasp_stop_tx(mcasp);
305         else
306                 mcasp_stop_rx(mcasp);
307 }
308 
309 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
310 {
311         struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
312         struct snd_pcm_substream *substream;
313         u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
314         u32 handled_mask = 0;
315         u32 stat;
316 
317         stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
318         if (stat & XUNDRN & irq_mask) {
319                 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
320                 handled_mask |= XUNDRN;
321 
322                 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
323                 if (substream) {
324                         snd_pcm_stream_lock_irq(substream);
325                         if (snd_pcm_running(substream))
326                                 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
327                         snd_pcm_stream_unlock_irq(substream);
328                 }
329         }
330 
331         if (!handled_mask)
332                 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
333                          stat);
334 
335         if (stat & XRERR)
336                 handled_mask |= XRERR;
337 
338         /* Ack the handled event only */
339         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
340 
341         return IRQ_RETVAL(handled_mask);
342 }
343 
344 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
345 {
346         struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
347         struct snd_pcm_substream *substream;
348         u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
349         u32 handled_mask = 0;
350         u32 stat;
351 
352         stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
353         if (stat & ROVRN & irq_mask) {
354                 dev_warn(mcasp->dev, "Receive buffer overflow\n");
355                 handled_mask |= ROVRN;
356 
357                 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
358                 if (substream) {
359                         snd_pcm_stream_lock_irq(substream);
360                         if (snd_pcm_running(substream))
361                                 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
362                         snd_pcm_stream_unlock_irq(substream);
363                 }
364         }
365 
366         if (!handled_mask)
367                 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
368                          stat);
369 
370         if (stat & XRERR)
371                 handled_mask |= XRERR;
372 
373         /* Ack the handled event only */
374         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
375 
376         return IRQ_RETVAL(handled_mask);
377 }
378 
379 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
380 {
381         struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
382         irqreturn_t ret = IRQ_NONE;
383 
384         if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
385                 ret = davinci_mcasp_tx_irq_handler(irq, data);
386 
387         if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
388                 ret |= davinci_mcasp_rx_irq_handler(irq, data);
389 
390         return ret;
391 }
392 
393 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
394                                          unsigned int fmt)
395 {
396         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
397         int ret = 0;
398         u32 data_delay;
399         bool fs_pol_rising;
400         bool inv_fs = false;
401 
402         if (!fmt)
403                 return 0;
404 
405         pm_runtime_get_sync(mcasp->dev);
406         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
407         case SND_SOC_DAIFMT_DSP_A:
408                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
409                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
410                 /* 1st data bit occur one ACLK cycle after the frame sync */
411                 data_delay = 1;
412                 break;
413         case SND_SOC_DAIFMT_DSP_B:
414         case SND_SOC_DAIFMT_AC97:
415                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
416                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
417                 /* No delay after FS */
418                 data_delay = 0;
419                 break;
420         case SND_SOC_DAIFMT_I2S:
421                 /* configure a full-word SYNC pulse (LRCLK) */
422                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
423                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
424                 /* 1st data bit occur one ACLK cycle after the frame sync */
425                 data_delay = 1;
426                 /* FS need to be inverted */
427                 inv_fs = true;
428                 break;
429         case SND_SOC_DAIFMT_LEFT_J:
430                 /* configure a full-word SYNC pulse (LRCLK) */
431                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
432                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
433                 /* No delay after FS */
434                 data_delay = 0;
435                 break;
436         default:
437                 ret = -EINVAL;
438                 goto out;
439         }
440 
441         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
442                        FSXDLY(3));
443         mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
444                        FSRDLY(3));
445 
446         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
447         case SND_SOC_DAIFMT_CBS_CFS:
448                 /* codec is clock and frame slave */
449                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
450                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
451 
452                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
453                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
454 
455                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
456                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
457                 mcasp->bclk_master = 1;
458                 break;
459         case SND_SOC_DAIFMT_CBS_CFM:
460                 /* codec is clock slave and frame master */
461                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
462                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
463 
464                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
465                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
466 
467                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
468                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
469                 mcasp->bclk_master = 1;
470                 break;
471         case SND_SOC_DAIFMT_CBM_CFS:
472                 /* codec is clock master and frame slave */
473                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
474                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
475 
476                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
477                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
478 
479                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
480                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
481                 mcasp->bclk_master = 0;
482                 break;
483         case SND_SOC_DAIFMT_CBM_CFM:
484                 /* codec is clock and frame master */
485                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
486                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
487 
488                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
489                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
490 
491                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
492                                ACLKX | AFSX | ACLKR | AHCLKR | AFSR);
493                 mcasp->bclk_master = 0;
494                 break;
495         default:
496                 ret = -EINVAL;
497                 goto out;
498         }
499 
500         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
501         case SND_SOC_DAIFMT_IB_NF:
502                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
503                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
504                 fs_pol_rising = true;
505                 break;
506         case SND_SOC_DAIFMT_NB_IF:
507                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
508                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
509                 fs_pol_rising = false;
510                 break;
511         case SND_SOC_DAIFMT_IB_IF:
512                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
513                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
514                 fs_pol_rising = false;
515                 break;
516         case SND_SOC_DAIFMT_NB_NF:
517                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
518                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
519                 fs_pol_rising = true;
520                 break;
521         default:
522                 ret = -EINVAL;
523                 goto out;
524         }
525 
526         if (inv_fs)
527                 fs_pol_rising = !fs_pol_rising;
528 
529         if (fs_pol_rising) {
530                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
531                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
532         } else {
533                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
534                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
535         }
536 
537         mcasp->dai_fmt = fmt;
538 out:
539         pm_runtime_put(mcasp->dev);
540         return ret;
541 }
542 
543 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
544                                       int div, bool explicit)
545 {
546         pm_runtime_get_sync(mcasp->dev);
547         switch (div_id) {
548         case MCASP_CLKDIV_AUXCLK:                       /* MCLK divider */
549                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
550                                AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
551                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
552                                AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
553                 break;
554 
555         case MCASP_CLKDIV_BCLK:                 /* BCLK divider */
556                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
557                                ACLKXDIV(div - 1), ACLKXDIV_MASK);
558                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
559                                ACLKRDIV(div - 1), ACLKRDIV_MASK);
560                 if (explicit)
561                         mcasp->bclk_div = div;
562                 break;
563 
564         case MCASP_CLKDIV_BCLK_FS_RATIO:
565                 /*
566                  * BCLK/LRCLK ratio descries how many bit-clock cycles
567                  * fit into one frame. The clock ratio is given for a
568                  * full period of data (for I2S format both left and
569                  * right channels), so it has to be divided by number
570                  * of tdm-slots (for I2S - divided by 2).
571                  * Instead of storing this ratio, we calculate a new
572                  * tdm_slot width by dividing the the ratio by the
573                  * number of configured tdm slots.
574                  */
575                 mcasp->slot_width = div / mcasp->tdm_slots;
576                 if (div % mcasp->tdm_slots)
577                         dev_warn(mcasp->dev,
578                                  "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
579                                  __func__, div, mcasp->tdm_slots);
580                 break;
581 
582         default:
583                 return -EINVAL;
584         }
585 
586         pm_runtime_put(mcasp->dev);
587         return 0;
588 }
589 
590 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
591                                     int div)
592 {
593         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
594 
595         return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
596 }
597 
598 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
599                                     unsigned int freq, int dir)
600 {
601         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
602 
603         pm_runtime_get_sync(mcasp->dev);
604         if (dir == SND_SOC_CLOCK_OUT) {
605                 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
606                 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
607                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
608         } else {
609                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
610                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
611                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
612         }
613 
614         mcasp->sysclk_freq = freq;
615 
616         pm_runtime_put(mcasp->dev);
617         return 0;
618 }
619 
620 /* All serializers must have equal number of channels */
621 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
622                                        int serializers)
623 {
624         struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
625         unsigned int *list = (unsigned int *) cl->list;
626         int slots = mcasp->tdm_slots;
627         int i, count = 0;
628 
629         if (mcasp->tdm_mask[stream])
630                 slots = hweight32(mcasp->tdm_mask[stream]);
631 
632         for (i = 2; i <= slots; i++)
633                 list[count++] = i;
634 
635         for (i = 2; i <= serializers; i++)
636                 list[count++] = i*slots;
637 
638         cl->count = count;
639 
640         return 0;
641 }
642 
643 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
644 {
645         int rx_serializers = 0, tx_serializers = 0, ret, i;
646 
647         for (i = 0; i < mcasp->num_serializer; i++)
648                 if (mcasp->serial_dir[i] == TX_MODE)
649                         tx_serializers++;
650                 else if (mcasp->serial_dir[i] == RX_MODE)
651                         rx_serializers++;
652 
653         ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
654                                           tx_serializers);
655         if (ret)
656                 return ret;
657 
658         ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
659                                           rx_serializers);
660 
661         return ret;
662 }
663 
664 
665 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
666                                       unsigned int tx_mask,
667                                       unsigned int rx_mask,
668                                       int slots, int slot_width)
669 {
670         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
671 
672         dev_dbg(mcasp->dev,
673                  "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
674                  __func__, tx_mask, rx_mask, slots, slot_width);
675 
676         if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
677                 dev_err(mcasp->dev,
678                         "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
679                         tx_mask, rx_mask, slots);
680                 return -EINVAL;
681         }
682 
683         if (slot_width &&
684             (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
685                 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
686                         __func__, slot_width);
687                 return -EINVAL;
688         }
689 
690         mcasp->tdm_slots = slots;
691         mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
692         mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
693         mcasp->slot_width = slot_width;
694 
695         return davinci_mcasp_set_ch_constraints(mcasp);
696 }
697 
698 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
699                                        int sample_width)
700 {
701         u32 fmt;
702         u32 tx_rotate = (sample_width / 4) & 0x7;
703         u32 mask = (1ULL << sample_width) - 1;
704         u32 slot_width = sample_width;
705 
706         /*
707          * For captured data we should not rotate, inversion and masking is
708          * enoguh to get the data to the right position:
709          * Format         data from bus         after reverse (XRBUF)
710          * S16_LE:      |LSB|MSB|xxx|xxx|       |xxx|xxx|MSB|LSB|
711          * S24_3LE:     |LSB|DAT|MSB|xxx|       |xxx|MSB|DAT|LSB|
712          * S24_LE:      |LSB|DAT|MSB|xxx|       |xxx|MSB|DAT|LSB|
713          * S32_LE:      |LSB|DAT|DAT|MSB|       |MSB|DAT|DAT|LSB|
714          */
715         u32 rx_rotate = 0;
716 
717         /*
718          * Setting the tdm slot width either with set_clkdiv() or
719          * set_tdm_slot() allows us to for example send 32 bits per
720          * channel to the codec, while only 16 of them carry audio
721          * payload.
722          */
723         if (mcasp->slot_width) {
724                 /*
725                  * When we have more bclk then it is needed for the
726                  * data, we need to use the rotation to move the
727                  * received samples to have correct alignment.
728                  */
729                 slot_width = mcasp->slot_width;
730                 rx_rotate = (slot_width - sample_width) / 4;
731         }
732 
733         /* mapping of the XSSZ bit-field as described in the datasheet */
734         fmt = (slot_width >> 1) - 1;
735 
736         if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
737                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
738                                RXSSZ(0x0F));
739                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
740                                TXSSZ(0x0F));
741                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
742                                TXROT(7));
743                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
744                                RXROT(7));
745                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
746         }
747 
748         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
749 
750         return 0;
751 }
752 
753 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
754                                  int period_words, int channels)
755 {
756         struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
757         int i;
758         u8 tx_ser = 0;
759         u8 rx_ser = 0;
760         u8 slots = mcasp->tdm_slots;
761         u8 max_active_serializers = (channels + slots - 1) / slots;
762         int active_serializers, numevt;
763         u32 reg;
764         /* Default configuration */
765         if (mcasp->version < MCASP_VERSION_3)
766                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
767 
768         /* All PINS as McASP */
769         mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
770 
771         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
772                 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
773                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
774         } else {
775                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
776                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
777         }
778 
779         for (i = 0; i < mcasp->num_serializer; i++) {
780                 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
781                                mcasp->serial_dir[i]);
782                 if (mcasp->serial_dir[i] == TX_MODE &&
783                                         tx_ser < max_active_serializers) {
784                         mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
785                         mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
786                                        DISMOD_LOW, DISMOD_MASK);
787                         tx_ser++;
788                 } else if (mcasp->serial_dir[i] == RX_MODE &&
789                                         rx_ser < max_active_serializers) {
790                         mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
791                         rx_ser++;
792                 } else {
793                         mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
794                                        SRMOD_INACTIVE, SRMOD_MASK);
795                 }
796         }
797 
798         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
799                 active_serializers = tx_ser;
800                 numevt = mcasp->txnumevt;
801                 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
802         } else {
803                 active_serializers = rx_ser;
804                 numevt = mcasp->rxnumevt;
805                 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
806         }
807 
808         if (active_serializers < max_active_serializers) {
809                 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
810                          "enabled in mcasp (%d)\n", channels,
811                          active_serializers * slots);
812                 return -EINVAL;
813         }
814 
815         /* AFIFO is not in use */
816         if (!numevt) {
817                 /* Configure the burst size for platform drivers */
818                 if (active_serializers > 1) {
819                         /*
820                          * If more than one serializers are in use we have one
821                          * DMA request to provide data for all serializers.
822                          * For example if three serializers are enabled the DMA
823                          * need to transfer three words per DMA request.
824                          */
825                         dma_data->maxburst = active_serializers;
826                 } else {
827                         dma_data->maxburst = 0;
828                 }
829                 return 0;
830         }
831 
832         if (period_words % active_serializers) {
833                 dev_err(mcasp->dev, "Invalid combination of period words and "
834                         "active serializers: %d, %d\n", period_words,
835                         active_serializers);
836                 return -EINVAL;
837         }
838 
839         /*
840          * Calculate the optimal AFIFO depth for platform side:
841          * The number of words for numevt need to be in steps of active
842          * serializers.
843          */
844         numevt = (numevt / active_serializers) * active_serializers;
845 
846         while (period_words % numevt && numevt > 0)
847                 numevt -= active_serializers;
848         if (numevt <= 0)
849                 numevt = active_serializers;
850 
851         mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
852         mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
853 
854         /* Configure the burst size for platform drivers */
855         if (numevt == 1)
856                 numevt = 0;
857         dma_data->maxburst = numevt;
858 
859         return 0;
860 }
861 
862 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
863                               int channels)
864 {
865         int i, active_slots;
866         int total_slots;
867         int active_serializers;
868         u32 mask = 0;
869         u32 busel = 0;
870 
871         total_slots = mcasp->tdm_slots;
872 
873         /*
874          * If more than one serializer is needed, then use them with
875          * all the specified tdm_slots. Otherwise, one serializer can
876          * cope with the transaction using just as many slots as there
877          * are channels in the stream.
878          */
879         if (mcasp->tdm_mask[stream]) {
880                 active_slots = hweight32(mcasp->tdm_mask[stream]);
881                 active_serializers = (channels + active_slots - 1) /
882                         active_slots;
883                 if (active_serializers == 1) {
884                         active_slots = channels;
885                         for (i = 0; i < total_slots; i++) {
886                                 if ((1 << i) & mcasp->tdm_mask[stream]) {
887                                         mask |= (1 << i);
888                                         if (--active_slots <= 0)
889                                                 break;
890                                 }
891                         }
892                 }
893         } else {
894                 active_serializers = (channels + total_slots - 1) / total_slots;
895                 if (active_serializers == 1)
896                         active_slots = channels;
897                 else
898                         active_slots = total_slots;
899 
900                 for (i = 0; i < active_slots; i++)
901                         mask |= (1 << i);
902         }
903         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
904 
905         if (!mcasp->dat_port)
906                 busel = TXSEL;
907 
908         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
909                 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
910                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
911                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
912                                FSXMOD(total_slots), FSXMOD(0x1FF));
913         } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
914                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
915                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
916                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
917                                FSRMOD(total_slots), FSRMOD(0x1FF));
918                 /*
919                  * If McASP is set to be TX/RX synchronous and the playback is
920                  * not running already we need to configure the TX slots in
921                  * order to have correct FSX on the bus
922                  */
923                 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
924                         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
925                                        FSXMOD(total_slots), FSXMOD(0x1FF));
926         }
927 
928         return 0;
929 }
930 
931 /* S/PDIF */
932 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
933                               unsigned int rate)
934 {
935         u32 cs_value = 0;
936         u8 *cs_bytes = (u8*) &cs_value;
937 
938         /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
939            and LSB first */
940         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
941 
942         /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
943         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
944 
945         /* Set the TX tdm : for all the slots */
946         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
947 
948         /* Set the TX clock controls : div = 1 and internal */
949         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
950 
951         mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
952 
953         /* Only 44100 and 48000 are valid, both have the same setting */
954         mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
955 
956         /* Enable the DIT */
957         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
958 
959         /* Set S/PDIF channel status bits */
960         cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
961         cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
962 
963         switch (rate) {
964         case 22050:
965                 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
966                 break;
967         case 24000:
968                 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
969                 break;
970         case 32000:
971                 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
972                 break;
973         case 44100:
974                 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
975                 break;
976         case 48000:
977                 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
978                 break;
979         case 88200:
980                 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
981                 break;
982         case 96000:
983                 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
984                 break;
985         case 176400:
986                 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
987                 break;
988         case 192000:
989                 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
990                 break;
991         default:
992                 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
993                 return -EINVAL;
994         }
995 
996         mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
997         mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
998 
999         return 0;
1000 }
1001 
1002 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1003                                       unsigned int bclk_freq, bool set)
1004 {
1005         int error_ppm;
1006         unsigned int sysclk_freq = mcasp->sysclk_freq;
1007         u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1008         int div = sysclk_freq / bclk_freq;
1009         int rem = sysclk_freq % bclk_freq;
1010         int aux_div = 1;
1011 
1012         if (div > (ACLKXDIV_MASK + 1)) {
1013                 if (reg & AHCLKXE) {
1014                         aux_div = div / (ACLKXDIV_MASK + 1);
1015                         if (div % (ACLKXDIV_MASK + 1))
1016                                 aux_div++;
1017 
1018                         sysclk_freq /= aux_div;
1019                         div = sysclk_freq / bclk_freq;
1020                         rem = sysclk_freq % bclk_freq;
1021                 } else if (set) {
1022                         dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1023                                  sysclk_freq);
1024                 }
1025         }
1026 
1027         if (rem != 0) {
1028                 if (div == 0 ||
1029                     ((sysclk_freq / div) - bclk_freq) >
1030                     (bclk_freq - (sysclk_freq / (div+1)))) {
1031                         div++;
1032                         rem = rem - bclk_freq;
1033                 }
1034         }
1035         error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1036                      (int)bclk_freq)) / div - 1000000;
1037 
1038         if (set) {
1039                 if (error_ppm)
1040                         dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1041                                  error_ppm);
1042 
1043                 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1044                 if (reg & AHCLKXE)
1045                         __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1046                                                    aux_div, 0);
1047         }
1048 
1049         return error_ppm;
1050 }
1051 
1052 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1053                                         struct snd_pcm_hw_params *params,
1054                                         struct snd_soc_dai *cpu_dai)
1055 {
1056         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1057         int word_length;
1058         int channels = params_channels(params);
1059         int period_size = params_period_size(params);
1060         int ret;
1061 
1062         ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1063         if (ret)
1064                 return ret;
1065 
1066         /*
1067          * If mcasp is BCLK master, and a BCLK divider was not provided by
1068          * the machine driver, we need to calculate the ratio.
1069          */
1070         if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1071                 int slots = mcasp->tdm_slots;
1072                 int rate = params_rate(params);
1073                 int sbits = params_width(params);
1074 
1075                 if (mcasp->slot_width)
1076                         sbits = mcasp->slot_width;
1077 
1078                 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
1079         }
1080 
1081         ret = mcasp_common_hw_param(mcasp, substream->stream,
1082                                     period_size * channels, channels);
1083         if (ret)
1084                 return ret;
1085 
1086         if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1087                 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1088         else
1089                 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1090                                          channels);
1091 
1092         if (ret)
1093                 return ret;
1094 
1095         switch (params_format(params)) {
1096         case SNDRV_PCM_FORMAT_U8:
1097         case SNDRV_PCM_FORMAT_S8:
1098                 word_length = 8;
1099                 break;
1100 
1101         case SNDRV_PCM_FORMAT_U16_LE:
1102         case SNDRV_PCM_FORMAT_S16_LE:
1103                 word_length = 16;
1104                 break;
1105 
1106         case SNDRV_PCM_FORMAT_U24_3LE:
1107         case SNDRV_PCM_FORMAT_S24_3LE:
1108                 word_length = 24;
1109                 break;
1110 
1111         case SNDRV_PCM_FORMAT_U24_LE:
1112         case SNDRV_PCM_FORMAT_S24_LE:
1113                 word_length = 24;
1114                 break;
1115 
1116         case SNDRV_PCM_FORMAT_U32_LE:
1117         case SNDRV_PCM_FORMAT_S32_LE:
1118                 word_length = 32;
1119                 break;
1120 
1121         default:
1122                 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1123                 return -EINVAL;
1124         }
1125 
1126         davinci_config_channel_size(mcasp, word_length);
1127 
1128         if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1129                 mcasp->channels = channels;
1130 
1131         return 0;
1132 }
1133 
1134 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1135                                      int cmd, struct snd_soc_dai *cpu_dai)
1136 {
1137         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1138         int ret = 0;
1139 
1140         switch (cmd) {
1141         case SNDRV_PCM_TRIGGER_RESUME:
1142         case SNDRV_PCM_TRIGGER_START:
1143         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1144                 davinci_mcasp_start(mcasp, substream->stream);
1145                 break;
1146         case SNDRV_PCM_TRIGGER_SUSPEND:
1147         case SNDRV_PCM_TRIGGER_STOP:
1148         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1149                 davinci_mcasp_stop(mcasp, substream->stream);
1150                 break;
1151 
1152         default:
1153                 ret = -EINVAL;
1154         }
1155 
1156         return ret;
1157 }
1158 
1159 static const unsigned int davinci_mcasp_dai_rates[] = {
1160         8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1161         88200, 96000, 176400, 192000,
1162 };
1163 
1164 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1165 
1166 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1167                                       struct snd_pcm_hw_rule *rule)
1168 {
1169         struct davinci_mcasp_ruledata *rd = rule->private;
1170         struct snd_interval *ri =
1171                 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1172         int sbits = params_width(params);
1173         int slots = rd->mcasp->tdm_slots;
1174         struct snd_interval range;
1175         int i;
1176 
1177         if (rd->mcasp->slot_width)
1178                 sbits = rd->mcasp->slot_width;
1179 
1180         snd_interval_any(&range);
1181         range.empty = 1;
1182 
1183         for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1184                 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1185                         uint bclk_freq = sbits*slots*
1186                                 davinci_mcasp_dai_rates[i];
1187                         int ppm;
1188 
1189                         ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
1190                                                          false);
1191                         if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1192                                 if (range.empty) {
1193                                         range.min = davinci_mcasp_dai_rates[i];
1194                                         range.empty = 0;
1195                                 }
1196                                 range.max = davinci_mcasp_dai_rates[i];
1197                         }
1198                 }
1199         }
1200 
1201         dev_dbg(rd->mcasp->dev,
1202                 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1203                 ri->min, ri->max, range.min, range.max, sbits, slots);
1204 
1205         return snd_interval_refine(hw_param_interval(params, rule->var),
1206                                    &range);
1207 }
1208 
1209 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1210                                         struct snd_pcm_hw_rule *rule)
1211 {
1212         struct davinci_mcasp_ruledata *rd = rule->private;
1213         struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1214         struct snd_mask nfmt;
1215         int rate = params_rate(params);
1216         int slots = rd->mcasp->tdm_slots;
1217         int i, count = 0;
1218 
1219         snd_mask_none(&nfmt);
1220 
1221         for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
1222                 if (snd_mask_test(fmt, i)) {
1223                         uint sbits = snd_pcm_format_width(i);
1224                         int ppm;
1225 
1226                         if (rd->mcasp->slot_width)
1227                                 sbits = rd->mcasp->slot_width;
1228 
1229                         ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
1230                                                          sbits * slots * rate,
1231                                                          false);
1232                         if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1233                                 snd_mask_set(&nfmt, i);
1234                                 count++;
1235                         }
1236                 }
1237         }
1238         dev_dbg(rd->mcasp->dev,
1239                 "%d possible sample format for %d Hz and %d tdm slots\n",
1240                 count, rate, slots);
1241 
1242         return snd_mask_refine(fmt, &nfmt);
1243 }
1244 
1245 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1246                                  struct snd_soc_dai *cpu_dai)
1247 {
1248         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1249         struct davinci_mcasp_ruledata *ruledata =
1250                                         &mcasp->ruledata[substream->stream];
1251         u32 max_channels = 0;
1252         int i, dir;
1253         int tdm_slots = mcasp->tdm_slots;
1254 
1255         /* Do not allow more then one stream per direction */
1256         if (mcasp->substreams[substream->stream])
1257                 return -EBUSY;
1258 
1259         mcasp->substreams[substream->stream] = substream;
1260 
1261         if (mcasp->tdm_mask[substream->stream])
1262                 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1263 
1264         if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1265                 return 0;
1266 
1267         /*
1268          * Limit the maximum allowed channels for the first stream:
1269          * number of serializers for the direction * tdm slots per serializer
1270          */
1271         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1272                 dir = TX_MODE;
1273         else
1274                 dir = RX_MODE;
1275 
1276         for (i = 0; i < mcasp->num_serializer; i++) {
1277                 if (mcasp->serial_dir[i] == dir)
1278                         max_channels++;
1279         }
1280         ruledata->serializers = max_channels;
1281         max_channels *= tdm_slots;
1282         /*
1283          * If the already active stream has less channels than the calculated
1284          * limnit based on the seirializers * tdm_slots, we need to use that as
1285          * a constraint for the second stream.
1286          * Otherwise (first stream or less allowed channels) we use the
1287          * calculated constraint.
1288          */
1289         if (mcasp->channels && mcasp->channels < max_channels)
1290                 max_channels = mcasp->channels;
1291         /*
1292          * But we can always allow channels upto the amount of
1293          * the available tdm_slots.
1294          */
1295         if (max_channels < tdm_slots)
1296                 max_channels = tdm_slots;
1297 
1298         snd_pcm_hw_constraint_minmax(substream->runtime,
1299                                      SNDRV_PCM_HW_PARAM_CHANNELS,
1300                                      2, max_channels);
1301 
1302         snd_pcm_hw_constraint_list(substream->runtime,
1303                                    0, SNDRV_PCM_HW_PARAM_CHANNELS,
1304                                    &mcasp->chconstr[substream->stream]);
1305 
1306         if (mcasp->slot_width)
1307                 snd_pcm_hw_constraint_minmax(substream->runtime,
1308                                              SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1309                                              8, mcasp->slot_width);
1310 
1311         /*
1312          * If we rely on implicit BCLK divider setting we should
1313          * set constraints based on what we can provide.
1314          */
1315         if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1316                 int ret;
1317 
1318                 ruledata->mcasp = mcasp;
1319 
1320                 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1321                                           SNDRV_PCM_HW_PARAM_RATE,
1322                                           davinci_mcasp_hw_rule_rate,
1323                                           ruledata,
1324                                           SNDRV_PCM_HW_PARAM_FORMAT, -1);
1325                 if (ret)
1326                         return ret;
1327                 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1328                                           SNDRV_PCM_HW_PARAM_FORMAT,
1329                                           davinci_mcasp_hw_rule_format,
1330                                           ruledata,
1331                                           SNDRV_PCM_HW_PARAM_RATE, -1);
1332                 if (ret)
1333                         return ret;
1334         }
1335 
1336         return 0;
1337 }
1338 
1339 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1340                                    struct snd_soc_dai *cpu_dai)
1341 {
1342         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1343 
1344         mcasp->substreams[substream->stream] = NULL;
1345 
1346         if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1347                 return;
1348 
1349         if (!cpu_dai->active)
1350                 mcasp->channels = 0;
1351 }
1352 
1353 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1354         .startup        = davinci_mcasp_startup,
1355         .shutdown       = davinci_mcasp_shutdown,
1356         .trigger        = davinci_mcasp_trigger,
1357         .hw_params      = davinci_mcasp_hw_params,
1358         .set_fmt        = davinci_mcasp_set_dai_fmt,
1359         .set_clkdiv     = davinci_mcasp_set_clkdiv,
1360         .set_sysclk     = davinci_mcasp_set_sysclk,
1361         .set_tdm_slot   = davinci_mcasp_set_tdm_slot,
1362 };
1363 
1364 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1365 {
1366         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1367 
1368         dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1369         dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1370 
1371         return 0;
1372 }
1373 
1374 #ifdef CONFIG_PM_SLEEP
1375 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1376 {
1377         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1378         struct davinci_mcasp_context *context = &mcasp->context;
1379         u32 reg;
1380         int i;
1381 
1382         context->pm_state = pm_runtime_active(mcasp->dev);
1383         if (!context->pm_state)
1384                 pm_runtime_get_sync(mcasp->dev);
1385 
1386         for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1387                 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1388 
1389         if (mcasp->txnumevt) {
1390                 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1391                 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1392         }
1393         if (mcasp->rxnumevt) {
1394                 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1395                 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1396         }
1397 
1398         for (i = 0; i < mcasp->num_serializer; i++)
1399                 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1400                                                 DAVINCI_MCASP_XRSRCTL_REG(i));
1401 
1402         pm_runtime_put_sync(mcasp->dev);
1403 
1404         return 0;
1405 }
1406 
1407 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1408 {
1409         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1410         struct davinci_mcasp_context *context = &mcasp->context;
1411         u32 reg;
1412         int i;
1413 
1414         pm_runtime_get_sync(mcasp->dev);
1415 
1416         for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1417                 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1418 
1419         if (mcasp->txnumevt) {
1420                 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1421                 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1422         }
1423         if (mcasp->rxnumevt) {
1424                 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1425                 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1426         }
1427 
1428         for (i = 0; i < mcasp->num_serializer; i++)
1429                 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1430                               context->xrsr_regs[i]);
1431 
1432         if (!context->pm_state)
1433                 pm_runtime_put_sync(mcasp->dev);
1434 
1435         return 0;
1436 }
1437 #else
1438 #define davinci_mcasp_suspend NULL
1439 #define davinci_mcasp_resume NULL
1440 #endif
1441 
1442 #define DAVINCI_MCASP_RATES     SNDRV_PCM_RATE_8000_192000
1443 
1444 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1445                                 SNDRV_PCM_FMTBIT_U8 | \
1446                                 SNDRV_PCM_FMTBIT_S16_LE | \
1447                                 SNDRV_PCM_FMTBIT_U16_LE | \
1448                                 SNDRV_PCM_FMTBIT_S24_LE | \
1449                                 SNDRV_PCM_FMTBIT_U24_LE | \
1450                                 SNDRV_PCM_FMTBIT_S24_3LE | \
1451                                 SNDRV_PCM_FMTBIT_U24_3LE | \
1452                                 SNDRV_PCM_FMTBIT_S32_LE | \
1453                                 SNDRV_PCM_FMTBIT_U32_LE)
1454 
1455 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1456         {
1457                 .name           = "davinci-mcasp.0",
1458                 .probe          = davinci_mcasp_dai_probe,
1459                 .suspend        = davinci_mcasp_suspend,
1460                 .resume         = davinci_mcasp_resume,
1461                 .playback       = {
1462                         .channels_min   = 2,
1463                         .channels_max   = 32 * 16,
1464                         .rates          = DAVINCI_MCASP_RATES,
1465                         .formats        = DAVINCI_MCASP_PCM_FMTS,
1466                 },
1467                 .capture        = {
1468                         .channels_min   = 2,
1469                         .channels_max   = 32 * 16,
1470                         .rates          = DAVINCI_MCASP_RATES,
1471                         .formats        = DAVINCI_MCASP_PCM_FMTS,
1472                 },
1473                 .ops            = &davinci_mcasp_dai_ops,
1474 
1475                 .symmetric_samplebits   = 1,
1476                 .symmetric_rates        = 1,
1477         },
1478         {
1479                 .name           = "davinci-mcasp.1",
1480                 .probe          = davinci_mcasp_dai_probe,
1481                 .playback       = {
1482                         .channels_min   = 1,
1483                         .channels_max   = 384,
1484                         .rates          = DAVINCI_MCASP_RATES,
1485                         .formats        = DAVINCI_MCASP_PCM_FMTS,
1486                 },
1487                 .ops            = &davinci_mcasp_dai_ops,
1488         },
1489 
1490 };
1491 
1492 static const struct snd_soc_component_driver davinci_mcasp_component = {
1493         .name           = "davinci-mcasp",
1494 };
1495 
1496 /* Some HW specific values and defaults. The rest is filled in from DT. */
1497 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1498         .tx_dma_offset = 0x400,
1499         .rx_dma_offset = 0x400,
1500         .version = MCASP_VERSION_1,
1501 };
1502 
1503 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1504         .tx_dma_offset = 0x2000,
1505         .rx_dma_offset = 0x2000,
1506         .version = MCASP_VERSION_2,
1507 };
1508 
1509 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1510         .tx_dma_offset = 0,
1511         .rx_dma_offset = 0,
1512         .version = MCASP_VERSION_3,
1513 };
1514 
1515 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1516         /* The CFG port offset will be calculated if it is needed */
1517         .tx_dma_offset = 0,
1518         .rx_dma_offset = 0,
1519         .version = MCASP_VERSION_4,
1520 };
1521 
1522 static const struct of_device_id mcasp_dt_ids[] = {
1523         {
1524                 .compatible = "ti,dm646x-mcasp-audio",
1525                 .data = &dm646x_mcasp_pdata,
1526         },
1527         {
1528                 .compatible = "ti,da830-mcasp-audio",
1529                 .data = &da830_mcasp_pdata,
1530         },
1531         {
1532                 .compatible = "ti,am33xx-mcasp-audio",
1533                 .data = &am33xx_mcasp_pdata,
1534         },
1535         {
1536                 .compatible = "ti,dra7-mcasp-audio",
1537                 .data = &dra7_mcasp_pdata,
1538         },
1539         { /* sentinel */ }
1540 };
1541 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1542 
1543 static int mcasp_reparent_fck(struct platform_device *pdev)
1544 {
1545         struct device_node *node = pdev->dev.of_node;
1546         struct clk *gfclk, *parent_clk;
1547         const char *parent_name;
1548         int ret;
1549 
1550         if (!node)
1551                 return 0;
1552 
1553         parent_name = of_get_property(node, "fck_parent", NULL);
1554         if (!parent_name)
1555                 return 0;
1556 
1557         dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1558 
1559         gfclk = clk_get(&pdev->dev, "fck");
1560         if (IS_ERR(gfclk)) {
1561                 dev_err(&pdev->dev, "failed to get fck\n");
1562                 return PTR_ERR(gfclk);
1563         }
1564 
1565         parent_clk = clk_get(NULL, parent_name);
1566         if (IS_ERR(parent_clk)) {
1567                 dev_err(&pdev->dev, "failed to get parent clock\n");
1568                 ret = PTR_ERR(parent_clk);
1569                 goto err1;
1570         }
1571 
1572         ret = clk_set_parent(gfclk, parent_clk);
1573         if (ret) {
1574                 dev_err(&pdev->dev, "failed to reparent fck\n");
1575                 goto err2;
1576         }
1577 
1578 err2:
1579         clk_put(parent_clk);
1580 err1:
1581         clk_put(gfclk);
1582         return ret;
1583 }
1584 
1585 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1586                                                 struct platform_device *pdev)
1587 {
1588         struct device_node *np = pdev->dev.of_node;
1589         struct davinci_mcasp_pdata *pdata = NULL;
1590         const struct of_device_id *match =
1591                         of_match_device(mcasp_dt_ids, &pdev->dev);
1592         struct of_phandle_args dma_spec;
1593 
1594         const u32 *of_serial_dir32;
1595         u32 val;
1596         int i, ret = 0;
1597 
1598         if (pdev->dev.platform_data) {
1599                 pdata = pdev->dev.platform_data;
1600                 return pdata;
1601         } else if (match) {
1602                 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1603                                      GFP_KERNEL);
1604                 if (!pdata) {
1605                         dev_err(&pdev->dev,
1606                                 "Failed to allocate memory for pdata\n");
1607                         ret = -ENOMEM;
1608                         return pdata;
1609                 }
1610         } else {
1611                 /* control shouldn't reach here. something is wrong */
1612                 ret = -EINVAL;
1613                 goto nodata;
1614         }
1615 
1616         ret = of_property_read_u32(np, "op-mode", &val);
1617         if (ret >= 0)
1618                 pdata->op_mode = val;
1619 
1620         ret = of_property_read_u32(np, "tdm-slots", &val);
1621         if (ret >= 0) {
1622                 if (val < 2 || val > 32) {
1623                         dev_err(&pdev->dev,
1624                                 "tdm-slots must be in rage [2-32]\n");
1625                         ret = -EINVAL;
1626                         goto nodata;
1627                 }
1628 
1629                 pdata->tdm_slots = val;
1630         }
1631 
1632         of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1633         val /= sizeof(u32);
1634         if (of_serial_dir32) {
1635                 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1636                                                  (sizeof(*of_serial_dir) * val),
1637                                                  GFP_KERNEL);
1638                 if (!of_serial_dir) {
1639                         ret = -ENOMEM;
1640                         goto nodata;
1641                 }
1642 
1643                 for (i = 0; i < val; i++)
1644                         of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1645 
1646                 pdata->num_serializer = val;
1647                 pdata->serial_dir = of_serial_dir;
1648         }
1649 
1650         ret = of_property_match_string(np, "dma-names", "tx");
1651         if (ret < 0)
1652                 goto nodata;
1653 
1654         ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1655                                          &dma_spec);
1656         if (ret < 0)
1657                 goto nodata;
1658 
1659         pdata->tx_dma_channel = dma_spec.args[0];
1660 
1661         /* RX is not valid in DIT mode */
1662         if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1663                 ret = of_property_match_string(np, "dma-names", "rx");
1664                 if (ret < 0)
1665                         goto nodata;
1666 
1667                 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1668                                                  &dma_spec);
1669                 if (ret < 0)
1670                         goto nodata;
1671 
1672                 pdata->rx_dma_channel = dma_spec.args[0];
1673         }
1674 
1675         ret = of_property_read_u32(np, "tx-num-evt", &val);
1676         if (ret >= 0)
1677                 pdata->txnumevt = val;
1678 
1679         ret = of_property_read_u32(np, "rx-num-evt", &val);
1680         if (ret >= 0)
1681                 pdata->rxnumevt = val;
1682 
1683         ret = of_property_read_u32(np, "sram-size-playback", &val);
1684         if (ret >= 0)
1685                 pdata->sram_size_playback = val;
1686 
1687         ret = of_property_read_u32(np, "sram-size-capture", &val);
1688         if (ret >= 0)
1689                 pdata->sram_size_capture = val;
1690 
1691         return  pdata;
1692 
1693 nodata:
1694         if (ret < 0) {
1695                 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1696                         ret);
1697                 pdata = NULL;
1698         }
1699         return  pdata;
1700 }
1701 
1702 enum {
1703         PCM_EDMA,
1704         PCM_SDMA,
1705 };
1706 static const char *sdma_prefix = "ti,omap";
1707 
1708 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1709 {
1710         struct dma_chan *chan;
1711         const char *tmp;
1712         int ret = PCM_EDMA;
1713 
1714         if (!mcasp->dev->of_node)
1715                 return PCM_EDMA;
1716 
1717         tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1718         chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1719         if (IS_ERR(chan)) {
1720                 if (PTR_ERR(chan) != -EPROBE_DEFER)
1721                         dev_err(mcasp->dev,
1722                                 "Can't verify DMA configuration (%ld)\n",
1723                                 PTR_ERR(chan));
1724                 return PTR_ERR(chan);
1725         }
1726         BUG_ON(!chan->device || !chan->device->dev);
1727 
1728         if (chan->device->dev->of_node)
1729                 ret = of_property_read_string(chan->device->dev->of_node,
1730                                               "compatible", &tmp);
1731         else
1732                 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1733 
1734         dma_release_channel(chan);
1735         if (ret)
1736                 return ret;
1737 
1738         dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1739         if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1740                 return PCM_SDMA;
1741 
1742         return PCM_EDMA;
1743 }
1744 
1745 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1746 {
1747         int i;
1748         u32 offset = 0;
1749 
1750         if (pdata->version != MCASP_VERSION_4)
1751                 return pdata->tx_dma_offset;
1752 
1753         for (i = 0; i < pdata->num_serializer; i++) {
1754                 if (pdata->serial_dir[i] == TX_MODE) {
1755                         if (!offset) {
1756                                 offset = DAVINCI_MCASP_TXBUF_REG(i);
1757                         } else {
1758                                 pr_err("%s: Only one serializer allowed!\n",
1759                                        __func__);
1760                                 break;
1761                         }
1762                 }
1763         }
1764 
1765         return offset;
1766 }
1767 
1768 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1769 {
1770         int i;
1771         u32 offset = 0;
1772 
1773         if (pdata->version != MCASP_VERSION_4)
1774                 return pdata->rx_dma_offset;
1775 
1776         for (i = 0; i < pdata->num_serializer; i++) {
1777                 if (pdata->serial_dir[i] == RX_MODE) {
1778                         if (!offset) {
1779                                 offset = DAVINCI_MCASP_RXBUF_REG(i);
1780                         } else {
1781                                 pr_err("%s: Only one serializer allowed!\n",
1782                                        __func__);
1783                                 break;
1784                         }
1785                 }
1786         }
1787 
1788         return offset;
1789 }
1790 
1791 static int davinci_mcasp_probe(struct platform_device *pdev)
1792 {
1793         struct snd_dmaengine_dai_dma_data *dma_data;
1794         struct resource *mem, *res, *dat;
1795         struct davinci_mcasp_pdata *pdata;
1796         struct davinci_mcasp *mcasp;
1797         char *irq_name;
1798         int *dma;
1799         int irq;
1800         int ret;
1801 
1802         if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1803                 dev_err(&pdev->dev, "No platform data supplied\n");
1804                 return -EINVAL;
1805         }
1806 
1807         mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1808                            GFP_KERNEL);
1809         if (!mcasp)
1810                 return  -ENOMEM;
1811 
1812         pdata = davinci_mcasp_set_pdata_from_of(pdev);
1813         if (!pdata) {
1814                 dev_err(&pdev->dev, "no platform data\n");
1815                 return -EINVAL;
1816         }
1817 
1818         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1819         if (!mem) {
1820                 dev_warn(mcasp->dev,
1821                          "\"mpu\" mem resource not found, using index 0\n");
1822                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1823                 if (!mem) {
1824                         dev_err(&pdev->dev, "no mem resource?\n");
1825                         return -ENODEV;
1826                 }
1827         }
1828 
1829         mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1830         if (IS_ERR(mcasp->base))
1831                 return PTR_ERR(mcasp->base);
1832 
1833         pm_runtime_enable(&pdev->dev);
1834 
1835         mcasp->op_mode = pdata->op_mode;
1836         /* sanity check for tdm slots parameter */
1837         if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1838                 if (pdata->tdm_slots < 2) {
1839                         dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1840                                 pdata->tdm_slots);
1841                         mcasp->tdm_slots = 2;
1842                 } else if (pdata->tdm_slots > 32) {
1843                         dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1844                                 pdata->tdm_slots);
1845                         mcasp->tdm_slots = 32;
1846                 } else {
1847                         mcasp->tdm_slots = pdata->tdm_slots;
1848                 }
1849         }
1850 
1851         mcasp->num_serializer = pdata->num_serializer;
1852 #ifdef CONFIG_PM_SLEEP
1853         mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1854                                         sizeof(u32) * mcasp->num_serializer,
1855                                         GFP_KERNEL);
1856 #endif
1857         mcasp->serial_dir = pdata->serial_dir;
1858         mcasp->version = pdata->version;
1859         mcasp->txnumevt = pdata->txnumevt;
1860         mcasp->rxnumevt = pdata->rxnumevt;
1861 
1862         mcasp->dev = &pdev->dev;
1863 
1864         irq = platform_get_irq_byname(pdev, "common");
1865         if (irq >= 0) {
1866                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1867                                           dev_name(&pdev->dev));
1868                 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1869                                                 davinci_mcasp_common_irq_handler,
1870                                                 IRQF_ONESHOT | IRQF_SHARED,
1871                                                 irq_name, mcasp);
1872                 if (ret) {
1873                         dev_err(&pdev->dev, "common IRQ request failed\n");
1874                         goto err;
1875                 }
1876 
1877                 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1878                 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1879         }
1880 
1881         irq = platform_get_irq_byname(pdev, "rx");
1882         if (irq >= 0) {
1883                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1884                                           dev_name(&pdev->dev));
1885                 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1886                                                 davinci_mcasp_rx_irq_handler,
1887                                                 IRQF_ONESHOT, irq_name, mcasp);
1888                 if (ret) {
1889                         dev_err(&pdev->dev, "RX IRQ request failed\n");
1890                         goto err;
1891                 }
1892 
1893                 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1894         }
1895 
1896         irq = platform_get_irq_byname(pdev, "tx");
1897         if (irq >= 0) {
1898                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1899                                           dev_name(&pdev->dev));
1900                 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1901                                                 davinci_mcasp_tx_irq_handler,
1902                                                 IRQF_ONESHOT, irq_name, mcasp);
1903                 if (ret) {
1904                         dev_err(&pdev->dev, "TX IRQ request failed\n");
1905                         goto err;
1906                 }
1907 
1908                 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1909         }
1910 
1911         dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1912         if (dat)
1913                 mcasp->dat_port = true;
1914 
1915         dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1916         if (dat)
1917                 dma_data->addr = dat->start;
1918         else
1919                 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
1920 
1921         dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1922         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1923         if (res)
1924                 *dma = res->start;
1925         else
1926                 *dma = pdata->tx_dma_channel;
1927 
1928         /* dmaengine filter data for DT and non-DT boot */
1929         if (pdev->dev.of_node)
1930                 dma_data->filter_data = "tx";
1931         else
1932                 dma_data->filter_data = dma;
1933 
1934         /* RX is not valid in DIT mode */
1935         if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1936                 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1937                 if (dat)
1938                         dma_data->addr = dat->start;
1939                 else
1940                         dma_data->addr =
1941                                 mem->start + davinci_mcasp_rxdma_offset(pdata);
1942 
1943                 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1944                 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1945                 if (res)
1946                         *dma = res->start;
1947                 else
1948                         *dma = pdata->rx_dma_channel;
1949 
1950                 /* dmaengine filter data for DT and non-DT boot */
1951                 if (pdev->dev.of_node)
1952                         dma_data->filter_data = "rx";
1953                 else
1954                         dma_data->filter_data = dma;
1955         }
1956 
1957         if (mcasp->version < MCASP_VERSION_3) {
1958                 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1959                 /* dma_params->dma_addr is pointing to the data port address */
1960                 mcasp->dat_port = true;
1961         } else {
1962                 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1963         }
1964 
1965         /* Allocate memory for long enough list for all possible
1966          * scenarios. Maximum number tdm slots is 32 and there cannot
1967          * be more serializers than given in the configuration.  The
1968          * serializer directions could be taken into account, but it
1969          * would make code much more complex and save only couple of
1970          * bytes.
1971          */
1972         mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
1973                 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1974                              (32 + mcasp->num_serializer - 2),
1975                              GFP_KERNEL);
1976 
1977         mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
1978                 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1979                              (32 + mcasp->num_serializer - 2),
1980                              GFP_KERNEL);
1981 
1982         if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
1983             !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list)
1984                 return -ENOMEM;
1985 
1986         ret = davinci_mcasp_set_ch_constraints(mcasp);
1987         if (ret)
1988                 goto err;
1989 
1990         dev_set_drvdata(&pdev->dev, mcasp);
1991 
1992         mcasp_reparent_fck(pdev);
1993 
1994         ret = devm_snd_soc_register_component(&pdev->dev,
1995                                         &davinci_mcasp_component,
1996                                         &davinci_mcasp_dai[pdata->op_mode], 1);
1997 
1998         if (ret != 0)
1999                 goto err;
2000 
2001         ret = davinci_mcasp_get_dma_type(mcasp);
2002         switch (ret) {
2003         case PCM_EDMA:
2004 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
2005         (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2006          IS_MODULE(CONFIG_SND_EDMA_SOC))
2007                 ret = edma_pcm_platform_register(&pdev->dev);
2008 #else
2009                 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
2010                 ret = -EINVAL;
2011                 goto err;
2012 #endif
2013                 break;
2014         case PCM_SDMA:
2015 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
2016         (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2017          IS_MODULE(CONFIG_SND_OMAP_SOC))
2018                 ret = omap_pcm_platform_register(&pdev->dev);
2019 #else
2020                 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
2021                 ret = -EINVAL;
2022                 goto err;
2023 #endif
2024                 break;
2025         default:
2026                 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2027         case -EPROBE_DEFER:
2028                 goto err;
2029                 break;
2030         }
2031 
2032         if (ret) {
2033                 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2034                 goto err;
2035         }
2036 
2037         return 0;
2038 
2039 err:
2040         pm_runtime_disable(&pdev->dev);
2041         return ret;
2042 }
2043 
2044 static int davinci_mcasp_remove(struct platform_device *pdev)
2045 {
2046         pm_runtime_disable(&pdev->dev);
2047 
2048         return 0;
2049 }
2050 
2051 static struct platform_driver davinci_mcasp_driver = {
2052         .probe          = davinci_mcasp_probe,
2053         .remove         = davinci_mcasp_remove,
2054         .driver         = {
2055                 .name   = "davinci-mcasp",
2056                 .of_match_table = mcasp_dt_ids,
2057         },
2058 };
2059 
2060 module_platform_driver(davinci_mcasp_driver);
2061 
2062 MODULE_AUTHOR("Steve Chen");
2063 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2064 MODULE_LICENSE("GPL");
2065 

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