Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/sound/soc/davinci/davinci-mcasp.c

  1 /*
  2  * ALSA SoC McASP Audio Layer for TI DAVINCI processor
  3  *
  4  * Multi-channel Audio Serial Port Driver
  5  *
  6  * Author: Nirmal Pandey <n-pandey@ti.com>,
  7  *         Suresh Rajashekara <suresh.r@ti.com>
  8  *         Steve Chen <schen@.mvista.com>
  9  *
 10  * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
 11  * Copyright:   (C) 2009  Texas Instruments, India
 12  *
 13  * This program is free software; you can redistribute it and/or modify
 14  * it under the terms of the GNU General Public License version 2 as
 15  * published by the Free Software Foundation.
 16  */
 17 
 18 #include <linux/init.h>
 19 #include <linux/module.h>
 20 #include <linux/device.h>
 21 #include <linux/slab.h>
 22 #include <linux/delay.h>
 23 #include <linux/io.h>
 24 #include <linux/clk.h>
 25 #include <linux/pm_runtime.h>
 26 #include <linux/of.h>
 27 #include <linux/of_platform.h>
 28 #include <linux/of_device.h>
 29 
 30 #include <sound/core.h>
 31 #include <sound/pcm.h>
 32 #include <sound/pcm_params.h>
 33 #include <sound/initval.h>
 34 #include <sound/soc.h>
 35 #include <sound/dmaengine_pcm.h>
 36 #include <sound/omap-pcm.h>
 37 
 38 #include "davinci-pcm.h"
 39 #include "davinci-mcasp.h"
 40 
 41 #define MCASP_MAX_AFIFO_DEPTH   64
 42 
 43 struct davinci_mcasp_context {
 44         u32     txfmtctl;
 45         u32     rxfmtctl;
 46         u32     txfmt;
 47         u32     rxfmt;
 48         u32     aclkxctl;
 49         u32     aclkrctl;
 50         u32     pdir;
 51 };
 52 
 53 struct davinci_mcasp {
 54         struct davinci_pcm_dma_params dma_params[2];
 55         struct snd_dmaengine_dai_dma_data dma_data[2];
 56         void __iomem *base;
 57         u32 fifo_base;
 58         struct device *dev;
 59 
 60         /* McASP specific data */
 61         int     tdm_slots;
 62         u8      op_mode;
 63         u8      num_serializer;
 64         u8      *serial_dir;
 65         u8      version;
 66         u16     bclk_lrclk_ratio;
 67         int     streams;
 68 
 69         int     sysclk_freq;
 70         bool    bclk_master;
 71 
 72         /* McASP FIFO related */
 73         u8      txnumevt;
 74         u8      rxnumevt;
 75 
 76         bool    dat_port;
 77 
 78 #ifdef CONFIG_PM_SLEEP
 79         struct davinci_mcasp_context context;
 80 #endif
 81 };
 82 
 83 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
 84                                   u32 val)
 85 {
 86         void __iomem *reg = mcasp->base + offset;
 87         __raw_writel(__raw_readl(reg) | val, reg);
 88 }
 89 
 90 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
 91                                   u32 val)
 92 {
 93         void __iomem *reg = mcasp->base + offset;
 94         __raw_writel((__raw_readl(reg) & ~(val)), reg);
 95 }
 96 
 97 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
 98                                   u32 val, u32 mask)
 99 {
100         void __iomem *reg = mcasp->base + offset;
101         __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
102 }
103 
104 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
105                                  u32 val)
106 {
107         __raw_writel(val, mcasp->base + offset);
108 }
109 
110 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
111 {
112         return (u32)__raw_readl(mcasp->base + offset);
113 }
114 
115 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
116 {
117         int i = 0;
118 
119         mcasp_set_bits(mcasp, ctl_reg, val);
120 
121         /* programming GBLCTL needs to read back from GBLCTL and verfiy */
122         /* loop count is to avoid the lock-up */
123         for (i = 0; i < 1000; i++) {
124                 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
125                         break;
126         }
127 
128         if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
129                 printk(KERN_ERR "GBLCTL write error\n");
130 }
131 
132 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
133 {
134         u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
135         u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
136 
137         return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
138 }
139 
140 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
141 {
142         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
143         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
144 
145         /*
146          * When ASYNC == 0 the transmit and receive sections operate
147          * synchronously from the transmit clock and frame sync. We need to make
148          * sure that the TX signlas are enabled when starting reception.
149          */
150         if (mcasp_is_synchronous(mcasp)) {
151                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
152                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
153         }
154 
155         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
156         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
157 
158         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
159         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
160         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
161 
162         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
163         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
164 
165         if (mcasp_is_synchronous(mcasp))
166                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
167 }
168 
169 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
170 {
171         u8 offset = 0, i;
172         u32 cnt;
173 
174         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
175         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
176         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
177         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
178 
179         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
180         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
181         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
182         for (i = 0; i < mcasp->num_serializer; i++) {
183                 if (mcasp->serial_dir[i] == TX_MODE) {
184                         offset = i;
185                         break;
186                 }
187         }
188 
189         /* wait for TX ready */
190         cnt = 0;
191         while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
192                  TXSTATE) && (cnt < 100000))
193                 cnt++;
194 
195         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
196 }
197 
198 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
199 {
200         u32 reg;
201 
202         mcasp->streams++;
203 
204         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
205                 if (mcasp->txnumevt) {  /* enable FIFO */
206                         reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
207                         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
208                         mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
209                 }
210                 mcasp_start_tx(mcasp);
211         } else {
212                 if (mcasp->rxnumevt) {  /* enable FIFO */
213                         reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
214                         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
215                         mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
216                 }
217                 mcasp_start_rx(mcasp);
218         }
219 }
220 
221 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
222 {
223         /*
224          * In synchronous mode stop the TX clocks if no other stream is
225          * running
226          */
227         if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
228                 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
229 
230         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
231         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
232 }
233 
234 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
235 {
236         u32 val = 0;
237 
238         /*
239          * In synchronous mode keep TX clocks running if the capture stream is
240          * still running.
241          */
242         if (mcasp_is_synchronous(mcasp) && mcasp->streams)
243                 val =  TXHCLKRST | TXCLKRST | TXFSRST;
244 
245         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
246         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
247 }
248 
249 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
250 {
251         u32 reg;
252 
253         mcasp->streams--;
254 
255         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
256                 if (mcasp->txnumevt) {  /* disable FIFO */
257                         reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
258                         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
259                 }
260                 mcasp_stop_tx(mcasp);
261         } else {
262                 if (mcasp->rxnumevt) {  /* disable FIFO */
263                         reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
264                         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
265                 }
266                 mcasp_stop_rx(mcasp);
267         }
268 }
269 
270 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
271                                          unsigned int fmt)
272 {
273         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
274         int ret = 0;
275         u32 data_delay;
276         bool fs_pol_rising;
277         bool inv_fs = false;
278 
279         pm_runtime_get_sync(mcasp->dev);
280         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
281         case SND_SOC_DAIFMT_DSP_A:
282                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
283                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
284                 /* 1st data bit occur one ACLK cycle after the frame sync */
285                 data_delay = 1;
286                 break;
287         case SND_SOC_DAIFMT_DSP_B:
288         case SND_SOC_DAIFMT_AC97:
289                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
290                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
291                 /* No delay after FS */
292                 data_delay = 0;
293                 break;
294         case SND_SOC_DAIFMT_I2S:
295                 /* configure a full-word SYNC pulse (LRCLK) */
296                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
297                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
298                 /* 1st data bit occur one ACLK cycle after the frame sync */
299                 data_delay = 1;
300                 /* FS need to be inverted */
301                 inv_fs = true;
302                 break;
303         case SND_SOC_DAIFMT_LEFT_J:
304                 /* configure a full-word SYNC pulse (LRCLK) */
305                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
306                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
307                 /* No delay after FS */
308                 data_delay = 0;
309                 break;
310         default:
311                 ret = -EINVAL;
312                 goto out;
313         }
314 
315         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
316                        FSXDLY(3));
317         mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
318                        FSRDLY(3));
319 
320         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
321         case SND_SOC_DAIFMT_CBS_CFS:
322                 /* codec is clock and frame slave */
323                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
324                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
325 
326                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
327                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
328 
329                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
330                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
331                 mcasp->bclk_master = 1;
332                 break;
333         case SND_SOC_DAIFMT_CBM_CFS:
334                 /* codec is clock master and frame slave */
335                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
336                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
337 
338                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
339                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
340 
341                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
342                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
343                 mcasp->bclk_master = 0;
344                 break;
345         case SND_SOC_DAIFMT_CBM_CFM:
346                 /* codec is clock and frame master */
347                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
348                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
349 
350                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
351                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
352 
353                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
354                                ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
355                 mcasp->bclk_master = 0;
356                 break;
357         default:
358                 ret = -EINVAL;
359                 goto out;
360         }
361 
362         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
363         case SND_SOC_DAIFMT_IB_NF:
364                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
365                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
366                 fs_pol_rising = true;
367                 break;
368         case SND_SOC_DAIFMT_NB_IF:
369                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
370                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
371                 fs_pol_rising = false;
372                 break;
373         case SND_SOC_DAIFMT_IB_IF:
374                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
375                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
376                 fs_pol_rising = false;
377                 break;
378         case SND_SOC_DAIFMT_NB_NF:
379                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
380                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
381                 fs_pol_rising = true;
382                 break;
383         default:
384                 ret = -EINVAL;
385                 goto out;
386         }
387 
388         if (inv_fs)
389                 fs_pol_rising = !fs_pol_rising;
390 
391         if (fs_pol_rising) {
392                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
393                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
394         } else {
395                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
396                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
397         }
398 out:
399         pm_runtime_put_sync(mcasp->dev);
400         return ret;
401 }
402 
403 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
404 {
405         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
406 
407         switch (div_id) {
408         case 0:         /* MCLK divider */
409                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
410                                AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
411                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
412                                AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
413                 break;
414 
415         case 1:         /* BCLK divider */
416                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
417                                ACLKXDIV(div - 1), ACLKXDIV_MASK);
418                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
419                                ACLKRDIV(div - 1), ACLKRDIV_MASK);
420                 break;
421 
422         case 2:         /* BCLK/LRCLK ratio */
423                 mcasp->bclk_lrclk_ratio = div;
424                 break;
425 
426         default:
427                 return -EINVAL;
428         }
429 
430         return 0;
431 }
432 
433 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
434                                     unsigned int freq, int dir)
435 {
436         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
437 
438         if (dir == SND_SOC_CLOCK_OUT) {
439                 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
440                 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
441                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
442         } else {
443                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
444                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
445                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
446         }
447 
448         mcasp->sysclk_freq = freq;
449 
450         return 0;
451 }
452 
453 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
454                                        int word_length)
455 {
456         u32 fmt;
457         u32 tx_rotate = (word_length / 4) & 0x7;
458         u32 rx_rotate = (32 - word_length) / 4;
459         u32 mask = (1ULL << word_length) - 1;
460 
461         /*
462          * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
463          * callback, take it into account here. That allows us to for example
464          * send 32 bits per channel to the codec, while only 16 of them carry
465          * audio payload.
466          * The clock ratio is given for a full period of data (for I2S format
467          * both left and right channels), so it has to be divided by number of
468          * tdm-slots (for I2S - divided by 2).
469          */
470         if (mcasp->bclk_lrclk_ratio)
471                 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
472 
473         /* mapping of the XSSZ bit-field as described in the datasheet */
474         fmt = (word_length >> 1) - 1;
475 
476         if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
477                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
478                                RXSSZ(0x0F));
479                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
480                                TXSSZ(0x0F));
481                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
482                                TXROT(7));
483                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
484                                RXROT(7));
485                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
486         }
487 
488         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
489 
490         return 0;
491 }
492 
493 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
494                                  int period_words, int channels)
495 {
496         struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream];
497         struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
498         int i;
499         u8 tx_ser = 0;
500         u8 rx_ser = 0;
501         u8 slots = mcasp->tdm_slots;
502         u8 max_active_serializers = (channels + slots - 1) / slots;
503         int active_serializers, numevt, n;
504         u32 reg;
505         /* Default configuration */
506         if (mcasp->version < MCASP_VERSION_3)
507                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
508 
509         /* All PINS as McASP */
510         mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
511 
512         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
513                 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
514                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
515         } else {
516                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
517                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
518         }
519 
520         for (i = 0; i < mcasp->num_serializer; i++) {
521                 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
522                                mcasp->serial_dir[i]);
523                 if (mcasp->serial_dir[i] == TX_MODE &&
524                                         tx_ser < max_active_serializers) {
525                         mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
526                         tx_ser++;
527                 } else if (mcasp->serial_dir[i] == RX_MODE &&
528                                         rx_ser < max_active_serializers) {
529                         mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
530                         rx_ser++;
531                 } else {
532                         mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
533                                        SRMOD_INACTIVE, SRMOD_MASK);
534                 }
535         }
536 
537         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
538                 active_serializers = tx_ser;
539                 numevt = mcasp->txnumevt;
540                 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
541         } else {
542                 active_serializers = rx_ser;
543                 numevt = mcasp->rxnumevt;
544                 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
545         }
546 
547         if (active_serializers < max_active_serializers) {
548                 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
549                          "enabled in mcasp (%d)\n", channels,
550                          active_serializers * slots);
551                 return -EINVAL;
552         }
553 
554         /* AFIFO is not in use */
555         if (!numevt) {
556                 /* Configure the burst size for platform drivers */
557                 if (active_serializers > 1) {
558                         /*
559                          * If more than one serializers are in use we have one
560                          * DMA request to provide data for all serializers.
561                          * For example if three serializers are enabled the DMA
562                          * need to transfer three words per DMA request.
563                          */
564                         dma_params->fifo_level = active_serializers;
565                         dma_data->maxburst = active_serializers;
566                 } else {
567                         dma_params->fifo_level = 0;
568                         dma_data->maxburst = 0;
569                 }
570                 return 0;
571         }
572 
573         if (period_words % active_serializers) {
574                 dev_err(mcasp->dev, "Invalid combination of period words and "
575                         "active serializers: %d, %d\n", period_words,
576                         active_serializers);
577                 return -EINVAL;
578         }
579 
580         /*
581          * Calculate the optimal AFIFO depth for platform side:
582          * The number of words for numevt need to be in steps of active
583          * serializers.
584          */
585         n = numevt % active_serializers;
586         if (n)
587                 numevt += (active_serializers - n);
588         while (period_words % numevt && numevt > 0)
589                 numevt -= active_serializers;
590         if (numevt <= 0)
591                 numevt = active_serializers;
592 
593         mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
594         mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
595 
596         /* Configure the burst size for platform drivers */
597         if (numevt == 1)
598                 numevt = 0;
599         dma_params->fifo_level = numevt;
600         dma_data->maxburst = numevt;
601 
602         return 0;
603 }
604 
605 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
606 {
607         int i, active_slots;
608         u32 mask = 0;
609         u32 busel = 0;
610 
611         if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
612                 dev_err(mcasp->dev, "tdm slot %d not supported\n",
613                         mcasp->tdm_slots);
614                 return -EINVAL;
615         }
616 
617         active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
618         for (i = 0; i < active_slots; i++)
619                 mask |= (1 << i);
620 
621         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
622 
623         if (!mcasp->dat_port)
624                 busel = TXSEL;
625 
626         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
627         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
628         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
629                        FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
630 
631         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
632         mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
633         mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
634                        FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
635 
636         return 0;
637 }
638 
639 /* S/PDIF */
640 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
641 {
642         /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
643            and LSB first */
644         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
645 
646         /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
647         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
648 
649         /* Set the TX tdm : for all the slots */
650         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
651 
652         /* Set the TX clock controls : div = 1 and internal */
653         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
654 
655         mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
656 
657         /* Only 44100 and 48000 are valid, both have the same setting */
658         mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
659 
660         /* Enable the DIT */
661         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
662 
663         return 0;
664 }
665 
666 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
667                                         struct snd_pcm_hw_params *params,
668                                         struct snd_soc_dai *cpu_dai)
669 {
670         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
671         struct davinci_pcm_dma_params *dma_params =
672                                         &mcasp->dma_params[substream->stream];
673         int word_length;
674         int channels = params_channels(params);
675         int period_size = params_period_size(params);
676         int ret;
677 
678         /* If mcasp is BCLK master we need to set BCLK divider */
679         if (mcasp->bclk_master) {
680                 unsigned int bclk_freq = snd_soc_params_to_bclk(params);
681                 if (mcasp->sysclk_freq % bclk_freq != 0) {
682                         dev_err(mcasp->dev, "Can't produce required BCLK\n");
683                         return -EINVAL;
684                 }
685                 davinci_mcasp_set_clkdiv(
686                         cpu_dai, 1, mcasp->sysclk_freq / bclk_freq);
687         }
688 
689         ret = mcasp_common_hw_param(mcasp, substream->stream,
690                                     period_size * channels, channels);
691         if (ret)
692                 return ret;
693 
694         if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
695                 ret = mcasp_dit_hw_param(mcasp);
696         else
697                 ret = mcasp_i2s_hw_param(mcasp, substream->stream);
698 
699         if (ret)
700                 return ret;
701 
702         switch (params_format(params)) {
703         case SNDRV_PCM_FORMAT_U8:
704         case SNDRV_PCM_FORMAT_S8:
705                 dma_params->data_type = 1;
706                 word_length = 8;
707                 break;
708 
709         case SNDRV_PCM_FORMAT_U16_LE:
710         case SNDRV_PCM_FORMAT_S16_LE:
711                 dma_params->data_type = 2;
712                 word_length = 16;
713                 break;
714 
715         case SNDRV_PCM_FORMAT_U24_3LE:
716         case SNDRV_PCM_FORMAT_S24_3LE:
717                 dma_params->data_type = 3;
718                 word_length = 24;
719                 break;
720 
721         case SNDRV_PCM_FORMAT_U24_LE:
722         case SNDRV_PCM_FORMAT_S24_LE:
723         case SNDRV_PCM_FORMAT_U32_LE:
724         case SNDRV_PCM_FORMAT_S32_LE:
725                 dma_params->data_type = 4;
726                 word_length = 32;
727                 break;
728 
729         default:
730                 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
731                 return -EINVAL;
732         }
733 
734         if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level)
735                 dma_params->acnt = 4;
736         else
737                 dma_params->acnt = dma_params->data_type;
738 
739         davinci_config_channel_size(mcasp, word_length);
740 
741         return 0;
742 }
743 
744 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
745                                      int cmd, struct snd_soc_dai *cpu_dai)
746 {
747         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
748         int ret = 0;
749 
750         switch (cmd) {
751         case SNDRV_PCM_TRIGGER_RESUME:
752         case SNDRV_PCM_TRIGGER_START:
753         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
754                 davinci_mcasp_start(mcasp, substream->stream);
755                 break;
756         case SNDRV_PCM_TRIGGER_SUSPEND:
757         case SNDRV_PCM_TRIGGER_STOP:
758         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
759                 davinci_mcasp_stop(mcasp, substream->stream);
760                 break;
761 
762         default:
763                 ret = -EINVAL;
764         }
765 
766         return ret;
767 }
768 
769 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
770         .trigger        = davinci_mcasp_trigger,
771         .hw_params      = davinci_mcasp_hw_params,
772         .set_fmt        = davinci_mcasp_set_dai_fmt,
773         .set_clkdiv     = davinci_mcasp_set_clkdiv,
774         .set_sysclk     = davinci_mcasp_set_sysclk,
775 };
776 
777 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
778 {
779         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
780 
781         if (mcasp->version == MCASP_VERSION_4) {
782                 /* Using dmaengine PCM */
783                 dai->playback_dma_data =
784                                 &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
785                 dai->capture_dma_data =
786                                 &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
787         } else {
788                 /* Using davinci-pcm */
789                 dai->playback_dma_data = mcasp->dma_params;
790                 dai->capture_dma_data = mcasp->dma_params;
791         }
792 
793         return 0;
794 }
795 
796 #ifdef CONFIG_PM_SLEEP
797 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
798 {
799         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
800         struct davinci_mcasp_context *context = &mcasp->context;
801 
802         context->txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
803         context->rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
804         context->txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
805         context->rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
806         context->aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
807         context->aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
808         context->pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
809 
810         return 0;
811 }
812 
813 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
814 {
815         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
816         struct davinci_mcasp_context *context = &mcasp->context;
817 
818         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, context->txfmtctl);
819         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, context->rxfmtctl);
820         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, context->txfmt);
821         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, context->rxfmt);
822         mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, context->aclkxctl);
823         mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, context->aclkrctl);
824         mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, context->pdir);
825 
826         return 0;
827 }
828 #else
829 #define davinci_mcasp_suspend NULL
830 #define davinci_mcasp_resume NULL
831 #endif
832 
833 #define DAVINCI_MCASP_RATES     SNDRV_PCM_RATE_8000_192000
834 
835 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
836                                 SNDRV_PCM_FMTBIT_U8 | \
837                                 SNDRV_PCM_FMTBIT_S16_LE | \
838                                 SNDRV_PCM_FMTBIT_U16_LE | \
839                                 SNDRV_PCM_FMTBIT_S24_LE | \
840                                 SNDRV_PCM_FMTBIT_U24_LE | \
841                                 SNDRV_PCM_FMTBIT_S24_3LE | \
842                                 SNDRV_PCM_FMTBIT_U24_3LE | \
843                                 SNDRV_PCM_FMTBIT_S32_LE | \
844                                 SNDRV_PCM_FMTBIT_U32_LE)
845 
846 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
847         {
848                 .name           = "davinci-mcasp.0",
849                 .probe          = davinci_mcasp_dai_probe,
850                 .suspend        = davinci_mcasp_suspend,
851                 .resume         = davinci_mcasp_resume,
852                 .playback       = {
853                         .channels_min   = 2,
854                         .channels_max   = 32 * 16,
855                         .rates          = DAVINCI_MCASP_RATES,
856                         .formats        = DAVINCI_MCASP_PCM_FMTS,
857                 },
858                 .capture        = {
859                         .channels_min   = 2,
860                         .channels_max   = 32 * 16,
861                         .rates          = DAVINCI_MCASP_RATES,
862                         .formats        = DAVINCI_MCASP_PCM_FMTS,
863                 },
864                 .ops            = &davinci_mcasp_dai_ops,
865 
866         },
867         {
868                 .name           = "davinci-mcasp.1",
869                 .probe          = davinci_mcasp_dai_probe,
870                 .playback       = {
871                         .channels_min   = 1,
872                         .channels_max   = 384,
873                         .rates          = DAVINCI_MCASP_RATES,
874                         .formats        = DAVINCI_MCASP_PCM_FMTS,
875                 },
876                 .ops            = &davinci_mcasp_dai_ops,
877         },
878 
879 };
880 
881 static const struct snd_soc_component_driver davinci_mcasp_component = {
882         .name           = "davinci-mcasp",
883 };
884 
885 /* Some HW specific values and defaults. The rest is filled in from DT. */
886 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
887         .tx_dma_offset = 0x400,
888         .rx_dma_offset = 0x400,
889         .asp_chan_q = EVENTQ_0,
890         .version = MCASP_VERSION_1,
891 };
892 
893 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
894         .tx_dma_offset = 0x2000,
895         .rx_dma_offset = 0x2000,
896         .asp_chan_q = EVENTQ_0,
897         .version = MCASP_VERSION_2,
898 };
899 
900 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
901         .tx_dma_offset = 0,
902         .rx_dma_offset = 0,
903         .asp_chan_q = EVENTQ_0,
904         .version = MCASP_VERSION_3,
905 };
906 
907 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
908         .tx_dma_offset = 0x200,
909         .rx_dma_offset = 0x284,
910         .asp_chan_q = EVENTQ_0,
911         .version = MCASP_VERSION_4,
912 };
913 
914 static const struct of_device_id mcasp_dt_ids[] = {
915         {
916                 .compatible = "ti,dm646x-mcasp-audio",
917                 .data = &dm646x_mcasp_pdata,
918         },
919         {
920                 .compatible = "ti,da830-mcasp-audio",
921                 .data = &da830_mcasp_pdata,
922         },
923         {
924                 .compatible = "ti,am33xx-mcasp-audio",
925                 .data = &am33xx_mcasp_pdata,
926         },
927         {
928                 .compatible = "ti,dra7-mcasp-audio",
929                 .data = &dra7_mcasp_pdata,
930         },
931         { /* sentinel */ }
932 };
933 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
934 
935 static int mcasp_reparent_fck(struct platform_device *pdev)
936 {
937         struct device_node *node = pdev->dev.of_node;
938         struct clk *gfclk, *parent_clk;
939         const char *parent_name;
940         int ret;
941 
942         if (!node)
943                 return 0;
944 
945         parent_name = of_get_property(node, "fck_parent", NULL);
946         if (!parent_name)
947                 return 0;
948 
949         gfclk = clk_get(&pdev->dev, "fck");
950         if (IS_ERR(gfclk)) {
951                 dev_err(&pdev->dev, "failed to get fck\n");
952                 return PTR_ERR(gfclk);
953         }
954 
955         parent_clk = clk_get(NULL, parent_name);
956         if (IS_ERR(parent_clk)) {
957                 dev_err(&pdev->dev, "failed to get parent clock\n");
958                 ret = PTR_ERR(parent_clk);
959                 goto err1;
960         }
961 
962         ret = clk_set_parent(gfclk, parent_clk);
963         if (ret) {
964                 dev_err(&pdev->dev, "failed to reparent fck\n");
965                 goto err2;
966         }
967 
968 err2:
969         clk_put(parent_clk);
970 err1:
971         clk_put(gfclk);
972         return ret;
973 }
974 
975 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
976                                                 struct platform_device *pdev)
977 {
978         struct device_node *np = pdev->dev.of_node;
979         struct davinci_mcasp_pdata *pdata = NULL;
980         const struct of_device_id *match =
981                         of_match_device(mcasp_dt_ids, &pdev->dev);
982         struct of_phandle_args dma_spec;
983 
984         const u32 *of_serial_dir32;
985         u32 val;
986         int i, ret = 0;
987 
988         if (pdev->dev.platform_data) {
989                 pdata = pdev->dev.platform_data;
990                 return pdata;
991         } else if (match) {
992                 pdata = (struct davinci_mcasp_pdata*) match->data;
993         } else {
994                 /* control shouldn't reach here. something is wrong */
995                 ret = -EINVAL;
996                 goto nodata;
997         }
998 
999         ret = of_property_read_u32(np, "op-mode", &val);
1000         if (ret >= 0)
1001                 pdata->op_mode = val;
1002 
1003         ret = of_property_read_u32(np, "tdm-slots", &val);
1004         if (ret >= 0) {
1005                 if (val < 2 || val > 32) {
1006                         dev_err(&pdev->dev,
1007                                 "tdm-slots must be in rage [2-32]\n");
1008                         ret = -EINVAL;
1009                         goto nodata;
1010                 }
1011 
1012                 pdata->tdm_slots = val;
1013         }
1014 
1015         of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1016         val /= sizeof(u32);
1017         if (of_serial_dir32) {
1018                 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1019                                                  (sizeof(*of_serial_dir) * val),
1020                                                  GFP_KERNEL);
1021                 if (!of_serial_dir) {
1022                         ret = -ENOMEM;
1023                         goto nodata;
1024                 }
1025 
1026                 for (i = 0; i < val; i++)
1027                         of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1028 
1029                 pdata->num_serializer = val;
1030                 pdata->serial_dir = of_serial_dir;
1031         }
1032 
1033         ret = of_property_match_string(np, "dma-names", "tx");
1034         if (ret < 0)
1035                 goto nodata;
1036 
1037         ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1038                                          &dma_spec);
1039         if (ret < 0)
1040                 goto nodata;
1041 
1042         pdata->tx_dma_channel = dma_spec.args[0];
1043 
1044         ret = of_property_match_string(np, "dma-names", "rx");
1045         if (ret < 0)
1046                 goto nodata;
1047 
1048         ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1049                                          &dma_spec);
1050         if (ret < 0)
1051                 goto nodata;
1052 
1053         pdata->rx_dma_channel = dma_spec.args[0];
1054 
1055         ret = of_property_read_u32(np, "tx-num-evt", &val);
1056         if (ret >= 0)
1057                 pdata->txnumevt = val;
1058 
1059         ret = of_property_read_u32(np, "rx-num-evt", &val);
1060         if (ret >= 0)
1061                 pdata->rxnumevt = val;
1062 
1063         ret = of_property_read_u32(np, "sram-size-playback", &val);
1064         if (ret >= 0)
1065                 pdata->sram_size_playback = val;
1066 
1067         ret = of_property_read_u32(np, "sram-size-capture", &val);
1068         if (ret >= 0)
1069                 pdata->sram_size_capture = val;
1070 
1071         return  pdata;
1072 
1073 nodata:
1074         if (ret < 0) {
1075                 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1076                         ret);
1077                 pdata = NULL;
1078         }
1079         return  pdata;
1080 }
1081 
1082 static int davinci_mcasp_probe(struct platform_device *pdev)
1083 {
1084         struct davinci_pcm_dma_params *dma_params;
1085         struct snd_dmaengine_dai_dma_data *dma_data;
1086         struct resource *mem, *ioarea, *res, *dat;
1087         struct davinci_mcasp_pdata *pdata;
1088         struct davinci_mcasp *mcasp;
1089         int ret;
1090 
1091         if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1092                 dev_err(&pdev->dev, "No platform data supplied\n");
1093                 return -EINVAL;
1094         }
1095 
1096         mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1097                            GFP_KERNEL);
1098         if (!mcasp)
1099                 return  -ENOMEM;
1100 
1101         pdata = davinci_mcasp_set_pdata_from_of(pdev);
1102         if (!pdata) {
1103                 dev_err(&pdev->dev, "no platform data\n");
1104                 return -EINVAL;
1105         }
1106 
1107         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1108         if (!mem) {
1109                 dev_warn(mcasp->dev,
1110                          "\"mpu\" mem resource not found, using index 0\n");
1111                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1112                 if (!mem) {
1113                         dev_err(&pdev->dev, "no mem resource?\n");
1114                         return -ENODEV;
1115                 }
1116         }
1117 
1118         ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1119                         resource_size(mem), pdev->name);
1120         if (!ioarea) {
1121                 dev_err(&pdev->dev, "Audio region already claimed\n");
1122                 return -EBUSY;
1123         }
1124 
1125         pm_runtime_enable(&pdev->dev);
1126 
1127         ret = pm_runtime_get_sync(&pdev->dev);
1128         if (IS_ERR_VALUE(ret)) {
1129                 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1130                 return ret;
1131         }
1132 
1133         mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1134         if (!mcasp->base) {
1135                 dev_err(&pdev->dev, "ioremap failed\n");
1136                 ret = -ENOMEM;
1137                 goto err;
1138         }
1139 
1140         mcasp->op_mode = pdata->op_mode;
1141         mcasp->tdm_slots = pdata->tdm_slots;
1142         mcasp->num_serializer = pdata->num_serializer;
1143         mcasp->serial_dir = pdata->serial_dir;
1144         mcasp->version = pdata->version;
1145         mcasp->txnumevt = pdata->txnumevt;
1146         mcasp->rxnumevt = pdata->rxnumevt;
1147 
1148         mcasp->dev = &pdev->dev;
1149 
1150         dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1151         if (dat)
1152                 mcasp->dat_port = true;
1153 
1154         dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1155         dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1156         dma_params->asp_chan_q = pdata->asp_chan_q;
1157         dma_params->ram_chan_q = pdata->ram_chan_q;
1158         dma_params->sram_pool = pdata->sram_pool;
1159         dma_params->sram_size = pdata->sram_size_playback;
1160         if (dat)
1161                 dma_params->dma_addr = dat->start;
1162         else
1163                 dma_params->dma_addr = mem->start + pdata->tx_dma_offset;
1164 
1165         /* Unconditional dmaengine stuff */
1166         dma_data->addr = dma_params->dma_addr;
1167 
1168         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1169         if (res)
1170                 dma_params->channel = res->start;
1171         else
1172                 dma_params->channel = pdata->tx_dma_channel;
1173 
1174         /* dmaengine filter data for DT and non-DT boot */
1175         if (pdev->dev.of_node)
1176                 dma_data->filter_data = "tx";
1177         else
1178                 dma_data->filter_data = &dma_params->channel;
1179 
1180         dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1181         dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1182         dma_params->asp_chan_q = pdata->asp_chan_q;
1183         dma_params->ram_chan_q = pdata->ram_chan_q;
1184         dma_params->sram_pool = pdata->sram_pool;
1185         dma_params->sram_size = pdata->sram_size_capture;
1186         if (dat)
1187                 dma_params->dma_addr = dat->start;
1188         else
1189                 dma_params->dma_addr = mem->start + pdata->rx_dma_offset;
1190 
1191         /* Unconditional dmaengine stuff */
1192         dma_data->addr = dma_params->dma_addr;
1193 
1194         if (mcasp->version < MCASP_VERSION_3) {
1195                 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1196                 /* dma_params->dma_addr is pointing to the data port address */
1197                 mcasp->dat_port = true;
1198         } else {
1199                 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1200         }
1201 
1202         res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1203         if (res)
1204                 dma_params->channel = res->start;
1205         else
1206                 dma_params->channel = pdata->rx_dma_channel;
1207 
1208         /* dmaengine filter data for DT and non-DT boot */
1209         if (pdev->dev.of_node)
1210                 dma_data->filter_data = "rx";
1211         else
1212                 dma_data->filter_data = &dma_params->channel;
1213 
1214         dev_set_drvdata(&pdev->dev, mcasp);
1215 
1216         mcasp_reparent_fck(pdev);
1217 
1218         ret = devm_snd_soc_register_component(&pdev->dev,
1219                                         &davinci_mcasp_component,
1220                                         &davinci_mcasp_dai[pdata->op_mode], 1);
1221 
1222         if (ret != 0)
1223                 goto err;
1224 
1225         switch (mcasp->version) {
1226         case MCASP_VERSION_1:
1227         case MCASP_VERSION_2:
1228         case MCASP_VERSION_3:
1229                 ret = davinci_soc_platform_register(&pdev->dev);
1230                 break;
1231         case MCASP_VERSION_4:
1232                 ret = omap_pcm_platform_register(&pdev->dev);
1233                 break;
1234         default:
1235                 dev_err(&pdev->dev, "Invalid McASP version: %d\n",
1236                         mcasp->version);
1237                 ret = -EINVAL;
1238                 break;
1239         }
1240 
1241         if (ret) {
1242                 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1243                 goto err;
1244         }
1245 
1246         return 0;
1247 
1248 err:
1249         pm_runtime_put_sync(&pdev->dev);
1250         pm_runtime_disable(&pdev->dev);
1251         return ret;
1252 }
1253 
1254 static int davinci_mcasp_remove(struct platform_device *pdev)
1255 {
1256         pm_runtime_put_sync(&pdev->dev);
1257         pm_runtime_disable(&pdev->dev);
1258 
1259         return 0;
1260 }
1261 
1262 static struct platform_driver davinci_mcasp_driver = {
1263         .probe          = davinci_mcasp_probe,
1264         .remove         = davinci_mcasp_remove,
1265         .driver         = {
1266                 .name   = "davinci-mcasp",
1267                 .owner  = THIS_MODULE,
1268                 .of_match_table = mcasp_dt_ids,
1269         },
1270 };
1271 
1272 module_platform_driver(davinci_mcasp_driver);
1273 
1274 MODULE_AUTHOR("Steve Chen");
1275 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1276 MODULE_LICENSE("GPL");
1277 

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