Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/sound/soc/davinci/davinci-mcasp.c

  1 /*
  2  * ALSA SoC McASP Audio Layer for TI DAVINCI processor
  3  *
  4  * Multi-channel Audio Serial Port Driver
  5  *
  6  * Author: Nirmal Pandey <n-pandey@ti.com>,
  7  *         Suresh Rajashekara <suresh.r@ti.com>
  8  *         Steve Chen <schen@.mvista.com>
  9  *
 10  * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
 11  * Copyright:   (C) 2009  Texas Instruments, India
 12  *
 13  * This program is free software; you can redistribute it and/or modify
 14  * it under the terms of the GNU General Public License version 2 as
 15  * published by the Free Software Foundation.
 16  */
 17 
 18 #include <linux/init.h>
 19 #include <linux/module.h>
 20 #include <linux/device.h>
 21 #include <linux/slab.h>
 22 #include <linux/delay.h>
 23 #include <linux/io.h>
 24 #include <linux/clk.h>
 25 #include <linux/pm_runtime.h>
 26 #include <linux/of.h>
 27 #include <linux/of_platform.h>
 28 #include <linux/of_device.h>
 29 
 30 #include <sound/asoundef.h>
 31 #include <sound/core.h>
 32 #include <sound/pcm.h>
 33 #include <sound/pcm_params.h>
 34 #include <sound/initval.h>
 35 #include <sound/soc.h>
 36 #include <sound/dmaengine_pcm.h>
 37 #include <sound/omap-pcm.h>
 38 
 39 #include "davinci-pcm.h"
 40 #include "edma-pcm.h"
 41 #include "davinci-mcasp.h"
 42 
 43 #define MCASP_MAX_AFIFO_DEPTH   64
 44 
 45 struct davinci_mcasp_context {
 46         u32     txfmtctl;
 47         u32     rxfmtctl;
 48         u32     txfmt;
 49         u32     rxfmt;
 50         u32     aclkxctl;
 51         u32     aclkrctl;
 52         u32     pdir;
 53 };
 54 
 55 struct davinci_mcasp {
 56         struct davinci_pcm_dma_params dma_params[2];
 57         struct snd_dmaengine_dai_dma_data dma_data[2];
 58         void __iomem *base;
 59         u32 fifo_base;
 60         struct device *dev;
 61 
 62         /* McASP specific data */
 63         int     tdm_slots;
 64         u8      op_mode;
 65         u8      num_serializer;
 66         u8      *serial_dir;
 67         u8      version;
 68         u8      bclk_div;
 69         u16     bclk_lrclk_ratio;
 70         int     streams;
 71 
 72         int     sysclk_freq;
 73         bool    bclk_master;
 74 
 75         /* McASP FIFO related */
 76         u8      txnumevt;
 77         u8      rxnumevt;
 78 
 79         bool    dat_port;
 80 
 81 #ifdef CONFIG_PM_SLEEP
 82         struct davinci_mcasp_context context;
 83 #endif
 84 };
 85 
 86 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
 87                                   u32 val)
 88 {
 89         void __iomem *reg = mcasp->base + offset;
 90         __raw_writel(__raw_readl(reg) | val, reg);
 91 }
 92 
 93 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
 94                                   u32 val)
 95 {
 96         void __iomem *reg = mcasp->base + offset;
 97         __raw_writel((__raw_readl(reg) & ~(val)), reg);
 98 }
 99 
100 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
101                                   u32 val, u32 mask)
102 {
103         void __iomem *reg = mcasp->base + offset;
104         __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
105 }
106 
107 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
108                                  u32 val)
109 {
110         __raw_writel(val, mcasp->base + offset);
111 }
112 
113 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
114 {
115         return (u32)__raw_readl(mcasp->base + offset);
116 }
117 
118 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
119 {
120         int i = 0;
121 
122         mcasp_set_bits(mcasp, ctl_reg, val);
123 
124         /* programming GBLCTL needs to read back from GBLCTL and verfiy */
125         /* loop count is to avoid the lock-up */
126         for (i = 0; i < 1000; i++) {
127                 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
128                         break;
129         }
130 
131         if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
132                 printk(KERN_ERR "GBLCTL write error\n");
133 }
134 
135 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
136 {
137         u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
138         u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
139 
140         return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
141 }
142 
143 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
144 {
145         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
146         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
147 
148         /*
149          * When ASYNC == 0 the transmit and receive sections operate
150          * synchronously from the transmit clock and frame sync. We need to make
151          * sure that the TX signlas are enabled when starting reception.
152          */
153         if (mcasp_is_synchronous(mcasp)) {
154                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
155                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
156         }
157 
158         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
159         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
160 
161         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
162         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
163         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
164 
165         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
166         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
167 
168         if (mcasp_is_synchronous(mcasp))
169                 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
170 }
171 
172 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
173 {
174         u8 offset = 0, i;
175         u32 cnt;
176 
177         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
178         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
179         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
180         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
181 
182         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
183         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
184         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
185         for (i = 0; i < mcasp->num_serializer; i++) {
186                 if (mcasp->serial_dir[i] == TX_MODE) {
187                         offset = i;
188                         break;
189                 }
190         }
191 
192         /* wait for TX ready */
193         cnt = 0;
194         while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
195                  TXSTATE) && (cnt < 100000))
196                 cnt++;
197 
198         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
199 }
200 
201 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
202 {
203         u32 reg;
204 
205         mcasp->streams++;
206 
207         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
208                 if (mcasp->txnumevt) {  /* enable FIFO */
209                         reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
210                         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
211                         mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
212                 }
213                 mcasp_start_tx(mcasp);
214         } else {
215                 if (mcasp->rxnumevt) {  /* enable FIFO */
216                         reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
217                         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
218                         mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
219                 }
220                 mcasp_start_rx(mcasp);
221         }
222 }
223 
224 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
225 {
226         /*
227          * In synchronous mode stop the TX clocks if no other stream is
228          * running
229          */
230         if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
231                 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
232 
233         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
234         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
235 }
236 
237 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
238 {
239         u32 val = 0;
240 
241         /*
242          * In synchronous mode keep TX clocks running if the capture stream is
243          * still running.
244          */
245         if (mcasp_is_synchronous(mcasp) && mcasp->streams)
246                 val =  TXHCLKRST | TXCLKRST | TXFSRST;
247 
248         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
249         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
250 }
251 
252 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
253 {
254         u32 reg;
255 
256         mcasp->streams--;
257 
258         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
259                 if (mcasp->txnumevt) {  /* disable FIFO */
260                         reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
261                         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
262                 }
263                 mcasp_stop_tx(mcasp);
264         } else {
265                 if (mcasp->rxnumevt) {  /* disable FIFO */
266                         reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
267                         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
268                 }
269                 mcasp_stop_rx(mcasp);
270         }
271 }
272 
273 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
274                                          unsigned int fmt)
275 {
276         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
277         int ret = 0;
278         u32 data_delay;
279         bool fs_pol_rising;
280         bool inv_fs = false;
281 
282         pm_runtime_get_sync(mcasp->dev);
283         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
284         case SND_SOC_DAIFMT_DSP_A:
285                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
286                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
287                 /* 1st data bit occur one ACLK cycle after the frame sync */
288                 data_delay = 1;
289                 break;
290         case SND_SOC_DAIFMT_DSP_B:
291         case SND_SOC_DAIFMT_AC97:
292                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
293                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
294                 /* No delay after FS */
295                 data_delay = 0;
296                 break;
297         case SND_SOC_DAIFMT_I2S:
298                 /* configure a full-word SYNC pulse (LRCLK) */
299                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
300                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
301                 /* 1st data bit occur one ACLK cycle after the frame sync */
302                 data_delay = 1;
303                 /* FS need to be inverted */
304                 inv_fs = true;
305                 break;
306         case SND_SOC_DAIFMT_LEFT_J:
307                 /* configure a full-word SYNC pulse (LRCLK) */
308                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
309                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
310                 /* No delay after FS */
311                 data_delay = 0;
312                 break;
313         default:
314                 ret = -EINVAL;
315                 goto out;
316         }
317 
318         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
319                        FSXDLY(3));
320         mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
321                        FSRDLY(3));
322 
323         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
324         case SND_SOC_DAIFMT_CBS_CFS:
325                 /* codec is clock and frame slave */
326                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
327                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
328 
329                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
330                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
331 
332                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
333                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
334                 mcasp->bclk_master = 1;
335                 break;
336         case SND_SOC_DAIFMT_CBM_CFS:
337                 /* codec is clock master and frame slave */
338                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
339                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
340 
341                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
342                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
343 
344                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
345                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
346                 mcasp->bclk_master = 0;
347                 break;
348         case SND_SOC_DAIFMT_CBM_CFM:
349                 /* codec is clock and frame master */
350                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
351                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
352 
353                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
354                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
355 
356                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
357                                ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
358                 mcasp->bclk_master = 0;
359                 break;
360         default:
361                 ret = -EINVAL;
362                 goto out;
363         }
364 
365         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
366         case SND_SOC_DAIFMT_IB_NF:
367                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
368                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
369                 fs_pol_rising = true;
370                 break;
371         case SND_SOC_DAIFMT_NB_IF:
372                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
373                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
374                 fs_pol_rising = false;
375                 break;
376         case SND_SOC_DAIFMT_IB_IF:
377                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
378                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
379                 fs_pol_rising = false;
380                 break;
381         case SND_SOC_DAIFMT_NB_NF:
382                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
383                 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
384                 fs_pol_rising = true;
385                 break;
386         default:
387                 ret = -EINVAL;
388                 goto out;
389         }
390 
391         if (inv_fs)
392                 fs_pol_rising = !fs_pol_rising;
393 
394         if (fs_pol_rising) {
395                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
396                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
397         } else {
398                 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
399                 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
400         }
401 out:
402         pm_runtime_put_sync(mcasp->dev);
403         return ret;
404 }
405 
406 static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
407                                       int div, bool explicit)
408 {
409         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
410 
411         switch (div_id) {
412         case 0:         /* MCLK divider */
413                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
414                                AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
415                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
416                                AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
417                 break;
418 
419         case 1:         /* BCLK divider */
420                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
421                                ACLKXDIV(div - 1), ACLKXDIV_MASK);
422                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
423                                ACLKRDIV(div - 1), ACLKRDIV_MASK);
424                 if (explicit)
425                         mcasp->bclk_div = div;
426                 break;
427 
428         case 2:         /* BCLK/LRCLK ratio */
429                 mcasp->bclk_lrclk_ratio = div;
430                 break;
431 
432         default:
433                 return -EINVAL;
434         }
435 
436         return 0;
437 }
438 
439 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
440                                     int div)
441 {
442         return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
443 }
444 
445 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
446                                     unsigned int freq, int dir)
447 {
448         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
449 
450         if (dir == SND_SOC_CLOCK_OUT) {
451                 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
452                 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
453                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
454         } else {
455                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
456                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
457                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
458         }
459 
460         mcasp->sysclk_freq = freq;
461 
462         return 0;
463 }
464 
465 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
466                                        int word_length)
467 {
468         u32 fmt;
469         u32 tx_rotate = (word_length / 4) & 0x7;
470         u32 mask = (1ULL << word_length) - 1;
471         /*
472          * For captured data we should not rotate, inversion and masking is
473          * enoguh to get the data to the right position:
474          * Format         data from bus         after reverse (XRBUF)
475          * S16_LE:      |LSB|MSB|xxx|xxx|       |xxx|xxx|MSB|LSB|
476          * S24_3LE:     |LSB|DAT|MSB|xxx|       |xxx|MSB|DAT|LSB|
477          * S24_LE:      |LSB|DAT|MSB|xxx|       |xxx|MSB|DAT|LSB|
478          * S32_LE:      |LSB|DAT|DAT|MSB|       |MSB|DAT|DAT|LSB|
479          */
480         u32 rx_rotate = 0;
481 
482         /*
483          * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
484          * callback, take it into account here. That allows us to for example
485          * send 32 bits per channel to the codec, while only 16 of them carry
486          * audio payload.
487          * The clock ratio is given for a full period of data (for I2S format
488          * both left and right channels), so it has to be divided by number of
489          * tdm-slots (for I2S - divided by 2).
490          */
491         if (mcasp->bclk_lrclk_ratio)
492                 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
493 
494         /* mapping of the XSSZ bit-field as described in the datasheet */
495         fmt = (word_length >> 1) - 1;
496 
497         if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
498                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
499                                RXSSZ(0x0F));
500                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
501                                TXSSZ(0x0F));
502                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
503                                TXROT(7));
504                 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
505                                RXROT(7));
506                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
507         }
508 
509         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
510 
511         return 0;
512 }
513 
514 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
515                                  int period_words, int channels)
516 {
517         struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream];
518         struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
519         int i;
520         u8 tx_ser = 0;
521         u8 rx_ser = 0;
522         u8 slots = mcasp->tdm_slots;
523         u8 max_active_serializers = (channels + slots - 1) / slots;
524         int active_serializers, numevt, n;
525         u32 reg;
526         /* Default configuration */
527         if (mcasp->version < MCASP_VERSION_3)
528                 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
529 
530         /* All PINS as McASP */
531         mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
532 
533         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
534                 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
535                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
536         } else {
537                 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
538                 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
539         }
540 
541         for (i = 0; i < mcasp->num_serializer; i++) {
542                 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
543                                mcasp->serial_dir[i]);
544                 if (mcasp->serial_dir[i] == TX_MODE &&
545                                         tx_ser < max_active_serializers) {
546                         mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
547                         tx_ser++;
548                 } else if (mcasp->serial_dir[i] == RX_MODE &&
549                                         rx_ser < max_active_serializers) {
550                         mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
551                         rx_ser++;
552                 } else {
553                         mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
554                                        SRMOD_INACTIVE, SRMOD_MASK);
555                 }
556         }
557 
558         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
559                 active_serializers = tx_ser;
560                 numevt = mcasp->txnumevt;
561                 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
562         } else {
563                 active_serializers = rx_ser;
564                 numevt = mcasp->rxnumevt;
565                 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
566         }
567 
568         if (active_serializers < max_active_serializers) {
569                 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
570                          "enabled in mcasp (%d)\n", channels,
571                          active_serializers * slots);
572                 return -EINVAL;
573         }
574 
575         /* AFIFO is not in use */
576         if (!numevt) {
577                 /* Configure the burst size for platform drivers */
578                 if (active_serializers > 1) {
579                         /*
580                          * If more than one serializers are in use we have one
581                          * DMA request to provide data for all serializers.
582                          * For example if three serializers are enabled the DMA
583                          * need to transfer three words per DMA request.
584                          */
585                         dma_params->fifo_level = active_serializers;
586                         dma_data->maxburst = active_serializers;
587                 } else {
588                         dma_params->fifo_level = 0;
589                         dma_data->maxburst = 0;
590                 }
591                 return 0;
592         }
593 
594         if (period_words % active_serializers) {
595                 dev_err(mcasp->dev, "Invalid combination of period words and "
596                         "active serializers: %d, %d\n", period_words,
597                         active_serializers);
598                 return -EINVAL;
599         }
600 
601         /*
602          * Calculate the optimal AFIFO depth for platform side:
603          * The number of words for numevt need to be in steps of active
604          * serializers.
605          */
606         n = numevt % active_serializers;
607         if (n)
608                 numevt += (active_serializers - n);
609         while (period_words % numevt && numevt > 0)
610                 numevt -= active_serializers;
611         if (numevt <= 0)
612                 numevt = active_serializers;
613 
614         mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
615         mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
616 
617         /* Configure the burst size for platform drivers */
618         if (numevt == 1)
619                 numevt = 0;
620         dma_params->fifo_level = numevt;
621         dma_data->maxburst = numevt;
622 
623         return 0;
624 }
625 
626 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
627 {
628         int i, active_slots;
629         u32 mask = 0;
630         u32 busel = 0;
631 
632         if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
633                 dev_err(mcasp->dev, "tdm slot %d not supported\n",
634                         mcasp->tdm_slots);
635                 return -EINVAL;
636         }
637 
638         active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
639         for (i = 0; i < active_slots; i++)
640                 mask |= (1 << i);
641 
642         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
643 
644         if (!mcasp->dat_port)
645                 busel = TXSEL;
646 
647         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
648         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
649         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
650                        FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
651 
652         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
653         mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
654         mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
655                        FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
656 
657         return 0;
658 }
659 
660 /* S/PDIF */
661 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
662                               unsigned int rate)
663 {
664         u32 cs_value = 0;
665         u8 *cs_bytes = (u8*) &cs_value;
666 
667         /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
668            and LSB first */
669         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
670 
671         /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
672         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
673 
674         /* Set the TX tdm : for all the slots */
675         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
676 
677         /* Set the TX clock controls : div = 1 and internal */
678         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
679 
680         mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
681 
682         /* Only 44100 and 48000 are valid, both have the same setting */
683         mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
684 
685         /* Enable the DIT */
686         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
687 
688         /* Set S/PDIF channel status bits */
689         cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
690         cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
691 
692         switch (rate) {
693         case 22050:
694                 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
695                 break;
696         case 24000:
697                 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
698                 break;
699         case 32000:
700                 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
701                 break;
702         case 44100:
703                 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
704                 break;
705         case 48000:
706                 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
707                 break;
708         case 88200:
709                 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
710                 break;
711         case 96000:
712                 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
713                 break;
714         case 176400:
715                 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
716                 break;
717         case 192000:
718                 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
719                 break;
720         default:
721                 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
722                 return -EINVAL;
723         }
724 
725         mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
726         mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
727 
728         return 0;
729 }
730 
731 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
732                                         struct snd_pcm_hw_params *params,
733                                         struct snd_soc_dai *cpu_dai)
734 {
735         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
736         struct davinci_pcm_dma_params *dma_params =
737                                         &mcasp->dma_params[substream->stream];
738         int word_length;
739         int channels = params_channels(params);
740         int period_size = params_period_size(params);
741         int ret;
742 
743         /*
744          * If mcasp is BCLK master, and a BCLK divider was not provided by
745          * the machine driver, we need to calculate the ratio.
746          */
747         if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
748                 unsigned int bclk_freq = snd_soc_params_to_bclk(params);
749                 unsigned int div = mcasp->sysclk_freq / bclk_freq;
750                 if (mcasp->sysclk_freq % bclk_freq != 0) {
751                         if (((mcasp->sysclk_freq / div) - bclk_freq) >
752                             (bclk_freq - (mcasp->sysclk_freq / (div+1))))
753                                 div++;
754                         dev_warn(mcasp->dev,
755                                  "Inaccurate BCLK: %u Hz / %u != %u Hz\n",
756                                  mcasp->sysclk_freq, div, bclk_freq);
757                 }
758                 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
759         }
760 
761         ret = mcasp_common_hw_param(mcasp, substream->stream,
762                                     period_size * channels, channels);
763         if (ret)
764                 return ret;
765 
766         if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
767                 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
768         else
769                 ret = mcasp_i2s_hw_param(mcasp, substream->stream);
770 
771         if (ret)
772                 return ret;
773 
774         switch (params_format(params)) {
775         case SNDRV_PCM_FORMAT_U8:
776         case SNDRV_PCM_FORMAT_S8:
777                 dma_params->data_type = 1;
778                 word_length = 8;
779                 break;
780 
781         case SNDRV_PCM_FORMAT_U16_LE:
782         case SNDRV_PCM_FORMAT_S16_LE:
783                 dma_params->data_type = 2;
784                 word_length = 16;
785                 break;
786 
787         case SNDRV_PCM_FORMAT_U24_3LE:
788         case SNDRV_PCM_FORMAT_S24_3LE:
789                 dma_params->data_type = 3;
790                 word_length = 24;
791                 break;
792 
793         case SNDRV_PCM_FORMAT_U24_LE:
794         case SNDRV_PCM_FORMAT_S24_LE:
795                 dma_params->data_type = 4;
796                 word_length = 24;
797                 break;
798 
799         case SNDRV_PCM_FORMAT_U32_LE:
800         case SNDRV_PCM_FORMAT_S32_LE:
801                 dma_params->data_type = 4;
802                 word_length = 32;
803                 break;
804 
805         default:
806                 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
807                 return -EINVAL;
808         }
809 
810         if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level)
811                 dma_params->acnt = 4;
812         else
813                 dma_params->acnt = dma_params->data_type;
814 
815         davinci_config_channel_size(mcasp, word_length);
816 
817         return 0;
818 }
819 
820 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
821                                      int cmd, struct snd_soc_dai *cpu_dai)
822 {
823         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
824         int ret = 0;
825 
826         switch (cmd) {
827         case SNDRV_PCM_TRIGGER_RESUME:
828         case SNDRV_PCM_TRIGGER_START:
829         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
830                 davinci_mcasp_start(mcasp, substream->stream);
831                 break;
832         case SNDRV_PCM_TRIGGER_SUSPEND:
833         case SNDRV_PCM_TRIGGER_STOP:
834         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
835                 davinci_mcasp_stop(mcasp, substream->stream);
836                 break;
837 
838         default:
839                 ret = -EINVAL;
840         }
841 
842         return ret;
843 }
844 
845 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
846         .trigger        = davinci_mcasp_trigger,
847         .hw_params      = davinci_mcasp_hw_params,
848         .set_fmt        = davinci_mcasp_set_dai_fmt,
849         .set_clkdiv     = davinci_mcasp_set_clkdiv,
850         .set_sysclk     = davinci_mcasp_set_sysclk,
851 };
852 
853 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
854 {
855         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
856 
857         if (mcasp->version >= MCASP_VERSION_3) {
858                 /* Using dmaengine PCM */
859                 dai->playback_dma_data =
860                                 &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
861                 dai->capture_dma_data =
862                                 &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
863         } else {
864                 /* Using davinci-pcm */
865                 dai->playback_dma_data = mcasp->dma_params;
866                 dai->capture_dma_data = mcasp->dma_params;
867         }
868 
869         return 0;
870 }
871 
872 #ifdef CONFIG_PM_SLEEP
873 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
874 {
875         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
876         struct davinci_mcasp_context *context = &mcasp->context;
877 
878         context->txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
879         context->rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
880         context->txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
881         context->rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
882         context->aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
883         context->aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
884         context->pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
885 
886         return 0;
887 }
888 
889 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
890 {
891         struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
892         struct davinci_mcasp_context *context = &mcasp->context;
893 
894         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, context->txfmtctl);
895         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, context->rxfmtctl);
896         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, context->txfmt);
897         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, context->rxfmt);
898         mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, context->aclkxctl);
899         mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, context->aclkrctl);
900         mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, context->pdir);
901 
902         return 0;
903 }
904 #else
905 #define davinci_mcasp_suspend NULL
906 #define davinci_mcasp_resume NULL
907 #endif
908 
909 #define DAVINCI_MCASP_RATES     SNDRV_PCM_RATE_8000_192000
910 
911 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
912                                 SNDRV_PCM_FMTBIT_U8 | \
913                                 SNDRV_PCM_FMTBIT_S16_LE | \
914                                 SNDRV_PCM_FMTBIT_U16_LE | \
915                                 SNDRV_PCM_FMTBIT_S24_LE | \
916                                 SNDRV_PCM_FMTBIT_U24_LE | \
917                                 SNDRV_PCM_FMTBIT_S24_3LE | \
918                                 SNDRV_PCM_FMTBIT_U24_3LE | \
919                                 SNDRV_PCM_FMTBIT_S32_LE | \
920                                 SNDRV_PCM_FMTBIT_U32_LE)
921 
922 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
923         {
924                 .name           = "davinci-mcasp.0",
925                 .probe          = davinci_mcasp_dai_probe,
926                 .suspend        = davinci_mcasp_suspend,
927                 .resume         = davinci_mcasp_resume,
928                 .playback       = {
929                         .channels_min   = 2,
930                         .channels_max   = 32 * 16,
931                         .rates          = DAVINCI_MCASP_RATES,
932                         .formats        = DAVINCI_MCASP_PCM_FMTS,
933                 },
934                 .capture        = {
935                         .channels_min   = 2,
936                         .channels_max   = 32 * 16,
937                         .rates          = DAVINCI_MCASP_RATES,
938                         .formats        = DAVINCI_MCASP_PCM_FMTS,
939                 },
940                 .ops            = &davinci_mcasp_dai_ops,
941 
942         },
943         {
944                 .name           = "davinci-mcasp.1",
945                 .probe          = davinci_mcasp_dai_probe,
946                 .playback       = {
947                         .channels_min   = 1,
948                         .channels_max   = 384,
949                         .rates          = DAVINCI_MCASP_RATES,
950                         .formats        = DAVINCI_MCASP_PCM_FMTS,
951                 },
952                 .ops            = &davinci_mcasp_dai_ops,
953         },
954 
955 };
956 
957 static const struct snd_soc_component_driver davinci_mcasp_component = {
958         .name           = "davinci-mcasp",
959 };
960 
961 /* Some HW specific values and defaults. The rest is filled in from DT. */
962 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
963         .tx_dma_offset = 0x400,
964         .rx_dma_offset = 0x400,
965         .asp_chan_q = EVENTQ_0,
966         .version = MCASP_VERSION_1,
967 };
968 
969 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
970         .tx_dma_offset = 0x2000,
971         .rx_dma_offset = 0x2000,
972         .asp_chan_q = EVENTQ_0,
973         .version = MCASP_VERSION_2,
974 };
975 
976 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
977         .tx_dma_offset = 0,
978         .rx_dma_offset = 0,
979         .asp_chan_q = EVENTQ_0,
980         .version = MCASP_VERSION_3,
981 };
982 
983 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
984         .tx_dma_offset = 0x200,
985         .rx_dma_offset = 0x284,
986         .asp_chan_q = EVENTQ_0,
987         .version = MCASP_VERSION_4,
988 };
989 
990 static const struct of_device_id mcasp_dt_ids[] = {
991         {
992                 .compatible = "ti,dm646x-mcasp-audio",
993                 .data = &dm646x_mcasp_pdata,
994         },
995         {
996                 .compatible = "ti,da830-mcasp-audio",
997                 .data = &da830_mcasp_pdata,
998         },
999         {
1000                 .compatible = "ti,am33xx-mcasp-audio",
1001                 .data = &am33xx_mcasp_pdata,
1002         },
1003         {
1004                 .compatible = "ti,dra7-mcasp-audio",
1005                 .data = &dra7_mcasp_pdata,
1006         },
1007         { /* sentinel */ }
1008 };
1009 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1010 
1011 static int mcasp_reparent_fck(struct platform_device *pdev)
1012 {
1013         struct device_node *node = pdev->dev.of_node;
1014         struct clk *gfclk, *parent_clk;
1015         const char *parent_name;
1016         int ret;
1017 
1018         if (!node)
1019                 return 0;
1020 
1021         parent_name = of_get_property(node, "fck_parent", NULL);
1022         if (!parent_name)
1023                 return 0;
1024 
1025         gfclk = clk_get(&pdev->dev, "fck");
1026         if (IS_ERR(gfclk)) {
1027                 dev_err(&pdev->dev, "failed to get fck\n");
1028                 return PTR_ERR(gfclk);
1029         }
1030 
1031         parent_clk = clk_get(NULL, parent_name);
1032         if (IS_ERR(parent_clk)) {
1033                 dev_err(&pdev->dev, "failed to get parent clock\n");
1034                 ret = PTR_ERR(parent_clk);
1035                 goto err1;
1036         }
1037 
1038         ret = clk_set_parent(gfclk, parent_clk);
1039         if (ret) {
1040                 dev_err(&pdev->dev, "failed to reparent fck\n");
1041                 goto err2;
1042         }
1043 
1044 err2:
1045         clk_put(parent_clk);
1046 err1:
1047         clk_put(gfclk);
1048         return ret;
1049 }
1050 
1051 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1052                                                 struct platform_device *pdev)
1053 {
1054         struct device_node *np = pdev->dev.of_node;
1055         struct davinci_mcasp_pdata *pdata = NULL;
1056         const struct of_device_id *match =
1057                         of_match_device(mcasp_dt_ids, &pdev->dev);
1058         struct of_phandle_args dma_spec;
1059 
1060         const u32 *of_serial_dir32;
1061         u32 val;
1062         int i, ret = 0;
1063 
1064         if (pdev->dev.platform_data) {
1065                 pdata = pdev->dev.platform_data;
1066                 return pdata;
1067         } else if (match) {
1068                 pdata = (struct davinci_mcasp_pdata*) match->data;
1069         } else {
1070                 /* control shouldn't reach here. something is wrong */
1071                 ret = -EINVAL;
1072                 goto nodata;
1073         }
1074 
1075         ret = of_property_read_u32(np, "op-mode", &val);
1076         if (ret >= 0)
1077                 pdata->op_mode = val;
1078 
1079         ret = of_property_read_u32(np, "tdm-slots", &val);
1080         if (ret >= 0) {
1081                 if (val < 2 || val > 32) {
1082                         dev_err(&pdev->dev,
1083                                 "tdm-slots must be in rage [2-32]\n");
1084                         ret = -EINVAL;
1085                         goto nodata;
1086                 }
1087 
1088                 pdata->tdm_slots = val;
1089         }
1090 
1091         of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1092         val /= sizeof(u32);
1093         if (of_serial_dir32) {
1094                 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1095                                                  (sizeof(*of_serial_dir) * val),
1096                                                  GFP_KERNEL);
1097                 if (!of_serial_dir) {
1098                         ret = -ENOMEM;
1099                         goto nodata;
1100                 }
1101 
1102                 for (i = 0; i < val; i++)
1103                         of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1104 
1105                 pdata->num_serializer = val;
1106                 pdata->serial_dir = of_serial_dir;
1107         }
1108 
1109         ret = of_property_match_string(np, "dma-names", "tx");
1110         if (ret < 0)
1111                 goto nodata;
1112 
1113         ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1114                                          &dma_spec);
1115         if (ret < 0)
1116                 goto nodata;
1117 
1118         pdata->tx_dma_channel = dma_spec.args[0];
1119 
1120         ret = of_property_match_string(np, "dma-names", "rx");
1121         if (ret < 0)
1122                 goto nodata;
1123 
1124         ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1125                                          &dma_spec);
1126         if (ret < 0)
1127                 goto nodata;
1128 
1129         pdata->rx_dma_channel = dma_spec.args[0];
1130 
1131         ret = of_property_read_u32(np, "tx-num-evt", &val);
1132         if (ret >= 0)
1133                 pdata->txnumevt = val;
1134 
1135         ret = of_property_read_u32(np, "rx-num-evt", &val);
1136         if (ret >= 0)
1137                 pdata->rxnumevt = val;
1138 
1139         ret = of_property_read_u32(np, "sram-size-playback", &val);
1140         if (ret >= 0)
1141                 pdata->sram_size_playback = val;
1142 
1143         ret = of_property_read_u32(np, "sram-size-capture", &val);
1144         if (ret >= 0)
1145                 pdata->sram_size_capture = val;
1146 
1147         return  pdata;
1148 
1149 nodata:
1150         if (ret < 0) {
1151                 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1152                         ret);
1153                 pdata = NULL;
1154         }
1155         return  pdata;
1156 }
1157 
1158 static int davinci_mcasp_probe(struct platform_device *pdev)
1159 {
1160         struct davinci_pcm_dma_params *dma_params;
1161         struct snd_dmaengine_dai_dma_data *dma_data;
1162         struct resource *mem, *ioarea, *res, *dat;
1163         struct davinci_mcasp_pdata *pdata;
1164         struct davinci_mcasp *mcasp;
1165         int ret;
1166 
1167         if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1168                 dev_err(&pdev->dev, "No platform data supplied\n");
1169                 return -EINVAL;
1170         }
1171 
1172         mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1173                            GFP_KERNEL);
1174         if (!mcasp)
1175                 return  -ENOMEM;
1176 
1177         pdata = davinci_mcasp_set_pdata_from_of(pdev);
1178         if (!pdata) {
1179                 dev_err(&pdev->dev, "no platform data\n");
1180                 return -EINVAL;
1181         }
1182 
1183         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1184         if (!mem) {
1185                 dev_warn(mcasp->dev,
1186                          "\"mpu\" mem resource not found, using index 0\n");
1187                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1188                 if (!mem) {
1189                         dev_err(&pdev->dev, "no mem resource?\n");
1190                         return -ENODEV;
1191                 }
1192         }
1193 
1194         ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1195                         resource_size(mem), pdev->name);
1196         if (!ioarea) {
1197                 dev_err(&pdev->dev, "Audio region already claimed\n");
1198                 return -EBUSY;
1199         }
1200 
1201         pm_runtime_enable(&pdev->dev);
1202 
1203         ret = pm_runtime_get_sync(&pdev->dev);
1204         if (IS_ERR_VALUE(ret)) {
1205                 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1206                 return ret;
1207         }
1208 
1209         mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1210         if (!mcasp->base) {
1211                 dev_err(&pdev->dev, "ioremap failed\n");
1212                 ret = -ENOMEM;
1213                 goto err;
1214         }
1215 
1216         mcasp->op_mode = pdata->op_mode;
1217         mcasp->tdm_slots = pdata->tdm_slots;
1218         mcasp->num_serializer = pdata->num_serializer;
1219         mcasp->serial_dir = pdata->serial_dir;
1220         mcasp->version = pdata->version;
1221         mcasp->txnumevt = pdata->txnumevt;
1222         mcasp->rxnumevt = pdata->rxnumevt;
1223 
1224         mcasp->dev = &pdev->dev;
1225 
1226         dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1227         if (dat)
1228                 mcasp->dat_port = true;
1229 
1230         dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1231         dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1232         dma_params->asp_chan_q = pdata->asp_chan_q;
1233         dma_params->ram_chan_q = pdata->ram_chan_q;
1234         dma_params->sram_pool = pdata->sram_pool;
1235         dma_params->sram_size = pdata->sram_size_playback;
1236         if (dat)
1237                 dma_params->dma_addr = dat->start;
1238         else
1239                 dma_params->dma_addr = mem->start + pdata->tx_dma_offset;
1240 
1241         /* Unconditional dmaengine stuff */
1242         dma_data->addr = dma_params->dma_addr;
1243 
1244         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1245         if (res)
1246                 dma_params->channel = res->start;
1247         else
1248                 dma_params->channel = pdata->tx_dma_channel;
1249 
1250         /* dmaengine filter data for DT and non-DT boot */
1251         if (pdev->dev.of_node)
1252                 dma_data->filter_data = "tx";
1253         else
1254                 dma_data->filter_data = &dma_params->channel;
1255 
1256         dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1257         dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1258         dma_params->asp_chan_q = pdata->asp_chan_q;
1259         dma_params->ram_chan_q = pdata->ram_chan_q;
1260         dma_params->sram_pool = pdata->sram_pool;
1261         dma_params->sram_size = pdata->sram_size_capture;
1262         if (dat)
1263                 dma_params->dma_addr = dat->start;
1264         else
1265                 dma_params->dma_addr = mem->start + pdata->rx_dma_offset;
1266 
1267         /* Unconditional dmaengine stuff */
1268         dma_data->addr = dma_params->dma_addr;
1269 
1270         if (mcasp->version < MCASP_VERSION_3) {
1271                 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1272                 /* dma_params->dma_addr is pointing to the data port address */
1273                 mcasp->dat_port = true;
1274         } else {
1275                 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1276         }
1277 
1278         res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1279         if (res)
1280                 dma_params->channel = res->start;
1281         else
1282                 dma_params->channel = pdata->rx_dma_channel;
1283 
1284         /* dmaengine filter data for DT and non-DT boot */
1285         if (pdev->dev.of_node)
1286                 dma_data->filter_data = "rx";
1287         else
1288                 dma_data->filter_data = &dma_params->channel;
1289 
1290         dev_set_drvdata(&pdev->dev, mcasp);
1291 
1292         mcasp_reparent_fck(pdev);
1293 
1294         ret = devm_snd_soc_register_component(&pdev->dev,
1295                                         &davinci_mcasp_component,
1296                                         &davinci_mcasp_dai[pdata->op_mode], 1);
1297 
1298         if (ret != 0)
1299                 goto err;
1300 
1301         switch (mcasp->version) {
1302 #if IS_BUILTIN(CONFIG_SND_DAVINCI_SOC) || \
1303         (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1304          IS_MODULE(CONFIG_SND_DAVINCI_SOC))
1305         case MCASP_VERSION_1:
1306         case MCASP_VERSION_2:
1307                 ret = davinci_soc_platform_register(&pdev->dev);
1308                 break;
1309 #endif
1310 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1311         (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1312          IS_MODULE(CONFIG_SND_EDMA_SOC))
1313         case MCASP_VERSION_3:
1314                 ret = edma_pcm_platform_register(&pdev->dev);
1315                 break;
1316 #endif
1317 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1318         (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1319          IS_MODULE(CONFIG_SND_OMAP_SOC))
1320         case MCASP_VERSION_4:
1321                 ret = omap_pcm_platform_register(&pdev->dev);
1322                 break;
1323 #endif
1324         default:
1325                 dev_err(&pdev->dev, "Invalid McASP version: %d\n",
1326                         mcasp->version);
1327                 ret = -EINVAL;
1328                 break;
1329         }
1330 
1331         if (ret) {
1332                 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1333                 goto err;
1334         }
1335 
1336         return 0;
1337 
1338 err:
1339         pm_runtime_put_sync(&pdev->dev);
1340         pm_runtime_disable(&pdev->dev);
1341         return ret;
1342 }
1343 
1344 static int davinci_mcasp_remove(struct platform_device *pdev)
1345 {
1346         pm_runtime_put_sync(&pdev->dev);
1347         pm_runtime_disable(&pdev->dev);
1348 
1349         return 0;
1350 }
1351 
1352 static struct platform_driver davinci_mcasp_driver = {
1353         .probe          = davinci_mcasp_probe,
1354         .remove         = davinci_mcasp_remove,
1355         .driver         = {
1356                 .name   = "davinci-mcasp",
1357                 .owner  = THIS_MODULE,
1358                 .of_match_table = mcasp_dt_ids,
1359         },
1360 };
1361 
1362 module_platform_driver(davinci_mcasp_driver);
1363 
1364 MODULE_AUTHOR("Steve Chen");
1365 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1366 MODULE_LICENSE("GPL");
1367 

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