Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/sound/soc/codecs/wm8994.c

  1 /*
  2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
  3  *
  4  * Copyright 2009-12 Wolfson Microelectronics plc
  5  *
  6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7  *
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 
 14 #include <linux/module.h>
 15 #include <linux/moduleparam.h>
 16 #include <linux/init.h>
 17 #include <linux/delay.h>
 18 #include <linux/pm.h>
 19 #include <linux/gcd.h>
 20 #include <linux/i2c.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/pm_runtime.h>
 23 #include <linux/regulator/consumer.h>
 24 #include <linux/slab.h>
 25 #include <sound/core.h>
 26 #include <sound/jack.h>
 27 #include <sound/pcm.h>
 28 #include <sound/pcm_params.h>
 29 #include <sound/soc.h>
 30 #include <sound/initval.h>
 31 #include <sound/tlv.h>
 32 #include <trace/events/asoc.h>
 33 
 34 #include <linux/mfd/wm8994/core.h>
 35 #include <linux/mfd/wm8994/registers.h>
 36 #include <linux/mfd/wm8994/pdata.h>
 37 #include <linux/mfd/wm8994/gpio.h>
 38 
 39 #include "wm8994.h"
 40 #include "wm_hubs.h"
 41 
 42 #define WM1811_JACKDET_MODE_NONE  0x0000
 43 #define WM1811_JACKDET_MODE_JACK  0x0100
 44 #define WM1811_JACKDET_MODE_MIC   0x0080
 45 #define WM1811_JACKDET_MODE_AUDIO 0x0180
 46 
 47 #define WM8994_NUM_DRC 3
 48 #define WM8994_NUM_EQ  3
 49 
 50 static struct {
 51         unsigned int reg;
 52         unsigned int mask;
 53 } wm8994_vu_bits[] = {
 54         { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
 55         { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
 56         { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
 57         { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
 58         { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
 59         { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
 60         { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
 61         { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
 62         { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
 63         { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
 64 
 65         { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
 66         { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
 67         { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
 68         { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
 69         { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
 70         { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
 71         { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
 72         { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
 73         { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
 74         { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
 75         { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
 76         { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
 77         { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
 78         { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
 79         { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
 80         { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
 81 };
 82 
 83 static int wm8994_drc_base[] = {
 84         WM8994_AIF1_DRC1_1,
 85         WM8994_AIF1_DRC2_1,
 86         WM8994_AIF2_DRC_1,
 87 };
 88 
 89 static int wm8994_retune_mobile_base[] = {
 90         WM8994_AIF1_DAC1_EQ_GAINS_1,
 91         WM8994_AIF1_DAC2_EQ_GAINS_1,
 92         WM8994_AIF2_EQ_GAINS_1,
 93 };
 94 
 95 static const struct wm8958_micd_rate micdet_rates[] = {
 96         { 32768,       true,  1, 4 },
 97         { 32768,       false, 1, 1 },
 98         { 44100 * 256, true,  7, 10 },
 99         { 44100 * 256, false, 7, 10 },
100 };
101 
102 static const struct wm8958_micd_rate jackdet_rates[] = {
103         { 32768,       true,  0, 1 },
104         { 32768,       false, 0, 1 },
105         { 44100 * 256, true,  10, 10 },
106         { 44100 * 256, false, 7, 8 },
107 };
108 
109 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110 {
111         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
112         struct wm8994 *control = wm8994->wm8994;
113         int best, i, sysclk, val;
114         bool idle;
115         const struct wm8958_micd_rate *rates;
116         int num_rates;
117 
118         idle = !wm8994->jack_mic;
119 
120         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121         if (sysclk & WM8994_SYSCLK_SRC)
122                 sysclk = wm8994->aifclk[1];
123         else
124                 sysclk = wm8994->aifclk[0];
125 
126         if (control->pdata.micd_rates) {
127                 rates = control->pdata.micd_rates;
128                 num_rates = control->pdata.num_micd_rates;
129         } else if (wm8994->jackdet) {
130                 rates = jackdet_rates;
131                 num_rates = ARRAY_SIZE(jackdet_rates);
132         } else {
133                 rates = micdet_rates;
134                 num_rates = ARRAY_SIZE(micdet_rates);
135         }
136 
137         best = 0;
138         for (i = 0; i < num_rates; i++) {
139                 if (rates[i].idle != idle)
140                         continue;
141                 if (abs(rates[i].sysclk - sysclk) <
142                     abs(rates[best].sysclk - sysclk))
143                         best = i;
144                 else if (rates[best].idle != idle)
145                         best = i;
146         }
147 
148         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
150 
151         dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152                 rates[best].start, rates[best].rate, sysclk,
153                 idle ? "idle" : "active");
154 
155         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156                             WM8958_MICD_BIAS_STARTTIME_MASK |
157                             WM8958_MICD_RATE_MASK, val);
158 }
159 
160 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161 {
162         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
163         int rate;
164         int reg1 = 0;
165         int offset;
166 
167         if (aif)
168                 offset = 4;
169         else
170                 offset = 0;
171 
172         switch (wm8994->sysclk[aif]) {
173         case WM8994_SYSCLK_MCLK1:
174                 rate = wm8994->mclk[0];
175                 break;
176 
177         case WM8994_SYSCLK_MCLK2:
178                 reg1 |= 0x8;
179                 rate = wm8994->mclk[1];
180                 break;
181 
182         case WM8994_SYSCLK_FLL1:
183                 reg1 |= 0x10;
184                 rate = wm8994->fll[0].out;
185                 break;
186 
187         case WM8994_SYSCLK_FLL2:
188                 reg1 |= 0x18;
189                 rate = wm8994->fll[1].out;
190                 break;
191 
192         default:
193                 return -EINVAL;
194         }
195 
196         if (rate >= 13500000) {
197                 rate /= 2;
198                 reg1 |= WM8994_AIF1CLK_DIV;
199 
200                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
201                         aif + 1, rate);
202         }
203 
204         wm8994->aifclk[aif] = rate;
205 
206         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208                             reg1);
209 
210         return 0;
211 }
212 
213 static int configure_clock(struct snd_soc_codec *codec)
214 {
215         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
216         int change, new;
217 
218         /* Bring up the AIF clocks first */
219         configure_aif_clock(codec, 0);
220         configure_aif_clock(codec, 1);
221 
222         /* Then switch CLK_SYS over to the higher of them; a change
223          * can only happen as a result of a clocking change which can
224          * only be made outside of DAPM so we can safely redo the
225          * clocking.
226          */
227 
228         /* If they're equal it doesn't matter which is used */
229         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230                 wm8958_micd_set_rate(codec);
231                 return 0;
232         }
233 
234         if (wm8994->aifclk[0] < wm8994->aifclk[1])
235                 new = WM8994_SYSCLK_SRC;
236         else
237                 new = 0;
238 
239         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240                                      WM8994_SYSCLK_SRC, new);
241         if (change)
242                 snd_soc_dapm_sync(&codec->dapm);
243 
244         wm8958_micd_set_rate(codec);
245 
246         return 0;
247 }
248 
249 static int check_clk_sys(struct snd_soc_dapm_widget *source,
250                          struct snd_soc_dapm_widget *sink)
251 {
252         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
253         const char *clk;
254 
255         /* Check what we're currently using for CLK_SYS */
256         if (reg & WM8994_SYSCLK_SRC)
257                 clk = "AIF2CLK";
258         else
259                 clk = "AIF1CLK";
260 
261         return strcmp(source->name, clk) == 0;
262 }
263 
264 static const char *sidetone_hpf_text[] = {
265         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
266 };
267 
268 static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
269                             WM8994_SIDETONE, 7, sidetone_hpf_text);
270 
271 static const char *adc_hpf_text[] = {
272         "HiFi", "Voice 1", "Voice 2", "Voice 3"
273 };
274 
275 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
276                             WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
277 
278 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
279                             WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
280 
281 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
282                             WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
283 
284 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
285 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
286 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
287 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
288 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
289 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
290 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
291 
292 #define WM8994_DRC_SWITCH(xname, reg, shift) \
293         SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
294                 snd_soc_get_volsw, wm8994_put_drc_sw)
295 
296 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
297                              struct snd_ctl_elem_value *ucontrol)
298 {
299         struct soc_mixer_control *mc =
300                 (struct soc_mixer_control *)kcontrol->private_value;
301         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
302         int mask, ret;
303 
304         /* Can't enable both ADC and DAC paths simultaneously */
305         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
306                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
307                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
308         else
309                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
310 
311         ret = snd_soc_read(codec, mc->reg);
312         if (ret < 0)
313                 return ret;
314         if (ret & mask)
315                 return -EINVAL;
316 
317         return snd_soc_put_volsw(kcontrol, ucontrol);
318 }
319 
320 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
321 {
322         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
323         struct wm8994 *control = wm8994->wm8994;
324         struct wm8994_pdata *pdata = &control->pdata;
325         int base = wm8994_drc_base[drc];
326         int cfg = wm8994->drc_cfg[drc];
327         int save, i;
328 
329         /* Save any enables; the configuration should clear them. */
330         save = snd_soc_read(codec, base);
331         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
332                 WM8994_AIF1ADC1R_DRC_ENA;
333 
334         for (i = 0; i < WM8994_DRC_REGS; i++)
335                 snd_soc_update_bits(codec, base + i, 0xffff,
336                                     pdata->drc_cfgs[cfg].regs[i]);
337 
338         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
339                              WM8994_AIF1ADC1L_DRC_ENA |
340                              WM8994_AIF1ADC1R_DRC_ENA, save);
341 }
342 
343 /* Icky as hell but saves code duplication */
344 static int wm8994_get_drc(const char *name)
345 {
346         if (strcmp(name, "AIF1DRC1 Mode") == 0)
347                 return 0;
348         if (strcmp(name, "AIF1DRC2 Mode") == 0)
349                 return 1;
350         if (strcmp(name, "AIF2DRC Mode") == 0)
351                 return 2;
352         return -EINVAL;
353 }
354 
355 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
356                                struct snd_ctl_elem_value *ucontrol)
357 {
358         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
359         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
360         struct wm8994 *control = wm8994->wm8994;
361         struct wm8994_pdata *pdata = &control->pdata;
362         int drc = wm8994_get_drc(kcontrol->id.name);
363         int value = ucontrol->value.integer.value[0];
364 
365         if (drc < 0)
366                 return drc;
367 
368         if (value >= pdata->num_drc_cfgs)
369                 return -EINVAL;
370 
371         wm8994->drc_cfg[drc] = value;
372 
373         wm8994_set_drc(codec, drc);
374 
375         return 0;
376 }
377 
378 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
379                                struct snd_ctl_elem_value *ucontrol)
380 {
381         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
382         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
383         int drc = wm8994_get_drc(kcontrol->id.name);
384 
385         if (drc < 0)
386                 return drc;
387         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
388 
389         return 0;
390 }
391 
392 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
393 {
394         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
395         struct wm8994 *control = wm8994->wm8994;
396         struct wm8994_pdata *pdata = &control->pdata;
397         int base = wm8994_retune_mobile_base[block];
398         int iface, best, best_val, save, i, cfg;
399 
400         if (!pdata || !wm8994->num_retune_mobile_texts)
401                 return;
402 
403         switch (block) {
404         case 0:
405         case 1:
406                 iface = 0;
407                 break;
408         case 2:
409                 iface = 1;
410                 break;
411         default:
412                 return;
413         }
414 
415         /* Find the version of the currently selected configuration
416          * with the nearest sample rate. */
417         cfg = wm8994->retune_mobile_cfg[block];
418         best = 0;
419         best_val = INT_MAX;
420         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
421                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
422                            wm8994->retune_mobile_texts[cfg]) == 0 &&
423                     abs(pdata->retune_mobile_cfgs[i].rate
424                         - wm8994->dac_rates[iface]) < best_val) {
425                         best = i;
426                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
427                                        - wm8994->dac_rates[iface]);
428                 }
429         }
430 
431         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432                 block,
433                 pdata->retune_mobile_cfgs[best].name,
434                 pdata->retune_mobile_cfgs[best].rate,
435                 wm8994->dac_rates[iface]);
436 
437         /* The EQ will be disabled while reconfiguring it, remember the
438          * current configuration.
439          */
440         save = snd_soc_read(codec, base);
441         save &= WM8994_AIF1DAC1_EQ_ENA;
442 
443         for (i = 0; i < WM8994_EQ_REGS; i++)
444                 snd_soc_update_bits(codec, base + i, 0xffff,
445                                 pdata->retune_mobile_cfgs[best].regs[i]);
446 
447         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
448 }
449 
450 /* Icky as hell but saves code duplication */
451 static int wm8994_get_retune_mobile_block(const char *name)
452 {
453         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
454                 return 0;
455         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
456                 return 1;
457         if (strcmp(name, "AIF2 EQ Mode") == 0)
458                 return 2;
459         return -EINVAL;
460 }
461 
462 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463                                          struct snd_ctl_elem_value *ucontrol)
464 {
465         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
466         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
467         struct wm8994 *control = wm8994->wm8994;
468         struct wm8994_pdata *pdata = &control->pdata;
469         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470         int value = ucontrol->value.integer.value[0];
471 
472         if (block < 0)
473                 return block;
474 
475         if (value >= pdata->num_retune_mobile_cfgs)
476                 return -EINVAL;
477 
478         wm8994->retune_mobile_cfg[block] = value;
479 
480         wm8994_set_retune_mobile(codec, block);
481 
482         return 0;
483 }
484 
485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486                                          struct snd_ctl_elem_value *ucontrol)
487 {
488         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
489         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
490         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491 
492         if (block < 0)
493                 return block;
494 
495         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
496 
497         return 0;
498 }
499 
500 static const char *aif_chan_src_text[] = {
501         "Left", "Right"
502 };
503 
504 static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
505                             WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
506 
507 static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
508                             WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
509 
510 static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
511                             WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
512 
513 static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
514                             WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
515 
516 static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
517                             WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
518 
519 static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
520                             WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
521 
522 static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
523                             WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
524 
525 static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
526                             WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
527 
528 static const char *osr_text[] = {
529         "Low Power", "High Performance",
530 };
531 
532 static SOC_ENUM_SINGLE_DECL(dac_osr,
533                             WM8994_OVERSAMPLING, 0, osr_text);
534 
535 static SOC_ENUM_SINGLE_DECL(adc_osr,
536                             WM8994_OVERSAMPLING, 1, osr_text);
537 
538 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
539 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
540                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
541                  1, 119, 0, digital_tlv),
542 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
543                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
544                  1, 119, 0, digital_tlv),
545 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
546                  WM8994_AIF2_ADC_RIGHT_VOLUME,
547                  1, 119, 0, digital_tlv),
548 
549 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
550 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
551 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
552 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
553 
554 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
555 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
556 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
557 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
558 
559 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
560                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
561 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
562                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
563 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
564                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
565 
566 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
567 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
568 
569 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
570 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
571 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
572 
573 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
574 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
575 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
576 
577 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
578 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
579 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
580 
581 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
582 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
583 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
584 
585 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
586                5, 12, 0, st_tlv),
587 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
588                0, 12, 0, st_tlv),
589 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
590                5, 12, 0, st_tlv),
591 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
592                0, 12, 0, st_tlv),
593 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
594 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
595 
596 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
597 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
598 
599 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
600 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
601 
602 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
603 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
604 
605 SOC_ENUM("ADC OSR", adc_osr),
606 SOC_ENUM("DAC OSR", dac_osr),
607 
608 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
609                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
610 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
611              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
612 
613 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
614                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
615 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
616              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
617 
618 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
619                6, 1, 1, wm_hubs_spkmix_tlv),
620 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
621                2, 1, 1, wm_hubs_spkmix_tlv),
622 
623 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
624                6, 1, 1, wm_hubs_spkmix_tlv),
625 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
626                2, 1, 1, wm_hubs_spkmix_tlv),
627 
628 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
629                10, 15, 0, wm8994_3d_tlv),
630 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
631            8, 1, 0),
632 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
633                10, 15, 0, wm8994_3d_tlv),
634 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
635            8, 1, 0),
636 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
637                10, 15, 0, wm8994_3d_tlv),
638 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
639            8, 1, 0),
640 };
641 
642 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
643 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
644                eq_tlv),
645 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
646                eq_tlv),
647 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
648                eq_tlv),
649 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
650                eq_tlv),
651 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
652                eq_tlv),
653 
654 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
655                eq_tlv),
656 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
657                eq_tlv),
658 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
659                eq_tlv),
660 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
661                eq_tlv),
662 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
663                eq_tlv),
664 
665 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
666                eq_tlv),
667 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
668                eq_tlv),
669 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
670                eq_tlv),
671 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
672                eq_tlv),
673 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
674                eq_tlv),
675 };
676 
677 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
678 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
679                    WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
680                    WM8994_AIF1ADC1R_DRC_ENA),
681 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
682                    WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
683                    WM8994_AIF1ADC2R_DRC_ENA),
684 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
685                    WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
686                    WM8994_AIF2ADCR_DRC_ENA),
687 };
688 
689 static const char *wm8958_ng_text[] = {
690         "30ms", "125ms", "250ms", "500ms",
691 };
692 
693 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
694                             WM8958_AIF1_DAC1_NOISE_GATE,
695                             WM8958_AIF1DAC1_NG_THR_SHIFT,
696                             wm8958_ng_text);
697 
698 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
699                             WM8958_AIF1_DAC2_NOISE_GATE,
700                             WM8958_AIF1DAC2_NG_THR_SHIFT,
701                             wm8958_ng_text);
702 
703 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
704                             WM8958_AIF2_DAC_NOISE_GATE,
705                             WM8958_AIF2DAC_NG_THR_SHIFT,
706                             wm8958_ng_text);
707 
708 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
709 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
710 
711 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
712            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
713 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
714 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
715                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
716                7, 1, ng_tlv),
717 
718 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
719            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
720 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
721 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
722                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
723                7, 1, ng_tlv),
724 
725 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
726            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
727 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
728 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
729                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
730                7, 1, ng_tlv),
731 };
732 
733 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
734 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
735                mixin_boost_tlv),
736 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
737                mixin_boost_tlv),
738 };
739 
740 /* We run all mode setting through a function to enforce audio mode */
741 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
742 {
743         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
744 
745         if (!wm8994->jackdet || !wm8994->micdet[0].jack)
746                 return;
747 
748         if (wm8994->active_refcount)
749                 mode = WM1811_JACKDET_MODE_AUDIO;
750 
751         if (mode == wm8994->jackdet_mode)
752                 return;
753 
754         wm8994->jackdet_mode = mode;
755 
756         /* Always use audio mode to detect while the system is active */
757         if (mode != WM1811_JACKDET_MODE_NONE)
758                 mode = WM1811_JACKDET_MODE_AUDIO;
759 
760         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
761                             WM1811_JACKDET_MODE_MASK, mode);
762 }
763 
764 static void active_reference(struct snd_soc_codec *codec)
765 {
766         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
767 
768         mutex_lock(&wm8994->accdet_lock);
769 
770         wm8994->active_refcount++;
771 
772         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
773                 wm8994->active_refcount);
774 
775         /* If we're using jack detection go into audio mode */
776         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
777 
778         mutex_unlock(&wm8994->accdet_lock);
779 }
780 
781 static void active_dereference(struct snd_soc_codec *codec)
782 {
783         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
784         u16 mode;
785 
786         mutex_lock(&wm8994->accdet_lock);
787 
788         wm8994->active_refcount--;
789 
790         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
791                 wm8994->active_refcount);
792 
793         if (wm8994->active_refcount == 0) {
794                 /* Go into appropriate detection only mode */
795                 if (wm8994->jack_mic || wm8994->mic_detecting)
796                         mode = WM1811_JACKDET_MODE_MIC;
797                 else
798                         mode = WM1811_JACKDET_MODE_JACK;
799 
800                 wm1811_jackdet_set_mode(codec, mode);
801         }
802 
803         mutex_unlock(&wm8994->accdet_lock);
804 }
805 
806 static int clk_sys_event(struct snd_soc_dapm_widget *w,
807                          struct snd_kcontrol *kcontrol, int event)
808 {
809         struct snd_soc_codec *codec = w->codec;
810         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
811 
812         switch (event) {
813         case SND_SOC_DAPM_PRE_PMU:
814                 return configure_clock(codec);
815 
816         case SND_SOC_DAPM_POST_PMU:
817                 /*
818                  * JACKDET won't run until we start the clock and it
819                  * only reports deltas, make sure we notify the state
820                  * up the stack on startup.  Use a *very* generous
821                  * timeout for paranoia, there's no urgency and we
822                  * don't want false reports.
823                  */
824                 if (wm8994->jackdet && !wm8994->clk_has_run) {
825                         queue_delayed_work(system_power_efficient_wq,
826                                            &wm8994->jackdet_bootstrap,
827                                            msecs_to_jiffies(1000));
828                         wm8994->clk_has_run = true;
829                 }
830                 break;
831 
832         case SND_SOC_DAPM_POST_PMD:
833                 configure_clock(codec);
834                 break;
835         }
836 
837         return 0;
838 }
839 
840 static void vmid_reference(struct snd_soc_codec *codec)
841 {
842         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
843 
844         pm_runtime_get_sync(codec->dev);
845 
846         wm8994->vmid_refcount++;
847 
848         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
849                 wm8994->vmid_refcount);
850 
851         if (wm8994->vmid_refcount == 1) {
852                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
853                                     WM8994_LINEOUT1_DISCH |
854                                     WM8994_LINEOUT2_DISCH, 0);
855 
856                 wm_hubs_vmid_ena(codec);
857 
858                 switch (wm8994->vmid_mode) {
859                 default:
860                         WARN_ON(NULL == "Invalid VMID mode");
861                 case WM8994_VMID_NORMAL:
862                         /* Startup bias, VMID ramp & buffer */
863                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
864                                             WM8994_BIAS_SRC |
865                                             WM8994_VMID_DISCH |
866                                             WM8994_STARTUP_BIAS_ENA |
867                                             WM8994_VMID_BUF_ENA |
868                                             WM8994_VMID_RAMP_MASK,
869                                             WM8994_BIAS_SRC |
870                                             WM8994_STARTUP_BIAS_ENA |
871                                             WM8994_VMID_BUF_ENA |
872                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
873 
874                         /* Main bias enable, VMID=2x40k */
875                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
876                                             WM8994_BIAS_ENA |
877                                             WM8994_VMID_SEL_MASK,
878                                             WM8994_BIAS_ENA | 0x2);
879 
880                         msleep(300);
881 
882                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
883                                             WM8994_VMID_RAMP_MASK |
884                                             WM8994_BIAS_SRC,
885                                             0);
886                         break;
887 
888                 case WM8994_VMID_FORCE:
889                         /* Startup bias, slow VMID ramp & buffer */
890                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
891                                             WM8994_BIAS_SRC |
892                                             WM8994_VMID_DISCH |
893                                             WM8994_STARTUP_BIAS_ENA |
894                                             WM8994_VMID_BUF_ENA |
895                                             WM8994_VMID_RAMP_MASK,
896                                             WM8994_BIAS_SRC |
897                                             WM8994_STARTUP_BIAS_ENA |
898                                             WM8994_VMID_BUF_ENA |
899                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
900 
901                         /* Main bias enable, VMID=2x40k */
902                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
903                                             WM8994_BIAS_ENA |
904                                             WM8994_VMID_SEL_MASK,
905                                             WM8994_BIAS_ENA | 0x2);
906 
907                         msleep(400);
908 
909                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
910                                             WM8994_VMID_RAMP_MASK |
911                                             WM8994_BIAS_SRC,
912                                             0);
913                         break;
914                 }
915         }
916 }
917 
918 static void vmid_dereference(struct snd_soc_codec *codec)
919 {
920         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
921 
922         wm8994->vmid_refcount--;
923 
924         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
925                 wm8994->vmid_refcount);
926 
927         if (wm8994->vmid_refcount == 0) {
928                 if (wm8994->hubs.lineout1_se)
929                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
930                                             WM8994_LINEOUT1N_ENA |
931                                             WM8994_LINEOUT1P_ENA,
932                                             WM8994_LINEOUT1N_ENA |
933                                             WM8994_LINEOUT1P_ENA);
934 
935                 if (wm8994->hubs.lineout2_se)
936                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
937                                             WM8994_LINEOUT2N_ENA |
938                                             WM8994_LINEOUT2P_ENA,
939                                             WM8994_LINEOUT2N_ENA |
940                                             WM8994_LINEOUT2P_ENA);
941 
942                 /* Start discharging VMID */
943                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
944                                     WM8994_BIAS_SRC |
945                                     WM8994_VMID_DISCH,
946                                     WM8994_BIAS_SRC |
947                                     WM8994_VMID_DISCH);
948 
949                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
950                                     WM8994_VMID_SEL_MASK, 0);
951 
952                 msleep(400);
953 
954                 /* Active discharge */
955                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
956                                     WM8994_LINEOUT1_DISCH |
957                                     WM8994_LINEOUT2_DISCH,
958                                     WM8994_LINEOUT1_DISCH |
959                                     WM8994_LINEOUT2_DISCH);
960 
961                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
962                                     WM8994_LINEOUT1N_ENA |
963                                     WM8994_LINEOUT1P_ENA |
964                                     WM8994_LINEOUT2N_ENA |
965                                     WM8994_LINEOUT2P_ENA, 0);
966 
967                 /* Switch off startup biases */
968                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
969                                     WM8994_BIAS_SRC |
970                                     WM8994_STARTUP_BIAS_ENA |
971                                     WM8994_VMID_BUF_ENA |
972                                     WM8994_VMID_RAMP_MASK, 0);
973 
974                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
975                                     WM8994_VMID_SEL_MASK, 0);
976         }
977 
978         pm_runtime_put(codec->dev);
979 }
980 
981 static int vmid_event(struct snd_soc_dapm_widget *w,
982                       struct snd_kcontrol *kcontrol, int event)
983 {
984         struct snd_soc_codec *codec = w->codec;
985 
986         switch (event) {
987         case SND_SOC_DAPM_PRE_PMU:
988                 vmid_reference(codec);
989                 break;
990 
991         case SND_SOC_DAPM_POST_PMD:
992                 vmid_dereference(codec);
993                 break;
994         }
995 
996         return 0;
997 }
998 
999 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
1000 {
1001         int source = 0;  /* GCC flow analysis can't track enable */
1002         int reg, reg_r;
1003 
1004         /* We also need the same AIF source for L/R and only one path */
1005         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1006         switch (reg) {
1007         case WM8994_AIF2DACL_TO_DAC1L:
1008                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1009                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1010                 break;
1011         case WM8994_AIF1DAC2L_TO_DAC1L:
1012                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1013                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1014                 break;
1015         case WM8994_AIF1DAC1L_TO_DAC1L:
1016                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1017                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1018                 break;
1019         default:
1020                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1021                 return false;
1022         }
1023 
1024         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1025         if (reg_r != reg) {
1026                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1027                 return false;
1028         }
1029 
1030         /* Set the source up */
1031         snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1032                             WM8994_CP_DYN_SRC_SEL_MASK, source);
1033 
1034         return true;
1035 }
1036 
1037 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1038                       struct snd_kcontrol *kcontrol, int event)
1039 {
1040         struct snd_soc_codec *codec = w->codec;
1041         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1042         struct wm8994 *control = wm8994->wm8994;
1043         int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1044         int i;
1045         int dac;
1046         int adc;
1047         int val;
1048 
1049         switch (control->type) {
1050         case WM8994:
1051         case WM8958:
1052                 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1053                 break;
1054         default:
1055                 break;
1056         }
1057 
1058         switch (event) {
1059         case SND_SOC_DAPM_PRE_PMU:
1060                 /* Don't enable timeslot 2 if not in use */
1061                 if (wm8994->channels[0] <= 2)
1062                         mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1063 
1064                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1065                 if ((val & WM8994_AIF1ADCL_SRC) &&
1066                     (val & WM8994_AIF1ADCR_SRC))
1067                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1068                 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1069                          !(val & WM8994_AIF1ADCR_SRC))
1070                         adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1071                 else
1072                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1073                                 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1074 
1075                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1076                 if ((val & WM8994_AIF1DACL_SRC) &&
1077                     (val & WM8994_AIF1DACR_SRC))
1078                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1079                 else if (!(val & WM8994_AIF1DACL_SRC) &&
1080                          !(val & WM8994_AIF1DACR_SRC))
1081                         dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1082                 else
1083                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1084                                 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1085 
1086                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1087                                     mask, adc);
1088                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1089                                     mask, dac);
1090                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1091                                     WM8994_AIF1DSPCLK_ENA |
1092                                     WM8994_SYSDSPCLK_ENA,
1093                                     WM8994_AIF1DSPCLK_ENA |
1094                                     WM8994_SYSDSPCLK_ENA);
1095                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1096                                     WM8994_AIF1ADC1R_ENA |
1097                                     WM8994_AIF1ADC1L_ENA |
1098                                     WM8994_AIF1ADC2R_ENA |
1099                                     WM8994_AIF1ADC2L_ENA);
1100                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1101                                     WM8994_AIF1DAC1R_ENA |
1102                                     WM8994_AIF1DAC1L_ENA |
1103                                     WM8994_AIF1DAC2R_ENA |
1104                                     WM8994_AIF1DAC2L_ENA);
1105                 break;
1106 
1107         case SND_SOC_DAPM_POST_PMU:
1108                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1109                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1110                                       snd_soc_read(codec,
1111                                                    wm8994_vu_bits[i].reg));
1112                 break;
1113 
1114         case SND_SOC_DAPM_PRE_PMD:
1115         case SND_SOC_DAPM_POST_PMD:
1116                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1117                                     mask, 0);
1118                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1119                                     mask, 0);
1120 
1121                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1122                 if (val & WM8994_AIF2DSPCLK_ENA)
1123                         val = WM8994_SYSDSPCLK_ENA;
1124                 else
1125                         val = 0;
1126                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1127                                     WM8994_SYSDSPCLK_ENA |
1128                                     WM8994_AIF1DSPCLK_ENA, val);
1129                 break;
1130         }
1131 
1132         return 0;
1133 }
1134 
1135 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1136                       struct snd_kcontrol *kcontrol, int event)
1137 {
1138         struct snd_soc_codec *codec = w->codec;
1139         int i;
1140         int dac;
1141         int adc;
1142         int val;
1143 
1144         switch (event) {
1145         case SND_SOC_DAPM_PRE_PMU:
1146                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1147                 if ((val & WM8994_AIF2ADCL_SRC) &&
1148                     (val & WM8994_AIF2ADCR_SRC))
1149                         adc = WM8994_AIF2ADCR_ENA;
1150                 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1151                          !(val & WM8994_AIF2ADCR_SRC))
1152                         adc = WM8994_AIF2ADCL_ENA;
1153                 else
1154                         adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1155 
1156 
1157                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1158                 if ((val & WM8994_AIF2DACL_SRC) &&
1159                     (val & WM8994_AIF2DACR_SRC))
1160                         dac = WM8994_AIF2DACR_ENA;
1161                 else if (!(val & WM8994_AIF2DACL_SRC) &&
1162                          !(val & WM8994_AIF2DACR_SRC))
1163                         dac = WM8994_AIF2DACL_ENA;
1164                 else
1165                         dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1166 
1167                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1168                                     WM8994_AIF2ADCL_ENA |
1169                                     WM8994_AIF2ADCR_ENA, adc);
1170                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1171                                     WM8994_AIF2DACL_ENA |
1172                                     WM8994_AIF2DACR_ENA, dac);
1173                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1174                                     WM8994_AIF2DSPCLK_ENA |
1175                                     WM8994_SYSDSPCLK_ENA,
1176                                     WM8994_AIF2DSPCLK_ENA |
1177                                     WM8994_SYSDSPCLK_ENA);
1178                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1179                                     WM8994_AIF2ADCL_ENA |
1180                                     WM8994_AIF2ADCR_ENA,
1181                                     WM8994_AIF2ADCL_ENA |
1182                                     WM8994_AIF2ADCR_ENA);
1183                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1184                                     WM8994_AIF2DACL_ENA |
1185                                     WM8994_AIF2DACR_ENA,
1186                                     WM8994_AIF2DACL_ENA |
1187                                     WM8994_AIF2DACR_ENA);
1188                 break;
1189 
1190         case SND_SOC_DAPM_POST_PMU:
1191                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1192                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1193                                       snd_soc_read(codec,
1194                                                    wm8994_vu_bits[i].reg));
1195                 break;
1196 
1197         case SND_SOC_DAPM_PRE_PMD:
1198         case SND_SOC_DAPM_POST_PMD:
1199                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1200                                     WM8994_AIF2DACL_ENA |
1201                                     WM8994_AIF2DACR_ENA, 0);
1202                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1203                                     WM8994_AIF2ADCL_ENA |
1204                                     WM8994_AIF2ADCR_ENA, 0);
1205 
1206                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1207                 if (val & WM8994_AIF1DSPCLK_ENA)
1208                         val = WM8994_SYSDSPCLK_ENA;
1209                 else
1210                         val = 0;
1211                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1212                                     WM8994_SYSDSPCLK_ENA |
1213                                     WM8994_AIF2DSPCLK_ENA, val);
1214                 break;
1215         }
1216 
1217         return 0;
1218 }
1219 
1220 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1221                            struct snd_kcontrol *kcontrol, int event)
1222 {
1223         struct snd_soc_codec *codec = w->codec;
1224         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1225 
1226         switch (event) {
1227         case SND_SOC_DAPM_PRE_PMU:
1228                 wm8994->aif1clk_enable = 1;
1229                 break;
1230         case SND_SOC_DAPM_POST_PMD:
1231                 wm8994->aif1clk_disable = 1;
1232                 break;
1233         }
1234 
1235         return 0;
1236 }
1237 
1238 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1239                            struct snd_kcontrol *kcontrol, int event)
1240 {
1241         struct snd_soc_codec *codec = w->codec;
1242         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1243 
1244         switch (event) {
1245         case SND_SOC_DAPM_PRE_PMU:
1246                 wm8994->aif2clk_enable = 1;
1247                 break;
1248         case SND_SOC_DAPM_POST_PMD:
1249                 wm8994->aif2clk_disable = 1;
1250                 break;
1251         }
1252 
1253         return 0;
1254 }
1255 
1256 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1257                           struct snd_kcontrol *kcontrol, int event)
1258 {
1259         struct snd_soc_codec *codec = w->codec;
1260         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1261 
1262         switch (event) {
1263         case SND_SOC_DAPM_PRE_PMU:
1264                 if (wm8994->aif1clk_enable) {
1265                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1266                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1267                                             WM8994_AIF1CLK_ENA_MASK,
1268                                             WM8994_AIF1CLK_ENA);
1269                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1270                         wm8994->aif1clk_enable = 0;
1271                 }
1272                 if (wm8994->aif2clk_enable) {
1273                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1274                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1275                                             WM8994_AIF2CLK_ENA_MASK,
1276                                             WM8994_AIF2CLK_ENA);
1277                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1278                         wm8994->aif2clk_enable = 0;
1279                 }
1280                 break;
1281         }
1282 
1283         /* We may also have postponed startup of DSP, handle that. */
1284         wm8958_aif_ev(w, kcontrol, event);
1285 
1286         return 0;
1287 }
1288 
1289 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1290                            struct snd_kcontrol *kcontrol, int event)
1291 {
1292         struct snd_soc_codec *codec = w->codec;
1293         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1294 
1295         switch (event) {
1296         case SND_SOC_DAPM_POST_PMD:
1297                 if (wm8994->aif1clk_disable) {
1298                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1299                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1300                                             WM8994_AIF1CLK_ENA_MASK, 0);
1301                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1302                         wm8994->aif1clk_disable = 0;
1303                 }
1304                 if (wm8994->aif2clk_disable) {
1305                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1306                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1307                                             WM8994_AIF2CLK_ENA_MASK, 0);
1308                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1309                         wm8994->aif2clk_disable = 0;
1310                 }
1311                 break;
1312         }
1313 
1314         return 0;
1315 }
1316 
1317 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1318                       struct snd_kcontrol *kcontrol, int event)
1319 {
1320         late_enable_ev(w, kcontrol, event);
1321         return 0;
1322 }
1323 
1324 static int micbias_ev(struct snd_soc_dapm_widget *w,
1325                       struct snd_kcontrol *kcontrol, int event)
1326 {
1327         late_enable_ev(w, kcontrol, event);
1328         return 0;
1329 }
1330 
1331 static int dac_ev(struct snd_soc_dapm_widget *w,
1332                   struct snd_kcontrol *kcontrol, int event)
1333 {
1334         struct snd_soc_codec *codec = w->codec;
1335         unsigned int mask = 1 << w->shift;
1336 
1337         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1338                             mask, mask);
1339         return 0;
1340 }
1341 
1342 static const char *adc_mux_text[] = {
1343         "ADC",
1344         "DMIC",
1345 };
1346 
1347 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
1348 
1349 static const struct snd_kcontrol_new adcl_mux =
1350         SOC_DAPM_ENUM("ADCL Mux", adc_enum);
1351 
1352 static const struct snd_kcontrol_new adcr_mux =
1353         SOC_DAPM_ENUM("ADCR Mux", adc_enum);
1354 
1355 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1356 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1357 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1358 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1359 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1360 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1361 };
1362 
1363 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1364 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1365 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1366 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1367 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1368 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1369 };
1370 
1371 /* Debugging; dump chip status after DAPM transitions */
1372 static int post_ev(struct snd_soc_dapm_widget *w,
1373             struct snd_kcontrol *kcontrol, int event)
1374 {
1375         struct snd_soc_codec *codec = w->codec;
1376         dev_dbg(codec->dev, "SRC status: %x\n",
1377                 snd_soc_read(codec,
1378                              WM8994_RATE_STATUS));
1379         return 0;
1380 }
1381 
1382 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1383 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1384                 1, 1, 0),
1385 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1386                 0, 1, 0),
1387 };
1388 
1389 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1390 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1391                 1, 1, 0),
1392 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1393                 0, 1, 0),
1394 };
1395 
1396 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1397 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1398                 1, 1, 0),
1399 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1400                 0, 1, 0),
1401 };
1402 
1403 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1404 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1405                 1, 1, 0),
1406 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1407                 0, 1, 0),
1408 };
1409 
1410 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1411 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1412                 5, 1, 0),
1413 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1414                 4, 1, 0),
1415 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1416                 2, 1, 0),
1417 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1418                 1, 1, 0),
1419 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1420                 0, 1, 0),
1421 };
1422 
1423 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1424 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1425                 5, 1, 0),
1426 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1427                 4, 1, 0),
1428 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1429                 2, 1, 0),
1430 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1431                 1, 1, 0),
1432 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1433                 0, 1, 0),
1434 };
1435 
1436 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1437         SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1438                 snd_soc_dapm_get_volsw, wm8994_put_class_w)
1439 
1440 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1441                               struct snd_ctl_elem_value *ucontrol)
1442 {
1443         struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
1444         int ret;
1445 
1446         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1447 
1448         wm_hubs_update_class_w(codec);
1449 
1450         return ret;
1451 }
1452 
1453 static const struct snd_kcontrol_new dac1l_mix[] = {
1454 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1455                       5, 1, 0),
1456 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1457                       4, 1, 0),
1458 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1459                       2, 1, 0),
1460 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1461                       1, 1, 0),
1462 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1463                       0, 1, 0),
1464 };
1465 
1466 static const struct snd_kcontrol_new dac1r_mix[] = {
1467 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1468                       5, 1, 0),
1469 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1470                       4, 1, 0),
1471 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1472                       2, 1, 0),
1473 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1474                       1, 1, 0),
1475 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1476                       0, 1, 0),
1477 };
1478 
1479 static const char *sidetone_text[] = {
1480         "ADC/DMIC1", "DMIC2",
1481 };
1482 
1483 static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
1484                             WM8994_SIDETONE, 0, sidetone_text);
1485 
1486 static const struct snd_kcontrol_new sidetone1_mux =
1487         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1488 
1489 static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
1490                             WM8994_SIDETONE, 1, sidetone_text);
1491 
1492 static const struct snd_kcontrol_new sidetone2_mux =
1493         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1494 
1495 static const char *aif1dac_text[] = {
1496         "AIF1DACDAT", "AIF3DACDAT",
1497 };
1498 
1499 static const char *loopback_text[] = {
1500         "None", "ADCDAT",
1501 };
1502 
1503 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
1504                             WM8994_AIF1_CONTROL_2,
1505                             WM8994_AIF1_LOOPBACK_SHIFT,
1506                             loopback_text);
1507 
1508 static const struct snd_kcontrol_new aif1_loopback =
1509         SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1510 
1511 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
1512                             WM8994_AIF2_CONTROL_2,
1513                             WM8994_AIF2_LOOPBACK_SHIFT,
1514                             loopback_text);
1515 
1516 static const struct snd_kcontrol_new aif2_loopback =
1517         SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1518 
1519 static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
1520                             WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
1521 
1522 static const struct snd_kcontrol_new aif1dac_mux =
1523         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1524 
1525 static const char *aif2dac_text[] = {
1526         "AIF2DACDAT", "AIF3DACDAT",
1527 };
1528 
1529 static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
1530                             WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
1531 
1532 static const struct snd_kcontrol_new aif2dac_mux =
1533         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1534 
1535 static const char *aif2adc_text[] = {
1536         "AIF2ADCDAT", "AIF3DACDAT",
1537 };
1538 
1539 static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
1540                             WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
1541 
1542 static const struct snd_kcontrol_new aif2adc_mux =
1543         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1544 
1545 static const char *aif3adc_text[] = {
1546         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1547 };
1548 
1549 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
1550                             WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1551 
1552 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1553         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1554 
1555 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
1556                             WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1557 
1558 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1559         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1560 
1561 static const char *mono_pcm_out_text[] = {
1562         "None", "AIF2ADCL", "AIF2ADCR",
1563 };
1564 
1565 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
1566                             WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
1567 
1568 static const struct snd_kcontrol_new mono_pcm_out_mux =
1569         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1570 
1571 static const char *aif2dac_src_text[] = {
1572         "AIF2", "AIF3",
1573 };
1574 
1575 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1576 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
1577                             WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
1578 
1579 static const struct snd_kcontrol_new aif2dacl_src_mux =
1580         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1581 
1582 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
1583                             WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
1584 
1585 static const struct snd_kcontrol_new aif2dacr_src_mux =
1586         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1587 
1588 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1589 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1590         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1591 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1592         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1593 
1594 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1595         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1596 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1597         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1598 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1599         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1600 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1601         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1602 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1603         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1604 
1605 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1606                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1607                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1608 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1609                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1610                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1611 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1612                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1613 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1614                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1615 
1616 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1617 };
1618 
1619 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1620 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1621                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1622                     SND_SOC_DAPM_PRE_PMD),
1623 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1624                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1625                     SND_SOC_DAPM_PRE_PMD),
1626 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1627 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1628                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1629 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1630                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1631 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1632 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1633 };
1634 
1635 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1636 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1637         dac_ev, SND_SOC_DAPM_PRE_PMU),
1638 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1639         dac_ev, SND_SOC_DAPM_PRE_PMU),
1640 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1641         dac_ev, SND_SOC_DAPM_PRE_PMU),
1642 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1643         dac_ev, SND_SOC_DAPM_PRE_PMU),
1644 };
1645 
1646 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1647 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1648 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1649 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1650 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1651 };
1652 
1653 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1654 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1655                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1656 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1657                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1658 };
1659 
1660 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1661 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1662 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1663 };
1664 
1665 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1666 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1667 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1668 SND_SOC_DAPM_INPUT("Clock"),
1669 
1670 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1671                       SND_SOC_DAPM_PRE_PMU),
1672 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1673                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1674 
1675 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1676                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1677                     SND_SOC_DAPM_PRE_PMD),
1678 
1679 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1680 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1681 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1682 
1683 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1684                      0, SND_SOC_NOPM, 9, 0),
1685 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1686                      0, SND_SOC_NOPM, 8, 0),
1687 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1688                       SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1689                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1690 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1691                       SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1692                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1693 
1694 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1695                      0, SND_SOC_NOPM, 11, 0),
1696 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1697                      0, SND_SOC_NOPM, 10, 0),
1698 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1699                       SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1700                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1701 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1702                       SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1703                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1704 
1705 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1706                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1707 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1708                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1709 
1710 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1711                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1712 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1713                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1714 
1715 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1716                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1717 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1718                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1719 
1720 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1721 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1722 
1723 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1724                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1725 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1726                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1727 
1728 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1729                      SND_SOC_NOPM, 13, 0),
1730 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1731                      SND_SOC_NOPM, 12, 0),
1732 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1733                       SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1734                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1735 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1736                       SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1737                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1738 
1739 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1740 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1741 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1742 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1743 
1744 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1745 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1746 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1747 
1748 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1749 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1750 
1751 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1752 
1753 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1754 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1755 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1756 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1757 
1758 /* Power is done with the muxes since the ADC power also controls the
1759  * downsampling chain, the chip will automatically manage the analogue
1760  * specific portions.
1761  */
1762 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1763 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1764 
1765 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1766 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1767 
1768 SND_SOC_DAPM_POST("Debug log", post_ev),
1769 };
1770 
1771 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1772 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1773 };
1774 
1775 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1776 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1777 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1778 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1779 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1780 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1781 };
1782 
1783 static const struct snd_soc_dapm_route intercon[] = {
1784         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1785         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1786 
1787         { "DSP1CLK", NULL, "CLK_SYS" },
1788         { "DSP2CLK", NULL, "CLK_SYS" },
1789         { "DSPINTCLK", NULL, "CLK_SYS" },
1790 
1791         { "AIF1ADC1L", NULL, "AIF1CLK" },
1792         { "AIF1ADC1L", NULL, "DSP1CLK" },
1793         { "AIF1ADC1R", NULL, "AIF1CLK" },
1794         { "AIF1ADC1R", NULL, "DSP1CLK" },
1795         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1796 
1797         { "AIF1DAC1L", NULL, "AIF1CLK" },
1798         { "AIF1DAC1L", NULL, "DSP1CLK" },
1799         { "AIF1DAC1R", NULL, "AIF1CLK" },
1800         { "AIF1DAC1R", NULL, "DSP1CLK" },
1801         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1802 
1803         { "AIF1ADC2L", NULL, "AIF1CLK" },
1804         { "AIF1ADC2L", NULL, "DSP1CLK" },
1805         { "AIF1ADC2R", NULL, "AIF1CLK" },
1806         { "AIF1ADC2R", NULL, "DSP1CLK" },
1807         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1808 
1809         { "AIF1DAC2L", NULL, "AIF1CLK" },
1810         { "AIF1DAC2L", NULL, "DSP1CLK" },
1811         { "AIF1DAC2R", NULL, "AIF1CLK" },
1812         { "AIF1DAC2R", NULL, "DSP1CLK" },
1813         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1814 
1815         { "AIF2ADCL", NULL, "AIF2CLK" },
1816         { "AIF2ADCL", NULL, "DSP2CLK" },
1817         { "AIF2ADCR", NULL, "AIF2CLK" },
1818         { "AIF2ADCR", NULL, "DSP2CLK" },
1819         { "AIF2ADCR", NULL, "DSPINTCLK" },
1820 
1821         { "AIF2DACL", NULL, "AIF2CLK" },
1822         { "AIF2DACL", NULL, "DSP2CLK" },
1823         { "AIF2DACR", NULL, "AIF2CLK" },
1824         { "AIF2DACR", NULL, "DSP2CLK" },
1825         { "AIF2DACR", NULL, "DSPINTCLK" },
1826 
1827         { "DMIC1L", NULL, "DMIC1DAT" },
1828         { "DMIC1L", NULL, "CLK_SYS" },
1829         { "DMIC1R", NULL, "DMIC1DAT" },
1830         { "DMIC1R", NULL, "CLK_SYS" },
1831         { "DMIC2L", NULL, "DMIC2DAT" },
1832         { "DMIC2L", NULL, "CLK_SYS" },
1833         { "DMIC2R", NULL, "DMIC2DAT" },
1834         { "DMIC2R", NULL, "CLK_SYS" },
1835 
1836         { "ADCL", NULL, "AIF1CLK" },
1837         { "ADCL", NULL, "DSP1CLK" },
1838         { "ADCL", NULL, "DSPINTCLK" },
1839 
1840         { "ADCR", NULL, "AIF1CLK" },
1841         { "ADCR", NULL, "DSP1CLK" },
1842         { "ADCR", NULL, "DSPINTCLK" },
1843 
1844         { "ADCL Mux", "ADC", "ADCL" },
1845         { "ADCL Mux", "DMIC", "DMIC1L" },
1846         { "ADCR Mux", "ADC", "ADCR" },
1847         { "ADCR Mux", "DMIC", "DMIC1R" },
1848 
1849         { "DAC1L", NULL, "AIF1CLK" },
1850         { "DAC1L", NULL, "DSP1CLK" },
1851         { "DAC1L", NULL, "DSPINTCLK" },
1852 
1853         { "DAC1R", NULL, "AIF1CLK" },
1854         { "DAC1R", NULL, "DSP1CLK" },
1855         { "DAC1R", NULL, "DSPINTCLK" },
1856 
1857         { "DAC2L", NULL, "AIF2CLK" },
1858         { "DAC2L", NULL, "DSP2CLK" },
1859         { "DAC2L", NULL, "DSPINTCLK" },
1860 
1861         { "DAC2R", NULL, "AIF2DACR" },
1862         { "DAC2R", NULL, "AIF2CLK" },
1863         { "DAC2R", NULL, "DSP2CLK" },
1864         { "DAC2R", NULL, "DSPINTCLK" },
1865 
1866         { "TOCLK", NULL, "CLK_SYS" },
1867 
1868         { "AIF1DACDAT", NULL, "AIF1 Playback" },
1869         { "AIF2DACDAT", NULL, "AIF2 Playback" },
1870         { "AIF3DACDAT", NULL, "AIF3 Playback" },
1871 
1872         { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1873         { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1874         { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1875 
1876         /* AIF1 outputs */
1877         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1878         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1879         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1880 
1881         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1882         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1883         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1884 
1885         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1886         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1887         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1888 
1889         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1890         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1891         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1892 
1893         /* Pin level routing for AIF3 */
1894         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1895         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1896         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1897         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1898 
1899         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1900         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1901         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1902         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1903         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1904         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1905         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1906 
1907         /* DAC1 inputs */
1908         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1909         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1910         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1911         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1912         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1913 
1914         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1915         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1916         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1917         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1918         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1919 
1920         /* DAC2/AIF2 outputs  */
1921         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1922         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1923         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1924         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1925         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1926         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1927 
1928         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1929         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1930         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1931         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1932         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1933         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1934 
1935         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1936         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1937         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1938         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1939 
1940         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1941 
1942         /* AIF3 output */
1943         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1944         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1945         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1946         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1947         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1948         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1949         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1950         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1951 
1952         /* Loopback */
1953         { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1954         { "AIF1 Loopback", "None", "AIF1DACDAT" },
1955         { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1956         { "AIF2 Loopback", "None", "AIF2DACDAT" },
1957 
1958         /* Sidetone */
1959         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1960         { "Left Sidetone", "DMIC2", "DMIC2L" },
1961         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1962         { "Right Sidetone", "DMIC2", "DMIC2R" },
1963 
1964         /* Output stages */
1965         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1966         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1967 
1968         { "SPKL", "DAC1 Switch", "DAC1L" },
1969         { "SPKL", "DAC2 Switch", "DAC2L" },
1970 
1971         { "SPKR", "DAC1 Switch", "DAC1R" },
1972         { "SPKR", "DAC2 Switch", "DAC2R" },
1973 
1974         { "Left Headphone Mux", "DAC", "DAC1L" },
1975         { "Right Headphone Mux", "DAC", "DAC1R" },
1976 };
1977 
1978 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1979         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1980         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1981         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1982         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1983         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1984         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1985         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1986         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1987 };
1988 
1989 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1990         { "DAC1L", NULL, "DAC1L Mixer" },
1991         { "DAC1R", NULL, "DAC1R Mixer" },
1992         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1993         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1994 };
1995 
1996 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1997         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1998         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1999         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2000         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
2001         { "MICBIAS1", NULL, "CLK_SYS" },
2002         { "MICBIAS1", NULL, "MICBIAS Supply" },
2003         { "MICBIAS2", NULL, "CLK_SYS" },
2004         { "MICBIAS2", NULL, "MICBIAS Supply" },
2005 };
2006 
2007 static const struct snd_soc_dapm_route wm8994_intercon[] = {
2008         { "AIF2DACL", NULL, "AIF2DAC Mux" },
2009         { "AIF2DACR", NULL, "AIF2DAC Mux" },
2010         { "MICBIAS1", NULL, "VMID" },
2011         { "MICBIAS2", NULL, "VMID" },
2012 };
2013 
2014 static const struct snd_soc_dapm_route wm8958_intercon[] = {
2015         { "AIF2DACL", NULL, "AIF2DACL Mux" },
2016         { "AIF2DACR", NULL, "AIF2DACR Mux" },
2017 
2018         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2019         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2020         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2021         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2022 
2023         { "AIF3DACDAT", NULL, "AIF3" },
2024         { "AIF3ADCDAT", NULL, "AIF3" },
2025 
2026         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2027         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2028 
2029         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2030 };
2031 
2032 /* The size in bits of the FLL divide multiplied by 10
2033  * to allow rounding later */
2034 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2035 
2036 struct fll_div {
2037         u16 outdiv;
2038         u16 n;
2039         u16 k;
2040         u16 lambda;
2041         u16 clk_ref_div;
2042         u16 fll_fratio;
2043 };
2044 
2045 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2046                                  int freq_in, int freq_out)
2047 {
2048         u64 Kpart;
2049         unsigned int K, Ndiv, Nmod, gcd_fll;
2050 
2051         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2052 
2053         /* Scale the input frequency down to <= 13.5MHz */
2054         fll->clk_ref_div = 0;
2055         while (freq_in > 13500000) {
2056                 fll->clk_ref_div++;
2057                 freq_in /= 2;
2058 
2059                 if (fll->clk_ref_div > 3)
2060                         return -EINVAL;
2061         }
2062         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2063 
2064         /* Scale the output to give 90MHz<=Fvco<=100MHz */
2065         fll->outdiv = 3;
2066         while (freq_out * (fll->outdiv + 1) < 90000000) {
2067                 fll->outdiv++;
2068                 if (fll->outdiv > 63)
2069                         return -EINVAL;
2070         }
2071         freq_out *= fll->outdiv + 1;
2072         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2073 
2074         if (freq_in > 1000000) {
2075                 fll->fll_fratio = 0;
2076         } else if (freq_in > 256000) {
2077                 fll->fll_fratio = 1;
2078                 freq_in *= 2;
2079         } else if (freq_in > 128000) {
2080                 fll->fll_fratio = 2;
2081                 freq_in *= 4;
2082         } else if (freq_in > 64000) {
2083                 fll->fll_fratio = 3;
2084                 freq_in *= 8;
2085         } else {
2086                 fll->fll_fratio = 4;
2087                 freq_in *= 16;
2088         }
2089         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2090 
2091         /* Now, calculate N.K */
2092         Ndiv = freq_out / freq_in;
2093 
2094         fll->n = Ndiv;
2095         Nmod = freq_out % freq_in;
2096         pr_debug("Nmod=%d\n", Nmod);
2097 
2098         switch (control->type) {
2099         case WM8994:
2100                 /* Calculate fractional part - scale up so we can round. */
2101                 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2102 
2103                 do_div(Kpart, freq_in);
2104 
2105                 K = Kpart & 0xFFFFFFFF;
2106 
2107                 if ((K % 10) >= 5)
2108                         K += 5;
2109 
2110                 /* Move down to proper range now rounding is done */
2111                 fll->k = K / 10;
2112                 fll->lambda = 0;
2113 
2114                 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2115                 break;
2116 
2117         default:
2118                 gcd_fll = gcd(freq_out, freq_in);
2119 
2120                 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2121                 fll->lambda = freq_in / gcd_fll;
2122                 
2123         }
2124 
2125         return 0;
2126 }
2127 
2128 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2129                           unsigned int freq_in, unsigned int freq_out)
2130 {
2131         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2132         struct wm8994 *control = wm8994->wm8994;
2133         int reg_offset, ret;
2134         struct fll_div fll;
2135         u16 reg, clk1, aif_reg, aif_src;
2136         unsigned long timeout;
2137         bool was_enabled;
2138 
2139         switch (id) {
2140         case WM8994_FLL1:
2141                 reg_offset = 0;
2142                 id = 0;
2143                 aif_src = 0x10;
2144                 break;
2145         case WM8994_FLL2:
2146                 reg_offset = 0x20;
2147                 id = 1;
2148                 aif_src = 0x18;
2149                 break;
2150         default:
2151                 return -EINVAL;
2152         }
2153 
2154         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2155         was_enabled = reg & WM8994_FLL1_ENA;
2156 
2157         switch (src) {
2158         case 0:
2159                 /* Allow no source specification when stopping */
2160                 if (freq_out)
2161                         return -EINVAL;
2162                 src = wm8994->fll[id].src;
2163                 break;
2164         case WM8994_FLL_SRC_MCLK1:
2165         case WM8994_FLL_SRC_MCLK2:
2166         case WM8994_FLL_SRC_LRCLK:
2167         case WM8994_FLL_SRC_BCLK:
2168                 break;
2169         case WM8994_FLL_SRC_INTERNAL:
2170                 freq_in = 12000000;
2171                 freq_out = 12000000;
2172                 break;
2173         default:
2174                 return -EINVAL;
2175         }
2176 
2177         /* Are we changing anything? */
2178         if (wm8994->fll[id].src == src &&
2179             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2180                 return 0;
2181 
2182         /* If we're stopping the FLL redo the old config - no
2183          * registers will actually be written but we avoid GCC flow
2184          * analysis bugs spewing warnings.
2185          */
2186         if (freq_out)
2187                 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2188         else
2189                 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2190                                             wm8994->fll[id].out);
2191         if (ret < 0)
2192                 return ret;
2193 
2194         /* Make sure that we're not providing SYSCLK right now */
2195         clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2196         if (clk1 & WM8994_SYSCLK_SRC)
2197                 aif_reg = WM8994_AIF2_CLOCKING_1;
2198         else
2199                 aif_reg = WM8994_AIF1_CLOCKING_1;
2200         reg = snd_soc_read(codec, aif_reg);
2201 
2202         if ((reg & WM8994_AIF1CLK_ENA) &&
2203             (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2204                 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2205                         id + 1);
2206                 return -EBUSY;
2207         }
2208 
2209         /* We always need to disable the FLL while reconfiguring */
2210         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2211                             WM8994_FLL1_ENA, 0);
2212 
2213         if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2214             freq_in == freq_out && freq_out) {
2215                 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2216                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2217                                     WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2218                 goto out;
2219         }
2220 
2221         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2222                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2223         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2224                             WM8994_FLL1_OUTDIV_MASK |
2225                             WM8994_FLL1_FRATIO_MASK, reg);
2226 
2227         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2228                             WM8994_FLL1_K_MASK, fll.k);
2229 
2230         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2231                             WM8994_FLL1_N_MASK,
2232                             fll.n << WM8994_FLL1_N_SHIFT);
2233 
2234         if (fll.lambda) {
2235                 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2236                                     WM8958_FLL1_LAMBDA_MASK,
2237                                     fll.lambda);
2238                 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2239                                     WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2240         } else {
2241                 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2242                                     WM8958_FLL1_EFS_ENA, 0);
2243         }
2244 
2245         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2246                             WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2247                             WM8994_FLL1_REFCLK_DIV_MASK |
2248                             WM8994_FLL1_REFCLK_SRC_MASK,
2249                             ((src == WM8994_FLL_SRC_INTERNAL)
2250                              << WM8994_FLL1_FRC_NCO_SHIFT) |
2251                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2252                             (src - 1));
2253 
2254         /* Clear any pending completion from a previous failure */
2255         try_wait_for_completion(&wm8994->fll_locked[id]);
2256 
2257         /* Enable (with fractional mode if required) */
2258         if (freq_out) {
2259                 /* Enable VMID if we need it */
2260                 if (!was_enabled) {
2261                         active_reference(codec);
2262 
2263                         switch (control->type) {
2264                         case WM8994:
2265                                 vmid_reference(codec);
2266                                 break;
2267                         case WM8958:
2268                                 if (control->revision < 1)
2269                                         vmid_reference(codec);
2270                                 break;
2271                         default:
2272                                 break;
2273                         }
2274                 }
2275 
2276                 reg = WM8994_FLL1_ENA;
2277 
2278                 if (fll.k)
2279                         reg |= WM8994_FLL1_FRAC;
2280                 if (src == WM8994_FLL_SRC_INTERNAL)
2281                         reg |= WM8994_FLL1_OSC_ENA;
2282 
2283                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2284                                     WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2285                                     WM8994_FLL1_FRAC, reg);
2286 
2287                 if (wm8994->fll_locked_irq) {
2288                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2289                                                               msecs_to_jiffies(10));
2290                         if (timeout == 0)
2291                                 dev_warn(codec->dev,
2292                                          "Timed out waiting for FLL lock\n");
2293                 } else {
2294                         msleep(5);
2295                 }
2296         } else {
2297                 if (was_enabled) {
2298                         switch (control->type) {
2299                         case WM8994:
2300                                 vmid_dereference(codec);
2301                                 break;
2302                         case WM8958:
2303                                 if (control->revision < 1)
2304                                         vmid_dereference(codec);
2305                                 break;
2306                         default:
2307                                 break;
2308                         }
2309 
2310                         active_dereference(codec);
2311                 }
2312         }
2313 
2314 out:
2315         wm8994->fll[id].in = freq_in;
2316         wm8994->fll[id].out = freq_out;
2317         wm8994->fll[id].src = src;
2318 
2319         configure_clock(codec);
2320 
2321         /*
2322          * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2323          * for detection.
2324          */
2325         if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2326                 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2327 
2328                 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2329                         & WM8994_AIF1CLK_RATE_MASK;
2330                 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2331                         & WM8994_AIF1CLK_RATE_MASK;
2332 
2333                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2334                                     WM8994_AIF1CLK_RATE_MASK, 0x1);
2335                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2336                                     WM8994_AIF2CLK_RATE_MASK, 0x1);
2337         } else if (wm8994->aifdiv[0]) {
2338                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2339                                     WM8994_AIF1CLK_RATE_MASK,
2340                                     wm8994->aifdiv[0]);
2341                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2342                                     WM8994_AIF2CLK_RATE_MASK,
2343                                     wm8994->aifdiv[1]);
2344 
2345                 wm8994->aifdiv[0] = 0;
2346                 wm8994->aifdiv[1] = 0;
2347         }
2348 
2349         return 0;
2350 }
2351 
2352 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2353 {
2354         struct completion *completion = data;
2355 
2356         complete(completion);
2357 
2358         return IRQ_HANDLED;
2359 }
2360 
2361 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2362 
2363 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2364                           unsigned int freq_in, unsigned int freq_out)
2365 {
2366         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2367 }
2368 
2369 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2370                 int clk_id, unsigned int freq, int dir)
2371 {
2372         struct snd_soc_codec *codec = dai->codec;
2373         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2374         int i;
2375 
2376         switch (dai->id) {
2377         case 1:
2378         case 2:
2379                 break;
2380 
2381         default:
2382                 /* AIF3 shares clocking with AIF1/2 */
2383                 return -EINVAL;
2384         }
2385 
2386         switch (clk_id) {
2387         case WM8994_SYSCLK_MCLK1:
2388                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2389                 wm8994->mclk[0] = freq;
2390                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2391                         dai->id, freq);
2392                 break;
2393 
2394         case WM8994_SYSCLK_MCLK2:
2395                 /* TODO: Set GPIO AF */
2396                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2397                 wm8994->mclk[1] = freq;
2398                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2399                         dai->id, freq);
2400                 break;
2401 
2402         case WM8994_SYSCLK_FLL1:
2403                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2404                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2405                 break;
2406 
2407         case WM8994_SYSCLK_FLL2:
2408                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2409                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2410                 break;
2411 
2412         case WM8994_SYSCLK_OPCLK:
2413                 /* Special case - a division (times 10) is given and
2414                  * no effect on main clocking.
2415                  */
2416                 if (freq) {
2417                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2418                                 if (opclk_divs[i] == freq)
2419                                         break;
2420                         if (i == ARRAY_SIZE(opclk_divs))
2421                                 return -EINVAL;
2422                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2423                                             WM8994_OPCLK_DIV_MASK, i);
2424                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2425                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2426                 } else {
2427                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2428                                             WM8994_OPCLK_ENA, 0);
2429                 }
2430 
2431         default:
2432                 return -EINVAL;
2433         }
2434 
2435         configure_clock(codec);
2436 
2437         /*
2438          * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2439          * for detection.
2440          */
2441         if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2442                 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2443 
2444                 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2445                         & WM8994_AIF1CLK_RATE_MASK;
2446                 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2447                         & WM8994_AIF1CLK_RATE_MASK;
2448 
2449                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2450                                     WM8994_AIF1CLK_RATE_MASK, 0x1);
2451                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2452                                     WM8994_AIF2CLK_RATE_MASK, 0x1);
2453         } else if (wm8994->aifdiv[0]) {
2454                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2455                                     WM8994_AIF1CLK_RATE_MASK,
2456                                     wm8994->aifdiv[0]);
2457                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2458                                     WM8994_AIF2CLK_RATE_MASK,
2459                                     wm8994->aifdiv[1]);
2460 
2461                 wm8994->aifdiv[0] = 0;
2462                 wm8994->aifdiv[1] = 0;
2463         }
2464 
2465         return 0;
2466 }
2467 
2468 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2469                                  enum snd_soc_bias_level level)
2470 {
2471         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2472         struct wm8994 *control = wm8994->wm8994;
2473 
2474         wm_hubs_set_bias_level(codec, level);
2475 
2476         switch (level) {
2477         case SND_SOC_BIAS_ON:
2478                 break;
2479 
2480         case SND_SOC_BIAS_PREPARE:
2481                 /* MICBIAS into regulating mode */
2482                 switch (control->type) {
2483                 case WM8958:
2484                 case WM1811:
2485                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2486                                             WM8958_MICB1_MODE, 0);
2487                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2488                                             WM8958_MICB2_MODE, 0);
2489                         break;
2490                 default:
2491                         break;
2492                 }
2493 
2494                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2495                         active_reference(codec);
2496                 break;
2497 
2498         case SND_SOC_BIAS_STANDBY:
2499                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2500                         switch (control->type) {
2501                         case WM8958:
2502                                 if (control->revision == 0) {
2503                                         /* Optimise performance for rev A */
2504                                         snd_soc_update_bits(codec,
2505                                                             WM8958_CHARGE_PUMP_2,
2506                                                             WM8958_CP_DISCH,
2507                                                             WM8958_CP_DISCH);
2508                                 }
2509                                 break;
2510 
2511                         default:
2512                                 break;
2513                         }
2514 
2515                         /* Discharge LINEOUT1 & 2 */
2516                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2517                                             WM8994_LINEOUT1_DISCH |
2518                                             WM8994_LINEOUT2_DISCH,
2519                                             WM8994_LINEOUT1_DISCH |
2520                                             WM8994_LINEOUT2_DISCH);
2521                 }
2522 
2523                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2524                         active_dereference(codec);
2525 
2526                 /* MICBIAS into bypass mode on newer devices */
2527                 switch (control->type) {
2528                 case WM8958:
2529                 case WM1811:
2530                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2531                                             WM8958_MICB1_MODE,
2532                                             WM8958_MICB1_MODE);
2533                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2534                                             WM8958_MICB2_MODE,
2535                                             WM8958_MICB2_MODE);
2536                         break;
2537                 default:
2538                         break;
2539                 }
2540                 break;
2541 
2542         case SND_SOC_BIAS_OFF:
2543                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2544                         wm8994->cur_fw = NULL;
2545                 break;
2546         }
2547 
2548         codec->dapm.bias_level = level;
2549 
2550         return 0;
2551 }
2552 
2553 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2554 {
2555         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2556         struct snd_soc_dapm_context *dapm = &codec->dapm;
2557 
2558         switch (mode) {
2559         case WM8994_VMID_NORMAL:
2560                 snd_soc_dapm_mutex_lock(dapm);
2561 
2562                 if (wm8994->hubs.lineout1_se) {
2563                         snd_soc_dapm_disable_pin_unlocked(dapm,
2564                                                           "LINEOUT1N Driver");
2565                         snd_soc_dapm_disable_pin_unlocked(dapm,
2566                                                           "LINEOUT1P Driver");
2567                 }
2568                 if (wm8994->hubs.lineout2_se) {
2569                         snd_soc_dapm_disable_pin_unlocked(dapm,
2570                                                           "LINEOUT2N Driver");
2571                         snd_soc_dapm_disable_pin_unlocked(dapm,
2572                                                           "LINEOUT2P Driver");
2573                 }
2574 
2575                 /* Do the sync with the old mode to allow it to clean up */
2576                 snd_soc_dapm_sync_unlocked(dapm);
2577                 wm8994->vmid_mode = mode;
2578 
2579                 snd_soc_dapm_mutex_unlock(dapm);
2580                 break;
2581 
2582         case WM8994_VMID_FORCE:
2583                 snd_soc_dapm_mutex_lock(dapm);
2584 
2585                 if (wm8994->hubs.lineout1_se) {
2586                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2587                                                                "LINEOUT1N Driver");
2588                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2589                                                                "LINEOUT1P Driver");
2590                 }
2591                 if (wm8994->hubs.lineout2_se) {
2592                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2593                                                                "LINEOUT2N Driver");
2594                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2595                                                                "LINEOUT2P Driver");
2596                 }
2597 
2598                 wm8994->vmid_mode = mode;
2599                 snd_soc_dapm_sync_unlocked(dapm);
2600 
2601                 snd_soc_dapm_mutex_unlock(dapm);
2602                 break;
2603 
2604         default:
2605                 return -EINVAL;
2606         }
2607 
2608         return 0;
2609 }
2610 
2611 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2612 {
2613         struct snd_soc_codec *codec = dai->codec;
2614         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2615         struct wm8994 *control = wm8994->wm8994;
2616         int ms_reg;
2617         int aif1_reg;
2618         int dac_reg;
2619         int adc_reg;
2620         int ms = 0;
2621         int aif1 = 0;
2622         int lrclk = 0;
2623 
2624         switch (dai->id) {
2625         case 1:
2626                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2627                 aif1_reg = WM8994_AIF1_CONTROL_1;
2628                 dac_reg = WM8994_AIF1DAC_LRCLK;
2629                 adc_reg = WM8994_AIF1ADC_LRCLK;
2630                 break;
2631         case 2:
2632                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2633                 aif1_reg = WM8994_AIF2_CONTROL_1;
2634                 dac_reg = WM8994_AIF1DAC_LRCLK;
2635                 adc_reg = WM8994_AIF1ADC_LRCLK;
2636                 break;
2637         default:
2638                 return -EINVAL;
2639         }
2640 
2641         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2642         case SND_SOC_DAIFMT_CBS_CFS:
2643                 break;
2644         case SND_SOC_DAIFMT_CBM_CFM:
2645                 ms = WM8994_AIF1_MSTR;
2646                 break;
2647         default:
2648                 return -EINVAL;
2649         }
2650 
2651         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2652         case SND_SOC_DAIFMT_DSP_B:
2653                 aif1 |= WM8994_AIF1_LRCLK_INV;
2654                 lrclk |= WM8958_AIF1_LRCLK_INV;
2655         case SND_SOC_DAIFMT_DSP_A:
2656                 aif1 |= 0x18;
2657                 break;
2658         case SND_SOC_DAIFMT_I2S:
2659                 aif1 |= 0x10;
2660                 break;
2661         case SND_SOC_DAIFMT_RIGHT_J:
2662                 break;
2663         case SND_SOC_DAIFMT_LEFT_J:
2664                 aif1 |= 0x8;
2665                 break;
2666         default:
2667                 return -EINVAL;
2668         }
2669 
2670         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2671         case SND_SOC_DAIFMT_DSP_A:
2672         case SND_SOC_DAIFMT_DSP_B:
2673                 /* frame inversion not valid for DSP modes */
2674                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2675                 case SND_SOC_DAIFMT_NB_NF:
2676                         break;
2677                 case SND_SOC_DAIFMT_IB_NF:
2678                         aif1 |= WM8994_AIF1_BCLK_INV;
2679                         break;
2680                 default:
2681                         return -EINVAL;
2682                 }
2683                 break;
2684 
2685         case SND_SOC_DAIFMT_I2S:
2686         case SND_SOC_DAIFMT_RIGHT_J:
2687         case SND_SOC_DAIFMT_LEFT_J:
2688                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2689                 case SND_SOC_DAIFMT_NB_NF:
2690                         break;
2691                 case SND_SOC_DAIFMT_IB_IF:
2692                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2693                         lrclk |= WM8958_AIF1_LRCLK_INV;
2694                         break;
2695                 case SND_SOC_DAIFMT_IB_NF:
2696                         aif1 |= WM8994_AIF1_BCLK_INV;
2697                         break;
2698                 case SND_SOC_DAIFMT_NB_IF:
2699                         aif1 |= WM8994_AIF1_LRCLK_INV;
2700                         lrclk |= WM8958_AIF1_LRCLK_INV;
2701                         break;
2702                 default:
2703                         return -EINVAL;
2704                 }
2705                 break;
2706         default:
2707                 return -EINVAL;
2708         }
2709 
2710         /* The AIF2 format configuration needs to be mirrored to AIF3
2711          * on WM8958 if it's in use so just do it all the time. */
2712         switch (control->type) {
2713         case WM1811:
2714         case WM8958:
2715                 if (dai->id == 2)
2716                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2717                                             WM8994_AIF1_LRCLK_INV |
2718                                             WM8958_AIF3_FMT_MASK, aif1);
2719                 break;
2720 
2721         default:
2722                 break;
2723         }
2724 
2725         snd_soc_update_bits(codec, aif1_reg,
2726                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2727                             WM8994_AIF1_FMT_MASK,
2728                             aif1);
2729         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2730                             ms);
2731         snd_soc_update_bits(codec, dac_reg,
2732                             WM8958_AIF1_LRCLK_INV, lrclk);
2733         snd_soc_update_bits(codec, adc_reg,
2734                             WM8958_AIF1_LRCLK_INV, lrclk);
2735 
2736         return 0;
2737 }
2738 
2739 static struct {
2740         int val, rate;
2741 } srs[] = {
2742         { 0,   8000 },
2743         { 1,  11025 },
2744         { 2,  12000 },
2745         { 3,  16000 },
2746         { 4,  22050 },
2747         { 5,  24000 },
2748         { 6,  32000 },
2749         { 7,  44100 },
2750         { 8,  48000 },
2751         { 9,  88200 },
2752         { 10, 96000 },
2753 };
2754 
2755 static int fs_ratios[] = {
2756         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2757 };
2758 
2759 static int bclk_divs[] = {
2760         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2761         640, 880, 960, 1280, 1760, 1920
2762 };
2763 
2764 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2765                             struct snd_pcm_hw_params *params,
2766                             struct snd_soc_dai *dai)
2767 {
2768         struct snd_soc_codec *codec = dai->codec;
2769         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2770         struct wm8994 *control = wm8994->wm8994;
2771         struct wm8994_pdata *pdata = &control->pdata;
2772         int aif1_reg;
2773         int aif2_reg;
2774         int bclk_reg;
2775         int lrclk_reg;
2776         int rate_reg;
2777         int aif1 = 0;
2778         int aif2 = 0;
2779         int bclk = 0;
2780         int lrclk = 0;
2781         int rate_val = 0;
2782         int id = dai->id - 1;
2783 
2784         int i, cur_val, best_val, bclk_rate, best;
2785 
2786         switch (dai->id) {
2787         case 1:
2788                 aif1_reg = WM8994_AIF1_CONTROL_1;
2789                 aif2_reg = WM8994_AIF1_CONTROL_2;
2790                 bclk_reg = WM8994_AIF1_BCLK;
2791                 rate_reg = WM8994_AIF1_RATE;
2792                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2793                     wm8994->lrclk_shared[0]) {
2794                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2795                 } else {
2796                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2797                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2798                 }
2799                 break;
2800         case 2:
2801                 aif1_reg = WM8994_AIF2_CONTROL_1;
2802                 aif2_reg = WM8994_AIF2_CONTROL_2;
2803                 bclk_reg = WM8994_AIF2_BCLK;
2804                 rate_reg = WM8994_AIF2_RATE;
2805                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2806                     wm8994->lrclk_shared[1]) {
2807                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2808                 } else {
2809                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2810                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2811                 }
2812                 break;
2813         default:
2814                 return -EINVAL;
2815         }
2816 
2817         bclk_rate = params_rate(params);
2818         switch (params_width(params)) {
2819         case 16:
2820                 bclk_rate *= 16;
2821                 break;
2822         case 20:
2823                 bclk_rate *= 20;
2824                 aif1 |= 0x20;
2825                 break;
2826         case 24:
2827                 bclk_rate *= 24;
2828                 aif1 |= 0x40;
2829                 break;
2830         case 32:
2831                 bclk_rate *= 32;
2832                 aif1 |= 0x60;
2833                 break;
2834         default:
2835                 return -EINVAL;
2836         }
2837 
2838         wm8994->channels[id] = params_channels(params);
2839         if (pdata->max_channels_clocked[id] &&
2840             wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2841                 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2842                         pdata->max_channels_clocked[id], wm8994->channels[id]);
2843                 wm8994->channels[id] = pdata->max_channels_clocked[id];
2844         }
2845 
2846         switch (wm8994->channels[id]) {
2847         case 1:
2848         case 2:
2849                 bclk_rate *= 2;
2850                 break;
2851         default:
2852                 bclk_rate *= 4;
2853                 break;
2854         }
2855 
2856         /* Try to find an appropriate sample rate; look for an exact match. */
2857         for (i = 0; i < ARRAY_SIZE(srs); i++)
2858                 if (srs[i].rate == params_rate(params))
2859                         break;
2860         if (i == ARRAY_SIZE(srs))
2861                 return -EINVAL;
2862         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2863 
2864         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2865         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2866                 dai->id, wm8994->aifclk[id], bclk_rate);
2867 
2868         if (wm8994->channels[id] == 1 &&
2869             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2870                 aif2 |= WM8994_AIF1_MONO;
2871 
2872         if (wm8994->aifclk[id] == 0) {
2873                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2874                 return -EINVAL;
2875         }
2876 
2877         /* AIFCLK/fs ratio; look for a close match in either direction */
2878         best = 0;
2879         best_val = abs((fs_ratios[0] * params_rate(params))
2880                        - wm8994->aifclk[id]);
2881         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2882                 cur_val = abs((fs_ratios[i] * params_rate(params))
2883                               - wm8994->aifclk[id]);
2884                 if (cur_val >= best_val)
2885                         continue;
2886                 best = i;
2887                 best_val = cur_val;
2888         }
2889         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2890                 dai->id, fs_ratios[best]);
2891         rate_val |= best;
2892 
2893         /* We may not get quite the right frequency if using
2894          * approximate clocks so look for the closest match that is
2895          * higher than the target (we need to ensure that there enough
2896          * BCLKs to clock out the samples).
2897          */
2898         best = 0;
2899         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2900                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2901                 if (cur_val < 0) /* BCLK table is sorted */
2902                         break;
2903                 best = i;
2904         }
2905         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2906         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2907                 bclk_divs[best], bclk_rate);
2908         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2909 
2910         lrclk = bclk_rate / params_rate(params);
2911         if (!lrclk) {
2912                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2913                         bclk_rate);
2914                 return -EINVAL;
2915         }
2916         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2917                 lrclk, bclk_rate / lrclk);
2918 
2919         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2920         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2921         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2922         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2923                             lrclk);
2924         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2925                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2926 
2927         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2928                 switch (dai->id) {
2929                 case 1:
2930                         wm8994->dac_rates[0] = params_rate(params);
2931                         wm8994_set_retune_mobile(codec, 0);
2932                         wm8994_set_retune_mobile(codec, 1);
2933                         break;
2934                 case 2:
2935                         wm8994->dac_rates[1] = params_rate(params);
2936                         wm8994_set_retune_mobile(codec, 2);
2937                         break;
2938                 }
2939         }
2940 
2941         return 0;
2942 }
2943 
2944 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2945                                  struct snd_pcm_hw_params *params,
2946                                  struct snd_soc_dai *dai)
2947 {
2948         struct snd_soc_codec *codec = dai->codec;
2949         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2950         struct wm8994 *control = wm8994->wm8994;
2951         int aif1_reg;
2952         int aif1 = 0;
2953 
2954         switch (dai->id) {
2955         case 3:
2956                 switch (control->type) {
2957                 case WM1811:
2958                 case WM8958:
2959                         aif1_reg = WM8958_AIF3_CONTROL_1;
2960                         break;
2961                 default:
2962                         return 0;
2963                 }
2964                 break;
2965         default:
2966                 return 0;
2967         }
2968 
2969         switch (params_width(params)) {
2970         case 16:
2971                 break;
2972         case 20:
2973                 aif1 |= 0x20;
2974                 break;
2975         case 24:
2976                 aif1 |= 0x40;
2977                 break;
2978         case 32:
2979                 aif1 |= 0x60;
2980                 break;
2981         default:
2982                 return -EINVAL;
2983         }
2984 
2985         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2986 }
2987 
2988 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2989 {
2990         struct snd_soc_codec *codec = codec_dai->codec;
2991         int mute_reg;
2992         int reg;
2993 
2994         switch (codec_dai->id) {
2995         case 1:
2996                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2997                 break;
2998         case 2:
2999                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
3000                 break;
3001         default:
3002                 return -EINVAL;
3003         }
3004 
3005         if (mute)
3006                 reg = WM8994_AIF1DAC1_MUTE;
3007         else
3008                 reg = 0;
3009 
3010         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3011 
3012         return 0;
3013 }
3014 
3015 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3016 {
3017         struct snd_soc_codec *codec = codec_dai->codec;
3018         int reg, val, mask;
3019 
3020         switch (codec_dai->id) {
3021         case 1:
3022                 reg = WM8994_AIF1_MASTER_SLAVE;
3023                 mask = WM8994_AIF1_TRI;
3024                 break;
3025         case 2:
3026                 reg = WM8994_AIF2_MASTER_SLAVE;
3027                 mask = WM8994_AIF2_TRI;
3028                 break;
3029         default:
3030                 return -EINVAL;
3031         }
3032 
3033         if (tristate)
3034                 val = mask;
3035         else
3036                 val = 0;
3037 
3038         return snd_soc_update_bits(codec, reg, mask, val);
3039 }
3040 
3041 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3042 {
3043         struct snd_soc_codec *codec = dai->codec;
3044 
3045         /* Disable the pulls on the AIF if we're using it to save power. */
3046         snd_soc_update_bits(codec, WM8994_GPIO_3,
3047                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
3048         snd_soc_update_bits(codec, WM8994_GPIO_4,
3049                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
3050         snd_soc_update_bits(codec, WM8994_GPIO_5,
3051                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
3052 
3053         return 0;
3054 }
3055 
3056 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3057 
3058 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3059                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3060 
3061 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3062         .set_sysclk     = wm8994_set_dai_sysclk,
3063         .set_fmt        = wm8994_set_dai_fmt,
3064         .hw_params      = wm8994_hw_params,
3065         .digital_mute   = wm8994_aif_mute,
3066         .set_pll        = wm8994_set_fll,
3067         .set_tristate   = wm8994_set_tristate,
3068 };
3069 
3070 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3071         .set_sysclk     = wm8994_set_dai_sysclk,
3072         .set_fmt        = wm8994_set_dai_fmt,
3073         .hw_params      = wm8994_hw_params,
3074         .digital_mute   = wm8994_aif_mute,
3075         .set_pll        = wm8994_set_fll,
3076         .set_tristate   = wm8994_set_tristate,
3077 };
3078 
3079 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3080         .hw_params      = wm8994_aif3_hw_params,
3081 };
3082 
3083 static struct snd_soc_dai_driver wm8994_dai[] = {
3084         {
3085                 .name = "wm8994-aif1",
3086                 .id = 1,
3087                 .playback = {
3088                         .stream_name = "AIF1 Playback",
3089                         .channels_min = 1,
3090                         .channels_max = 2,
3091                         .rates = WM8994_RATES,
3092                         .formats = WM8994_FORMATS,
3093                         .sig_bits = 24,
3094                 },
3095                 .capture = {
3096                         .stream_name = "AIF1 Capture",
3097                         .channels_min = 1,
3098                         .channels_max = 2,
3099                         .rates = WM8994_RATES,
3100                         .formats = WM8994_FORMATS,
3101                         .sig_bits = 24,
3102                  },
3103                 .ops = &wm8994_aif1_dai_ops,
3104         },
3105         {
3106                 .name = "wm8994-aif2",
3107                 .id = 2,
3108                 .playback = {
3109                         .stream_name = "AIF2 Playback",
3110                         .channels_min = 1,
3111                         .channels_max = 2,
3112                         .rates = WM8994_RATES,
3113                         .formats = WM8994_FORMATS,
3114                         .sig_bits = 24,
3115                 },
3116                 .capture = {
3117                         .stream_name = "AIF2 Capture",
3118                         .channels_min = 1,
3119                         .channels_max = 2,
3120                         .rates = WM8994_RATES,
3121                         .formats = WM8994_FORMATS,
3122                         .sig_bits = 24,
3123                 },
3124                 .probe = wm8994_aif2_probe,
3125                 .ops = &wm8994_aif2_dai_ops,
3126         },
3127         {
3128                 .name = "wm8994-aif3",
3129                 .id = 3,
3130                 .playback = {
3131                         .stream_name = "AIF3 Playback",
3132                         .channels_min = 1,
3133                         .channels_max = 2,
3134                         .rates = WM8994_RATES,
3135                         .formats = WM8994_FORMATS,
3136                         .sig_bits = 24,
3137                 },
3138                 .capture = {
3139                         .stream_name = "AIF3 Capture",
3140                         .channels_min = 1,
3141                         .channels_max = 2,
3142                         .rates = WM8994_RATES,
3143                         .formats = WM8994_FORMATS,
3144                         .sig_bits = 24,
3145                  },
3146                 .ops = &wm8994_aif3_dai_ops,
3147         }
3148 };
3149 
3150 #ifdef CONFIG_PM
3151 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3152 {
3153         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3154         int i, ret;
3155 
3156         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3157                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3158                        sizeof(struct wm8994_fll_config));
3159                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3160                 if (ret < 0)
3161                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3162                                  i + 1, ret);
3163         }
3164 
3165         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3166 
3167         return 0;
3168 }
3169 
3170 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3171 {
3172         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3173         int i, ret;
3174 
3175         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3176                 if (!wm8994->fll_suspend[i].out)
3177                         continue;
3178 
3179                 ret = _wm8994_set_fll(codec, i + 1,
3180                                      wm8994->fll_suspend[i].src,
3181                                      wm8994->fll_suspend[i].in,
3182                                      wm8994->fll_suspend[i].out);
3183                 if (ret < 0)
3184                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3185                                  i + 1, ret);
3186         }
3187 
3188         return 0;
3189 }
3190 #else
3191 #define wm8994_codec_suspend NULL
3192 #define wm8994_codec_resume NULL
3193 #endif
3194 
3195 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3196 {
3197         struct snd_soc_codec *codec = wm8994->hubs.codec;
3198         struct wm8994 *control = wm8994->wm8994;
3199         struct wm8994_pdata *pdata = &control->pdata;
3200         struct snd_kcontrol_new controls[] = {
3201                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3202                              wm8994->retune_mobile_enum,
3203                              wm8994_get_retune_mobile_enum,
3204                              wm8994_put_retune_mobile_enum),
3205                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3206                              wm8994->retune_mobile_enum,
3207                              wm8994_get_retune_mobile_enum,
3208                              wm8994_put_retune_mobile_enum),
3209                 SOC_ENUM_EXT("AIF2 EQ Mode",
3210                              wm8994->retune_mobile_enum,
3211                              wm8994_get_retune_mobile_enum,
3212                              wm8994_put_retune_mobile_enum),
3213         };
3214         int ret, i, j;
3215         const char **t;
3216 
3217         /* We need an array of texts for the enum API but the number
3218          * of texts is likely to be less than the number of
3219          * configurations due to the sample rate dependency of the
3220          * configurations. */
3221         wm8994->num_retune_mobile_texts = 0;
3222         wm8994->retune_mobile_texts = NULL;
3223         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3224                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3225                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
3226                                    wm8994->retune_mobile_texts[j]) == 0)
3227                                 break;
3228                 }
3229 
3230                 if (j != wm8994->num_retune_mobile_texts)
3231                         continue;
3232 
3233                 /* Expand the array... */
3234                 t = krealloc(wm8994->retune_mobile_texts,
3235                              sizeof(char *) *
3236                              (wm8994->num_retune_mobile_texts + 1),
3237                              GFP_KERNEL);
3238                 if (t == NULL)
3239                         continue;
3240 
3241                 /* ...store the new entry... */
3242                 t[wm8994->num_retune_mobile_texts] =
3243                         pdata->retune_mobile_cfgs[i].name;
3244 
3245                 /* ...and remember the new version. */
3246                 wm8994->num_retune_mobile_texts++;
3247                 wm8994->retune_mobile_texts = t;
3248         }
3249 
3250         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3251                 wm8994->num_retune_mobile_texts);
3252 
3253         wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
3254         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3255 
3256         ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3257                                    ARRAY_SIZE(controls));
3258         if (ret != 0)
3259                 dev_err(wm8994->hubs.codec->dev,
3260                         "Failed to add ReTune Mobile controls: %d\n", ret);
3261 }
3262 
3263 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3264 {
3265         struct snd_soc_codec *codec = wm8994->hubs.codec;
3266         struct wm8994 *control = wm8994->wm8994;
3267         struct wm8994_pdata *pdata = &control->pdata;
3268         int ret, i;
3269 
3270         if (!pdata)
3271                 return;
3272 
3273         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3274                                       pdata->lineout2_diff,
3275                                       pdata->lineout1fb,
3276                                       pdata->lineout2fb,
3277                                       pdata->jd_scthr,
3278                                       pdata->jd_thr,
3279                                       pdata->micb1_delay,
3280                                       pdata->micb2_delay,
3281                                       pdata->micbias1_lvl,
3282                                       pdata->micbias2_lvl);
3283 
3284         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3285 
3286         if (pdata->num_drc_cfgs) {
3287                 struct snd_kcontrol_new controls[] = {
3288                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3289                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3290                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3291                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3292                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3293                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3294                 };
3295 
3296                 /* We need an array of texts for the enum API */
3297                 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3298                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3299                 if (!wm8994->drc_texts)
3300                         return;
3301 
3302                 for (i = 0; i < pdata->num_drc_cfgs; i++)
3303                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3304 
3305                 wm8994->drc_enum.items = pdata->num_drc_cfgs;
3306                 wm8994->drc_enum.texts = wm8994->drc_texts;
3307 
3308                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3309                                            ARRAY_SIZE(controls));
3310                 for (i = 0; i < WM8994_NUM_DRC; i++)
3311                         wm8994_set_drc(codec, i);
3312         } else {
3313                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3314                                                  wm8994_drc_controls,
3315                                                  ARRAY_SIZE(wm8994_drc_controls));
3316         }
3317 
3318         if (ret != 0)
3319                 dev_err(wm8994->hubs.codec->dev,
3320                         "Failed to add DRC mode controls: %d\n", ret);
3321 
3322 
3323         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3324                 pdata->num_retune_mobile_cfgs);
3325 
3326         if (pdata->num_retune_mobile_cfgs)
3327                 wm8994_handle_retune_mobile_pdata(wm8994);
3328         else
3329                 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3330                                      ARRAY_SIZE(wm8994_eq_controls));
3331 
3332         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3333                 if (pdata->micbias[i]) {
3334                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
3335                                 pdata->micbias[i] & 0xffff);
3336                 }
3337         }
3338 }
3339 
3340 /**
3341  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3342  *
3343  * @codec:   WM8994 codec
3344  * @jack:    jack to report detection events on
3345  * @micbias: microphone bias to detect on
3346  *
3347  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
3348  * being used to bring out signals to the processor then only platform
3349  * data configuration is needed for WM8994 and processor GPIOs should
3350  * be configured using snd_soc_jack_add_gpios() instead.
3351  *
3352  * Configuration of detection levels is available via the micbias1_lvl
3353  * and micbias2_lvl platform data members.
3354  */
3355 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3356                       int micbias)
3357 {
3358         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3359         struct wm8994_micdet *micdet;
3360         struct wm8994 *control = wm8994->wm8994;
3361         int reg, ret;
3362 
3363         if (control->type != WM8994) {
3364                 dev_warn(codec->dev, "Not a WM8994\n");
3365                 return -EINVAL;
3366         }
3367 
3368         switch (micbias) {
3369         case 1:
3370                 micdet = &wm8994->micdet[0];
3371                 if (jack)
3372                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3373                                                             "MICBIAS1");
3374                 else
3375                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3376                                                        "MICBIAS1");
3377                 break;
3378         case 2:
3379                 micdet = &wm8994->micdet[1];
3380                 if (jack)
3381                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3382                                                             "MICBIAS1");
3383                 else
3384                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3385                                                        "MICBIAS1");
3386                 break;
3387         default:
3388                 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3389                 return -EINVAL;
3390         }
3391 
3392         if (ret != 0)
3393                 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3394                          micbias, ret);
3395 
3396         dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3397                 micbias, jack);
3398 
3399         /* Store the configuration */
3400         micdet->jack = jack;
3401         micdet->detecting = true;
3402 
3403         /* If either of the jacks is set up then enable detection */
3404         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3405                 reg = WM8994_MICD_ENA;
3406         else
3407                 reg = 0;
3408 
3409         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3410 
3411         /* enable MICDET and MICSHRT deboune */
3412         snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3413                             WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3414                             WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3415                             WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3416 
3417         snd_soc_dapm_sync(&codec->dapm);
3418 
3419         return 0;
3420 }
3421 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3422 
3423 static void wm8994_mic_work(struct work_struct *work)
3424 {
3425         struct wm8994_priv *priv = container_of(work,
3426                                                 struct wm8994_priv,
3427                                                 mic_work.work);
3428         struct regmap *regmap = priv->wm8994->regmap;
3429         struct device *dev = priv->wm8994->dev;
3430         unsigned int reg;
3431         int ret;
3432         int report;
3433 
3434         pm_runtime_get_sync(dev);
3435 
3436         ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3437         if (ret < 0) {
3438                 dev_err(dev, "Failed to read microphone status: %d\n",
3439                         ret);
3440                 pm_runtime_put(dev);
3441                 return;
3442         }
3443 
3444         dev_dbg(dev, "Microphone status: %x\n", reg);
3445 
3446         report = 0;
3447         if (reg & WM8994_MIC1_DET_STS) {
3448                 if (priv->micdet[0].detecting)
3449                         report = SND_JACK_HEADSET;
3450         }
3451         if (reg & WM8994_MIC1_SHRT_STS) {
3452                 if (priv->micdet[0].detecting)
3453                         report = SND_JACK_HEADPHONE;
3454                 else
3455                         report |= SND_JACK_BTN_0;
3456         }
3457         if (report)
3458                 priv->micdet[0].detecting = false;
3459         else
3460                 priv->micdet[0].detecting = true;
3461 
3462         snd_soc_jack_report(priv->micdet[0].jack, report,
3463                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3464 
3465         report = 0;
3466         if (reg & WM8994_MIC2_DET_STS) {
3467                 if (priv->micdet[1].detecting)
3468                         report = SND_JACK_HEADSET;
3469         }
3470         if (reg & WM8994_MIC2_SHRT_STS) {
3471                 if (priv->micdet[1].detecting)
3472                         report = SND_JACK_HEADPHONE;
3473                 else
3474                         report |= SND_JACK_BTN_0;
3475         }
3476         if (report)
3477                 priv->micdet[1].detecting = false;
3478         else
3479                 priv->micdet[1].detecting = true;
3480 
3481         snd_soc_jack_report(priv->micdet[1].jack, report,
3482                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3483 
3484         pm_runtime_put(dev);
3485 }
3486 
3487 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3488 {
3489         struct wm8994_priv *priv = data;
3490         struct snd_soc_codec *codec = priv->hubs.codec;
3491 
3492 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3493         trace_snd_soc_jack_irq(dev_name(codec->dev));
3494 #endif
3495 
3496         pm_wakeup_event(codec->dev, 300);
3497 
3498         queue_delayed_work(system_power_efficient_wq,
3499                            &priv->mic_work, msecs_to_jiffies(250));
3500 
3501         return IRQ_HANDLED;
3502 }
3503 
3504 /* Should be called with accdet_lock held */
3505 static void wm1811_micd_stop(struct snd_soc_codec *codec)
3506 {
3507         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3508 
3509         if (!wm8994->jackdet)
3510                 return;
3511 
3512         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3513 
3514         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3515 
3516         if (wm8994->wm8994->pdata.jd_ext_cap)
3517                 snd_soc_dapm_disable_pin(&codec->dapm,
3518                                          "MICBIAS2");
3519 }
3520 
3521 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
3522 {
3523         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3524         int report;
3525 
3526         report = 0;
3527         if (status & 0x4)
3528                 report |= SND_JACK_BTN_0;
3529 
3530         if (status & 0x8)
3531                 report |= SND_JACK_BTN_1;
3532 
3533         if (status & 0x10)
3534                 report |= SND_JACK_BTN_2;
3535 
3536         if (status & 0x20)
3537                 report |= SND_JACK_BTN_3;
3538 
3539         if (status & 0x40)
3540                 report |= SND_JACK_BTN_4;
3541 
3542         if (status & 0x80)
3543                 report |= SND_JACK_BTN_5;
3544 
3545         snd_soc_jack_report(wm8994->micdet[0].jack, report,
3546                             wm8994->btn_mask);
3547 }
3548 
3549 static void wm8958_open_circuit_work(struct work_struct *work)
3550 {
3551         struct wm8994_priv *wm8994 = container_of(work,
3552                                                   struct wm8994_priv,
3553                                                   open_circuit_work.work);
3554         struct device *dev = wm8994->wm8994->dev;
3555 
3556         mutex_lock(&wm8994->accdet_lock);
3557 
3558         wm1811_micd_stop(wm8994->hubs.codec);
3559 
3560         dev_dbg(dev, "Reporting open circuit\n");
3561 
3562         wm8994->jack_mic = false;
3563         wm8994->mic_detecting = true;
3564 
3565         wm8958_micd_set_rate(wm8994->hubs.codec);
3566 
3567         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3568                             wm8994->btn_mask |
3569                             SND_JACK_HEADSET);
3570 
3571         mutex_unlock(&wm8994->accdet_lock);
3572 }
3573 
3574 static void wm8958_mic_id(void *data, u16 status)
3575 {
3576         struct snd_soc_codec *codec = data;
3577         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3578 
3579         /* Either nothing present or just starting detection */
3580         if (!(status & WM8958_MICD_STS)) {
3581                 /* If nothing present then clear our statuses */
3582                 dev_dbg(codec->dev, "Detected open circuit\n");
3583 
3584                 queue_delayed_work(system_power_efficient_wq,
3585                                    &wm8994->open_circuit_work,
3586                                    msecs_to_jiffies(2500));
3587                 return;
3588         }
3589 
3590         /* If the measurement is showing a high impedence we've got a
3591          * microphone.
3592          */
3593         if (status & 0x600) {
3594                 dev_dbg(codec->dev, "Detected microphone\n");
3595 
3596                 wm8994->mic_detecting = false;
3597                 wm8994->jack_mic = true;
3598 
3599                 wm8958_micd_set_rate(codec);
3600 
3601                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3602                                     SND_JACK_HEADSET);
3603         }
3604 
3605 
3606         if (status & 0xfc) {
3607                 dev_dbg(codec->dev, "Detected headphone\n");
3608                 wm8994->mic_detecting = false;
3609 
3610                 wm8958_micd_set_rate(codec);
3611 
3612                 /* If we have jackdet that will detect removal */
3613                 wm1811_micd_stop(codec);
3614 
3615                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3616                                     SND_JACK_HEADSET);
3617         }
3618 }
3619 
3620 /* Deferred mic detection to allow for extra settling time */
3621 static void wm1811_mic_work(struct work_struct *work)
3622 {
3623         struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3624                                                   mic_work.work);
3625         struct wm8994 *control = wm8994->wm8994;
3626         struct snd_soc_codec *codec = wm8994->hubs.codec;
3627 
3628         pm_runtime_get_sync(codec->dev);
3629 
3630         /* If required for an external cap force MICBIAS on */
3631         if (control->pdata.jd_ext_cap) {
3632                 snd_soc_dapm_force_enable_pin(&codec->dapm,
3633                                               "MICBIAS2");
3634                 snd_soc_dapm_sync(&codec->dapm);
3635         }
3636 
3637         mutex_lock(&wm8994->accdet_lock);
3638 
3639         dev_dbg(codec->dev, "Starting mic detection\n");
3640 
3641         /* Use a user-supplied callback if we have one */
3642         if (wm8994->micd_cb) {
3643                 wm8994->micd_cb(wm8994->micd_cb_data);
3644         } else {
3645                 /*
3646                  * Start off measument of microphone impedence to find out
3647                  * what's actually there.
3648                  */
3649                 wm8994->mic_detecting = true;
3650                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3651 
3652                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3653                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3654         }
3655 
3656         mutex_unlock(&wm8994->accdet_lock);
3657 
3658         pm_runtime_put(codec->dev);
3659 }
3660 
3661 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3662 {
3663         struct wm8994_priv *wm8994 = data;
3664         struct wm8994 *control = wm8994->wm8994;
3665         struct snd_soc_codec *codec = wm8994->hubs.codec;
3666         int reg, delay;
3667         bool present;
3668 
3669         pm_runtime_get_sync(codec->dev);
3670 
3671         cancel_delayed_work_sync(&wm8994->mic_complete_work);
3672 
3673         mutex_lock(&wm8994->accdet_lock);
3674 
3675         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3676         if (reg < 0) {
3677                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3678                 mutex_unlock(&wm8994->accdet_lock);
3679                 pm_runtime_put(codec->dev);
3680                 return IRQ_NONE;
3681         }
3682 
3683         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3684 
3685         present = reg & WM1811_JACKDET_LVL;
3686 
3687         if (present) {
3688                 dev_dbg(codec->dev, "Jack detected\n");
3689 
3690                 wm8958_micd_set_rate(codec);
3691 
3692                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3693                                     WM8958_MICB2_DISCH, 0);
3694 
3695                 /* Disable debounce while inserted */
3696                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3697                                     WM1811_JACKDET_DB, 0);
3698 
3699                 delay = control->pdata.micdet_delay;
3700                 queue_delayed_work(system_power_efficient_wq,
3701                                    &wm8994->mic_work,
3702                                    msecs_to_jiffies(delay));
3703         } else {
3704                 dev_dbg(codec->dev, "Jack not detected\n");
3705 
3706                 cancel_delayed_work_sync(&wm8994->mic_work);
3707 
3708                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3709                                     WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3710 
3711                 /* Enable debounce while removed */
3712                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3713                                     WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3714 
3715                 wm8994->mic_detecting = false;
3716                 wm8994->jack_mic = false;
3717                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3718                                     WM8958_MICD_ENA, 0);
3719                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3720         }
3721 
3722         mutex_unlock(&wm8994->accdet_lock);
3723 
3724         /* Turn off MICBIAS if it was on for an external cap */
3725         if (control->pdata.jd_ext_cap && !present)
3726                 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3727 
3728         if (present)
3729                 snd_soc_jack_report(wm8994->micdet[0].jack,
3730                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3731         else
3732                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3733                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3734                                     wm8994->btn_mask);
3735 
3736         /* Since we only report deltas force an update, ensures we
3737          * avoid bootstrapping issues with the core. */
3738         snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3739 
3740         pm_runtime_put(codec->dev);
3741         return IRQ_HANDLED;
3742 }
3743 
3744 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3745 {
3746         struct wm8994_priv *wm8994 = container_of(work,
3747                                                 struct wm8994_priv,
3748                                                 jackdet_bootstrap.work);
3749         wm1811_jackdet_irq(0, wm8994);
3750 }
3751 
3752 /**
3753  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3754  *
3755  * @codec:   WM8958 codec
3756  * @jack:    jack to report detection events on
3757  *
3758  * Enable microphone detection functionality for the WM8958.  By
3759  * default simple detection which supports the detection of up to 6
3760  * buttons plus video and microphone functionality is supported.
3761  *
3762  * The WM8958 has an advanced jack detection facility which is able to
3763  * support complex accessory detection, especially when used in
3764  * conjunction with external circuitry.  In order to provide maximum
3765  * flexiblity a callback is provided which allows a completely custom
3766  * detection algorithm.
3767  */
3768 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3769                       wm1811_micdet_cb det_cb, void *det_cb_data,
3770                       wm1811_mic_id_cb id_cb, void *id_cb_data)
3771 {
3772         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3773         struct wm8994 *control = wm8994->wm8994;
3774         u16 micd_lvl_sel;
3775 
3776         switch (control->type) {
3777         case WM1811:
3778         case WM8958:
3779                 break;
3780         default:
3781                 return -EINVAL;
3782         }
3783 
3784         if (jack) {
3785                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3786                 snd_soc_dapm_sync(&codec->dapm);
3787 
3788                 wm8994->micdet[0].jack = jack;
3789 
3790                 if (det_cb) {
3791                         wm8994->micd_cb = det_cb;
3792                         wm8994->micd_cb_data = det_cb_data;
3793                 } else {
3794                         wm8994->mic_detecting = true;
3795                         wm8994->jack_mic = false;
3796                 }
3797 
3798                 if (id_cb) {
3799                         wm8994->mic_id_cb = id_cb;
3800                         wm8994->mic_id_cb_data = id_cb_data;
3801                 } else {
3802                         wm8994->mic_id_cb = wm8958_mic_id;
3803                         wm8994->mic_id_cb_data = codec;
3804                 }
3805 
3806                 wm8958_micd_set_rate(codec);
3807 
3808                 /* Detect microphones and short circuits by default */
3809                 if (control->pdata.micd_lvl_sel)
3810                         micd_lvl_sel = control->pdata.micd_lvl_sel;
3811                 else
3812                         micd_lvl_sel = 0x41;
3813 
3814                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3815                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3816                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3817 
3818                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3819                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3820 
3821                 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3822 
3823                 /*
3824                  * If we can use jack detection start off with that,
3825                  * otherwise jump straight to microphone detection.
3826                  */
3827                 if (wm8994->jackdet) {
3828                         /* Disable debounce for the initial detect */
3829                         snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3830                                             WM1811_JACKDET_DB, 0);
3831 
3832                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
3833                                             WM8958_MICB2_DISCH,
3834                                             WM8958_MICB2_DISCH);
3835                         snd_soc_update_bits(codec, WM8994_LDO_1,
3836                                             WM8994_LDO1_DISCH, 0);
3837                         wm1811_jackdet_set_mode(codec,
3838                                                 WM1811_JACKDET_MODE_JACK);
3839                 } else {
3840                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3841                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3842                 }
3843 
3844         } else {
3845                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3846                                     WM8958_MICD_ENA, 0);
3847                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3848                 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3849                 snd_soc_dapm_sync(&codec->dapm);
3850         }
3851 
3852         return 0;
3853 }
3854 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3855 
3856 static void wm8958_mic_work(struct work_struct *work)
3857 {
3858         struct wm8994_priv *wm8994 = container_of(work,
3859                                                   struct wm8994_priv,
3860                                                   mic_complete_work.work);
3861         struct snd_soc_codec *codec = wm8994->hubs.codec;
3862 
3863         pm_runtime_get_sync(codec->dev);
3864 
3865         mutex_lock(&wm8994->accdet_lock);
3866 
3867         wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3868 
3869         mutex_unlock(&wm8994->accdet_lock);
3870 
3871         pm_runtime_put(codec->dev);
3872 }
3873 
3874 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3875 {
3876         struct wm8994_priv *wm8994 = data;
3877         struct snd_soc_codec *codec = wm8994->hubs.codec;
3878         int reg, count, ret, id_delay;
3879 
3880         /*
3881          * Jack detection may have detected a removal simulataneously
3882          * with an update of the MICDET status; if so it will have
3883          * stopped detection and we can ignore this interrupt.
3884          */
3885         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3886                 return IRQ_HANDLED;
3887 
3888         cancel_delayed_work_sync(&wm8994->mic_complete_work);
3889         cancel_delayed_work_sync(&wm8994->open_circuit_work);
3890 
3891         pm_runtime_get_sync(codec->dev);
3892 
3893         /* We may occasionally read a detection without an impedence
3894          * range being provided - if that happens loop again.
3895          */
3896         count = 10;
3897         do {
3898                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3899                 if (reg < 0) {
3900                         dev_err(codec->dev,
3901                                 "Failed to read mic detect status: %d\n",
3902                                 reg);
3903                         pm_runtime_put(codec->dev);
3904                         return IRQ_NONE;
3905                 }
3906 
3907                 if (!(reg & WM8958_MICD_VALID)) {
3908                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3909                         goto out;
3910                 }
3911 
3912                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3913                         break;
3914 
3915                 msleep(1);
3916         } while (count--);
3917 
3918         if (count == 0)
3919                 dev_warn(codec->dev, "No impedance range reported for jack\n");
3920 
3921 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3922         trace_snd_soc_jack_irq(dev_name(codec->dev));
3923 #endif
3924 
3925         /* Avoid a transient report when the accessory is being removed */
3926         if (wm8994->jackdet) {
3927                 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3928                 if (ret < 0) {
3929                         dev_err(codec->dev, "Failed to read jack status: %d\n",
3930                                 ret);
3931                 } else if (!(ret & WM1811_JACKDET_LVL)) {
3932                         dev_dbg(codec->dev, "Ignoring removed jack\n");
3933                         goto out;
3934                 }
3935         } else if (!(reg & WM8958_MICD_STS)) {
3936                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3937                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3938                                     wm8994->btn_mask);
3939                 wm8994->mic_detecting = true;
3940                 goto out;
3941         }
3942 
3943         wm8994->mic_status = reg;
3944         id_delay = wm8994->wm8994->pdata.mic_id_delay;
3945 
3946         if (wm8994->mic_detecting)
3947                 queue_delayed_work(system_power_efficient_wq,
3948                                    &wm8994->mic_complete_work,
3949                                    msecs_to_jiffies(id_delay));
3950         else
3951                 wm8958_button_det(codec, reg);
3952 
3953 out:
3954         pm_runtime_put(codec->dev);
3955         return IRQ_HANDLED;
3956 }
3957 
3958 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3959 {
3960         struct snd_soc_codec *codec = data;
3961 
3962         dev_err(codec->dev, "FIFO error\n");
3963 
3964         return IRQ_HANDLED;
3965 }
3966 
3967 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3968 {
3969         struct snd_soc_codec *codec = data;
3970 
3971         dev_err(codec->dev, "Thermal warning\n");
3972 
3973         return IRQ_HANDLED;
3974 }
3975 
3976 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3977 {
3978         struct snd_soc_codec *codec = data;
3979 
3980         dev_crit(codec->dev, "Thermal shutdown\n");
3981 
3982         return IRQ_HANDLED;
3983 }
3984 
3985 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3986 {
3987         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3988         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3989         struct snd_soc_dapm_context *dapm = &codec->dapm;
3990         unsigned int reg;
3991         int ret, i;
3992 
3993         wm8994->hubs.codec = codec;
3994 
3995         mutex_init(&wm8994->accdet_lock);
3996         INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3997                           wm1811_jackdet_bootstrap);
3998         INIT_DELAYED_WORK(&wm8994->open_circuit_work,
3999                           wm8958_open_circuit_work);
4000 
4001         switch (control->type) {
4002         case WM8994:
4003                 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4004                 break;
4005         case WM1811:
4006                 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4007                 break;
4008         default:
4009                 break;
4010         }
4011 
4012         INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4013 
4014         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4015                 init_completion(&wm8994->fll_locked[i]);
4016 
4017         wm8994->micdet_irq = control->pdata.micdet_irq;
4018 
4019         /* By default use idle_bias_off, will override for WM8994 */
4020         codec->dapm.idle_bias_off = 1;
4021 
4022         /* Set revision-specific configuration */
4023         switch (control->type) {
4024         case WM8994:
4025                 /* Single ended line outputs should have VMID on. */
4026                 if (!control->pdata.lineout1_diff ||
4027                     !control->pdata.lineout2_diff)
4028                         codec->dapm.idle_bias_off = 0;
4029 
4030                 switch (control->revision) {
4031                 case 2:
4032                 case 3:
4033                         wm8994->hubs.dcs_codes_l = -5;
4034                         wm8994->hubs.dcs_codes_r = -5;
4035                         wm8994->hubs.hp_startup_mode = 1;
4036                         wm8994->hubs.dcs_readback_mode = 1;
4037                         wm8994->hubs.series_startup = 1;
4038                         break;
4039                 default:
4040                         wm8994->hubs.dcs_readback_mode = 2;
4041                         break;
4042                 }
4043                 break;
4044 
4045         case WM8958:
4046                 wm8994->hubs.dcs_readback_mode = 1;
4047                 wm8994->hubs.hp_startup_mode = 1;
4048 
4049                 switch (control->revision) {
4050                 case 0:
4051                         break;
4052                 default:
4053                         wm8994->fll_byp = true;
4054                         break;
4055                 }
4056                 break;
4057 
4058         case WM1811:
4059                 wm8994->hubs.dcs_readback_mode = 2;
4060                 wm8994->hubs.no_series_update = 1;
4061                 wm8994->hubs.hp_startup_mode = 1;
4062                 wm8994->hubs.no_cache_dac_hp_direct = true;
4063                 wm8994->fll_byp = true;
4064 
4065                 wm8994->hubs.dcs_codes_l = -9;
4066                 wm8994->hubs.dcs_codes_r = -7;
4067 
4068                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
4069                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4070                 break;
4071 
4072         default:
4073                 break;
4074         }
4075 
4076         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4077                            wm8994_fifo_error, "FIFO error", codec);
4078         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4079                            wm8994_temp_warn, "Thermal warning", codec);
4080         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4081                            wm8994_temp_shut, "Thermal shutdown", codec);
4082 
4083         switch (control->type) {
4084         case WM8994:
4085                 if (wm8994->micdet_irq) {
4086                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4087                                                    wm8994_mic_irq,
4088                                                    IRQF_TRIGGER_RISING,
4089                                                    "Mic1 detect",
4090                                                    wm8994);
4091                         if (ret != 0)
4092                                 dev_warn(codec->dev,
4093                                          "Failed to request Mic1 detect IRQ: %d\n",
4094                                          ret);
4095                 }
4096 
4097                 ret = wm8994_request_irq(wm8994->wm8994,
4098                                          WM8994_IRQ_MIC1_SHRT,
4099                                          wm8994_mic_irq, "Mic 1 short",
4100                                          wm8994);
4101                 if (ret != 0)
4102                         dev_warn(codec->dev,
4103                                  "Failed to request Mic1 short IRQ: %d\n",
4104                                  ret);
4105 
4106                 ret = wm8994_request_irq(wm8994->wm8994,
4107                                          WM8994_IRQ_MIC2_DET,
4108                                          wm8994_mic_irq, "Mic 2 detect",
4109                                          wm8994);
4110                 if (ret != 0)
4111                         dev_warn(codec->dev,
4112                                  "Failed to request Mic2 detect IRQ: %d\n",
4113                                  ret);
4114 
4115                 ret = wm8994_request_irq(wm8994->wm8994,
4116                                          WM8994_IRQ_MIC2_SHRT,
4117                                          wm8994_mic_irq, "Mic 2 short",
4118                                          wm8994);
4119                 if (ret != 0)
4120                         dev_warn(codec->dev,
4121                                  "Failed to request Mic2 short IRQ: %d\n",
4122                                  ret);
4123                 break;
4124 
4125         case WM8958:
4126         case WM1811:
4127                 if (wm8994->micdet_irq) {
4128                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4129                                                    wm8958_mic_irq,
4130                                                    IRQF_TRIGGER_RISING,
4131                                                    "Mic detect",
4132                                                    wm8994);
4133                         if (ret != 0)
4134                                 dev_warn(codec->dev,
4135                                          "Failed to request Mic detect IRQ: %d\n",
4136                                          ret);
4137                 } else {
4138                         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4139                                            wm8958_mic_irq, "Mic detect",
4140                                            wm8994);
4141                 }
4142         }
4143 
4144         switch (control->type) {
4145         case WM1811:
4146                 if (control->cust_id > 1 || control->revision > 1) {
4147                         ret = wm8994_request_irq(wm8994->wm8994,
4148                                                  WM8994_IRQ_GPIO(6),
4149                                                  wm1811_jackdet_irq, "JACKDET",
4150                                                  wm8994);
4151                         if (ret == 0)
4152                                 wm8994->jackdet = true;
4153                 }
4154                 break;
4155         default:
4156                 break;
4157         }
4158 
4159         wm8994->fll_locked_irq = true;
4160         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4161                 ret = wm8994_request_irq(wm8994->wm8994,
4162                                          WM8994_IRQ_FLL1_LOCK + i,
4163                                          wm8994_fll_locked_irq, "FLL lock",
4164                                          &wm8994->fll_locked[i]);
4165                 if (ret != 0)
4166                         wm8994->fll_locked_irq = false;
4167         }
4168 
4169         /* Make sure we can read from the GPIOs if they're inputs */
4170         pm_runtime_get_sync(codec->dev);
4171 
4172         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
4173          * configured on init - if a system wants to do this dynamically
4174          * at runtime we can deal with that then.
4175          */
4176         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
4177         if (ret < 0) {
4178                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
4179                 goto err_irq;
4180         }
4181         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4182                 wm8994->lrclk_shared[0] = 1;
4183                 wm8994_dai[0].symmetric_rates = 1;
4184         } else {
4185                 wm8994->lrclk_shared[0] = 0;
4186         }
4187 
4188         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
4189         if (ret < 0) {
4190                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4191                 goto err_irq;
4192         }
4193         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4194                 wm8994->lrclk_shared[1] = 1;
4195                 wm8994_dai[1].symmetric_rates = 1;
4196         } else {
4197                 wm8994->lrclk_shared[1] = 0;
4198         }
4199 
4200         pm_runtime_put(codec->dev);
4201 
4202         /* Latch volume update bits */
4203         for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4204                 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4205                                     wm8994_vu_bits[i].mask,
4206                                     wm8994_vu_bits[i].mask);
4207 
4208         /* Set the low bit of the 3D stereo depth so TLV matches */
4209         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4210                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4211                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4212         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4213                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4214                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4215         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4216                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4217                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4218 
4219         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4220          * use this; it only affects behaviour on idle TDM clock
4221          * cycles. */
4222         switch (control->type) {
4223         case WM8994:
4224         case WM8958:
4225                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4226                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4227                 break;
4228         default:
4229                 break;
4230         }
4231 
4232         /* Put MICBIAS into bypass mode by default on newer devices */
4233         switch (control->type) {
4234         case WM8958:
4235         case WM1811:
4236                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4237                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4238                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4239                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4240                 break;
4241         default:
4242                 break;
4243         }
4244 
4245         wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4246         wm_hubs_update_class_w(codec);
4247 
4248         wm8994_handle_pdata(wm8994);
4249 
4250         wm_hubs_add_analogue_controls(codec);
4251         snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4252                              ARRAY_SIZE(wm8994_snd_controls));
4253         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4254                                   ARRAY_SIZE(wm8994_dapm_widgets));
4255 
4256         switch (control->type) {
4257         case WM8994:
4258                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4259                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
4260                 if (control->revision < 4) {
4261                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4262                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4263                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4264                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4265                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4266                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4267                 } else {
4268                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4269                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4270                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4271                                                   ARRAY_SIZE(wm8994_adc_widgets));
4272                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4273                                                   ARRAY_SIZE(wm8994_dac_widgets));
4274                 }
4275                 break;
4276         case WM8958:
4277                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4278                                      ARRAY_SIZE(wm8958_snd_controls));
4279                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4280                                           ARRAY_SIZE(wm8958_dapm_widgets));
4281                 if (control->revision < 1) {
4282                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4283                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4284                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4285                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4286                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4287                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4288                 } else {
4289                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4290                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4291                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4292                                                   ARRAY_SIZE(wm8994_adc_widgets));
4293                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4294                                                   ARRAY_SIZE(wm8994_dac_widgets));
4295                 }
4296                 break;
4297 
4298         case WM1811:
4299                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4300                                      ARRAY_SIZE(wm8958_snd_controls));
4301                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4302                                           ARRAY_SIZE(wm8958_dapm_widgets));
4303                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4304                                           ARRAY_SIZE(wm8994_lateclk_widgets));
4305                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4306                                           ARRAY_SIZE(wm8994_adc_widgets));
4307                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4308                                           ARRAY_SIZE(wm8994_dac_widgets));
4309                 break;
4310         }
4311 
4312         wm_hubs_add_analogue_routes(codec, 0, 0);
4313         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4314                                  wm_hubs_dcs_done, "DC servo done",
4315                                  &wm8994->hubs);
4316         if (ret == 0)
4317                 wm8994->hubs.dcs_done_irq = true;
4318         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4319 
4320         switch (control->type) {
4321         case WM8994:
4322                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4323                                         ARRAY_SIZE(wm8994_intercon));
4324 
4325                 if (control->revision < 4) {
4326                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4327                                                 ARRAY_SIZE(wm8994_revd_intercon));
4328                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4329                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4330                 } else {
4331                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4332                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4333                 }
4334                 break;
4335         case WM8958:
4336                 if (control->revision < 1) {
4337                         snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4338                                                 ARRAY_SIZE(wm8994_intercon));
4339                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4340                                                 ARRAY_SIZE(wm8994_revd_intercon));
4341                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4342                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4343                 } else {
4344                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4345                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4346                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4347                                                 ARRAY_SIZE(wm8958_intercon));
4348                 }
4349 
4350                 wm8958_dsp2_init(codec);
4351                 break;
4352         case WM1811:
4353                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4354                                         ARRAY_SIZE(wm8994_lateclk_intercon));
4355                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4356                                         ARRAY_SIZE(wm8958_intercon));
4357                 break;
4358         }
4359 
4360         return 0;
4361 
4362 err_irq:
4363         if (wm8994->jackdet)
4364                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4365         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4366         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4367         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4368         if (wm8994->micdet_irq)
4369                 free_irq(wm8994->micdet_irq, wm8994);
4370         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4371                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4372                                 &wm8994->fll_locked[i]);
4373         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4374                         &wm8994->hubs);
4375         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4376         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4377         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4378 
4379         return ret;
4380 }
4381 
4382 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4383 {
4384         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4385         struct wm8994 *control = wm8994->wm8994;
4386         int i;
4387 
4388         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4389 
4390         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4391                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4392                                 &wm8994->fll_locked[i]);
4393 
4394         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4395                         &wm8994->hubs);
4396         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4397         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4398         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4399 
4400         if (wm8994->jackdet)
4401                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4402 
4403         switch (control->type) {
4404         case WM8994:
4405                 if (wm8994->micdet_irq)
4406                         free_irq(wm8994->micdet_irq, wm8994);
4407                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4408                                 wm8994);
4409                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4410                                 wm8994);
4411                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4412                                 wm8994);
4413                 break;
4414 
4415         case WM1811:
4416         case WM8958:
4417                 if (wm8994->micdet_irq)
4418                         free_irq(wm8994->micdet_irq, wm8994);
4419                 break;
4420         }
4421         release_firmware(wm8994->mbc);
4422         release_firmware(wm8994->mbc_vss);
4423         release_firmware(wm8994->enh_eq);
4424         kfree(wm8994->retune_mobile_texts);
4425         return 0;
4426 }
4427 
4428 static struct regmap *wm8994_get_regmap(struct device *dev)
4429 {
4430         struct wm8994 *control = dev_get_drvdata(dev->parent);
4431 
4432         return control->regmap;
4433 }
4434 
4435 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4436         .probe =        wm8994_codec_probe,
4437         .remove =       wm8994_codec_remove,
4438         .suspend =      wm8994_codec_suspend,
4439         .resume =       wm8994_codec_resume,
4440         .get_regmap =   wm8994_get_regmap,
4441         .set_bias_level = wm8994_set_bias_level,
4442 };
4443 
4444 static int wm8994_probe(struct platform_device *pdev)
4445 {
4446         struct wm8994_priv *wm8994;
4447 
4448         wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4449                               GFP_KERNEL);
4450         if (wm8994 == NULL)
4451                 return -ENOMEM;
4452         platform_set_drvdata(pdev, wm8994);
4453 
4454         wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4455 
4456         pm_runtime_enable(&pdev->dev);
4457         pm_runtime_idle(&pdev->dev);
4458 
4459         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4460                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
4461 }
4462 
4463 static int wm8994_remove(struct platform_device *pdev)
4464 {
4465         snd_soc_unregister_codec(&pdev->dev);
4466         pm_runtime_disable(&pdev->dev);
4467 
4468         return 0;
4469 }
4470 
4471 #ifdef CONFIG_PM_SLEEP
4472 static int wm8994_suspend(struct device *dev)
4473 {
4474         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4475 
4476         /* Drop down to power saving mode when system is suspended */
4477         if (wm8994->jackdet && !wm8994->active_refcount)
4478                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4479                                    WM1811_JACKDET_MODE_MASK,
4480                                    wm8994->jackdet_mode);
4481 
4482         return 0;
4483 }
4484 
4485 static int wm8994_resume(struct device *dev)
4486 {
4487         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4488 
4489         if (wm8994->jackdet && wm8994->jackdet_mode)
4490                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4491                                    WM1811_JACKDET_MODE_MASK,
4492                                    WM1811_JACKDET_MODE_AUDIO);
4493 
4494         return 0;
4495 }
4496 #endif
4497 
4498 static const struct dev_pm_ops wm8994_pm_ops = {
4499         SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4500 };
4501 
4502 static struct platform_driver wm8994_codec_driver = {
4503         .driver = {
4504                 .name = "wm8994-codec",
4505                 .owner = THIS_MODULE,
4506                 .pm = &wm8994_pm_ops,
4507         },
4508         .probe = wm8994_probe,
4509         .remove = wm8994_remove,
4510 };
4511 
4512 module_platform_driver(wm8994_codec_driver);
4513 
4514 MODULE_DESCRIPTION("ASoC WM8994 driver");
4515 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4516 MODULE_LICENSE("GPL");
4517 MODULE_ALIAS("platform:wm8994-codec");
4518 

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