Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/sound/soc/codecs/wm8962.c

  1 /*
  2  * wm8962.c  --  WM8962 ALSA SoC Audio driver
  3  *
  4  * Copyright 2010-2 Wolfson Microelectronics plc
  5  *
  6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7  *
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 
 14 #include <linux/module.h>
 15 #include <linux/moduleparam.h>
 16 #include <linux/init.h>
 17 #include <linux/clk.h>
 18 #include <linux/delay.h>
 19 #include <linux/pm.h>
 20 #include <linux/gcd.h>
 21 #include <linux/gpio.h>
 22 #include <linux/i2c.h>
 23 #include <linux/input.h>
 24 #include <linux/pm_runtime.h>
 25 #include <linux/regmap.h>
 26 #include <linux/regulator/consumer.h>
 27 #include <linux/slab.h>
 28 #include <linux/workqueue.h>
 29 #include <linux/mutex.h>
 30 #include <sound/core.h>
 31 #include <sound/jack.h>
 32 #include <sound/pcm.h>
 33 #include <sound/pcm_params.h>
 34 #include <sound/soc.h>
 35 #include <sound/initval.h>
 36 #include <sound/tlv.h>
 37 #include <sound/wm8962.h>
 38 #include <trace/events/asoc.h>
 39 
 40 #include "wm8962.h"
 41 
 42 #define WM8962_NUM_SUPPLIES 8
 43 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
 44         "DCVDD",
 45         "DBVDD",
 46         "AVDD",
 47         "CPVDD",
 48         "MICVDD",
 49         "PLLVDD",
 50         "SPKVDD1",
 51         "SPKVDD2",
 52 };
 53 
 54 /* codec private data */
 55 struct wm8962_priv {
 56         struct wm8962_pdata pdata;
 57         struct regmap *regmap;
 58         struct snd_soc_codec *codec;
 59 
 60         int sysclk;
 61         int sysclk_rate;
 62 
 63         int bclk;  /* Desired BCLK */
 64         int lrclk;
 65 
 66         struct completion fll_lock;
 67         int fll_src;
 68         int fll_fref;
 69         int fll_fout;
 70 
 71         struct mutex dsp2_ena_lock;
 72         u16 dsp2_ena;
 73 
 74         struct delayed_work mic_work;
 75         struct snd_soc_jack *jack;
 76 
 77         struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
 78         struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
 79 
 80         struct input_dev *beep;
 81         struct work_struct beep_work;
 82         int beep_rate;
 83 
 84 #ifdef CONFIG_GPIOLIB
 85         struct gpio_chip gpio_chip;
 86 #endif
 87 
 88         int irq;
 89 };
 90 
 91 /* We can't use the same notifier block for more than one supply and
 92  * there's no way I can see to get from a callback to the caller
 93  * except container_of().
 94  */
 95 #define WM8962_REGULATOR_EVENT(n) \
 96 static int wm8962_regulator_event_##n(struct notifier_block *nb, \
 97                                     unsigned long event, void *data)    \
 98 { \
 99         struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
100                                                   disable_nb[n]); \
101         if (event & REGULATOR_EVENT_DISABLE) { \
102                 regcache_mark_dirty(wm8962->regmap);    \
103         } \
104         return 0; \
105 }
106 
107 WM8962_REGULATOR_EVENT(0)
108 WM8962_REGULATOR_EVENT(1)
109 WM8962_REGULATOR_EVENT(2)
110 WM8962_REGULATOR_EVENT(3)
111 WM8962_REGULATOR_EVENT(4)
112 WM8962_REGULATOR_EVENT(5)
113 WM8962_REGULATOR_EVENT(6)
114 WM8962_REGULATOR_EVENT(7)
115 
116 static struct reg_default wm8962_reg[] = {
117         { 0, 0x009F },   /* R0     - Left Input volume */
118         { 1, 0x049F },   /* R1     - Right Input volume */
119         { 2, 0x0000 },   /* R2     - HPOUTL volume */
120         { 3, 0x0000 },   /* R3     - HPOUTR volume */
121 
122         { 5, 0x0018 },   /* R5     - ADC & DAC Control 1 */
123         { 6, 0x2008 },   /* R6     - ADC & DAC Control 2 */
124         { 7, 0x000A },   /* R7     - Audio Interface 0 */
125 
126         { 9, 0x0300 },   /* R9     - Audio Interface 1 */
127         { 10, 0x00C0 },  /* R10    - Left DAC volume */
128         { 11, 0x00C0 },  /* R11    - Right DAC volume */
129 
130         { 14, 0x0040 },   /* R14    - Audio Interface 2 */
131         { 15, 0x6243 },   /* R15    - Software Reset */
132 
133         { 17, 0x007B },   /* R17    - ALC1 */
134 
135         { 19, 0x1C32 },   /* R19    - ALC3 */
136         { 20, 0x3200 },   /* R20    - Noise Gate */
137         { 21, 0x00C0 },   /* R21    - Left ADC volume */
138         { 22, 0x00C0 },   /* R22    - Right ADC volume */
139         { 23, 0x0160 },   /* R23    - Additional control(1) */
140         { 24, 0x0000 },   /* R24    - Additional control(2) */
141         { 25, 0x0000 },   /* R25    - Pwr Mgmt (1) */
142         { 26, 0x0000 },   /* R26    - Pwr Mgmt (2) */
143         { 27, 0x0010 },   /* R27    - Additional Control (3) */
144         { 28, 0x0000 },   /* R28    - Anti-pop */
145 
146         { 30, 0x005E },   /* R30    - Clocking 3 */
147         { 31, 0x0000 },   /* R31    - Input mixer control (1) */
148         { 32, 0x0145 },   /* R32    - Left input mixer volume */
149         { 33, 0x0145 },   /* R33    - Right input mixer volume */
150         { 34, 0x0009 },   /* R34    - Input mixer control (2) */
151         { 35, 0x0003 },   /* R35    - Input bias control */
152         { 37, 0x0008 },   /* R37    - Left input PGA control */
153         { 38, 0x0008 },   /* R38    - Right input PGA control */
154 
155         { 40, 0x0000 },   /* R40    - SPKOUTL volume */
156         { 41, 0x0000 },   /* R41    - SPKOUTR volume */
157 
158         { 49, 0x0010 },   /* R49    - Class D Control 1 */
159         { 51, 0x0003 },   /* R51    - Class D Control 2 */
160 
161         { 56, 0x0506 },   /* R56    - Clocking 4 */
162         { 57, 0x0000 },   /* R57    - DAC DSP Mixing (1) */
163         { 58, 0x0000 },   /* R58    - DAC DSP Mixing (2) */
164 
165         { 60, 0x0300 },   /* R60    - DC Servo 0 */
166         { 61, 0x0300 },   /* R61    - DC Servo 1 */
167 
168         { 64, 0x0810 },   /* R64    - DC Servo 4 */
169 
170         { 68, 0x001B },   /* R68    - Analogue PGA Bias */
171         { 69, 0x0000 },   /* R69    - Analogue HP 0 */
172 
173         { 71, 0x01FB },   /* R71    - Analogue HP 2 */
174         { 72, 0x0000 },   /* R72    - Charge Pump 1 */
175 
176         { 82, 0x0004 },   /* R82    - Charge Pump B */
177 
178         { 87, 0x0000 },   /* R87    - Write Sequencer Control 1 */
179 
180         { 90, 0x0000 },   /* R90    - Write Sequencer Control 2 */
181 
182         { 93, 0x0000 },   /* R93    - Write Sequencer Control 3 */
183         { 94, 0x0000 },   /* R94    - Control Interface */
184 
185         { 99, 0x0000 },   /* R99    - Mixer Enables */
186         { 100, 0x0000 },   /* R100   - Headphone Mixer (1) */
187         { 101, 0x0000 },   /* R101   - Headphone Mixer (2) */
188         { 102, 0x013F },   /* R102   - Headphone Mixer (3) */
189         { 103, 0x013F },   /* R103   - Headphone Mixer (4) */
190 
191         { 105, 0x0000 },   /* R105   - Speaker Mixer (1) */
192         { 106, 0x0000 },   /* R106   - Speaker Mixer (2) */
193         { 107, 0x013F },   /* R107   - Speaker Mixer (3) */
194         { 108, 0x013F },   /* R108   - Speaker Mixer (4) */
195         { 109, 0x0003 },   /* R109   - Speaker Mixer (5) */
196         { 110, 0x0002 },   /* R110   - Beep Generator (1) */
197 
198         { 115, 0x0006 },   /* R115   - Oscillator Trim (3) */
199         { 116, 0x0026 },   /* R116   - Oscillator Trim (4) */
200 
201         { 119, 0x0000 },   /* R119   - Oscillator Trim (7) */
202 
203         { 124, 0x0011 },   /* R124   - Analogue Clocking1 */
204         { 125, 0x004B },   /* R125   - Analogue Clocking2 */
205         { 126, 0x000D },   /* R126   - Analogue Clocking3 */
206         { 127, 0x0000 },   /* R127   - PLL Software Reset */
207 
208         { 131, 0x0000 },   /* R131   - PLL 4 */
209 
210         { 136, 0x0067 },   /* R136   - PLL 9 */
211         { 137, 0x001C },   /* R137   - PLL 10 */
212         { 138, 0x0071 },   /* R138   - PLL 11 */
213         { 139, 0x00C7 },   /* R139   - PLL 12 */
214         { 140, 0x0067 },   /* R140   - PLL 13 */
215         { 141, 0x0048 },   /* R141   - PLL 14 */
216         { 142, 0x0022 },   /* R142   - PLL 15 */
217         { 143, 0x0097 },   /* R143   - PLL 16 */
218 
219         { 155, 0x000C },   /* R155   - FLL Control (1) */
220         { 156, 0x0039 },   /* R156   - FLL Control (2) */
221         { 157, 0x0180 },   /* R157   - FLL Control (3) */
222 
223         { 159, 0x0032 },   /* R159   - FLL Control (5) */
224         { 160, 0x0018 },   /* R160   - FLL Control (6) */
225         { 161, 0x007D },   /* R161   - FLL Control (7) */
226         { 162, 0x0008 },   /* R162   - FLL Control (8) */
227 
228         { 252, 0x0005 },   /* R252   - General test 1 */
229 
230         { 256, 0x0000 },   /* R256   - DF1 */
231         { 257, 0x0000 },   /* R257   - DF2 */
232         { 258, 0x0000 },   /* R258   - DF3 */
233         { 259, 0x0000 },   /* R259   - DF4 */
234         { 260, 0x0000 },   /* R260   - DF5 */
235         { 261, 0x0000 },   /* R261   - DF6 */
236         { 262, 0x0000 },   /* R262   - DF7 */
237 
238         { 264, 0x0000 },   /* R264   - LHPF1 */
239         { 265, 0x0000 },   /* R265   - LHPF2 */
240 
241         { 268, 0x0000 },   /* R268   - THREED1 */
242         { 269, 0x0000 },   /* R269   - THREED2 */
243         { 270, 0x0000 },   /* R270   - THREED3 */
244         { 271, 0x0000 },   /* R271   - THREED4 */
245 
246         { 276, 0x000C },   /* R276   - DRC 1 */
247         { 277, 0x0925 },   /* R277   - DRC 2 */
248         { 278, 0x0000 },   /* R278   - DRC 3 */
249         { 279, 0x0000 },   /* R279   - DRC 4 */
250         { 280, 0x0000 },   /* R280   - DRC 5 */
251 
252         { 285, 0x0000 },   /* R285   - Tloopback */
253 
254         { 335, 0x0004 },   /* R335   - EQ1 */
255         { 336, 0x6318 },   /* R336   - EQ2 */
256         { 337, 0x6300 },   /* R337   - EQ3 */
257         { 338, 0x0FCA },   /* R338   - EQ4 */
258         { 339, 0x0400 },   /* R339   - EQ5 */
259         { 340, 0x00D8 },   /* R340   - EQ6 */
260         { 341, 0x1EB5 },   /* R341   - EQ7 */
261         { 342, 0xF145 },   /* R342   - EQ8 */
262         { 343, 0x0B75 },   /* R343   - EQ9 */
263         { 344, 0x01C5 },   /* R344   - EQ10 */
264         { 345, 0x1C58 },   /* R345   - EQ11 */
265         { 346, 0xF373 },   /* R346   - EQ12 */
266         { 347, 0x0A54 },   /* R347   - EQ13 */
267         { 348, 0x0558 },   /* R348   - EQ14 */
268         { 349, 0x168E },   /* R349   - EQ15 */
269         { 350, 0xF829 },   /* R350   - EQ16 */
270         { 351, 0x07AD },   /* R351   - EQ17 */
271         { 352, 0x1103 },   /* R352   - EQ18 */
272         { 353, 0x0564 },   /* R353   - EQ19 */
273         { 354, 0x0559 },   /* R354   - EQ20 */
274         { 355, 0x4000 },   /* R355   - EQ21 */
275         { 356, 0x6318 },   /* R356   - EQ22 */
276         { 357, 0x6300 },   /* R357   - EQ23 */
277         { 358, 0x0FCA },   /* R358   - EQ24 */
278         { 359, 0x0400 },   /* R359   - EQ25 */
279         { 360, 0x00D8 },   /* R360   - EQ26 */
280         { 361, 0x1EB5 },   /* R361   - EQ27 */
281         { 362, 0xF145 },   /* R362   - EQ28 */
282         { 363, 0x0B75 },   /* R363   - EQ29 */
283         { 364, 0x01C5 },   /* R364   - EQ30 */
284         { 365, 0x1C58 },   /* R365   - EQ31 */
285         { 366, 0xF373 },   /* R366   - EQ32 */
286         { 367, 0x0A54 },   /* R367   - EQ33 */
287         { 368, 0x0558 },   /* R368   - EQ34 */
288         { 369, 0x168E },   /* R369   - EQ35 */
289         { 370, 0xF829 },   /* R370   - EQ36 */
290         { 371, 0x07AD },   /* R371   - EQ37 */
291         { 372, 0x1103 },   /* R372   - EQ38 */
292         { 373, 0x0564 },   /* R373   - EQ39 */
293         { 374, 0x0559 },   /* R374   - EQ40 */
294         { 375, 0x4000 },   /* R375   - EQ41 */
295 
296         { 513, 0x0000 },   /* R513   - GPIO 2 */
297         { 514, 0x0000 },   /* R514   - GPIO 3 */
298 
299         { 516, 0x8100 },   /* R516   - GPIO 5 */
300         { 517, 0x8100 },   /* R517   - GPIO 6 */
301 
302         { 568, 0x0030 },   /* R568   - Interrupt Status 1 Mask */
303         { 569, 0xFFED },   /* R569   - Interrupt Status 2 Mask */
304 
305         { 576, 0x0000 },   /* R576   - Interrupt Control */
306 
307         { 584, 0x002D },   /* R584   - IRQ Debounce */
308 
309         { 586, 0x0000 },   /* R586   -  MICINT Source Pol */
310 
311         { 768, 0x1C00 },   /* R768   - DSP2 Power Management */
312 
313         { 8192, 0x0000 },   /* R8192  - DSP2 Instruction RAM 0 */
314 
315         { 9216, 0x0030 },   /* R9216  - DSP2 Address RAM 2 */
316         { 9217, 0x0000 },   /* R9217  - DSP2 Address RAM 1 */
317         { 9218, 0x0000 },   /* R9218  - DSP2 Address RAM 0 */
318 
319         { 12288, 0x0000 },   /* R12288 - DSP2 Data1 RAM 1 */
320         { 12289, 0x0000 },   /* R12289 - DSP2 Data1 RAM 0 */
321 
322         { 13312, 0x0000 },   /* R13312 - DSP2 Data2 RAM 1 */
323         { 13313, 0x0000 },   /* R13313 - DSP2 Data2 RAM 0 */
324 
325         { 14336, 0x0000 },   /* R14336 - DSP2 Data3 RAM 1 */
326         { 14337, 0x0000 },   /* R14337 - DSP2 Data3 RAM 0 */
327 
328         { 15360, 0x000A },   /* R15360 - DSP2 Coeff RAM 0 */
329 
330         { 16384, 0x0000 },   /* R16384 - RETUNEADC_SHARED_COEFF_1 */
331         { 16385, 0x0000 },   /* R16385 - RETUNEADC_SHARED_COEFF_0 */
332         { 16386, 0x0000 },   /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
333         { 16387, 0x0000 },   /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
334         { 16388, 0x0000 },   /* R16388 - SOUNDSTAGE_ENABLES_1 */
335         { 16389, 0x0000 },   /* R16389 - SOUNDSTAGE_ENABLES_0 */
336 
337         { 16896, 0x0002 },   /* R16896 - HDBASS_AI_1 */
338         { 16897, 0xBD12 },   /* R16897 - HDBASS_AI_0 */
339         { 16898, 0x007C },   /* R16898 - HDBASS_AR_1 */
340         { 16899, 0x586C },   /* R16899 - HDBASS_AR_0 */
341         { 16900, 0x0053 },   /* R16900 - HDBASS_B_1 */
342         { 16901, 0x8121 },   /* R16901 - HDBASS_B_0 */
343         { 16902, 0x003F },   /* R16902 - HDBASS_K_1 */
344         { 16903, 0x8BD8 },   /* R16903 - HDBASS_K_0 */
345         { 16904, 0x0032 },   /* R16904 - HDBASS_N1_1 */
346         { 16905, 0xF52D },   /* R16905 - HDBASS_N1_0 */
347         { 16906, 0x0065 },   /* R16906 - HDBASS_N2_1 */
348         { 16907, 0xAC8C },   /* R16907 - HDBASS_N2_0 */
349         { 16908, 0x006B },   /* R16908 - HDBASS_N3_1 */
350         { 16909, 0xE087 },   /* R16909 - HDBASS_N3_0 */
351         { 16910, 0x0072 },   /* R16910 - HDBASS_N4_1 */
352         { 16911, 0x1483 },   /* R16911 - HDBASS_N4_0 */
353         { 16912, 0x0072 },   /* R16912 - HDBASS_N5_1 */
354         { 16913, 0x1483 },   /* R16913 - HDBASS_N5_0 */
355         { 16914, 0x0043 },   /* R16914 - HDBASS_X1_1 */
356         { 16915, 0x3525 },   /* R16915 - HDBASS_X1_0 */
357         { 16916, 0x0006 },   /* R16916 - HDBASS_X2_1 */
358         { 16917, 0x6A4A },   /* R16917 - HDBASS_X2_0 */
359         { 16918, 0x0043 },   /* R16918 - HDBASS_X3_1 */
360         { 16919, 0x6079 },   /* R16919 - HDBASS_X3_0 */
361         { 16920, 0x0008 },   /* R16920 - HDBASS_ATK_1 */
362         { 16921, 0x0000 },   /* R16921 - HDBASS_ATK_0 */
363         { 16922, 0x0001 },   /* R16922 - HDBASS_DCY_1 */
364         { 16923, 0x0000 },   /* R16923 - HDBASS_DCY_0 */
365         { 16924, 0x0059 },   /* R16924 - HDBASS_PG_1 */
366         { 16925, 0x999A },   /* R16925 - HDBASS_PG_0 */
367 
368         { 17048, 0x0083 },   /* R17408 - HPF_C_1 */
369         { 17049, 0x98AD },   /* R17409 - HPF_C_0 */
370 
371         { 17920, 0x007F },   /* R17920 - ADCL_RETUNE_C1_1 */
372         { 17921, 0xFFFF },   /* R17921 - ADCL_RETUNE_C1_0 */
373         { 17922, 0x0000 },   /* R17922 - ADCL_RETUNE_C2_1 */
374         { 17923, 0x0000 },   /* R17923 - ADCL_RETUNE_C2_0 */
375         { 17924, 0x0000 },   /* R17924 - ADCL_RETUNE_C3_1 */
376         { 17925, 0x0000 },   /* R17925 - ADCL_RETUNE_C3_0 */
377         { 17926, 0x0000 },   /* R17926 - ADCL_RETUNE_C4_1 */
378         { 17927, 0x0000 },   /* R17927 - ADCL_RETUNE_C4_0 */
379         { 17928, 0x0000 },   /* R17928 - ADCL_RETUNE_C5_1 */
380         { 17929, 0x0000 },   /* R17929 - ADCL_RETUNE_C5_0 */
381         { 17930, 0x0000 },   /* R17930 - ADCL_RETUNE_C6_1 */
382         { 17931, 0x0000 },   /* R17931 - ADCL_RETUNE_C6_0 */
383         { 17932, 0x0000 },   /* R17932 - ADCL_RETUNE_C7_1 */
384         { 17933, 0x0000 },   /* R17933 - ADCL_RETUNE_C7_0 */
385         { 17934, 0x0000 },   /* R17934 - ADCL_RETUNE_C8_1 */
386         { 17935, 0x0000 },   /* R17935 - ADCL_RETUNE_C8_0 */
387         { 17936, 0x0000 },   /* R17936 - ADCL_RETUNE_C9_1 */
388         { 17937, 0x0000 },   /* R17937 - ADCL_RETUNE_C9_0 */
389         { 17938, 0x0000 },   /* R17938 - ADCL_RETUNE_C10_1 */
390         { 17939, 0x0000 },   /* R17939 - ADCL_RETUNE_C10_0 */
391         { 17940, 0x0000 },   /* R17940 - ADCL_RETUNE_C11_1 */
392         { 17941, 0x0000 },   /* R17941 - ADCL_RETUNE_C11_0 */
393         { 17942, 0x0000 },   /* R17942 - ADCL_RETUNE_C12_1 */
394         { 17943, 0x0000 },   /* R17943 - ADCL_RETUNE_C12_0 */
395         { 17944, 0x0000 },   /* R17944 - ADCL_RETUNE_C13_1 */
396         { 17945, 0x0000 },   /* R17945 - ADCL_RETUNE_C13_0 */
397         { 17946, 0x0000 },   /* R17946 - ADCL_RETUNE_C14_1 */
398         { 17947, 0x0000 },   /* R17947 - ADCL_RETUNE_C14_0 */
399         { 17948, 0x0000 },   /* R17948 - ADCL_RETUNE_C15_1 */
400         { 17949, 0x0000 },   /* R17949 - ADCL_RETUNE_C15_0 */
401         { 17950, 0x0000 },   /* R17950 - ADCL_RETUNE_C16_1 */
402         { 17951, 0x0000 },   /* R17951 - ADCL_RETUNE_C16_0 */
403         { 17952, 0x0000 },   /* R17952 - ADCL_RETUNE_C17_1 */
404         { 17953, 0x0000 },   /* R17953 - ADCL_RETUNE_C17_0 */
405         { 17954, 0x0000 },   /* R17954 - ADCL_RETUNE_C18_1 */
406         { 17955, 0x0000 },   /* R17955 - ADCL_RETUNE_C18_0 */
407         { 17956, 0x0000 },   /* R17956 - ADCL_RETUNE_C19_1 */
408         { 17957, 0x0000 },   /* R17957 - ADCL_RETUNE_C19_0 */
409         { 17958, 0x0000 },   /* R17958 - ADCL_RETUNE_C20_1 */
410         { 17959, 0x0000 },   /* R17959 - ADCL_RETUNE_C20_0 */
411         { 17960, 0x0000 },   /* R17960 - ADCL_RETUNE_C21_1 */
412         { 17961, 0x0000 },   /* R17961 - ADCL_RETUNE_C21_0 */
413         { 17962, 0x0000 },   /* R17962 - ADCL_RETUNE_C22_1 */
414         { 17963, 0x0000 },   /* R17963 - ADCL_RETUNE_C22_0 */
415         { 17964, 0x0000 },   /* R17964 - ADCL_RETUNE_C23_1 */
416         { 17965, 0x0000 },   /* R17965 - ADCL_RETUNE_C23_0 */
417         { 17966, 0x0000 },   /* R17966 - ADCL_RETUNE_C24_1 */
418         { 17967, 0x0000 },   /* R17967 - ADCL_RETUNE_C24_0 */
419         { 17968, 0x0000 },   /* R17968 - ADCL_RETUNE_C25_1 */
420         { 17969, 0x0000 },   /* R17969 - ADCL_RETUNE_C25_0 */
421         { 17970, 0x0000 },   /* R17970 - ADCL_RETUNE_C26_1 */
422         { 17971, 0x0000 },   /* R17971 - ADCL_RETUNE_C26_0 */
423         { 17972, 0x0000 },   /* R17972 - ADCL_RETUNE_C27_1 */
424         { 17973, 0x0000 },   /* R17973 - ADCL_RETUNE_C27_0 */
425         { 17974, 0x0000 },   /* R17974 - ADCL_RETUNE_C28_1 */
426         { 17975, 0x0000 },   /* R17975 - ADCL_RETUNE_C28_0 */
427         { 17976, 0x0000 },   /* R17976 - ADCL_RETUNE_C29_1 */
428         { 17977, 0x0000 },   /* R17977 - ADCL_RETUNE_C29_0 */
429         { 17978, 0x0000 },   /* R17978 - ADCL_RETUNE_C30_1 */
430         { 17979, 0x0000 },   /* R17979 - ADCL_RETUNE_C30_0 */
431         { 17980, 0x0000 },   /* R17980 - ADCL_RETUNE_C31_1 */
432         { 17981, 0x0000 },   /* R17981 - ADCL_RETUNE_C31_0 */
433         { 17982, 0x0000 },   /* R17982 - ADCL_RETUNE_C32_1 */
434         { 17983, 0x0000 },   /* R17983 - ADCL_RETUNE_C32_0 */
435 
436         { 18432, 0x0020 },   /* R18432 - RETUNEADC_PG2_1 */
437         { 18433, 0x0000 },   /* R18433 - RETUNEADC_PG2_0 */
438         { 18434, 0x0040 },   /* R18434 - RETUNEADC_PG_1 */
439         { 18435, 0x0000 },   /* R18435 - RETUNEADC_PG_0 */
440 
441         { 18944, 0x007F },   /* R18944 - ADCR_RETUNE_C1_1 */
442         { 18945, 0xFFFF },   /* R18945 - ADCR_RETUNE_C1_0 */
443         { 18946, 0x0000 },   /* R18946 - ADCR_RETUNE_C2_1 */
444         { 18947, 0x0000 },   /* R18947 - ADCR_RETUNE_C2_0 */
445         { 18948, 0x0000 },   /* R18948 - ADCR_RETUNE_C3_1 */
446         { 18949, 0x0000 },   /* R18949 - ADCR_RETUNE_C3_0 */
447         { 18950, 0x0000 },   /* R18950 - ADCR_RETUNE_C4_1 */
448         { 18951, 0x0000 },   /* R18951 - ADCR_RETUNE_C4_0 */
449         { 18952, 0x0000 },   /* R18952 - ADCR_RETUNE_C5_1 */
450         { 18953, 0x0000 },   /* R18953 - ADCR_RETUNE_C5_0 */
451         { 18954, 0x0000 },   /* R18954 - ADCR_RETUNE_C6_1 */
452         { 18955, 0x0000 },   /* R18955 - ADCR_RETUNE_C6_0 */
453         { 18956, 0x0000 },   /* R18956 - ADCR_RETUNE_C7_1 */
454         { 18957, 0x0000 },   /* R18957 - ADCR_RETUNE_C7_0 */
455         { 18958, 0x0000 },   /* R18958 - ADCR_RETUNE_C8_1 */
456         { 18959, 0x0000 },   /* R18959 - ADCR_RETUNE_C8_0 */
457         { 18960, 0x0000 },   /* R18960 - ADCR_RETUNE_C9_1 */
458         { 18961, 0x0000 },   /* R18961 - ADCR_RETUNE_C9_0 */
459         { 18962, 0x0000 },   /* R18962 - ADCR_RETUNE_C10_1 */
460         { 18963, 0x0000 },   /* R18963 - ADCR_RETUNE_C10_0 */
461         { 18964, 0x0000 },   /* R18964 - ADCR_RETUNE_C11_1 */
462         { 18965, 0x0000 },   /* R18965 - ADCR_RETUNE_C11_0 */
463         { 18966, 0x0000 },   /* R18966 - ADCR_RETUNE_C12_1 */
464         { 18967, 0x0000 },   /* R18967 - ADCR_RETUNE_C12_0 */
465         { 18968, 0x0000 },   /* R18968 - ADCR_RETUNE_C13_1 */
466         { 18969, 0x0000 },   /* R18969 - ADCR_RETUNE_C13_0 */
467         { 18970, 0x0000 },   /* R18970 - ADCR_RETUNE_C14_1 */
468         { 18971, 0x0000 },   /* R18971 - ADCR_RETUNE_C14_0 */
469         { 18972, 0x0000 },   /* R18972 - ADCR_RETUNE_C15_1 */
470         { 18973, 0x0000 },   /* R18973 - ADCR_RETUNE_C15_0 */
471         { 18974, 0x0000 },   /* R18974 - ADCR_RETUNE_C16_1 */
472         { 18975, 0x0000 },   /* R18975 - ADCR_RETUNE_C16_0 */
473         { 18976, 0x0000 },   /* R18976 - ADCR_RETUNE_C17_1 */
474         { 18977, 0x0000 },   /* R18977 - ADCR_RETUNE_C17_0 */
475         { 18978, 0x0000 },   /* R18978 - ADCR_RETUNE_C18_1 */
476         { 18979, 0x0000 },   /* R18979 - ADCR_RETUNE_C18_0 */
477         { 18980, 0x0000 },   /* R18980 - ADCR_RETUNE_C19_1 */
478         { 18981, 0x0000 },   /* R18981 - ADCR_RETUNE_C19_0 */
479         { 18982, 0x0000 },   /* R18982 - ADCR_RETUNE_C20_1 */
480         { 18983, 0x0000 },   /* R18983 - ADCR_RETUNE_C20_0 */
481         { 18984, 0x0000 },   /* R18984 - ADCR_RETUNE_C21_1 */
482         { 18985, 0x0000 },   /* R18985 - ADCR_RETUNE_C21_0 */
483         { 18986, 0x0000 },   /* R18986 - ADCR_RETUNE_C22_1 */
484         { 18987, 0x0000 },   /* R18987 - ADCR_RETUNE_C22_0 */
485         { 18988, 0x0000 },   /* R18988 - ADCR_RETUNE_C23_1 */
486         { 18989, 0x0000 },   /* R18989 - ADCR_RETUNE_C23_0 */
487         { 18990, 0x0000 },   /* R18990 - ADCR_RETUNE_C24_1 */
488         { 18991, 0x0000 },   /* R18991 - ADCR_RETUNE_C24_0 */
489         { 18992, 0x0000 },   /* R18992 - ADCR_RETUNE_C25_1 */
490         { 18993, 0x0000 },   /* R18993 - ADCR_RETUNE_C25_0 */
491         { 18994, 0x0000 },   /* R18994 - ADCR_RETUNE_C26_1 */
492         { 18995, 0x0000 },   /* R18995 - ADCR_RETUNE_C26_0 */
493         { 18996, 0x0000 },   /* R18996 - ADCR_RETUNE_C27_1 */
494         { 18997, 0x0000 },   /* R18997 - ADCR_RETUNE_C27_0 */
495         { 18998, 0x0000 },   /* R18998 - ADCR_RETUNE_C28_1 */
496         { 18999, 0x0000 },   /* R18999 - ADCR_RETUNE_C28_0 */
497         { 19000, 0x0000 },   /* R19000 - ADCR_RETUNE_C29_1 */
498         { 19001, 0x0000 },   /* R19001 - ADCR_RETUNE_C29_0 */
499         { 19002, 0x0000 },   /* R19002 - ADCR_RETUNE_C30_1 */
500         { 19003, 0x0000 },   /* R19003 - ADCR_RETUNE_C30_0 */
501         { 19004, 0x0000 },   /* R19004 - ADCR_RETUNE_C31_1 */
502         { 19005, 0x0000 },   /* R19005 - ADCR_RETUNE_C31_0 */
503         { 19006, 0x0000 },   /* R19006 - ADCR_RETUNE_C32_1 */
504         { 19007, 0x0000 },   /* R19007 - ADCR_RETUNE_C32_0 */
505 
506         { 19456, 0x007F },   /* R19456 - DACL_RETUNE_C1_1 */
507         { 19457, 0xFFFF },   /* R19457 - DACL_RETUNE_C1_0 */
508         { 19458, 0x0000 },   /* R19458 - DACL_RETUNE_C2_1 */
509         { 19459, 0x0000 },   /* R19459 - DACL_RETUNE_C2_0 */
510         { 19460, 0x0000 },   /* R19460 - DACL_RETUNE_C3_1 */
511         { 19461, 0x0000 },   /* R19461 - DACL_RETUNE_C3_0 */
512         { 19462, 0x0000 },   /* R19462 - DACL_RETUNE_C4_1 */
513         { 19463, 0x0000 },   /* R19463 - DACL_RETUNE_C4_0 */
514         { 19464, 0x0000 },   /* R19464 - DACL_RETUNE_C5_1 */
515         { 19465, 0x0000 },   /* R19465 - DACL_RETUNE_C5_0 */
516         { 19466, 0x0000 },   /* R19466 - DACL_RETUNE_C6_1 */
517         { 19467, 0x0000 },   /* R19467 - DACL_RETUNE_C6_0 */
518         { 19468, 0x0000 },   /* R19468 - DACL_RETUNE_C7_1 */
519         { 19469, 0x0000 },   /* R19469 - DACL_RETUNE_C7_0 */
520         { 19470, 0x0000 },   /* R19470 - DACL_RETUNE_C8_1 */
521         { 19471, 0x0000 },   /* R19471 - DACL_RETUNE_C8_0 */
522         { 19472, 0x0000 },   /* R19472 - DACL_RETUNE_C9_1 */
523         { 19473, 0x0000 },   /* R19473 - DACL_RETUNE_C9_0 */
524         { 19474, 0x0000 },   /* R19474 - DACL_RETUNE_C10_1 */
525         { 19475, 0x0000 },   /* R19475 - DACL_RETUNE_C10_0 */
526         { 19476, 0x0000 },   /* R19476 - DACL_RETUNE_C11_1 */
527         { 19477, 0x0000 },   /* R19477 - DACL_RETUNE_C11_0 */
528         { 19478, 0x0000 },   /* R19478 - DACL_RETUNE_C12_1 */
529         { 19479, 0x0000 },   /* R19479 - DACL_RETUNE_C12_0 */
530         { 19480, 0x0000 },   /* R19480 - DACL_RETUNE_C13_1 */
531         { 19481, 0x0000 },   /* R19481 - DACL_RETUNE_C13_0 */
532         { 19482, 0x0000 },   /* R19482 - DACL_RETUNE_C14_1 */
533         { 19483, 0x0000 },   /* R19483 - DACL_RETUNE_C14_0 */
534         { 19484, 0x0000 },   /* R19484 - DACL_RETUNE_C15_1 */
535         { 19485, 0x0000 },   /* R19485 - DACL_RETUNE_C15_0 */
536         { 19486, 0x0000 },   /* R19486 - DACL_RETUNE_C16_1 */
537         { 19487, 0x0000 },   /* R19487 - DACL_RETUNE_C16_0 */
538         { 19488, 0x0000 },   /* R19488 - DACL_RETUNE_C17_1 */
539         { 19489, 0x0000 },   /* R19489 - DACL_RETUNE_C17_0 */
540         { 19490, 0x0000 },   /* R19490 - DACL_RETUNE_C18_1 */
541         { 19491, 0x0000 },   /* R19491 - DACL_RETUNE_C18_0 */
542         { 19492, 0x0000 },   /* R19492 - DACL_RETUNE_C19_1 */
543         { 19493, 0x0000 },   /* R19493 - DACL_RETUNE_C19_0 */
544         { 19494, 0x0000 },   /* R19494 - DACL_RETUNE_C20_1 */
545         { 19495, 0x0000 },   /* R19495 - DACL_RETUNE_C20_0 */
546         { 19496, 0x0000 },   /* R19496 - DACL_RETUNE_C21_1 */
547         { 19497, 0x0000 },   /* R19497 - DACL_RETUNE_C21_0 */
548         { 19498, 0x0000 },   /* R19498 - DACL_RETUNE_C22_1 */
549         { 19499, 0x0000 },   /* R19499 - DACL_RETUNE_C22_0 */
550         { 19500, 0x0000 },   /* R19500 - DACL_RETUNE_C23_1 */
551         { 19501, 0x0000 },   /* R19501 - DACL_RETUNE_C23_0 */
552         { 19502, 0x0000 },   /* R19502 - DACL_RETUNE_C24_1 */
553         { 19503, 0x0000 },   /* R19503 - DACL_RETUNE_C24_0 */
554         { 19504, 0x0000 },   /* R19504 - DACL_RETUNE_C25_1 */
555         { 19505, 0x0000 },   /* R19505 - DACL_RETUNE_C25_0 */
556         { 19506, 0x0000 },   /* R19506 - DACL_RETUNE_C26_1 */
557         { 19507, 0x0000 },   /* R19507 - DACL_RETUNE_C26_0 */
558         { 19508, 0x0000 },   /* R19508 - DACL_RETUNE_C27_1 */
559         { 19509, 0x0000 },   /* R19509 - DACL_RETUNE_C27_0 */
560         { 19510, 0x0000 },   /* R19510 - DACL_RETUNE_C28_1 */
561         { 19511, 0x0000 },   /* R19511 - DACL_RETUNE_C28_0 */
562         { 19512, 0x0000 },   /* R19512 - DACL_RETUNE_C29_1 */
563         { 19513, 0x0000 },   /* R19513 - DACL_RETUNE_C29_0 */
564         { 19514, 0x0000 },   /* R19514 - DACL_RETUNE_C30_1 */
565         { 19515, 0x0000 },   /* R19515 - DACL_RETUNE_C30_0 */
566         { 19516, 0x0000 },   /* R19516 - DACL_RETUNE_C31_1 */
567         { 19517, 0x0000 },   /* R19517 - DACL_RETUNE_C31_0 */
568         { 19518, 0x0000 },   /* R19518 - DACL_RETUNE_C32_1 */
569         { 19519, 0x0000 },   /* R19519 - DACL_RETUNE_C32_0 */
570 
571         { 19968, 0x0020 },   /* R19968 - RETUNEDAC_PG2_1 */
572         { 19969, 0x0000 },   /* R19969 - RETUNEDAC_PG2_0 */
573         { 19970, 0x0040 },   /* R19970 - RETUNEDAC_PG_1 */
574         { 19971, 0x0000 },   /* R19971 - RETUNEDAC_PG_0 */
575 
576         { 20480, 0x007F },   /* R20480 - DACR_RETUNE_C1_1 */
577         { 20481, 0xFFFF },   /* R20481 - DACR_RETUNE_C1_0 */
578         { 20482, 0x0000 },   /* R20482 - DACR_RETUNE_C2_1 */
579         { 20483, 0x0000 },   /* R20483 - DACR_RETUNE_C2_0 */
580         { 20484, 0x0000 },   /* R20484 - DACR_RETUNE_C3_1 */
581         { 20485, 0x0000 },   /* R20485 - DACR_RETUNE_C3_0 */
582         { 20486, 0x0000 },   /* R20486 - DACR_RETUNE_C4_1 */
583         { 20487, 0x0000 },   /* R20487 - DACR_RETUNE_C4_0 */
584         { 20488, 0x0000 },   /* R20488 - DACR_RETUNE_C5_1 */
585         { 20489, 0x0000 },   /* R20489 - DACR_RETUNE_C5_0 */
586         { 20490, 0x0000 },   /* R20490 - DACR_RETUNE_C6_1 */
587         { 20491, 0x0000 },   /* R20491 - DACR_RETUNE_C6_0 */
588         { 20492, 0x0000 },   /* R20492 - DACR_RETUNE_C7_1 */
589         { 20493, 0x0000 },   /* R20493 - DACR_RETUNE_C7_0 */
590         { 20494, 0x0000 },   /* R20494 - DACR_RETUNE_C8_1 */
591         { 20495, 0x0000 },   /* R20495 - DACR_RETUNE_C8_0 */
592         { 20496, 0x0000 },   /* R20496 - DACR_RETUNE_C9_1 */
593         { 20497, 0x0000 },   /* R20497 - DACR_RETUNE_C9_0 */
594         { 20498, 0x0000 },   /* R20498 - DACR_RETUNE_C10_1 */
595         { 20499, 0x0000 },   /* R20499 - DACR_RETUNE_C10_0 */
596         { 20500, 0x0000 },   /* R20500 - DACR_RETUNE_C11_1 */
597         { 20501, 0x0000 },   /* R20501 - DACR_RETUNE_C11_0 */
598         { 20502, 0x0000 },   /* R20502 - DACR_RETUNE_C12_1 */
599         { 20503, 0x0000 },   /* R20503 - DACR_RETUNE_C12_0 */
600         { 20504, 0x0000 },   /* R20504 - DACR_RETUNE_C13_1 */
601         { 20505, 0x0000 },   /* R20505 - DACR_RETUNE_C13_0 */
602         { 20506, 0x0000 },   /* R20506 - DACR_RETUNE_C14_1 */
603         { 20507, 0x0000 },   /* R20507 - DACR_RETUNE_C14_0 */
604         { 20508, 0x0000 },   /* R20508 - DACR_RETUNE_C15_1 */
605         { 20509, 0x0000 },   /* R20509 - DACR_RETUNE_C15_0 */
606         { 20510, 0x0000 },   /* R20510 - DACR_RETUNE_C16_1 */
607         { 20511, 0x0000 },   /* R20511 - DACR_RETUNE_C16_0 */
608         { 20512, 0x0000 },   /* R20512 - DACR_RETUNE_C17_1 */
609         { 20513, 0x0000 },   /* R20513 - DACR_RETUNE_C17_0 */
610         { 20514, 0x0000 },   /* R20514 - DACR_RETUNE_C18_1 */
611         { 20515, 0x0000 },   /* R20515 - DACR_RETUNE_C18_0 */
612         { 20516, 0x0000 },   /* R20516 - DACR_RETUNE_C19_1 */
613         { 20517, 0x0000 },   /* R20517 - DACR_RETUNE_C19_0 */
614         { 20518, 0x0000 },   /* R20518 - DACR_RETUNE_C20_1 */
615         { 20519, 0x0000 },   /* R20519 - DACR_RETUNE_C20_0 */
616         { 20520, 0x0000 },   /* R20520 - DACR_RETUNE_C21_1 */
617         { 20521, 0x0000 },   /* R20521 - DACR_RETUNE_C21_0 */
618         { 20522, 0x0000 },   /* R20522 - DACR_RETUNE_C22_1 */
619         { 20523, 0x0000 },   /* R20523 - DACR_RETUNE_C22_0 */
620         { 20524, 0x0000 },   /* R20524 - DACR_RETUNE_C23_1 */
621         { 20525, 0x0000 },   /* R20525 - DACR_RETUNE_C23_0 */
622         { 20526, 0x0000 },   /* R20526 - DACR_RETUNE_C24_1 */
623         { 20527, 0x0000 },   /* R20527 - DACR_RETUNE_C24_0 */
624         { 20528, 0x0000 },   /* R20528 - DACR_RETUNE_C25_1 */
625         { 20529, 0x0000 },   /* R20529 - DACR_RETUNE_C25_0 */
626         { 20530, 0x0000 },   /* R20530 - DACR_RETUNE_C26_1 */
627         { 20531, 0x0000 },   /* R20531 - DACR_RETUNE_C26_0 */
628         { 20532, 0x0000 },   /* R20532 - DACR_RETUNE_C27_1 */
629         { 20533, 0x0000 },   /* R20533 - DACR_RETUNE_C27_0 */
630         { 20534, 0x0000 },   /* R20534 - DACR_RETUNE_C28_1 */
631         { 20535, 0x0000 },   /* R20535 - DACR_RETUNE_C28_0 */
632         { 20536, 0x0000 },   /* R20536 - DACR_RETUNE_C29_1 */
633         { 20537, 0x0000 },   /* R20537 - DACR_RETUNE_C29_0 */
634         { 20538, 0x0000 },   /* R20538 - DACR_RETUNE_C30_1 */
635         { 20539, 0x0000 },   /* R20539 - DACR_RETUNE_C30_0 */
636         { 20540, 0x0000 },   /* R20540 - DACR_RETUNE_C31_1 */
637         { 20541, 0x0000 },   /* R20541 - DACR_RETUNE_C31_0 */
638         { 20542, 0x0000 },   /* R20542 - DACR_RETUNE_C32_1 */
639         { 20543, 0x0000 },   /* R20543 - DACR_RETUNE_C32_0 */
640 
641         { 20992, 0x008C },   /* R20992 - VSS_XHD2_1 */
642         { 20993, 0x0200 },   /* R20993 - VSS_XHD2_0 */
643         { 20994, 0x0035 },   /* R20994 - VSS_XHD3_1 */
644         { 20995, 0x0700 },   /* R20995 - VSS_XHD3_0 */
645         { 20996, 0x003A },   /* R20996 - VSS_XHN1_1 */
646         { 20997, 0x4100 },   /* R20997 - VSS_XHN1_0 */
647         { 20998, 0x008B },   /* R20998 - VSS_XHN2_1 */
648         { 20999, 0x7D00 },   /* R20999 - VSS_XHN2_0 */
649         { 21000, 0x003A },   /* R21000 - VSS_XHN3_1 */
650         { 21001, 0x4100 },   /* R21001 - VSS_XHN3_0 */
651         { 21002, 0x008C },   /* R21002 - VSS_XLA_1 */
652         { 21003, 0xFEE8 },   /* R21003 - VSS_XLA_0 */
653         { 21004, 0x0078 },   /* R21004 - VSS_XLB_1 */
654         { 21005, 0x0000 },   /* R21005 - VSS_XLB_0 */
655         { 21006, 0x003F },   /* R21006 - VSS_XLG_1 */
656         { 21007, 0xB260 },   /* R21007 - VSS_XLG_0 */
657         { 21008, 0x002D },   /* R21008 - VSS_PG2_1 */
658         { 21009, 0x1818 },   /* R21009 - VSS_PG2_0 */
659         { 21010, 0x0020 },   /* R21010 - VSS_PG_1 */
660         { 21011, 0x0000 },   /* R21011 - VSS_PG_0 */
661         { 21012, 0x00F1 },   /* R21012 - VSS_XTD1_1 */
662         { 21013, 0x8340 },   /* R21013 - VSS_XTD1_0 */
663         { 21014, 0x00FB },   /* R21014 - VSS_XTD2_1 */
664         { 21015, 0x8300 },   /* R21015 - VSS_XTD2_0 */
665         { 21016, 0x00EE },   /* R21016 - VSS_XTD3_1 */
666         { 21017, 0xAEC0 },   /* R21017 - VSS_XTD3_0 */
667         { 21018, 0x00FB },   /* R21018 - VSS_XTD4_1 */
668         { 21019, 0xAC40 },   /* R21019 - VSS_XTD4_0 */
669         { 21020, 0x00F1 },   /* R21020 - VSS_XTD5_1 */
670         { 21021, 0x7F80 },   /* R21021 - VSS_XTD5_0 */
671         { 21022, 0x00F4 },   /* R21022 - VSS_XTD6_1 */
672         { 21023, 0x3B40 },   /* R21023 - VSS_XTD6_0 */
673         { 21024, 0x00F5 },   /* R21024 - VSS_XTD7_1 */
674         { 21025, 0xFB00 },   /* R21025 - VSS_XTD7_0 */
675         { 21026, 0x00EA },   /* R21026 - VSS_XTD8_1 */
676         { 21027, 0x10C0 },   /* R21027 - VSS_XTD8_0 */
677         { 21028, 0x00FC },   /* R21028 - VSS_XTD9_1 */
678         { 21029, 0xC580 },   /* R21029 - VSS_XTD9_0 */
679         { 21030, 0x00E2 },   /* R21030 - VSS_XTD10_1 */
680         { 21031, 0x75C0 },   /* R21031 - VSS_XTD10_0 */
681         { 21032, 0x0004 },   /* R21032 - VSS_XTD11_1 */
682         { 21033, 0xB480 },   /* R21033 - VSS_XTD11_0 */
683         { 21034, 0x00D4 },   /* R21034 - VSS_XTD12_1 */
684         { 21035, 0xF980 },   /* R21035 - VSS_XTD12_0 */
685         { 21036, 0x0004 },   /* R21036 - VSS_XTD13_1 */
686         { 21037, 0x9140 },   /* R21037 - VSS_XTD13_0 */
687         { 21038, 0x00D8 },   /* R21038 - VSS_XTD14_1 */
688         { 21039, 0xA480 },   /* R21039 - VSS_XTD14_0 */
689         { 21040, 0x0002 },   /* R21040 - VSS_XTD15_1 */
690         { 21041, 0x3DC0 },   /* R21041 - VSS_XTD15_0 */
691         { 21042, 0x00CF },   /* R21042 - VSS_XTD16_1 */
692         { 21043, 0x7A80 },   /* R21043 - VSS_XTD16_0 */
693         { 21044, 0x00DC },   /* R21044 - VSS_XTD17_1 */
694         { 21045, 0x0600 },   /* R21045 - VSS_XTD17_0 */
695         { 21046, 0x00F2 },   /* R21046 - VSS_XTD18_1 */
696         { 21047, 0xDAC0 },   /* R21047 - VSS_XTD18_0 */
697         { 21048, 0x00BA },   /* R21048 - VSS_XTD19_1 */
698         { 21049, 0xF340 },   /* R21049 - VSS_XTD19_0 */
699         { 21050, 0x000A },   /* R21050 - VSS_XTD20_1 */
700         { 21051, 0x7940 },   /* R21051 - VSS_XTD20_0 */
701         { 21052, 0x001C },   /* R21052 - VSS_XTD21_1 */
702         { 21053, 0x0680 },   /* R21053 - VSS_XTD21_0 */
703         { 21054, 0x00FD },   /* R21054 - VSS_XTD22_1 */
704         { 21055, 0x2D00 },   /* R21055 - VSS_XTD22_0 */
705         { 21056, 0x001C },   /* R21056 - VSS_XTD23_1 */
706         { 21057, 0xE840 },   /* R21057 - VSS_XTD23_0 */
707         { 21058, 0x000D },   /* R21058 - VSS_XTD24_1 */
708         { 21059, 0xDC40 },   /* R21059 - VSS_XTD24_0 */
709         { 21060, 0x00FC },   /* R21060 - VSS_XTD25_1 */
710         { 21061, 0x9D00 },   /* R21061 - VSS_XTD25_0 */
711         { 21062, 0x0009 },   /* R21062 - VSS_XTD26_1 */
712         { 21063, 0x5580 },   /* R21063 - VSS_XTD26_0 */
713         { 21064, 0x00FE },   /* R21064 - VSS_XTD27_1 */
714         { 21065, 0x7E80 },   /* R21065 - VSS_XTD27_0 */
715         { 21066, 0x000E },   /* R21066 - VSS_XTD28_1 */
716         { 21067, 0xAB40 },   /* R21067 - VSS_XTD28_0 */
717         { 21068, 0x00F9 },   /* R21068 - VSS_XTD29_1 */
718         { 21069, 0x9880 },   /* R21069 - VSS_XTD29_0 */
719         { 21070, 0x0009 },   /* R21070 - VSS_XTD30_1 */
720         { 21071, 0x87C0 },   /* R21071 - VSS_XTD30_0 */
721         { 21072, 0x00FD },   /* R21072 - VSS_XTD31_1 */
722         { 21073, 0x2C40 },   /* R21073 - VSS_XTD31_0 */
723         { 21074, 0x0009 },   /* R21074 - VSS_XTD32_1 */
724         { 21075, 0x4800 },   /* R21075 - VSS_XTD32_0 */
725         { 21076, 0x0003 },   /* R21076 - VSS_XTS1_1 */
726         { 21077, 0x5F40 },   /* R21077 - VSS_XTS1_0 */
727         { 21078, 0x0000 },   /* R21078 - VSS_XTS2_1 */
728         { 21079, 0x8700 },   /* R21079 - VSS_XTS2_0 */
729         { 21080, 0x00FA },   /* R21080 - VSS_XTS3_1 */
730         { 21081, 0xE4C0 },   /* R21081 - VSS_XTS3_0 */
731         { 21082, 0x0000 },   /* R21082 - VSS_XTS4_1 */
732         { 21083, 0x0B40 },   /* R21083 - VSS_XTS4_0 */
733         { 21084, 0x0004 },   /* R21084 - VSS_XTS5_1 */
734         { 21085, 0xE180 },   /* R21085 - VSS_XTS5_0 */
735         { 21086, 0x0001 },   /* R21086 - VSS_XTS6_1 */
736         { 21087, 0x1F40 },   /* R21087 - VSS_XTS6_0 */
737         { 21088, 0x00F8 },   /* R21088 - VSS_XTS7_1 */
738         { 21089, 0xB000 },   /* R21089 - VSS_XTS7_0 */
739         { 21090, 0x00FB },   /* R21090 - VSS_XTS8_1 */
740         { 21091, 0xCBC0 },   /* R21091 - VSS_XTS8_0 */
741         { 21092, 0x0004 },   /* R21092 - VSS_XTS9_1 */
742         { 21093, 0xF380 },   /* R21093 - VSS_XTS9_0 */
743         { 21094, 0x0007 },   /* R21094 - VSS_XTS10_1 */
744         { 21095, 0xDF40 },   /* R21095 - VSS_XTS10_0 */
745         { 21096, 0x00FF },   /* R21096 - VSS_XTS11_1 */
746         { 21097, 0x0700 },   /* R21097 - VSS_XTS11_0 */
747         { 21098, 0x00EF },   /* R21098 - VSS_XTS12_1 */
748         { 21099, 0xD700 },   /* R21099 - VSS_XTS12_0 */
749         { 21100, 0x00FB },   /* R21100 - VSS_XTS13_1 */
750         { 21101, 0xAF40 },   /* R21101 - VSS_XTS13_0 */
751         { 21102, 0x0010 },   /* R21102 - VSS_XTS14_1 */
752         { 21103, 0x8A80 },   /* R21103 - VSS_XTS14_0 */
753         { 21104, 0x0011 },   /* R21104 - VSS_XTS15_1 */
754         { 21105, 0x07C0 },   /* R21105 - VSS_XTS15_0 */
755         { 21106, 0x00E0 },   /* R21106 - VSS_XTS16_1 */
756         { 21107, 0x0800 },   /* R21107 - VSS_XTS16_0 */
757         { 21108, 0x00D2 },   /* R21108 - VSS_XTS17_1 */
758         { 21109, 0x7600 },   /* R21109 - VSS_XTS17_0 */
759         { 21110, 0x0020 },   /* R21110 - VSS_XTS18_1 */
760         { 21111, 0xCF40 },   /* R21111 - VSS_XTS18_0 */
761         { 21112, 0x0030 },   /* R21112 - VSS_XTS19_1 */
762         { 21113, 0x2340 },   /* R21113 - VSS_XTS19_0 */
763         { 21114, 0x00FD },   /* R21114 - VSS_XTS20_1 */
764         { 21115, 0x69C0 },   /* R21115 - VSS_XTS20_0 */
765         { 21116, 0x0028 },   /* R21116 - VSS_XTS21_1 */
766         { 21117, 0x3500 },   /* R21117 - VSS_XTS21_0 */
767         { 21118, 0x0006 },   /* R21118 - VSS_XTS22_1 */
768         { 21119, 0x3300 },   /* R21119 - VSS_XTS22_0 */
769         { 21120, 0x00D9 },   /* R21120 - VSS_XTS23_1 */
770         { 21121, 0xF6C0 },   /* R21121 - VSS_XTS23_0 */
771         { 21122, 0x00F3 },   /* R21122 - VSS_XTS24_1 */
772         { 21123, 0x3340 },   /* R21123 - VSS_XTS24_0 */
773         { 21124, 0x000F },   /* R21124 - VSS_XTS25_1 */
774         { 21125, 0x4200 },   /* R21125 - VSS_XTS25_0 */
775         { 21126, 0x0004 },   /* R21126 - VSS_XTS26_1 */
776         { 21127, 0x0C80 },   /* R21127 - VSS_XTS26_0 */
777         { 21128, 0x00FB },   /* R21128 - VSS_XTS27_1 */
778         { 21129, 0x3F80 },   /* R21129 - VSS_XTS27_0 */
779         { 21130, 0x00F7 },   /* R21130 - VSS_XTS28_1 */
780         { 21131, 0x57C0 },   /* R21131 - VSS_XTS28_0 */
781         { 21132, 0x0003 },   /* R21132 - VSS_XTS29_1 */
782         { 21133, 0x5400 },   /* R21133 - VSS_XTS29_0 */
783         { 21134, 0x0000 },   /* R21134 - VSS_XTS30_1 */
784         { 21135, 0xC6C0 },   /* R21135 - VSS_XTS30_0 */
785         { 21136, 0x0003 },   /* R21136 - VSS_XTS31_1 */
786         { 21137, 0x12C0 },   /* R21137 - VSS_XTS31_0 */
787         { 21138, 0x00FD },   /* R21138 - VSS_XTS32_1 */
788         { 21139, 0x8580 },   /* R21139 - VSS_XTS32_0 */
789 };
790 
791 static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
792 {
793         switch (reg) {
794         case WM8962_CLOCKING1:
795         case WM8962_CLOCKING2:
796         case WM8962_SOFTWARE_RESET:
797         case WM8962_ALC2:
798         case WM8962_THERMAL_SHUTDOWN_STATUS:
799         case WM8962_ADDITIONAL_CONTROL_4:
800         case WM8962_DC_SERVO_6:
801         case WM8962_INTERRUPT_STATUS_1:
802         case WM8962_INTERRUPT_STATUS_2:
803         case WM8962_DSP2_EXECCONTROL:
804                 return true;
805         default:
806                 return false;
807         }
808 }
809 
810 static bool wm8962_readable_register(struct device *dev, unsigned int reg)
811 {
812         switch (reg) {
813         case WM8962_LEFT_INPUT_VOLUME:
814         case WM8962_RIGHT_INPUT_VOLUME:
815         case WM8962_HPOUTL_VOLUME:
816         case WM8962_HPOUTR_VOLUME:
817         case WM8962_CLOCKING1:
818         case WM8962_ADC_DAC_CONTROL_1:
819         case WM8962_ADC_DAC_CONTROL_2:
820         case WM8962_AUDIO_INTERFACE_0:
821         case WM8962_CLOCKING2:
822         case WM8962_AUDIO_INTERFACE_1:
823         case WM8962_LEFT_DAC_VOLUME:
824         case WM8962_RIGHT_DAC_VOLUME:
825         case WM8962_AUDIO_INTERFACE_2:
826         case WM8962_SOFTWARE_RESET:
827         case WM8962_ALC1:
828         case WM8962_ALC2:
829         case WM8962_ALC3:
830         case WM8962_NOISE_GATE:
831         case WM8962_LEFT_ADC_VOLUME:
832         case WM8962_RIGHT_ADC_VOLUME:
833         case WM8962_ADDITIONAL_CONTROL_1:
834         case WM8962_ADDITIONAL_CONTROL_2:
835         case WM8962_PWR_MGMT_1:
836         case WM8962_PWR_MGMT_2:
837         case WM8962_ADDITIONAL_CONTROL_3:
838         case WM8962_ANTI_POP:
839         case WM8962_CLOCKING_3:
840         case WM8962_INPUT_MIXER_CONTROL_1:
841         case WM8962_LEFT_INPUT_MIXER_VOLUME:
842         case WM8962_RIGHT_INPUT_MIXER_VOLUME:
843         case WM8962_INPUT_MIXER_CONTROL_2:
844         case WM8962_INPUT_BIAS_CONTROL:
845         case WM8962_LEFT_INPUT_PGA_CONTROL:
846         case WM8962_RIGHT_INPUT_PGA_CONTROL:
847         case WM8962_SPKOUTL_VOLUME:
848         case WM8962_SPKOUTR_VOLUME:
849         case WM8962_THERMAL_SHUTDOWN_STATUS:
850         case WM8962_ADDITIONAL_CONTROL_4:
851         case WM8962_CLASS_D_CONTROL_1:
852         case WM8962_CLASS_D_CONTROL_2:
853         case WM8962_CLOCKING_4:
854         case WM8962_DAC_DSP_MIXING_1:
855         case WM8962_DAC_DSP_MIXING_2:
856         case WM8962_DC_SERVO_0:
857         case WM8962_DC_SERVO_1:
858         case WM8962_DC_SERVO_4:
859         case WM8962_DC_SERVO_6:
860         case WM8962_ANALOGUE_PGA_BIAS:
861         case WM8962_ANALOGUE_HP_0:
862         case WM8962_ANALOGUE_HP_2:
863         case WM8962_CHARGE_PUMP_1:
864         case WM8962_CHARGE_PUMP_B:
865         case WM8962_WRITE_SEQUENCER_CONTROL_1:
866         case WM8962_WRITE_SEQUENCER_CONTROL_2:
867         case WM8962_WRITE_SEQUENCER_CONTROL_3:
868         case WM8962_CONTROL_INTERFACE:
869         case WM8962_MIXER_ENABLES:
870         case WM8962_HEADPHONE_MIXER_1:
871         case WM8962_HEADPHONE_MIXER_2:
872         case WM8962_HEADPHONE_MIXER_3:
873         case WM8962_HEADPHONE_MIXER_4:
874         case WM8962_SPEAKER_MIXER_1:
875         case WM8962_SPEAKER_MIXER_2:
876         case WM8962_SPEAKER_MIXER_3:
877         case WM8962_SPEAKER_MIXER_4:
878         case WM8962_SPEAKER_MIXER_5:
879         case WM8962_BEEP_GENERATOR_1:
880         case WM8962_OSCILLATOR_TRIM_3:
881         case WM8962_OSCILLATOR_TRIM_4:
882         case WM8962_OSCILLATOR_TRIM_7:
883         case WM8962_ANALOGUE_CLOCKING1:
884         case WM8962_ANALOGUE_CLOCKING2:
885         case WM8962_ANALOGUE_CLOCKING3:
886         case WM8962_PLL_SOFTWARE_RESET:
887         case WM8962_PLL2:
888         case WM8962_PLL_4:
889         case WM8962_PLL_9:
890         case WM8962_PLL_10:
891         case WM8962_PLL_11:
892         case WM8962_PLL_12:
893         case WM8962_PLL_13:
894         case WM8962_PLL_14:
895         case WM8962_PLL_15:
896         case WM8962_PLL_16:
897         case WM8962_FLL_CONTROL_1:
898         case WM8962_FLL_CONTROL_2:
899         case WM8962_FLL_CONTROL_3:
900         case WM8962_FLL_CONTROL_5:
901         case WM8962_FLL_CONTROL_6:
902         case WM8962_FLL_CONTROL_7:
903         case WM8962_FLL_CONTROL_8:
904         case WM8962_GENERAL_TEST_1:
905         case WM8962_DF1:
906         case WM8962_DF2:
907         case WM8962_DF3:
908         case WM8962_DF4:
909         case WM8962_DF5:
910         case WM8962_DF6:
911         case WM8962_DF7:
912         case WM8962_LHPF1:
913         case WM8962_LHPF2:
914         case WM8962_THREED1:
915         case WM8962_THREED2:
916         case WM8962_THREED3:
917         case WM8962_THREED4:
918         case WM8962_DRC_1:
919         case WM8962_DRC_2:
920         case WM8962_DRC_3:
921         case WM8962_DRC_4:
922         case WM8962_DRC_5:
923         case WM8962_TLOOPBACK:
924         case WM8962_EQ1:
925         case WM8962_EQ2:
926         case WM8962_EQ3:
927         case WM8962_EQ4:
928         case WM8962_EQ5:
929         case WM8962_EQ6:
930         case WM8962_EQ7:
931         case WM8962_EQ8:
932         case WM8962_EQ9:
933         case WM8962_EQ10:
934         case WM8962_EQ11:
935         case WM8962_EQ12:
936         case WM8962_EQ13:
937         case WM8962_EQ14:
938         case WM8962_EQ15:
939         case WM8962_EQ16:
940         case WM8962_EQ17:
941         case WM8962_EQ18:
942         case WM8962_EQ19:
943         case WM8962_EQ20:
944         case WM8962_EQ21:
945         case WM8962_EQ22:
946         case WM8962_EQ23:
947         case WM8962_EQ24:
948         case WM8962_EQ25:
949         case WM8962_EQ26:
950         case WM8962_EQ27:
951         case WM8962_EQ28:
952         case WM8962_EQ29:
953         case WM8962_EQ30:
954         case WM8962_EQ31:
955         case WM8962_EQ32:
956         case WM8962_EQ33:
957         case WM8962_EQ34:
958         case WM8962_EQ35:
959         case WM8962_EQ36:
960         case WM8962_EQ37:
961         case WM8962_EQ38:
962         case WM8962_EQ39:
963         case WM8962_EQ40:
964         case WM8962_EQ41:
965         case WM8962_GPIO_BASE:
966         case WM8962_GPIO_2:
967         case WM8962_GPIO_3:
968         case WM8962_GPIO_5:
969         case WM8962_GPIO_6:
970         case WM8962_INTERRUPT_STATUS_1:
971         case WM8962_INTERRUPT_STATUS_2:
972         case WM8962_INTERRUPT_STATUS_1_MASK:
973         case WM8962_INTERRUPT_STATUS_2_MASK:
974         case WM8962_INTERRUPT_CONTROL:
975         case WM8962_IRQ_DEBOUNCE:
976         case WM8962_MICINT_SOURCE_POL:
977         case WM8962_DSP2_POWER_MANAGEMENT:
978         case WM8962_DSP2_EXECCONTROL:
979         case WM8962_DSP2_INSTRUCTION_RAM_0:
980         case WM8962_DSP2_ADDRESS_RAM_2:
981         case WM8962_DSP2_ADDRESS_RAM_1:
982         case WM8962_DSP2_ADDRESS_RAM_0:
983         case WM8962_DSP2_DATA1_RAM_1:
984         case WM8962_DSP2_DATA1_RAM_0:
985         case WM8962_DSP2_DATA2_RAM_1:
986         case WM8962_DSP2_DATA2_RAM_0:
987         case WM8962_DSP2_DATA3_RAM_1:
988         case WM8962_DSP2_DATA3_RAM_0:
989         case WM8962_DSP2_COEFF_RAM_0:
990         case WM8962_RETUNEADC_SHARED_COEFF_1:
991         case WM8962_RETUNEADC_SHARED_COEFF_0:
992         case WM8962_RETUNEDAC_SHARED_COEFF_1:
993         case WM8962_RETUNEDAC_SHARED_COEFF_0:
994         case WM8962_SOUNDSTAGE_ENABLES_1:
995         case WM8962_SOUNDSTAGE_ENABLES_0:
996         case WM8962_HDBASS_AI_1:
997         case WM8962_HDBASS_AI_0:
998         case WM8962_HDBASS_AR_1:
999         case WM8962_HDBASS_AR_0:
1000         case WM8962_HDBASS_B_1:
1001         case WM8962_HDBASS_B_0:
1002         case WM8962_HDBASS_K_1:
1003         case WM8962_HDBASS_K_0:
1004         case WM8962_HDBASS_N1_1:
1005         case WM8962_HDBASS_N1_0:
1006         case WM8962_HDBASS_N2_1:
1007         case WM8962_HDBASS_N2_0:
1008         case WM8962_HDBASS_N3_1:
1009         case WM8962_HDBASS_N3_0:
1010         case WM8962_HDBASS_N4_1:
1011         case WM8962_HDBASS_N4_0:
1012         case WM8962_HDBASS_N5_1:
1013         case WM8962_HDBASS_N5_0:
1014         case WM8962_HDBASS_X1_1:
1015         case WM8962_HDBASS_X1_0:
1016         case WM8962_HDBASS_X2_1:
1017         case WM8962_HDBASS_X2_0:
1018         case WM8962_HDBASS_X3_1:
1019         case WM8962_HDBASS_X3_0:
1020         case WM8962_HDBASS_ATK_1:
1021         case WM8962_HDBASS_ATK_0:
1022         case WM8962_HDBASS_DCY_1:
1023         case WM8962_HDBASS_DCY_0:
1024         case WM8962_HDBASS_PG_1:
1025         case WM8962_HDBASS_PG_0:
1026         case WM8962_HPF_C_1:
1027         case WM8962_HPF_C_0:
1028         case WM8962_ADCL_RETUNE_C1_1:
1029         case WM8962_ADCL_RETUNE_C1_0:
1030         case WM8962_ADCL_RETUNE_C2_1:
1031         case WM8962_ADCL_RETUNE_C2_0:
1032         case WM8962_ADCL_RETUNE_C3_1:
1033         case WM8962_ADCL_RETUNE_C3_0:
1034         case WM8962_ADCL_RETUNE_C4_1:
1035         case WM8962_ADCL_RETUNE_C4_0:
1036         case WM8962_ADCL_RETUNE_C5_1:
1037         case WM8962_ADCL_RETUNE_C5_0:
1038         case WM8962_ADCL_RETUNE_C6_1:
1039         case WM8962_ADCL_RETUNE_C6_0:
1040         case WM8962_ADCL_RETUNE_C7_1:
1041         case WM8962_ADCL_RETUNE_C7_0:
1042         case WM8962_ADCL_RETUNE_C8_1:
1043         case WM8962_ADCL_RETUNE_C8_0:
1044         case WM8962_ADCL_RETUNE_C9_1:
1045         case WM8962_ADCL_RETUNE_C9_0:
1046         case WM8962_ADCL_RETUNE_C10_1:
1047         case WM8962_ADCL_RETUNE_C10_0:
1048         case WM8962_ADCL_RETUNE_C11_1:
1049         case WM8962_ADCL_RETUNE_C11_0:
1050         case WM8962_ADCL_RETUNE_C12_1:
1051         case WM8962_ADCL_RETUNE_C12_0:
1052         case WM8962_ADCL_RETUNE_C13_1:
1053         case WM8962_ADCL_RETUNE_C13_0:
1054         case WM8962_ADCL_RETUNE_C14_1:
1055         case WM8962_ADCL_RETUNE_C14_0:
1056         case WM8962_ADCL_RETUNE_C15_1:
1057         case WM8962_ADCL_RETUNE_C15_0:
1058         case WM8962_ADCL_RETUNE_C16_1:
1059         case WM8962_ADCL_RETUNE_C16_0:
1060         case WM8962_ADCL_RETUNE_C17_1:
1061         case WM8962_ADCL_RETUNE_C17_0:
1062         case WM8962_ADCL_RETUNE_C18_1:
1063         case WM8962_ADCL_RETUNE_C18_0:
1064         case WM8962_ADCL_RETUNE_C19_1:
1065         case WM8962_ADCL_RETUNE_C19_0:
1066         case WM8962_ADCL_RETUNE_C20_1:
1067         case WM8962_ADCL_RETUNE_C20_0:
1068         case WM8962_ADCL_RETUNE_C21_1:
1069         case WM8962_ADCL_RETUNE_C21_0:
1070         case WM8962_ADCL_RETUNE_C22_1:
1071         case WM8962_ADCL_RETUNE_C22_0:
1072         case WM8962_ADCL_RETUNE_C23_1:
1073         case WM8962_ADCL_RETUNE_C23_0:
1074         case WM8962_ADCL_RETUNE_C24_1:
1075         case WM8962_ADCL_RETUNE_C24_0:
1076         case WM8962_ADCL_RETUNE_C25_1:
1077         case WM8962_ADCL_RETUNE_C25_0:
1078         case WM8962_ADCL_RETUNE_C26_1:
1079         case WM8962_ADCL_RETUNE_C26_0:
1080         case WM8962_ADCL_RETUNE_C27_1:
1081         case WM8962_ADCL_RETUNE_C27_0:
1082         case WM8962_ADCL_RETUNE_C28_1:
1083         case WM8962_ADCL_RETUNE_C28_0:
1084         case WM8962_ADCL_RETUNE_C29_1:
1085         case WM8962_ADCL_RETUNE_C29_0:
1086         case WM8962_ADCL_RETUNE_C30_1:
1087         case WM8962_ADCL_RETUNE_C30_0:
1088         case WM8962_ADCL_RETUNE_C31_1:
1089         case WM8962_ADCL_RETUNE_C31_0:
1090         case WM8962_ADCL_RETUNE_C32_1:
1091         case WM8962_ADCL_RETUNE_C32_0:
1092         case WM8962_RETUNEADC_PG2_1:
1093         case WM8962_RETUNEADC_PG2_0:
1094         case WM8962_RETUNEADC_PG_1:
1095         case WM8962_RETUNEADC_PG_0:
1096         case WM8962_ADCR_RETUNE_C1_1:
1097         case WM8962_ADCR_RETUNE_C1_0:
1098         case WM8962_ADCR_RETUNE_C2_1:
1099         case WM8962_ADCR_RETUNE_C2_0:
1100         case WM8962_ADCR_RETUNE_C3_1:
1101         case WM8962_ADCR_RETUNE_C3_0:
1102         case WM8962_ADCR_RETUNE_C4_1:
1103         case WM8962_ADCR_RETUNE_C4_0:
1104         case WM8962_ADCR_RETUNE_C5_1:
1105         case WM8962_ADCR_RETUNE_C5_0:
1106         case WM8962_ADCR_RETUNE_C6_1:
1107         case WM8962_ADCR_RETUNE_C6_0:
1108         case WM8962_ADCR_RETUNE_C7_1:
1109         case WM8962_ADCR_RETUNE_C7_0:
1110         case WM8962_ADCR_RETUNE_C8_1:
1111         case WM8962_ADCR_RETUNE_C8_0:
1112         case WM8962_ADCR_RETUNE_C9_1:
1113         case WM8962_ADCR_RETUNE_C9_0:
1114         case WM8962_ADCR_RETUNE_C10_1:
1115         case WM8962_ADCR_RETUNE_C10_0:
1116         case WM8962_ADCR_RETUNE_C11_1:
1117         case WM8962_ADCR_RETUNE_C11_0:
1118         case WM8962_ADCR_RETUNE_C12_1:
1119         case WM8962_ADCR_RETUNE_C12_0:
1120         case WM8962_ADCR_RETUNE_C13_1:
1121         case WM8962_ADCR_RETUNE_C13_0:
1122         case WM8962_ADCR_RETUNE_C14_1:
1123         case WM8962_ADCR_RETUNE_C14_0:
1124         case WM8962_ADCR_RETUNE_C15_1:
1125         case WM8962_ADCR_RETUNE_C15_0:
1126         case WM8962_ADCR_RETUNE_C16_1:
1127         case WM8962_ADCR_RETUNE_C16_0:
1128         case WM8962_ADCR_RETUNE_C17_1:
1129         case WM8962_ADCR_RETUNE_C17_0:
1130         case WM8962_ADCR_RETUNE_C18_1:
1131         case WM8962_ADCR_RETUNE_C18_0:
1132         case WM8962_ADCR_RETUNE_C19_1:
1133         case WM8962_ADCR_RETUNE_C19_0:
1134         case WM8962_ADCR_RETUNE_C20_1:
1135         case WM8962_ADCR_RETUNE_C20_0:
1136         case WM8962_ADCR_RETUNE_C21_1:
1137         case WM8962_ADCR_RETUNE_C21_0:
1138         case WM8962_ADCR_RETUNE_C22_1:
1139         case WM8962_ADCR_RETUNE_C22_0:
1140         case WM8962_ADCR_RETUNE_C23_1:
1141         case WM8962_ADCR_RETUNE_C23_0:
1142         case WM8962_ADCR_RETUNE_C24_1:
1143         case WM8962_ADCR_RETUNE_C24_0:
1144         case WM8962_ADCR_RETUNE_C25_1:
1145         case WM8962_ADCR_RETUNE_C25_0:
1146         case WM8962_ADCR_RETUNE_C26_1:
1147         case WM8962_ADCR_RETUNE_C26_0:
1148         case WM8962_ADCR_RETUNE_C27_1:
1149         case WM8962_ADCR_RETUNE_C27_0:
1150         case WM8962_ADCR_RETUNE_C28_1:
1151         case WM8962_ADCR_RETUNE_C28_0:
1152         case WM8962_ADCR_RETUNE_C29_1:
1153         case WM8962_ADCR_RETUNE_C29_0:
1154         case WM8962_ADCR_RETUNE_C30_1:
1155         case WM8962_ADCR_RETUNE_C30_0:
1156         case WM8962_ADCR_RETUNE_C31_1:
1157         case WM8962_ADCR_RETUNE_C31_0:
1158         case WM8962_ADCR_RETUNE_C32_1:
1159         case WM8962_ADCR_RETUNE_C32_0:
1160         case WM8962_DACL_RETUNE_C1_1:
1161         case WM8962_DACL_RETUNE_C1_0:
1162         case WM8962_DACL_RETUNE_C2_1:
1163         case WM8962_DACL_RETUNE_C2_0:
1164         case WM8962_DACL_RETUNE_C3_1:
1165         case WM8962_DACL_RETUNE_C3_0:
1166         case WM8962_DACL_RETUNE_C4_1:
1167         case WM8962_DACL_RETUNE_C4_0:
1168         case WM8962_DACL_RETUNE_C5_1:
1169         case WM8962_DACL_RETUNE_C5_0:
1170         case WM8962_DACL_RETUNE_C6_1:
1171         case WM8962_DACL_RETUNE_C6_0:
1172         case WM8962_DACL_RETUNE_C7_1:
1173         case WM8962_DACL_RETUNE_C7_0:
1174         case WM8962_DACL_RETUNE_C8_1:
1175         case WM8962_DACL_RETUNE_C8_0:
1176         case WM8962_DACL_RETUNE_C9_1:
1177         case WM8962_DACL_RETUNE_C9_0:
1178         case WM8962_DACL_RETUNE_C10_1:
1179         case WM8962_DACL_RETUNE_C10_0:
1180         case WM8962_DACL_RETUNE_C11_1:
1181         case WM8962_DACL_RETUNE_C11_0:
1182         case WM8962_DACL_RETUNE_C12_1:
1183         case WM8962_DACL_RETUNE_C12_0:
1184         case WM8962_DACL_RETUNE_C13_1:
1185         case WM8962_DACL_RETUNE_C13_0:
1186         case WM8962_DACL_RETUNE_C14_1:
1187         case WM8962_DACL_RETUNE_C14_0:
1188         case WM8962_DACL_RETUNE_C15_1:
1189         case WM8962_DACL_RETUNE_C15_0:
1190         case WM8962_DACL_RETUNE_C16_1:
1191         case WM8962_DACL_RETUNE_C16_0:
1192         case WM8962_DACL_RETUNE_C17_1:
1193         case WM8962_DACL_RETUNE_C17_0:
1194         case WM8962_DACL_RETUNE_C18_1:
1195         case WM8962_DACL_RETUNE_C18_0:
1196         case WM8962_DACL_RETUNE_C19_1:
1197         case WM8962_DACL_RETUNE_C19_0:
1198         case WM8962_DACL_RETUNE_C20_1:
1199         case WM8962_DACL_RETUNE_C20_0:
1200         case WM8962_DACL_RETUNE_C21_1:
1201         case WM8962_DACL_RETUNE_C21_0:
1202         case WM8962_DACL_RETUNE_C22_1:
1203         case WM8962_DACL_RETUNE_C22_0:
1204         case WM8962_DACL_RETUNE_C23_1:
1205         case WM8962_DACL_RETUNE_C23_0:
1206         case WM8962_DACL_RETUNE_C24_1:
1207         case WM8962_DACL_RETUNE_C24_0:
1208         case WM8962_DACL_RETUNE_C25_1:
1209         case WM8962_DACL_RETUNE_C25_0:
1210         case WM8962_DACL_RETUNE_C26_1:
1211         case WM8962_DACL_RETUNE_C26_0:
1212         case WM8962_DACL_RETUNE_C27_1:
1213         case WM8962_DACL_RETUNE_C27_0:
1214         case WM8962_DACL_RETUNE_C28_1:
1215         case WM8962_DACL_RETUNE_C28_0:
1216         case WM8962_DACL_RETUNE_C29_1:
1217         case WM8962_DACL_RETUNE_C29_0:
1218         case WM8962_DACL_RETUNE_C30_1:
1219         case WM8962_DACL_RETUNE_C30_0:
1220         case WM8962_DACL_RETUNE_C31_1:
1221         case WM8962_DACL_RETUNE_C31_0:
1222         case WM8962_DACL_RETUNE_C32_1:
1223         case WM8962_DACL_RETUNE_C32_0:
1224         case WM8962_RETUNEDAC_PG2_1:
1225         case WM8962_RETUNEDAC_PG2_0:
1226         case WM8962_RETUNEDAC_PG_1:
1227         case WM8962_RETUNEDAC_PG_0:
1228         case WM8962_DACR_RETUNE_C1_1:
1229         case WM8962_DACR_RETUNE_C1_0:
1230         case WM8962_DACR_RETUNE_C2_1:
1231         case WM8962_DACR_RETUNE_C2_0:
1232         case WM8962_DACR_RETUNE_C3_1:
1233         case WM8962_DACR_RETUNE_C3_0:
1234         case WM8962_DACR_RETUNE_C4_1:
1235         case WM8962_DACR_RETUNE_C4_0:
1236         case WM8962_DACR_RETUNE_C5_1:
1237         case WM8962_DACR_RETUNE_C5_0:
1238         case WM8962_DACR_RETUNE_C6_1:
1239         case WM8962_DACR_RETUNE_C6_0:
1240         case WM8962_DACR_RETUNE_C7_1:
1241         case WM8962_DACR_RETUNE_C7_0:
1242         case WM8962_DACR_RETUNE_C8_1:
1243         case WM8962_DACR_RETUNE_C8_0:
1244         case WM8962_DACR_RETUNE_C9_1:
1245         case WM8962_DACR_RETUNE_C9_0:
1246         case WM8962_DACR_RETUNE_C10_1:
1247         case WM8962_DACR_RETUNE_C10_0:
1248         case WM8962_DACR_RETUNE_C11_1:
1249         case WM8962_DACR_RETUNE_C11_0:
1250         case WM8962_DACR_RETUNE_C12_1:
1251         case WM8962_DACR_RETUNE_C12_0:
1252         case WM8962_DACR_RETUNE_C13_1:
1253         case WM8962_DACR_RETUNE_C13_0:
1254         case WM8962_DACR_RETUNE_C14_1:
1255         case WM8962_DACR_RETUNE_C14_0:
1256         case WM8962_DACR_RETUNE_C15_1:
1257         case WM8962_DACR_RETUNE_C15_0:
1258         case WM8962_DACR_RETUNE_C16_1:
1259         case WM8962_DACR_RETUNE_C16_0:
1260         case WM8962_DACR_RETUNE_C17_1:
1261         case WM8962_DACR_RETUNE_C17_0:
1262         case WM8962_DACR_RETUNE_C18_1:
1263         case WM8962_DACR_RETUNE_C18_0:
1264         case WM8962_DACR_RETUNE_C19_1:
1265         case WM8962_DACR_RETUNE_C19_0:
1266         case WM8962_DACR_RETUNE_C20_1:
1267         case WM8962_DACR_RETUNE_C20_0:
1268         case WM8962_DACR_RETUNE_C21_1:
1269         case WM8962_DACR_RETUNE_C21_0:
1270         case WM8962_DACR_RETUNE_C22_1:
1271         case WM8962_DACR_RETUNE_C22_0:
1272         case WM8962_DACR_RETUNE_C23_1:
1273         case WM8962_DACR_RETUNE_C23_0:
1274         case WM8962_DACR_RETUNE_C24_1:
1275         case WM8962_DACR_RETUNE_C24_0:
1276         case WM8962_DACR_RETUNE_C25_1:
1277         case WM8962_DACR_RETUNE_C25_0:
1278         case WM8962_DACR_RETUNE_C26_1:
1279         case WM8962_DACR_RETUNE_C26_0:
1280         case WM8962_DACR_RETUNE_C27_1:
1281         case WM8962_DACR_RETUNE_C27_0:
1282         case WM8962_DACR_RETUNE_C28_1:
1283         case WM8962_DACR_RETUNE_C28_0:
1284         case WM8962_DACR_RETUNE_C29_1:
1285         case WM8962_DACR_RETUNE_C29_0:
1286         case WM8962_DACR_RETUNE_C30_1:
1287         case WM8962_DACR_RETUNE_C30_0:
1288         case WM8962_DACR_RETUNE_C31_1:
1289         case WM8962_DACR_RETUNE_C31_0:
1290         case WM8962_DACR_RETUNE_C32_1:
1291         case WM8962_DACR_RETUNE_C32_0:
1292         case WM8962_VSS_XHD2_1:
1293         case WM8962_VSS_XHD2_0:
1294         case WM8962_VSS_XHD3_1:
1295         case WM8962_VSS_XHD3_0:
1296         case WM8962_VSS_XHN1_1:
1297         case WM8962_VSS_XHN1_0:
1298         case WM8962_VSS_XHN2_1:
1299         case WM8962_VSS_XHN2_0:
1300         case WM8962_VSS_XHN3_1:
1301         case WM8962_VSS_XHN3_0:
1302         case WM8962_VSS_XLA_1:
1303         case WM8962_VSS_XLA_0:
1304         case WM8962_VSS_XLB_1:
1305         case WM8962_VSS_XLB_0:
1306         case WM8962_VSS_XLG_1:
1307         case WM8962_VSS_XLG_0:
1308         case WM8962_VSS_PG2_1:
1309         case WM8962_VSS_PG2_0:
1310         case WM8962_VSS_PG_1:
1311         case WM8962_VSS_PG_0:
1312         case WM8962_VSS_XTD1_1:
1313         case WM8962_VSS_XTD1_0:
1314         case WM8962_VSS_XTD2_1:
1315         case WM8962_VSS_XTD2_0:
1316         case WM8962_VSS_XTD3_1:
1317         case WM8962_VSS_XTD3_0:
1318         case WM8962_VSS_XTD4_1:
1319         case WM8962_VSS_XTD4_0:
1320         case WM8962_VSS_XTD5_1:
1321         case WM8962_VSS_XTD5_0:
1322         case WM8962_VSS_XTD6_1:
1323         case WM8962_VSS_XTD6_0:
1324         case WM8962_VSS_XTD7_1:
1325         case WM8962_VSS_XTD7_0:
1326         case WM8962_VSS_XTD8_1:
1327         case WM8962_VSS_XTD8_0:
1328         case WM8962_VSS_XTD9_1:
1329         case WM8962_VSS_XTD9_0:
1330         case WM8962_VSS_XTD10_1:
1331         case WM8962_VSS_XTD10_0:
1332         case WM8962_VSS_XTD11_1:
1333         case WM8962_VSS_XTD11_0:
1334         case WM8962_VSS_XTD12_1:
1335         case WM8962_VSS_XTD12_0:
1336         case WM8962_VSS_XTD13_1:
1337         case WM8962_VSS_XTD13_0:
1338         case WM8962_VSS_XTD14_1:
1339         case WM8962_VSS_XTD14_0:
1340         case WM8962_VSS_XTD15_1:
1341         case WM8962_VSS_XTD15_0:
1342         case WM8962_VSS_XTD16_1:
1343         case WM8962_VSS_XTD16_0:
1344         case WM8962_VSS_XTD17_1:
1345         case WM8962_VSS_XTD17_0:
1346         case WM8962_VSS_XTD18_1:
1347         case WM8962_VSS_XTD18_0:
1348         case WM8962_VSS_XTD19_1:
1349         case WM8962_VSS_XTD19_0:
1350         case WM8962_VSS_XTD20_1:
1351         case WM8962_VSS_XTD20_0:
1352         case WM8962_VSS_XTD21_1:
1353         case WM8962_VSS_XTD21_0:
1354         case WM8962_VSS_XTD22_1:
1355         case WM8962_VSS_XTD22_0:
1356         case WM8962_VSS_XTD23_1:
1357         case WM8962_VSS_XTD23_0:
1358         case WM8962_VSS_XTD24_1:
1359         case WM8962_VSS_XTD24_0:
1360         case WM8962_VSS_XTD25_1:
1361         case WM8962_VSS_XTD25_0:
1362         case WM8962_VSS_XTD26_1:
1363         case WM8962_VSS_XTD26_0:
1364         case WM8962_VSS_XTD27_1:
1365         case WM8962_VSS_XTD27_0:
1366         case WM8962_VSS_XTD28_1:
1367         case WM8962_VSS_XTD28_0:
1368         case WM8962_VSS_XTD29_1:
1369         case WM8962_VSS_XTD29_0:
1370         case WM8962_VSS_XTD30_1:
1371         case WM8962_VSS_XTD30_0:
1372         case WM8962_VSS_XTD31_1:
1373         case WM8962_VSS_XTD31_0:
1374         case WM8962_VSS_XTD32_1:
1375         case WM8962_VSS_XTD32_0:
1376         case WM8962_VSS_XTS1_1:
1377         case WM8962_VSS_XTS1_0:
1378         case WM8962_VSS_XTS2_1:
1379         case WM8962_VSS_XTS2_0:
1380         case WM8962_VSS_XTS3_1:
1381         case WM8962_VSS_XTS3_0:
1382         case WM8962_VSS_XTS4_1:
1383         case WM8962_VSS_XTS4_0:
1384         case WM8962_VSS_XTS5_1:
1385         case WM8962_VSS_XTS5_0:
1386         case WM8962_VSS_XTS6_1:
1387         case WM8962_VSS_XTS6_0:
1388         case WM8962_VSS_XTS7_1:
1389         case WM8962_VSS_XTS7_0:
1390         case WM8962_VSS_XTS8_1:
1391         case WM8962_VSS_XTS8_0:
1392         case WM8962_VSS_XTS9_1:
1393         case WM8962_VSS_XTS9_0:
1394         case WM8962_VSS_XTS10_1:
1395         case WM8962_VSS_XTS10_0:
1396         case WM8962_VSS_XTS11_1:
1397         case WM8962_VSS_XTS11_0:
1398         case WM8962_VSS_XTS12_1:
1399         case WM8962_VSS_XTS12_0:
1400         case WM8962_VSS_XTS13_1:
1401         case WM8962_VSS_XTS13_0:
1402         case WM8962_VSS_XTS14_1:
1403         case WM8962_VSS_XTS14_0:
1404         case WM8962_VSS_XTS15_1:
1405         case WM8962_VSS_XTS15_0:
1406         case WM8962_VSS_XTS16_1:
1407         case WM8962_VSS_XTS16_0:
1408         case WM8962_VSS_XTS17_1:
1409         case WM8962_VSS_XTS17_0:
1410         case WM8962_VSS_XTS18_1:
1411         case WM8962_VSS_XTS18_0:
1412         case WM8962_VSS_XTS19_1:
1413         case WM8962_VSS_XTS19_0:
1414         case WM8962_VSS_XTS20_1:
1415         case WM8962_VSS_XTS20_0:
1416         case WM8962_VSS_XTS21_1:
1417         case WM8962_VSS_XTS21_0:
1418         case WM8962_VSS_XTS22_1:
1419         case WM8962_VSS_XTS22_0:
1420         case WM8962_VSS_XTS23_1:
1421         case WM8962_VSS_XTS23_0:
1422         case WM8962_VSS_XTS24_1:
1423         case WM8962_VSS_XTS24_0:
1424         case WM8962_VSS_XTS25_1:
1425         case WM8962_VSS_XTS25_0:
1426         case WM8962_VSS_XTS26_1:
1427         case WM8962_VSS_XTS26_0:
1428         case WM8962_VSS_XTS27_1:
1429         case WM8962_VSS_XTS27_0:
1430         case WM8962_VSS_XTS28_1:
1431         case WM8962_VSS_XTS28_0:
1432         case WM8962_VSS_XTS29_1:
1433         case WM8962_VSS_XTS29_0:
1434         case WM8962_VSS_XTS30_1:
1435         case WM8962_VSS_XTS30_0:
1436         case WM8962_VSS_XTS31_1:
1437         case WM8962_VSS_XTS31_0:
1438         case WM8962_VSS_XTS32_1:
1439         case WM8962_VSS_XTS32_0:
1440                 return true;
1441         default:
1442                 return false;
1443         }
1444 }
1445 
1446 static int wm8962_reset(struct wm8962_priv *wm8962)
1447 {
1448         int ret;
1449 
1450         ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
1451         if (ret != 0)
1452                 return ret;
1453 
1454         return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
1455 }
1456 
1457 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1458 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1459 static const unsigned int mixinpga_tlv[] = {
1460         TLV_DB_RANGE_HEAD(5),
1461         0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1462         2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1463         3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1464         5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1465         6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
1466 };
1467 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1468 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1469 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1470 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1471 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1472 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1473 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1474 static const unsigned int classd_tlv[] = {
1475         TLV_DB_RANGE_HEAD(2),
1476         0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1477         7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
1478 };
1479 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1480 
1481 static int wm8962_dsp2_write_config(struct snd_soc_codec *codec)
1482 {
1483         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1484 
1485         return regcache_sync_region(wm8962->regmap,
1486                                     WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
1487 }
1488 
1489 static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val)
1490 {
1491         u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME);
1492         u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME);
1493         u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1);
1494 
1495         /* Mute the ADCs and DACs */
1496         snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0);
1497         snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1498         snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1499                             WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1500 
1501         snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val);
1502 
1503         /* Restore the ADCs and DACs */
1504         snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl);
1505         snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr);
1506         snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1507                             WM8962_DAC_MUTE, dac);
1508 
1509         return 0;
1510 }
1511 
1512 static int wm8962_dsp2_start(struct snd_soc_codec *codec)
1513 {
1514         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1515 
1516         wm8962_dsp2_write_config(codec);
1517 
1518         snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1519 
1520         wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1521 
1522         return 0;
1523 }
1524 
1525 static int wm8962_dsp2_stop(struct snd_soc_codec *codec)
1526 {
1527         wm8962_dsp2_set_enable(codec, 0);
1528 
1529         snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1530 
1531         return 0;
1532 }
1533 
1534 #define WM8962_DSP2_ENABLE(xname, xshift) \
1535 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1536         .info = wm8962_dsp2_ena_info, \
1537         .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1538         .private_value = xshift }
1539 
1540 static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1541                                 struct snd_ctl_elem_info *uinfo)
1542 {
1543         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1544 
1545         uinfo->count = 1;
1546         uinfo->value.integer.min = 0;
1547         uinfo->value.integer.max = 1;
1548 
1549         return 0;
1550 }
1551 
1552 static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1553                                struct snd_ctl_elem_value *ucontrol)
1554 {
1555         int shift = kcontrol->private_value;
1556         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1557         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1558 
1559         ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1560 
1561         return 0;
1562 }
1563 
1564 static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1565                                struct snd_ctl_elem_value *ucontrol)
1566 {
1567         int shift = kcontrol->private_value;
1568         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1569         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1570         int old = wm8962->dsp2_ena;
1571         int ret = 0;
1572         int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) &
1573                 WM8962_DSP2_ENA;
1574 
1575         mutex_lock(&wm8962->dsp2_ena_lock);
1576 
1577         if (ucontrol->value.integer.value[0])
1578                 wm8962->dsp2_ena |= 1 << shift;
1579         else
1580                 wm8962->dsp2_ena &= ~(1 << shift);
1581 
1582         if (wm8962->dsp2_ena == old)
1583                 goto out;
1584 
1585         ret = 1;
1586 
1587         if (dsp2_running) {
1588                 if (wm8962->dsp2_ena)
1589                         wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1590                 else
1591                         wm8962_dsp2_stop(codec);
1592         }
1593 
1594 out:
1595         mutex_unlock(&wm8962->dsp2_ena_lock);
1596 
1597         return ret;
1598 }
1599 
1600 /* The VU bits for the headphones are in a different register to the mute
1601  * bits and only take effect on the PGA if it is actually powered.
1602  */
1603 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1604                             struct snd_ctl_elem_value *ucontrol)
1605 {
1606         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1607         int ret;
1608 
1609         /* Apply the update (if any) */
1610         ret = snd_soc_put_volsw(kcontrol, ucontrol);
1611         if (ret == 0)
1612                 return 0;
1613 
1614         /* If the left PGA is enabled hit that VU bit... */
1615         ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1616         if (ret & WM8962_HPOUTL_PGA_ENA) {
1617                 snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
1618                               snd_soc_read(codec, WM8962_HPOUTL_VOLUME));
1619                 return 1;
1620         }
1621 
1622         /* ...otherwise the right.  The VU is stereo. */
1623         if (ret & WM8962_HPOUTR_PGA_ENA)
1624                 snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
1625                               snd_soc_read(codec, WM8962_HPOUTR_VOLUME));
1626 
1627         return 1;
1628 }
1629 
1630 /* The VU bits for the speakers are in a different register to the mute
1631  * bits and only take effect on the PGA if it is actually powered.
1632  */
1633 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1634                             struct snd_ctl_elem_value *ucontrol)
1635 {
1636         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1637         int ret;
1638 
1639         /* Apply the update (if any) */
1640         ret = snd_soc_put_volsw(kcontrol, ucontrol);
1641         if (ret == 0)
1642                 return 0;
1643 
1644         /* If the left PGA is enabled hit that VU bit... */
1645         ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1646         if (ret & WM8962_SPKOUTL_PGA_ENA) {
1647                 snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
1648                               snd_soc_read(codec, WM8962_SPKOUTL_VOLUME));
1649                 return 1;
1650         }
1651 
1652         /* ...otherwise the right.  The VU is stereo. */
1653         if (ret & WM8962_SPKOUTR_PGA_ENA)
1654                 snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
1655                               snd_soc_read(codec, WM8962_SPKOUTR_VOLUME));
1656 
1657         return 1;
1658 }
1659 
1660 static const char *cap_hpf_mode_text[] = {
1661         "Hi-fi", "Application"
1662 };
1663 
1664 static SOC_ENUM_SINGLE_DECL(cap_hpf_mode,
1665                             WM8962_ADC_DAC_CONTROL_2, 10, cap_hpf_mode_text);
1666 
1667 
1668 static const char *cap_lhpf_mode_text[] = {
1669         "LPF", "HPF"
1670 };
1671 
1672 static SOC_ENUM_SINGLE_DECL(cap_lhpf_mode,
1673                             WM8962_LHPF1, 1, cap_lhpf_mode_text);
1674 
1675 static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1676 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1677 
1678 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1679                mixin_tlv),
1680 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1681                mixinpga_tlv),
1682 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1683                mixin_tlv),
1684 
1685 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1686                mixin_tlv),
1687 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1688                mixinpga_tlv),
1689 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1690                mixin_tlv),
1691 
1692 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1693                  WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1694 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1695                  WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1696 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1697              WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1698 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1699              WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
1700 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1701 SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1702 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
1703 SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1704 SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
1705 
1706 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1707                  WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1708 
1709 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1710                  WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1711 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
1712 SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1713 SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
1714 
1715 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1716            5, 1, 0),
1717 
1718 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1719 
1720 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1721                  WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1722 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1723                snd_soc_get_volsw, wm8962_put_hp_sw),
1724 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1725              7, 1, 0),
1726 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1727                hp_tlv),
1728 
1729 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1730              WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1731 
1732 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1733                3, 7, 0, bypass_tlv),
1734 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1735                0, 7, 0, bypass_tlv),
1736 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1737                7, 1, 1, inmix_tlv),
1738 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1739                6, 1, 1, inmix_tlv),
1740 
1741 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1742                3, 7, 0, bypass_tlv),
1743 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1744                0, 7, 0, bypass_tlv),
1745 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1746                7, 1, 1, inmix_tlv),
1747 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1748                6, 1, 1, inmix_tlv),
1749 
1750 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1751                classd_tlv),
1752 
1753 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1754 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1755                  WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1756 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1757                  WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1758 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1759                  WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1760 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1761                  WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1762 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1763                  WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
1764 SND_SOC_BYTES("EQL Coefficients", WM8962_EQ4, 18),
1765 SND_SOC_BYTES("EQR Coefficients", WM8962_EQ24, 18),
1766 
1767 
1768 SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1769 SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1770 
1771 SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1772 SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1773 
1774 SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1775 SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1776 
1777 WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1778 SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
1779 WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1780 WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1781 SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
1782 WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
1783 SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
1784 
1785 SOC_DOUBLE("ALC Switch", WM8962_ALC1, WM8962_ALCL_ENA_SHIFT,
1786                 WM8962_ALCR_ENA_SHIFT, 1, 0),
1787 SND_SOC_BYTES_MASK("ALC Coefficients", WM8962_ALC1, 4,
1788                 WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK),
1789 };
1790 
1791 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1792 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1793 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1794                snd_soc_get_volsw, wm8962_put_spk_sw),
1795 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1796 
1797 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1798 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1799                3, 7, 0, bypass_tlv),
1800 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1801                0, 7, 0, bypass_tlv),
1802 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1803                7, 1, 1, inmix_tlv),
1804 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1805                6, 1, 1, inmix_tlv),
1806 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1807                7, 1, 0, inmix_tlv),
1808 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1809                6, 1, 0, inmix_tlv),
1810 };
1811 
1812 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1813 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1814                  WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1815 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1816                snd_soc_get_volsw, wm8962_put_spk_sw),
1817 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1818              7, 1, 0),
1819 
1820 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1821              WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1822 
1823 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1824                3, 7, 0, bypass_tlv),
1825 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1826                0, 7, 0, bypass_tlv),
1827 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1828                7, 1, 1, inmix_tlv),
1829 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1830                6, 1, 1, inmix_tlv),
1831 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1832                7, 1, 0, inmix_tlv),
1833 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1834                6, 1, 0, inmix_tlv),
1835 
1836 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1837                3, 7, 0, bypass_tlv),
1838 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1839                0, 7, 0, bypass_tlv),
1840 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1841                7, 1, 1, inmix_tlv),
1842 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1843                6, 1, 1, inmix_tlv),
1844 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1845                5, 1, 0, inmix_tlv),
1846 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1847                4, 1, 0, inmix_tlv),
1848 };
1849 
1850 static int cp_event(struct snd_soc_dapm_widget *w,
1851                     struct snd_kcontrol *kcontrol, int event)
1852 {
1853         switch (event) {
1854         case SND_SOC_DAPM_POST_PMU:
1855                 msleep(5);
1856                 break;
1857 
1858         default:
1859                 WARN(1, "Invalid event %d\n", event);
1860                 return -EINVAL;
1861         }
1862 
1863         return 0;
1864 }
1865 
1866 static int hp_event(struct snd_soc_dapm_widget *w,
1867                     struct snd_kcontrol *kcontrol, int event)
1868 {
1869         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1870         int timeout;
1871         int reg;
1872         int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1873                         WM8962_DCS_STARTUP_DONE_HP1R);
1874 
1875         switch (event) {
1876         case SND_SOC_DAPM_POST_PMU:
1877                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1878                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1879                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1880                 udelay(20);
1881 
1882                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1883                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1884                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1885 
1886                 /* Start the DC servo */
1887                 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1888                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1889                                     WM8962_HP1L_DCS_STARTUP |
1890                                     WM8962_HP1R_DCS_STARTUP,
1891                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1892                                     WM8962_HP1L_DCS_STARTUP |
1893                                     WM8962_HP1R_DCS_STARTUP);
1894 
1895                 /* Wait for it to complete, should be well under 100ms */
1896                 timeout = 0;
1897                 do {
1898                         msleep(1);
1899                         reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
1900                         if (reg < 0) {
1901                                 dev_err(codec->dev,
1902                                         "Failed to read DCS status: %d\n",
1903                                         reg);
1904                                 continue;
1905                         }
1906                         dev_dbg(codec->dev, "DCS status: %x\n", reg);
1907                 } while (++timeout < 200 && (reg & expected) != expected);
1908 
1909                 if ((reg & expected) != expected)
1910                         dev_err(codec->dev, "DC servo timed out\n");
1911                 else
1912                         dev_dbg(codec->dev, "DC servo complete after %dms\n",
1913                                 timeout);
1914 
1915                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1916                                     WM8962_HP1L_ENA_OUTP |
1917                                     WM8962_HP1R_ENA_OUTP,
1918                                     WM8962_HP1L_ENA_OUTP |
1919                                     WM8962_HP1R_ENA_OUTP);
1920                 udelay(20);
1921 
1922                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1923                                     WM8962_HP1L_RMV_SHORT |
1924                                     WM8962_HP1R_RMV_SHORT,
1925                                     WM8962_HP1L_RMV_SHORT |
1926                                     WM8962_HP1R_RMV_SHORT);
1927                 break;
1928 
1929         case SND_SOC_DAPM_PRE_PMD:
1930                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1931                                     WM8962_HP1L_RMV_SHORT |
1932                                     WM8962_HP1R_RMV_SHORT, 0);
1933 
1934                 udelay(20);
1935 
1936                 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1937                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1938                                     WM8962_HP1L_DCS_STARTUP |
1939                                     WM8962_HP1R_DCS_STARTUP,
1940                                     0);
1941 
1942                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1943                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1944                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1945                                     WM8962_HP1L_ENA_OUTP |
1946                                     WM8962_HP1R_ENA_OUTP, 0);
1947                                     
1948                 break;
1949 
1950         default:
1951                 WARN(1, "Invalid event %d\n", event);
1952                 return -EINVAL;
1953         
1954         }
1955 
1956         return 0;
1957 }
1958 
1959 /* VU bits for the output PGAs only take effect while the PGA is powered */
1960 static int out_pga_event(struct snd_soc_dapm_widget *w,
1961                          struct snd_kcontrol *kcontrol, int event)
1962 {
1963         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1964         int reg;
1965 
1966         switch (w->shift) {
1967         case WM8962_HPOUTR_PGA_ENA_SHIFT:
1968                 reg = WM8962_HPOUTR_VOLUME;
1969                 break;
1970         case WM8962_HPOUTL_PGA_ENA_SHIFT:
1971                 reg = WM8962_HPOUTL_VOLUME;
1972                 break;
1973         case WM8962_SPKOUTR_PGA_ENA_SHIFT:
1974                 reg = WM8962_SPKOUTR_VOLUME;
1975                 break;
1976         case WM8962_SPKOUTL_PGA_ENA_SHIFT:
1977                 reg = WM8962_SPKOUTL_VOLUME;
1978                 break;
1979         default:
1980                 WARN(1, "Invalid shift %d\n", w->shift);
1981                 return -EINVAL;
1982         }
1983 
1984         switch (event) {
1985         case SND_SOC_DAPM_POST_PMU:
1986                 return snd_soc_write(codec, reg, snd_soc_read(codec, reg));
1987         default:
1988                 WARN(1, "Invalid event %d\n", event);
1989                 return -EINVAL;
1990         }
1991 }
1992 
1993 static int dsp2_event(struct snd_soc_dapm_widget *w,
1994                       struct snd_kcontrol *kcontrol, int event)
1995 {
1996         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1997         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1998 
1999         switch (event) {
2000         case SND_SOC_DAPM_POST_PMU:
2001                 if (wm8962->dsp2_ena)
2002                         wm8962_dsp2_start(codec);
2003                 break;
2004 
2005         case SND_SOC_DAPM_PRE_PMD:
2006                 if (wm8962->dsp2_ena)
2007                         wm8962_dsp2_stop(codec);
2008                 break;
2009 
2010         default:
2011                 WARN(1, "Invalid event %d\n", event);
2012                 return -EINVAL;
2013         }
2014 
2015         return 0;
2016 }
2017 
2018 static const char *st_text[] = { "None", "Left", "Right" };
2019 
2020 static SOC_ENUM_SINGLE_DECL(str_enum,
2021                             WM8962_DAC_DSP_MIXING_1, 2, st_text);
2022 
2023 static const struct snd_kcontrol_new str_mux =
2024         SOC_DAPM_ENUM("Right Sidetone", str_enum);
2025 
2026 static SOC_ENUM_SINGLE_DECL(stl_enum,
2027                             WM8962_DAC_DSP_MIXING_2, 2, st_text);
2028 
2029 static const struct snd_kcontrol_new stl_mux =
2030         SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2031 
2032 static const char *outmux_text[] = { "DAC", "Mixer" };
2033 
2034 static SOC_ENUM_SINGLE_DECL(spkoutr_enum,
2035                             WM8962_SPEAKER_MIXER_2, 7, outmux_text);
2036 
2037 static const struct snd_kcontrol_new spkoutr_mux =
2038         SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2039 
2040 static SOC_ENUM_SINGLE_DECL(spkoutl_enum,
2041                             WM8962_SPEAKER_MIXER_1, 7, outmux_text);
2042 
2043 static const struct snd_kcontrol_new spkoutl_mux =
2044         SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2045 
2046 static SOC_ENUM_SINGLE_DECL(hpoutr_enum,
2047                             WM8962_HEADPHONE_MIXER_2, 7, outmux_text);
2048 
2049 static const struct snd_kcontrol_new hpoutr_mux =
2050         SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2051 
2052 static SOC_ENUM_SINGLE_DECL(hpoutl_enum,
2053                             WM8962_HEADPHONE_MIXER_1, 7, outmux_text);
2054 
2055 static const struct snd_kcontrol_new hpoutl_mux =
2056         SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2057 
2058 static const struct snd_kcontrol_new inpgal[] = {
2059 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2060 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2061 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2062 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2063 };
2064 
2065 static const struct snd_kcontrol_new inpgar[] = {
2066 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2067 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2068 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2069 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2070 };
2071 
2072 static const struct snd_kcontrol_new mixinl[] = {
2073 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2074 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2075 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2076 };
2077 
2078 static const struct snd_kcontrol_new mixinr[] = {
2079 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2080 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2081 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2082 };
2083 
2084 static const struct snd_kcontrol_new hpmixl[] = {
2085 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2086 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2087 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2088 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2089 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2090 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2091 };
2092 
2093 static const struct snd_kcontrol_new hpmixr[] = {
2094 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2095 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2096 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2097 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2098 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2099 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2100 };
2101 
2102 static const struct snd_kcontrol_new spkmixl[] = {
2103 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2104 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2105 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2106 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2107 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2108 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2109 };
2110 
2111 static const struct snd_kcontrol_new spkmixr[] = {
2112 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2113 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2114 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2115 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2116 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2117 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2118 };
2119 
2120 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2121 SND_SOC_DAPM_INPUT("IN1L"),
2122 SND_SOC_DAPM_INPUT("IN1R"),
2123 SND_SOC_DAPM_INPUT("IN2L"),
2124 SND_SOC_DAPM_INPUT("IN2R"),
2125 SND_SOC_DAPM_INPUT("IN3L"),
2126 SND_SOC_DAPM_INPUT("IN3R"),
2127 SND_SOC_DAPM_INPUT("IN4L"),
2128 SND_SOC_DAPM_INPUT("IN4R"),
2129 SND_SOC_DAPM_SIGGEN("Beep"),
2130 SND_SOC_DAPM_INPUT("DMICDAT"),
2131 
2132 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
2133 
2134 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2135 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
2136 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2137                     SND_SOC_DAPM_POST_PMU),
2138 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
2139 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2140                       WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2141                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2142 SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2143 SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
2144 
2145 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2146                    inpgal, ARRAY_SIZE(inpgal)),
2147 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2148                    inpgar, ARRAY_SIZE(inpgar)),
2149 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2150                    mixinl, ARRAY_SIZE(mixinl)),
2151 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2152                    mixinr, ARRAY_SIZE(mixinr)),
2153 
2154 SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
2155 
2156 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2157 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2158 
2159 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2160 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2161 
2162 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2163 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2164 
2165 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2166 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2167 
2168 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2169                    hpmixl, ARRAY_SIZE(hpmixl)),
2170 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2171                    hpmixr, ARRAY_SIZE(hpmixr)),
2172 
2173 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2174                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2175 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2176                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2177 
2178 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2179                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2180 
2181 SND_SOC_DAPM_OUTPUT("HPOUTL"),
2182 SND_SOC_DAPM_OUTPUT("HPOUTR"),
2183 };
2184 
2185 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2186 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2187                    spkmixl, ARRAY_SIZE(spkmixl)),
2188 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2189                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2190 SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2191 SND_SOC_DAPM_OUTPUT("SPKOUT"),
2192 };
2193 
2194 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2195 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2196                    spkmixl, ARRAY_SIZE(spkmixl)),
2197 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2198                    spkmixr, ARRAY_SIZE(spkmixr)),
2199 
2200 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2201                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2202 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2203                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2204 
2205 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2206 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2207 
2208 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2209 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2210 };
2211 
2212 static const struct snd_soc_dapm_route wm8962_intercon[] = {
2213         { "INPGAL", "IN1L Switch", "IN1L" },
2214         { "INPGAL", "IN2L Switch", "IN2L" },
2215         { "INPGAL", "IN3L Switch", "IN3L" },
2216         { "INPGAL", "IN4L Switch", "IN4L" },
2217 
2218         { "INPGAR", "IN1R Switch", "IN1R" },
2219         { "INPGAR", "IN2R Switch", "IN2R" },
2220         { "INPGAR", "IN3R Switch", "IN3R" },
2221         { "INPGAR", "IN4R Switch", "IN4R" },
2222 
2223         { "MIXINL", "IN2L Switch", "IN2L" },
2224         { "MIXINL", "IN3L Switch", "IN3L" },
2225         { "MIXINL", "PGA Switch", "INPGAL" },
2226 
2227         { "MIXINR", "IN2R Switch", "IN2R" },
2228         { "MIXINR", "IN3R Switch", "IN3R" },
2229         { "MIXINR", "PGA Switch", "INPGAR" },
2230 
2231         { "MICBIAS", NULL, "SYSCLK" },
2232 
2233         { "DMIC_ENA", NULL, "DMICDAT" },
2234 
2235         { "ADCL", NULL, "SYSCLK" },
2236         { "ADCL", NULL, "TOCLK" },
2237         { "ADCL", NULL, "MIXINL" },
2238         { "ADCL", NULL, "DMIC_ENA" },
2239         { "ADCL", NULL, "DSP2" },
2240 
2241         { "ADCR", NULL, "SYSCLK" },
2242         { "ADCR", NULL, "TOCLK" },
2243         { "ADCR", NULL, "MIXINR" },
2244         { "ADCR", NULL, "DMIC_ENA" },
2245         { "ADCR", NULL, "DSP2" },
2246 
2247         { "STL", "Left", "ADCL" },
2248         { "STL", "Right", "ADCR" },
2249         { "STL", NULL, "Class G" },
2250 
2251         { "STR", "Left", "ADCL" },
2252         { "STR", "Right", "ADCR" },
2253         { "STR", NULL, "Class G" },
2254 
2255         { "DACL", NULL, "SYSCLK" },
2256         { "DACL", NULL, "TOCLK" },
2257         { "DACL", NULL, "Beep" },
2258         { "DACL", NULL, "STL" },
2259         { "DACL", NULL, "DSP2" },
2260 
2261         { "DACR", NULL, "SYSCLK" },
2262         { "DACR", NULL, "TOCLK" },
2263         { "DACR", NULL, "Beep" },
2264         { "DACR", NULL, "STR" },
2265         { "DACR", NULL, "DSP2" },
2266 
2267         { "HPMIXL", "IN4L Switch", "IN4L" },
2268         { "HPMIXL", "IN4R Switch", "IN4R" },
2269         { "HPMIXL", "DACL Switch", "DACL" },
2270         { "HPMIXL", "DACR Switch", "DACR" },
2271         { "HPMIXL", "MIXINL Switch", "MIXINL" },
2272         { "HPMIXL", "MIXINR Switch", "MIXINR" },
2273 
2274         { "HPMIXR", "IN4L Switch", "IN4L" },
2275         { "HPMIXR", "IN4R Switch", "IN4R" },
2276         { "HPMIXR", "DACL Switch", "DACL" },
2277         { "HPMIXR", "DACR Switch", "DACR" },
2278         { "HPMIXR", "MIXINL Switch", "MIXINL" },
2279         { "HPMIXR", "MIXINR Switch", "MIXINR" },
2280 
2281         { "Left Bypass", NULL, "HPMIXL" },
2282         { "Left Bypass", NULL, "Class G" },
2283 
2284         { "Right Bypass", NULL, "HPMIXR" },
2285         { "Right Bypass", NULL, "Class G" },
2286 
2287         { "HPOUTL PGA", "Mixer", "Left Bypass" },
2288         { "HPOUTL PGA", "DAC", "DACL" },
2289 
2290         { "HPOUTR PGA", "Mixer", "Right Bypass" },
2291         { "HPOUTR PGA", "DAC", "DACR" },
2292 
2293         { "HPOUT", NULL, "HPOUTL PGA" },
2294         { "HPOUT", NULL, "HPOUTR PGA" },
2295         { "HPOUT", NULL, "Charge Pump" },
2296         { "HPOUT", NULL, "SYSCLK" },
2297         { "HPOUT", NULL, "TOCLK" },
2298 
2299         { "HPOUTL", NULL, "HPOUT" },
2300         { "HPOUTR", NULL, "HPOUT" },
2301 
2302         { "HPOUTL", NULL, "TEMP_HP" },
2303         { "HPOUTR", NULL, "TEMP_HP" },
2304 };
2305 
2306 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2307         { "Speaker Mixer", "IN4L Switch", "IN4L" },
2308         { "Speaker Mixer", "IN4R Switch", "IN4R" },
2309         { "Speaker Mixer", "DACL Switch", "DACL" },
2310         { "Speaker Mixer", "DACR Switch", "DACR" },
2311         { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2312         { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2313 
2314         { "Speaker PGA", "Mixer", "Speaker Mixer" },
2315         { "Speaker PGA", "DAC", "DACL" },
2316 
2317         { "Speaker Output", NULL, "Speaker PGA" },
2318         { "Speaker Output", NULL, "SYSCLK" },
2319         { "Speaker Output", NULL, "TOCLK" },
2320         { "Speaker Output", NULL, "TEMP_SPK" },
2321 
2322         { "SPKOUT", NULL, "Speaker Output" },
2323 };
2324 
2325 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2326         { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2327         { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2328         { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2329         { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2330         { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2331         { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2332 
2333         { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2334         { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2335         { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2336         { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2337         { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2338         { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2339 
2340         { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2341         { "SPKOUTL PGA", "DAC", "DACL" },
2342 
2343         { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2344         { "SPKOUTR PGA", "DAC", "DACR" },
2345 
2346         { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2347         { "SPKOUTL Output", NULL, "SYSCLK" },
2348         { "SPKOUTL Output", NULL, "TOCLK" },
2349         { "SPKOUTL Output", NULL, "TEMP_SPK" },
2350 
2351         { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2352         { "SPKOUTR Output", NULL, "SYSCLK" },
2353         { "SPKOUTR Output", NULL, "TOCLK" },
2354         { "SPKOUTR Output", NULL, "TEMP_SPK" },
2355 
2356         { "SPKOUTL", NULL, "SPKOUTL Output" },
2357         { "SPKOUTR", NULL, "SPKOUTR Output" },
2358 };
2359 
2360 static int wm8962_add_widgets(struct snd_soc_codec *codec)
2361 {
2362         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2363         struct wm8962_pdata *pdata = &wm8962->pdata;
2364         struct snd_soc_dapm_context *dapm = &codec->dapm;
2365 
2366         snd_soc_add_codec_controls(codec, wm8962_snd_controls,
2367                              ARRAY_SIZE(wm8962_snd_controls));
2368         if (pdata->spk_mono)
2369                 snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls,
2370                                      ARRAY_SIZE(wm8962_spk_mono_controls));
2371         else
2372                 snd_soc_add_codec_controls(codec, wm8962_spk_stereo_controls,
2373                                      ARRAY_SIZE(wm8962_spk_stereo_controls));
2374 
2375 
2376         snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2377                                   ARRAY_SIZE(wm8962_dapm_widgets));
2378         if (pdata->spk_mono)
2379                 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2380                                           ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2381         else
2382                 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2383                                           ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2384 
2385         snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2386                                 ARRAY_SIZE(wm8962_intercon));
2387         if (pdata->spk_mono)
2388                 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2389                                         ARRAY_SIZE(wm8962_spk_mono_intercon));
2390         else
2391                 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2392                                         ARRAY_SIZE(wm8962_spk_stereo_intercon));
2393 
2394 
2395         snd_soc_dapm_disable_pin(dapm, "Beep");
2396 
2397         return 0;
2398 }
2399 
2400 /* -1 for reserved values */
2401 static const int bclk_divs[] = {
2402         1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2403 };
2404 
2405 static const int sysclk_rates[] = {
2406         64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
2407 };
2408 
2409 static void wm8962_configure_bclk(struct snd_soc_codec *codec)
2410 {
2411         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2412         int dspclk, i;
2413         int clocking2 = 0;
2414         int clocking4 = 0;
2415         int aif2 = 0;
2416 
2417         if (!wm8962->sysclk_rate) {
2418                 dev_dbg(codec->dev, "No SYSCLK configured\n");
2419                 return;
2420         }
2421 
2422         if (!wm8962->bclk || !wm8962->lrclk) {
2423                 dev_dbg(codec->dev, "No audio clocks configured\n");
2424                 return;
2425         }
2426 
2427         for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2428                 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2429                         clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2430                         break;
2431                 }
2432         }
2433 
2434         if (i == ARRAY_SIZE(sysclk_rates)) {
2435                 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
2436                         wm8962->sysclk_rate / wm8962->lrclk);
2437                 return;
2438         }
2439 
2440         dev_dbg(codec->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2441 
2442         snd_soc_update_bits(codec, WM8962_CLOCKING_4,
2443                             WM8962_SYSCLK_RATE_MASK, clocking4);
2444 
2445         /* DSPCLK_DIV can be only generated correctly after enabling SYSCLK.
2446          * So we here provisionally enable it and then disable it afterward
2447          * if current bias_level hasn't reached SND_SOC_BIAS_ON.
2448          */
2449         if (codec->dapm.bias_level != SND_SOC_BIAS_ON)
2450                 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2451                                 WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
2452 
2453         dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
2454 
2455         if (codec->dapm.bias_level != SND_SOC_BIAS_ON)
2456                 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2457                                 WM8962_SYSCLK_ENA_MASK, 0);
2458 
2459         if (dspclk < 0) {
2460                 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
2461                 return;
2462         }
2463 
2464         dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2465         switch (dspclk) {
2466         case 0:
2467                 dspclk = wm8962->sysclk_rate;
2468                 break;
2469         case 1:
2470                 dspclk = wm8962->sysclk_rate / 2;
2471                 break;
2472         case 2:
2473                 dspclk = wm8962->sysclk_rate / 4;
2474                 break;
2475         default:
2476                 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2477                 dspclk = wm8962->sysclk;
2478         }
2479 
2480         dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2481 
2482         /* We're expecting an exact match */
2483         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2484                 if (bclk_divs[i] < 0)
2485                         continue;
2486 
2487                 if (dspclk / bclk_divs[i] == wm8962->bclk) {
2488                         dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
2489                                 bclk_divs[i], wm8962->bclk);
2490                         clocking2 |= i;
2491                         break;
2492                 }
2493         }
2494         if (i == ARRAY_SIZE(bclk_divs)) {
2495                 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
2496                         dspclk / wm8962->bclk);
2497                 return;
2498         }
2499 
2500         aif2 |= wm8962->bclk / wm8962->lrclk;
2501         dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
2502                 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2503 
2504         snd_soc_update_bits(codec, WM8962_CLOCKING2,
2505                             WM8962_BCLK_DIV_MASK, clocking2);
2506         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
2507                             WM8962_AIF_RATE_MASK, aif2);
2508 }
2509 
2510 static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2511                                  enum snd_soc_bias_level level)
2512 {
2513         if (level == codec->dapm.bias_level)
2514                 return 0;
2515 
2516         switch (level) {
2517         case SND_SOC_BIAS_ON:
2518                 break;
2519 
2520         case SND_SOC_BIAS_PREPARE:
2521                 /* VMID 2*50k */
2522                 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2523                                     WM8962_VMID_SEL_MASK, 0x80);
2524 
2525                 wm8962_configure_bclk(codec);
2526                 break;
2527 
2528         case SND_SOC_BIAS_STANDBY:
2529                 /* VMID 2*250k */
2530                 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2531                                     WM8962_VMID_SEL_MASK, 0x100);
2532 
2533                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2534                         msleep(100);
2535                 break;
2536 
2537         case SND_SOC_BIAS_OFF:
2538                 break;
2539         }
2540 
2541         codec->dapm.bias_level = level;
2542         return 0;
2543 }
2544 
2545 static const struct {
2546         int rate;
2547         int reg;
2548 } sr_vals[] = {
2549         { 48000, 0 },
2550         { 44100, 0 },
2551         { 32000, 1 },
2552         { 22050, 2 },
2553         { 24000, 2 },
2554         { 16000, 3 },
2555         { 11025, 4 },
2556         { 12000, 4 },
2557         { 8000,  5 },
2558         { 88200, 6 },
2559         { 96000, 6 },
2560 };
2561 
2562 static int wm8962_hw_params(struct snd_pcm_substream *substream,
2563                             struct snd_pcm_hw_params *params,
2564                             struct snd_soc_dai *dai)
2565 {
2566         struct snd_soc_codec *codec = dai->codec;
2567         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2568         int i;
2569         int aif0 = 0;
2570         int adctl3 = 0;
2571 
2572         wm8962->bclk = snd_soc_params_to_bclk(params);
2573         if (params_channels(params) == 1)
2574                 wm8962->bclk *= 2;
2575 
2576         wm8962->lrclk = params_rate(params);
2577 
2578         for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
2579                 if (sr_vals[i].rate == wm8962->lrclk) {
2580                         adctl3 |= sr_vals[i].reg;
2581                         break;
2582                 }
2583         }
2584         if (i == ARRAY_SIZE(sr_vals)) {
2585                 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
2586                 return -EINVAL;
2587         }
2588 
2589         if (wm8962->lrclk % 8000 == 0)
2590                 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2591 
2592         switch (params_width(params)) {
2593         case 16:
2594                 break;
2595         case 20:
2596                 aif0 |= 0x4;
2597                 break;
2598         case 24:
2599                 aif0 |= 0x8;
2600                 break;
2601         case 32:
2602                 aif0 |= 0xc;
2603                 break;
2604         default:
2605                 return -EINVAL;
2606         }
2607 
2608         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2609                             WM8962_WL_MASK, aif0);
2610         snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
2611                             WM8962_SAMPLE_RATE_INT_MODE |
2612                             WM8962_SAMPLE_RATE_MASK, adctl3);
2613 
2614         dev_dbg(codec->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
2615                 wm8962->bclk, wm8962->lrclk);
2616 
2617         if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
2618                 wm8962_configure_bclk(codec);
2619 
2620         return 0;
2621 }
2622 
2623 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2624                                  unsigned int freq, int dir)
2625 {
2626         struct snd_soc_codec *codec = dai->codec;
2627         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2628         int src;
2629 
2630         switch (clk_id) {
2631         case WM8962_SYSCLK_MCLK:
2632                 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2633                 src = 0;
2634                 break;
2635         case WM8962_SYSCLK_FLL:
2636                 wm8962->sysclk = WM8962_SYSCLK_FLL;
2637                 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
2638                 break;
2639         default:
2640                 return -EINVAL;
2641         }
2642 
2643         snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2644                             src);
2645 
2646         wm8962->sysclk_rate = freq;
2647 
2648         return 0;
2649 }
2650 
2651 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2652 {
2653         struct snd_soc_codec *codec = dai->codec;
2654         int aif0 = 0;
2655 
2656         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2657         case SND_SOC_DAIFMT_DSP_B:
2658                 aif0 |= WM8962_LRCLK_INV | 3;
2659         case SND_SOC_DAIFMT_DSP_A:
2660                 aif0 |= 3;
2661 
2662                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2663                 case SND_SOC_DAIFMT_NB_NF:
2664                 case SND_SOC_DAIFMT_IB_NF:
2665                         break;
2666                 default:
2667                         return -EINVAL;
2668                 }
2669                 break;
2670 
2671         case SND_SOC_DAIFMT_RIGHT_J:
2672                 break;
2673         case SND_SOC_DAIFMT_LEFT_J:
2674                 aif0 |= 1;
2675                 break;
2676         case SND_SOC_DAIFMT_I2S:
2677                 aif0 |= 2;
2678                 break;
2679         default:
2680                 return -EINVAL;
2681         }
2682 
2683         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2684         case SND_SOC_DAIFMT_NB_NF:
2685                 break;
2686         case SND_SOC_DAIFMT_IB_NF:
2687                 aif0 |= WM8962_BCLK_INV;
2688                 break;
2689         case SND_SOC_DAIFMT_NB_IF:
2690                 aif0 |= WM8962_LRCLK_INV;
2691                 break;
2692         case SND_SOC_DAIFMT_IB_IF:
2693                 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2694                 break;
2695         default:
2696                 return -EINVAL;
2697         }
2698 
2699         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2700         case SND_SOC_DAIFMT_CBM_CFM:
2701                 aif0 |= WM8962_MSTR;
2702                 break;
2703         case SND_SOC_DAIFMT_CBS_CFS:
2704                 break;
2705         default:
2706                 return -EINVAL;
2707         }
2708 
2709         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2710                             WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2711                             WM8962_LRCLK_INV, aif0);
2712 
2713         return 0;
2714 }
2715 
2716 struct _fll_div {
2717         u16 fll_fratio;
2718         u16 fll_outdiv;
2719         u16 fll_refclk_div;
2720         u16 n;
2721         u16 theta;
2722         u16 lambda;
2723 };
2724 
2725 /* The size in bits of the FLL divide multiplied by 10
2726  * to allow rounding later */
2727 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2728 
2729 static struct {
2730         unsigned int min;
2731         unsigned int max;
2732         u16 fll_fratio;
2733         int ratio;
2734 } fll_fratios[] = {
2735         {       0,    64000, 4, 16 },
2736         {   64000,   128000, 3,  8 },
2737         {  128000,   256000, 2,  4 },
2738         {  256000,  1000000, 1,  2 },
2739         { 1000000, 13500000, 0,  1 },
2740 };
2741 
2742 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2743                        unsigned int Fout)
2744 {
2745         unsigned int target;
2746         unsigned int div;
2747         unsigned int fratio, gcd_fll;
2748         int i;
2749 
2750         /* Fref must be <=13.5MHz */
2751         div = 1;
2752         fll_div->fll_refclk_div = 0;
2753         while ((Fref / div) > 13500000) {
2754                 div *= 2;
2755                 fll_div->fll_refclk_div++;
2756 
2757                 if (div > 4) {
2758                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2759                                Fref);
2760                         return -EINVAL;
2761                 }
2762         }
2763 
2764         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2765 
2766         /* Apply the division for our remaining calculations */
2767         Fref /= div;
2768 
2769         /* Fvco should be 90-100MHz; don't check the upper bound */
2770         div = 2;
2771         while (Fout * div < 90000000) {
2772                 div++;
2773                 if (div > 64) {
2774                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2775                                Fout);
2776                         return -EINVAL;
2777                 }
2778         }
2779         target = Fout * div;
2780         fll_div->fll_outdiv = div - 1;
2781 
2782         pr_debug("FLL Fvco=%dHz\n", target);
2783 
2784         /* Find an appropriate FLL_FRATIO and factor it out of the target */
2785         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2786                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2787                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2788                         fratio = fll_fratios[i].ratio;
2789                         break;
2790                 }
2791         }
2792         if (i == ARRAY_SIZE(fll_fratios)) {
2793                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2794                 return -EINVAL;
2795         }
2796 
2797         fll_div->n = target / (fratio * Fref);
2798 
2799         if (target % Fref == 0) {
2800                 fll_div->theta = 0;
2801                 fll_div->lambda = 0;
2802         } else {
2803                 gcd_fll = gcd(target, fratio * Fref);
2804 
2805                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2806                         / gcd_fll;
2807                 fll_div->lambda = (fratio * Fref) / gcd_fll;
2808         }
2809 
2810         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2811                  fll_div->n, fll_div->theta, fll_div->lambda);
2812         pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2813                  fll_div->fll_fratio, fll_div->fll_outdiv,
2814                  fll_div->fll_refclk_div);
2815 
2816         return 0;
2817 }
2818 
2819 static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2820                           unsigned int Fref, unsigned int Fout)
2821 {
2822         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2823         struct _fll_div fll_div;
2824         unsigned long timeout;
2825         int ret;
2826         int fll1 = 0;
2827 
2828         /* Any change? */
2829         if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2830             Fout == wm8962->fll_fout)
2831                 return 0;
2832 
2833         if (Fout == 0) {
2834                 dev_dbg(codec->dev, "FLL disabled\n");
2835 
2836                 wm8962->fll_fref = 0;
2837                 wm8962->fll_fout = 0;
2838 
2839                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2840                                     WM8962_FLL_ENA, 0);
2841 
2842                 pm_runtime_put(codec->dev);
2843 
2844                 return 0;
2845         }
2846 
2847         ret = fll_factors(&fll_div, Fref, Fout);
2848         if (ret != 0)
2849                 return ret;
2850 
2851         /* Parameters good, disable so we can reprogram */
2852         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2853 
2854         switch (fll_id) {
2855         case WM8962_FLL_MCLK:
2856         case WM8962_FLL_BCLK:
2857         case WM8962_FLL_OSC:
2858                 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2859                 break;
2860         case WM8962_FLL_INT:
2861                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2862                                     WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2863                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
2864                                     WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2865                 break;
2866         default:
2867                 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2868                 return -EINVAL;
2869         }
2870 
2871         if (fll_div.theta || fll_div.lambda)
2872                 fll1 |= WM8962_FLL_FRAC;
2873 
2874         /* Stop the FLL while we reconfigure */
2875         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2876 
2877         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
2878                             WM8962_FLL_OUTDIV_MASK |
2879                             WM8962_FLL_REFCLK_DIV_MASK,
2880                             (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2881                             (fll_div.fll_refclk_div));
2882 
2883         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
2884                             WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2885 
2886         snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
2887         snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
2888         snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
2889 
2890         reinit_completion(&wm8962->fll_lock);
2891 
2892         ret = pm_runtime_get_sync(codec->dev);
2893         if (ret < 0) {
2894                 dev_err(codec->dev, "Failed to resume device: %d\n", ret);
2895                 return ret;
2896         }
2897 
2898         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2899                             WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
2900                             WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
2901 
2902         dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2903 
2904         /* This should be a massive overestimate but go even
2905          * higher if we'll error out
2906          */
2907         if (wm8962->irq)
2908                 timeout = msecs_to_jiffies(5);
2909         else
2910                 timeout = msecs_to_jiffies(1);
2911 
2912         timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2913                                               timeout);
2914 
2915         if (timeout == 0 && wm8962->irq) {
2916                 dev_err(codec->dev, "FLL lock timed out");
2917                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2918                                     WM8962_FLL_ENA, 0);
2919                 pm_runtime_put(codec->dev);
2920                 return -ETIMEDOUT;
2921         }
2922 
2923         wm8962->fll_fref = Fref;
2924         wm8962->fll_fout = Fout;
2925         wm8962->fll_src = source;
2926 
2927         return 0;
2928 }
2929 
2930 static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2931 {
2932         struct snd_soc_codec *codec = dai->codec;
2933         int val, ret;
2934 
2935         if (mute)
2936                 val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT;
2937         else
2938                 val = 0;
2939 
2940         /**
2941          * The DAC mute bit is mirrored in two registers, update both to keep
2942          * the register cache consistent.
2943          */
2944         ret = snd_soc_update_bits(codec, WM8962_CLASS_D_CONTROL_1,
2945                                   WM8962_DAC_MUTE_ALT, val);
2946         if (ret < 0)
2947                 return ret;
2948 
2949         return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
2950                                    WM8962_DAC_MUTE, val);
2951 }
2952 
2953 #define WM8962_RATES SNDRV_PCM_RATE_8000_96000
2954 
2955 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2956                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2957 
2958 static const struct snd_soc_dai_ops wm8962_dai_ops = {
2959         .hw_params = wm8962_hw_params,
2960         .set_sysclk = wm8962_set_dai_sysclk,
2961         .set_fmt = wm8962_set_dai_fmt,
2962         .digital_mute = wm8962_mute,
2963 };
2964 
2965 static struct snd_soc_dai_driver wm8962_dai = {
2966         .name = "wm8962",
2967         .playback = {
2968                 .stream_name = "Playback",
2969                 .channels_min = 1,
2970                 .channels_max = 2,
2971                 .rates = WM8962_RATES,
2972                 .formats = WM8962_FORMATS,
2973         },
2974         .capture = {
2975                 .stream_name = "Capture",
2976                 .channels_min = 1,
2977                 .channels_max = 2,
2978                 .rates = WM8962_RATES,
2979                 .formats = WM8962_FORMATS,
2980         },
2981         .ops = &wm8962_dai_ops,
2982         .symmetric_rates = 1,
2983 };
2984 
2985 static void wm8962_mic_work(struct work_struct *work)
2986 {
2987         struct wm8962_priv *wm8962 = container_of(work,
2988                                                   struct wm8962_priv,
2989                                                   mic_work.work);
2990         struct snd_soc_codec *codec = wm8962->codec;
2991         int status = 0;
2992         int irq_pol = 0;
2993         int reg;
2994 
2995         reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
2996 
2997         if (reg & WM8962_MICDET_STS) {
2998                 status |= SND_JACK_MICROPHONE;
2999                 irq_pol |= WM8962_MICD_IRQ_POL;
3000         }
3001 
3002         if (reg & WM8962_MICSHORT_STS) {
3003                 status |= SND_JACK_BTN_0;
3004                 irq_pol |= WM8962_MICSCD_IRQ_POL;
3005         }
3006 
3007         snd_soc_jack_report(wm8962->jack, status,
3008                             SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3009 
3010         snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
3011                             WM8962_MICSCD_IRQ_POL |
3012                             WM8962_MICD_IRQ_POL, irq_pol);
3013 }
3014 
3015 static irqreturn_t wm8962_irq(int irq, void *data)
3016 {
3017         struct device *dev = data;
3018         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3019         unsigned int mask;
3020         unsigned int active;
3021         int reg, ret;
3022 
3023         ret = pm_runtime_get_sync(dev);
3024         if (ret < 0) {
3025                 dev_err(dev, "Failed to resume: %d\n", ret);
3026                 return IRQ_NONE;
3027         }
3028 
3029         ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
3030                           &mask);
3031         if (ret != 0) {
3032                 pm_runtime_put(dev);
3033                 dev_err(dev, "Failed to read interrupt mask: %d\n",
3034                         ret);
3035                 return IRQ_NONE;
3036         }
3037 
3038         ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
3039         if (ret != 0) {
3040                 pm_runtime_put(dev);
3041                 dev_err(dev, "Failed to read interrupt: %d\n", ret);
3042                 return IRQ_NONE;
3043         }
3044 
3045         active &= ~mask;
3046 
3047         if (!active) {
3048                 pm_runtime_put(dev);
3049                 return IRQ_NONE;
3050         }
3051 
3052         /* Acknowledge the interrupts */
3053         ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
3054         if (ret != 0)
3055                 dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
3056 
3057         if (active & WM8962_FLL_LOCK_EINT) {
3058                 dev_dbg(dev, "FLL locked\n");
3059                 complete(&wm8962->fll_lock);
3060         }
3061 
3062         if (active & WM8962_FIFOS_ERR_EINT)
3063                 dev_err(dev, "FIFO error\n");
3064 
3065         if (active & WM8962_TEMP_SHUT_EINT) {
3066                 dev_crit(dev, "Thermal shutdown\n");
3067 
3068                 ret = regmap_read(wm8962->regmap,
3069                                   WM8962_THERMAL_SHUTDOWN_STATUS,  &reg);
3070                 if (ret != 0) {
3071                         dev_warn(dev, "Failed to read thermal status: %d\n",
3072                                  ret);
3073                         reg = 0;
3074                 }
3075 
3076                 if (reg & WM8962_TEMP_ERR_HP)
3077                         dev_crit(dev, "Headphone thermal error\n");
3078                 if (reg & WM8962_TEMP_WARN_HP)
3079                         dev_crit(dev, "Headphone thermal warning\n");
3080                 if (reg & WM8962_TEMP_ERR_SPK)
3081                         dev_crit(dev, "Speaker thermal error\n");
3082                 if (reg & WM8962_TEMP_WARN_SPK)
3083                         dev_crit(dev, "Speaker thermal warning\n");
3084         }
3085 
3086         if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3087                 dev_dbg(dev, "Microphone event detected\n");
3088 
3089 #ifndef CONFIG_SND_SOC_WM8962_MODULE
3090                 trace_snd_soc_jack_irq(dev_name(dev));
3091 #endif
3092 
3093                 pm_wakeup_event(dev, 300);
3094 
3095                 queue_delayed_work(system_power_efficient_wq,
3096                                    &wm8962->mic_work,
3097                                    msecs_to_jiffies(250));
3098         }
3099 
3100         pm_runtime_put(dev);
3101 
3102         return IRQ_HANDLED;
3103 }
3104 
3105 /**
3106  * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3107  *
3108  * @codec:  WM8962 codec
3109  * @jack:   jack to report detection events on
3110  *
3111  * Enable microphone detection via IRQ on the WM8962.  If GPIOs are
3112  * being used to bring out signals to the processor then only platform
3113  * data configuration is needed for WM8962 and processor GPIOs should
3114  * be configured using snd_soc_jack_add_gpios() instead.
3115  *
3116  * If no jack is supplied detection will be disabled.
3117  */
3118 int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3119 {
3120         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3121         struct snd_soc_dapm_context *dapm = &codec->dapm;
3122         int irq_mask, enable;
3123 
3124         wm8962->jack = jack;
3125         if (jack) {
3126                 irq_mask = 0;
3127                 enable = WM8962_MICDET_ENA;
3128         } else {
3129                 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3130                 enable = 0;
3131         }
3132 
3133         snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
3134                             WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3135         snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3136                             WM8962_MICDET_ENA, enable);
3137 
3138         /* Send an initial empty report */
3139         snd_soc_jack_report(wm8962->jack, 0,
3140                             SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3141 
3142         snd_soc_dapm_mutex_lock(dapm);
3143 
3144         if (jack) {
3145                 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
3146                 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
3147         } else {
3148                 snd_soc_dapm_disable_pin_unlocked(dapm, "SYSCLK");
3149                 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
3150         }
3151 
3152         snd_soc_dapm_mutex_unlock(dapm);
3153 
3154         return 0;
3155 }
3156 EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3157 
3158 static int beep_rates[] = {
3159         500, 1000, 2000, 4000,
3160 };
3161 
3162 static void wm8962_beep_work(struct work_struct *work)
3163 {
3164         struct wm8962_priv *wm8962 =
3165                 container_of(work, struct wm8962_priv, beep_work);
3166         struct snd_soc_codec *codec = wm8962->codec;
3167         struct snd_soc_dapm_context *dapm = &codec->dapm;
3168         int i;
3169         int reg = 0;
3170         int best = 0;
3171 
3172         if (wm8962->beep_rate) {
3173                 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3174                         if (abs(wm8962->beep_rate - beep_rates[i]) <
3175                             abs(wm8962->beep_rate - beep_rates[best]))
3176                                 best = i;
3177                 }
3178 
3179                 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
3180                         beep_rates[best], wm8962->beep_rate);
3181 
3182                 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3183 
3184                 snd_soc_dapm_enable_pin(dapm, "Beep");
3185         } else {
3186                 dev_dbg(codec->dev, "Disabling beep\n");
3187                 snd_soc_dapm_disable_pin(dapm, "Beep");
3188         }
3189 
3190         snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3191                             WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3192 
3193         snd_soc_dapm_sync(dapm);
3194 }
3195 
3196 /* For usability define a way of injecting beep events for the device -
3197  * many systems will not have a keyboard.
3198  */
3199 static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3200                              unsigned int code, int hz)
3201 {
3202         struct snd_soc_codec *codec = input_get_drvdata(dev);
3203         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3204 
3205         dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
3206 
3207         switch (code) {
3208         case SND_BELL:
3209                 if (hz)
3210                         hz = 1000;
3211         case SND_TONE:
3212                 break;
3213         default:
3214                 return -1;
3215         }
3216 
3217         /* Kick the beep from a workqueue */
3218         wm8962->beep_rate = hz;
3219         schedule_work(&wm8962->beep_work);
3220         return 0;
3221 }
3222 
3223 static ssize_t wm8962_beep_set(struct device *dev,
3224                                struct device_attribute *attr,
3225                                const char *buf, size_t count)
3226 {
3227         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3228         long int time;
3229         int ret;
3230 
3231         ret = kstrtol(buf, 10, &time);
3232         if (ret != 0)
3233                 return ret;
3234 
3235         input_event(wm8962->beep, EV_SND, SND_TONE, time);
3236 
3237         return count;
3238 }
3239 
3240 static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3241 
3242 static void wm8962_init_beep(struct snd_soc_codec *codec)
3243 {
3244         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3245         int ret;
3246 
3247         wm8962->beep = devm_input_allocate_device(codec->dev);
3248         if (!wm8962->beep) {
3249                 dev_err(codec->dev, "Failed to allocate beep device\n");
3250                 return;
3251         }
3252 
3253         INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3254         wm8962->beep_rate = 0;
3255 
3256         wm8962->beep->name = "WM8962 Beep Generator";
3257         wm8962->beep->phys = dev_name(codec->dev);
3258         wm8962->beep->id.bustype = BUS_I2C;
3259 
3260         wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3261         wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3262         wm8962->beep->event = wm8962_beep_event;
3263         wm8962->beep->dev.parent = codec->dev;
3264         input_set_drvdata(wm8962->beep, codec);
3265 
3266         ret = input_register_device(wm8962->beep);
3267         if (ret != 0) {
3268                 wm8962->beep = NULL;
3269                 dev_err(codec->dev, "Failed to register beep device\n");
3270         }
3271 
3272         ret = device_create_file(codec->dev, &dev_attr_beep);
3273         if (ret != 0) {
3274                 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
3275                         ret);
3276         }
3277 }
3278 
3279 static void wm8962_free_beep(struct snd_soc_codec *codec)
3280 {
3281         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3282 
3283         device_remove_file(codec->dev, &dev_attr_beep);
3284         cancel_work_sync(&wm8962->beep_work);
3285         wm8962->beep = NULL;
3286 
3287         snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3288 }
3289 
3290 static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio)
3291 {
3292         int mask = 0;
3293         int val = 0;
3294 
3295         /* Some of the GPIOs are behind MFP configuration and need to
3296          * be put into GPIO mode. */
3297         switch (gpio) {
3298         case 2:
3299                 mask = WM8962_CLKOUT2_SEL_MASK;
3300                 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3301                 break;
3302         case 3:
3303                 mask = WM8962_CLKOUT3_SEL_MASK;
3304                 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3305                 break;
3306         default:
3307                 break;
3308         }
3309 
3310         if (mask)
3311                 regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1,
3312                                    mask, val);
3313 }
3314 
3315 #ifdef CONFIG_GPIOLIB
3316 static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
3317 {
3318         return container_of(chip, struct wm8962_priv, gpio_chip);
3319 }
3320 
3321 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3322 {
3323         struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3324 
3325         /* The WM8962 GPIOs aren't linearly numbered.  For simplicity
3326          * we export linear numbers and error out if the unsupported
3327          * ones are requsted.
3328          */
3329         switch (offset + 1) {
3330         case 2:
3331         case 3:
3332         case 5:
3333         case 6:
3334                 break;
3335         default:
3336                 return -EINVAL;
3337         }
3338 
3339         wm8962_set_gpio_mode(wm8962, offset + 1);
3340 
3341         return 0;
3342 }
3343 
3344 static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3345 {
3346         struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3347         struct snd_soc_codec *codec = wm8962->codec;
3348 
3349         snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3350                             WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
3351 }
3352 
3353 static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3354                                      unsigned offset, int value)
3355 {
3356         struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3357         struct snd_soc_codec *codec = wm8962->codec;
3358         int ret, val;
3359 
3360         /* Force function 1 (logic output) */
3361         val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3362 
3363         ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3364                                   WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3365         if (ret < 0)
3366                 return ret;
3367 
3368         return 0;
3369 }
3370 
3371 static struct gpio_chip wm8962_template_chip = {
3372         .label                  = "wm8962",
3373         .owner                  = THIS_MODULE,
3374         .request                = wm8962_gpio_request,
3375         .direction_output       = wm8962_gpio_direction_out,
3376         .set                    = wm8962_gpio_set,
3377         .can_sleep              = 1,
3378 };
3379 
3380 static void wm8962_init_gpio(struct snd_soc_codec *codec)
3381 {
3382         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3383         struct wm8962_pdata *pdata = &wm8962->pdata;
3384         int ret;
3385 
3386         wm8962->gpio_chip = wm8962_template_chip;
3387         wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3388         wm8962->gpio_chip.dev = codec->dev;
3389 
3390         if (pdata->gpio_base)
3391                 wm8962->gpio_chip.base = pdata->gpio_base;
3392         else
3393                 wm8962->gpio_chip.base = -1;
3394 
3395         ret = gpiochip_add(&wm8962->gpio_chip);
3396         if (ret != 0)
3397                 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
3398 }
3399 
3400 static void wm8962_free_gpio(struct snd_soc_codec *codec)
3401 {
3402         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3403 
3404         gpiochip_remove(&wm8962->gpio_chip);
3405 }
3406 #else
3407 static void wm8962_init_gpio(struct snd_soc_codec *codec)
3408 {
3409 }
3410 
3411 static void wm8962_free_gpio(struct snd_soc_codec *codec)
3412 {
3413 }
3414 #endif
3415 
3416 static int wm8962_probe(struct snd_soc_codec *codec)
3417 {
3418         int ret;
3419         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3420         int i;
3421         bool dmicclk, dmicdat;
3422 
3423         wm8962->codec = codec;
3424 
3425         wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3426         wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3427         wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3428         wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3429         wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3430         wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3431         wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3432         wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3433 
3434         /* This should really be moved into the regulator core */
3435         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3436                 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3437                                                   &wm8962->disable_nb[i]);
3438                 if (ret != 0) {
3439                         dev_err(codec->dev,
3440                                 "Failed to register regulator notifier: %d\n",
3441                                 ret);
3442                 }
3443         }
3444 
3445         wm8962_add_widgets(codec);
3446 
3447         /* Save boards having to disable DMIC when not in use */
3448         dmicclk = false;
3449         dmicdat = false;
3450         for (i = 0; i < WM8962_MAX_GPIO; i++) {
3451                 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
3452                         & WM8962_GP2_FN_MASK) {
3453                 case WM8962_GPIO_FN_DMICCLK:
3454                         dmicclk = true;
3455                         break;
3456                 case WM8962_GPIO_FN_DMICDAT:
3457                         dmicdat = true;
3458                         break;
3459                 default:
3460                         break;
3461                 }
3462         }
3463         if (!dmicclk || !dmicdat) {
3464                 dev_dbg(codec->dev, "DMIC not in use, disabling\n");
3465                 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
3466         }
3467         if (dmicclk != dmicdat)
3468                 dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
3469 
3470         wm8962_init_beep(codec);
3471         wm8962_init_gpio(codec);
3472 
3473         return 0;
3474 }
3475 
3476 static int wm8962_remove(struct snd_soc_codec *codec)
3477 {
3478         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3479         int i;
3480 
3481         cancel_delayed_work_sync(&wm8962->mic_work);
3482 
3483         wm8962_free_gpio(codec);
3484         wm8962_free_beep(codec);
3485         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3486                 regulator_unregister_notifier(wm8962->supplies[i].consumer,
3487                                               &wm8962->disable_nb[i]);
3488 
3489         return 0;
3490 }
3491 
3492 static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
3493         .probe =        wm8962_probe,
3494         .remove =       wm8962_remove,
3495         .set_bias_level = wm8962_set_bias_level,
3496         .set_pll = wm8962_set_fll,
3497         .idle_bias_off = true,
3498 };
3499 
3500 /* Improve power consumption for IN4 DC measurement mode */
3501 static const struct reg_default wm8962_dc_measure[] = {
3502         { 0xfd, 0x1 },
3503         { 0xcc, 0x40 },
3504         { 0xfd, 0 },
3505 };
3506 
3507 static const struct regmap_config wm8962_regmap = {
3508         .reg_bits = 16,
3509         .val_bits = 16,
3510 
3511         .max_register = WM8962_MAX_REGISTER,
3512         .reg_defaults = wm8962_reg,
3513         .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3514         .volatile_reg = wm8962_volatile_register,
3515         .readable_reg = wm8962_readable_register,
3516         .cache_type = REGCACHE_RBTREE,
3517 };
3518 
3519 static int wm8962_set_pdata_from_of(struct i2c_client *i2c,
3520                                     struct wm8962_pdata *pdata)
3521 {
3522         const struct device_node *np = i2c->dev.of_node;
3523         u32 val32;
3524         int i;
3525 
3526         if (of_property_read_bool(np, "spk-mono"))
3527                 pdata->spk_mono = true;
3528 
3529         if (of_property_read_u32(np, "mic-cfg", &val32) >= 0)
3530                 pdata->mic_cfg = val32;
3531 
3532         if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init,
3533                                        ARRAY_SIZE(pdata->gpio_init)) >= 0)
3534                 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) {
3535                         /*
3536                          * The range of GPIO register value is [0x0, 0xffff]
3537                          * While the default value of each register is 0x0
3538                          * Any other value will be regarded as default value
3539                          */
3540                         if (pdata->gpio_init[i] > 0xffff)
3541                                 pdata->gpio_init[i] = 0x0;
3542                 }
3543 
3544         pdata->mclk = devm_clk_get(&i2c->dev, NULL);
3545 
3546         return 0;
3547 }
3548 
3549 static int wm8962_i2c_probe(struct i2c_client *i2c,
3550                             const struct i2c_device_id *id)
3551 {
3552         struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
3553         struct wm8962_priv *wm8962;
3554         unsigned int reg;
3555         int ret, i, irq_pol, trigger;
3556 
3557         wm8962 = devm_kzalloc(&i2c->dev, sizeof(*wm8962), GFP_KERNEL);
3558         if (wm8962 == NULL)
3559                 return -ENOMEM;
3560 
3561         mutex_init(&wm8962->dsp2_ena_lock);
3562 
3563         i2c_set_clientdata(i2c, wm8962);
3564 
3565         INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3566         init_completion(&wm8962->fll_lock);
3567         wm8962->irq = i2c->irq;
3568 
3569         /* If platform data was supplied, update the default data in priv */
3570         if (pdata) {
3571                 memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata));
3572         } else if (i2c->dev.of_node) {
3573                 ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata);
3574                 if (ret != 0)
3575                         return ret;
3576         }
3577 
3578         /* Mark the mclk pointer to NULL if no mclk assigned */
3579         if (IS_ERR(wm8962->pdata.mclk)) {
3580                 /* But do not ignore the request for probe defer */
3581                 if (PTR_ERR(wm8962->pdata.mclk) == -EPROBE_DEFER)
3582                         return -EPROBE_DEFER;
3583                 wm8962->pdata.mclk = NULL;
3584         }
3585 
3586         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3587                 wm8962->supplies[i].supply = wm8962_supply_names[i];
3588 
3589         ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3590                                  wm8962->supplies);
3591         if (ret != 0) {
3592                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3593                 goto err;
3594         }
3595 
3596         ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3597                                     wm8962->supplies);
3598         if (ret != 0) {
3599                 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3600                 return ret;
3601         }
3602 
3603         wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap);
3604         if (IS_ERR(wm8962->regmap)) {
3605                 ret = PTR_ERR(wm8962->regmap);
3606                 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3607                 goto err_enable;
3608         }
3609 
3610         /*
3611          * We haven't marked the chip revision as volatile due to
3612          * sharing a register with the right input volume; explicitly
3613          * bypass the cache to read it.
3614          */
3615         regcache_cache_bypass(wm8962->regmap, true);
3616 
3617         ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg);
3618         if (ret < 0) {
3619                 dev_err(&i2c->dev, "Failed to read ID register\n");
3620                 goto err_enable;
3621         }
3622         if (reg != 0x6243) {
3623                 dev_err(&i2c->dev,
3624                         "Device is not a WM8962, ID %x != 0x6243\n", reg);
3625                 ret = -EINVAL;
3626                 goto err_enable;
3627         }
3628 
3629         ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg);
3630         if (ret < 0) {
3631                 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3632                         ret);
3633                 goto err_enable;
3634         }
3635 
3636         dev_info(&i2c->dev, "customer id %x revision %c\n",
3637                  (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3638                  ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3639                  + 'A');
3640 
3641         regcache_cache_bypass(wm8962->regmap, false);
3642 
3643         ret = wm8962_reset(wm8962);
3644         if (ret < 0) {
3645                 dev_err(&i2c->dev, "Failed to issue reset\n");
3646                 goto err_enable;
3647         }
3648 
3649         /* SYSCLK defaults to on; make sure it is off so we can safely
3650          * write to registers if the device is declocked.
3651          */
3652         regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3653                            WM8962_SYSCLK_ENA, 0);
3654 
3655         /* Ensure we have soft control over all registers */
3656         regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3657                            WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3658 
3659         /* Ensure that the oscillator and PLLs are disabled */
3660         regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3661                            WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3662                            0);
3663 
3664         /* Apply static configuration for GPIOs */
3665         for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++)
3666                 if (wm8962->pdata.gpio_init[i]) {
3667                         wm8962_set_gpio_mode(wm8962, i + 1);
3668                         regmap_write(wm8962->regmap, 0x200 + i,
3669                                      wm8962->pdata.gpio_init[i] & 0xffff);
3670                 }
3671 
3672 
3673         /* Put the speakers into mono mode? */
3674         if (wm8962->pdata.spk_mono)
3675                 regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2,
3676                                    WM8962_SPK_MONO_MASK, WM8962_SPK_MONO);
3677 
3678         /* Micbias setup, detection enable and detection
3679          * threasholds. */
3680         if (wm8962->pdata.mic_cfg)
3681                 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3682                                    WM8962_MICDET_ENA |
3683                                    WM8962_MICDET_THR_MASK |
3684                                    WM8962_MICSHORT_THR_MASK |
3685                                    WM8962_MICBIAS_LVL,
3686                                    wm8962->pdata.mic_cfg);
3687 
3688         /* Latch volume update bits */
3689         regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME,
3690                            WM8962_IN_VU, WM8962_IN_VU);
3691         regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME,
3692                            WM8962_IN_VU, WM8962_IN_VU);
3693         regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME,
3694                            WM8962_ADC_VU, WM8962_ADC_VU);
3695         regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME,
3696                            WM8962_ADC_VU, WM8962_ADC_VU);
3697         regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME,
3698                            WM8962_DAC_VU, WM8962_DAC_VU);
3699         regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME,
3700                            WM8962_DAC_VU, WM8962_DAC_VU);
3701         regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME,
3702                            WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3703         regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME,
3704                            WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3705         regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME,
3706                            WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3707         regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME,
3708                            WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3709 
3710         /* Stereo control for EQ */
3711         regmap_update_bits(wm8962->regmap, WM8962_EQ1,
3712                            WM8962_EQ_SHARED_COEFF, 0);
3713 
3714         /* Don't debouce interrupts so we don't need SYSCLK */
3715         regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE,
3716                            WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3717                            WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3718                            0);
3719 
3720         if (wm8962->pdata.in4_dc_measure) {
3721                 ret = regmap_register_patch(wm8962->regmap,
3722                                             wm8962_dc_measure,
3723                                             ARRAY_SIZE(wm8962_dc_measure));
3724                 if (ret != 0)
3725                         dev_err(&i2c->dev,
3726                                 "Failed to configure for DC mesurement: %d\n",
3727                                 ret);
3728         }
3729 
3730         if (wm8962->irq) {
3731                 if (wm8962->pdata.irq_active_low) {
3732                         trigger = IRQF_TRIGGER_LOW;
3733                         irq_pol = WM8962_IRQ_POL;
3734                 } else {
3735                         trigger = IRQF_TRIGGER_HIGH;
3736                         irq_pol = 0;
3737                 }
3738 
3739                 regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL,
3740                                    WM8962_IRQ_POL, irq_pol);
3741 
3742                 ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL,
3743                                                 wm8962_irq,
3744                                                 trigger | IRQF_ONESHOT,
3745                                                 "wm8962", &i2c->dev);
3746                 if (ret != 0) {
3747                         dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
3748                                 wm8962->irq, ret);
3749                         wm8962->irq = 0;
3750                         /* Non-fatal */
3751                 } else {
3752                         /* Enable some IRQs by default */
3753                         regmap_update_bits(wm8962->regmap,
3754                                            WM8962_INTERRUPT_STATUS_2_MASK,
3755                                            WM8962_FLL_LOCK_EINT |
3756                                            WM8962_TEMP_SHUT_EINT |
3757                                            WM8962_FIFOS_ERR_EINT, 0);
3758                 }
3759         }
3760 
3761         pm_runtime_enable(&i2c->dev);
3762         pm_request_idle(&i2c->dev);
3763 
3764         ret = snd_soc_register_codec(&i2c->dev,
3765                                      &soc_codec_dev_wm8962, &wm8962_dai, 1);
3766         if (ret < 0)
3767                 goto err_enable;
3768 
3769         regcache_cache_only(wm8962->regmap, true);
3770 
3771         /* The drivers should power up as needed */
3772         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3773 
3774         return 0;
3775 
3776 err_enable:
3777         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3778 err:
3779         return ret;
3780 }
3781 
3782 static int wm8962_i2c_remove(struct i2c_client *client)
3783 {
3784         snd_soc_unregister_codec(&client->dev);
3785         return 0;
3786 }
3787 
3788 #ifdef CONFIG_PM
3789 static int wm8962_runtime_resume(struct device *dev)
3790 {
3791         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3792         int ret;
3793 
3794         ret = clk_prepare_enable(wm8962->pdata.mclk);
3795         if (ret) {
3796                 dev_err(dev, "Failed to enable MCLK: %d\n", ret);
3797                 return ret;
3798         }
3799 
3800         ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3801                                     wm8962->supplies);
3802         if (ret != 0) {
3803                 dev_err(dev,
3804                         "Failed to enable supplies: %d\n", ret);
3805                 return ret;
3806         }
3807 
3808         regcache_cache_only(wm8962->regmap, false);
3809 
3810         wm8962_reset(wm8962);
3811 
3812         /* SYSCLK defaults to on; make sure it is off so we can safely
3813          * write to registers if the device is declocked.
3814          */
3815         regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3816                            WM8962_SYSCLK_ENA, 0);
3817 
3818         /* Ensure we have soft control over all registers */
3819         regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3820                            WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3821 
3822         /* Ensure that the oscillator and PLLs are disabled */
3823         regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3824                            WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3825                            0);
3826 
3827         regcache_sync(wm8962->regmap);
3828 
3829         regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3830                            WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
3831                            WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
3832 
3833         /* Bias enable at 2*5k (fast start-up) */
3834         regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3835                            WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK,
3836                            WM8962_BIAS_ENA | 0x180);
3837 
3838         msleep(5);
3839 
3840         return 0;
3841 }
3842 
3843 static int wm8962_runtime_suspend(struct device *dev)
3844 {
3845         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3846 
3847         regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3848                            WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3849 
3850         regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3851                            WM8962_STARTUP_BIAS_ENA |
3852                            WM8962_VMID_BUF_ENA, 0);
3853 
3854         regcache_cache_only(wm8962->regmap, true);
3855 
3856         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3857                                wm8962->supplies);
3858 
3859         clk_disable_unprepare(wm8962->pdata.mclk);
3860 
3861         return 0;
3862 }
3863 #endif
3864 
3865 static struct dev_pm_ops wm8962_pm = {
3866         SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3867 };
3868 
3869 static const struct i2c_device_id wm8962_i2c_id[] = {
3870         { "wm8962", 0 },
3871         { }
3872 };
3873 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3874 
3875 static const struct of_device_id wm8962_of_match[] = {
3876         { .compatible = "wlf,wm8962", },
3877         { }
3878 };
3879 MODULE_DEVICE_TABLE(of, wm8962_of_match);
3880 
3881 static struct i2c_driver wm8962_i2c_driver = {
3882         .driver = {
3883                 .name = "wm8962",
3884                 .owner = THIS_MODULE,
3885                 .of_match_table = wm8962_of_match,
3886                 .pm = &wm8962_pm,
3887         },
3888         .probe =    wm8962_i2c_probe,
3889         .remove =   wm8962_i2c_remove,
3890         .id_table = wm8962_i2c_id,
3891 };
3892 
3893 module_i2c_driver(wm8962_i2c_driver);
3894 
3895 MODULE_DESCRIPTION("ASoC WM8962 driver");
3896 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3897 MODULE_LICENSE("GPL");
3898 

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