Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/sound/soc/codecs/wm8903.c

  1 /*
  2  * wm8903.c  --  WM8903 ALSA SoC Audio driver
  3  *
  4  * Copyright 2008-12 Wolfson Microelectronics
  5  * Copyright 2011-2012 NVIDIA, Inc.
  6  *
  7  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  *
 13  * TODO:
 14  *  - TDM mode configuration.
 15  *  - Digital microphone support.
 16  */
 17 
 18 #include <linux/module.h>
 19 #include <linux/moduleparam.h>
 20 #include <linux/init.h>
 21 #include <linux/completion.h>
 22 #include <linux/delay.h>
 23 #include <linux/gpio.h>
 24 #include <linux/pm.h>
 25 #include <linux/i2c.h>
 26 #include <linux/regmap.h>
 27 #include <linux/slab.h>
 28 #include <linux/irq.h>
 29 #include <sound/core.h>
 30 #include <sound/jack.h>
 31 #include <sound/pcm.h>
 32 #include <sound/pcm_params.h>
 33 #include <sound/tlv.h>
 34 #include <sound/soc.h>
 35 #include <sound/initval.h>
 36 #include <sound/wm8903.h>
 37 #include <trace/events/asoc.h>
 38 
 39 #include "wm8903.h"
 40 
 41 /* Register defaults at reset */
 42 static const struct reg_default wm8903_reg_defaults[] = {
 43         { 4,  0x0018 },     /* R4   - Bias Control 0 */
 44         { 5,  0x0000 },     /* R5   - VMID Control 0 */
 45         { 6,  0x0000 },     /* R6   - Mic Bias Control 0 */
 46         { 8,  0x0001 },     /* R8   - Analogue DAC 0 */
 47         { 10, 0x0001 },     /* R10  - Analogue ADC 0 */
 48         { 12, 0x0000 },     /* R12  - Power Management 0 */
 49         { 13, 0x0000 },     /* R13  - Power Management 1 */
 50         { 14, 0x0000 },     /* R14  - Power Management 2 */
 51         { 15, 0x0000 },     /* R15  - Power Management 3 */
 52         { 16, 0x0000 },     /* R16  - Power Management 4 */
 53         { 17, 0x0000 },     /* R17  - Power Management 5 */
 54         { 18, 0x0000 },     /* R18  - Power Management 6 */
 55         { 20, 0x0400 },     /* R20  - Clock Rates 0 */
 56         { 21, 0x0D07 },     /* R21  - Clock Rates 1 */
 57         { 22, 0x0000 },     /* R22  - Clock Rates 2 */
 58         { 24, 0x0050 },     /* R24  - Audio Interface 0 */
 59         { 25, 0x0242 },     /* R25  - Audio Interface 1 */
 60         { 26, 0x0008 },     /* R26  - Audio Interface 2 */
 61         { 27, 0x0022 },     /* R27  - Audio Interface 3 */
 62         { 30, 0x00C0 },     /* R30  - DAC Digital Volume Left */
 63         { 31, 0x00C0 },     /* R31  - DAC Digital Volume Right */
 64         { 32, 0x0000 },     /* R32  - DAC Digital 0 */
 65         { 33, 0x0000 },     /* R33  - DAC Digital 1 */
 66         { 36, 0x00C0 },     /* R36  - ADC Digital Volume Left */
 67         { 37, 0x00C0 },     /* R37  - ADC Digital Volume Right */
 68         { 38, 0x0000 },     /* R38  - ADC Digital 0 */
 69         { 39, 0x0073 },     /* R39  - Digital Microphone 0 */
 70         { 40, 0x09BF },     /* R40  - DRC 0 */
 71         { 41, 0x3241 },     /* R41  - DRC 1 */
 72         { 42, 0x0020 },     /* R42  - DRC 2 */
 73         { 43, 0x0000 },     /* R43  - DRC 3 */
 74         { 44, 0x0085 },     /* R44  - Analogue Left Input 0 */
 75         { 45, 0x0085 },     /* R45  - Analogue Right Input 0 */
 76         { 46, 0x0044 },     /* R46  - Analogue Left Input 1 */
 77         { 47, 0x0044 },     /* R47  - Analogue Right Input 1 */
 78         { 50, 0x0008 },     /* R50  - Analogue Left Mix 0 */
 79         { 51, 0x0004 },     /* R51  - Analogue Right Mix 0 */
 80         { 52, 0x0000 },     /* R52  - Analogue Spk Mix Left 0 */
 81         { 53, 0x0000 },     /* R53  - Analogue Spk Mix Left 1 */
 82         { 54, 0x0000 },     /* R54  - Analogue Spk Mix Right 0 */
 83         { 55, 0x0000 },     /* R55  - Analogue Spk Mix Right 1 */
 84         { 57, 0x002D },     /* R57  - Analogue OUT1 Left */
 85         { 58, 0x002D },     /* R58  - Analogue OUT1 Right */
 86         { 59, 0x0039 },     /* R59  - Analogue OUT2 Left */
 87         { 60, 0x0039 },     /* R60  - Analogue OUT2 Right */
 88         { 62, 0x0139 },     /* R62  - Analogue OUT3 Left */
 89         { 63, 0x0139 },     /* R63  - Analogue OUT3 Right */
 90         { 64, 0x0000 },     /* R65  - Analogue SPK Output Control 0 */
 91         { 67, 0x0010 },     /* R67  - DC Servo 0 */
 92         { 69, 0x00A4 },     /* R69  - DC Servo 2 */
 93         { 90, 0x0000 },     /* R90  - Analogue HP 0 */
 94         { 94, 0x0000 },     /* R94  - Analogue Lineout 0 */
 95         { 98, 0x0000 },     /* R98  - Charge Pump 0 */
 96         { 104, 0x0000 },    /* R104 - Class W 0 */
 97         { 108, 0x0000 },    /* R108 - Write Sequencer 0 */
 98         { 109, 0x0000 },    /* R109 - Write Sequencer 1 */
 99         { 110, 0x0000 },    /* R110 - Write Sequencer 2 */
100         { 111, 0x0000 },    /* R111 - Write Sequencer 3 */
101         { 112, 0x0000 },    /* R112 - Write Sequencer 4 */
102         { 114, 0x0000 },    /* R114 - Control Interface */
103         { 116, 0x00A8 },    /* R116 - GPIO Control 1 */
104         { 117, 0x00A8 },    /* R117 - GPIO Control 2 */
105         { 118, 0x00A8 },    /* R118 - GPIO Control 3 */
106         { 119, 0x0220 },    /* R119 - GPIO Control 4 */
107         { 120, 0x01A0 },    /* R120 - GPIO Control 5 */
108         { 122, 0xFFFF },    /* R122 - Interrupt Status 1 Mask */
109         { 123, 0x0000 },    /* R123 - Interrupt Polarity 1 */
110         { 126, 0x0000 },    /* R126 - Interrupt Control */
111         { 129, 0x0000 },    /* R129 - Control Interface Test 1 */
112         { 149, 0x6810 },    /* R149 - Charge Pump Test 1 */
113         { 164, 0x0028 },    /* R164 - Clock Rate Test 4 */
114         { 172, 0x0000 },    /* R172 - Analogue Output Bias 0 */
115 };
116 
117 struct wm8903_priv {
118         struct wm8903_platform_data *pdata;
119         struct device *dev;
120         struct snd_soc_codec *codec;
121         struct regmap *regmap;
122 
123         int sysclk;
124         int irq;
125 
126         int fs;
127         int deemph;
128 
129         int dcs_pending;
130         int dcs_cache[4];
131 
132         /* Reference count */
133         int class_w_users;
134 
135         struct snd_soc_jack *mic_jack;
136         int mic_det;
137         int mic_short;
138         int mic_last_report;
139         int mic_delay;
140 
141 #ifdef CONFIG_GPIOLIB
142         struct gpio_chip gpio_chip;
143 #endif
144 };
145 
146 static bool wm8903_readable_register(struct device *dev, unsigned int reg)
147 {
148         switch (reg) {
149         case WM8903_SW_RESET_AND_ID:
150         case WM8903_REVISION_NUMBER:
151         case WM8903_BIAS_CONTROL_0:
152         case WM8903_VMID_CONTROL_0:
153         case WM8903_MIC_BIAS_CONTROL_0:
154         case WM8903_ANALOGUE_DAC_0:
155         case WM8903_ANALOGUE_ADC_0:
156         case WM8903_POWER_MANAGEMENT_0:
157         case WM8903_POWER_MANAGEMENT_1:
158         case WM8903_POWER_MANAGEMENT_2:
159         case WM8903_POWER_MANAGEMENT_3:
160         case WM8903_POWER_MANAGEMENT_4:
161         case WM8903_POWER_MANAGEMENT_5:
162         case WM8903_POWER_MANAGEMENT_6:
163         case WM8903_CLOCK_RATES_0:
164         case WM8903_CLOCK_RATES_1:
165         case WM8903_CLOCK_RATES_2:
166         case WM8903_AUDIO_INTERFACE_0:
167         case WM8903_AUDIO_INTERFACE_1:
168         case WM8903_AUDIO_INTERFACE_2:
169         case WM8903_AUDIO_INTERFACE_3:
170         case WM8903_DAC_DIGITAL_VOLUME_LEFT:
171         case WM8903_DAC_DIGITAL_VOLUME_RIGHT:
172         case WM8903_DAC_DIGITAL_0:
173         case WM8903_DAC_DIGITAL_1:
174         case WM8903_ADC_DIGITAL_VOLUME_LEFT:
175         case WM8903_ADC_DIGITAL_VOLUME_RIGHT:
176         case WM8903_ADC_DIGITAL_0:
177         case WM8903_DIGITAL_MICROPHONE_0:
178         case WM8903_DRC_0:
179         case WM8903_DRC_1:
180         case WM8903_DRC_2:
181         case WM8903_DRC_3:
182         case WM8903_ANALOGUE_LEFT_INPUT_0:
183         case WM8903_ANALOGUE_RIGHT_INPUT_0:
184         case WM8903_ANALOGUE_LEFT_INPUT_1:
185         case WM8903_ANALOGUE_RIGHT_INPUT_1:
186         case WM8903_ANALOGUE_LEFT_MIX_0:
187         case WM8903_ANALOGUE_RIGHT_MIX_0:
188         case WM8903_ANALOGUE_SPK_MIX_LEFT_0:
189         case WM8903_ANALOGUE_SPK_MIX_LEFT_1:
190         case WM8903_ANALOGUE_SPK_MIX_RIGHT_0:
191         case WM8903_ANALOGUE_SPK_MIX_RIGHT_1:
192         case WM8903_ANALOGUE_OUT1_LEFT:
193         case WM8903_ANALOGUE_OUT1_RIGHT:
194         case WM8903_ANALOGUE_OUT2_LEFT:
195         case WM8903_ANALOGUE_OUT2_RIGHT:
196         case WM8903_ANALOGUE_OUT3_LEFT:
197         case WM8903_ANALOGUE_OUT3_RIGHT:
198         case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0:
199         case WM8903_DC_SERVO_0:
200         case WM8903_DC_SERVO_2:
201         case WM8903_DC_SERVO_READBACK_1:
202         case WM8903_DC_SERVO_READBACK_2:
203         case WM8903_DC_SERVO_READBACK_3:
204         case WM8903_DC_SERVO_READBACK_4:
205         case WM8903_ANALOGUE_HP_0:
206         case WM8903_ANALOGUE_LINEOUT_0:
207         case WM8903_CHARGE_PUMP_0:
208         case WM8903_CLASS_W_0:
209         case WM8903_WRITE_SEQUENCER_0:
210         case WM8903_WRITE_SEQUENCER_1:
211         case WM8903_WRITE_SEQUENCER_2:
212         case WM8903_WRITE_SEQUENCER_3:
213         case WM8903_WRITE_SEQUENCER_4:
214         case WM8903_CONTROL_INTERFACE:
215         case WM8903_GPIO_CONTROL_1:
216         case WM8903_GPIO_CONTROL_2:
217         case WM8903_GPIO_CONTROL_3:
218         case WM8903_GPIO_CONTROL_4:
219         case WM8903_GPIO_CONTROL_5:
220         case WM8903_INTERRUPT_STATUS_1:
221         case WM8903_INTERRUPT_STATUS_1_MASK:
222         case WM8903_INTERRUPT_POLARITY_1:
223         case WM8903_INTERRUPT_CONTROL:
224         case WM8903_CLOCK_RATE_TEST_4:
225         case WM8903_ANALOGUE_OUTPUT_BIAS_0:
226                 return true;
227         default:
228                 return false;
229         }
230 }
231 
232 static bool wm8903_volatile_register(struct device *dev, unsigned int reg)
233 {
234         switch (reg) {
235         case WM8903_SW_RESET_AND_ID:
236         case WM8903_REVISION_NUMBER:
237         case WM8903_INTERRUPT_STATUS_1:
238         case WM8903_WRITE_SEQUENCER_4:
239         case WM8903_DC_SERVO_READBACK_1:
240         case WM8903_DC_SERVO_READBACK_2:
241         case WM8903_DC_SERVO_READBACK_3:
242         case WM8903_DC_SERVO_READBACK_4:
243                 return 1;
244 
245         default:
246                 return 0;
247         }
248 }
249 
250 static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
251                            struct snd_kcontrol *kcontrol, int event)
252 {
253         WARN_ON(event != SND_SOC_DAPM_POST_PMU);
254         mdelay(4);
255 
256         return 0;
257 }
258 
259 static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
260                             struct snd_kcontrol *kcontrol, int event)
261 {
262         struct snd_soc_codec *codec = w->codec;
263         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
264 
265         switch (event) {
266         case SND_SOC_DAPM_POST_PMU:
267                 wm8903->dcs_pending |= 1 << w->shift;
268                 break;
269         case SND_SOC_DAPM_PRE_PMD:
270                 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
271                                     1 << w->shift, 0);
272                 break;
273         }
274 
275         return 0;
276 }
277 
278 #define WM8903_DCS_MODE_WRITE_STOP 0
279 #define WM8903_DCS_MODE_START_STOP 2
280 
281 static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
282                                 enum snd_soc_dapm_type event, int subseq)
283 {
284         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
285         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
286         int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
287         int i, val;
288 
289         /* Complete any pending DC servo starts */
290         if (wm8903->dcs_pending) {
291                 dev_dbg(codec->dev, "Starting DC servo for %x\n",
292                         wm8903->dcs_pending);
293 
294                 /* If we've no cached values then we need to do startup */
295                 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
296                         if (!(wm8903->dcs_pending & (1 << i)))
297                                 continue;
298 
299                         if (wm8903->dcs_cache[i]) {
300                                 dev_dbg(codec->dev,
301                                         "Restore DC servo %d value %x\n",
302                                         3 - i, wm8903->dcs_cache[i]);
303 
304                                 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
305                                               wm8903->dcs_cache[i] & 0xff);
306                         } else {
307                                 dev_dbg(codec->dev,
308                                         "Calibrate DC servo %d\n", 3 - i);
309                                 dcs_mode = WM8903_DCS_MODE_START_STOP;
310                         }
311                 }
312 
313                 /* Don't trust the cache for analogue */
314                 if (wm8903->class_w_users)
315                         dcs_mode = WM8903_DCS_MODE_START_STOP;
316 
317                 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
318                                     WM8903_DCS_MODE_MASK, dcs_mode);
319 
320                 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
321                                     WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
322 
323                 switch (dcs_mode) {
324                 case WM8903_DCS_MODE_WRITE_STOP:
325                         break;
326 
327                 case WM8903_DCS_MODE_START_STOP:
328                         msleep(270);
329 
330                         /* Cache the measured offsets for digital */
331                         if (wm8903->class_w_users)
332                                 break;
333 
334                         for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
335                                 if (!(wm8903->dcs_pending & (1 << i)))
336                                         continue;
337 
338                                 val = snd_soc_read(codec,
339                                                    WM8903_DC_SERVO_READBACK_1 + i);
340                                 dev_dbg(codec->dev, "DC servo %d: %x\n",
341                                         3 - i, val);
342                                 wm8903->dcs_cache[i] = val;
343                         }
344                         break;
345 
346                 default:
347                         pr_warn("DCS mode %d delay not set\n", dcs_mode);
348                         break;
349                 }
350 
351                 wm8903->dcs_pending = 0;
352         }
353 }
354 
355 /*
356  * When used with DAC outputs only the WM8903 charge pump supports
357  * operation in class W mode, providing very low power consumption
358  * when used with digital sources.  Enable and disable this mode
359  * automatically depending on the mixer configuration.
360  *
361  * All the relevant controls are simple switches.
362  */
363 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
364                               struct snd_ctl_elem_value *ucontrol)
365 {
366         struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
367         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
368         u16 reg;
369         int ret;
370 
371         reg = snd_soc_read(codec, WM8903_CLASS_W_0);
372 
373         /* Turn it off if we're about to enable bypass */
374         if (ucontrol->value.integer.value[0]) {
375                 if (wm8903->class_w_users == 0) {
376                         dev_dbg(codec->dev, "Disabling Class W\n");
377                         snd_soc_write(codec, WM8903_CLASS_W_0, reg &
378                                      ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
379                 }
380                 wm8903->class_w_users++;
381         }
382 
383         /* Implement the change */
384         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
385 
386         /* If we've just disabled the last bypass path turn Class W on */
387         if (!ucontrol->value.integer.value[0]) {
388                 if (wm8903->class_w_users == 1) {
389                         dev_dbg(codec->dev, "Enabling Class W\n");
390                         snd_soc_write(codec, WM8903_CLASS_W_0, reg |
391                                      WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
392                 }
393                 wm8903->class_w_users--;
394         }
395 
396         dev_dbg(codec->dev, "Bypass use count now %d\n",
397                 wm8903->class_w_users);
398 
399         return ret;
400 }
401 
402 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
403         SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
404                 snd_soc_dapm_get_volsw, wm8903_class_w_put)
405 
406 
407 static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
408 
409 static int wm8903_set_deemph(struct snd_soc_codec *codec)
410 {
411         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
412         int val, i, best;
413 
414         /* If we're using deemphasis select the nearest available sample
415          * rate.
416          */
417         if (wm8903->deemph) {
418                 best = 1;
419                 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
420                         if (abs(wm8903_deemph[i] - wm8903->fs) <
421                             abs(wm8903_deemph[best] - wm8903->fs))
422                                 best = i;
423                 }
424 
425                 val = best << WM8903_DEEMPH_SHIFT;
426         } else {
427                 best = 0;
428                 val = 0;
429         }
430 
431         dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
432                 best, wm8903_deemph[best]);
433 
434         return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
435                                    WM8903_DEEMPH_MASK, val);
436 }
437 
438 static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
439                              struct snd_ctl_elem_value *ucontrol)
440 {
441         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
442         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
443 
444         ucontrol->value.enumerated.item[0] = wm8903->deemph;
445 
446         return 0;
447 }
448 
449 static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
450                              struct snd_ctl_elem_value *ucontrol)
451 {
452         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
453         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
454         int deemph = ucontrol->value.enumerated.item[0];
455         int ret = 0;
456 
457         if (deemph > 1)
458                 return -EINVAL;
459 
460         mutex_lock(&codec->mutex);
461         if (wm8903->deemph != deemph) {
462                 wm8903->deemph = deemph;
463 
464                 wm8903_set_deemph(codec);
465 
466                 ret = 1;
467         }
468         mutex_unlock(&codec->mutex);
469 
470         return ret;
471 }
472 
473 /* ALSA can only do steps of .01dB */
474 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
475 
476 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
477 
478 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
479 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
480 
481 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
482 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
483 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
484 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
485 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
486 
487 static const char *hpf_mode_text[] = {
488         "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
489 };
490 
491 static SOC_ENUM_SINGLE_DECL(hpf_mode,
492                             WM8903_ADC_DIGITAL_0, 5, hpf_mode_text);
493 
494 static const char *osr_text[] = {
495         "Low power", "High performance"
496 };
497 
498 static SOC_ENUM_SINGLE_DECL(adc_osr,
499                             WM8903_ANALOGUE_ADC_0, 0, osr_text);
500 
501 static SOC_ENUM_SINGLE_DECL(dac_osr,
502                             WM8903_DAC_DIGITAL_1, 0, osr_text);
503 
504 static const char *drc_slope_text[] = {
505         "1", "1/2", "1/4", "1/8", "1/16", ""
506 };
507 
508 static SOC_ENUM_SINGLE_DECL(drc_slope_r0,
509                             WM8903_DRC_2, 3, drc_slope_text);
510 
511 static SOC_ENUM_SINGLE_DECL(drc_slope_r1,
512                             WM8903_DRC_2, 0, drc_slope_text);
513 
514 static const char *drc_attack_text[] = {
515         "instantaneous",
516         "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
517         "46.4ms", "92.8ms", "185.6ms"
518 };
519 
520 static SOC_ENUM_SINGLE_DECL(drc_attack,
521                             WM8903_DRC_1, 12, drc_attack_text);
522 
523 static const char *drc_decay_text[] = {
524         "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
525         "23.87s", "47.56s"
526 };
527 
528 static SOC_ENUM_SINGLE_DECL(drc_decay,
529                             WM8903_DRC_1, 8, drc_decay_text);
530 
531 static const char *drc_ff_delay_text[] = {
532         "5 samples", "9 samples"
533 };
534 
535 static SOC_ENUM_SINGLE_DECL(drc_ff_delay,
536                             WM8903_DRC_0, 5, drc_ff_delay_text);
537 
538 static const char *drc_qr_decay_text[] = {
539         "0.725ms", "1.45ms", "5.8ms"
540 };
541 
542 static SOC_ENUM_SINGLE_DECL(drc_qr_decay,
543                             WM8903_DRC_1, 4, drc_qr_decay_text);
544 
545 static const char *drc_smoothing_text[] = {
546         "Low", "Medium", "High"
547 };
548 
549 static SOC_ENUM_SINGLE_DECL(drc_smoothing,
550                             WM8903_DRC_0, 11, drc_smoothing_text);
551 
552 static const char *soft_mute_text[] = {
553         "Fast (fs/2)", "Slow (fs/32)"
554 };
555 
556 static SOC_ENUM_SINGLE_DECL(soft_mute,
557                             WM8903_DAC_DIGITAL_1, 10, soft_mute_text);
558 
559 static const char *mute_mode_text[] = {
560         "Hard", "Soft"
561 };
562 
563 static SOC_ENUM_SINGLE_DECL(mute_mode,
564                             WM8903_DAC_DIGITAL_1, 9, mute_mode_text);
565 
566 static const char *companding_text[] = {
567         "ulaw", "alaw"
568 };
569 
570 static SOC_ENUM_SINGLE_DECL(dac_companding,
571                             WM8903_AUDIO_INTERFACE_0, 0, companding_text);
572 
573 static SOC_ENUM_SINGLE_DECL(adc_companding,
574                             WM8903_AUDIO_INTERFACE_0, 2, companding_text);
575 
576 static const char *input_mode_text[] = {
577         "Single-Ended", "Differential Line", "Differential Mic"
578 };
579 
580 static SOC_ENUM_SINGLE_DECL(linput_mode_enum,
581                             WM8903_ANALOGUE_LEFT_INPUT_1, 0, input_mode_text);
582 
583 static SOC_ENUM_SINGLE_DECL(rinput_mode_enum,
584                             WM8903_ANALOGUE_RIGHT_INPUT_1, 0, input_mode_text);
585 
586 static const char *linput_mux_text[] = {
587         "IN1L", "IN2L", "IN3L"
588 };
589 
590 static SOC_ENUM_SINGLE_DECL(linput_enum,
591                             WM8903_ANALOGUE_LEFT_INPUT_1, 2, linput_mux_text);
592 
593 static SOC_ENUM_SINGLE_DECL(linput_inv_enum,
594                             WM8903_ANALOGUE_LEFT_INPUT_1, 4, linput_mux_text);
595 
596 static const char *rinput_mux_text[] = {
597         "IN1R", "IN2R", "IN3R"
598 };
599 
600 static SOC_ENUM_SINGLE_DECL(rinput_enum,
601                             WM8903_ANALOGUE_RIGHT_INPUT_1, 2, rinput_mux_text);
602 
603 static SOC_ENUM_SINGLE_DECL(rinput_inv_enum,
604                             WM8903_ANALOGUE_RIGHT_INPUT_1, 4, rinput_mux_text);
605 
606 
607 static const char *sidetone_text[] = {
608         "None", "Left", "Right"
609 };
610 
611 static SOC_ENUM_SINGLE_DECL(lsidetone_enum,
612                             WM8903_DAC_DIGITAL_0, 2, sidetone_text);
613 
614 static SOC_ENUM_SINGLE_DECL(rsidetone_enum,
615                             WM8903_DAC_DIGITAL_0, 0, sidetone_text);
616 
617 static const char *adcinput_text[] = {
618         "ADC", "DMIC"
619 };
620 
621 static SOC_ENUM_SINGLE_DECL(adcinput_enum,
622                             WM8903_CLOCK_RATE_TEST_4, 9, adcinput_text);
623 
624 static const char *aif_text[] = {
625         "Left", "Right"
626 };
627 
628 static SOC_ENUM_SINGLE_DECL(lcapture_enum,
629                             WM8903_AUDIO_INTERFACE_0, 7, aif_text);
630 
631 static SOC_ENUM_SINGLE_DECL(rcapture_enum,
632                             WM8903_AUDIO_INTERFACE_0, 6, aif_text);
633 
634 static SOC_ENUM_SINGLE_DECL(lplay_enum,
635                             WM8903_AUDIO_INTERFACE_0, 5, aif_text);
636 
637 static SOC_ENUM_SINGLE_DECL(rplay_enum,
638                             WM8903_AUDIO_INTERFACE_0, 4, aif_text);
639 
640 static const struct snd_kcontrol_new wm8903_snd_controls[] = {
641 
642 /* Input PGAs - No TLV since the scale depends on PGA mode */
643 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
644            7, 1, 1),
645 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
646            0, 31, 0),
647 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
648            6, 1, 0),
649 
650 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
651            7, 1, 1),
652 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
653            0, 31, 0),
654 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
655            6, 1, 0),
656 
657 /* ADCs */
658 SOC_ENUM("ADC OSR", adc_osr),
659 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
660 SOC_ENUM("HPF Mode", hpf_mode),
661 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
662 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
663 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
664 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
665                drc_tlv_thresh),
666 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
667 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
668 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
669 SOC_ENUM("DRC Attack Rate", drc_attack),
670 SOC_ENUM("DRC Decay Rate", drc_decay),
671 SOC_ENUM("DRC FF Delay", drc_ff_delay),
672 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
673 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
674 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
675 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
676 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
677 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
678 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
679 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
680 
681 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
682                  WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
683 SOC_ENUM("ADC Companding Mode", adc_companding),
684 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
685 
686 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
687                12, 0, digital_sidetone_tlv),
688 
689 /* DAC */
690 SOC_ENUM("DAC OSR", dac_osr),
691 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
692                  WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
693 SOC_ENUM("DAC Soft Mute Rate", soft_mute),
694 SOC_ENUM("DAC Mute Mode", mute_mode),
695 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
696 SOC_ENUM("DAC Companding Mode", dac_companding),
697 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
698 SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0, 9, 3, 0,
699                dac_boost_tlv),
700 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
701                     wm8903_get_deemph, wm8903_put_deemph),
702 
703 /* Headphones */
704 SOC_DOUBLE_R("Headphone Switch",
705              WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
706              8, 1, 1),
707 SOC_DOUBLE_R("Headphone ZC Switch",
708              WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
709              6, 1, 0),
710 SOC_DOUBLE_R_TLV("Headphone Volume",
711                  WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
712                  0, 63, 0, out_tlv),
713 
714 /* Line out */
715 SOC_DOUBLE_R("Line Out Switch",
716              WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
717              8, 1, 1),
718 SOC_DOUBLE_R("Line Out ZC Switch",
719              WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
720              6, 1, 0),
721 SOC_DOUBLE_R_TLV("Line Out Volume",
722                  WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
723                  0, 63, 0, out_tlv),
724 
725 /* Speaker */
726 SOC_DOUBLE_R("Speaker Switch",
727              WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
728 SOC_DOUBLE_R("Speaker ZC Switch",
729              WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
730 SOC_DOUBLE_R_TLV("Speaker Volume",
731                  WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
732                  0, 63, 0, out_tlv),
733 };
734 
735 static const struct snd_kcontrol_new linput_mode_mux =
736         SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
737 
738 static const struct snd_kcontrol_new rinput_mode_mux =
739         SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
740 
741 static const struct snd_kcontrol_new linput_mux =
742         SOC_DAPM_ENUM("Left Input Mux", linput_enum);
743 
744 static const struct snd_kcontrol_new linput_inv_mux =
745         SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
746 
747 static const struct snd_kcontrol_new rinput_mux =
748         SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
749 
750 static const struct snd_kcontrol_new rinput_inv_mux =
751         SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
752 
753 static const struct snd_kcontrol_new lsidetone_mux =
754         SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
755 
756 static const struct snd_kcontrol_new rsidetone_mux =
757         SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
758 
759 static const struct snd_kcontrol_new adcinput_mux =
760         SOC_DAPM_ENUM("ADC Input", adcinput_enum);
761 
762 static const struct snd_kcontrol_new lcapture_mux =
763         SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
764 
765 static const struct snd_kcontrol_new rcapture_mux =
766         SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
767 
768 static const struct snd_kcontrol_new lplay_mux =
769         SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
770 
771 static const struct snd_kcontrol_new rplay_mux =
772         SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
773 
774 static const struct snd_kcontrol_new left_output_mixer[] = {
775 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
776 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
777 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
778 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
779 };
780 
781 static const struct snd_kcontrol_new right_output_mixer[] = {
782 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
783 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
784 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
785 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
786 };
787 
788 static const struct snd_kcontrol_new left_speaker_mixer[] = {
789 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
790 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
791 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
792 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
793                 0, 1, 0),
794 };
795 
796 static const struct snd_kcontrol_new right_speaker_mixer[] = {
797 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
798 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
799 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
800                 1, 1, 0),
801 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
802                 0, 1, 0),
803 };
804 
805 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
806 SND_SOC_DAPM_INPUT("IN1L"),
807 SND_SOC_DAPM_INPUT("IN1R"),
808 SND_SOC_DAPM_INPUT("IN2L"),
809 SND_SOC_DAPM_INPUT("IN2R"),
810 SND_SOC_DAPM_INPUT("IN3L"),
811 SND_SOC_DAPM_INPUT("IN3R"),
812 SND_SOC_DAPM_INPUT("DMICDAT"),
813 
814 SND_SOC_DAPM_OUTPUT("HPOUTL"),
815 SND_SOC_DAPM_OUTPUT("HPOUTR"),
816 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
817 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
818 SND_SOC_DAPM_OUTPUT("LOP"),
819 SND_SOC_DAPM_OUTPUT("LON"),
820 SND_SOC_DAPM_OUTPUT("ROP"),
821 SND_SOC_DAPM_OUTPUT("RON"),
822 
823 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
824 
825 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
826 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
827                  &linput_inv_mux),
828 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
829 
830 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
831 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
832                  &rinput_inv_mux),
833 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
834 
835 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
836 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
837 
838 SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
839 SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
840 
841 SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
842 SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
843 
844 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
845 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
846 
847 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
848 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
849 
850 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
851 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
852 
853 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
854 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
855 
856 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
857 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
858 
859 SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
860 SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
861 
862 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
863                    left_output_mixer, ARRAY_SIZE(left_output_mixer)),
864 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
865                    right_output_mixer, ARRAY_SIZE(right_output_mixer)),
866 
867 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
868                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
869 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
870                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
871 
872 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
873                    1, 0, NULL, 0),
874 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
875                    0, 0, NULL, 0),
876 
877 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
878                    NULL, 0),
879 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
880                    NULL, 0),
881 
882 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
883 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
884 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
885 SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
886 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
887 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
888 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
889 SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
890 
891 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
892                    NULL, 0),
893 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
894                    NULL, 0),
895 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
896                    NULL, 0),
897 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
898                    NULL, 0),
899 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
900                    NULL, 0),
901 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
902                    NULL, 0),
903 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
904                    NULL, 0),
905 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
906                    NULL, 0),
907 
908 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
909 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
910                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
911 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
912                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
913 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
914                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
915 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
916                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
917 
918 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
919                  NULL, 0),
920 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
921                  NULL, 0),
922 
923 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
924                     wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
925 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
926 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
927 };
928 
929 static const struct snd_soc_dapm_route wm8903_intercon[] = {
930 
931         { "CLK_DSP", NULL, "CLK_SYS" },
932         { "MICBIAS", NULL, "CLK_SYS" },
933         { "HPL_DCS", NULL, "CLK_SYS" },
934         { "HPR_DCS", NULL, "CLK_SYS" },
935         { "LINEOUTL_DCS", NULL, "CLK_SYS" },
936         { "LINEOUTR_DCS", NULL, "CLK_SYS" },
937 
938         { "Left Input Mux", "IN1L", "IN1L" },
939         { "Left Input Mux", "IN2L", "IN2L" },
940         { "Left Input Mux", "IN3L", "IN3L" },
941 
942         { "Left Input Inverting Mux", "IN1L", "IN1L" },
943         { "Left Input Inverting Mux", "IN2L", "IN2L" },
944         { "Left Input Inverting Mux", "IN3L", "IN3L" },
945 
946         { "Right Input Mux", "IN1R", "IN1R" },
947         { "Right Input Mux", "IN2R", "IN2R" },
948         { "Right Input Mux", "IN3R", "IN3R" },
949 
950         { "Right Input Inverting Mux", "IN1R", "IN1R" },
951         { "Right Input Inverting Mux", "IN2R", "IN2R" },
952         { "Right Input Inverting Mux", "IN3R", "IN3R" },
953 
954         { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
955         { "Left Input Mode Mux", "Differential Line",
956           "Left Input Mux" },
957         { "Left Input Mode Mux", "Differential Line",
958           "Left Input Inverting Mux" },
959         { "Left Input Mode Mux", "Differential Mic",
960           "Left Input Mux" },
961         { "Left Input Mode Mux", "Differential Mic",
962           "Left Input Inverting Mux" },
963 
964         { "Right Input Mode Mux", "Single-Ended",
965           "Right Input Inverting Mux" },
966         { "Right Input Mode Mux", "Differential Line",
967           "Right Input Mux" },
968         { "Right Input Mode Mux", "Differential Line",
969           "Right Input Inverting Mux" },
970         { "Right Input Mode Mux", "Differential Mic",
971           "Right Input Mux" },
972         { "Right Input Mode Mux", "Differential Mic",
973           "Right Input Inverting Mux" },
974 
975         { "Left Input PGA", NULL, "Left Input Mode Mux" },
976         { "Right Input PGA", NULL, "Right Input Mode Mux" },
977 
978         { "Left ADC Input", "ADC", "Left Input PGA" },
979         { "Left ADC Input", "DMIC", "DMICDAT" },
980         { "Right ADC Input", "ADC", "Right Input PGA" },
981         { "Right ADC Input", "DMIC", "DMICDAT" },
982 
983         { "Left Capture Mux", "Left", "ADCL" },
984         { "Left Capture Mux", "Right", "ADCR" },
985 
986         { "Right Capture Mux", "Left", "ADCL" },
987         { "Right Capture Mux", "Right", "ADCR" },
988 
989         { "AIFTXL", NULL, "Left Capture Mux" },
990         { "AIFTXR", NULL, "Right Capture Mux" },
991 
992         { "ADCL", NULL, "Left ADC Input" },
993         { "ADCL", NULL, "CLK_DSP" },
994         { "ADCR", NULL, "Right ADC Input" },
995         { "ADCR", NULL, "CLK_DSP" },
996 
997         { "Left Playback Mux", "Left", "AIFRXL" },
998         { "Left Playback Mux", "Right", "AIFRXR" },
999 
1000         { "Right Playback Mux", "Left", "AIFRXL" },
1001         { "Right Playback Mux", "Right", "AIFRXR" },
1002 
1003         { "DACL Sidetone", "Left", "ADCL" },
1004         { "DACL Sidetone", "Right", "ADCR" },
1005         { "DACR Sidetone", "Left", "ADCL" },
1006         { "DACR Sidetone", "Right", "ADCR" },
1007 
1008         { "DACL", NULL, "Left Playback Mux" },
1009         { "DACL", NULL, "DACL Sidetone" },
1010         { "DACL", NULL, "CLK_DSP" },
1011 
1012         { "DACR", NULL, "Right Playback Mux" },
1013         { "DACR", NULL, "DACR Sidetone" },
1014         { "DACR", NULL, "CLK_DSP" },
1015 
1016         { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1017         { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1018         { "Left Output Mixer", "DACL Switch", "DACL" },
1019         { "Left Output Mixer", "DACR Switch", "DACR" },
1020 
1021         { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1022         { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1023         { "Right Output Mixer", "DACL Switch", "DACL" },
1024         { "Right Output Mixer", "DACR Switch", "DACR" },
1025 
1026         { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1027         { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1028         { "Left Speaker Mixer", "DACL Switch", "DACL" },
1029         { "Left Speaker Mixer", "DACR Switch", "DACR" },
1030 
1031         { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1032         { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1033         { "Right Speaker Mixer", "DACL Switch", "DACL" },
1034         { "Right Speaker Mixer", "DACR Switch", "DACR" },
1035 
1036         { "Left Line Output PGA", NULL, "Left Output Mixer" },
1037         { "Right Line Output PGA", NULL, "Right Output Mixer" },
1038 
1039         { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1040         { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1041 
1042         { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1043         { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1044 
1045         { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1046         { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1047         { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1048         { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1049         { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1050         { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1051         { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1052         { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
1053 
1054         { "HPL_DCS", NULL, "DCS Master" },
1055         { "HPR_DCS", NULL, "DCS Master" },
1056         { "LINEOUTL_DCS", NULL, "DCS Master" },
1057         { "LINEOUTR_DCS", NULL, "DCS Master" },
1058 
1059         { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1060         { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1061         { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1062         { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1063 
1064         { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1065         { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1066         { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1067         { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1068 
1069         { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1070         { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1071         { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1072         { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1073 
1074         { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1075         { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1076         { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1077         { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
1078 
1079         { "LOP", NULL, "Left Speaker PGA" },
1080         { "LON", NULL, "Left Speaker PGA" },
1081 
1082         { "ROP", NULL, "Right Speaker PGA" },
1083         { "RON", NULL, "Right Speaker PGA" },
1084 
1085         { "Charge Pump", NULL, "CLK_DSP" },
1086 
1087         { "Left Headphone Output PGA", NULL, "Charge Pump" },
1088         { "Right Headphone Output PGA", NULL, "Charge Pump" },
1089         { "Left Line Output PGA", NULL, "Charge Pump" },
1090         { "Right Line Output PGA", NULL, "Charge Pump" },
1091 };
1092 
1093 static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1094                                  enum snd_soc_bias_level level)
1095 {
1096         switch (level) {
1097         case SND_SOC_BIAS_ON:
1098                 break;
1099 
1100         case SND_SOC_BIAS_PREPARE:
1101                 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1102                                     WM8903_VMID_RES_MASK,
1103                                     WM8903_VMID_RES_50K);
1104                 break;
1105 
1106         case SND_SOC_BIAS_STANDBY:
1107                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1108                         snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1109                                             WM8903_POBCTRL | WM8903_ISEL_MASK |
1110                                             WM8903_STARTUP_BIAS_ENA |
1111                                             WM8903_BIAS_ENA,
1112                                             WM8903_POBCTRL |
1113                                             (2 << WM8903_ISEL_SHIFT) |
1114                                             WM8903_STARTUP_BIAS_ENA);
1115 
1116                         snd_soc_update_bits(codec,
1117                                             WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1118                                             WM8903_SPK_DISCHARGE,
1119                                             WM8903_SPK_DISCHARGE);
1120 
1121                         msleep(33);
1122 
1123                         snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1124                                             WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1125                                             WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1126 
1127                         snd_soc_update_bits(codec,
1128                                             WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1129                                             WM8903_SPK_DISCHARGE, 0);
1130 
1131                         snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1132                                             WM8903_VMID_TIE_ENA |
1133                                             WM8903_BUFIO_ENA |
1134                                             WM8903_VMID_IO_ENA |
1135                                             WM8903_VMID_SOFT_MASK |
1136                                             WM8903_VMID_RES_MASK |
1137                                             WM8903_VMID_BUF_ENA,
1138                                             WM8903_VMID_TIE_ENA |
1139                                             WM8903_BUFIO_ENA |
1140                                             WM8903_VMID_IO_ENA |
1141                                             (2 << WM8903_VMID_SOFT_SHIFT) |
1142                                             WM8903_VMID_RES_250K |
1143                                             WM8903_VMID_BUF_ENA);
1144 
1145                         msleep(129);
1146 
1147                         snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1148                                             WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1149                                             0);
1150 
1151                         snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1152                                             WM8903_VMID_SOFT_MASK, 0);
1153 
1154                         snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1155                                             WM8903_VMID_RES_MASK,
1156                                             WM8903_VMID_RES_50K);
1157 
1158                         snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1159                                             WM8903_BIAS_ENA | WM8903_POBCTRL,
1160                                             WM8903_BIAS_ENA);
1161 
1162                         /* By default no bypass paths are enabled so
1163                          * enable Class W support.
1164                          */
1165                         dev_dbg(codec->dev, "Enabling Class W\n");
1166                         snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1167                                             WM8903_CP_DYN_FREQ |
1168                                             WM8903_CP_DYN_V,
1169                                             WM8903_CP_DYN_FREQ |
1170                                             WM8903_CP_DYN_V);
1171                 }
1172 
1173                 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1174                                     WM8903_VMID_RES_MASK,
1175                                     WM8903_VMID_RES_250K);
1176                 break;
1177 
1178         case SND_SOC_BIAS_OFF:
1179                 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1180                                     WM8903_BIAS_ENA, 0);
1181 
1182                 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1183                                     WM8903_VMID_SOFT_MASK,
1184                                     2 << WM8903_VMID_SOFT_SHIFT);
1185 
1186                 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1187                                     WM8903_VMID_BUF_ENA, 0);
1188 
1189                 msleep(290);
1190 
1191                 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1192                                     WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1193                                     WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1194                                     WM8903_VMID_SOFT_MASK |
1195                                     WM8903_VMID_BUF_ENA, 0);
1196 
1197                 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1198                                     WM8903_STARTUP_BIAS_ENA, 0);
1199                 break;
1200         }
1201 
1202         codec->dapm.bias_level = level;
1203 
1204         return 0;
1205 }
1206 
1207 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1208                                  int clk_id, unsigned int freq, int dir)
1209 {
1210         struct snd_soc_codec *codec = codec_dai->codec;
1211         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1212 
1213         wm8903->sysclk = freq;
1214 
1215         return 0;
1216 }
1217 
1218 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1219                               unsigned int fmt)
1220 {
1221         struct snd_soc_codec *codec = codec_dai->codec;
1222         u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1223 
1224         aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1225                   WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1226 
1227         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1228         case SND_SOC_DAIFMT_CBS_CFS:
1229                 break;
1230         case SND_SOC_DAIFMT_CBS_CFM:
1231                 aif1 |= WM8903_LRCLK_DIR;
1232                 break;
1233         case SND_SOC_DAIFMT_CBM_CFM:
1234                 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1235                 break;
1236         case SND_SOC_DAIFMT_CBM_CFS:
1237                 aif1 |= WM8903_BCLK_DIR;
1238                 break;
1239         default:
1240                 return -EINVAL;
1241         }
1242 
1243         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1244         case SND_SOC_DAIFMT_DSP_A:
1245                 aif1 |= 0x3;
1246                 break;
1247         case SND_SOC_DAIFMT_DSP_B:
1248                 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1249                 break;
1250         case SND_SOC_DAIFMT_I2S:
1251                 aif1 |= 0x2;
1252                 break;
1253         case SND_SOC_DAIFMT_RIGHT_J:
1254                 aif1 |= 0x1;
1255                 break;
1256         case SND_SOC_DAIFMT_LEFT_J:
1257                 break;
1258         default:
1259                 return -EINVAL;
1260         }
1261 
1262         /* Clock inversion */
1263         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1264         case SND_SOC_DAIFMT_DSP_A:
1265         case SND_SOC_DAIFMT_DSP_B:
1266                 /* frame inversion not valid for DSP modes */
1267                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1268                 case SND_SOC_DAIFMT_NB_NF:
1269                         break;
1270                 case SND_SOC_DAIFMT_IB_NF:
1271                         aif1 |= WM8903_AIF_BCLK_INV;
1272                         break;
1273                 default:
1274                         return -EINVAL;
1275                 }
1276                 break;
1277         case SND_SOC_DAIFMT_I2S:
1278         case SND_SOC_DAIFMT_RIGHT_J:
1279         case SND_SOC_DAIFMT_LEFT_J:
1280                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1281                 case SND_SOC_DAIFMT_NB_NF:
1282                         break;
1283                 case SND_SOC_DAIFMT_IB_IF:
1284                         aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1285                         break;
1286                 case SND_SOC_DAIFMT_IB_NF:
1287                         aif1 |= WM8903_AIF_BCLK_INV;
1288                         break;
1289                 case SND_SOC_DAIFMT_NB_IF:
1290                         aif1 |= WM8903_AIF_LRCLK_INV;
1291                         break;
1292                 default:
1293                         return -EINVAL;
1294                 }
1295                 break;
1296         default:
1297                 return -EINVAL;
1298         }
1299 
1300         snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1301 
1302         return 0;
1303 }
1304 
1305 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1306 {
1307         struct snd_soc_codec *codec = codec_dai->codec;
1308         u16 reg;
1309 
1310         reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1311 
1312         if (mute)
1313                 reg |= WM8903_DAC_MUTE;
1314         else
1315                 reg &= ~WM8903_DAC_MUTE;
1316 
1317         snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
1318 
1319         return 0;
1320 }
1321 
1322 /* Lookup table for CLK_SYS/fs ratio.  256fs or more is recommended
1323  * for optimal performance so we list the lower rates first and match
1324  * on the last match we find. */
1325 static struct {
1326         int div;
1327         int rate;
1328         int mode;
1329         int mclk_div;
1330 } clk_sys_ratios[] = {
1331         {   64, 0x0, 0x0, 1 },
1332         {   68, 0x0, 0x1, 1 },
1333         {  125, 0x0, 0x2, 1 },
1334         {  128, 0x1, 0x0, 1 },
1335         {  136, 0x1, 0x1, 1 },
1336         {  192, 0x2, 0x0, 1 },
1337         {  204, 0x2, 0x1, 1 },
1338 
1339         {   64, 0x0, 0x0, 2 },
1340         {   68, 0x0, 0x1, 2 },
1341         {  125, 0x0, 0x2, 2 },
1342         {  128, 0x1, 0x0, 2 },
1343         {  136, 0x1, 0x1, 2 },
1344         {  192, 0x2, 0x0, 2 },
1345         {  204, 0x2, 0x1, 2 },
1346 
1347         {  250, 0x2, 0x2, 1 },
1348         {  256, 0x3, 0x0, 1 },
1349         {  272, 0x3, 0x1, 1 },
1350         {  384, 0x4, 0x0, 1 },
1351         {  408, 0x4, 0x1, 1 },
1352         {  375, 0x4, 0x2, 1 },
1353         {  512, 0x5, 0x0, 1 },
1354         {  544, 0x5, 0x1, 1 },
1355         {  500, 0x5, 0x2, 1 },
1356         {  768, 0x6, 0x0, 1 },
1357         {  816, 0x6, 0x1, 1 },
1358         {  750, 0x6, 0x2, 1 },
1359         { 1024, 0x7, 0x0, 1 },
1360         { 1088, 0x7, 0x1, 1 },
1361         { 1000, 0x7, 0x2, 1 },
1362         { 1408, 0x8, 0x0, 1 },
1363         { 1496, 0x8, 0x1, 1 },
1364         { 1536, 0x9, 0x0, 1 },
1365         { 1632, 0x9, 0x1, 1 },
1366         { 1500, 0x9, 0x2, 1 },
1367 
1368         {  250, 0x2, 0x2, 2 },
1369         {  256, 0x3, 0x0, 2 },
1370         {  272, 0x3, 0x1, 2 },
1371         {  384, 0x4, 0x0, 2 },
1372         {  408, 0x4, 0x1, 2 },
1373         {  375, 0x4, 0x2, 2 },
1374         {  512, 0x5, 0x0, 2 },
1375         {  544, 0x5, 0x1, 2 },
1376         {  500, 0x5, 0x2, 2 },
1377         {  768, 0x6, 0x0, 2 },
1378         {  816, 0x6, 0x1, 2 },
1379         {  750, 0x6, 0x2, 2 },
1380         { 1024, 0x7, 0x0, 2 },
1381         { 1088, 0x7, 0x1, 2 },
1382         { 1000, 0x7, 0x2, 2 },
1383         { 1408, 0x8, 0x0, 2 },
1384         { 1496, 0x8, 0x1, 2 },
1385         { 1536, 0x9, 0x0, 2 },
1386         { 1632, 0x9, 0x1, 2 },
1387         { 1500, 0x9, 0x2, 2 },
1388 };
1389 
1390 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1391 static struct {
1392         int ratio;
1393         int div;
1394 } bclk_divs[] = {
1395         {  10,  0 },
1396         {  20,  2 },
1397         {  30,  3 },
1398         {  40,  4 },
1399         {  50,  5 },
1400         {  60,  7 },
1401         {  80,  8 },
1402         { 100,  9 },
1403         { 120, 11 },
1404         { 160, 12 },
1405         { 200, 13 },
1406         { 220, 14 },
1407         { 240, 15 },
1408         { 300, 17 },
1409         { 320, 18 },
1410         { 440, 19 },
1411         { 480, 20 },
1412 };
1413 
1414 /* Sample rates for DSP */
1415 static struct {
1416         int rate;
1417         int value;
1418 } sample_rates[] = {
1419         {  8000,  0 },
1420         { 11025,  1 },
1421         { 12000,  2 },
1422         { 16000,  3 },
1423         { 22050,  4 },
1424         { 24000,  5 },
1425         { 32000,  6 },
1426         { 44100,  7 },
1427         { 48000,  8 },
1428         { 88200,  9 },
1429         { 96000, 10 },
1430         { 0,      0 },
1431 };
1432 
1433 static int wm8903_hw_params(struct snd_pcm_substream *substream,
1434                             struct snd_pcm_hw_params *params,
1435                             struct snd_soc_dai *dai)
1436 {
1437         struct snd_soc_codec *codec = dai->codec;
1438         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1439         int fs = params_rate(params);
1440         int bclk;
1441         int bclk_div;
1442         int i;
1443         int dsp_config;
1444         int clk_config;
1445         int best_val;
1446         int cur_val;
1447         int clk_sys;
1448 
1449         u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1450         u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1451         u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1452         u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1453         u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1454         u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1455 
1456         /* Enable sloping stopband filter for low sample rates */
1457         if (fs <= 24000)
1458                 dac_digital1 |= WM8903_DAC_SB_FILT;
1459         else
1460                 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1461 
1462         /* Configure sample rate logic for DSP - choose nearest rate */
1463         dsp_config = 0;
1464         best_val = abs(sample_rates[dsp_config].rate - fs);
1465         for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1466                 cur_val = abs(sample_rates[i].rate - fs);
1467                 if (cur_val <= best_val) {
1468                         dsp_config = i;
1469                         best_val = cur_val;
1470                 }
1471         }
1472 
1473         dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1474         clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1475         clock1 |= sample_rates[dsp_config].value;
1476 
1477         aif1 &= ~WM8903_AIF_WL_MASK;
1478         bclk = 2 * fs;
1479         switch (params_width(params)) {
1480         case 16:
1481                 bclk *= 16;
1482                 break;
1483         case 20:
1484                 bclk *= 20;
1485                 aif1 |= 0x4;
1486                 break;
1487         case 24:
1488                 bclk *= 24;
1489                 aif1 |= 0x8;
1490                 break;
1491         case 32:
1492                 bclk *= 32;
1493                 aif1 |= 0xc;
1494                 break;
1495         default:
1496                 return -EINVAL;
1497         }
1498 
1499         dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1500                 wm8903->sysclk, fs);
1501 
1502         /* We may not have an MCLK which allows us to generate exactly
1503          * the clock we want, particularly with USB derived inputs, so
1504          * approximate.
1505          */
1506         clk_config = 0;
1507         best_val = abs((wm8903->sysclk /
1508                         (clk_sys_ratios[0].mclk_div *
1509                          clk_sys_ratios[0].div)) - fs);
1510         for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1511                 cur_val = abs((wm8903->sysclk /
1512                                (clk_sys_ratios[i].mclk_div *
1513                                 clk_sys_ratios[i].div)) - fs);
1514 
1515                 if (cur_val <= best_val) {
1516                         clk_config = i;
1517                         best_val = cur_val;
1518                 }
1519         }
1520 
1521         if (clk_sys_ratios[clk_config].mclk_div == 2) {
1522                 clock0 |= WM8903_MCLKDIV2;
1523                 clk_sys = wm8903->sysclk / 2;
1524         } else {
1525                 clock0 &= ~WM8903_MCLKDIV2;
1526                 clk_sys = wm8903->sysclk;
1527         }
1528 
1529         clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1530                     WM8903_CLK_SYS_MODE_MASK);
1531         clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1532         clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1533 
1534         dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1535                 clk_sys_ratios[clk_config].rate,
1536                 clk_sys_ratios[clk_config].mode,
1537                 clk_sys_ratios[clk_config].div);
1538 
1539         dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1540 
1541         /* We may not get quite the right frequency if using
1542          * approximate clocks so look for the closest match that is
1543          * higher than the target (we need to ensure that there enough
1544          * BCLKs to clock out the samples).
1545          */
1546         bclk_div = 0;
1547         best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1548         i = 1;
1549         while (i < ARRAY_SIZE(bclk_divs)) {
1550                 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1551                 if (cur_val < 0) /* BCLK table is sorted */
1552                         break;
1553                 bclk_div = i;
1554                 best_val = cur_val;
1555                 i++;
1556         }
1557 
1558         aif2 &= ~WM8903_BCLK_DIV_MASK;
1559         aif3 &= ~WM8903_LRCLK_RATE_MASK;
1560 
1561         dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1562                 bclk_divs[bclk_div].ratio / 10, bclk,
1563                 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1564 
1565         aif2 |= bclk_divs[bclk_div].div;
1566         aif3 |= bclk / fs;
1567 
1568         wm8903->fs = params_rate(params);
1569         wm8903_set_deemph(codec);
1570 
1571         snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1572         snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1573         snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1574         snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1575         snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1576         snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
1577 
1578         return 0;
1579 }
1580 
1581 /**
1582  * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1583  *
1584  * @codec:  WM8903 codec
1585  * @jack:   jack to report detection events on
1586  * @det:    value to report for presence detection
1587  * @shrt:   value to report for short detection
1588  *
1589  * Enable microphone detection via IRQ on the WM8903.  If GPIOs are
1590  * being used to bring out signals to the processor then only platform
1591  * data configuration is needed for WM8903 and processor GPIOs should
1592  * be configured using snd_soc_jack_add_gpios() instead.
1593  *
1594  * The current threasholds for detection should be configured using
1595  * micdet_cfg in the platform data.  Using this function will force on
1596  * the microphone bias for the device.
1597  */
1598 int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1599                       int det, int shrt)
1600 {
1601         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1602         int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
1603 
1604         dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1605                 det, shrt);
1606 
1607         /* Store the configuration */
1608         wm8903->mic_jack = jack;
1609         wm8903->mic_det = det;
1610         wm8903->mic_short = shrt;
1611 
1612         /* Enable interrupts we've got a report configured for */
1613         if (det)
1614                 irq_mask &= ~WM8903_MICDET_EINT;
1615         if (shrt)
1616                 irq_mask &= ~WM8903_MICSHRT_EINT;
1617 
1618         snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1619                             WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1620                             irq_mask);
1621 
1622         if (det || shrt) {
1623                 /* Enable mic detection, this may not have been set through
1624                  * platform data (eg, if the defaults are OK). */
1625                 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1626                                     WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1627                 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1628                                     WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1629         } else {
1630                 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1631                                     WM8903_MICDET_ENA, 0);
1632         }
1633 
1634         return 0;
1635 }
1636 EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1637 
1638 static irqreturn_t wm8903_irq(int irq, void *data)
1639 {
1640         struct wm8903_priv *wm8903 = data;
1641         int mic_report, ret;
1642         unsigned int int_val, mask, int_pol;
1643 
1644         ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1_MASK,
1645                           &mask);
1646         if (ret != 0) {
1647                 dev_err(wm8903->dev, "Failed to read IRQ mask: %d\n", ret);
1648                 return IRQ_NONE;
1649         }
1650 
1651         ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1, &int_val);
1652         if (ret != 0) {
1653                 dev_err(wm8903->dev, "Failed to read IRQ status: %d\n", ret);
1654                 return IRQ_NONE;
1655         }
1656 
1657         int_val &= ~mask;
1658 
1659         if (int_val & WM8903_WSEQ_BUSY_EINT) {
1660                 dev_warn(wm8903->dev, "Write sequencer done\n");
1661         }
1662 
1663         /*
1664          * The rest is microphone jack detection.  We need to manually
1665          * invert the polarity of the interrupt after each event - to
1666          * simplify the code keep track of the last state we reported
1667          * and just invert the relevant bits in both the report and
1668          * the polarity register.
1669          */
1670         mic_report = wm8903->mic_last_report;
1671         ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
1672                           &int_pol);
1673         if (ret != 0) {
1674                 dev_err(wm8903->dev, "Failed to read interrupt polarity: %d\n",
1675                         ret);
1676                 return IRQ_HANDLED;
1677         }
1678 
1679 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1680         if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1681                 trace_snd_soc_jack_irq(dev_name(wm8903->dev));
1682 #endif
1683 
1684         if (int_val & WM8903_MICSHRT_EINT) {
1685                 dev_dbg(wm8903->dev, "Microphone short (pol=%x)\n", int_pol);
1686 
1687                 mic_report ^= wm8903->mic_short;
1688                 int_pol ^= WM8903_MICSHRT_INV;
1689         }
1690 
1691         if (int_val & WM8903_MICDET_EINT) {
1692                 dev_dbg(wm8903->dev, "Microphone detect (pol=%x)\n", int_pol);
1693 
1694                 mic_report ^= wm8903->mic_det;
1695                 int_pol ^= WM8903_MICDET_INV;
1696 
1697                 msleep(wm8903->mic_delay);
1698         }
1699 
1700         regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
1701                            WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1702 
1703         snd_soc_jack_report(wm8903->mic_jack, mic_report,
1704                             wm8903->mic_short | wm8903->mic_det);
1705 
1706         wm8903->mic_last_report = mic_report;
1707 
1708         return IRQ_HANDLED;
1709 }
1710 
1711 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1712                                SNDRV_PCM_RATE_11025 |   \
1713                                SNDRV_PCM_RATE_16000 |   \
1714                                SNDRV_PCM_RATE_22050 |   \
1715                                SNDRV_PCM_RATE_32000 |   \
1716                                SNDRV_PCM_RATE_44100 |   \
1717                                SNDRV_PCM_RATE_48000 |   \
1718                                SNDRV_PCM_RATE_88200 |   \
1719                                SNDRV_PCM_RATE_96000)
1720 
1721 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1722                               SNDRV_PCM_RATE_11025 |    \
1723                               SNDRV_PCM_RATE_16000 |    \
1724                               SNDRV_PCM_RATE_22050 |    \
1725                               SNDRV_PCM_RATE_32000 |    \
1726                               SNDRV_PCM_RATE_44100 |    \
1727                               SNDRV_PCM_RATE_48000)
1728 
1729 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1730                         SNDRV_PCM_FMTBIT_S20_3LE |\
1731                         SNDRV_PCM_FMTBIT_S24_LE)
1732 
1733 static const struct snd_soc_dai_ops wm8903_dai_ops = {
1734         .hw_params      = wm8903_hw_params,
1735         .digital_mute   = wm8903_digital_mute,
1736         .set_fmt        = wm8903_set_dai_fmt,
1737         .set_sysclk     = wm8903_set_dai_sysclk,
1738 };
1739 
1740 static struct snd_soc_dai_driver wm8903_dai = {
1741         .name = "wm8903-hifi",
1742         .playback = {
1743                 .stream_name = "Playback",
1744                 .channels_min = 2,
1745                 .channels_max = 2,
1746                 .rates = WM8903_PLAYBACK_RATES,
1747                 .formats = WM8903_FORMATS,
1748         },
1749         .capture = {
1750                  .stream_name = "Capture",
1751                  .channels_min = 2,
1752                  .channels_max = 2,
1753                  .rates = WM8903_CAPTURE_RATES,
1754                  .formats = WM8903_FORMATS,
1755          },
1756         .ops = &wm8903_dai_ops,
1757         .symmetric_rates = 1,
1758 };
1759 
1760 static int wm8903_suspend(struct snd_soc_codec *codec)
1761 {
1762         wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1763 
1764         return 0;
1765 }
1766 
1767 static int wm8903_resume(struct snd_soc_codec *codec)
1768 {
1769         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1770 
1771         regcache_sync(wm8903->regmap);
1772 
1773         wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1774 
1775         return 0;
1776 }
1777 
1778 #ifdef CONFIG_GPIOLIB
1779 static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1780 {
1781         return container_of(chip, struct wm8903_priv, gpio_chip);
1782 }
1783 
1784 static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1785 {
1786         if (offset >= WM8903_NUM_GPIO)
1787                 return -EINVAL;
1788 
1789         return 0;
1790 }
1791 
1792 static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1793 {
1794         struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1795         unsigned int mask, val;
1796         int ret;
1797 
1798         mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1799         val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1800                 WM8903_GP1_DIR;
1801 
1802         ret = regmap_update_bits(wm8903->regmap,
1803                                  WM8903_GPIO_CONTROL_1 + offset, mask, val);
1804         if (ret < 0)
1805                 return ret;
1806 
1807         return 0;
1808 }
1809 
1810 static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1811 {
1812         struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1813         unsigned int reg;
1814 
1815         regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, &reg);
1816 
1817         return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1818 }
1819 
1820 static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1821                                      unsigned offset, int value)
1822 {
1823         struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1824         unsigned int mask, val;
1825         int ret;
1826 
1827         mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1828         val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1829                 (value << WM8903_GP2_LVL_SHIFT);
1830 
1831         ret = regmap_update_bits(wm8903->regmap,
1832                                  WM8903_GPIO_CONTROL_1 + offset, mask, val);
1833         if (ret < 0)
1834                 return ret;
1835 
1836         return 0;
1837 }
1838 
1839 static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1840 {
1841         struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1842 
1843         regmap_update_bits(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset,
1844                            WM8903_GP1_LVL_MASK,
1845                            !!value << WM8903_GP1_LVL_SHIFT);
1846 }
1847 
1848 static struct gpio_chip wm8903_template_chip = {
1849         .label                  = "wm8903",
1850         .owner                  = THIS_MODULE,
1851         .request                = wm8903_gpio_request,
1852         .direction_input        = wm8903_gpio_direction_in,
1853         .get                    = wm8903_gpio_get,
1854         .direction_output       = wm8903_gpio_direction_out,
1855         .set                    = wm8903_gpio_set,
1856         .can_sleep              = 1,
1857 };
1858 
1859 static void wm8903_init_gpio(struct wm8903_priv *wm8903)
1860 {
1861         struct wm8903_platform_data *pdata = wm8903->pdata;
1862         int ret;
1863 
1864         wm8903->gpio_chip = wm8903_template_chip;
1865         wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1866         wm8903->gpio_chip.dev = wm8903->dev;
1867 
1868         if (pdata->gpio_base)
1869                 wm8903->gpio_chip.base = pdata->gpio_base;
1870         else
1871                 wm8903->gpio_chip.base = -1;
1872 
1873         ret = gpiochip_add(&wm8903->gpio_chip);
1874         if (ret != 0)
1875                 dev_err(wm8903->dev, "Failed to add GPIOs: %d\n", ret);
1876 }
1877 
1878 static void wm8903_free_gpio(struct wm8903_priv *wm8903)
1879 {
1880         gpiochip_remove(&wm8903->gpio_chip);
1881 }
1882 #else
1883 static void wm8903_init_gpio(struct wm8903_priv *wm8903)
1884 {
1885 }
1886 
1887 static void wm8903_free_gpio(struct wm8903_priv *wm8903)
1888 {
1889 }
1890 #endif
1891 
1892 static int wm8903_probe(struct snd_soc_codec *codec)
1893 {
1894         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1895 
1896         wm8903->codec = codec;
1897 
1898         /* power on device */
1899         wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1900 
1901         return 0;
1902 }
1903 
1904 /* power down chip */
1905 static int wm8903_remove(struct snd_soc_codec *codec)
1906 {
1907         wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1908 
1909         return 0;
1910 }
1911 
1912 static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1913         .probe =        wm8903_probe,
1914         .remove =       wm8903_remove,
1915         .suspend =      wm8903_suspend,
1916         .resume =       wm8903_resume,
1917         .set_bias_level = wm8903_set_bias_level,
1918         .seq_notifier = wm8903_seq_notifier,
1919         .controls = wm8903_snd_controls,
1920         .num_controls = ARRAY_SIZE(wm8903_snd_controls),
1921         .dapm_widgets = wm8903_dapm_widgets,
1922         .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
1923         .dapm_routes = wm8903_intercon,
1924         .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
1925 };
1926 
1927 static const struct regmap_config wm8903_regmap = {
1928         .reg_bits = 8,
1929         .val_bits = 16,
1930 
1931         .max_register = WM8903_MAX_REGISTER,
1932         .volatile_reg = wm8903_volatile_register,
1933         .readable_reg = wm8903_readable_register,
1934 
1935         .cache_type = REGCACHE_RBTREE,
1936         .reg_defaults = wm8903_reg_defaults,
1937         .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults),
1938 };
1939 
1940 static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c,
1941                                         struct wm8903_platform_data *pdata)
1942 {
1943         struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
1944         if (!irq_data) {
1945                 dev_err(&i2c->dev, "Invalid IRQ: %d\n",
1946                         i2c->irq);
1947                 return -EINVAL;
1948         }
1949 
1950         switch (irqd_get_trigger_type(irq_data)) {
1951         case IRQ_TYPE_NONE:
1952         default:
1953                 /*
1954                 * We assume the controller imposes no restrictions,
1955                 * so we are able to select active-high
1956                 */
1957                 /* Fall-through */
1958         case IRQ_TYPE_LEVEL_HIGH:
1959                 pdata->irq_active_low = false;
1960                 break;
1961         case IRQ_TYPE_LEVEL_LOW:
1962                 pdata->irq_active_low = true;
1963                 break;
1964         }
1965 
1966         return 0;
1967 }
1968 
1969 static int wm8903_set_pdata_from_of(struct i2c_client *i2c,
1970                                     struct wm8903_platform_data *pdata)
1971 {
1972         const struct device_node *np = i2c->dev.of_node;
1973         u32 val32;
1974         int i;
1975 
1976         if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0)
1977                 pdata->micdet_cfg = val32;
1978 
1979         if (of_property_read_u32(np, "micdet-delay", &val32) >= 0)
1980                 pdata->micdet_delay = val32;
1981 
1982         if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg,
1983                                        ARRAY_SIZE(pdata->gpio_cfg)) >= 0) {
1984                 /*
1985                  * In device tree: 0 means "write 0",
1986                  * 0xffffffff means "don't touch".
1987                  *
1988                  * In platform data: 0 means "don't touch",
1989                  * 0x8000 means "write 0".
1990                  *
1991                  * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000.
1992                  *
1993                  *  Convert from DT to pdata representation here,
1994                  * so no other code needs to change.
1995                  */
1996                 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1997                         if (pdata->gpio_cfg[i] == 0) {
1998                                 pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO;
1999                         } else if (pdata->gpio_cfg[i] == 0xffffffff) {
2000                                 pdata->gpio_cfg[i] = 0;
2001                         } else if (pdata->gpio_cfg[i] > 0x7fff) {
2002                                 dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n",
2003                                         i, pdata->gpio_cfg[i]);
2004                                 return -EINVAL;
2005                         }
2006                 }
2007         }
2008 
2009         return 0;
2010 }
2011 
2012 static int wm8903_i2c_probe(struct i2c_client *i2c,
2013                             const struct i2c_device_id *id)
2014 {
2015         struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
2016         struct wm8903_priv *wm8903;
2017         int trigger;
2018         bool mic_gpio = false;
2019         unsigned int val, irq_pol;
2020         int ret, i;
2021 
2022         wm8903 = devm_kzalloc(&i2c->dev,  sizeof(struct wm8903_priv),
2023                               GFP_KERNEL);
2024         if (wm8903 == NULL)
2025                 return -ENOMEM;
2026         wm8903->dev = &i2c->dev;
2027 
2028         wm8903->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap);
2029         if (IS_ERR(wm8903->regmap)) {
2030                 ret = PTR_ERR(wm8903->regmap);
2031                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2032                         ret);
2033                 return ret;
2034         }
2035 
2036         i2c_set_clientdata(i2c, wm8903);
2037 
2038         /* If no platform data was supplied, create storage for defaults */
2039         if (pdata) {
2040                 wm8903->pdata = pdata;
2041         } else {
2042                 wm8903->pdata = devm_kzalloc(&i2c->dev,
2043                                         sizeof(struct wm8903_platform_data),
2044                                         GFP_KERNEL);
2045                 if (wm8903->pdata == NULL) {
2046                         dev_err(&i2c->dev, "Failed to allocate pdata\n");
2047                         return -ENOMEM;
2048                 }
2049 
2050                 if (i2c->irq) {
2051                         ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata);
2052                         if (ret != 0)
2053                                 return ret;
2054                 }
2055 
2056                 if (i2c->dev.of_node) {
2057                         ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata);
2058                         if (ret != 0)
2059                                 return ret;
2060                 }
2061         }
2062 
2063         pdata = wm8903->pdata;
2064 
2065         ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val);
2066         if (ret != 0) {
2067                 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
2068                 goto err;
2069         }
2070         if (val != 0x8903) {
2071                 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val);
2072                 ret = -ENODEV;
2073                 goto err;
2074         }
2075 
2076         ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val);
2077         if (ret != 0) {
2078                 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
2079                 goto err;
2080         }
2081         dev_info(&i2c->dev, "WM8903 revision %c\n",
2082                  (val & WM8903_CHIP_REV_MASK) + 'A');
2083 
2084         /* Reset the device */
2085         regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903);
2086 
2087         wm8903_init_gpio(wm8903);
2088 
2089         /* Set up GPIO pin state, detect if any are MIC detect outputs */
2090         for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
2091                 if ((!pdata->gpio_cfg[i]) ||
2092                     (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO))
2093                         continue;
2094 
2095                 regmap_write(wm8903->regmap, WM8903_GPIO_CONTROL_1 + i,
2096                                 pdata->gpio_cfg[i] & 0x7fff);
2097 
2098                 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
2099                         >> WM8903_GP1_FN_SHIFT;
2100 
2101                 switch (val) {
2102                 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
2103                 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
2104                         mic_gpio = true;
2105                         break;
2106                 default:
2107                         break;
2108                 }
2109         }
2110 
2111         /* Set up microphone detection */
2112         regmap_write(wm8903->regmap, WM8903_MIC_BIAS_CONTROL_0,
2113                      pdata->micdet_cfg);
2114 
2115         /* Microphone detection needs the WSEQ clock */
2116         if (pdata->micdet_cfg)
2117                 regmap_update_bits(wm8903->regmap, WM8903_WRITE_SEQUENCER_0,
2118                                    WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
2119 
2120         /* If microphone detection is enabled by pdata but
2121          * detected via IRQ then interrupts can be lost before
2122          * the machine driver has set up microphone detection
2123          * IRQs as the IRQs are clear on read.  The detection
2124          * will be enabled when the machine driver configures.
2125          */
2126         WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
2127 
2128         wm8903->mic_delay = pdata->micdet_delay;
2129 
2130         if (i2c->irq) {
2131                 if (pdata->irq_active_low) {
2132                         trigger = IRQF_TRIGGER_LOW;
2133                         irq_pol = WM8903_IRQ_POL;
2134                 } else {
2135                         trigger = IRQF_TRIGGER_HIGH;
2136                         irq_pol = 0;
2137                 }
2138 
2139                 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_CONTROL,
2140                                    WM8903_IRQ_POL, irq_pol);
2141 
2142                 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,
2143                                            trigger | IRQF_ONESHOT,
2144                                            "wm8903", wm8903);
2145                 if (ret != 0) {
2146                         dev_err(wm8903->dev, "Failed to request IRQ: %d\n",
2147                                 ret);
2148                         return ret;
2149                 }
2150 
2151                 /* Enable write sequencer interrupts */
2152                 regmap_update_bits(wm8903->regmap,
2153                                    WM8903_INTERRUPT_STATUS_1_MASK,
2154                                    WM8903_IM_WSEQ_BUSY_EINT, 0);
2155         }
2156 
2157         /* Latch volume update bits */
2158         regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_LEFT,
2159                            WM8903_ADCVU, WM8903_ADCVU);
2160         regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_RIGHT,
2161                            WM8903_ADCVU, WM8903_ADCVU);
2162 
2163         regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_LEFT,
2164                            WM8903_DACVU, WM8903_DACVU);
2165         regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_RIGHT,
2166                            WM8903_DACVU, WM8903_DACVU);
2167 
2168         regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_LEFT,
2169                            WM8903_HPOUTVU, WM8903_HPOUTVU);
2170         regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_RIGHT,
2171                            WM8903_HPOUTVU, WM8903_HPOUTVU);
2172 
2173         regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_LEFT,
2174                            WM8903_LINEOUTVU, WM8903_LINEOUTVU);
2175         regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_RIGHT,
2176                            WM8903_LINEOUTVU, WM8903_LINEOUTVU);
2177 
2178         regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_LEFT,
2179                            WM8903_SPKVU, WM8903_SPKVU);
2180         regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_RIGHT,
2181                            WM8903_SPKVU, WM8903_SPKVU);
2182 
2183         /* Enable DAC soft mute by default */
2184         regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_1,
2185                            WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
2186                            WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
2187 
2188         ret = snd_soc_register_codec(&i2c->dev,
2189                         &soc_codec_dev_wm8903, &wm8903_dai, 1);
2190         if (ret != 0)
2191                 goto err;
2192 
2193         return 0;
2194 err:
2195         return ret;
2196 }
2197 
2198 static int wm8903_i2c_remove(struct i2c_client *client)
2199 {
2200         struct wm8903_priv *wm8903 = i2c_get_clientdata(client);
2201 
2202         if (client->irq)
2203                 free_irq(client->irq, wm8903);
2204         wm8903_free_gpio(wm8903);
2205         snd_soc_unregister_codec(&client->dev);
2206 
2207         return 0;
2208 }
2209 
2210 static const struct of_device_id wm8903_of_match[] = {
2211         { .compatible = "wlf,wm8903", },
2212         {},
2213 };
2214 MODULE_DEVICE_TABLE(of, wm8903_of_match);
2215 
2216 static const struct i2c_device_id wm8903_i2c_id[] = {
2217         { "wm8903", 0 },
2218         { }
2219 };
2220 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2221 
2222 static struct i2c_driver wm8903_i2c_driver = {
2223         .driver = {
2224                 .name = "wm8903",
2225                 .owner = THIS_MODULE,
2226                 .of_match_table = wm8903_of_match,
2227         },
2228         .probe =    wm8903_i2c_probe,
2229         .remove =   wm8903_i2c_remove,
2230         .id_table = wm8903_i2c_id,
2231 };
2232 
2233 module_i2c_driver(wm8903_i2c_driver);
2234 
2235 MODULE_DESCRIPTION("ASoC WM8903 driver");
2236 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2237 MODULE_LICENSE("GPL");
2238 

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