Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/sound/soc/codecs/wm8400.c

  1 /*
  2  * wm8400.c  --  WM8400 ALSA Soc Audio driver
  3  *
  4  * Copyright 2008-11 Wolfson Microelectronics PLC.
  5  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  6  *
  7  *  This program is free software; you can redistribute  it and/or modify it
  8  *  under  the terms of  the GNU General  Public License as published by the
  9  *  Free Software Foundation;  either version 2 of the  License, or (at your
 10  *  option) any later version.
 11  *
 12  */
 13 
 14 #include <linux/module.h>
 15 #include <linux/moduleparam.h>
 16 #include <linux/kernel.h>
 17 #include <linux/slab.h>
 18 #include <linux/init.h>
 19 #include <linux/delay.h>
 20 #include <linux/pm.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/regulator/consumer.h>
 23 #include <linux/mfd/wm8400-audio.h>
 24 #include <linux/mfd/wm8400-private.h>
 25 #include <linux/mfd/core.h>
 26 #include <sound/core.h>
 27 #include <sound/pcm.h>
 28 #include <sound/pcm_params.h>
 29 #include <sound/soc.h>
 30 #include <sound/initval.h>
 31 #include <sound/tlv.h>
 32 
 33 #include "wm8400.h"
 34 
 35 static struct regulator_bulk_data power[] = {
 36         {
 37                 .supply = "I2S1VDD",
 38         },
 39         {
 40                 .supply = "I2S2VDD",
 41         },
 42         {
 43                 .supply = "DCVDD",
 44         },
 45         {
 46                 .supply = "AVDD",
 47         },
 48         {
 49                 .supply = "FLLVDD",
 50         },
 51         {
 52                 .supply = "HPVDD",
 53         },
 54         {
 55                 .supply = "SPKVDD",
 56         },
 57 };
 58 
 59 /* codec private data */
 60 struct wm8400_priv {
 61         struct wm8400 *wm8400;
 62         u16 fake_register;
 63         unsigned int sysclk;
 64         unsigned int pcmclk;
 65         int fll_in, fll_out;
 66 };
 67 
 68 static void wm8400_codec_reset(struct snd_soc_codec *codec)
 69 {
 70         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
 71 
 72         wm8400_reset_codec_reg_cache(wm8400->wm8400);
 73 }
 74 
 75 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
 76 
 77 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
 78 
 79 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
 80 
 81 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
 82 
 83 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
 84 
 85 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
 86 
 87 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
 88 
 89 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
 90 
 91 static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
 92         struct snd_ctl_elem_value *ucontrol)
 93 {
 94         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 95         struct soc_mixer_control *mc =
 96                 (struct soc_mixer_control *)kcontrol->private_value;
 97         int reg = mc->reg;
 98         int ret;
 99         u16 val;
100 
101         ret = snd_soc_put_volsw(kcontrol, ucontrol);
102         if (ret < 0)
103                 return ret;
104 
105         /* now hit the volume update bits (always bit 8) */
106         val = snd_soc_read(codec, reg);
107         return snd_soc_write(codec, reg, val | 0x0100);
108 }
109 
110 #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
111         SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
112                 snd_soc_get_volsw, wm8400_outpga_put_volsw_vu, tlv_array)
113 
114 
115 static const char *wm8400_digital_sidetone[] =
116         {"None", "Left ADC", "Right ADC", "Reserved"};
117 
118 static SOC_ENUM_SINGLE_DECL(wm8400_left_digital_sidetone_enum,
119                             WM8400_DIGITAL_SIDE_TONE,
120                             WM8400_ADC_TO_DACL_SHIFT,
121                             wm8400_digital_sidetone);
122 
123 static SOC_ENUM_SINGLE_DECL(wm8400_right_digital_sidetone_enum,
124                             WM8400_DIGITAL_SIDE_TONE,
125                             WM8400_ADC_TO_DACR_SHIFT,
126                             wm8400_digital_sidetone);
127 
128 static const char *wm8400_adcmode[] =
129         {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
130 
131 static SOC_ENUM_SINGLE_DECL(wm8400_right_adcmode_enum,
132                             WM8400_ADC_CTRL,
133                             WM8400_ADC_HPF_CUT_SHIFT,
134                             wm8400_adcmode);
135 
136 static const struct snd_kcontrol_new wm8400_snd_controls[] = {
137 /* INMIXL */
138 SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT,
139            1, 0),
140 SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT,
141            1, 0),
142 /* INMIXR */
143 SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT,
144            1, 0),
145 SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT,
146            1, 0),
147 
148 /* LOMIX */
149 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
150         WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
151 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
152         WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv),
153 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
154         WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv),
155 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
156         WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
157 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
158         WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
159 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
160         WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
161 
162 /* ROMIX */
163 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
164         WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
165 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
166         WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv),
167 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
168         WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv),
169 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
170         WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
171 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
172         WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv),
173 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
174         WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv),
175 
176 /* LOUT */
177 WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME,
178         WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv),
179 SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0),
180 
181 /* ROUT */
182 WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME,
183         WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv),
184 SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0),
185 
186 /* LOPGA */
187 WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME,
188         WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv),
189 SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME,
190         WM8400_LOPGAZC_SHIFT, 1, 0),
191 
192 /* ROPGA */
193 WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME,
194         WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv),
195 SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME,
196         WM8400_ROPGAZC_SHIFT, 1, 0),
197 
198 SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
199         WM8400_LONMUTE_SHIFT, 1, 0),
200 SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
201         WM8400_LOPMUTE_SHIFT, 1, 0),
202 SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
203         WM8400_LOATTN_SHIFT, 1, 0),
204 SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
205         WM8400_RONMUTE_SHIFT, 1, 0),
206 SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
207         WM8400_ROPMUTE_SHIFT, 1, 0),
208 SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
209         WM8400_ROATTN_SHIFT, 1, 0),
210 
211 SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME,
212         WM8400_OUT3MUTE_SHIFT, 1, 0),
213 SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME,
214         WM8400_OUT3ATTN_SHIFT, 1, 0),
215 
216 SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME,
217         WM8400_OUT4MUTE_SHIFT, 1, 0),
218 SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME,
219         WM8400_OUT4ATTN_SHIFT, 1, 0),
220 
221 SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1,
222         WM8400_CDMODE_SHIFT, 1, 0),
223 
224 SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME,
225         WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0),
226 SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3,
227         WM8400_DCGAIN_SHIFT, 6, 0),
228 SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3,
229         WM8400_ACGAIN_SHIFT, 6, 0),
230 
231 WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
232         WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT,
233         127, 0, out_dac_tlv),
234 
235 WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
236         WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT,
237         127, 0, out_dac_tlv),
238 
239 SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum),
240 SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum),
241 
242 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
243         WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
244 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
245         WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
246 
247 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL,
248         WM8400_ADC_HPF_ENA_SHIFT, 1, 0),
249 
250 SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum),
251 
252 WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
253         WM8400_LEFT_ADC_DIGITAL_VOLUME,
254         WM8400_ADCL_VOL_SHIFT,
255         WM8400_ADCL_VOL_MASK,
256         0,
257         in_adc_tlv),
258 
259 WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
260         WM8400_RIGHT_ADC_DIGITAL_VOLUME,
261         WM8400_ADCR_VOL_SHIFT,
262         WM8400_ADCR_VOL_MASK,
263         0,
264         in_adc_tlv),
265 
266 WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
267         WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
268         WM8400_LIN12VOL_SHIFT,
269         WM8400_LIN12VOL_MASK,
270         0,
271         in_pga_tlv),
272 
273 SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
274         WM8400_LI12ZC_SHIFT, 1, 0),
275 
276 SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
277         WM8400_LI12MUTE_SHIFT, 1, 0),
278 
279 WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
280         WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
281         WM8400_LIN34VOL_SHIFT,
282         WM8400_LIN34VOL_MASK,
283         0,
284         in_pga_tlv),
285 
286 SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
287         WM8400_LI34ZC_SHIFT, 1, 0),
288 
289 SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
290         WM8400_LI34MUTE_SHIFT, 1, 0),
291 
292 WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
293         WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
294         WM8400_RIN12VOL_SHIFT,
295         WM8400_RIN12VOL_MASK,
296         0,
297         in_pga_tlv),
298 
299 SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
300         WM8400_RI12ZC_SHIFT, 1, 0),
301 
302 SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
303         WM8400_RI12MUTE_SHIFT, 1, 0),
304 
305 WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
306         WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
307         WM8400_RIN34VOL_SHIFT,
308         WM8400_RIN34VOL_MASK,
309         0,
310         in_pga_tlv),
311 
312 SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
313         WM8400_RI34ZC_SHIFT, 1, 0),
314 
315 SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
316         WM8400_RI34MUTE_SHIFT, 1, 0),
317 
318 };
319 
320 /*
321  * _DAPM_ Controls
322  */
323 
324 static int outmixer_event (struct snd_soc_dapm_widget *w,
325         struct snd_kcontrol * kcontrol, int event)
326 {
327         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
328         struct soc_mixer_control *mc =
329                 (struct soc_mixer_control *)kcontrol->private_value;
330         u32 reg_shift = mc->shift;
331         int ret = 0;
332         u16 reg;
333 
334         switch (reg_shift) {
335         case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) :
336                 reg = snd_soc_read(codec, WM8400_OUTPUT_MIXER1);
337                 if (reg & WM8400_LDLO) {
338                         printk(KERN_WARNING
339                         "Cannot set as Output Mixer 1 LDLO Set\n");
340                         ret = -1;
341                 }
342                 break;
343         case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8):
344                 reg = snd_soc_read(codec, WM8400_OUTPUT_MIXER2);
345                 if (reg & WM8400_RDRO) {
346                         printk(KERN_WARNING
347                         "Cannot set as Output Mixer 2 RDRO Set\n");
348                         ret = -1;
349                 }
350                 break;
351         case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8):
352                 reg = snd_soc_read(codec, WM8400_SPEAKER_MIXER);
353                 if (reg & WM8400_LDSPK) {
354                         printk(KERN_WARNING
355                         "Cannot set as Speaker Mixer LDSPK Set\n");
356                         ret = -1;
357                 }
358                 break;
359         case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8):
360                 reg = snd_soc_read(codec, WM8400_SPEAKER_MIXER);
361                 if (reg & WM8400_RDSPK) {
362                         printk(KERN_WARNING
363                         "Cannot set as Speaker Mixer RDSPK Set\n");
364                         ret = -1;
365                 }
366                 break;
367         }
368 
369         return ret;
370 }
371 
372 /* INMIX dB values */
373 static const DECLARE_TLV_DB_SCALE(in_mix_tlv, -1200, 600, 0);
374 
375 /* Left In PGA Connections */
376 static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = {
377 SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0),
378 SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0),
379 };
380 
381 static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = {
382 SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0),
383 SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0),
384 };
385 
386 /* Right In PGA Connections */
387 static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = {
388 SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0),
389 SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0),
390 };
391 
392 static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = {
393 SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0),
394 SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0),
395 };
396 
397 /* INMIXL */
398 static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = {
399 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3,
400         WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv),
401 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT,
402         7, 0, in_mix_tlv),
403 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
404                 1, 0),
405 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
406                 1, 0),
407 };
408 
409 /* INMIXR */
410 static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = {
411 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4,
412         WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv),
413 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT,
414         7, 0, in_mix_tlv),
415 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
416         1, 0),
417 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
418         1, 0),
419 };
420 
421 /* AINLMUX */
422 static const char *wm8400_ainlmux[] =
423         {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
424 
425 static SOC_ENUM_SINGLE_DECL(wm8400_ainlmux_enum,
426                             WM8400_INPUT_MIXER1,
427                             WM8400_AINLMODE_SHIFT,
428                             wm8400_ainlmux);
429 
430 static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls =
431 SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum);
432 
433 /* DIFFINL */
434 
435 /* AINRMUX */
436 static const char *wm8400_ainrmux[] =
437         {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
438 
439 static SOC_ENUM_SINGLE_DECL(wm8400_ainrmux_enum,
440                             WM8400_INPUT_MIXER1,
441                             WM8400_AINRMODE_SHIFT,
442                             wm8400_ainrmux);
443 
444 static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls =
445 SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum);
446 
447 /* RXVOICE */
448 static const struct snd_kcontrol_new wm8400_dapm_rxvoice_controls[] = {
449 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8400_INPUT_MIXER5, WM8400_LR4BVOL_SHIFT,
450                         WM8400_LR4BVOL_MASK, 0, in_mix_tlv),
451 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8400_INPUT_MIXER6, WM8400_RL4BVOL_SHIFT,
452                         WM8400_RL4BVOL_MASK, 0, in_mix_tlv),
453 };
454 
455 /* LOMIX */
456 static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = {
457 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
458         WM8400_LRBLO_SHIFT, 1, 0),
459 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
460         WM8400_LLBLO_SHIFT, 1, 0),
461 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
462         WM8400_LRI3LO_SHIFT, 1, 0),
463 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
464         WM8400_LLI3LO_SHIFT, 1, 0),
465 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
466         WM8400_LR12LO_SHIFT, 1, 0),
467 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
468         WM8400_LL12LO_SHIFT, 1, 0),
469 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1,
470         WM8400_LDLO_SHIFT, 1, 0),
471 };
472 
473 /* ROMIX */
474 static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = {
475 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
476         WM8400_RLBRO_SHIFT, 1, 0),
477 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
478         WM8400_RRBRO_SHIFT, 1, 0),
479 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
480         WM8400_RLI3RO_SHIFT, 1, 0),
481 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
482         WM8400_RRI3RO_SHIFT, 1, 0),
483 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
484         WM8400_RL12RO_SHIFT, 1, 0),
485 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
486         WM8400_RR12RO_SHIFT, 1, 0),
487 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2,
488         WM8400_RDRO_SHIFT, 1, 0),
489 };
490 
491 /* LONMIX */
492 static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = {
493 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
494         WM8400_LLOPGALON_SHIFT, 1, 0),
495 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1,
496         WM8400_LROPGALON_SHIFT, 1, 0),
497 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1,
498         WM8400_LOPLON_SHIFT, 1, 0),
499 };
500 
501 /* LOPMIX */
502 static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = {
503 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1,
504         WM8400_LR12LOP_SHIFT, 1, 0),
505 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1,
506         WM8400_LL12LOP_SHIFT, 1, 0),
507 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
508         WM8400_LLOPGALOP_SHIFT, 1, 0),
509 };
510 
511 /* RONMIX */
512 static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = {
513 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
514         WM8400_RROPGARON_SHIFT, 1, 0),
515 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2,
516         WM8400_RLOPGARON_SHIFT, 1, 0),
517 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2,
518         WM8400_ROPRON_SHIFT, 1, 0),
519 };
520 
521 /* ROPMIX */
522 static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = {
523 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2,
524         WM8400_RL12ROP_SHIFT, 1, 0),
525 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2,
526         WM8400_RR12ROP_SHIFT, 1, 0),
527 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
528         WM8400_RROPGAROP_SHIFT, 1, 0),
529 };
530 
531 /* OUT3MIX */
532 static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = {
533 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
534         WM8400_LI4O3_SHIFT, 1, 0),
535 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER,
536         WM8400_LPGAO3_SHIFT, 1, 0),
537 };
538 
539 /* OUT4MIX */
540 static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = {
541 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER,
542         WM8400_RPGAO4_SHIFT, 1, 0),
543 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
544         WM8400_RI4O4_SHIFT, 1, 0),
545 };
546 
547 /* SPKMIX */
548 static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = {
549 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
550         WM8400_LI2SPK_SHIFT, 1, 0),
551 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER,
552         WM8400_LB2SPK_SHIFT, 1, 0),
553 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER,
554         WM8400_LOPGASPK_SHIFT, 1, 0),
555 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER,
556         WM8400_LDSPK_SHIFT, 1, 0),
557 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER,
558         WM8400_RDSPK_SHIFT, 1, 0),
559 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER,
560         WM8400_ROPGASPK_SHIFT, 1, 0),
561 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER,
562         WM8400_RL12ROP_SHIFT, 1, 0),
563 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
564         WM8400_RI2SPK_SHIFT, 1, 0),
565 };
566 
567 static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = {
568 /* Input Side */
569 /* Input Lines */
570 SND_SOC_DAPM_INPUT("LIN1"),
571 SND_SOC_DAPM_INPUT("LIN2"),
572 SND_SOC_DAPM_INPUT("LIN3"),
573 SND_SOC_DAPM_INPUT("LIN4/RXN"),
574 SND_SOC_DAPM_INPUT("RIN3"),
575 SND_SOC_DAPM_INPUT("RIN4/RXP"),
576 SND_SOC_DAPM_INPUT("RIN1"),
577 SND_SOC_DAPM_INPUT("RIN2"),
578 SND_SOC_DAPM_INPUT("Internal ADC Source"),
579 
580 /* DACs */
581 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2,
582         WM8400_ADCL_ENA_SHIFT, 0),
583 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2,
584         WM8400_ADCR_ENA_SHIFT, 0),
585 
586 /* Input PGAs */
587 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2,
588                    WM8400_LIN12_ENA_SHIFT,
589                    0, &wm8400_dapm_lin12_pga_controls[0],
590                    ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)),
591 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2,
592                    WM8400_LIN34_ENA_SHIFT,
593                    0, &wm8400_dapm_lin34_pga_controls[0],
594                    ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)),
595 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2,
596                    WM8400_RIN12_ENA_SHIFT,
597                    0, &wm8400_dapm_rin12_pga_controls[0],
598                    ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)),
599 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2,
600                    WM8400_RIN34_ENA_SHIFT,
601                    0, &wm8400_dapm_rin34_pga_controls[0],
602                    ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)),
603 
604 SND_SOC_DAPM_SUPPLY("INL", WM8400_POWER_MANAGEMENT_2, WM8400_AINL_ENA_SHIFT,
605                     0, NULL, 0),
606 SND_SOC_DAPM_SUPPLY("INR", WM8400_POWER_MANAGEMENT_2, WM8400_AINR_ENA_SHIFT,
607                     0, NULL, 0),
608 
609 /* INMIXL */
610 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
611         &wm8400_dapm_inmixl_controls[0],
612         ARRAY_SIZE(wm8400_dapm_inmixl_controls)),
613 
614 /* AINLMUX */
615 SND_SOC_DAPM_MUX("AILNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainlmux_controls),
616 
617 /* INMIXR */
618 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
619         &wm8400_dapm_inmixr_controls[0],
620         ARRAY_SIZE(wm8400_dapm_inmixr_controls)),
621 
622 /* AINRMUX */
623 SND_SOC_DAPM_MUX("AIRNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainrmux_controls),
624 
625 /* Output Side */
626 /* DACs */
627 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3,
628         WM8400_DACL_ENA_SHIFT, 0),
629 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3,
630         WM8400_DACR_ENA_SHIFT, 0),
631 
632 /* LOMIX */
633 SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3,
634                      WM8400_LOMIX_ENA_SHIFT,
635                      0, &wm8400_dapm_lomix_controls[0],
636                      ARRAY_SIZE(wm8400_dapm_lomix_controls),
637                      outmixer_event, SND_SOC_DAPM_PRE_REG),
638 
639 /* LONMIX */
640 SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT,
641                    0, &wm8400_dapm_lonmix_controls[0],
642                    ARRAY_SIZE(wm8400_dapm_lonmix_controls)),
643 
644 /* LOPMIX */
645 SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT,
646                    0, &wm8400_dapm_lopmix_controls[0],
647                    ARRAY_SIZE(wm8400_dapm_lopmix_controls)),
648 
649 /* OUT3MIX */
650 SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT,
651                    0, &wm8400_dapm_out3mix_controls[0],
652                    ARRAY_SIZE(wm8400_dapm_out3mix_controls)),
653 
654 /* SPKMIX */
655 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT,
656                      0, &wm8400_dapm_spkmix_controls[0],
657                      ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event,
658                      SND_SOC_DAPM_PRE_REG),
659 
660 /* OUT4MIX */
661 SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT,
662         0, &wm8400_dapm_out4mix_controls[0],
663         ARRAY_SIZE(wm8400_dapm_out4mix_controls)),
664 
665 /* ROPMIX */
666 SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT,
667                    0, &wm8400_dapm_ropmix_controls[0],
668                    ARRAY_SIZE(wm8400_dapm_ropmix_controls)),
669 
670 /* RONMIX */
671 SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT,
672                    0, &wm8400_dapm_ronmix_controls[0],
673                    ARRAY_SIZE(wm8400_dapm_ronmix_controls)),
674 
675 /* ROMIX */
676 SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3,
677                      WM8400_ROMIX_ENA_SHIFT,
678                      0, &wm8400_dapm_romix_controls[0],
679                      ARRAY_SIZE(wm8400_dapm_romix_controls),
680                      outmixer_event, SND_SOC_DAPM_PRE_REG),
681 
682 /* LOUT PGA */
683 SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT,
684                  0, NULL, 0),
685 
686 /* ROUT PGA */
687 SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT,
688                  0, NULL, 0),
689 
690 /* LOPGA */
691 SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0,
692         NULL, 0),
693 
694 /* ROPGA */
695 SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0,
696         NULL, 0),
697 
698 /* MICBIAS */
699 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8400_POWER_MANAGEMENT_1,
700                     WM8400_MIC1BIAS_ENA_SHIFT, 0, NULL, 0),
701 
702 SND_SOC_DAPM_OUTPUT("LON"),
703 SND_SOC_DAPM_OUTPUT("LOP"),
704 SND_SOC_DAPM_OUTPUT("OUT3"),
705 SND_SOC_DAPM_OUTPUT("LOUT"),
706 SND_SOC_DAPM_OUTPUT("SPKN"),
707 SND_SOC_DAPM_OUTPUT("SPKP"),
708 SND_SOC_DAPM_OUTPUT("ROUT"),
709 SND_SOC_DAPM_OUTPUT("OUT4"),
710 SND_SOC_DAPM_OUTPUT("ROP"),
711 SND_SOC_DAPM_OUTPUT("RON"),
712 
713 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
714 };
715 
716 static const struct snd_soc_dapm_route wm8400_dapm_routes[] = {
717         /* Make DACs turn on when playing even if not mixed into any outputs */
718         {"Internal DAC Sink", NULL, "Left DAC"},
719         {"Internal DAC Sink", NULL, "Right DAC"},
720 
721         /* Make ADCs turn on when recording
722          * even if not mixed from any inputs */
723         {"Left ADC", NULL, "Internal ADC Source"},
724         {"Right ADC", NULL, "Internal ADC Source"},
725 
726         /* Input Side */
727         /* LIN12 PGA */
728         {"LIN12 PGA", "LIN1 Switch", "LIN1"},
729         {"LIN12 PGA", "LIN2 Switch", "LIN2"},
730         /* LIN34 PGA */
731         {"LIN34 PGA", "LIN3 Switch", "LIN3"},
732         {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
733         /* INMIXL */
734         {"INMIXL", NULL, "INL"},
735         {"INMIXL", "Record Left Volume", "LOMIX"},
736         {"INMIXL", "LIN2 Volume", "LIN2"},
737         {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
738         {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
739         /* AILNMUX */
740         {"AILNMUX", NULL, "INL"},
741         {"AILNMUX", "INMIXL Mix", "INMIXL"},
742         {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"},
743         {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"},
744         {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
745         {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
746         /* ADC */
747         {"Left ADC", NULL, "AILNMUX"},
748 
749         /* RIN12 PGA */
750         {"RIN12 PGA", "RIN1 Switch", "RIN1"},
751         {"RIN12 PGA", "RIN2 Switch", "RIN2"},
752         /* RIN34 PGA */
753         {"RIN34 PGA", "RIN3 Switch", "RIN3"},
754         {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
755         /* INMIXR */
756         {"INMIXR", NULL, "INR"},
757         {"INMIXR", "Record Right Volume", "ROMIX"},
758         {"INMIXR", "RIN2 Volume", "RIN2"},
759         {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
760         {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
761         /* AIRNMUX */
762         {"AIRNMUX", NULL, "INR"},
763         {"AIRNMUX", "INMIXR Mix", "INMIXR"},
764         {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"},
765         {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"},
766         {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"},
767         {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
768         /* ADC */
769         {"Right ADC", NULL, "AIRNMUX"},
770 
771         /* LOMIX */
772         {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
773         {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
774         {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
775         {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
776         {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"},
777         {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"},
778         {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
779 
780         /* ROMIX */
781         {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
782         {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
783         {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
784         {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
785         {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"},
786         {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"},
787         {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
788 
789         /* SPKMIX */
790         {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
791         {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
792         {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"},
793         {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"},
794         {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
795         {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
796         {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
797         {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
798 
799         /* LONMIX */
800         {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
801         {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
802         {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
803 
804         /* LOPMIX */
805         {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
806         {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
807         {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
808 
809         /* OUT3MIX */
810         {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
811         {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
812 
813         /* OUT4MIX */
814         {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
815         {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
816 
817         /* RONMIX */
818         {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
819         {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
820         {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
821 
822         /* ROPMIX */
823         {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
824         {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
825         {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
826 
827         /* Out Mixer PGAs */
828         {"LOPGA", NULL, "LOMIX"},
829         {"ROPGA", NULL, "ROMIX"},
830 
831         {"LOUT PGA", NULL, "LOMIX"},
832         {"ROUT PGA", NULL, "ROMIX"},
833 
834         /* Output Pins */
835         {"LON", NULL, "LONMIX"},
836         {"LOP", NULL, "LOPMIX"},
837         {"OUT3", NULL, "OUT3MIX"},
838         {"LOUT", NULL, "LOUT PGA"},
839         {"SPKN", NULL, "SPKMIX"},
840         {"ROUT", NULL, "ROUT PGA"},
841         {"OUT4", NULL, "OUT4MIX"},
842         {"ROP", NULL, "ROPMIX"},
843         {"RON", NULL, "RONMIX"},
844 };
845 
846 /*
847  * Clock after FLL and dividers
848  */
849 static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai,
850                 int clk_id, unsigned int freq, int dir)
851 {
852         struct snd_soc_codec *codec = codec_dai->codec;
853         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
854 
855         wm8400->sysclk = freq;
856         return 0;
857 }
858 
859 struct fll_factors {
860         u16 n;
861         u16 k;
862         u16 outdiv;
863         u16 fratio;
864         u16 freq_ref;
865 };
866 
867 #define FIXED_FLL_SIZE ((1 << 16) * 10)
868 
869 static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors,
870                        unsigned int Fref, unsigned int Fout)
871 {
872         u64 Kpart;
873         unsigned int K, Nmod, target;
874 
875         factors->outdiv = 2;
876         while (Fout * factors->outdiv <  90000000 ||
877                Fout * factors->outdiv > 100000000) {
878                 factors->outdiv *= 2;
879                 if (factors->outdiv > 32) {
880                         dev_err(wm8400->wm8400->dev,
881                                 "Unsupported FLL output frequency %uHz\n",
882                                 Fout);
883                         return -EINVAL;
884                 }
885         }
886         target = Fout * factors->outdiv;
887         factors->outdiv = factors->outdiv >> 2;
888 
889         if (Fref < 48000)
890                 factors->freq_ref = 1;
891         else
892                 factors->freq_ref = 0;
893 
894         if (Fref < 1000000)
895                 factors->fratio = 9;
896         else
897                 factors->fratio = 0;
898 
899         /* Ensure we have a fractional part */
900         do {
901                 if (Fref < 1000000)
902                         factors->fratio--;
903                 else
904                         factors->fratio++;
905 
906                 if (factors->fratio < 1 || factors->fratio > 8) {
907                         dev_err(wm8400->wm8400->dev,
908                                 "Unable to calculate FRATIO\n");
909                         return -EINVAL;
910                 }
911 
912                 factors->n = target / (Fref * factors->fratio);
913                 Nmod = target % (Fref * factors->fratio);
914         } while (Nmod == 0);
915 
916         /* Calculate fractional part - scale up so we can round. */
917         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
918 
919         do_div(Kpart, (Fref * factors->fratio));
920 
921         K = Kpart & 0xFFFFFFFF;
922 
923         if ((K % 10) >= 5)
924                 K += 5;
925 
926         /* Move down to proper range now rounding is done */
927         factors->k = K / 10;
928 
929         dev_dbg(wm8400->wm8400->dev,
930                 "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n",
931                 Fref, Fout,
932                 factors->n, factors->k, factors->fratio, factors->outdiv);
933 
934         return 0;
935 }
936 
937 static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
938                               int source, unsigned int freq_in,
939                               unsigned int freq_out)
940 {
941         struct snd_soc_codec *codec = codec_dai->codec;
942         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
943         struct fll_factors factors;
944         int ret;
945         u16 reg;
946 
947         if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out)
948                 return 0;
949 
950         if (freq_out) {
951                 ret = fll_factors(wm8400, &factors, freq_in, freq_out);
952                 if (ret != 0)
953                         return ret;
954         } else {
955                 /* Bodge GCC 4.4.0 uninitialised variable warning - it
956                  * doesn't seem capable of working out that we exit if
957                  * freq_out is 0 before any of the uses. */
958                 memset(&factors, 0, sizeof(factors));
959         }
960 
961         wm8400->fll_out = freq_out;
962         wm8400->fll_in = freq_in;
963 
964         /* We *must* disable the FLL before any changes */
965         reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_2);
966         reg &= ~WM8400_FLL_ENA;
967         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_2, reg);
968 
969         reg = snd_soc_read(codec, WM8400_FLL_CONTROL_1);
970         reg &= ~WM8400_FLL_OSC_ENA;
971         snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg);
972 
973         if (!freq_out)
974                 return 0;
975 
976         reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK);
977         reg |= WM8400_FLL_FRAC | factors.fratio;
978         reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT;
979         snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg);
980 
981         snd_soc_write(codec, WM8400_FLL_CONTROL_2, factors.k);
982         snd_soc_write(codec, WM8400_FLL_CONTROL_3, factors.n);
983 
984         reg = snd_soc_read(codec, WM8400_FLL_CONTROL_4);
985         reg &= ~WM8400_FLL_OUTDIV_MASK;
986         reg |= factors.outdiv;
987         snd_soc_write(codec, WM8400_FLL_CONTROL_4, reg);
988 
989         return 0;
990 }
991 
992 /*
993  * Sets ADC and Voice DAC format.
994  */
995 static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
996                 unsigned int fmt)
997 {
998         struct snd_soc_codec *codec = codec_dai->codec;
999         u16 audio1, audio3;
1000 
1001         audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1);
1002         audio3 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_3);
1003 
1004         /* set master/slave audio interface */
1005         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1006         case SND_SOC_DAIFMT_CBS_CFS:
1007                 audio3 &= ~WM8400_AIF_MSTR1;
1008                 break;
1009         case SND_SOC_DAIFMT_CBM_CFM:
1010                 audio3 |= WM8400_AIF_MSTR1;
1011                 break;
1012         default:
1013                 return -EINVAL;
1014         }
1015 
1016         audio1 &= ~WM8400_AIF_FMT_MASK;
1017 
1018         /* interface format */
1019         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1020         case SND_SOC_DAIFMT_I2S:
1021                 audio1 |= WM8400_AIF_FMT_I2S;
1022                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1023                 break;
1024         case SND_SOC_DAIFMT_RIGHT_J:
1025                 audio1 |= WM8400_AIF_FMT_RIGHTJ;
1026                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1027                 break;
1028         case SND_SOC_DAIFMT_LEFT_J:
1029                 audio1 |= WM8400_AIF_FMT_LEFTJ;
1030                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1031                 break;
1032         case SND_SOC_DAIFMT_DSP_A:
1033                 audio1 |= WM8400_AIF_FMT_DSP;
1034                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1035                 break;
1036         case SND_SOC_DAIFMT_DSP_B:
1037                 audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV;
1038                 break;
1039         default:
1040                 return -EINVAL;
1041         }
1042 
1043         snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1044         snd_soc_write(codec, WM8400_AUDIO_INTERFACE_3, audio3);
1045         return 0;
1046 }
1047 
1048 static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1049                 int div_id, int div)
1050 {
1051         struct snd_soc_codec *codec = codec_dai->codec;
1052         u16 reg;
1053 
1054         switch (div_id) {
1055         case WM8400_MCLK_DIV:
1056                 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1057                         ~WM8400_MCLK_DIV_MASK;
1058                 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1059                 break;
1060         case WM8400_DACCLK_DIV:
1061                 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1062                         ~WM8400_DAC_CLKDIV_MASK;
1063                 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1064                 break;
1065         case WM8400_ADCCLK_DIV:
1066                 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1067                         ~WM8400_ADC_CLKDIV_MASK;
1068                 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1069                 break;
1070         case WM8400_BCLK_DIV:
1071                 reg = snd_soc_read(codec, WM8400_CLOCKING_1) &
1072                         ~WM8400_BCLK_DIV_MASK;
1073                 snd_soc_write(codec, WM8400_CLOCKING_1, reg | div);
1074                 break;
1075         default:
1076                 return -EINVAL;
1077         }
1078 
1079         return 0;
1080 }
1081 
1082 /*
1083  * Set PCM DAI bit size and sample rate.
1084  */
1085 static int wm8400_hw_params(struct snd_pcm_substream *substream,
1086         struct snd_pcm_hw_params *params,
1087         struct snd_soc_dai *dai)
1088 {
1089         struct snd_soc_codec *codec = dai->codec;
1090         u16 audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1);
1091 
1092         audio1 &= ~WM8400_AIF_WL_MASK;
1093         /* bit size */
1094         switch (params_width(params)) {
1095         case 16:
1096                 break;
1097         case 20:
1098                 audio1 |= WM8400_AIF_WL_20BITS;
1099                 break;
1100         case 24:
1101                 audio1 |= WM8400_AIF_WL_24BITS;
1102                 break;
1103         case 32:
1104                 audio1 |= WM8400_AIF_WL_32BITS;
1105                 break;
1106         }
1107 
1108         snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1109         return 0;
1110 }
1111 
1112 static int wm8400_mute(struct snd_soc_dai *dai, int mute)
1113 {
1114         struct snd_soc_codec *codec = dai->codec;
1115         u16 val = snd_soc_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE;
1116 
1117         if (mute)
1118                 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1119         else
1120                 snd_soc_write(codec, WM8400_DAC_CTRL, val);
1121 
1122         return 0;
1123 }
1124 
1125 /* TODO: set bias for best performance at standby */
1126 static int wm8400_set_bias_level(struct snd_soc_codec *codec,
1127                                  enum snd_soc_bias_level level)
1128 {
1129         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
1130         u16 val;
1131         int ret;
1132 
1133         switch (level) {
1134         case SND_SOC_BIAS_ON:
1135                 break;
1136 
1137         case SND_SOC_BIAS_PREPARE:
1138                 /* VMID=2*50k */
1139                 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) &
1140                         ~WM8400_VMID_MODE_MASK;
1141                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2);
1142                 break;
1143 
1144         case SND_SOC_BIAS_STANDBY:
1145                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1146                         ret = regulator_bulk_enable(ARRAY_SIZE(power),
1147                                                     &power[0]);
1148                         if (ret != 0) {
1149                                 dev_err(wm8400->wm8400->dev,
1150                                         "Failed to enable regulators: %d\n",
1151                                         ret);
1152                                 return ret;
1153                         }
1154 
1155                         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1,
1156                                      WM8400_CODEC_ENA | WM8400_SYSCLK_ENA);
1157 
1158                         /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1159                         snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1160                                      WM8400_BUFDCOPEN | WM8400_POBCTRL);
1161 
1162                         msleep(50);
1163 
1164                         /* Enable VREF & VMID at 2x50k */
1165                         val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1166                         val |= 0x2 | WM8400_VREF_ENA;
1167                         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1168 
1169                         /* Enable BUFIOEN */
1170                         snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1171                                      WM8400_BUFDCOPEN | WM8400_POBCTRL |
1172                                      WM8400_BUFIOEN);
1173 
1174                         /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1175                         snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN);
1176                 }
1177 
1178                 /* VMID=2*300k */
1179                 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) &
1180                         ~WM8400_VMID_MODE_MASK;
1181                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4);
1182                 break;
1183 
1184         case SND_SOC_BIAS_OFF:
1185                 /* Enable POBCTRL and SOFT_ST */
1186                 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1187                         WM8400_POBCTRL | WM8400_BUFIOEN);
1188 
1189                 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1190                 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1191                         WM8400_BUFDCOPEN | WM8400_POBCTRL |
1192                         WM8400_BUFIOEN);
1193 
1194                 /* mute DAC */
1195                 val = snd_soc_read(codec, WM8400_DAC_CTRL);
1196                 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1197 
1198                 /* Enable any disabled outputs */
1199                 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1200                 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
1201                         WM8400_OUT4_ENA | WM8400_LOUT_ENA |
1202                         WM8400_ROUT_ENA;
1203                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1204 
1205                 /* Disable VMID */
1206                 val &= ~WM8400_VMID_MODE_MASK;
1207                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1208 
1209                 msleep(300);
1210 
1211                 /* Enable all output discharge bits */
1212                 snd_soc_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
1213                         WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
1214                         WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
1215                         WM8400_DIS_ROUT);
1216 
1217                 /* Disable VREF */
1218                 val &= ~WM8400_VREF_ENA;
1219                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1220 
1221                 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1222                 snd_soc_write(codec, WM8400_ANTIPOP2, 0x0);
1223 
1224                 ret = regulator_bulk_disable(ARRAY_SIZE(power),
1225                                              &power[0]);
1226                 if (ret != 0)
1227                         return ret;
1228 
1229                 break;
1230         }
1231 
1232         return 0;
1233 }
1234 
1235 #define WM8400_RATES SNDRV_PCM_RATE_8000_96000
1236 
1237 #define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1238         SNDRV_PCM_FMTBIT_S24_LE)
1239 
1240 static const struct snd_soc_dai_ops wm8400_dai_ops = {
1241         .hw_params = wm8400_hw_params,
1242         .digital_mute = wm8400_mute,
1243         .set_fmt = wm8400_set_dai_fmt,
1244         .set_clkdiv = wm8400_set_dai_clkdiv,
1245         .set_sysclk = wm8400_set_dai_sysclk,
1246         .set_pll = wm8400_set_dai_pll,
1247 };
1248 
1249 /*
1250  * The WM8400 supports 2 different and mutually exclusive DAI
1251  * configurations.
1252  *
1253  * 1. ADC/DAC on Primary Interface
1254  * 2. ADC on Primary Interface/DAC on secondary
1255  */
1256 static struct snd_soc_dai_driver wm8400_dai = {
1257 /* ADC/DAC on primary */
1258         .name = "wm8400-hifi",
1259         .playback = {
1260                 .stream_name = "Playback",
1261                 .channels_min = 1,
1262                 .channels_max = 2,
1263                 .rates = WM8400_RATES,
1264                 .formats = WM8400_FORMATS,
1265         },
1266         .capture = {
1267                 .stream_name = "Capture",
1268                 .channels_min = 1,
1269                 .channels_max = 2,
1270                 .rates = WM8400_RATES,
1271                 .formats = WM8400_FORMATS,
1272         },
1273         .ops = &wm8400_dai_ops,
1274 };
1275 
1276 static int wm8400_codec_probe(struct snd_soc_codec *codec)
1277 {
1278         struct wm8400 *wm8400 = dev_get_platdata(codec->dev);
1279         struct wm8400_priv *priv;
1280         int ret;
1281         u16 reg;
1282 
1283         priv = devm_kzalloc(codec->dev, sizeof(struct wm8400_priv),
1284                             GFP_KERNEL);
1285         if (priv == NULL)
1286                 return -ENOMEM;
1287 
1288         snd_soc_codec_set_drvdata(codec, priv);
1289         priv->wm8400 = wm8400;
1290 
1291         ret = devm_regulator_bulk_get(wm8400->dev,
1292                                  ARRAY_SIZE(power), &power[0]);
1293         if (ret != 0) {
1294                 dev_err(codec->dev, "Failed to get regulators: %d\n", ret);
1295                 return ret;
1296         }
1297 
1298         wm8400_codec_reset(codec);
1299 
1300         reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1301         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA);
1302 
1303         /* Latch volume update bits */
1304         reg = snd_soc_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME);
1305         snd_soc_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
1306                      reg & WM8400_IPVU);
1307         reg = snd_soc_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME);
1308         snd_soc_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
1309                      reg & WM8400_IPVU);
1310 
1311         snd_soc_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1312         snd_soc_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1313 
1314         return 0;
1315 }
1316 
1317 static int  wm8400_codec_remove(struct snd_soc_codec *codec)
1318 {
1319         u16 reg;
1320 
1321         reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1322         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1,
1323                      reg & (~WM8400_CODEC_ENA));
1324 
1325         return 0;
1326 }
1327 
1328 static struct regmap *wm8400_get_regmap(struct device *dev)
1329 {
1330         struct wm8400 *wm8400 = dev_get_platdata(dev);
1331 
1332         return wm8400->regmap;
1333 }
1334 
1335 static struct snd_soc_codec_driver soc_codec_dev_wm8400 = {
1336         .probe =        wm8400_codec_probe,
1337         .remove =       wm8400_codec_remove,
1338         .get_regmap =   wm8400_get_regmap,
1339         .set_bias_level = wm8400_set_bias_level,
1340         .suspend_bias_off = true,
1341 
1342         .controls = wm8400_snd_controls,
1343         .num_controls = ARRAY_SIZE(wm8400_snd_controls),
1344         .dapm_widgets = wm8400_dapm_widgets,
1345         .num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets),
1346         .dapm_routes = wm8400_dapm_routes,
1347         .num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes),
1348 };
1349 
1350 static int wm8400_probe(struct platform_device *pdev)
1351 {
1352         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8400,
1353                         &wm8400_dai, 1);
1354 }
1355 
1356 static int wm8400_remove(struct platform_device *pdev)
1357 {
1358         snd_soc_unregister_codec(&pdev->dev);
1359         return 0;
1360 }
1361 
1362 static struct platform_driver wm8400_codec_driver = {
1363         .driver = {
1364                    .name = "wm8400-codec",
1365                    },
1366         .probe = wm8400_probe,
1367         .remove = wm8400_remove,
1368 };
1369 
1370 module_platform_driver(wm8400_codec_driver);
1371 
1372 MODULE_DESCRIPTION("ASoC WM8400 driver");
1373 MODULE_AUTHOR("Mark Brown");
1374 MODULE_LICENSE("GPL");
1375 MODULE_ALIAS("platform:wm8400-codec");
1376 

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