Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/sound/soc/codecs/wm8400.c

  1 /*
  2  * wm8400.c  --  WM8400 ALSA Soc Audio driver
  3  *
  4  * Copyright 2008-11 Wolfson Microelectronics PLC.
  5  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  6  *
  7  *  This program is free software; you can redistribute  it and/or modify it
  8  *  under  the terms of  the GNU General  Public License as published by the
  9  *  Free Software Foundation;  either version 2 of the  License, or (at your
 10  *  option) any later version.
 11  *
 12  */
 13 
 14 #include <linux/module.h>
 15 #include <linux/moduleparam.h>
 16 #include <linux/kernel.h>
 17 #include <linux/slab.h>
 18 #include <linux/init.h>
 19 #include <linux/delay.h>
 20 #include <linux/pm.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/regulator/consumer.h>
 23 #include <linux/mfd/wm8400-audio.h>
 24 #include <linux/mfd/wm8400-private.h>
 25 #include <linux/mfd/core.h>
 26 #include <sound/core.h>
 27 #include <sound/pcm.h>
 28 #include <sound/pcm_params.h>
 29 #include <sound/soc.h>
 30 #include <sound/initval.h>
 31 #include <sound/tlv.h>
 32 
 33 #include "wm8400.h"
 34 
 35 static struct regulator_bulk_data power[] = {
 36         {
 37                 .supply = "I2S1VDD",
 38         },
 39         {
 40                 .supply = "I2S2VDD",
 41         },
 42         {
 43                 .supply = "DCVDD",
 44         },
 45         {
 46                 .supply = "AVDD",
 47         },
 48         {
 49                 .supply = "FLLVDD",
 50         },
 51         {
 52                 .supply = "HPVDD",
 53         },
 54         {
 55                 .supply = "SPKVDD",
 56         },
 57 };
 58 
 59 /* codec private data */
 60 struct wm8400_priv {
 61         struct wm8400 *wm8400;
 62         u16 fake_register;
 63         unsigned int sysclk;
 64         unsigned int pcmclk;
 65         int fll_in, fll_out;
 66 };
 67 
 68 static void wm8400_codec_reset(struct snd_soc_codec *codec)
 69 {
 70         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
 71 
 72         wm8400_reset_codec_reg_cache(wm8400->wm8400);
 73 }
 74 
 75 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
 76 
 77 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
 78 
 79 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
 80 
 81 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
 82 
 83 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
 84 
 85 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
 86 
 87 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
 88 
 89 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
 90 
 91 static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
 92         struct snd_ctl_elem_value *ucontrol)
 93 {
 94         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 95         struct soc_mixer_control *mc =
 96                 (struct soc_mixer_control *)kcontrol->private_value;
 97         int reg = mc->reg;
 98         int ret;
 99         u16 val;
100 
101         ret = snd_soc_put_volsw(kcontrol, ucontrol);
102         if (ret < 0)
103                 return ret;
104 
105         /* now hit the volume update bits (always bit 8) */
106         val = snd_soc_read(codec, reg);
107         return snd_soc_write(codec, reg, val | 0x0100);
108 }
109 
110 #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
111         SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
112                 snd_soc_get_volsw, wm8400_outpga_put_volsw_vu, tlv_array)
113 
114 
115 static const char *wm8400_digital_sidetone[] =
116         {"None", "Left ADC", "Right ADC", "Reserved"};
117 
118 static SOC_ENUM_SINGLE_DECL(wm8400_left_digital_sidetone_enum,
119                             WM8400_DIGITAL_SIDE_TONE,
120                             WM8400_ADC_TO_DACL_SHIFT,
121                             wm8400_digital_sidetone);
122 
123 static SOC_ENUM_SINGLE_DECL(wm8400_right_digital_sidetone_enum,
124                             WM8400_DIGITAL_SIDE_TONE,
125                             WM8400_ADC_TO_DACR_SHIFT,
126                             wm8400_digital_sidetone);
127 
128 static const char *wm8400_adcmode[] =
129         {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
130 
131 static SOC_ENUM_SINGLE_DECL(wm8400_right_adcmode_enum,
132                             WM8400_ADC_CTRL,
133                             WM8400_ADC_HPF_CUT_SHIFT,
134                             wm8400_adcmode);
135 
136 static const struct snd_kcontrol_new wm8400_snd_controls[] = {
137 /* INMIXL */
138 SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT,
139            1, 0),
140 SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT,
141            1, 0),
142 /* INMIXR */
143 SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT,
144            1, 0),
145 SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT,
146            1, 0),
147 
148 /* LOMIX */
149 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
150         WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
151 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
152         WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv),
153 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
154         WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv),
155 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
156         WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
157 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
158         WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
159 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
160         WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
161 
162 /* ROMIX */
163 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
164         WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
165 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
166         WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv),
167 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
168         WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv),
169 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
170         WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
171 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
172         WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv),
173 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
174         WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv),
175 
176 /* LOUT */
177 WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME,
178         WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv),
179 SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0),
180 
181 /* ROUT */
182 WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME,
183         WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv),
184 SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0),
185 
186 /* LOPGA */
187 WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME,
188         WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv),
189 SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME,
190         WM8400_LOPGAZC_SHIFT, 1, 0),
191 
192 /* ROPGA */
193 WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME,
194         WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv),
195 SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME,
196         WM8400_ROPGAZC_SHIFT, 1, 0),
197 
198 SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
199         WM8400_LONMUTE_SHIFT, 1, 0),
200 SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
201         WM8400_LOPMUTE_SHIFT, 1, 0),
202 SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
203         WM8400_LOATTN_SHIFT, 1, 0),
204 SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
205         WM8400_RONMUTE_SHIFT, 1, 0),
206 SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
207         WM8400_ROPMUTE_SHIFT, 1, 0),
208 SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
209         WM8400_ROATTN_SHIFT, 1, 0),
210 
211 SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME,
212         WM8400_OUT3MUTE_SHIFT, 1, 0),
213 SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME,
214         WM8400_OUT3ATTN_SHIFT, 1, 0),
215 
216 SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME,
217         WM8400_OUT4MUTE_SHIFT, 1, 0),
218 SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME,
219         WM8400_OUT4ATTN_SHIFT, 1, 0),
220 
221 SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1,
222         WM8400_CDMODE_SHIFT, 1, 0),
223 
224 SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME,
225         WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0),
226 SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3,
227         WM8400_DCGAIN_SHIFT, 6, 0),
228 SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3,
229         WM8400_ACGAIN_SHIFT, 6, 0),
230 
231 WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
232         WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT,
233         127, 0, out_dac_tlv),
234 
235 WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
236         WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT,
237         127, 0, out_dac_tlv),
238 
239 SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum),
240 SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum),
241 
242 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
243         WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
244 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
245         WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
246 
247 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL,
248         WM8400_ADC_HPF_ENA_SHIFT, 1, 0),
249 
250 SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum),
251 
252 WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
253         WM8400_LEFT_ADC_DIGITAL_VOLUME,
254         WM8400_ADCL_VOL_SHIFT,
255         WM8400_ADCL_VOL_MASK,
256         0,
257         in_adc_tlv),
258 
259 WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
260         WM8400_RIGHT_ADC_DIGITAL_VOLUME,
261         WM8400_ADCR_VOL_SHIFT,
262         WM8400_ADCR_VOL_MASK,
263         0,
264         in_adc_tlv),
265 
266 WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
267         WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
268         WM8400_LIN12VOL_SHIFT,
269         WM8400_LIN12VOL_MASK,
270         0,
271         in_pga_tlv),
272 
273 SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
274         WM8400_LI12ZC_SHIFT, 1, 0),
275 
276 SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
277         WM8400_LI12MUTE_SHIFT, 1, 0),
278 
279 WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
280         WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
281         WM8400_LIN34VOL_SHIFT,
282         WM8400_LIN34VOL_MASK,
283         0,
284         in_pga_tlv),
285 
286 SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
287         WM8400_LI34ZC_SHIFT, 1, 0),
288 
289 SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
290         WM8400_LI34MUTE_SHIFT, 1, 0),
291 
292 WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
293         WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
294         WM8400_RIN12VOL_SHIFT,
295         WM8400_RIN12VOL_MASK,
296         0,
297         in_pga_tlv),
298 
299 SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
300         WM8400_RI12ZC_SHIFT, 1, 0),
301 
302 SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
303         WM8400_RI12MUTE_SHIFT, 1, 0),
304 
305 WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
306         WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
307         WM8400_RIN34VOL_SHIFT,
308         WM8400_RIN34VOL_MASK,
309         0,
310         in_pga_tlv),
311 
312 SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
313         WM8400_RI34ZC_SHIFT, 1, 0),
314 
315 SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
316         WM8400_RI34MUTE_SHIFT, 1, 0),
317 
318 };
319 
320 /*
321  * _DAPM_ Controls
322  */
323 
324 static int outmixer_event (struct snd_soc_dapm_widget *w,
325         struct snd_kcontrol * kcontrol, int event)
326 {
327         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
328         struct soc_mixer_control *mc =
329                 (struct soc_mixer_control *)kcontrol->private_value;
330         u32 reg_shift = mc->shift;
331         int ret = 0;
332         u16 reg;
333 
334         switch (reg_shift) {
335         case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) :
336                 reg = snd_soc_read(codec, WM8400_OUTPUT_MIXER1);
337                 if (reg & WM8400_LDLO) {
338                         printk(KERN_WARNING
339                         "Cannot set as Output Mixer 1 LDLO Set\n");
340                         ret = -1;
341                 }
342                 break;
343         case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8):
344                 reg = snd_soc_read(codec, WM8400_OUTPUT_MIXER2);
345                 if (reg & WM8400_RDRO) {
346                         printk(KERN_WARNING
347                         "Cannot set as Output Mixer 2 RDRO Set\n");
348                         ret = -1;
349                 }
350                 break;
351         case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8):
352                 reg = snd_soc_read(codec, WM8400_SPEAKER_MIXER);
353                 if (reg & WM8400_LDSPK) {
354                         printk(KERN_WARNING
355                         "Cannot set as Speaker Mixer LDSPK Set\n");
356                         ret = -1;
357                 }
358                 break;
359         case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8):
360                 reg = snd_soc_read(codec, WM8400_SPEAKER_MIXER);
361                 if (reg & WM8400_RDSPK) {
362                         printk(KERN_WARNING
363                         "Cannot set as Speaker Mixer RDSPK Set\n");
364                         ret = -1;
365                 }
366                 break;
367         }
368 
369         return ret;
370 }
371 
372 /* INMIX dB values */
373 static const unsigned int in_mix_tlv[] = {
374         TLV_DB_RANGE_HEAD(1),
375         0,7, TLV_DB_SCALE_ITEM(-1200, 600, 0),
376 };
377 
378 /* Left In PGA Connections */
379 static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = {
380 SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0),
381 SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0),
382 };
383 
384 static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = {
385 SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0),
386 SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0),
387 };
388 
389 /* Right In PGA Connections */
390 static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = {
391 SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0),
392 SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0),
393 };
394 
395 static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = {
396 SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0),
397 SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0),
398 };
399 
400 /* INMIXL */
401 static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = {
402 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3,
403         WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv),
404 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT,
405         7, 0, in_mix_tlv),
406 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
407                 1, 0),
408 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
409                 1, 0),
410 };
411 
412 /* INMIXR */
413 static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = {
414 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4,
415         WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv),
416 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT,
417         7, 0, in_mix_tlv),
418 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
419         1, 0),
420 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
421         1, 0),
422 };
423 
424 /* AINLMUX */
425 static const char *wm8400_ainlmux[] =
426         {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
427 
428 static SOC_ENUM_SINGLE_DECL(wm8400_ainlmux_enum,
429                             WM8400_INPUT_MIXER1,
430                             WM8400_AINLMODE_SHIFT,
431                             wm8400_ainlmux);
432 
433 static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls =
434 SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum);
435 
436 /* DIFFINL */
437 
438 /* AINRMUX */
439 static const char *wm8400_ainrmux[] =
440         {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
441 
442 static SOC_ENUM_SINGLE_DECL(wm8400_ainrmux_enum,
443                             WM8400_INPUT_MIXER1,
444                             WM8400_AINRMODE_SHIFT,
445                             wm8400_ainrmux);
446 
447 static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls =
448 SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum);
449 
450 /* RXVOICE */
451 static const struct snd_kcontrol_new wm8400_dapm_rxvoice_controls[] = {
452 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8400_INPUT_MIXER5, WM8400_LR4BVOL_SHIFT,
453                         WM8400_LR4BVOL_MASK, 0, in_mix_tlv),
454 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8400_INPUT_MIXER6, WM8400_RL4BVOL_SHIFT,
455                         WM8400_RL4BVOL_MASK, 0, in_mix_tlv),
456 };
457 
458 /* LOMIX */
459 static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = {
460 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
461         WM8400_LRBLO_SHIFT, 1, 0),
462 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
463         WM8400_LLBLO_SHIFT, 1, 0),
464 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
465         WM8400_LRI3LO_SHIFT, 1, 0),
466 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
467         WM8400_LLI3LO_SHIFT, 1, 0),
468 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
469         WM8400_LR12LO_SHIFT, 1, 0),
470 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
471         WM8400_LL12LO_SHIFT, 1, 0),
472 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1,
473         WM8400_LDLO_SHIFT, 1, 0),
474 };
475 
476 /* ROMIX */
477 static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = {
478 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
479         WM8400_RLBRO_SHIFT, 1, 0),
480 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
481         WM8400_RRBRO_SHIFT, 1, 0),
482 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
483         WM8400_RLI3RO_SHIFT, 1, 0),
484 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
485         WM8400_RRI3RO_SHIFT, 1, 0),
486 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
487         WM8400_RL12RO_SHIFT, 1, 0),
488 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
489         WM8400_RR12RO_SHIFT, 1, 0),
490 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2,
491         WM8400_RDRO_SHIFT, 1, 0),
492 };
493 
494 /* LONMIX */
495 static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = {
496 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
497         WM8400_LLOPGALON_SHIFT, 1, 0),
498 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1,
499         WM8400_LROPGALON_SHIFT, 1, 0),
500 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1,
501         WM8400_LOPLON_SHIFT, 1, 0),
502 };
503 
504 /* LOPMIX */
505 static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = {
506 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1,
507         WM8400_LR12LOP_SHIFT, 1, 0),
508 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1,
509         WM8400_LL12LOP_SHIFT, 1, 0),
510 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
511         WM8400_LLOPGALOP_SHIFT, 1, 0),
512 };
513 
514 /* RONMIX */
515 static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = {
516 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
517         WM8400_RROPGARON_SHIFT, 1, 0),
518 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2,
519         WM8400_RLOPGARON_SHIFT, 1, 0),
520 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2,
521         WM8400_ROPRON_SHIFT, 1, 0),
522 };
523 
524 /* ROPMIX */
525 static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = {
526 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2,
527         WM8400_RL12ROP_SHIFT, 1, 0),
528 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2,
529         WM8400_RR12ROP_SHIFT, 1, 0),
530 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
531         WM8400_RROPGAROP_SHIFT, 1, 0),
532 };
533 
534 /* OUT3MIX */
535 static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = {
536 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
537         WM8400_LI4O3_SHIFT, 1, 0),
538 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER,
539         WM8400_LPGAO3_SHIFT, 1, 0),
540 };
541 
542 /* OUT4MIX */
543 static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = {
544 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER,
545         WM8400_RPGAO4_SHIFT, 1, 0),
546 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
547         WM8400_RI4O4_SHIFT, 1, 0),
548 };
549 
550 /* SPKMIX */
551 static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = {
552 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
553         WM8400_LI2SPK_SHIFT, 1, 0),
554 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER,
555         WM8400_LB2SPK_SHIFT, 1, 0),
556 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER,
557         WM8400_LOPGASPK_SHIFT, 1, 0),
558 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER,
559         WM8400_LDSPK_SHIFT, 1, 0),
560 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER,
561         WM8400_RDSPK_SHIFT, 1, 0),
562 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER,
563         WM8400_ROPGASPK_SHIFT, 1, 0),
564 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER,
565         WM8400_RL12ROP_SHIFT, 1, 0),
566 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
567         WM8400_RI2SPK_SHIFT, 1, 0),
568 };
569 
570 static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = {
571 /* Input Side */
572 /* Input Lines */
573 SND_SOC_DAPM_INPUT("LIN1"),
574 SND_SOC_DAPM_INPUT("LIN2"),
575 SND_SOC_DAPM_INPUT("LIN3"),
576 SND_SOC_DAPM_INPUT("LIN4/RXN"),
577 SND_SOC_DAPM_INPUT("RIN3"),
578 SND_SOC_DAPM_INPUT("RIN4/RXP"),
579 SND_SOC_DAPM_INPUT("RIN1"),
580 SND_SOC_DAPM_INPUT("RIN2"),
581 SND_SOC_DAPM_INPUT("Internal ADC Source"),
582 
583 /* DACs */
584 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2,
585         WM8400_ADCL_ENA_SHIFT, 0),
586 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2,
587         WM8400_ADCR_ENA_SHIFT, 0),
588 
589 /* Input PGAs */
590 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2,
591                    WM8400_LIN12_ENA_SHIFT,
592                    0, &wm8400_dapm_lin12_pga_controls[0],
593                    ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)),
594 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2,
595                    WM8400_LIN34_ENA_SHIFT,
596                    0, &wm8400_dapm_lin34_pga_controls[0],
597                    ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)),
598 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2,
599                    WM8400_RIN12_ENA_SHIFT,
600                    0, &wm8400_dapm_rin12_pga_controls[0],
601                    ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)),
602 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2,
603                    WM8400_RIN34_ENA_SHIFT,
604                    0, &wm8400_dapm_rin34_pga_controls[0],
605                    ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)),
606 
607 SND_SOC_DAPM_SUPPLY("INL", WM8400_POWER_MANAGEMENT_2, WM8400_AINL_ENA_SHIFT,
608                     0, NULL, 0),
609 SND_SOC_DAPM_SUPPLY("INR", WM8400_POWER_MANAGEMENT_2, WM8400_AINR_ENA_SHIFT,
610                     0, NULL, 0),
611 
612 /* INMIXL */
613 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
614         &wm8400_dapm_inmixl_controls[0],
615         ARRAY_SIZE(wm8400_dapm_inmixl_controls)),
616 
617 /* AINLMUX */
618 SND_SOC_DAPM_MUX("AILNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainlmux_controls),
619 
620 /* INMIXR */
621 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
622         &wm8400_dapm_inmixr_controls[0],
623         ARRAY_SIZE(wm8400_dapm_inmixr_controls)),
624 
625 /* AINRMUX */
626 SND_SOC_DAPM_MUX("AIRNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainrmux_controls),
627 
628 /* Output Side */
629 /* DACs */
630 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3,
631         WM8400_DACL_ENA_SHIFT, 0),
632 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3,
633         WM8400_DACR_ENA_SHIFT, 0),
634 
635 /* LOMIX */
636 SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3,
637                      WM8400_LOMIX_ENA_SHIFT,
638                      0, &wm8400_dapm_lomix_controls[0],
639                      ARRAY_SIZE(wm8400_dapm_lomix_controls),
640                      outmixer_event, SND_SOC_DAPM_PRE_REG),
641 
642 /* LONMIX */
643 SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT,
644                    0, &wm8400_dapm_lonmix_controls[0],
645                    ARRAY_SIZE(wm8400_dapm_lonmix_controls)),
646 
647 /* LOPMIX */
648 SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT,
649                    0, &wm8400_dapm_lopmix_controls[0],
650                    ARRAY_SIZE(wm8400_dapm_lopmix_controls)),
651 
652 /* OUT3MIX */
653 SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT,
654                    0, &wm8400_dapm_out3mix_controls[0],
655                    ARRAY_SIZE(wm8400_dapm_out3mix_controls)),
656 
657 /* SPKMIX */
658 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT,
659                      0, &wm8400_dapm_spkmix_controls[0],
660                      ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event,
661                      SND_SOC_DAPM_PRE_REG),
662 
663 /* OUT4MIX */
664 SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT,
665         0, &wm8400_dapm_out4mix_controls[0],
666         ARRAY_SIZE(wm8400_dapm_out4mix_controls)),
667 
668 /* ROPMIX */
669 SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT,
670                    0, &wm8400_dapm_ropmix_controls[0],
671                    ARRAY_SIZE(wm8400_dapm_ropmix_controls)),
672 
673 /* RONMIX */
674 SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT,
675                    0, &wm8400_dapm_ronmix_controls[0],
676                    ARRAY_SIZE(wm8400_dapm_ronmix_controls)),
677 
678 /* ROMIX */
679 SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3,
680                      WM8400_ROMIX_ENA_SHIFT,
681                      0, &wm8400_dapm_romix_controls[0],
682                      ARRAY_SIZE(wm8400_dapm_romix_controls),
683                      outmixer_event, SND_SOC_DAPM_PRE_REG),
684 
685 /* LOUT PGA */
686 SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT,
687                  0, NULL, 0),
688 
689 /* ROUT PGA */
690 SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT,
691                  0, NULL, 0),
692 
693 /* LOPGA */
694 SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0,
695         NULL, 0),
696 
697 /* ROPGA */
698 SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0,
699         NULL, 0),
700 
701 /* MICBIAS */
702 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8400_POWER_MANAGEMENT_1,
703                     WM8400_MIC1BIAS_ENA_SHIFT, 0, NULL, 0),
704 
705 SND_SOC_DAPM_OUTPUT("LON"),
706 SND_SOC_DAPM_OUTPUT("LOP"),
707 SND_SOC_DAPM_OUTPUT("OUT3"),
708 SND_SOC_DAPM_OUTPUT("LOUT"),
709 SND_SOC_DAPM_OUTPUT("SPKN"),
710 SND_SOC_DAPM_OUTPUT("SPKP"),
711 SND_SOC_DAPM_OUTPUT("ROUT"),
712 SND_SOC_DAPM_OUTPUT("OUT4"),
713 SND_SOC_DAPM_OUTPUT("ROP"),
714 SND_SOC_DAPM_OUTPUT("RON"),
715 
716 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
717 };
718 
719 static const struct snd_soc_dapm_route wm8400_dapm_routes[] = {
720         /* Make DACs turn on when playing even if not mixed into any outputs */
721         {"Internal DAC Sink", NULL, "Left DAC"},
722         {"Internal DAC Sink", NULL, "Right DAC"},
723 
724         /* Make ADCs turn on when recording
725          * even if not mixed from any inputs */
726         {"Left ADC", NULL, "Internal ADC Source"},
727         {"Right ADC", NULL, "Internal ADC Source"},
728 
729         /* Input Side */
730         /* LIN12 PGA */
731         {"LIN12 PGA", "LIN1 Switch", "LIN1"},
732         {"LIN12 PGA", "LIN2 Switch", "LIN2"},
733         /* LIN34 PGA */
734         {"LIN34 PGA", "LIN3 Switch", "LIN3"},
735         {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
736         /* INMIXL */
737         {"INMIXL", NULL, "INL"},
738         {"INMIXL", "Record Left Volume", "LOMIX"},
739         {"INMIXL", "LIN2 Volume", "LIN2"},
740         {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
741         {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
742         /* AILNMUX */
743         {"AILNMUX", NULL, "INL"},
744         {"AILNMUX", "INMIXL Mix", "INMIXL"},
745         {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"},
746         {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"},
747         {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
748         {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
749         /* ADC */
750         {"Left ADC", NULL, "AILNMUX"},
751 
752         /* RIN12 PGA */
753         {"RIN12 PGA", "RIN1 Switch", "RIN1"},
754         {"RIN12 PGA", "RIN2 Switch", "RIN2"},
755         /* RIN34 PGA */
756         {"RIN34 PGA", "RIN3 Switch", "RIN3"},
757         {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
758         /* INMIXR */
759         {"INMIXR", NULL, "INR"},
760         {"INMIXR", "Record Right Volume", "ROMIX"},
761         {"INMIXR", "RIN2 Volume", "RIN2"},
762         {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
763         {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
764         /* AIRNMUX */
765         {"AIRNMUX", NULL, "INR"},
766         {"AIRNMUX", "INMIXR Mix", "INMIXR"},
767         {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"},
768         {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"},
769         {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"},
770         {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
771         /* ADC */
772         {"Right ADC", NULL, "AIRNMUX"},
773 
774         /* LOMIX */
775         {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
776         {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
777         {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
778         {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
779         {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"},
780         {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"},
781         {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
782 
783         /* ROMIX */
784         {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
785         {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
786         {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
787         {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
788         {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"},
789         {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"},
790         {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
791 
792         /* SPKMIX */
793         {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
794         {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
795         {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"},
796         {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"},
797         {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
798         {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
799         {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
800         {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
801 
802         /* LONMIX */
803         {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
804         {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
805         {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
806 
807         /* LOPMIX */
808         {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
809         {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
810         {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
811 
812         /* OUT3MIX */
813         {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
814         {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
815 
816         /* OUT4MIX */
817         {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
818         {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
819 
820         /* RONMIX */
821         {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
822         {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
823         {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
824 
825         /* ROPMIX */
826         {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
827         {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
828         {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
829 
830         /* Out Mixer PGAs */
831         {"LOPGA", NULL, "LOMIX"},
832         {"ROPGA", NULL, "ROMIX"},
833 
834         {"LOUT PGA", NULL, "LOMIX"},
835         {"ROUT PGA", NULL, "ROMIX"},
836 
837         /* Output Pins */
838         {"LON", NULL, "LONMIX"},
839         {"LOP", NULL, "LOPMIX"},
840         {"OUT3", NULL, "OUT3MIX"},
841         {"LOUT", NULL, "LOUT PGA"},
842         {"SPKN", NULL, "SPKMIX"},
843         {"ROUT", NULL, "ROUT PGA"},
844         {"OUT4", NULL, "OUT4MIX"},
845         {"ROP", NULL, "ROPMIX"},
846         {"RON", NULL, "RONMIX"},
847 };
848 
849 /*
850  * Clock after FLL and dividers
851  */
852 static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai,
853                 int clk_id, unsigned int freq, int dir)
854 {
855         struct snd_soc_codec *codec = codec_dai->codec;
856         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
857 
858         wm8400->sysclk = freq;
859         return 0;
860 }
861 
862 struct fll_factors {
863         u16 n;
864         u16 k;
865         u16 outdiv;
866         u16 fratio;
867         u16 freq_ref;
868 };
869 
870 #define FIXED_FLL_SIZE ((1 << 16) * 10)
871 
872 static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors,
873                        unsigned int Fref, unsigned int Fout)
874 {
875         u64 Kpart;
876         unsigned int K, Nmod, target;
877 
878         factors->outdiv = 2;
879         while (Fout * factors->outdiv <  90000000 ||
880                Fout * factors->outdiv > 100000000) {
881                 factors->outdiv *= 2;
882                 if (factors->outdiv > 32) {
883                         dev_err(wm8400->wm8400->dev,
884                                 "Unsupported FLL output frequency %uHz\n",
885                                 Fout);
886                         return -EINVAL;
887                 }
888         }
889         target = Fout * factors->outdiv;
890         factors->outdiv = factors->outdiv >> 2;
891 
892         if (Fref < 48000)
893                 factors->freq_ref = 1;
894         else
895                 factors->freq_ref = 0;
896 
897         if (Fref < 1000000)
898                 factors->fratio = 9;
899         else
900                 factors->fratio = 0;
901 
902         /* Ensure we have a fractional part */
903         do {
904                 if (Fref < 1000000)
905                         factors->fratio--;
906                 else
907                         factors->fratio++;
908 
909                 if (factors->fratio < 1 || factors->fratio > 8) {
910                         dev_err(wm8400->wm8400->dev,
911                                 "Unable to calculate FRATIO\n");
912                         return -EINVAL;
913                 }
914 
915                 factors->n = target / (Fref * factors->fratio);
916                 Nmod = target % (Fref * factors->fratio);
917         } while (Nmod == 0);
918 
919         /* Calculate fractional part - scale up so we can round. */
920         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
921 
922         do_div(Kpart, (Fref * factors->fratio));
923 
924         K = Kpart & 0xFFFFFFFF;
925 
926         if ((K % 10) >= 5)
927                 K += 5;
928 
929         /* Move down to proper range now rounding is done */
930         factors->k = K / 10;
931 
932         dev_dbg(wm8400->wm8400->dev,
933                 "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n",
934                 Fref, Fout,
935                 factors->n, factors->k, factors->fratio, factors->outdiv);
936 
937         return 0;
938 }
939 
940 static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
941                               int source, unsigned int freq_in,
942                               unsigned int freq_out)
943 {
944         struct snd_soc_codec *codec = codec_dai->codec;
945         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
946         struct fll_factors factors;
947         int ret;
948         u16 reg;
949 
950         if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out)
951                 return 0;
952 
953         if (freq_out) {
954                 ret = fll_factors(wm8400, &factors, freq_in, freq_out);
955                 if (ret != 0)
956                         return ret;
957         } else {
958                 /* Bodge GCC 4.4.0 uninitialised variable warning - it
959                  * doesn't seem capable of working out that we exit if
960                  * freq_out is 0 before any of the uses. */
961                 memset(&factors, 0, sizeof(factors));
962         }
963 
964         wm8400->fll_out = freq_out;
965         wm8400->fll_in = freq_in;
966 
967         /* We *must* disable the FLL before any changes */
968         reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_2);
969         reg &= ~WM8400_FLL_ENA;
970         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_2, reg);
971 
972         reg = snd_soc_read(codec, WM8400_FLL_CONTROL_1);
973         reg &= ~WM8400_FLL_OSC_ENA;
974         snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg);
975 
976         if (!freq_out)
977                 return 0;
978 
979         reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK);
980         reg |= WM8400_FLL_FRAC | factors.fratio;
981         reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT;
982         snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg);
983 
984         snd_soc_write(codec, WM8400_FLL_CONTROL_2, factors.k);
985         snd_soc_write(codec, WM8400_FLL_CONTROL_3, factors.n);
986 
987         reg = snd_soc_read(codec, WM8400_FLL_CONTROL_4);
988         reg &= ~WM8400_FLL_OUTDIV_MASK;
989         reg |= factors.outdiv;
990         snd_soc_write(codec, WM8400_FLL_CONTROL_4, reg);
991 
992         return 0;
993 }
994 
995 /*
996  * Sets ADC and Voice DAC format.
997  */
998 static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
999                 unsigned int fmt)
1000 {
1001         struct snd_soc_codec *codec = codec_dai->codec;
1002         u16 audio1, audio3;
1003 
1004         audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1);
1005         audio3 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_3);
1006 
1007         /* set master/slave audio interface */
1008         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1009         case SND_SOC_DAIFMT_CBS_CFS:
1010                 audio3 &= ~WM8400_AIF_MSTR1;
1011                 break;
1012         case SND_SOC_DAIFMT_CBM_CFM:
1013                 audio3 |= WM8400_AIF_MSTR1;
1014                 break;
1015         default:
1016                 return -EINVAL;
1017         }
1018 
1019         audio1 &= ~WM8400_AIF_FMT_MASK;
1020 
1021         /* interface format */
1022         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1023         case SND_SOC_DAIFMT_I2S:
1024                 audio1 |= WM8400_AIF_FMT_I2S;
1025                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1026                 break;
1027         case SND_SOC_DAIFMT_RIGHT_J:
1028                 audio1 |= WM8400_AIF_FMT_RIGHTJ;
1029                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1030                 break;
1031         case SND_SOC_DAIFMT_LEFT_J:
1032                 audio1 |= WM8400_AIF_FMT_LEFTJ;
1033                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1034                 break;
1035         case SND_SOC_DAIFMT_DSP_A:
1036                 audio1 |= WM8400_AIF_FMT_DSP;
1037                 audio1 &= ~WM8400_AIF_LRCLK_INV;
1038                 break;
1039         case SND_SOC_DAIFMT_DSP_B:
1040                 audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV;
1041                 break;
1042         default:
1043                 return -EINVAL;
1044         }
1045 
1046         snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1047         snd_soc_write(codec, WM8400_AUDIO_INTERFACE_3, audio3);
1048         return 0;
1049 }
1050 
1051 static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1052                 int div_id, int div)
1053 {
1054         struct snd_soc_codec *codec = codec_dai->codec;
1055         u16 reg;
1056 
1057         switch (div_id) {
1058         case WM8400_MCLK_DIV:
1059                 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1060                         ~WM8400_MCLK_DIV_MASK;
1061                 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1062                 break;
1063         case WM8400_DACCLK_DIV:
1064                 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1065                         ~WM8400_DAC_CLKDIV_MASK;
1066                 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1067                 break;
1068         case WM8400_ADCCLK_DIV:
1069                 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1070                         ~WM8400_ADC_CLKDIV_MASK;
1071                 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1072                 break;
1073         case WM8400_BCLK_DIV:
1074                 reg = snd_soc_read(codec, WM8400_CLOCKING_1) &
1075                         ~WM8400_BCLK_DIV_MASK;
1076                 snd_soc_write(codec, WM8400_CLOCKING_1, reg | div);
1077                 break;
1078         default:
1079                 return -EINVAL;
1080         }
1081 
1082         return 0;
1083 }
1084 
1085 /*
1086  * Set PCM DAI bit size and sample rate.
1087  */
1088 static int wm8400_hw_params(struct snd_pcm_substream *substream,
1089         struct snd_pcm_hw_params *params,
1090         struct snd_soc_dai *dai)
1091 {
1092         struct snd_soc_codec *codec = dai->codec;
1093         u16 audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1);
1094 
1095         audio1 &= ~WM8400_AIF_WL_MASK;
1096         /* bit size */
1097         switch (params_width(params)) {
1098         case 16:
1099                 break;
1100         case 20:
1101                 audio1 |= WM8400_AIF_WL_20BITS;
1102                 break;
1103         case 24:
1104                 audio1 |= WM8400_AIF_WL_24BITS;
1105                 break;
1106         case 32:
1107                 audio1 |= WM8400_AIF_WL_32BITS;
1108                 break;
1109         }
1110 
1111         snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1112         return 0;
1113 }
1114 
1115 static int wm8400_mute(struct snd_soc_dai *dai, int mute)
1116 {
1117         struct snd_soc_codec *codec = dai->codec;
1118         u16 val = snd_soc_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE;
1119 
1120         if (mute)
1121                 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1122         else
1123                 snd_soc_write(codec, WM8400_DAC_CTRL, val);
1124 
1125         return 0;
1126 }
1127 
1128 /* TODO: set bias for best performance at standby */
1129 static int wm8400_set_bias_level(struct snd_soc_codec *codec,
1130                                  enum snd_soc_bias_level level)
1131 {
1132         struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
1133         u16 val;
1134         int ret;
1135 
1136         switch (level) {
1137         case SND_SOC_BIAS_ON:
1138                 break;
1139 
1140         case SND_SOC_BIAS_PREPARE:
1141                 /* VMID=2*50k */
1142                 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) &
1143                         ~WM8400_VMID_MODE_MASK;
1144                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2);
1145                 break;
1146 
1147         case SND_SOC_BIAS_STANDBY:
1148                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1149                         ret = regulator_bulk_enable(ARRAY_SIZE(power),
1150                                                     &power[0]);
1151                         if (ret != 0) {
1152                                 dev_err(wm8400->wm8400->dev,
1153                                         "Failed to enable regulators: %d\n",
1154                                         ret);
1155                                 return ret;
1156                         }
1157 
1158                         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1,
1159                                      WM8400_CODEC_ENA | WM8400_SYSCLK_ENA);
1160 
1161                         /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1162                         snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1163                                      WM8400_BUFDCOPEN | WM8400_POBCTRL);
1164 
1165                         msleep(50);
1166 
1167                         /* Enable VREF & VMID at 2x50k */
1168                         val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1169                         val |= 0x2 | WM8400_VREF_ENA;
1170                         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1171 
1172                         /* Enable BUFIOEN */
1173                         snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1174                                      WM8400_BUFDCOPEN | WM8400_POBCTRL |
1175                                      WM8400_BUFIOEN);
1176 
1177                         /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1178                         snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN);
1179                 }
1180 
1181                 /* VMID=2*300k */
1182                 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) &
1183                         ~WM8400_VMID_MODE_MASK;
1184                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4);
1185                 break;
1186 
1187         case SND_SOC_BIAS_OFF:
1188                 /* Enable POBCTRL and SOFT_ST */
1189                 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1190                         WM8400_POBCTRL | WM8400_BUFIOEN);
1191 
1192                 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1193                 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1194                         WM8400_BUFDCOPEN | WM8400_POBCTRL |
1195                         WM8400_BUFIOEN);
1196 
1197                 /* mute DAC */
1198                 val = snd_soc_read(codec, WM8400_DAC_CTRL);
1199                 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1200 
1201                 /* Enable any disabled outputs */
1202                 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1203                 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
1204                         WM8400_OUT4_ENA | WM8400_LOUT_ENA |
1205                         WM8400_ROUT_ENA;
1206                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1207 
1208                 /* Disable VMID */
1209                 val &= ~WM8400_VMID_MODE_MASK;
1210                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1211 
1212                 msleep(300);
1213 
1214                 /* Enable all output discharge bits */
1215                 snd_soc_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
1216                         WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
1217                         WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
1218                         WM8400_DIS_ROUT);
1219 
1220                 /* Disable VREF */
1221                 val &= ~WM8400_VREF_ENA;
1222                 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1223 
1224                 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1225                 snd_soc_write(codec, WM8400_ANTIPOP2, 0x0);
1226 
1227                 ret = regulator_bulk_disable(ARRAY_SIZE(power),
1228                                              &power[0]);
1229                 if (ret != 0)
1230                         return ret;
1231 
1232                 break;
1233         }
1234 
1235         codec->dapm.bias_level = level;
1236         return 0;
1237 }
1238 
1239 #define WM8400_RATES SNDRV_PCM_RATE_8000_96000
1240 
1241 #define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1242         SNDRV_PCM_FMTBIT_S24_LE)
1243 
1244 static const struct snd_soc_dai_ops wm8400_dai_ops = {
1245         .hw_params = wm8400_hw_params,
1246         .digital_mute = wm8400_mute,
1247         .set_fmt = wm8400_set_dai_fmt,
1248         .set_clkdiv = wm8400_set_dai_clkdiv,
1249         .set_sysclk = wm8400_set_dai_sysclk,
1250         .set_pll = wm8400_set_dai_pll,
1251 };
1252 
1253 /*
1254  * The WM8400 supports 2 different and mutually exclusive DAI
1255  * configurations.
1256  *
1257  * 1. ADC/DAC on Primary Interface
1258  * 2. ADC on Primary Interface/DAC on secondary
1259  */
1260 static struct snd_soc_dai_driver wm8400_dai = {
1261 /* ADC/DAC on primary */
1262         .name = "wm8400-hifi",
1263         .playback = {
1264                 .stream_name = "Playback",
1265                 .channels_min = 1,
1266                 .channels_max = 2,
1267                 .rates = WM8400_RATES,
1268                 .formats = WM8400_FORMATS,
1269         },
1270         .capture = {
1271                 .stream_name = "Capture",
1272                 .channels_min = 1,
1273                 .channels_max = 2,
1274                 .rates = WM8400_RATES,
1275                 .formats = WM8400_FORMATS,
1276         },
1277         .ops = &wm8400_dai_ops,
1278 };
1279 
1280 static int wm8400_codec_probe(struct snd_soc_codec *codec)
1281 {
1282         struct wm8400 *wm8400 = dev_get_platdata(codec->dev);
1283         struct wm8400_priv *priv;
1284         int ret;
1285         u16 reg;
1286 
1287         priv = devm_kzalloc(codec->dev, sizeof(struct wm8400_priv),
1288                             GFP_KERNEL);
1289         if (priv == NULL)
1290                 return -ENOMEM;
1291 
1292         snd_soc_codec_set_drvdata(codec, priv);
1293         priv->wm8400 = wm8400;
1294 
1295         ret = devm_regulator_bulk_get(wm8400->dev,
1296                                  ARRAY_SIZE(power), &power[0]);
1297         if (ret != 0) {
1298                 dev_err(codec->dev, "Failed to get regulators: %d\n", ret);
1299                 return ret;
1300         }
1301 
1302         wm8400_codec_reset(codec);
1303 
1304         reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1305         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA);
1306 
1307         /* Latch volume update bits */
1308         reg = snd_soc_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME);
1309         snd_soc_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
1310                      reg & WM8400_IPVU);
1311         reg = snd_soc_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME);
1312         snd_soc_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
1313                      reg & WM8400_IPVU);
1314 
1315         snd_soc_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1316         snd_soc_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1317 
1318         return 0;
1319 }
1320 
1321 static int  wm8400_codec_remove(struct snd_soc_codec *codec)
1322 {
1323         u16 reg;
1324 
1325         reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1326         snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1,
1327                      reg & (~WM8400_CODEC_ENA));
1328 
1329         return 0;
1330 }
1331 
1332 static struct regmap *wm8400_get_regmap(struct device *dev)
1333 {
1334         struct wm8400 *wm8400 = dev_get_platdata(dev);
1335 
1336         return wm8400->regmap;
1337 }
1338 
1339 static struct snd_soc_codec_driver soc_codec_dev_wm8400 = {
1340         .probe =        wm8400_codec_probe,
1341         .remove =       wm8400_codec_remove,
1342         .get_regmap =   wm8400_get_regmap,
1343         .set_bias_level = wm8400_set_bias_level,
1344         .suspend_bias_off = true,
1345 
1346         .controls = wm8400_snd_controls,
1347         .num_controls = ARRAY_SIZE(wm8400_snd_controls),
1348         .dapm_widgets = wm8400_dapm_widgets,
1349         .num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets),
1350         .dapm_routes = wm8400_dapm_routes,
1351         .num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes),
1352 };
1353 
1354 static int wm8400_probe(struct platform_device *pdev)
1355 {
1356         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8400,
1357                         &wm8400_dai, 1);
1358 }
1359 
1360 static int wm8400_remove(struct platform_device *pdev)
1361 {
1362         snd_soc_unregister_codec(&pdev->dev);
1363         return 0;
1364 }
1365 
1366 static struct platform_driver wm8400_codec_driver = {
1367         .driver = {
1368                    .name = "wm8400-codec",
1369                    },
1370         .probe = wm8400_probe,
1371         .remove = wm8400_remove,
1372 };
1373 
1374 module_platform_driver(wm8400_codec_driver);
1375 
1376 MODULE_DESCRIPTION("ASoC WM8400 driver");
1377 MODULE_AUTHOR("Mark Brown");
1378 MODULE_LICENSE("GPL");
1379 MODULE_ALIAS("platform:wm8400-codec");
1380 

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