Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/sound/soc/codecs/tlv320aic32x4.c

  1 /*
  2  * linux/sound/soc/codecs/tlv320aic32x4.c
  3  *
  4  * Copyright 2011 Vista Silicon S.L.
  5  *
  6  * Author: Javier Martin <javier.martin@vista-silicon.com>
  7  *
  8  * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License as published by
 12  * the Free Software Foundation; either version 2 of the License, or
 13  * (at your option) any later version.
 14  *
 15  * This program is distributed in the hope that it will be useful,
 16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 18  * GNU General Public License for more details.
 19  *
 20  * You should have received a copy of the GNU General Public License
 21  * along with this program; if not, write to the Free Software
 22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 23  * MA 02110-1301, USA.
 24  */
 25 
 26 #include <linux/module.h>
 27 #include <linux/moduleparam.h>
 28 #include <linux/init.h>
 29 #include <linux/delay.h>
 30 #include <linux/pm.h>
 31 #include <linux/gpio.h>
 32 #include <linux/of_gpio.h>
 33 #include <linux/cdev.h>
 34 #include <linux/slab.h>
 35 #include <linux/clk.h>
 36 #include <linux/regulator/consumer.h>
 37 
 38 #include <sound/tlv320aic32x4.h>
 39 #include <sound/core.h>
 40 #include <sound/pcm.h>
 41 #include <sound/pcm_params.h>
 42 #include <sound/soc.h>
 43 #include <sound/soc-dapm.h>
 44 #include <sound/initval.h>
 45 #include <sound/tlv.h>
 46 
 47 #include "tlv320aic32x4.h"
 48 
 49 struct aic32x4_rate_divs {
 50         u32 mclk;
 51         u32 rate;
 52         u8 p_val;
 53         u8 pll_j;
 54         u16 pll_d;
 55         u16 dosr;
 56         u8 ndac;
 57         u8 mdac;
 58         u8 aosr;
 59         u8 nadc;
 60         u8 madc;
 61         u8 blck_N;
 62 };
 63 
 64 struct aic32x4_priv {
 65         struct regmap *regmap;
 66         u32 sysclk;
 67         u32 power_cfg;
 68         u32 micpga_routing;
 69         bool swapdacs;
 70         int rstn_gpio;
 71         struct clk *mclk;
 72 
 73         struct regulator *supply_ldo;
 74         struct regulator *supply_iov;
 75         struct regulator *supply_dv;
 76         struct regulator *supply_av;
 77 };
 78 
 79 /* 0dB min, 0.5dB steps */
 80 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
 81 /* -63.5dB min, 0.5dB steps */
 82 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
 83 /* -6dB min, 1dB steps */
 84 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
 85 /* -12dB min, 0.5dB steps */
 86 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
 87 
 88 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
 89         SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
 90                         AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
 91         SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
 92                         AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
 93                         tlv_driver_gain),
 94         SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
 95                         AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
 96                         tlv_driver_gain),
 97         SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
 98                         AIC32X4_HPRGAIN, 6, 0x01, 1),
 99         SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
100                         AIC32X4_LORGAIN, 6, 0x01, 1),
101         SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
102                         AIC32X4_RMICPGAVOL, 7, 0x01, 1),
103 
104         SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
105         SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
106 
107         SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
108                         AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
109         SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
110                         AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
111 
112         SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
113 
114         SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
115         SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
116         SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
117                         4, 0x07, 0),
118         SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
119                         0, 0x03, 0),
120         SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
121                         6, 0x03, 0),
122         SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
123                         1, 0x1F, 0),
124         SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
125                         0, 0x7F, 0),
126         SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
127                         3, 0x1F, 0),
128         SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
129                         3, 0x1F, 0),
130         SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
131                         0, 0x1F, 0),
132         SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
133                         0, 0x0F, 0),
134 };
135 
136 static const struct aic32x4_rate_divs aic32x4_divs[] = {
137         /* 8k rate */
138         {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
139         {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
140         {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
141         /* 11.025k rate */
142         {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
143         {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
144         /* 16k rate */
145         {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
146         {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
147         {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
148         /* 22.05k rate */
149         {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
150         {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
151         {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
152         /* 32k rate */
153         {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
154         {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
155         /* 44.1k rate */
156         {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
157         {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
158         {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
159         /* 48k rate */
160         {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
161         {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
162         {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4},
163 
164         /* 96k rate */
165         {AIC32X4_FREQ_25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1},
166 };
167 
168 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
169         SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
170         SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
171 };
172 
173 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
174         SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
175         SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
176 };
177 
178 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
179         SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
180 };
181 
182 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
183         SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
184 };
185 
186 static const char * const resistor_text[] = {
187         "Off", "10 kOhm", "20 kOhm", "40 kOhm",
188 };
189 
190 /* Left mixer pins */
191 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
192 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
193 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
194 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
195 
196 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
197 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
198 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
199 
200 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
201         SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
202 };
203 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
204         SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
205 };
206 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
207         SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
208 };
209 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
210         SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
211 };
212 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
213         SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
214 };
215 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
216         SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
217 };
218 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
219         SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
220 };
221 
222 /*  Right mixer pins */
223 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
224 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
225 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
226 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
227 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
228 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
229 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
230 
231 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
232         SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
233 };
234 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
235         SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
236 };
237 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
238         SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
239 };
240 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
241         SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
242 };
243 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
244         SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
245 };
246 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
247         SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
248 };
249 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
250         SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
251 };
252 
253 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
254         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
255         SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
256                            &hpl_output_mixer_controls[0],
257                            ARRAY_SIZE(hpl_output_mixer_controls)),
258         SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
259 
260         SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
261                            &lol_output_mixer_controls[0],
262                            ARRAY_SIZE(lol_output_mixer_controls)),
263         SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
264 
265         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
266         SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
267                            &hpr_output_mixer_controls[0],
268                            ARRAY_SIZE(hpr_output_mixer_controls)),
269         SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
270         SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
271                            &lor_output_mixer_controls[0],
272                            ARRAY_SIZE(lor_output_mixer_controls)),
273         SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
274 
275         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
276         SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
277                         in1r_to_rmixer_controls),
278         SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
279                         in2r_to_rmixer_controls),
280         SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
281                         in3r_to_rmixer_controls),
282         SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
283                         in2l_to_rmixer_controls),
284         SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
285                         cmr_to_rmixer_controls),
286         SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
287                         in1l_to_rmixer_controls),
288         SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
289                         in3l_to_rmixer_controls),
290 
291         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
292         SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
293                         in1l_to_lmixer_controls),
294         SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
295                         in2l_to_lmixer_controls),
296         SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
297                         in3l_to_lmixer_controls),
298         SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
299                         in1r_to_lmixer_controls),
300         SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
301                         cml_to_lmixer_controls),
302         SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
303                         in2r_to_lmixer_controls),
304         SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
305                         in3r_to_lmixer_controls),
306 
307         SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
308 
309         SND_SOC_DAPM_OUTPUT("HPL"),
310         SND_SOC_DAPM_OUTPUT("HPR"),
311         SND_SOC_DAPM_OUTPUT("LOL"),
312         SND_SOC_DAPM_OUTPUT("LOR"),
313         SND_SOC_DAPM_INPUT("IN1_L"),
314         SND_SOC_DAPM_INPUT("IN1_R"),
315         SND_SOC_DAPM_INPUT("IN2_L"),
316         SND_SOC_DAPM_INPUT("IN2_R"),
317         SND_SOC_DAPM_INPUT("IN3_L"),
318         SND_SOC_DAPM_INPUT("IN3_R"),
319 };
320 
321 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
322         /* Left Output */
323         {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
324         {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
325 
326         {"HPL Power", NULL, "HPL Output Mixer"},
327         {"HPL", NULL, "HPL Power"},
328 
329         {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
330 
331         {"LOL Power", NULL, "LOL Output Mixer"},
332         {"LOL", NULL, "LOL Power"},
333 
334         /* Right Output */
335         {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
336         {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
337 
338         {"HPR Power", NULL, "HPR Output Mixer"},
339         {"HPR", NULL, "HPR Power"},
340 
341         {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
342 
343         {"LOR Power", NULL, "LOR Output Mixer"},
344         {"LOR", NULL, "LOR Power"},
345 
346         /* Right Input */
347         {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
348         {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
349         {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
350         {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
351 
352         {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
353         {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
354         {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
355         {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
356 
357         {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
358         {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
359         {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
360         {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
361 
362         {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
363         {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
364         {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
365         {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
366 
367         {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
368         {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
369         {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
370         {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
371 
372         {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
373         {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
374         {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
375         {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
376 
377         {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
378         {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
379         {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
380         {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
381 
382         /* Left Input */
383         {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
384         {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
385         {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
386         {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
387 
388         {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
389         {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
390         {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
391         {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
392 
393         {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
394         {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
395         {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
396         {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
397 
398         {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
399         {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
400         {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
401         {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
402 
403         {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
404         {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
405         {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
406         {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
407 
408         {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
409         {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
410         {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
411         {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
412 
413         {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
414         {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
415         {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
416         {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
417 };
418 
419 static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
420         {
421                 .selector_reg = 0,
422                 .selector_mask  = 0xff,
423                 .window_start = 0,
424                 .window_len = 128,
425                 .range_min = 0,
426                 .range_max = AIC32X4_RMICPGAVOL,
427         },
428 };
429 
430 const struct regmap_config aic32x4_regmap_config = {
431         .max_register = AIC32X4_RMICPGAVOL,
432         .ranges = aic32x4_regmap_pages,
433         .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
434 };
435 EXPORT_SYMBOL(aic32x4_regmap_config);
436 
437 static inline int aic32x4_get_divs(int mclk, int rate)
438 {
439         int i;
440 
441         for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
442                 if ((aic32x4_divs[i].rate == rate)
443                     && (aic32x4_divs[i].mclk == mclk)) {
444                         return i;
445                 }
446         }
447         printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
448         return -EINVAL;
449 }
450 
451 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
452                                   int clk_id, unsigned int freq, int dir)
453 {
454         struct snd_soc_codec *codec = codec_dai->codec;
455         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
456 
457         switch (freq) {
458         case AIC32X4_FREQ_12000000:
459         case AIC32X4_FREQ_24000000:
460         case AIC32X4_FREQ_25000000:
461                 aic32x4->sysclk = freq;
462                 return 0;
463         }
464         printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
465         return -EINVAL;
466 }
467 
468 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
469 {
470         struct snd_soc_codec *codec = codec_dai->codec;
471         u8 iface_reg_1;
472         u8 iface_reg_2;
473         u8 iface_reg_3;
474 
475         iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
476         iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
477         iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
478         iface_reg_2 = 0;
479         iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
480         iface_reg_3 = iface_reg_3 & ~(1 << 3);
481 
482         /* set master/slave audio interface */
483         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
484         case SND_SOC_DAIFMT_CBM_CFM:
485                 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
486                 break;
487         case SND_SOC_DAIFMT_CBS_CFS:
488                 break;
489         default:
490                 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
491                 return -EINVAL;
492         }
493 
494         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
495         case SND_SOC_DAIFMT_I2S:
496                 break;
497         case SND_SOC_DAIFMT_DSP_A:
498                 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
499                 iface_reg_3 |= (1 << 3); /* invert bit clock */
500                 iface_reg_2 = 0x01; /* add offset 1 */
501                 break;
502         case SND_SOC_DAIFMT_DSP_B:
503                 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
504                 iface_reg_3 |= (1 << 3); /* invert bit clock */
505                 break;
506         case SND_SOC_DAIFMT_RIGHT_J:
507                 iface_reg_1 |=
508                         (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
509                 break;
510         case SND_SOC_DAIFMT_LEFT_J:
511                 iface_reg_1 |=
512                         (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
513                 break;
514         default:
515                 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
516                 return -EINVAL;
517         }
518 
519         snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
520         snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
521         snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
522         return 0;
523 }
524 
525 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
526                              struct snd_pcm_hw_params *params,
527                              struct snd_soc_dai *dai)
528 {
529         struct snd_soc_codec *codec = dai->codec;
530         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
531         u8 data;
532         int i;
533 
534         i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
535         if (i < 0) {
536                 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
537                 return i;
538         }
539 
540         /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
541         snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
542         snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
543 
544         /* We will fix R value to 1 and will make P & J=K.D as varialble */
545         data = snd_soc_read(codec, AIC32X4_PLLPR);
546         data &= ~(7 << 4);
547         snd_soc_write(codec, AIC32X4_PLLPR,
548                       (data | (aic32x4_divs[i].p_val << 4) | 0x01));
549 
550         snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
551 
552         snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
553         snd_soc_write(codec, AIC32X4_PLLDLSB,
554                       (aic32x4_divs[i].pll_d & 0xff));
555 
556         /* NDAC divider value */
557         data = snd_soc_read(codec, AIC32X4_NDAC);
558         data &= ~(0x7f);
559         snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
560 
561         /* MDAC divider value */
562         data = snd_soc_read(codec, AIC32X4_MDAC);
563         data &= ~(0x7f);
564         snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
565 
566         /* DOSR MSB & LSB values */
567         snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
568         snd_soc_write(codec, AIC32X4_DOSRLSB,
569                       (aic32x4_divs[i].dosr & 0xff));
570 
571         /* NADC divider value */
572         data = snd_soc_read(codec, AIC32X4_NADC);
573         data &= ~(0x7f);
574         snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
575 
576         /* MADC divider value */
577         data = snd_soc_read(codec, AIC32X4_MADC);
578         data &= ~(0x7f);
579         snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
580 
581         /* AOSR value */
582         snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
583 
584         /* BCLK N divider */
585         data = snd_soc_read(codec, AIC32X4_BCLKN);
586         data &= ~(0x7f);
587         snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
588 
589         data = snd_soc_read(codec, AIC32X4_IFACE1);
590         data = data & ~(3 << 4);
591         switch (params_width(params)) {
592         case 16:
593                 break;
594         case 20:
595                 data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
596                 break;
597         case 24:
598                 data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
599                 break;
600         case 32:
601                 data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
602                 break;
603         }
604         snd_soc_write(codec, AIC32X4_IFACE1, data);
605 
606         if (params_channels(params) == 1) {
607                 data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
608         } else {
609                 if (aic32x4->swapdacs)
610                         data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
611                 else
612                         data = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
613         }
614         snd_soc_update_bits(codec, AIC32X4_DACSETUP, AIC32X4_DAC_CHAN_MASK,
615                         data);
616 
617         return 0;
618 }
619 
620 static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
621 {
622         struct snd_soc_codec *codec = dai->codec;
623         u8 dac_reg;
624 
625         dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON;
626         if (mute)
627                 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON);
628         else
629                 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg);
630         return 0;
631 }
632 
633 static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
634                                   enum snd_soc_bias_level level)
635 {
636         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
637         int ret;
638 
639         switch (level) {
640         case SND_SOC_BIAS_ON:
641                 /* Switch on master clock */
642                 ret = clk_prepare_enable(aic32x4->mclk);
643                 if (ret) {
644                         dev_err(codec->dev, "Failed to enable master clock\n");
645                         return ret;
646                 }
647 
648                 /* Switch on PLL */
649                 snd_soc_update_bits(codec, AIC32X4_PLLPR,
650                                     AIC32X4_PLLEN, AIC32X4_PLLEN);
651 
652                 /* Switch on NDAC Divider */
653                 snd_soc_update_bits(codec, AIC32X4_NDAC,
654                                     AIC32X4_NDACEN, AIC32X4_NDACEN);
655 
656                 /* Switch on MDAC Divider */
657                 snd_soc_update_bits(codec, AIC32X4_MDAC,
658                                     AIC32X4_MDACEN, AIC32X4_MDACEN);
659 
660                 /* Switch on NADC Divider */
661                 snd_soc_update_bits(codec, AIC32X4_NADC,
662                                     AIC32X4_NADCEN, AIC32X4_NADCEN);
663 
664                 /* Switch on MADC Divider */
665                 snd_soc_update_bits(codec, AIC32X4_MADC,
666                                     AIC32X4_MADCEN, AIC32X4_MADCEN);
667 
668                 /* Switch on BCLK_N Divider */
669                 snd_soc_update_bits(codec, AIC32X4_BCLKN,
670                                     AIC32X4_BCLKEN, AIC32X4_BCLKEN);
671                 break;
672         case SND_SOC_BIAS_PREPARE:
673                 break;
674         case SND_SOC_BIAS_STANDBY:
675                 /* Switch off BCLK_N Divider */
676                 snd_soc_update_bits(codec, AIC32X4_BCLKN,
677                                     AIC32X4_BCLKEN, 0);
678 
679                 /* Switch off MADC Divider */
680                 snd_soc_update_bits(codec, AIC32X4_MADC,
681                                     AIC32X4_MADCEN, 0);
682 
683                 /* Switch off NADC Divider */
684                 snd_soc_update_bits(codec, AIC32X4_NADC,
685                                     AIC32X4_NADCEN, 0);
686 
687                 /* Switch off MDAC Divider */
688                 snd_soc_update_bits(codec, AIC32X4_MDAC,
689                                     AIC32X4_MDACEN, 0);
690 
691                 /* Switch off NDAC Divider */
692                 snd_soc_update_bits(codec, AIC32X4_NDAC,
693                                     AIC32X4_NDACEN, 0);
694 
695                 /* Switch off PLL */
696                 snd_soc_update_bits(codec, AIC32X4_PLLPR,
697                                     AIC32X4_PLLEN, 0);
698 
699                 /* Switch off master clock */
700                 clk_disable_unprepare(aic32x4->mclk);
701                 break;
702         case SND_SOC_BIAS_OFF:
703                 break;
704         }
705         return 0;
706 }
707 
708 #define AIC32X4_RATES   SNDRV_PCM_RATE_8000_96000
709 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
710                          | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
711 
712 static const struct snd_soc_dai_ops aic32x4_ops = {
713         .hw_params = aic32x4_hw_params,
714         .digital_mute = aic32x4_mute,
715         .set_fmt = aic32x4_set_dai_fmt,
716         .set_sysclk = aic32x4_set_dai_sysclk,
717 };
718 
719 static struct snd_soc_dai_driver aic32x4_dai = {
720         .name = "tlv320aic32x4-hifi",
721         .playback = {
722                      .stream_name = "Playback",
723                      .channels_min = 1,
724                      .channels_max = 2,
725                      .rates = AIC32X4_RATES,
726                      .formats = AIC32X4_FORMATS,},
727         .capture = {
728                     .stream_name = "Capture",
729                     .channels_min = 1,
730                     .channels_max = 2,
731                     .rates = AIC32X4_RATES,
732                     .formats = AIC32X4_FORMATS,},
733         .ops = &aic32x4_ops,
734         .symmetric_rates = 1,
735 };
736 
737 static int aic32x4_codec_probe(struct snd_soc_codec *codec)
738 {
739         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
740         u32 tmp_reg;
741 
742         if (gpio_is_valid(aic32x4->rstn_gpio)) {
743                 ndelay(10);
744                 gpio_set_value(aic32x4->rstn_gpio, 1);
745         }
746 
747         snd_soc_write(codec, AIC32X4_RESET, 0x01);
748 
749         /* Power platform configuration */
750         if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
751                 snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
752                                                       AIC32X4_MICBIAS_2075V);
753         }
754         if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
755                 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
756 
757         tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
758                         AIC32X4_LDOCTLEN : 0;
759         snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
760 
761         tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
762         if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
763                 tmp_reg |= AIC32X4_LDOIN_18_36;
764         if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
765                 tmp_reg |= AIC32X4_LDOIN2HP;
766         snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
767 
768         /* Mic PGA routing */
769         if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
770                 snd_soc_write(codec, AIC32X4_LMICPGANIN,
771                                 AIC32X4_LMICPGANIN_IN2R_10K);
772         else
773                 snd_soc_write(codec, AIC32X4_LMICPGANIN,
774                                 AIC32X4_LMICPGANIN_CM1L_10K);
775         if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
776                 snd_soc_write(codec, AIC32X4_RMICPGANIN,
777                                 AIC32X4_RMICPGANIN_IN1L_10K);
778         else
779                 snd_soc_write(codec, AIC32X4_RMICPGANIN,
780                                 AIC32X4_RMICPGANIN_CM1R_10K);
781 
782         /*
783          * Workaround: for an unknown reason, the ADC needs to be powered up
784          * and down for the first capture to work properly. It seems related to
785          * a HW BUG or some kind of behavior not documented in the datasheet.
786          */
787         tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP);
788         snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg |
789                                 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
790         snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg);
791 
792         return 0;
793 }
794 
795 static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
796         .probe = aic32x4_codec_probe,
797         .set_bias_level = aic32x4_set_bias_level,
798         .suspend_bias_off = true,
799 
800         .controls = aic32x4_snd_controls,
801         .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
802         .dapm_widgets = aic32x4_dapm_widgets,
803         .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
804         .dapm_routes = aic32x4_dapm_routes,
805         .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
806 };
807 
808 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
809                 struct device_node *np)
810 {
811         aic32x4->swapdacs = false;
812         aic32x4->micpga_routing = 0;
813         aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
814 
815         return 0;
816 }
817 
818 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
819 {
820         regulator_disable(aic32x4->supply_iov);
821 
822         if (!IS_ERR(aic32x4->supply_ldo))
823                 regulator_disable(aic32x4->supply_ldo);
824 
825         if (!IS_ERR(aic32x4->supply_dv))
826                 regulator_disable(aic32x4->supply_dv);
827 
828         if (!IS_ERR(aic32x4->supply_av))
829                 regulator_disable(aic32x4->supply_av);
830 }
831 
832 static int aic32x4_setup_regulators(struct device *dev,
833                 struct aic32x4_priv *aic32x4)
834 {
835         int ret = 0;
836 
837         aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
838         aic32x4->supply_iov = devm_regulator_get(dev, "iov");
839         aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
840         aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
841 
842         /* Check if the regulator requirements are fulfilled */
843 
844         if (IS_ERR(aic32x4->supply_iov)) {
845                 dev_err(dev, "Missing supply 'iov'\n");
846                 return PTR_ERR(aic32x4->supply_iov);
847         }
848 
849         if (IS_ERR(aic32x4->supply_ldo)) {
850                 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
851                         return -EPROBE_DEFER;
852 
853                 if (IS_ERR(aic32x4->supply_dv)) {
854                         dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
855                         return PTR_ERR(aic32x4->supply_dv);
856                 }
857                 if (IS_ERR(aic32x4->supply_av)) {
858                         dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
859                         return PTR_ERR(aic32x4->supply_av);
860                 }
861         } else {
862                 if (IS_ERR(aic32x4->supply_dv) &&
863                                 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
864                         return -EPROBE_DEFER;
865                 if (IS_ERR(aic32x4->supply_av) &&
866                                 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
867                         return -EPROBE_DEFER;
868         }
869 
870         ret = regulator_enable(aic32x4->supply_iov);
871         if (ret) {
872                 dev_err(dev, "Failed to enable regulator iov\n");
873                 return ret;
874         }
875 
876         if (!IS_ERR(aic32x4->supply_ldo)) {
877                 ret = regulator_enable(aic32x4->supply_ldo);
878                 if (ret) {
879                         dev_err(dev, "Failed to enable regulator ldo\n");
880                         goto error_ldo;
881                 }
882         }
883 
884         if (!IS_ERR(aic32x4->supply_dv)) {
885                 ret = regulator_enable(aic32x4->supply_dv);
886                 if (ret) {
887                         dev_err(dev, "Failed to enable regulator dv\n");
888                         goto error_dv;
889                 }
890         }
891 
892         if (!IS_ERR(aic32x4->supply_av)) {
893                 ret = regulator_enable(aic32x4->supply_av);
894                 if (ret) {
895                         dev_err(dev, "Failed to enable regulator av\n");
896                         goto error_av;
897                 }
898         }
899 
900         if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
901                 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
902 
903         return 0;
904 
905 error_av:
906         if (!IS_ERR(aic32x4->supply_dv))
907                 regulator_disable(aic32x4->supply_dv);
908 
909 error_dv:
910         if (!IS_ERR(aic32x4->supply_ldo))
911                 regulator_disable(aic32x4->supply_ldo);
912 
913 error_ldo:
914         regulator_disable(aic32x4->supply_iov);
915         return ret;
916 }
917 
918 int aic32x4_probe(struct device *dev, struct regmap *regmap)
919 {
920         struct aic32x4_priv *aic32x4;
921         struct aic32x4_pdata *pdata = dev->platform_data;
922         struct device_node *np = dev->of_node;
923         int ret;
924 
925         if (IS_ERR(regmap))
926                 return PTR_ERR(regmap);
927 
928         aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
929                                GFP_KERNEL);
930         if (aic32x4 == NULL)
931                 return -ENOMEM;
932 
933         dev_set_drvdata(dev, aic32x4);
934 
935         if (pdata) {
936                 aic32x4->power_cfg = pdata->power_cfg;
937                 aic32x4->swapdacs = pdata->swapdacs;
938                 aic32x4->micpga_routing = pdata->micpga_routing;
939                 aic32x4->rstn_gpio = pdata->rstn_gpio;
940         } else if (np) {
941                 ret = aic32x4_parse_dt(aic32x4, np);
942                 if (ret) {
943                         dev_err(dev, "Failed to parse DT node\n");
944                         return ret;
945                 }
946         } else {
947                 aic32x4->power_cfg = 0;
948                 aic32x4->swapdacs = false;
949                 aic32x4->micpga_routing = 0;
950                 aic32x4->rstn_gpio = -1;
951         }
952 
953         aic32x4->mclk = devm_clk_get(dev, "mclk");
954         if (IS_ERR(aic32x4->mclk)) {
955                 dev_err(dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n");
956                 return PTR_ERR(aic32x4->mclk);
957         }
958 
959         if (gpio_is_valid(aic32x4->rstn_gpio)) {
960                 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
961                                 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
962                 if (ret != 0)
963                         return ret;
964         }
965 
966         ret = aic32x4_setup_regulators(dev, aic32x4);
967         if (ret) {
968                 dev_err(dev, "Failed to setup regulators\n");
969                 return ret;
970         }
971 
972         ret = snd_soc_register_codec(dev,
973                         &soc_codec_dev_aic32x4, &aic32x4_dai, 1);
974         if (ret) {
975                 dev_err(dev, "Failed to register codec\n");
976                 aic32x4_disable_regulators(aic32x4);
977                 return ret;
978         }
979 
980         return 0;
981 }
982 EXPORT_SYMBOL(aic32x4_probe);
983 
984 int aic32x4_remove(struct device *dev)
985 {
986         struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
987 
988         aic32x4_disable_regulators(aic32x4);
989 
990         snd_soc_unregister_codec(dev);
991 
992         return 0;
993 }
994 EXPORT_SYMBOL(aic32x4_remove);
995 
996 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
997 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
998 MODULE_LICENSE("GPL");
999 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us