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Linux/sound/soc/codecs/sgtl5000.c

  1 /*
  2  * sgtl5000.c  --  SGTL5000 ALSA SoC Audio driver
  3  *
  4  * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  */
 10 
 11 #include <linux/module.h>
 12 #include <linux/moduleparam.h>
 13 #include <linux/init.h>
 14 #include <linux/delay.h>
 15 #include <linux/slab.h>
 16 #include <linux/pm.h>
 17 #include <linux/i2c.h>
 18 #include <linux/clk.h>
 19 #include <linux/regmap.h>
 20 #include <linux/regulator/driver.h>
 21 #include <linux/regulator/machine.h>
 22 #include <linux/regulator/consumer.h>
 23 #include <linux/of_device.h>
 24 #include <sound/core.h>
 25 #include <sound/tlv.h>
 26 #include <sound/pcm.h>
 27 #include <sound/pcm_params.h>
 28 #include <sound/soc.h>
 29 #include <sound/soc-dapm.h>
 30 #include <sound/initval.h>
 31 
 32 #include "sgtl5000.h"
 33 
 34 #define SGTL5000_DAP_REG_OFFSET 0x0100
 35 #define SGTL5000_MAX_REG_OFFSET 0x013A
 36 
 37 /* default value of sgtl5000 registers */
 38 static const struct reg_default sgtl5000_reg_defaults[] = {
 39         { SGTL5000_CHIP_DIG_POWER,              0x0000 },
 40         { SGTL5000_CHIP_CLK_CTRL,               0x0008 },
 41         { SGTL5000_CHIP_I2S_CTRL,               0x0010 },
 42         { SGTL5000_CHIP_SSS_CTRL,               0x0010 },
 43         { SGTL5000_CHIP_ADCDAC_CTRL,            0x020c },
 44         { SGTL5000_CHIP_DAC_VOL,                0x3c3c },
 45         { SGTL5000_CHIP_PAD_STRENGTH,           0x015f },
 46         { SGTL5000_CHIP_ANA_ADC_CTRL,           0x0000 },
 47         { SGTL5000_CHIP_ANA_HP_CTRL,            0x1818 },
 48         { SGTL5000_CHIP_ANA_CTRL,               0x0111 },
 49         { SGTL5000_CHIP_LINREG_CTRL,            0x0000 },
 50         { SGTL5000_CHIP_REF_CTRL,               0x0000 },
 51         { SGTL5000_CHIP_MIC_CTRL,               0x0000 },
 52         { SGTL5000_CHIP_LINE_OUT_CTRL,          0x0000 },
 53         { SGTL5000_CHIP_LINE_OUT_VOL,           0x0404 },
 54         { SGTL5000_CHIP_ANA_POWER,              0x7060 },
 55         { SGTL5000_CHIP_PLL_CTRL,               0x5000 },
 56         { SGTL5000_CHIP_CLK_TOP_CTRL,           0x0000 },
 57         { SGTL5000_CHIP_ANA_STATUS,             0x0000 },
 58         { SGTL5000_CHIP_SHORT_CTRL,             0x0000 },
 59         { SGTL5000_CHIP_ANA_TEST2,              0x0000 },
 60         { SGTL5000_DAP_CTRL,                    0x0000 },
 61         { SGTL5000_DAP_PEQ,                     0x0000 },
 62         { SGTL5000_DAP_BASS_ENHANCE,            0x0040 },
 63         { SGTL5000_DAP_BASS_ENHANCE_CTRL,       0x051f },
 64         { SGTL5000_DAP_AUDIO_EQ,                0x0000 },
 65         { SGTL5000_DAP_SURROUND,                0x0040 },
 66         { SGTL5000_DAP_EQ_BASS_BAND0,           0x002f },
 67         { SGTL5000_DAP_EQ_BASS_BAND1,           0x002f },
 68         { SGTL5000_DAP_EQ_BASS_BAND2,           0x002f },
 69         { SGTL5000_DAP_EQ_BASS_BAND3,           0x002f },
 70         { SGTL5000_DAP_EQ_BASS_BAND4,           0x002f },
 71         { SGTL5000_DAP_MAIN_CHAN,               0x8000 },
 72         { SGTL5000_DAP_MIX_CHAN,                0x0000 },
 73         { SGTL5000_DAP_AVC_CTRL,                0x0510 },
 74         { SGTL5000_DAP_AVC_THRESHOLD,           0x1473 },
 75         { SGTL5000_DAP_AVC_ATTACK,              0x0028 },
 76         { SGTL5000_DAP_AVC_DECAY,               0x0050 },
 77 };
 78 
 79 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
 80 enum sgtl5000_regulator_supplies {
 81         VDDA,
 82         VDDIO,
 83         VDDD,
 84         SGTL5000_SUPPLY_NUM
 85 };
 86 
 87 /* vddd is optional supply */
 88 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
 89         "VDDA",
 90         "VDDIO",
 91         "VDDD"
 92 };
 93 
 94 #define LDO_CONSUMER_NAME       "VDDD_LDO"
 95 #define LDO_VOLTAGE             1200000
 96 
 97 static struct regulator_consumer_supply ldo_consumer[] = {
 98         REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
 99 };
100 
101 static struct regulator_init_data ldo_init_data = {
102         .constraints = {
103                 .min_uV                 = 1200000,
104                 .max_uV                 = 1200000,
105                 .valid_modes_mask       = REGULATOR_MODE_NORMAL,
106                 .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
107         },
108         .num_consumer_supplies = 1,
109         .consumer_supplies = &ldo_consumer[0],
110 };
111 
112 /*
113  * sgtl5000 internal ldo regulator,
114  * enabled when VDDD not provided
115  */
116 struct ldo_regulator {
117         struct regulator_desc desc;
118         struct regulator_dev *dev;
119         int voltage;
120         void *codec_data;
121         bool enabled;
122 };
123 
124 /* sgtl5000 private structure in codec */
125 struct sgtl5000_priv {
126         int sysclk;     /* sysclk rate */
127         int master;     /* i2s master or not */
128         int fmt;        /* i2s data format */
129         struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
130         struct ldo_regulator *ldo;
131         struct regmap *regmap;
132         struct clk *mclk;
133         int revision;
134 };
135 
136 /*
137  * mic_bias power on/off share the same register bits with
138  * output impedance of mic bias, when power on mic bias, we
139  * need reclaim it to impedance value.
140  * 0x0 = Powered off
141  * 0x1 = 2Kohm
142  * 0x2 = 4Kohm
143  * 0x3 = 8Kohm
144  */
145 static int mic_bias_event(struct snd_soc_dapm_widget *w,
146         struct snd_kcontrol *kcontrol, int event)
147 {
148         switch (event) {
149         case SND_SOC_DAPM_POST_PMU:
150                 /* change mic bias resistor to 4Kohm */
151                 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
152                                 SGTL5000_BIAS_R_MASK,
153                                 SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
154                 break;
155 
156         case SND_SOC_DAPM_PRE_PMD:
157                 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
158                                 SGTL5000_BIAS_R_MASK, 0);
159                 break;
160         }
161         return 0;
162 }
163 
164 /*
165  * As manual described, ADC/DAC only works when VAG powerup,
166  * So enabled VAG before ADC/DAC up.
167  * In power down case, we need wait 400ms when vag fully ramped down.
168  */
169 static int power_vag_event(struct snd_soc_dapm_widget *w,
170         struct snd_kcontrol *kcontrol, int event)
171 {
172         const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
173 
174         switch (event) {
175         case SND_SOC_DAPM_POST_PMU:
176                 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
177                         SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
178                 break;
179 
180         case SND_SOC_DAPM_PRE_PMD:
181                 /*
182                  * Don't clear VAG_POWERUP, when both DAC and ADC are
183                  * operational to prevent inadvertently starving the
184                  * other one of them.
185                  */
186                 if ((snd_soc_read(w->codec, SGTL5000_CHIP_ANA_POWER) &
187                                 mask) != mask) {
188                         snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
189                                 SGTL5000_VAG_POWERUP, 0);
190                         msleep(400);
191                 }
192                 break;
193         default:
194                 break;
195         }
196 
197         return 0;
198 }
199 
200 /* input sources for ADC */
201 static const char *adc_mux_text[] = {
202         "MIC_IN", "LINE_IN"
203 };
204 
205 static SOC_ENUM_SINGLE_DECL(adc_enum,
206                             SGTL5000_CHIP_ANA_CTRL, 2,
207                             adc_mux_text);
208 
209 static const struct snd_kcontrol_new adc_mux =
210 SOC_DAPM_ENUM("Capture Mux", adc_enum);
211 
212 /* input sources for DAC */
213 static const char *dac_mux_text[] = {
214         "DAC", "LINE_IN"
215 };
216 
217 static SOC_ENUM_SINGLE_DECL(dac_enum,
218                             SGTL5000_CHIP_ANA_CTRL, 6,
219                             dac_mux_text);
220 
221 static const struct snd_kcontrol_new dac_mux =
222 SOC_DAPM_ENUM("Headphone Mux", dac_enum);
223 
224 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
225         SND_SOC_DAPM_INPUT("LINE_IN"),
226         SND_SOC_DAPM_INPUT("MIC_IN"),
227 
228         SND_SOC_DAPM_OUTPUT("HP_OUT"),
229         SND_SOC_DAPM_OUTPUT("LINE_OUT"),
230 
231         SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
232                             mic_bias_event,
233                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
234 
235         SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
236         SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
237 
238         SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
239         SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
240 
241         /* aif for i2s input */
242         SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
243                                 0, SGTL5000_CHIP_DIG_POWER,
244                                 0, 0),
245 
246         /* aif for i2s output */
247         SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
248                                 0, SGTL5000_CHIP_DIG_POWER,
249                                 1, 0),
250 
251         SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
252         SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
253 
254         SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
255         SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
256 };
257 
258 /* routes for sgtl5000 */
259 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
260         {"Capture Mux", "LINE_IN", "LINE_IN"},  /* line_in --> adc_mux */
261         {"Capture Mux", "MIC_IN", "MIC_IN"},    /* mic_in --> adc_mux */
262 
263         {"ADC", NULL, "Capture Mux"},           /* adc_mux --> adc */
264         {"AIFOUT", NULL, "ADC"},                /* adc --> i2s_out */
265 
266         {"DAC", NULL, "AIFIN"},                 /* i2s-->dac,skip audio mux */
267         {"Headphone Mux", "DAC", "DAC"},        /* dac --> hp_mux */
268         {"LO", NULL, "DAC"},                    /* dac --> line_out */
269 
270         {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
271         {"HP", NULL, "Headphone Mux"},          /* hp_mux --> hp */
272 
273         {"LINE_OUT", NULL, "LO"},
274         {"HP_OUT", NULL, "HP"},
275 };
276 
277 /* custom function to fetch info of PCM playback volume */
278 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
279                           struct snd_ctl_elem_info *uinfo)
280 {
281         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
282         uinfo->count = 2;
283         uinfo->value.integer.min = 0;
284         uinfo->value.integer.max = 0xfc - 0x3c;
285         return 0;
286 }
287 
288 /*
289  * custom function to get of PCM playback volume
290  *
291  * dac volume register
292  * 15-------------8-7--------------0
293  * | R channel vol | L channel vol |
294  *  -------------------------------
295  *
296  * PCM volume with 0.5017 dB steps from 0 to -90 dB
297  *
298  * register values map to dB
299  * 0x3B and less = Reserved
300  * 0x3C = 0 dB
301  * 0x3D = -0.5 dB
302  * 0xF0 = -90 dB
303  * 0xFC and greater = Muted
304  *
305  * register value map to userspace value
306  *
307  * register value       0x3c(0dB)         0xf0(-90dB)0xfc
308  *                      ------------------------------
309  * userspace value      0xc0                         0
310  */
311 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
312                          struct snd_ctl_elem_value *ucontrol)
313 {
314         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
315         int reg;
316         int l;
317         int r;
318 
319         reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
320 
321         /* get left channel volume */
322         l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
323 
324         /* get right channel volume */
325         r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
326 
327         /* make sure value fall in (0x3c,0xfc) */
328         l = clamp(l, 0x3c, 0xfc);
329         r = clamp(r, 0x3c, 0xfc);
330 
331         /* invert it and map to userspace value */
332         l = 0xfc - l;
333         r = 0xfc - r;
334 
335         ucontrol->value.integer.value[0] = l;
336         ucontrol->value.integer.value[1] = r;
337 
338         return 0;
339 }
340 
341 /*
342  * custom function to put of PCM playback volume
343  *
344  * dac volume register
345  * 15-------------8-7--------------0
346  * | R channel vol | L channel vol |
347  *  -------------------------------
348  *
349  * PCM volume with 0.5017 dB steps from 0 to -90 dB
350  *
351  * register values map to dB
352  * 0x3B and less = Reserved
353  * 0x3C = 0 dB
354  * 0x3D = -0.5 dB
355  * 0xF0 = -90 dB
356  * 0xFC and greater = Muted
357  *
358  * userspace value map to register value
359  *
360  * userspace value      0xc0                         0
361  *                      ------------------------------
362  * register value       0x3c(0dB)       0xf0(-90dB)0xfc
363  */
364 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
365                          struct snd_ctl_elem_value *ucontrol)
366 {
367         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
368         int reg;
369         int l;
370         int r;
371 
372         l = ucontrol->value.integer.value[0];
373         r = ucontrol->value.integer.value[1];
374 
375         /* make sure userspace volume fall in (0, 0xfc-0x3c) */
376         l = clamp(l, 0, 0xfc - 0x3c);
377         r = clamp(r, 0, 0xfc - 0x3c);
378 
379         /* invert it, get the value can be set to register */
380         l = 0xfc - l;
381         r = 0xfc - r;
382 
383         /* shift to get the register value */
384         reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
385                 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
386 
387         snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
388 
389         return 0;
390 }
391 
392 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
393 
394 /* tlv for mic gain, 0db 20db 30db 40db */
395 static const unsigned int mic_gain_tlv[] = {
396         TLV_DB_RANGE_HEAD(2),
397         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
398         1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
399 };
400 
401 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
402 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
403 
404 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
405         /* SOC_DOUBLE_S8_TLV with invert */
406         {
407                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
408                 .name = "PCM Playback Volume",
409                 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
410                         SNDRV_CTL_ELEM_ACCESS_READWRITE,
411                 .info = dac_info_volsw,
412                 .get = dac_get_volsw,
413                 .put = dac_put_volsw,
414         },
415 
416         SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
417         SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
418                         SGTL5000_CHIP_ANA_ADC_CTRL,
419                         8, 1, 0, capture_6db_attenuate),
420         SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
421 
422         SOC_DOUBLE_TLV("Headphone Playback Volume",
423                         SGTL5000_CHIP_ANA_HP_CTRL,
424                         0, 8,
425                         0x7f, 1,
426                         headphone_volume),
427         SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
428                         5, 1, 0),
429 
430         SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
431                         0, 3, 0, mic_gain_tlv),
432 };
433 
434 /* mute the codec used by alsa core */
435 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
436 {
437         struct snd_soc_codec *codec = codec_dai->codec;
438         u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
439 
440         snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
441                         adcdac_ctrl, mute ? adcdac_ctrl : 0);
442 
443         return 0;
444 }
445 
446 /* set codec format */
447 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
448 {
449         struct snd_soc_codec *codec = codec_dai->codec;
450         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
451         u16 i2sctl = 0;
452 
453         sgtl5000->master = 0;
454         /*
455          * i2s clock and frame master setting.
456          * ONLY support:
457          *  - clock and frame slave,
458          *  - clock and frame master
459          */
460         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
461         case SND_SOC_DAIFMT_CBS_CFS:
462                 break;
463         case SND_SOC_DAIFMT_CBM_CFM:
464                 i2sctl |= SGTL5000_I2S_MASTER;
465                 sgtl5000->master = 1;
466                 break;
467         default:
468                 return -EINVAL;
469         }
470 
471         /* setting i2s data format */
472         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
473         case SND_SOC_DAIFMT_DSP_A:
474                 i2sctl |= SGTL5000_I2S_MODE_PCM;
475                 break;
476         case SND_SOC_DAIFMT_DSP_B:
477                 i2sctl |= SGTL5000_I2S_MODE_PCM;
478                 i2sctl |= SGTL5000_I2S_LRALIGN;
479                 break;
480         case SND_SOC_DAIFMT_I2S:
481                 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
482                 break;
483         case SND_SOC_DAIFMT_RIGHT_J:
484                 i2sctl |= SGTL5000_I2S_MODE_RJ;
485                 i2sctl |= SGTL5000_I2S_LRPOL;
486                 break;
487         case SND_SOC_DAIFMT_LEFT_J:
488                 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
489                 i2sctl |= SGTL5000_I2S_LRALIGN;
490                 break;
491         default:
492                 return -EINVAL;
493         }
494 
495         sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
496 
497         /* Clock inversion */
498         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
499         case SND_SOC_DAIFMT_NB_NF:
500                 break;
501         case SND_SOC_DAIFMT_IB_NF:
502                 i2sctl |= SGTL5000_I2S_SCLK_INV;
503                 break;
504         default:
505                 return -EINVAL;
506         }
507 
508         snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
509 
510         return 0;
511 }
512 
513 /* set codec sysclk */
514 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
515                                    int clk_id, unsigned int freq, int dir)
516 {
517         struct snd_soc_codec *codec = codec_dai->codec;
518         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
519 
520         switch (clk_id) {
521         case SGTL5000_SYSCLK:
522                 sgtl5000->sysclk = freq;
523                 break;
524         default:
525                 return -EINVAL;
526         }
527 
528         return 0;
529 }
530 
531 /*
532  * set clock according to i2s frame clock,
533  * sgtl5000 provide 2 clock sources.
534  * 1. sys_mclk. sample freq can only configure to
535  *      1/256, 1/384, 1/512 of sys_mclk.
536  * 2. pll. can derive any audio clocks.
537  *
538  * clock setting rules:
539  * 1. in slave mode, only sys_mclk can use.
540  * 2. as constraint by sys_mclk, sample freq should
541  *      set to 32k, 44.1k and above.
542  * 3. using sys_mclk prefer to pll to save power.
543  */
544 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
545 {
546         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
547         int clk_ctl = 0;
548         int sys_fs;     /* sample freq */
549 
550         /*
551          * sample freq should be divided by frame clock,
552          * if frame clock lower than 44.1khz, sample feq should set to
553          * 32khz or 44.1khz.
554          */
555         switch (frame_rate) {
556         case 8000:
557         case 16000:
558                 sys_fs = 32000;
559                 break;
560         case 11025:
561         case 22050:
562                 sys_fs = 44100;
563                 break;
564         default:
565                 sys_fs = frame_rate;
566                 break;
567         }
568 
569         /* set divided factor of frame clock */
570         switch (sys_fs / frame_rate) {
571         case 4:
572                 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
573                 break;
574         case 2:
575                 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
576                 break;
577         case 1:
578                 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
579                 break;
580         default:
581                 return -EINVAL;
582         }
583 
584         /* set the sys_fs according to frame rate */
585         switch (sys_fs) {
586         case 32000:
587                 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
588                 break;
589         case 44100:
590                 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
591                 break;
592         case 48000:
593                 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
594                 break;
595         case 96000:
596                 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
597                 break;
598         default:
599                 dev_err(codec->dev, "frame rate %d not supported\n",
600                         frame_rate);
601                 return -EINVAL;
602         }
603 
604         /*
605          * calculate the divider of mclk/sample_freq,
606          * factor of freq =96k can only be 256, since mclk in range (12m,27m)
607          */
608         switch (sgtl5000->sysclk / sys_fs) {
609         case 256:
610                 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
611                         SGTL5000_MCLK_FREQ_SHIFT;
612                 break;
613         case 384:
614                 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
615                         SGTL5000_MCLK_FREQ_SHIFT;
616                 break;
617         case 512:
618                 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
619                         SGTL5000_MCLK_FREQ_SHIFT;
620                 break;
621         default:
622                 /* if mclk not satisify the divider, use pll */
623                 if (sgtl5000->master) {
624                         clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
625                                 SGTL5000_MCLK_FREQ_SHIFT;
626                 } else {
627                         dev_err(codec->dev,
628                                 "PLL not supported in slave mode\n");
629                         dev_err(codec->dev, "%d ratio is not supported. "
630                                 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
631                                 sgtl5000->sysclk / sys_fs);
632                         return -EINVAL;
633                 }
634         }
635 
636         /* if using pll, please check manual 6.4.2 for detail */
637         if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
638                 u64 out, t;
639                 int div2;
640                 int pll_ctl;
641                 unsigned int in, int_div, frac_div;
642 
643                 if (sgtl5000->sysclk > 17000000) {
644                         div2 = 1;
645                         in = sgtl5000->sysclk / 2;
646                 } else {
647                         div2 = 0;
648                         in = sgtl5000->sysclk;
649                 }
650                 if (sys_fs == 44100)
651                         out = 180633600;
652                 else
653                         out = 196608000;
654                 t = do_div(out, in);
655                 int_div = out;
656                 t *= 2048;
657                 do_div(t, in);
658                 frac_div = t;
659                 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
660                     frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
661 
662                 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
663                 if (div2)
664                         snd_soc_update_bits(codec,
665                                 SGTL5000_CHIP_CLK_TOP_CTRL,
666                                 SGTL5000_INPUT_FREQ_DIV2,
667                                 SGTL5000_INPUT_FREQ_DIV2);
668                 else
669                         snd_soc_update_bits(codec,
670                                 SGTL5000_CHIP_CLK_TOP_CTRL,
671                                 SGTL5000_INPUT_FREQ_DIV2,
672                                 0);
673 
674                 /* power up pll */
675                 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
676                         SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
677                         SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
678 
679                 /* if using pll, clk_ctrl must be set after pll power up */
680                 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
681         } else {
682                 /* otherwise, clk_ctrl must be set before pll power down */
683                 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
684 
685                 /* power down pll */
686                 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
687                         SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
688                         0);
689         }
690 
691         return 0;
692 }
693 
694 /*
695  * Set PCM DAI bit size and sample rate.
696  * input: params_rate, params_fmt
697  */
698 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
699                                   struct snd_pcm_hw_params *params,
700                                   struct snd_soc_dai *dai)
701 {
702         struct snd_soc_codec *codec = dai->codec;
703         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
704         int channels = params_channels(params);
705         int i2s_ctl = 0;
706         int stereo;
707         int ret;
708 
709         /* sysclk should already set */
710         if (!sgtl5000->sysclk) {
711                 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
712                 return -EFAULT;
713         }
714 
715         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
716                 stereo = SGTL5000_DAC_STEREO;
717         else
718                 stereo = SGTL5000_ADC_STEREO;
719 
720         /* set mono to save power */
721         snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
722                         channels == 1 ? 0 : stereo);
723 
724         /* set codec clock base on lrclk */
725         ret = sgtl5000_set_clock(codec, params_rate(params));
726         if (ret)
727                 return ret;
728 
729         /* set i2s data format */
730         switch (params_width(params)) {
731         case 16:
732                 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
733                         return -EINVAL;
734                 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
735                 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
736                     SGTL5000_I2S_SCLKFREQ_SHIFT;
737                 break;
738         case 20:
739                 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
740                 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
741                     SGTL5000_I2S_SCLKFREQ_SHIFT;
742                 break;
743         case 24:
744                 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
745                 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
746                     SGTL5000_I2S_SCLKFREQ_SHIFT;
747                 break;
748         case 32:
749                 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
750                         return -EINVAL;
751                 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
752                 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
753                     SGTL5000_I2S_SCLKFREQ_SHIFT;
754                 break;
755         default:
756                 return -EINVAL;
757         }
758 
759         snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
760                             SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
761                             i2s_ctl);
762 
763         return 0;
764 }
765 
766 #ifdef CONFIG_REGULATOR
767 static int ldo_regulator_is_enabled(struct regulator_dev *dev)
768 {
769         struct ldo_regulator *ldo = rdev_get_drvdata(dev);
770 
771         return ldo->enabled;
772 }
773 
774 static int ldo_regulator_enable(struct regulator_dev *dev)
775 {
776         struct ldo_regulator *ldo = rdev_get_drvdata(dev);
777         struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
778         int reg;
779 
780         if (ldo_regulator_is_enabled(dev))
781                 return 0;
782 
783         /* set regulator value firstly */
784         reg = (1600 - ldo->voltage / 1000) / 50;
785         reg = clamp(reg, 0x0, 0xf);
786 
787         /* amend the voltage value, unit: uV */
788         ldo->voltage = (1600 - reg * 50) * 1000;
789 
790         /* set voltage to register */
791         snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
792                                 SGTL5000_LINREG_VDDD_MASK, reg);
793 
794         snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
795                                 SGTL5000_LINEREG_D_POWERUP,
796                                 SGTL5000_LINEREG_D_POWERUP);
797 
798         /* when internal ldo enabled, simple digital power can be disabled */
799         snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
800                                 SGTL5000_LINREG_SIMPLE_POWERUP,
801                                 0);
802 
803         ldo->enabled = 1;
804         return 0;
805 }
806 
807 static int ldo_regulator_disable(struct regulator_dev *dev)
808 {
809         struct ldo_regulator *ldo = rdev_get_drvdata(dev);
810         struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
811 
812         snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
813                                 SGTL5000_LINEREG_D_POWERUP,
814                                 0);
815 
816         /* clear voltage info */
817         snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
818                                 SGTL5000_LINREG_VDDD_MASK, 0);
819 
820         ldo->enabled = 0;
821 
822         return 0;
823 }
824 
825 static int ldo_regulator_get_voltage(struct regulator_dev *dev)
826 {
827         struct ldo_regulator *ldo = rdev_get_drvdata(dev);
828 
829         return ldo->voltage;
830 }
831 
832 static struct regulator_ops ldo_regulator_ops = {
833         .is_enabled = ldo_regulator_is_enabled,
834         .enable = ldo_regulator_enable,
835         .disable = ldo_regulator_disable,
836         .get_voltage = ldo_regulator_get_voltage,
837 };
838 
839 static int ldo_regulator_register(struct snd_soc_codec *codec,
840                                 struct regulator_init_data *init_data,
841                                 int voltage)
842 {
843         struct ldo_regulator *ldo;
844         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
845         struct regulator_config config = { };
846 
847         ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
848 
849         if (!ldo)
850                 return -ENOMEM;
851 
852         ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
853         if (!ldo->desc.name) {
854                 kfree(ldo);
855                 dev_err(codec->dev, "failed to allocate decs name memory\n");
856                 return -ENOMEM;
857         }
858 
859         ldo->desc.type  = REGULATOR_VOLTAGE;
860         ldo->desc.owner = THIS_MODULE;
861         ldo->desc.ops   = &ldo_regulator_ops;
862         ldo->desc.n_voltages = 1;
863 
864         ldo->codec_data = codec;
865         ldo->voltage = voltage;
866 
867         config.dev = codec->dev;
868         config.driver_data = ldo;
869         config.init_data = init_data;
870 
871         ldo->dev = regulator_register(&ldo->desc, &config);
872         if (IS_ERR(ldo->dev)) {
873                 int ret = PTR_ERR(ldo->dev);
874 
875                 dev_err(codec->dev, "failed to register regulator\n");
876                 kfree(ldo->desc.name);
877                 kfree(ldo);
878 
879                 return ret;
880         }
881         sgtl5000->ldo = ldo;
882 
883         return 0;
884 }
885 
886 static int ldo_regulator_remove(struct snd_soc_codec *codec)
887 {
888         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
889         struct ldo_regulator *ldo = sgtl5000->ldo;
890 
891         if (!ldo)
892                 return 0;
893 
894         regulator_unregister(ldo->dev);
895         kfree(ldo->desc.name);
896         kfree(ldo);
897 
898         return 0;
899 }
900 #else
901 static int ldo_regulator_register(struct snd_soc_codec *codec,
902                                 struct regulator_init_data *init_data,
903                                 int voltage)
904 {
905         dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
906         return -EINVAL;
907 }
908 
909 static int ldo_regulator_remove(struct snd_soc_codec *codec)
910 {
911         return 0;
912 }
913 #endif
914 
915 /*
916  * set dac bias
917  * common state changes:
918  * startup:
919  * off --> standby --> prepare --> on
920  * standby --> prepare --> on
921  *
922  * stop:
923  * on --> prepare --> standby
924  */
925 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
926                                    enum snd_soc_bias_level level)
927 {
928         int ret;
929         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
930 
931         switch (level) {
932         case SND_SOC_BIAS_ON:
933         case SND_SOC_BIAS_PREPARE:
934                 break;
935         case SND_SOC_BIAS_STANDBY:
936                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
937                         ret = regulator_bulk_enable(
938                                                 ARRAY_SIZE(sgtl5000->supplies),
939                                                 sgtl5000->supplies);
940                         if (ret)
941                                 return ret;
942                         udelay(10);
943 
944                         regcache_cache_only(sgtl5000->regmap, false);
945 
946                         ret = regcache_sync(sgtl5000->regmap);
947                         if (ret != 0) {
948                                 dev_err(codec->dev,
949                                         "Failed to restore cache: %d\n", ret);
950 
951                                 regcache_cache_only(sgtl5000->regmap, true);
952                                 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
953                                                        sgtl5000->supplies);
954 
955                                 return ret;
956                         }
957                 }
958 
959                 break;
960         case SND_SOC_BIAS_OFF:
961                 regcache_cache_only(sgtl5000->regmap, true);
962                 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
963                                         sgtl5000->supplies);
964                 break;
965         }
966 
967         codec->dapm.bias_level = level;
968         return 0;
969 }
970 
971 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
972                         SNDRV_PCM_FMTBIT_S20_3LE |\
973                         SNDRV_PCM_FMTBIT_S24_LE |\
974                         SNDRV_PCM_FMTBIT_S32_LE)
975 
976 static const struct snd_soc_dai_ops sgtl5000_ops = {
977         .hw_params = sgtl5000_pcm_hw_params,
978         .digital_mute = sgtl5000_digital_mute,
979         .set_fmt = sgtl5000_set_dai_fmt,
980         .set_sysclk = sgtl5000_set_dai_sysclk,
981 };
982 
983 static struct snd_soc_dai_driver sgtl5000_dai = {
984         .name = "sgtl5000",
985         .playback = {
986                 .stream_name = "Playback",
987                 .channels_min = 1,
988                 .channels_max = 2,
989                 /*
990                  * only support 8~48K + 96K,
991                  * TODO modify hw_param to support more
992                  */
993                 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
994                 .formats = SGTL5000_FORMATS,
995         },
996         .capture = {
997                 .stream_name = "Capture",
998                 .channels_min = 1,
999                 .channels_max = 2,
1000                 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1001                 .formats = SGTL5000_FORMATS,
1002         },
1003         .ops = &sgtl5000_ops,
1004         .symmetric_rates = 1,
1005 };
1006 
1007 static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
1008 {
1009         switch (reg) {
1010         case SGTL5000_CHIP_ID:
1011         case SGTL5000_CHIP_ADCDAC_CTRL:
1012         case SGTL5000_CHIP_ANA_STATUS:
1013                 return true;
1014         }
1015 
1016         return false;
1017 }
1018 
1019 static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1020 {
1021         switch (reg) {
1022         case SGTL5000_CHIP_ID:
1023         case SGTL5000_CHIP_DIG_POWER:
1024         case SGTL5000_CHIP_CLK_CTRL:
1025         case SGTL5000_CHIP_I2S_CTRL:
1026         case SGTL5000_CHIP_SSS_CTRL:
1027         case SGTL5000_CHIP_ADCDAC_CTRL:
1028         case SGTL5000_CHIP_DAC_VOL:
1029         case SGTL5000_CHIP_PAD_STRENGTH:
1030         case SGTL5000_CHIP_ANA_ADC_CTRL:
1031         case SGTL5000_CHIP_ANA_HP_CTRL:
1032         case SGTL5000_CHIP_ANA_CTRL:
1033         case SGTL5000_CHIP_LINREG_CTRL:
1034         case SGTL5000_CHIP_REF_CTRL:
1035         case SGTL5000_CHIP_MIC_CTRL:
1036         case SGTL5000_CHIP_LINE_OUT_CTRL:
1037         case SGTL5000_CHIP_LINE_OUT_VOL:
1038         case SGTL5000_CHIP_ANA_POWER:
1039         case SGTL5000_CHIP_PLL_CTRL:
1040         case SGTL5000_CHIP_CLK_TOP_CTRL:
1041         case SGTL5000_CHIP_ANA_STATUS:
1042         case SGTL5000_CHIP_SHORT_CTRL:
1043         case SGTL5000_CHIP_ANA_TEST2:
1044         case SGTL5000_DAP_CTRL:
1045         case SGTL5000_DAP_PEQ:
1046         case SGTL5000_DAP_BASS_ENHANCE:
1047         case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1048         case SGTL5000_DAP_AUDIO_EQ:
1049         case SGTL5000_DAP_SURROUND:
1050         case SGTL5000_DAP_FLT_COEF_ACCESS:
1051         case SGTL5000_DAP_COEF_WR_B0_MSB:
1052         case SGTL5000_DAP_COEF_WR_B0_LSB:
1053         case SGTL5000_DAP_EQ_BASS_BAND0:
1054         case SGTL5000_DAP_EQ_BASS_BAND1:
1055         case SGTL5000_DAP_EQ_BASS_BAND2:
1056         case SGTL5000_DAP_EQ_BASS_BAND3:
1057         case SGTL5000_DAP_EQ_BASS_BAND4:
1058         case SGTL5000_DAP_MAIN_CHAN:
1059         case SGTL5000_DAP_MIX_CHAN:
1060         case SGTL5000_DAP_AVC_CTRL:
1061         case SGTL5000_DAP_AVC_THRESHOLD:
1062         case SGTL5000_DAP_AVC_ATTACK:
1063         case SGTL5000_DAP_AVC_DECAY:
1064         case SGTL5000_DAP_COEF_WR_B1_MSB:
1065         case SGTL5000_DAP_COEF_WR_B1_LSB:
1066         case SGTL5000_DAP_COEF_WR_B2_MSB:
1067         case SGTL5000_DAP_COEF_WR_B2_LSB:
1068         case SGTL5000_DAP_COEF_WR_A1_MSB:
1069         case SGTL5000_DAP_COEF_WR_A1_LSB:
1070         case SGTL5000_DAP_COEF_WR_A2_MSB:
1071         case SGTL5000_DAP_COEF_WR_A2_LSB:
1072                 return true;
1073 
1074         default:
1075                 return false;
1076         }
1077 }
1078 
1079 /*
1080  * sgtl5000 has 3 internal power supplies:
1081  * 1. VAG, normally set to vdda/2
1082  * 2. chargepump, set to different value
1083  *      according to voltage of vdda and vddio
1084  * 3. line out VAG, normally set to vddio/2
1085  *
1086  * and should be set according to:
1087  * 1. vddd provided by external or not
1088  * 2. vdda and vddio voltage value. > 3.1v or not
1089  * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1090  */
1091 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1092 {
1093         int vddd;
1094         int vdda;
1095         int vddio;
1096         u16 ana_pwr;
1097         u16 lreg_ctrl;
1098         int vag;
1099         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1100 
1101         vdda  = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1102         vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1103         vddd  = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1104 
1105         vdda  = vdda / 1000;
1106         vddio = vddio / 1000;
1107         vddd  = vddd / 1000;
1108 
1109         if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1110                 dev_err(codec->dev, "regulator voltage not set correctly\n");
1111 
1112                 return -EINVAL;
1113         }
1114 
1115         /* according to datasheet, maximum voltage of supplies */
1116         if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1117                 dev_err(codec->dev,
1118                         "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1119                         vdda, vddio, vddd);
1120 
1121                 return -EINVAL;
1122         }
1123 
1124         /* reset value */
1125         ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1126         ana_pwr |= SGTL5000_DAC_STEREO |
1127                         SGTL5000_ADC_STEREO |
1128                         SGTL5000_REFTOP_POWERUP;
1129         lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1130 
1131         if (vddio < 3100 && vdda < 3100) {
1132                 /* enable internal oscillator used for charge pump */
1133                 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1134                                         SGTL5000_INT_OSC_EN,
1135                                         SGTL5000_INT_OSC_EN);
1136                 /* Enable VDDC charge pump */
1137                 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1138         } else if (vddio >= 3100 && vdda >= 3100) {
1139                 /*
1140                  * if vddio and vddd > 3.1v,
1141                  * charge pump should be clean before set ana_pwr
1142                  */
1143                 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1144                                 SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
1145 
1146                 /* VDDC use VDDIO rail */
1147                 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1148                 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1149                             SGTL5000_VDDC_MAN_ASSN_SHIFT;
1150         }
1151 
1152         snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1153 
1154         snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1155 
1156         /* set voltage to register */
1157         snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
1158                                 SGTL5000_LINREG_VDDD_MASK, 0x8);
1159 
1160         /*
1161          * if vddd linear reg has been enabled,
1162          * simple digital supply should be clear to get
1163          * proper VDDD voltage.
1164          */
1165         if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1166                 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1167                                 SGTL5000_LINREG_SIMPLE_POWERUP,
1168                                 0);
1169         else
1170                 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1171                                 SGTL5000_LINREG_SIMPLE_POWERUP |
1172                                 SGTL5000_STARTUP_POWERUP,
1173                                 0);
1174 
1175         /*
1176          * set ADC/DAC VAG to vdda / 2,
1177          * should stay in range (0.8v, 1.575v)
1178          */
1179         vag = vdda / 2;
1180         if (vag <= SGTL5000_ANA_GND_BASE)
1181                 vag = 0;
1182         else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1183                  (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1184                 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1185         else
1186                 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1187 
1188         snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1189                         SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1190 
1191         /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1192         vag = vddio / 2;
1193         if (vag <= SGTL5000_LINE_OUT_GND_BASE)
1194                 vag = 0;
1195         else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
1196                 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1197                 vag = SGTL5000_LINE_OUT_GND_MAX;
1198         else
1199                 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
1200                     SGTL5000_LINE_OUT_GND_STP;
1201 
1202         snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1203                         SGTL5000_LINE_OUT_CURRENT_MASK |
1204                         SGTL5000_LINE_OUT_GND_MASK,
1205                         vag << SGTL5000_LINE_OUT_GND_SHIFT |
1206                         SGTL5000_LINE_OUT_CURRENT_360u <<
1207                                 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1208 
1209         return 0;
1210 }
1211 
1212 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1213 {
1214         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1215         int ret;
1216 
1217         /* set internal ldo to 1.2v */
1218         ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1219         if (ret) {
1220                 dev_err(codec->dev,
1221                         "Failed to register vddd internal supplies: %d\n", ret);
1222                 return ret;
1223         }
1224 
1225         sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1226 
1227         dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1228         return 0;
1229 }
1230 
1231 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1232 {
1233         int ret;
1234         int i;
1235         int external_vddd = 0;
1236         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1237         struct regulator *vddd;
1238 
1239         for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1240                 sgtl5000->supplies[i].supply = supply_names[i];
1241 
1242         /* External VDDD only works before revision 0x11 */
1243         if (sgtl5000->revision < 0x11) {
1244                 vddd = regulator_get_optional(codec->dev, "VDDD");
1245                 if (IS_ERR(vddd)) {
1246                         /* See if it's just not registered yet */
1247                         if (PTR_ERR(vddd) == -EPROBE_DEFER)
1248                                 return -EPROBE_DEFER;
1249                 } else {
1250                         external_vddd = 1;
1251                         regulator_put(vddd);
1252                 }
1253         }
1254 
1255         if (!external_vddd) {
1256                 ret = sgtl5000_replace_vddd_with_ldo(codec);
1257                 if (ret)
1258                         return ret;
1259         }
1260 
1261         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1262                                  sgtl5000->supplies);
1263         if (ret)
1264                 goto err_ldo_remove;
1265 
1266         ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1267                                         sgtl5000->supplies);
1268         if (ret)
1269                 goto err_regulator_free;
1270 
1271         /* wait for all power rails bring up */
1272         udelay(10);
1273 
1274         return 0;
1275 
1276 err_regulator_free:
1277         regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1278                                 sgtl5000->supplies);
1279 err_ldo_remove:
1280         if (!external_vddd)
1281                 ldo_regulator_remove(codec);
1282         return ret;
1283 
1284 }
1285 
1286 static int sgtl5000_probe(struct snd_soc_codec *codec)
1287 {
1288         int ret;
1289         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1290 
1291         ret = sgtl5000_enable_regulators(codec);
1292         if (ret)
1293                 return ret;
1294 
1295         /* power up sgtl5000 */
1296         ret = sgtl5000_set_power_regs(codec);
1297         if (ret)
1298                 goto err;
1299 
1300         /* enable small pop, introduce 400ms delay in turning off */
1301         snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1302                                 SGTL5000_SMALL_POP, 1);
1303 
1304         /* disable short cut detector */
1305         snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1306 
1307         /*
1308          * set i2s as default input of sound switch
1309          * TODO: add sound switch to control and dapm widge.
1310          */
1311         snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1312                         SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1313         snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1314                         SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1315 
1316         /* enable dac volume ramp by default */
1317         snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1318                         SGTL5000_DAC_VOL_RAMP_EN |
1319                         SGTL5000_DAC_MUTE_RIGHT |
1320                         SGTL5000_DAC_MUTE_LEFT);
1321 
1322         snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1323 
1324         snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1325                         SGTL5000_HP_ZCD_EN |
1326                         SGTL5000_ADC_ZCD_EN);
1327 
1328         snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2);
1329 
1330         /*
1331          * disable DAP
1332          * TODO:
1333          * Enable DAP in kcontrol and dapm.
1334          */
1335         snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1336 
1337         return 0;
1338 
1339 err:
1340         regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1341                                                 sgtl5000->supplies);
1342         regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1343                                 sgtl5000->supplies);
1344         ldo_regulator_remove(codec);
1345 
1346         return ret;
1347 }
1348 
1349 static int sgtl5000_remove(struct snd_soc_codec *codec)
1350 {
1351         struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1352 
1353         regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1354                                                 sgtl5000->supplies);
1355         regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1356                                 sgtl5000->supplies);
1357         ldo_regulator_remove(codec);
1358 
1359         return 0;
1360 }
1361 
1362 static struct snd_soc_codec_driver sgtl5000_driver = {
1363         .probe = sgtl5000_probe,
1364         .remove = sgtl5000_remove,
1365         .set_bias_level = sgtl5000_set_bias_level,
1366         .suspend_bias_off = true,
1367         .controls = sgtl5000_snd_controls,
1368         .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1369         .dapm_widgets = sgtl5000_dapm_widgets,
1370         .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1371         .dapm_routes = sgtl5000_dapm_routes,
1372         .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1373 };
1374 
1375 static const struct regmap_config sgtl5000_regmap = {
1376         .reg_bits = 16,
1377         .val_bits = 16,
1378         .reg_stride = 2,
1379 
1380         .max_register = SGTL5000_MAX_REG_OFFSET,
1381         .volatile_reg = sgtl5000_volatile,
1382         .readable_reg = sgtl5000_readable,
1383 
1384         .cache_type = REGCACHE_RBTREE,
1385         .reg_defaults = sgtl5000_reg_defaults,
1386         .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1387 };
1388 
1389 /*
1390  * Write all the default values from sgtl5000_reg_defaults[] array into the
1391  * sgtl5000 registers, to make sure we always start with the sane registers
1392  * values as stated in the datasheet.
1393  *
1394  * Since sgtl5000 does not have a reset line, nor a reset command in software,
1395  * we follow this approach to guarantee we always start from the default values
1396  * and avoid problems like, not being able to probe after an audio playback
1397  * followed by a system reset or a 'reboot' command in Linux
1398  */
1399 static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000)
1400 {
1401         int i, ret, val, index;
1402 
1403         for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1404                 val = sgtl5000_reg_defaults[i].def;
1405                 index = sgtl5000_reg_defaults[i].reg;
1406                 ret = regmap_write(sgtl5000->regmap, index, val);
1407                 if (ret)
1408                         return ret;
1409         }
1410 
1411         return 0;
1412 }
1413 
1414 static int sgtl5000_i2c_probe(struct i2c_client *client,
1415                               const struct i2c_device_id *id)
1416 {
1417         struct sgtl5000_priv *sgtl5000;
1418         int ret, reg, rev;
1419         unsigned int mclk;
1420 
1421         sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv),
1422                                                                 GFP_KERNEL);
1423         if (!sgtl5000)
1424                 return -ENOMEM;
1425 
1426         sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1427         if (IS_ERR(sgtl5000->regmap)) {
1428                 ret = PTR_ERR(sgtl5000->regmap);
1429                 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1430                 return ret;
1431         }
1432 
1433         sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1434         if (IS_ERR(sgtl5000->mclk)) {
1435                 ret = PTR_ERR(sgtl5000->mclk);
1436                 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
1437                 /* Defer the probe to see if the clk will be provided later */
1438                 if (ret == -ENOENT)
1439                         return -EPROBE_DEFER;
1440                 return ret;
1441         }
1442 
1443         /* SGTL5000 SYS_MCLK should be between 8 and 27 MHz */
1444         mclk = clk_get_rate(sgtl5000->mclk);
1445         if (mclk < 8000000 || mclk > 27000000) {
1446                 dev_err(&client->dev, "Invalid SYS_CLK frequency: %u.%03uMHz\n",
1447                         mclk / 1000000, mclk / 1000 % 1000);
1448                 return -EINVAL;
1449         }
1450 
1451         ret = clk_prepare_enable(sgtl5000->mclk);
1452         if (ret)
1453                 return ret;
1454 
1455         /* read chip information */
1456         ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
1457         if (ret)
1458                 goto disable_clk;
1459 
1460         if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1461             SGTL5000_PARTID_PART_ID) {
1462                 dev_err(&client->dev,
1463                         "Device with ID register %x is not a sgtl5000\n", reg);
1464                 ret = -ENODEV;
1465                 goto disable_clk;
1466         }
1467 
1468         rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1469         dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1470         sgtl5000->revision = rev;
1471 
1472         i2c_set_clientdata(client, sgtl5000);
1473 
1474         /* Ensure sgtl5000 will start with sane register values */
1475         ret = sgtl5000_fill_defaults(sgtl5000);
1476         if (ret)
1477                 goto disable_clk;
1478 
1479         ret = snd_soc_register_codec(&client->dev,
1480                         &sgtl5000_driver, &sgtl5000_dai, 1);
1481         if (ret)
1482                 goto disable_clk;
1483 
1484         return 0;
1485 
1486 disable_clk:
1487         clk_disable_unprepare(sgtl5000->mclk);
1488         return ret;
1489 }
1490 
1491 static int sgtl5000_i2c_remove(struct i2c_client *client)
1492 {
1493         struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1494 
1495         snd_soc_unregister_codec(&client->dev);
1496         clk_disable_unprepare(sgtl5000->mclk);
1497         return 0;
1498 }
1499 
1500 static const struct i2c_device_id sgtl5000_id[] = {
1501         {"sgtl5000", 0},
1502         {},
1503 };
1504 
1505 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1506 
1507 static const struct of_device_id sgtl5000_dt_ids[] = {
1508         { .compatible = "fsl,sgtl5000", },
1509         { /* sentinel */ }
1510 };
1511 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1512 
1513 static struct i2c_driver sgtl5000_i2c_driver = {
1514         .driver = {
1515                    .name = "sgtl5000",
1516                    .owner = THIS_MODULE,
1517                    .of_match_table = sgtl5000_dt_ids,
1518                    },
1519         .probe = sgtl5000_i2c_probe,
1520         .remove = sgtl5000_i2c_remove,
1521         .id_table = sgtl5000_id,
1522 };
1523 
1524 module_i2c_driver(sgtl5000_i2c_driver);
1525 
1526 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1527 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1528 MODULE_LICENSE("GPL");
1529 

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