Version:  2.0.40 2.2.26 2.4.37 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7

Linux/sound/soc/codecs/da9055.c

  1 /*
  2  * DA9055 ALSA Soc codec driver
  3  *
  4  * Copyright (c) 2012 Dialog Semiconductor
  5  *
  6  * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C
  7  * Written by David Chen <david.chen@diasemi.com> and
  8  * Ashish Chavan <ashish.chavan@kpitcummins.com>
  9  *
 10  * This program is free software; you can redistribute it and/or modify it
 11  * under the terms of the GNU General Public License as published by the
 12  * Free Software Foundation; either version 2 of the License, or (at your
 13  * option) any later version.
 14  */
 15 
 16 #include <linux/delay.h>
 17 #include <linux/i2c.h>
 18 #include <linux/regmap.h>
 19 #include <linux/slab.h>
 20 #include <linux/module.h>
 21 #include <linux/of.h>
 22 #include <linux/of_device.h>
 23 #include <sound/pcm.h>
 24 #include <sound/pcm_params.h>
 25 #include <sound/soc.h>
 26 #include <sound/initval.h>
 27 #include <sound/tlv.h>
 28 #include <sound/da9055.h>
 29 
 30 /* DA9055 register space */
 31 
 32 /* Status Registers */
 33 #define DA9055_STATUS1                  0x02
 34 #define DA9055_PLL_STATUS               0x03
 35 #define DA9055_AUX_L_GAIN_STATUS        0x04
 36 #define DA9055_AUX_R_GAIN_STATUS        0x05
 37 #define DA9055_MIC_L_GAIN_STATUS        0x06
 38 #define DA9055_MIC_R_GAIN_STATUS        0x07
 39 #define DA9055_MIXIN_L_GAIN_STATUS      0x08
 40 #define DA9055_MIXIN_R_GAIN_STATUS      0x09
 41 #define DA9055_ADC_L_GAIN_STATUS        0x0A
 42 #define DA9055_ADC_R_GAIN_STATUS        0x0B
 43 #define DA9055_DAC_L_GAIN_STATUS        0x0C
 44 #define DA9055_DAC_R_GAIN_STATUS        0x0D
 45 #define DA9055_HP_L_GAIN_STATUS         0x0E
 46 #define DA9055_HP_R_GAIN_STATUS         0x0F
 47 #define DA9055_LINE_GAIN_STATUS         0x10
 48 
 49 /* System Initialisation Registers */
 50 #define DA9055_CIF_CTRL                 0x20
 51 #define DA9055_DIG_ROUTING_AIF          0X21
 52 #define DA9055_SR                       0x22
 53 #define DA9055_REFERENCES               0x23
 54 #define DA9055_PLL_FRAC_TOP             0x24
 55 #define DA9055_PLL_FRAC_BOT             0x25
 56 #define DA9055_PLL_INTEGER              0x26
 57 #define DA9055_PLL_CTRL                 0x27
 58 #define DA9055_AIF_CLK_MODE             0x28
 59 #define DA9055_AIF_CTRL                 0x29
 60 #define DA9055_DIG_ROUTING_DAC          0x2A
 61 #define DA9055_ALC_CTRL1                0x2B
 62 
 63 /* Input - Gain, Select and Filter Registers */
 64 #define DA9055_AUX_L_GAIN               0x30
 65 #define DA9055_AUX_R_GAIN               0x31
 66 #define DA9055_MIXIN_L_SELECT           0x32
 67 #define DA9055_MIXIN_R_SELECT           0x33
 68 #define DA9055_MIXIN_L_GAIN             0x34
 69 #define DA9055_MIXIN_R_GAIN             0x35
 70 #define DA9055_ADC_L_GAIN               0x36
 71 #define DA9055_ADC_R_GAIN               0x37
 72 #define DA9055_ADC_FILTERS1             0x38
 73 #define DA9055_MIC_L_GAIN               0x39
 74 #define DA9055_MIC_R_GAIN               0x3A
 75 
 76 /* Output - Gain, Select and Filter Registers */
 77 #define DA9055_DAC_FILTERS5             0x40
 78 #define DA9055_DAC_FILTERS2             0x41
 79 #define DA9055_DAC_FILTERS3             0x42
 80 #define DA9055_DAC_FILTERS4             0x43
 81 #define DA9055_DAC_FILTERS1             0x44
 82 #define DA9055_DAC_L_GAIN               0x45
 83 #define DA9055_DAC_R_GAIN               0x46
 84 #define DA9055_CP_CTRL                  0x47
 85 #define DA9055_HP_L_GAIN                0x48
 86 #define DA9055_HP_R_GAIN                0x49
 87 #define DA9055_LINE_GAIN                0x4A
 88 #define DA9055_MIXOUT_L_SELECT          0x4B
 89 #define DA9055_MIXOUT_R_SELECT          0x4C
 90 
 91 /* System Controller Registers */
 92 #define DA9055_SYSTEM_MODES_INPUT       0x50
 93 #define DA9055_SYSTEM_MODES_OUTPUT      0x51
 94 
 95 /* Control Registers */
 96 #define DA9055_AUX_L_CTRL               0x60
 97 #define DA9055_AUX_R_CTRL               0x61
 98 #define DA9055_MIC_BIAS_CTRL            0x62
 99 #define DA9055_MIC_L_CTRL               0x63
100 #define DA9055_MIC_R_CTRL               0x64
101 #define DA9055_MIXIN_L_CTRL             0x65
102 #define DA9055_MIXIN_R_CTRL             0x66
103 #define DA9055_ADC_L_CTRL               0x67
104 #define DA9055_ADC_R_CTRL               0x68
105 #define DA9055_DAC_L_CTRL               0x69
106 #define DA9055_DAC_R_CTRL               0x6A
107 #define DA9055_HP_L_CTRL                0x6B
108 #define DA9055_HP_R_CTRL                0x6C
109 #define DA9055_LINE_CTRL                0x6D
110 #define DA9055_MIXOUT_L_CTRL            0x6E
111 #define DA9055_MIXOUT_R_CTRL            0x6F
112 
113 /* Configuration Registers */
114 #define DA9055_LDO_CTRL                 0x90
115 #define DA9055_IO_CTRL                  0x91
116 #define DA9055_GAIN_RAMP_CTRL           0x92
117 #define DA9055_MIC_CONFIG               0x93
118 #define DA9055_PC_COUNT                 0x94
119 #define DA9055_CP_VOL_THRESHOLD1        0x95
120 #define DA9055_CP_DELAY                 0x96
121 #define DA9055_CP_DETECTOR              0x97
122 #define DA9055_AIF_OFFSET               0x98
123 #define DA9055_DIG_CTRL                 0x99
124 #define DA9055_ALC_CTRL2                0x9A
125 #define DA9055_ALC_CTRL3                0x9B
126 #define DA9055_ALC_NOISE                0x9C
127 #define DA9055_ALC_TARGET_MIN           0x9D
128 #define DA9055_ALC_TARGET_MAX           0x9E
129 #define DA9055_ALC_GAIN_LIMITS          0x9F
130 #define DA9055_ALC_ANA_GAIN_LIMITS      0xA0
131 #define DA9055_ALC_ANTICLIP_CTRL        0xA1
132 #define DA9055_ALC_ANTICLIP_LEVEL       0xA2
133 #define DA9055_ALC_OFFSET_OP2M_L        0xA6
134 #define DA9055_ALC_OFFSET_OP2U_L        0xA7
135 #define DA9055_ALC_OFFSET_OP2M_R        0xAB
136 #define DA9055_ALC_OFFSET_OP2U_R        0xAC
137 #define DA9055_ALC_CIC_OP_LVL_CTRL      0xAD
138 #define DA9055_ALC_CIC_OP_LVL_DATA      0xAE
139 #define DA9055_DAC_NG_SETUP_TIME        0xAF
140 #define DA9055_DAC_NG_OFF_THRESHOLD     0xB0
141 #define DA9055_DAC_NG_ON_THRESHOLD      0xB1
142 #define DA9055_DAC_NG_CTRL              0xB2
143 
144 /* SR bit fields */
145 #define DA9055_SR_8000                  (0x1 << 0)
146 #define DA9055_SR_11025                 (0x2 << 0)
147 #define DA9055_SR_12000                 (0x3 << 0)
148 #define DA9055_SR_16000                 (0x5 << 0)
149 #define DA9055_SR_22050                 (0x6 << 0)
150 #define DA9055_SR_24000                 (0x7 << 0)
151 #define DA9055_SR_32000                 (0x9 << 0)
152 #define DA9055_SR_44100                 (0xA << 0)
153 #define DA9055_SR_48000                 (0xB << 0)
154 #define DA9055_SR_88200                 (0xE << 0)
155 #define DA9055_SR_96000                 (0xF << 0)
156 
157 /* REFERENCES bit fields */
158 #define DA9055_BIAS_EN                  (1 << 3)
159 #define DA9055_VMID_EN                  (1 << 7)
160 
161 /* PLL_CTRL bit fields */
162 #define DA9055_PLL_INDIV_10_20_MHZ      (1 << 2)
163 #define DA9055_PLL_SRM_EN               (1 << 6)
164 #define DA9055_PLL_EN                   (1 << 7)
165 
166 /* AIF_CLK_MODE bit fields */
167 #define DA9055_AIF_BCLKS_PER_WCLK_32    (0 << 0)
168 #define DA9055_AIF_BCLKS_PER_WCLK_64    (1 << 0)
169 #define DA9055_AIF_BCLKS_PER_WCLK_128   (2 << 0)
170 #define DA9055_AIF_BCLKS_PER_WCLK_256   (3 << 0)
171 #define DA9055_AIF_CLK_EN_SLAVE_MODE    (0 << 7)
172 #define DA9055_AIF_CLK_EN_MASTER_MODE   (1 << 7)
173 
174 /* AIF_CTRL bit fields */
175 #define DA9055_AIF_FORMAT_I2S_MODE      (0 << 0)
176 #define DA9055_AIF_FORMAT_LEFT_J        (1 << 0)
177 #define DA9055_AIF_FORMAT_RIGHT_J       (2 << 0)
178 #define DA9055_AIF_FORMAT_DSP           (3 << 0)
179 #define DA9055_AIF_WORD_S16_LE          (0 << 2)
180 #define DA9055_AIF_WORD_S20_3LE         (1 << 2)
181 #define DA9055_AIF_WORD_S24_LE          (2 << 2)
182 #define DA9055_AIF_WORD_S32_LE          (3 << 2)
183 
184 /* MIC_L_CTRL bit fields */
185 #define DA9055_MIC_L_MUTE_EN            (1 << 6)
186 
187 /* MIC_R_CTRL bit fields */
188 #define DA9055_MIC_R_MUTE_EN            (1 << 6)
189 
190 /* MIXIN_L_CTRL bit fields */
191 #define DA9055_MIXIN_L_MIX_EN           (1 << 3)
192 
193 /* MIXIN_R_CTRL bit fields */
194 #define DA9055_MIXIN_R_MIX_EN           (1 << 3)
195 
196 /* ADC_L_CTRL bit fields */
197 #define DA9055_ADC_L_EN                 (1 << 7)
198 
199 /* ADC_R_CTRL bit fields */
200 #define DA9055_ADC_R_EN                 (1 << 7)
201 
202 /* DAC_L_CTRL bit fields */
203 #define DA9055_DAC_L_MUTE_EN            (1 << 6)
204 
205 /* DAC_R_CTRL bit fields */
206 #define DA9055_DAC_R_MUTE_EN            (1 << 6)
207 
208 /* HP_L_CTRL bit fields */
209 #define DA9055_HP_L_AMP_OE              (1 << 3)
210 
211 /* HP_R_CTRL bit fields */
212 #define DA9055_HP_R_AMP_OE              (1 << 3)
213 
214 /* LINE_CTRL bit fields */
215 #define DA9055_LINE_AMP_OE              (1 << 3)
216 
217 /* MIXOUT_L_CTRL bit fields */
218 #define DA9055_MIXOUT_L_MIX_EN          (1 << 3)
219 
220 /* MIXOUT_R_CTRL bit fields */
221 #define DA9055_MIXOUT_R_MIX_EN          (1 << 3)
222 
223 /* MIC bias select bit fields */
224 #define DA9055_MICBIAS2_EN              (1 << 6)
225 
226 /* ALC_CIC_OP_LEVEL_CTRL bit fields */
227 #define DA9055_ALC_DATA_MIDDLE          (2 << 0)
228 #define DA9055_ALC_DATA_TOP             (3 << 0)
229 #define DA9055_ALC_CIC_OP_CHANNEL_LEFT  (0 << 7)
230 #define DA9055_ALC_CIC_OP_CHANNEL_RIGHT (1 << 7)
231 
232 #define DA9055_AIF_BCLK_MASK            (3 << 0)
233 #define DA9055_AIF_CLK_MODE_MASK        (1 << 7)
234 #define DA9055_AIF_FORMAT_MASK          (3 << 0)
235 #define DA9055_AIF_WORD_LENGTH_MASK     (3 << 2)
236 #define DA9055_GAIN_RAMPING_EN          (1 << 5)
237 #define DA9055_MICBIAS_LEVEL_MASK       (3 << 4)
238 
239 #define DA9055_ALC_OFFSET_15_8          0x00FF00
240 #define DA9055_ALC_OFFSET_17_16         0x030000
241 #define DA9055_ALC_AVG_ITERATIONS       5
242 
243 struct pll_div {
244         int fref;
245         int fout;
246         u8 frac_top;
247         u8 frac_bot;
248         u8 integer;
249         u8 mode;        /* 0 = slave, 1 = master */
250 };
251 
252 /* PLL divisor table */
253 static const struct pll_div da9055_pll_div[] = {
254         /* for MASTER mode, fs = 44.1Khz and its harmonics */
255         {11289600, 2822400, 0x00, 0x00, 0x20, 1},       /* MCLK=11.2896Mhz */
256         {12000000, 2822400, 0x03, 0x61, 0x1E, 1},       /* MCLK=12Mhz */
257         {12288000, 2822400, 0x0C, 0xCC, 0x1D, 1},       /* MCLK=12.288Mhz */
258         {13000000, 2822400, 0x19, 0x45, 0x1B, 1},       /* MCLK=13Mhz */
259         {13500000, 2822400, 0x18, 0x56, 0x1A, 1},       /* MCLK=13.5Mhz */
260         {14400000, 2822400, 0x02, 0xD0, 0x19, 1},       /* MCLK=14.4Mhz */
261         {19200000, 2822400, 0x1A, 0x1C, 0x12, 1},       /* MCLK=19.2Mhz */
262         {19680000, 2822400, 0x0B, 0x6D, 0x12, 1},       /* MCLK=19.68Mhz */
263         {19800000, 2822400, 0x07, 0xDD, 0x12, 1},       /* MCLK=19.8Mhz */
264         /* for MASTER mode, fs = 48Khz and its harmonics */
265         {11289600, 3072000, 0x1A, 0x8E, 0x22, 1},       /* MCLK=11.2896Mhz */
266         {12000000, 3072000, 0x18, 0x93, 0x20, 1},       /* MCLK=12Mhz */
267         {12288000, 3072000, 0x00, 0x00, 0x20, 1},       /* MCLK=12.288Mhz */
268         {13000000, 3072000, 0x07, 0xEA, 0x1E, 1},       /* MCLK=13Mhz */
269         {13500000, 3072000, 0x04, 0x11, 0x1D, 1},       /* MCLK=13.5Mhz */
270         {14400000, 3072000, 0x09, 0xD0, 0x1B, 1},       /* MCLK=14.4Mhz */
271         {19200000, 3072000, 0x0F, 0x5C, 0x14, 1},       /* MCLK=19.2Mhz */
272         {19680000, 3072000, 0x1F, 0x60, 0x13, 1},       /* MCLK=19.68Mhz */
273         {19800000, 3072000, 0x1B, 0x80, 0x13, 1},       /* MCLK=19.8Mhz */
274         /* for SLAVE mode with SRM */
275         {11289600, 2822400, 0x0D, 0x47, 0x21, 0},       /* MCLK=11.2896Mhz */
276         {12000000, 2822400, 0x0D, 0xFA, 0x1F, 0},       /* MCLK=12Mhz */
277         {12288000, 2822400, 0x16, 0x66, 0x1E, 0},       /* MCLK=12.288Mhz */
278         {13000000, 2822400, 0x00, 0x98, 0x1D, 0},       /* MCLK=13Mhz */
279         {13500000, 2822400, 0x1E, 0x33, 0x1B, 0},       /* MCLK=13.5Mhz */
280         {14400000, 2822400, 0x06, 0x50, 0x1A, 0},       /* MCLK=14.4Mhz */
281         {19200000, 2822400, 0x14, 0xBC, 0x13, 0},       /* MCLK=19.2Mhz */
282         {19680000, 2822400, 0x05, 0x66, 0x13, 0},       /* MCLK=19.68Mhz */
283         {19800000, 2822400, 0x01, 0xAE, 0x13, 0},       /* MCLK=19.8Mhz  */
284 };
285 
286 enum clk_src {
287         DA9055_CLKSRC_MCLK
288 };
289 
290 /* Gain and Volume */
291 
292 static const DECLARE_TLV_DB_RANGE(aux_vol_tlv,
293         0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0),
294         /* -54dB to 15dB */
295         0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
296 );
297 
298 static const DECLARE_TLV_DB_RANGE(digital_gain_tlv,
299         0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
300         /* -78dB to 12dB */
301         0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
302 );
303 
304 static const DECLARE_TLV_DB_RANGE(alc_analog_gain_tlv,
305         0x0, 0x0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
306         /* 0dB to 36dB */
307         0x01, 0x07, TLV_DB_SCALE_ITEM(0, 600, 0)
308 );
309 
310 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
311 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
312 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
313 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0);
314 static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0);
316 static const DECLARE_TLV_DB_SCALE(alc_gain_tlv, 0, 600, 0);
317 
318 /* ADC and DAC high pass filter cutoff value */
319 static const char * const da9055_hpf_cutoff_txt[] = {
320         "Fs/24000", "Fs/12000", "Fs/6000", "Fs/3000"
321 };
322 
323 static SOC_ENUM_SINGLE_DECL(da9055_dac_hpf_cutoff,
324                             DA9055_DAC_FILTERS1, 4, da9055_hpf_cutoff_txt);
325 
326 static SOC_ENUM_SINGLE_DECL(da9055_adc_hpf_cutoff,
327                             DA9055_ADC_FILTERS1, 4, da9055_hpf_cutoff_txt);
328 
329 /* ADC and DAC voice mode (8kHz) high pass cutoff value */
330 static const char * const da9055_vf_cutoff_txt[] = {
331         "2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
332 };
333 
334 static SOC_ENUM_SINGLE_DECL(da9055_dac_vf_cutoff,
335                             DA9055_DAC_FILTERS1, 0, da9055_vf_cutoff_txt);
336 
337 static SOC_ENUM_SINGLE_DECL(da9055_adc_vf_cutoff,
338                             DA9055_ADC_FILTERS1, 0, da9055_vf_cutoff_txt);
339 
340 /* Gain ramping rate value */
341 static const char * const da9055_gain_ramping_txt[] = {
342         "nominal rate", "nominal rate * 4", "nominal rate * 8",
343         "nominal rate / 8"
344 };
345 
346 static SOC_ENUM_SINGLE_DECL(da9055_gain_ramping_rate,
347                             DA9055_GAIN_RAMP_CTRL, 0, da9055_gain_ramping_txt);
348 
349 /* DAC noise gate setup time value */
350 static const char * const da9055_dac_ng_setup_time_txt[] = {
351         "256 samples", "512 samples", "1024 samples", "2048 samples"
352 };
353 
354 static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_setup_time,
355                             DA9055_DAC_NG_SETUP_TIME, 0,
356                             da9055_dac_ng_setup_time_txt);
357 
358 /* DAC noise gate rampup rate value */
359 static const char * const da9055_dac_ng_rampup_txt[] = {
360         "0.02 ms/dB", "0.16 ms/dB"
361 };
362 
363 static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_rampup_rate,
364                             DA9055_DAC_NG_SETUP_TIME, 2,
365                             da9055_dac_ng_rampup_txt);
366 
367 /* DAC noise gate rampdown rate value */
368 static const char * const da9055_dac_ng_rampdown_txt[] = {
369         "0.64 ms/dB", "20.48 ms/dB"
370 };
371 
372 static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_rampdown_rate,
373                             DA9055_DAC_NG_SETUP_TIME, 3,
374                             da9055_dac_ng_rampdown_txt);
375 
376 /* DAC soft mute rate value */
377 static const char * const da9055_dac_soft_mute_rate_txt[] = {
378         "1", "2", "4", "8", "16", "32", "64"
379 };
380 
381 static SOC_ENUM_SINGLE_DECL(da9055_dac_soft_mute_rate,
382                             DA9055_DAC_FILTERS5, 4,
383                             da9055_dac_soft_mute_rate_txt);
384 
385 /* DAC routing select */
386 static const char * const da9055_dac_src_txt[] = {
387         "ADC output left", "ADC output right", "AIF input left",
388         "AIF input right"
389 };
390 
391 static SOC_ENUM_SINGLE_DECL(da9055_dac_l_src,
392                             DA9055_DIG_ROUTING_DAC, 0, da9055_dac_src_txt);
393 
394 static SOC_ENUM_SINGLE_DECL(da9055_dac_r_src,
395                             DA9055_DIG_ROUTING_DAC, 4, da9055_dac_src_txt);
396 
397 /* MIC PGA Left source select */
398 static const char * const da9055_mic_l_src_txt[] = {
399         "MIC1_P_N", "MIC1_P", "MIC1_N", "MIC2_L"
400 };
401 
402 static SOC_ENUM_SINGLE_DECL(da9055_mic_l_src,
403                             DA9055_MIXIN_L_SELECT, 4, da9055_mic_l_src_txt);
404 
405 /* MIC PGA Right source select */
406 static const char * const da9055_mic_r_src_txt[] = {
407         "MIC2_R_L", "MIC2_R", "MIC2_L"
408 };
409 
410 static SOC_ENUM_SINGLE_DECL(da9055_mic_r_src,
411                             DA9055_MIXIN_R_SELECT, 4, da9055_mic_r_src_txt);
412 
413 /* ALC Input Signal Tracking rate select */
414 static const char * const da9055_signal_tracking_rate_txt[] = {
415         "1/4", "1/16", "1/256", "1/65536"
416 };
417 
418 static SOC_ENUM_SINGLE_DECL(da9055_integ_attack_rate,
419                             DA9055_ALC_CTRL3, 4,
420                             da9055_signal_tracking_rate_txt);
421 
422 static SOC_ENUM_SINGLE_DECL(da9055_integ_release_rate,
423                             DA9055_ALC_CTRL3, 6,
424                             da9055_signal_tracking_rate_txt);
425 
426 /* ALC Attack Rate select */
427 static const char * const da9055_attack_rate_txt[] = {
428         "44/fs", "88/fs", "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs",
429         "5632/fs", "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
430 };
431 
432 static SOC_ENUM_SINGLE_DECL(da9055_attack_rate,
433                             DA9055_ALC_CTRL2, 0, da9055_attack_rate_txt);
434 
435 /* ALC Release Rate select */
436 static const char * const da9055_release_rate_txt[] = {
437         "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", "5632/fs",
438         "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
439 };
440 
441 static SOC_ENUM_SINGLE_DECL(da9055_release_rate,
442                             DA9055_ALC_CTRL2, 4, da9055_release_rate_txt);
443 
444 /* ALC Hold Time select */
445 static const char * const da9055_hold_time_txt[] = {
446         "62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
447         "7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
448         "253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
449 };
450 
451 static SOC_ENUM_SINGLE_DECL(da9055_hold_time,
452                             DA9055_ALC_CTRL3, 0, da9055_hold_time_txt);
453 
454 static int da9055_get_alc_data(struct snd_soc_codec *codec, u8 reg_val)
455 {
456         int mid_data, top_data;
457         int sum = 0;
458         u8 iteration;
459 
460         for (iteration = 0; iteration < DA9055_ALC_AVG_ITERATIONS;
461              iteration++) {
462                 /* Select the left or right channel and capture data */
463                 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL, reg_val);
464 
465                 /* Select middle 8 bits for read back from data register */
466                 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL,
467                               reg_val | DA9055_ALC_DATA_MIDDLE);
468                 mid_data = snd_soc_read(codec, DA9055_ALC_CIC_OP_LVL_DATA);
469 
470                 /* Select top 8 bits for read back from data register */
471                 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL,
472                               reg_val | DA9055_ALC_DATA_TOP);
473                 top_data = snd_soc_read(codec, DA9055_ALC_CIC_OP_LVL_DATA);
474 
475                 sum += ((mid_data << 8) | (top_data << 16));
476         }
477 
478         return sum / DA9055_ALC_AVG_ITERATIONS;
479 }
480 
481 static int da9055_put_alc_sw(struct snd_kcontrol *kcontrol,
482                              struct snd_ctl_elem_value *ucontrol)
483 {
484         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
485         u8 reg_val, adc_left, adc_right, mic_left, mic_right;
486         int avg_left_data, avg_right_data, offset_l, offset_r;
487 
488         if (ucontrol->value.integer.value[0]) {
489                 /*
490                  * While enabling ALC (or ALC sync mode), calibration of the DC
491                  * offsets must be done first
492                  */
493 
494                 /* Save current values from Mic control registers */
495                 mic_left = snd_soc_read(codec, DA9055_MIC_L_CTRL);
496                 mic_right = snd_soc_read(codec, DA9055_MIC_R_CTRL);
497 
498                 /* Mute Mic PGA Left and Right */
499                 snd_soc_update_bits(codec, DA9055_MIC_L_CTRL,
500                                     DA9055_MIC_L_MUTE_EN, DA9055_MIC_L_MUTE_EN);
501                 snd_soc_update_bits(codec, DA9055_MIC_R_CTRL,
502                                     DA9055_MIC_R_MUTE_EN, DA9055_MIC_R_MUTE_EN);
503 
504                 /* Save current values from ADC control registers */
505                 adc_left = snd_soc_read(codec, DA9055_ADC_L_CTRL);
506                 adc_right = snd_soc_read(codec, DA9055_ADC_R_CTRL);
507 
508                 /* Enable ADC Left and Right */
509                 snd_soc_update_bits(codec, DA9055_ADC_L_CTRL,
510                                     DA9055_ADC_L_EN, DA9055_ADC_L_EN);
511                 snd_soc_update_bits(codec, DA9055_ADC_R_CTRL,
512                                     DA9055_ADC_R_EN, DA9055_ADC_R_EN);
513 
514                 /* Calculate average for Left and Right data */
515                 /* Left Data */
516                 avg_left_data = da9055_get_alc_data(codec,
517                                 DA9055_ALC_CIC_OP_CHANNEL_LEFT);
518                 /* Right Data */
519                 avg_right_data = da9055_get_alc_data(codec,
520                                  DA9055_ALC_CIC_OP_CHANNEL_RIGHT);
521 
522                 /* Calculate DC offset */
523                 offset_l = -avg_left_data;
524                 offset_r = -avg_right_data;
525 
526                 reg_val = (offset_l & DA9055_ALC_OFFSET_15_8) >> 8;
527                 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2M_L, reg_val);
528                 reg_val = (offset_l & DA9055_ALC_OFFSET_17_16) >> 16;
529                 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2U_L, reg_val);
530 
531                 reg_val = (offset_r & DA9055_ALC_OFFSET_15_8) >> 8;
532                 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2M_R, reg_val);
533                 reg_val = (offset_r & DA9055_ALC_OFFSET_17_16) >> 16;
534                 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2U_R, reg_val);
535 
536                 /* Restore original values of ADC control registers */
537                 snd_soc_write(codec, DA9055_ADC_L_CTRL, adc_left);
538                 snd_soc_write(codec, DA9055_ADC_R_CTRL, adc_right);
539 
540                 /* Restore original values of Mic control registers */
541                 snd_soc_write(codec, DA9055_MIC_L_CTRL, mic_left);
542                 snd_soc_write(codec, DA9055_MIC_R_CTRL, mic_right);
543         }
544 
545         return snd_soc_put_volsw(kcontrol, ucontrol);
546 }
547 
548 static const struct snd_kcontrol_new da9055_snd_controls[] = {
549 
550         /* Volume controls */
551         SOC_DOUBLE_R_TLV("Mic Volume",
552                          DA9055_MIC_L_GAIN, DA9055_MIC_R_GAIN,
553                          0, 0x7, 0, mic_vol_tlv),
554         SOC_DOUBLE_R_TLV("Aux Volume",
555                          DA9055_AUX_L_GAIN, DA9055_AUX_R_GAIN,
556                          0, 0x3f, 0, aux_vol_tlv),
557         SOC_DOUBLE_R_TLV("Mixin PGA Volume",
558                          DA9055_MIXIN_L_GAIN, DA9055_MIXIN_R_GAIN,
559                          0, 0xf, 0, mixin_gain_tlv),
560         SOC_DOUBLE_R_TLV("ADC Volume",
561                          DA9055_ADC_L_GAIN, DA9055_ADC_R_GAIN,
562                          0, 0x7f, 0, digital_gain_tlv),
563 
564         SOC_DOUBLE_R_TLV("DAC Volume",
565                          DA9055_DAC_L_GAIN, DA9055_DAC_R_GAIN,
566                          0, 0x7f, 0, digital_gain_tlv),
567         SOC_DOUBLE_R_TLV("Headphone Volume",
568                          DA9055_HP_L_GAIN, DA9055_HP_R_GAIN,
569                          0, 0x3f, 0, hp_vol_tlv),
570         SOC_SINGLE_TLV("Lineout Volume", DA9055_LINE_GAIN, 0, 0x3f, 0,
571                        lineout_vol_tlv),
572 
573         /* DAC Equalizer controls */
574         SOC_SINGLE("DAC EQ Switch", DA9055_DAC_FILTERS4, 7, 1, 0),
575         SOC_SINGLE_TLV("DAC EQ1 Volume", DA9055_DAC_FILTERS2, 0, 0xf, 0,
576                        eq_gain_tlv),
577         SOC_SINGLE_TLV("DAC EQ2 Volume", DA9055_DAC_FILTERS2, 4, 0xf, 0,
578                        eq_gain_tlv),
579         SOC_SINGLE_TLV("DAC EQ3 Volume", DA9055_DAC_FILTERS3, 0, 0xf, 0,
580                        eq_gain_tlv),
581         SOC_SINGLE_TLV("DAC EQ4 Volume", DA9055_DAC_FILTERS3, 4, 0xf, 0,
582                        eq_gain_tlv),
583         SOC_SINGLE_TLV("DAC EQ5 Volume", DA9055_DAC_FILTERS4, 0, 0xf, 0,
584                        eq_gain_tlv),
585 
586         /* High Pass Filter and Voice Mode controls */
587         SOC_SINGLE("ADC HPF Switch", DA9055_ADC_FILTERS1, 7, 1, 0),
588         SOC_ENUM("ADC HPF Cutoff", da9055_adc_hpf_cutoff),
589         SOC_SINGLE("ADC Voice Mode Switch", DA9055_ADC_FILTERS1, 3, 1, 0),
590         SOC_ENUM("ADC Voice Cutoff", da9055_adc_vf_cutoff),
591 
592         SOC_SINGLE("DAC HPF Switch", DA9055_DAC_FILTERS1, 7, 1, 0),
593         SOC_ENUM("DAC HPF Cutoff", da9055_dac_hpf_cutoff),
594         SOC_SINGLE("DAC Voice Mode Switch", DA9055_DAC_FILTERS1, 3, 1, 0),
595         SOC_ENUM("DAC Voice Cutoff", da9055_dac_vf_cutoff),
596 
597         /* Mute controls */
598         SOC_DOUBLE_R("Mic Switch", DA9055_MIC_L_CTRL,
599                      DA9055_MIC_R_CTRL, 6, 1, 0),
600         SOC_DOUBLE_R("Aux Switch", DA9055_AUX_L_CTRL,
601                      DA9055_AUX_R_CTRL, 6, 1, 0),
602         SOC_DOUBLE_R("Mixin PGA Switch", DA9055_MIXIN_L_CTRL,
603                      DA9055_MIXIN_R_CTRL, 6, 1, 0),
604         SOC_DOUBLE_R("ADC Switch", DA9055_ADC_L_CTRL,
605                      DA9055_ADC_R_CTRL, 6, 1, 0),
606         SOC_DOUBLE_R("Headphone Switch", DA9055_HP_L_CTRL,
607                      DA9055_HP_R_CTRL, 6, 1, 0),
608         SOC_SINGLE("Lineout Switch", DA9055_LINE_CTRL, 6, 1, 0),
609         SOC_SINGLE("DAC Soft Mute Switch", DA9055_DAC_FILTERS5, 7, 1, 0),
610         SOC_ENUM("DAC Soft Mute Rate", da9055_dac_soft_mute_rate),
611 
612         /* Zero Cross controls */
613         SOC_DOUBLE_R("Aux ZC Switch", DA9055_AUX_L_CTRL,
614                      DA9055_AUX_R_CTRL, 4, 1, 0),
615         SOC_DOUBLE_R("Mixin PGA ZC Switch", DA9055_MIXIN_L_CTRL,
616                      DA9055_MIXIN_R_CTRL, 4, 1, 0),
617         SOC_DOUBLE_R("Headphone ZC Switch", DA9055_HP_L_CTRL,
618                      DA9055_HP_R_CTRL, 4, 1, 0),
619         SOC_SINGLE("Lineout ZC Switch", DA9055_LINE_CTRL, 4, 1, 0),
620 
621         /* Gain Ramping controls */
622         SOC_DOUBLE_R("Aux Gain Ramping Switch", DA9055_AUX_L_CTRL,
623                      DA9055_AUX_R_CTRL, 5, 1, 0),
624         SOC_DOUBLE_R("Mixin Gain Ramping Switch", DA9055_MIXIN_L_CTRL,
625                      DA9055_MIXIN_R_CTRL, 5, 1, 0),
626         SOC_DOUBLE_R("ADC Gain Ramping Switch", DA9055_ADC_L_CTRL,
627                      DA9055_ADC_R_CTRL, 5, 1, 0),
628         SOC_DOUBLE_R("DAC Gain Ramping Switch", DA9055_DAC_L_CTRL,
629                      DA9055_DAC_R_CTRL, 5, 1, 0),
630         SOC_DOUBLE_R("Headphone Gain Ramping Switch", DA9055_HP_L_CTRL,
631                      DA9055_HP_R_CTRL, 5, 1, 0),
632         SOC_SINGLE("Lineout Gain Ramping Switch", DA9055_LINE_CTRL, 5, 1, 0),
633         SOC_ENUM("Gain Ramping Rate", da9055_gain_ramping_rate),
634 
635         /* DAC Noise Gate controls */
636         SOC_SINGLE("DAC NG Switch", DA9055_DAC_NG_CTRL, 7, 1, 0),
637         SOC_SINGLE("DAC NG ON Threshold", DA9055_DAC_NG_ON_THRESHOLD,
638                    0, 0x7, 0),
639         SOC_SINGLE("DAC NG OFF Threshold", DA9055_DAC_NG_OFF_THRESHOLD,
640                    0, 0x7, 0),
641         SOC_ENUM("DAC NG Setup Time", da9055_dac_ng_setup_time),
642         SOC_ENUM("DAC NG Rampup Rate", da9055_dac_ng_rampup_rate),
643         SOC_ENUM("DAC NG Rampdown Rate", da9055_dac_ng_rampdown_rate),
644 
645         /* DAC Invertion control */
646         SOC_SINGLE("DAC Left Invert", DA9055_DIG_CTRL, 3, 1, 0),
647         SOC_SINGLE("DAC Right Invert", DA9055_DIG_CTRL, 7, 1, 0),
648 
649         /* DMIC controls */
650         SOC_DOUBLE_R("DMIC Switch", DA9055_MIXIN_L_SELECT,
651                      DA9055_MIXIN_R_SELECT, 7, 1, 0),
652 
653         /* ALC Controls */
654         SOC_DOUBLE_EXT("ALC Switch", DA9055_ALC_CTRL1, 3, 7, 1, 0,
655                        snd_soc_get_volsw, da9055_put_alc_sw),
656         SOC_SINGLE_EXT("ALC Sync Mode Switch", DA9055_ALC_CTRL1, 1, 1, 0,
657                        snd_soc_get_volsw, da9055_put_alc_sw),
658         SOC_SINGLE("ALC Offset Switch", DA9055_ALC_CTRL1, 0, 1, 0),
659         SOC_SINGLE("ALC Anticlip Mode Switch", DA9055_ALC_ANTICLIP_CTRL,
660                    7, 1, 0),
661         SOC_SINGLE("ALC Anticlip Level", DA9055_ALC_ANTICLIP_LEVEL,
662                    0, 0x7f, 0),
663         SOC_SINGLE_TLV("ALC Min Threshold Volume", DA9055_ALC_TARGET_MIN,
664                        0, 0x3f, 1, alc_threshold_tlv),
665         SOC_SINGLE_TLV("ALC Max Threshold Volume", DA9055_ALC_TARGET_MAX,
666                        0, 0x3f, 1, alc_threshold_tlv),
667         SOC_SINGLE_TLV("ALC Noise Threshold Volume", DA9055_ALC_NOISE,
668                        0, 0x3f, 1, alc_threshold_tlv),
669         SOC_SINGLE_TLV("ALC Max Gain Volume", DA9055_ALC_GAIN_LIMITS,
670                        4, 0xf, 0, alc_gain_tlv),
671         SOC_SINGLE_TLV("ALC Max Attenuation Volume", DA9055_ALC_GAIN_LIMITS,
672                        0, 0xf, 0, alc_gain_tlv),
673         SOC_SINGLE_TLV("ALC Min Analog Gain Volume",
674                        DA9055_ALC_ANA_GAIN_LIMITS,
675                        0, 0x7, 0, alc_analog_gain_tlv),
676         SOC_SINGLE_TLV("ALC Max Analog Gain Volume",
677                        DA9055_ALC_ANA_GAIN_LIMITS,
678                        4, 0x7, 0, alc_analog_gain_tlv),
679         SOC_ENUM("ALC Attack Rate", da9055_attack_rate),
680         SOC_ENUM("ALC Release Rate", da9055_release_rate),
681         SOC_ENUM("ALC Hold Time", da9055_hold_time),
682         /*
683          * Rate at which input signal envelope is tracked as the signal gets
684          * larger
685          */
686         SOC_ENUM("ALC Integ Attack Rate", da9055_integ_attack_rate),
687         /*
688          * Rate at which input signal envelope is tracked as the signal gets
689          * smaller
690          */
691         SOC_ENUM("ALC Integ Release Rate", da9055_integ_release_rate),
692 };
693 
694 /* DAPM Controls */
695 
696 /* Mic PGA Left Source */
697 static const struct snd_kcontrol_new da9055_mic_l_mux_controls =
698 SOC_DAPM_ENUM("Route", da9055_mic_l_src);
699 
700 /* Mic PGA Right Source */
701 static const struct snd_kcontrol_new da9055_mic_r_mux_controls =
702 SOC_DAPM_ENUM("Route", da9055_mic_r_src);
703 
704 /* In Mixer Left */
705 static const struct snd_kcontrol_new da9055_dapm_mixinl_controls[] = {
706         SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXIN_L_SELECT, 0, 1, 0),
707         SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_L_SELECT, 1, 1, 0),
708         SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_L_SELECT, 2, 1, 0),
709 };
710 
711 /* In Mixer Right */
712 static const struct snd_kcontrol_new da9055_dapm_mixinr_controls[] = {
713         SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXIN_R_SELECT, 0, 1, 0),
714         SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_R_SELECT, 1, 1, 0),
715         SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_R_SELECT, 2, 1, 0),
716         SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXIN_R_SELECT, 3, 1, 0),
717 };
718 
719 /* DAC Left Source */
720 static const struct snd_kcontrol_new da9055_dac_l_mux_controls =
721 SOC_DAPM_ENUM("Route", da9055_dac_l_src);
722 
723 /* DAC Right Source */
724 static const struct snd_kcontrol_new da9055_dac_r_mux_controls =
725 SOC_DAPM_ENUM("Route", da9055_dac_r_src);
726 
727 /* Out Mixer Left */
728 static const struct snd_kcontrol_new da9055_dapm_mixoutl_controls[] = {
729         SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXOUT_L_SELECT, 0, 1, 0),
730         SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_L_SELECT, 1, 1, 0),
731         SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_L_SELECT, 2, 1, 0),
732         SOC_DAPM_SINGLE("DAC Left Switch", DA9055_MIXOUT_L_SELECT, 3, 1, 0),
733         SOC_DAPM_SINGLE("Aux Left Invert Switch", DA9055_MIXOUT_L_SELECT,
734                         4, 1, 0),
735         SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_L_SELECT,
736                         5, 1, 0),
737         SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_L_SELECT,
738                         6, 1, 0),
739 };
740 
741 /* Out Mixer Right */
742 static const struct snd_kcontrol_new da9055_dapm_mixoutr_controls[] = {
743         SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXOUT_R_SELECT, 0, 1, 0),
744         SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_R_SELECT, 1, 1, 0),
745         SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_R_SELECT, 2, 1, 0),
746         SOC_DAPM_SINGLE("DAC Right Switch", DA9055_MIXOUT_R_SELECT, 3, 1, 0),
747         SOC_DAPM_SINGLE("Aux Right Invert Switch", DA9055_MIXOUT_R_SELECT,
748                         4, 1, 0),
749         SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_R_SELECT,
750                         5, 1, 0),
751         SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_R_SELECT,
752                         6, 1, 0),
753 };
754 
755 /* Headphone Output Enable */
756 static const struct snd_kcontrol_new da9055_dapm_hp_l_control =
757 SOC_DAPM_SINGLE("Switch", DA9055_HP_L_CTRL, 3, 1, 0);
758 
759 static const struct snd_kcontrol_new da9055_dapm_hp_r_control =
760 SOC_DAPM_SINGLE("Switch", DA9055_HP_R_CTRL, 3, 1, 0);
761 
762 /* Lineout Output Enable */
763 static const struct snd_kcontrol_new da9055_dapm_lineout_control =
764 SOC_DAPM_SINGLE("Switch", DA9055_LINE_CTRL, 3, 1, 0);
765 
766 /* DAPM widgets */
767 static const struct snd_soc_dapm_widget da9055_dapm_widgets[] = {
768         /* Input Side */
769 
770         /* Input Lines */
771         SND_SOC_DAPM_INPUT("MIC1"),
772         SND_SOC_DAPM_INPUT("MIC2"),
773         SND_SOC_DAPM_INPUT("AUXL"),
774         SND_SOC_DAPM_INPUT("AUXR"),
775 
776         /* MUXs for Mic PGA source selection */
777         SND_SOC_DAPM_MUX("Mic Left Source", SND_SOC_NOPM, 0, 0,
778                          &da9055_mic_l_mux_controls),
779         SND_SOC_DAPM_MUX("Mic Right Source", SND_SOC_NOPM, 0, 0,
780                          &da9055_mic_r_mux_controls),
781 
782         /* Input PGAs */
783         SND_SOC_DAPM_PGA("Mic Left", DA9055_MIC_L_CTRL, 7, 0, NULL, 0),
784         SND_SOC_DAPM_PGA("Mic Right", DA9055_MIC_R_CTRL, 7, 0, NULL, 0),
785         SND_SOC_DAPM_PGA("Aux Left", DA9055_AUX_L_CTRL, 7, 0, NULL, 0),
786         SND_SOC_DAPM_PGA("Aux Right", DA9055_AUX_R_CTRL, 7, 0, NULL, 0),
787         SND_SOC_DAPM_PGA("MIXIN Left", DA9055_MIXIN_L_CTRL, 7, 0, NULL, 0),
788         SND_SOC_DAPM_PGA("MIXIN Right", DA9055_MIXIN_R_CTRL, 7, 0, NULL, 0),
789 
790         SND_SOC_DAPM_SUPPLY("Mic Bias", DA9055_MIC_BIAS_CTRL, 7, 0, NULL, 0),
791         SND_SOC_DAPM_SUPPLY("AIF", DA9055_AIF_CTRL, 7, 0, NULL, 0),
792         SND_SOC_DAPM_SUPPLY("Charge Pump", DA9055_CP_CTRL, 7, 0, NULL, 0),
793 
794         /* Input Mixers */
795         SND_SOC_DAPM_MIXER("In Mixer Left", SND_SOC_NOPM, 0, 0,
796                            &da9055_dapm_mixinl_controls[0],
797                            ARRAY_SIZE(da9055_dapm_mixinl_controls)),
798         SND_SOC_DAPM_MIXER("In Mixer Right", SND_SOC_NOPM, 0, 0,
799                            &da9055_dapm_mixinr_controls[0],
800                            ARRAY_SIZE(da9055_dapm_mixinr_controls)),
801 
802         /* ADCs */
803         SND_SOC_DAPM_ADC("ADC Left", "Capture", DA9055_ADC_L_CTRL, 7, 0),
804         SND_SOC_DAPM_ADC("ADC Right", "Capture", DA9055_ADC_R_CTRL, 7, 0),
805 
806         /* Output Side */
807 
808         /* MUXs for DAC source selection */
809         SND_SOC_DAPM_MUX("DAC Left Source", SND_SOC_NOPM, 0, 0,
810                          &da9055_dac_l_mux_controls),
811         SND_SOC_DAPM_MUX("DAC Right Source", SND_SOC_NOPM, 0, 0,
812                          &da9055_dac_r_mux_controls),
813 
814         /* AIF input */
815         SND_SOC_DAPM_AIF_IN("AIFIN Left", "Playback", 0, SND_SOC_NOPM, 0, 0),
816         SND_SOC_DAPM_AIF_IN("AIFIN Right", "Playback", 0, SND_SOC_NOPM, 0, 0),
817 
818         /* DACs */
819         SND_SOC_DAPM_DAC("DAC Left", "Playback", DA9055_DAC_L_CTRL, 7, 0),
820         SND_SOC_DAPM_DAC("DAC Right", "Playback", DA9055_DAC_R_CTRL, 7, 0),
821 
822         /* Output Mixers */
823         SND_SOC_DAPM_MIXER("Out Mixer Left", SND_SOC_NOPM, 0, 0,
824                            &da9055_dapm_mixoutl_controls[0],
825                            ARRAY_SIZE(da9055_dapm_mixoutl_controls)),
826         SND_SOC_DAPM_MIXER("Out Mixer Right", SND_SOC_NOPM, 0, 0,
827                            &da9055_dapm_mixoutr_controls[0],
828                            ARRAY_SIZE(da9055_dapm_mixoutr_controls)),
829 
830         /* Output Enable Switches */
831         SND_SOC_DAPM_SWITCH("Headphone Left Enable", SND_SOC_NOPM, 0, 0,
832                             &da9055_dapm_hp_l_control),
833         SND_SOC_DAPM_SWITCH("Headphone Right Enable", SND_SOC_NOPM, 0, 0,
834                             &da9055_dapm_hp_r_control),
835         SND_SOC_DAPM_SWITCH("Lineout Enable", SND_SOC_NOPM, 0, 0,
836                             &da9055_dapm_lineout_control),
837 
838         /* Output PGAs */
839         SND_SOC_DAPM_PGA("MIXOUT Left", DA9055_MIXOUT_L_CTRL, 7, 0, NULL, 0),
840         SND_SOC_DAPM_PGA("MIXOUT Right", DA9055_MIXOUT_R_CTRL, 7, 0, NULL, 0),
841         SND_SOC_DAPM_PGA("Lineout", DA9055_LINE_CTRL, 7, 0, NULL, 0),
842         SND_SOC_DAPM_PGA("Headphone Left", DA9055_HP_L_CTRL, 7, 0, NULL, 0),
843         SND_SOC_DAPM_PGA("Headphone Right", DA9055_HP_R_CTRL, 7, 0, NULL, 0),
844 
845         /* Output Lines */
846         SND_SOC_DAPM_OUTPUT("HPL"),
847         SND_SOC_DAPM_OUTPUT("HPR"),
848         SND_SOC_DAPM_OUTPUT("LINE"),
849 };
850 
851 /* DAPM audio route definition */
852 static const struct snd_soc_dapm_route da9055_audio_map[] = {
853         /* Dest       Connecting Widget    source */
854 
855         /* Input path */
856         {"Mic Left Source", "MIC1_P_N", "MIC1"},
857         {"Mic Left Source", "MIC1_P", "MIC1"},
858         {"Mic Left Source", "MIC1_N", "MIC1"},
859         {"Mic Left Source", "MIC2_L", "MIC2"},
860 
861         {"Mic Right Source", "MIC2_R_L", "MIC2"},
862         {"Mic Right Source", "MIC2_R", "MIC2"},
863         {"Mic Right Source", "MIC2_L", "MIC2"},
864 
865         {"Mic Left", NULL, "Mic Left Source"},
866         {"Mic Right", NULL, "Mic Right Source"},
867 
868         {"Aux Left", NULL, "AUXL"},
869         {"Aux Right", NULL, "AUXR"},
870 
871         {"In Mixer Left", "Mic Left Switch", "Mic Left"},
872         {"In Mixer Left", "Mic Right Switch", "Mic Right"},
873         {"In Mixer Left", "Aux Left Switch", "Aux Left"},
874 
875         {"In Mixer Right", "Mic Right Switch", "Mic Right"},
876         {"In Mixer Right", "Mic Left Switch", "Mic Left"},
877         {"In Mixer Right", "Aux Right Switch", "Aux Right"},
878         {"In Mixer Right", "Mixin Left Switch", "MIXIN Left"},
879 
880         {"MIXIN Left", NULL, "In Mixer Left"},
881         {"ADC Left", NULL, "MIXIN Left"},
882 
883         {"MIXIN Right", NULL, "In Mixer Right"},
884         {"ADC Right", NULL, "MIXIN Right"},
885 
886         {"ADC Left", NULL, "AIF"},
887         {"ADC Right", NULL, "AIF"},
888 
889         /* Output path */
890         {"AIFIN Left", NULL, "AIF"},
891         {"AIFIN Right", NULL, "AIF"},
892 
893         {"DAC Left Source", "ADC output left", "ADC Left"},
894         {"DAC Left Source", "ADC output right", "ADC Right"},
895         {"DAC Left Source", "AIF input left", "AIFIN Left"},
896         {"DAC Left Source", "AIF input right", "AIFIN Right"},
897 
898         {"DAC Right Source", "ADC output left", "ADC Left"},
899         {"DAC Right Source", "ADC output right", "ADC Right"},
900         {"DAC Right Source", "AIF input left", "AIFIN Left"},
901         {"DAC Right Source", "AIF input right", "AIFIN Right"},
902 
903         {"DAC Left", NULL, "DAC Left Source"},
904         {"DAC Right", NULL, "DAC Right Source"},
905 
906         {"Out Mixer Left", "Aux Left Switch", "Aux Left"},
907         {"Out Mixer Left", "Mixin Left Switch", "MIXIN Left"},
908         {"Out Mixer Left", "Mixin Right Switch", "MIXIN Right"},
909         {"Out Mixer Left", "Aux Left Invert Switch", "Aux Left"},
910         {"Out Mixer Left", "Mixin Left Invert Switch", "MIXIN Left"},
911         {"Out Mixer Left", "Mixin Right Invert Switch", "MIXIN Right"},
912         {"Out Mixer Left", "DAC Left Switch", "DAC Left"},
913 
914         {"Out Mixer Right", "Aux Right Switch", "Aux Right"},
915         {"Out Mixer Right", "Mixin Right Switch", "MIXIN Right"},
916         {"Out Mixer Right", "Mixin Left Switch", "MIXIN Left"},
917         {"Out Mixer Right", "Aux Right Invert Switch", "Aux Right"},
918         {"Out Mixer Right", "Mixin Right Invert Switch", "MIXIN Right"},
919         {"Out Mixer Right", "Mixin Left Invert Switch", "MIXIN Left"},
920         {"Out Mixer Right", "DAC Right Switch", "DAC Right"},
921 
922         {"MIXOUT Left", NULL, "Out Mixer Left"},
923         {"Headphone Left Enable", "Switch", "MIXOUT Left"},
924         {"Headphone Left", NULL, "Headphone Left Enable"},
925         {"Headphone Left", NULL, "Charge Pump"},
926         {"HPL", NULL, "Headphone Left"},
927 
928         {"MIXOUT Right", NULL, "Out Mixer Right"},
929         {"Headphone Right Enable", "Switch", "MIXOUT Right"},
930         {"Headphone Right", NULL, "Headphone Right Enable"},
931         {"Headphone Right", NULL, "Charge Pump"},
932         {"HPR", NULL, "Headphone Right"},
933 
934         {"MIXOUT Right", NULL, "Out Mixer Right"},
935         {"Lineout Enable", "Switch", "MIXOUT Right"},
936         {"Lineout", NULL, "Lineout Enable"},
937         {"LINE", NULL, "Lineout"},
938 };
939 
940 /* Codec private data */
941 struct da9055_priv {
942         struct regmap *regmap;
943         unsigned int mclk_rate;
944         int master;
945         struct da9055_platform_data *pdata;
946 };
947 
948 static const struct reg_default da9055_reg_defaults[] = {
949         { 0x21, 0x10 },
950         { 0x22, 0x0A },
951         { 0x23, 0x00 },
952         { 0x24, 0x00 },
953         { 0x25, 0x00 },
954         { 0x26, 0x00 },
955         { 0x27, 0x0C },
956         { 0x28, 0x01 },
957         { 0x29, 0x08 },
958         { 0x2A, 0x32 },
959         { 0x2B, 0x00 },
960         { 0x30, 0x35 },
961         { 0x31, 0x35 },
962         { 0x32, 0x00 },
963         { 0x33, 0x00 },
964         { 0x34, 0x03 },
965         { 0x35, 0x03 },
966         { 0x36, 0x6F },
967         { 0x37, 0x6F },
968         { 0x38, 0x80 },
969         { 0x39, 0x01 },
970         { 0x3A, 0x01 },
971         { 0x40, 0x00 },
972         { 0x41, 0x88 },
973         { 0x42, 0x88 },
974         { 0x43, 0x08 },
975         { 0x44, 0x80 },
976         { 0x45, 0x6F },
977         { 0x46, 0x6F },
978         { 0x47, 0x61 },
979         { 0x48, 0x35 },
980         { 0x49, 0x35 },
981         { 0x4A, 0x35 },
982         { 0x4B, 0x00 },
983         { 0x4C, 0x00 },
984         { 0x60, 0x44 },
985         { 0x61, 0x44 },
986         { 0x62, 0x00 },
987         { 0x63, 0x40 },
988         { 0x64, 0x40 },
989         { 0x65, 0x40 },
990         { 0x66, 0x40 },
991         { 0x67, 0x40 },
992         { 0x68, 0x40 },
993         { 0x69, 0x48 },
994         { 0x6A, 0x40 },
995         { 0x6B, 0x41 },
996         { 0x6C, 0x40 },
997         { 0x6D, 0x40 },
998         { 0x6E, 0x10 },
999         { 0x6F, 0x10 },
1000         { 0x90, 0x80 },
1001         { 0x92, 0x02 },
1002         { 0x93, 0x00 },
1003         { 0x99, 0x00 },
1004         { 0x9A, 0x00 },
1005         { 0x9B, 0x00 },
1006         { 0x9C, 0x3F },
1007         { 0x9D, 0x00 },
1008         { 0x9E, 0x3F },
1009         { 0x9F, 0xFF },
1010         { 0xA0, 0x71 },
1011         { 0xA1, 0x00 },
1012         { 0xA2, 0x00 },
1013         { 0xA6, 0x00 },
1014         { 0xA7, 0x00 },
1015         { 0xAB, 0x00 },
1016         { 0xAC, 0x00 },
1017         { 0xAD, 0x00 },
1018         { 0xAF, 0x08 },
1019         { 0xB0, 0x00 },
1020         { 0xB1, 0x00 },
1021         { 0xB2, 0x00 },
1022 };
1023 
1024 static bool da9055_volatile_register(struct device *dev,
1025                                      unsigned int reg)
1026 {
1027         switch (reg) {
1028         case DA9055_STATUS1:
1029         case DA9055_PLL_STATUS:
1030         case DA9055_AUX_L_GAIN_STATUS:
1031         case DA9055_AUX_R_GAIN_STATUS:
1032         case DA9055_MIC_L_GAIN_STATUS:
1033         case DA9055_MIC_R_GAIN_STATUS:
1034         case DA9055_MIXIN_L_GAIN_STATUS:
1035         case DA9055_MIXIN_R_GAIN_STATUS:
1036         case DA9055_ADC_L_GAIN_STATUS:
1037         case DA9055_ADC_R_GAIN_STATUS:
1038         case DA9055_DAC_L_GAIN_STATUS:
1039         case DA9055_DAC_R_GAIN_STATUS:
1040         case DA9055_HP_L_GAIN_STATUS:
1041         case DA9055_HP_R_GAIN_STATUS:
1042         case DA9055_LINE_GAIN_STATUS:
1043         case DA9055_ALC_CIC_OP_LVL_DATA:
1044                 return 1;
1045         default:
1046                 return 0;
1047         }
1048 }
1049 
1050 /* Set DAI word length */
1051 static int da9055_hw_params(struct snd_pcm_substream *substream,
1052                             struct snd_pcm_hw_params *params,
1053                             struct snd_soc_dai *dai)
1054 {
1055         struct snd_soc_codec *codec = dai->codec;
1056         struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1057         u8 aif_ctrl, fs;
1058         u32 sysclk;
1059 
1060         switch (params_width(params)) {
1061         case 16:
1062                 aif_ctrl = DA9055_AIF_WORD_S16_LE;
1063                 break;
1064         case 20:
1065                 aif_ctrl = DA9055_AIF_WORD_S20_3LE;
1066                 break;
1067         case 24:
1068                 aif_ctrl = DA9055_AIF_WORD_S24_LE;
1069                 break;
1070         case 32:
1071                 aif_ctrl = DA9055_AIF_WORD_S32_LE;
1072                 break;
1073         default:
1074                 return -EINVAL;
1075         }
1076 
1077         /* Set AIF format */
1078         snd_soc_update_bits(codec, DA9055_AIF_CTRL, DA9055_AIF_WORD_LENGTH_MASK,
1079                             aif_ctrl);
1080 
1081         switch (params_rate(params)) {
1082         case 8000:
1083                 fs              = DA9055_SR_8000;
1084                 sysclk          = 3072000;
1085                 break;
1086         case 11025:
1087                 fs              = DA9055_SR_11025;
1088                 sysclk          = 2822400;
1089                 break;
1090         case 12000:
1091                 fs              = DA9055_SR_12000;
1092                 sysclk          = 3072000;
1093                 break;
1094         case 16000:
1095                 fs              = DA9055_SR_16000;
1096                 sysclk          = 3072000;
1097                 break;
1098         case 22050:
1099                 fs              = DA9055_SR_22050;
1100                 sysclk          = 2822400;
1101                 break;
1102         case 32000:
1103                 fs              = DA9055_SR_32000;
1104                 sysclk          = 3072000;
1105                 break;
1106         case 44100:
1107                 fs              = DA9055_SR_44100;
1108                 sysclk          = 2822400;
1109                 break;
1110         case 48000:
1111                 fs              = DA9055_SR_48000;
1112                 sysclk          = 3072000;
1113                 break;
1114         case 88200:
1115                 fs              = DA9055_SR_88200;
1116                 sysclk          = 2822400;
1117                 break;
1118         case 96000:
1119                 fs              = DA9055_SR_96000;
1120                 sysclk          = 3072000;
1121                 break;
1122         default:
1123                 return -EINVAL;
1124         }
1125 
1126         if (da9055->mclk_rate) {
1127                 /* PLL Mode, Write actual FS */
1128                 snd_soc_write(codec, DA9055_SR, fs);
1129         } else {
1130                 /*
1131                  * Non-PLL Mode
1132                  * When PLL is bypassed, chip assumes constant MCLK of
1133                  * 12.288MHz and uses sample rate value to divide this MCLK
1134                  * to derive its sys clk. As sys clk has to be 256 * Fs, we
1135                  * need to write constant sample rate i.e. 48KHz.
1136                  */
1137                 snd_soc_write(codec, DA9055_SR, DA9055_SR_48000);
1138         }
1139 
1140         if (da9055->mclk_rate && (da9055->mclk_rate != sysclk)) {
1141                 /* PLL Mode */
1142                 if (!da9055->master) {
1143                         /* PLL slave mode, enable PLL and also SRM */
1144                         snd_soc_update_bits(codec, DA9055_PLL_CTRL,
1145                                             DA9055_PLL_EN | DA9055_PLL_SRM_EN,
1146                                             DA9055_PLL_EN | DA9055_PLL_SRM_EN);
1147                 } else {
1148                         /* PLL master mode, only enable PLL */
1149                         snd_soc_update_bits(codec, DA9055_PLL_CTRL,
1150                                             DA9055_PLL_EN, DA9055_PLL_EN);
1151                 }
1152         } else {
1153                 /* Non PLL Mode, disable PLL */
1154                 snd_soc_update_bits(codec, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
1155         }
1156 
1157         return 0;
1158 }
1159 
1160 /* Set DAI mode and Format */
1161 static int da9055_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1162 {
1163         struct snd_soc_codec *codec = codec_dai->codec;
1164         struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1165         u8 aif_clk_mode, aif_ctrl, mode;
1166 
1167         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1168         case SND_SOC_DAIFMT_CBM_CFM:
1169                 /* DA9055 in I2S Master Mode */
1170                 mode = 1;
1171                 aif_clk_mode = DA9055_AIF_CLK_EN_MASTER_MODE;
1172                 break;
1173         case SND_SOC_DAIFMT_CBS_CFS:
1174                 /* DA9055 in I2S Slave Mode */
1175                 mode = 0;
1176                 aif_clk_mode = DA9055_AIF_CLK_EN_SLAVE_MODE;
1177                 break;
1178         default:
1179                 return -EINVAL;
1180         }
1181 
1182         /* Don't allow change of mode if PLL is enabled */
1183         if ((snd_soc_read(codec, DA9055_PLL_CTRL) & DA9055_PLL_EN) &&
1184             (da9055->master != mode))
1185                 return -EINVAL;
1186 
1187         da9055->master = mode;
1188 
1189         /* Only I2S is supported */
1190         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1191         case SND_SOC_DAIFMT_I2S:
1192                 aif_ctrl = DA9055_AIF_FORMAT_I2S_MODE;
1193                 break;
1194         case SND_SOC_DAIFMT_LEFT_J:
1195                 aif_ctrl = DA9055_AIF_FORMAT_LEFT_J;
1196                 break;
1197         case SND_SOC_DAIFMT_RIGHT_J:
1198                 aif_ctrl = DA9055_AIF_FORMAT_RIGHT_J;
1199                 break;
1200         case SND_SOC_DAIFMT_DSP_A:
1201                 aif_ctrl = DA9055_AIF_FORMAT_DSP;
1202                 break;
1203         default:
1204                 return -EINVAL;
1205         }
1206 
1207         /* By default only 32 BCLK per WCLK is supported */
1208         aif_clk_mode |= DA9055_AIF_BCLKS_PER_WCLK_32;
1209 
1210         snd_soc_update_bits(codec, DA9055_AIF_CLK_MODE,
1211                             (DA9055_AIF_CLK_MODE_MASK | DA9055_AIF_BCLK_MASK),
1212                             aif_clk_mode);
1213         snd_soc_update_bits(codec, DA9055_AIF_CTRL, DA9055_AIF_FORMAT_MASK,
1214                             aif_ctrl);
1215         return 0;
1216 }
1217 
1218 static int da9055_mute(struct snd_soc_dai *dai, int mute)
1219 {
1220         struct snd_soc_codec *codec = dai->codec;
1221 
1222         if (mute) {
1223                 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL,
1224                                     DA9055_DAC_L_MUTE_EN, DA9055_DAC_L_MUTE_EN);
1225                 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL,
1226                                     DA9055_DAC_R_MUTE_EN, DA9055_DAC_R_MUTE_EN);
1227         } else {
1228                 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL,
1229                                     DA9055_DAC_L_MUTE_EN, 0);
1230                 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL,
1231                                     DA9055_DAC_R_MUTE_EN, 0);
1232         }
1233 
1234         return 0;
1235 }
1236 
1237 #define DA9055_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1238                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1239 
1240 static int da9055_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1241                                  int clk_id, unsigned int freq, int dir)
1242 {
1243         struct snd_soc_codec *codec = codec_dai->codec;
1244         struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1245 
1246         switch (clk_id) {
1247         case DA9055_CLKSRC_MCLK:
1248                 switch (freq) {
1249                 case 11289600:
1250                 case 12000000:
1251                 case 12288000:
1252                 case 13000000:
1253                 case 13500000:
1254                 case 14400000:
1255                 case 19200000:
1256                 case 19680000:
1257                 case 19800000:
1258                         da9055->mclk_rate = freq;
1259                         return 0;
1260                 default:
1261                         dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
1262                                 freq);
1263                         return -EINVAL;
1264                 }
1265                 break;
1266         default:
1267                 dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
1268                 return -EINVAL;
1269         }
1270 }
1271 
1272 /*
1273  * da9055_set_dai_pll   : Configure the codec PLL
1274  * @param codec_dai     : Pointer to codec DAI
1275  * @param pll_id        : da9055 has only one pll, so pll_id is always zero
1276  * @param fref          : Input MCLK frequency
1277  * @param fout          : FsDM value
1278  * @return int          : Zero for success, negative error code for error
1279  *
1280  * Note: Supported PLL input frequencies are 11.2896MHz, 12MHz, 12.288MHz,
1281  *       13MHz, 13.5MHz, 14.4MHz, 19.2MHz, 19.6MHz and 19.8MHz
1282  */
1283 static int da9055_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1284                               int source, unsigned int fref, unsigned int fout)
1285 {
1286         struct snd_soc_codec *codec = codec_dai->codec;
1287         struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1288 
1289         u8 pll_frac_top, pll_frac_bot, pll_integer, cnt;
1290 
1291         /* Disable PLL before setting the divisors */
1292         snd_soc_update_bits(codec, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
1293 
1294         /* In slave mode, there is only one set of divisors */
1295         if (!da9055->master && (fout != 2822400))
1296                 goto pll_err;
1297 
1298         /* Search pll div array for correct divisors */
1299         for (cnt = 0; cnt < ARRAY_SIZE(da9055_pll_div); cnt++) {
1300                 /* Check fref, mode  and fout */
1301                 if ((fref == da9055_pll_div[cnt].fref) &&
1302                     (da9055->master ==  da9055_pll_div[cnt].mode) &&
1303                     (fout == da9055_pll_div[cnt].fout)) {
1304                         /* All match, pick up divisors */
1305                         pll_frac_top = da9055_pll_div[cnt].frac_top;
1306                         pll_frac_bot = da9055_pll_div[cnt].frac_bot;
1307                         pll_integer = da9055_pll_div[cnt].integer;
1308                         break;
1309                 }
1310         }
1311         if (cnt >= ARRAY_SIZE(da9055_pll_div))
1312                 goto pll_err;
1313 
1314         /* Write PLL dividers */
1315         snd_soc_write(codec, DA9055_PLL_FRAC_TOP, pll_frac_top);
1316         snd_soc_write(codec, DA9055_PLL_FRAC_BOT, pll_frac_bot);
1317         snd_soc_write(codec, DA9055_PLL_INTEGER, pll_integer);
1318 
1319         return 0;
1320 pll_err:
1321         dev_err(codec_dai->dev, "Error in setting up PLL\n");
1322         return -EINVAL;
1323 }
1324 
1325 /* DAI operations */
1326 static const struct snd_soc_dai_ops da9055_dai_ops = {
1327         .hw_params      = da9055_hw_params,
1328         .set_fmt        = da9055_set_dai_fmt,
1329         .set_sysclk     = da9055_set_dai_sysclk,
1330         .set_pll        = da9055_set_dai_pll,
1331         .digital_mute   = da9055_mute,
1332 };
1333 
1334 static struct snd_soc_dai_driver da9055_dai = {
1335         .name = "da9055-hifi",
1336         /* Playback Capabilities */
1337         .playback = {
1338                 .stream_name = "Playback",
1339                 .channels_min = 1,
1340                 .channels_max = 2,
1341                 .rates = SNDRV_PCM_RATE_8000_96000,
1342                 .formats = DA9055_FORMATS,
1343         },
1344         /* Capture Capabilities */
1345         .capture = {
1346                 .stream_name = "Capture",
1347                 .channels_min = 1,
1348                 .channels_max = 2,
1349                 .rates = SNDRV_PCM_RATE_8000_96000,
1350                 .formats = DA9055_FORMATS,
1351         },
1352         .ops = &da9055_dai_ops,
1353         .symmetric_rates = 1,
1354 };
1355 
1356 static int da9055_set_bias_level(struct snd_soc_codec *codec,
1357                                  enum snd_soc_bias_level level)
1358 {
1359         switch (level) {
1360         case SND_SOC_BIAS_ON:
1361         case SND_SOC_BIAS_PREPARE:
1362                 break;
1363         case SND_SOC_BIAS_STANDBY:
1364                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1365                         /* Enable VMID reference & master bias */
1366                         snd_soc_update_bits(codec, DA9055_REFERENCES,
1367                                             DA9055_VMID_EN | DA9055_BIAS_EN,
1368                                             DA9055_VMID_EN | DA9055_BIAS_EN);
1369                 }
1370                 break;
1371         case SND_SOC_BIAS_OFF:
1372                 /* Disable VMID reference & master bias */
1373                 snd_soc_update_bits(codec, DA9055_REFERENCES,
1374                                     DA9055_VMID_EN | DA9055_BIAS_EN, 0);
1375                 break;
1376         }
1377         return 0;
1378 }
1379 
1380 static int da9055_probe(struct snd_soc_codec *codec)
1381 {
1382         struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec);
1383 
1384         /* Enable all Gain Ramps */
1385         snd_soc_update_bits(codec, DA9055_AUX_L_CTRL,
1386                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1387         snd_soc_update_bits(codec, DA9055_AUX_R_CTRL,
1388                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1389         snd_soc_update_bits(codec, DA9055_MIXIN_L_CTRL,
1390                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1391         snd_soc_update_bits(codec, DA9055_MIXIN_R_CTRL,
1392                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1393         snd_soc_update_bits(codec, DA9055_ADC_L_CTRL,
1394                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1395         snd_soc_update_bits(codec, DA9055_ADC_R_CTRL,
1396                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1397         snd_soc_update_bits(codec, DA9055_DAC_L_CTRL,
1398                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1399         snd_soc_update_bits(codec, DA9055_DAC_R_CTRL,
1400                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1401         snd_soc_update_bits(codec, DA9055_HP_L_CTRL,
1402                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1403         snd_soc_update_bits(codec, DA9055_HP_R_CTRL,
1404                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1405         snd_soc_update_bits(codec, DA9055_LINE_CTRL,
1406                             DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
1407 
1408         /*
1409          * There are two separate control bits for input and output mixers.
1410          * One to enable corresponding amplifier and other to enable its
1411          * output. As amplifier bits are related to power control, they are
1412          * being managed by DAPM while other (non power related) bits are
1413          * enabled here
1414          */
1415         snd_soc_update_bits(codec, DA9055_MIXIN_L_CTRL,
1416                             DA9055_MIXIN_L_MIX_EN, DA9055_MIXIN_L_MIX_EN);
1417         snd_soc_update_bits(codec, DA9055_MIXIN_R_CTRL,
1418                             DA9055_MIXIN_R_MIX_EN, DA9055_MIXIN_R_MIX_EN);
1419 
1420         snd_soc_update_bits(codec, DA9055_MIXOUT_L_CTRL,
1421                             DA9055_MIXOUT_L_MIX_EN, DA9055_MIXOUT_L_MIX_EN);
1422         snd_soc_update_bits(codec, DA9055_MIXOUT_R_CTRL,
1423                             DA9055_MIXOUT_R_MIX_EN, DA9055_MIXOUT_R_MIX_EN);
1424 
1425         /* Set this as per your system configuration */
1426         snd_soc_write(codec, DA9055_PLL_CTRL, DA9055_PLL_INDIV_10_20_MHZ);
1427 
1428         /* Set platform data values */
1429         if (da9055->pdata) {
1430                 /* set mic bias source */
1431                 if (da9055->pdata->micbias_source) {
1432                         snd_soc_update_bits(codec, DA9055_MIXIN_R_SELECT,
1433                                             DA9055_MICBIAS2_EN,
1434                                             DA9055_MICBIAS2_EN);
1435                 } else {
1436                         snd_soc_update_bits(codec, DA9055_MIXIN_R_SELECT,
1437                                             DA9055_MICBIAS2_EN, 0);
1438                 }
1439                 /* set mic bias voltage */
1440                 switch (da9055->pdata->micbias) {
1441                 case DA9055_MICBIAS_2_2V:
1442                 case DA9055_MICBIAS_2_1V:
1443                 case DA9055_MICBIAS_1_8V:
1444                 case DA9055_MICBIAS_1_6V:
1445                         snd_soc_update_bits(codec, DA9055_MIC_CONFIG,
1446                                             DA9055_MICBIAS_LEVEL_MASK,
1447                                             (da9055->pdata->micbias) << 4);
1448                         break;
1449                 }
1450         }
1451         return 0;
1452 }
1453 
1454 static struct snd_soc_codec_driver soc_codec_dev_da9055 = {
1455         .probe                  = da9055_probe,
1456         .set_bias_level         = da9055_set_bias_level,
1457 
1458         .controls               = da9055_snd_controls,
1459         .num_controls           = ARRAY_SIZE(da9055_snd_controls),
1460 
1461         .dapm_widgets           = da9055_dapm_widgets,
1462         .num_dapm_widgets       = ARRAY_SIZE(da9055_dapm_widgets),
1463         .dapm_routes            = da9055_audio_map,
1464         .num_dapm_routes        = ARRAY_SIZE(da9055_audio_map),
1465 };
1466 
1467 static const struct regmap_config da9055_regmap_config = {
1468         .reg_bits = 8,
1469         .val_bits = 8,
1470 
1471         .reg_defaults = da9055_reg_defaults,
1472         .num_reg_defaults = ARRAY_SIZE(da9055_reg_defaults),
1473         .volatile_reg = da9055_volatile_register,
1474         .cache_type = REGCACHE_RBTREE,
1475 };
1476 
1477 static int da9055_i2c_probe(struct i2c_client *i2c,
1478                             const struct i2c_device_id *id)
1479 {
1480         struct da9055_priv *da9055;
1481         struct da9055_platform_data *pdata = dev_get_platdata(&i2c->dev);
1482         int ret;
1483 
1484         da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055_priv),
1485                               GFP_KERNEL);
1486         if (!da9055)
1487                 return -ENOMEM;
1488 
1489         if (pdata)
1490                 da9055->pdata = pdata;
1491 
1492         i2c_set_clientdata(i2c, da9055);
1493 
1494         da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config);
1495         if (IS_ERR(da9055->regmap)) {
1496                 ret = PTR_ERR(da9055->regmap);
1497                 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1498                 return ret;
1499         }
1500 
1501         ret = snd_soc_register_codec(&i2c->dev,
1502                         &soc_codec_dev_da9055, &da9055_dai, 1);
1503         if (ret < 0) {
1504                 dev_err(&i2c->dev, "Failed to register da9055 codec: %d\n",
1505                         ret);
1506         }
1507         return ret;
1508 }
1509 
1510 static int da9055_remove(struct i2c_client *client)
1511 {
1512         snd_soc_unregister_codec(&client->dev);
1513         return 0;
1514 }
1515 
1516 /*
1517  * DO NOT change the device Ids. The naming is intentionally specific as both
1518  * the CODEC and PMIC parts of this chip are instantiated separately as I2C
1519  * devices (both have configurable I2C addresses, and are to all intents and
1520  * purposes separate). As a result there are specific DA9055 Ids for CODEC
1521  * and PMIC, which must be different to operate together.
1522  */
1523 static const struct i2c_device_id da9055_i2c_id[] = {
1524         { "da9055-codec", 0 },
1525         { }
1526 };
1527 MODULE_DEVICE_TABLE(i2c, da9055_i2c_id);
1528 
1529 static const struct of_device_id da9055_of_match[] = {
1530         { .compatible = "dlg,da9055-codec", },
1531         { }
1532 };
1533 MODULE_DEVICE_TABLE(of, da9055_of_match);
1534 
1535 /* I2C codec control layer */
1536 static struct i2c_driver da9055_i2c_driver = {
1537         .driver = {
1538                 .name = "da9055-codec",
1539                 .of_match_table = of_match_ptr(da9055_of_match),
1540         },
1541         .probe          = da9055_i2c_probe,
1542         .remove         = da9055_remove,
1543         .id_table       = da9055_i2c_id,
1544 };
1545 
1546 module_i2c_driver(da9055_i2c_driver);
1547 
1548 MODULE_DESCRIPTION("ASoC DA9055 Codec driver");
1549 MODULE_AUTHOR("David Chen, Ashish Chavan");
1550 MODULE_LICENSE("GPL");
1551 

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