Version:  2.6.34 2.6.35 2.6.36 2.6.37 2.6.38 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14

Linux/sound/soc/codecs/cs42l52.c

  1 /*
  2  * cs42l52.c -- CS42L52 ALSA SoC audio driver
  3  *
  4  * Copyright 2012 CirrusLogic, Inc.
  5  *
  6  * Author: Georgi Vlaev <joe@nucleusys.com>
  7  * Author: Brian Austin <brian.austin@cirrus.com>
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  *
 13  */
 14 
 15 #include <linux/module.h>
 16 #include <linux/moduleparam.h>
 17 #include <linux/kernel.h>
 18 #include <linux/init.h>
 19 #include <linux/delay.h>
 20 #include <linux/of_gpio.h>
 21 #include <linux/pm.h>
 22 #include <linux/i2c.h>
 23 #include <linux/input.h>
 24 #include <linux/regmap.h>
 25 #include <linux/slab.h>
 26 #include <linux/workqueue.h>
 27 #include <linux/platform_device.h>
 28 #include <sound/core.h>
 29 #include <sound/pcm.h>
 30 #include <sound/pcm_params.h>
 31 #include <sound/soc.h>
 32 #include <sound/soc-dapm.h>
 33 #include <sound/initval.h>
 34 #include <sound/tlv.h>
 35 #include <sound/cs42l52.h>
 36 #include "cs42l52.h"
 37 
 38 struct sp_config {
 39         u8 spc, format, spfs;
 40         u32 srate;
 41 };
 42 
 43 struct  cs42l52_private {
 44         struct regmap *regmap;
 45         struct snd_soc_codec *codec;
 46         struct device *dev;
 47         struct sp_config config;
 48         struct cs42l52_platform_data pdata;
 49         u32 sysclk;
 50         u8 mclksel;
 51         u32 mclk;
 52         u8 flags;
 53 #if IS_ENABLED(CONFIG_INPUT)
 54         struct input_dev *beep;
 55         struct work_struct beep_work;
 56         int beep_rate;
 57 #endif
 58 };
 59 
 60 static const struct reg_default cs42l52_reg_defaults[] = {
 61         { CS42L52_PWRCTL1, 0x9F },      /* r02 PWRCTL 1 */
 62         { CS42L52_PWRCTL2, 0x07 },      /* r03 PWRCTL 2 */
 63         { CS42L52_PWRCTL3, 0xFF },      /* r04 PWRCTL 3 */
 64         { CS42L52_CLK_CTL, 0xA0 },      /* r05 Clocking Ctl */
 65         { CS42L52_IFACE_CTL1, 0x00 },   /* r06 Interface Ctl 1 */
 66         { CS42L52_ADC_PGA_A, 0x80 },    /* r08 Input A Select */
 67         { CS42L52_ADC_PGA_B, 0x80 },    /* r09 Input B Select */
 68         { CS42L52_ANALOG_HPF_CTL, 0xA5 },       /* r0A Analog HPF Ctl */
 69         { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
 70         { CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
 71         { CS42L52_PB_CTL1, 0x60 },      /* r0D Playback Ctl 1 */
 72         { CS42L52_MISC_CTL, 0x02 },     /* r0E Misc. Ctl */
 73         { CS42L52_PB_CTL2, 0x00 },      /* r0F Playback Ctl 2 */
 74         { CS42L52_MICA_CTL, 0x00 },     /* r10 MICA Amp Ctl */
 75         { CS42L52_MICB_CTL, 0x00 },     /* r11 MICB Amp Ctl */
 76         { CS42L52_PGAA_CTL, 0x00 },     /* r12 PGAA Vol, Misc. */
 77         { CS42L52_PGAB_CTL, 0x00 },     /* r13 PGAB Vol, Misc. */
 78         { CS42L52_PASSTHRUA_VOL, 0x00 },        /* r14 Bypass A Vol */
 79         { CS42L52_PASSTHRUB_VOL, 0x00 },        /* r15 Bypass B Vol */
 80         { CS42L52_ADCA_VOL, 0x00 },     /* r16 ADCA Volume */
 81         { CS42L52_ADCB_VOL, 0x00 },     /* r17 ADCB Volume */
 82         { CS42L52_ADCA_MIXER_VOL, 0x80 },       /* r18 ADCA Mixer Volume */
 83         { CS42L52_ADCB_MIXER_VOL, 0x80 },       /* r19 ADCB Mixer Volume */
 84         { CS42L52_PCMA_MIXER_VOL, 0x00 },       /* r1A PCMA Mixer Volume */
 85         { CS42L52_PCMB_MIXER_VOL, 0x00 },       /* r1B PCMB Mixer Volume */
 86         { CS42L52_BEEP_FREQ, 0x00 },    /* r1C Beep Freq on Time */
 87         { CS42L52_BEEP_VOL, 0x00 },     /* r1D Beep Volume off Time */
 88         { CS42L52_BEEP_TONE_CTL, 0x00 },        /* r1E Beep Tone Cfg. */
 89         { CS42L52_TONE_CTL, 0x00 },     /* r1F Tone Ctl */
 90         { CS42L52_MASTERA_VOL, 0x00 },  /* r20 Master A Volume */
 91         { CS42L52_MASTERB_VOL, 0x00 },  /* r21 Master B Volume */
 92         { CS42L52_HPA_VOL, 0x00 },      /* r22 Headphone A Volume */
 93         { CS42L52_HPB_VOL, 0x00 },      /* r23 Headphone B Volume */
 94         { CS42L52_SPKA_VOL, 0x00 },     /* r24 Speaker A Volume */
 95         { CS42L52_SPKB_VOL, 0x00 },     /* r25 Speaker B Volume */
 96         { CS42L52_ADC_PCM_MIXER, 0x00 },        /* r26 Channel Mixer and Swap */
 97         { CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
 98         { CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
 99         { CS42L52_LIMITER_AT_RATE, 0xC0 },      /* r29 Limiter Attack Rate */
100         { CS42L52_ALC_CTL, 0x00 },      /* r2A ALC Ctl 1 Attack Rate */
101         { CS42L52_ALC_RATE, 0x3F },     /* r2B ALC Release Rate */
102         { CS42L52_ALC_THRESHOLD, 0x3f },        /* r2C ALC Thresholds */
103         { CS42L52_NOISE_GATE_CTL, 0x00 },       /* r2D Noise Gate Ctl */
104         { CS42L52_CLK_STATUS, 0x00 },   /* r2E Overflow and Clock Status */
105         { CS42L52_BATT_COMPEN, 0x00 },  /* r2F battery Compensation */
106         { CS42L52_BATT_LEVEL, 0x00 },   /* r30 VP Battery Level */
107         { CS42L52_SPK_STATUS, 0x00 },   /* r31 Speaker Status */
108         { CS42L52_TEM_CTL, 0x3B },      /* r32 Temp Ctl */
109         { CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */
110 };
111 
112 static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
113 {
114         switch (reg) {
115         case CS42L52_CHIP:
116         case CS42L52_PWRCTL1:
117         case CS42L52_PWRCTL2:
118         case CS42L52_PWRCTL3:
119         case CS42L52_CLK_CTL:
120         case CS42L52_IFACE_CTL1:
121         case CS42L52_IFACE_CTL2:
122         case CS42L52_ADC_PGA_A:
123         case CS42L52_ADC_PGA_B:
124         case CS42L52_ANALOG_HPF_CTL:
125         case CS42L52_ADC_HPF_FREQ:
126         case CS42L52_ADC_MISC_CTL:
127         case CS42L52_PB_CTL1:
128         case CS42L52_MISC_CTL:
129         case CS42L52_PB_CTL2:
130         case CS42L52_MICA_CTL:
131         case CS42L52_MICB_CTL:
132         case CS42L52_PGAA_CTL:
133         case CS42L52_PGAB_CTL:
134         case CS42L52_PASSTHRUA_VOL:
135         case CS42L52_PASSTHRUB_VOL:
136         case CS42L52_ADCA_VOL:
137         case CS42L52_ADCB_VOL:
138         case CS42L52_ADCA_MIXER_VOL:
139         case CS42L52_ADCB_MIXER_VOL:
140         case CS42L52_PCMA_MIXER_VOL:
141         case CS42L52_PCMB_MIXER_VOL:
142         case CS42L52_BEEP_FREQ:
143         case CS42L52_BEEP_VOL:
144         case CS42L52_BEEP_TONE_CTL:
145         case CS42L52_TONE_CTL:
146         case CS42L52_MASTERA_VOL:
147         case CS42L52_MASTERB_VOL:
148         case CS42L52_HPA_VOL:
149         case CS42L52_HPB_VOL:
150         case CS42L52_SPKA_VOL:
151         case CS42L52_SPKB_VOL:
152         case CS42L52_ADC_PCM_MIXER:
153         case CS42L52_LIMITER_CTL1:
154         case CS42L52_LIMITER_CTL2:
155         case CS42L52_LIMITER_AT_RATE:
156         case CS42L52_ALC_CTL:
157         case CS42L52_ALC_RATE:
158         case CS42L52_ALC_THRESHOLD:
159         case CS42L52_NOISE_GATE_CTL:
160         case CS42L52_CLK_STATUS:
161         case CS42L52_BATT_COMPEN:
162         case CS42L52_BATT_LEVEL:
163         case CS42L52_SPK_STATUS:
164         case CS42L52_TEM_CTL:
165         case CS42L52_THE_FOLDBACK:
166         case CS42L52_CHARGE_PUMP:
167                 return true;
168         default:
169                 return false;
170         }
171 }
172 
173 static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
174 {
175         switch (reg) {
176         case CS42L52_IFACE_CTL2:
177         case CS42L52_CLK_STATUS:
178         case CS42L52_BATT_LEVEL:
179         case CS42L52_SPK_STATUS:
180         case CS42L52_CHARGE_PUMP:
181                 return 1;
182         default:
183                 return 0;
184         }
185 }
186 
187 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
188 
189 static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
190 
191 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
192 
193 static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
194 
195 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
196 
197 static DECLARE_TLV_DB_SCALE(mix_tlv, -50, 50, 0);
198 
199 static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0);
200 
201 static const unsigned int limiter_tlv[] = {
202         TLV_DB_RANGE_HEAD(2),
203         0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
204         3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
205 };
206 
207 static const char * const cs42l52_adca_text[] = {
208         "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
209 
210 static const char * const cs42l52_adcb_text[] = {
211         "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
212 
213 static const struct soc_enum adca_enum =
214         SOC_ENUM_SINGLE(CS42L52_ADC_PGA_A, 5,
215                 ARRAY_SIZE(cs42l52_adca_text), cs42l52_adca_text);
216 
217 static const struct soc_enum adcb_enum =
218         SOC_ENUM_SINGLE(CS42L52_ADC_PGA_B, 5,
219                 ARRAY_SIZE(cs42l52_adcb_text), cs42l52_adcb_text);
220 
221 static const struct snd_kcontrol_new adca_mux =
222         SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
223 
224 static const struct snd_kcontrol_new adcb_mux =
225         SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
226 
227 static const char * const mic_bias_level_text[] = {
228         "0.5 +VA", "0.6 +VA", "0.7 +VA",
229         "0.8 +VA", "0.83 +VA", "0.91 +VA"
230 };
231 
232 static const struct soc_enum mic_bias_level_enum =
233         SOC_ENUM_SINGLE(CS42L52_IFACE_CTL2, 0,
234                         ARRAY_SIZE(mic_bias_level_text), mic_bias_level_text);
235 
236 static const char * const cs42l52_mic_text[] = { "MIC1", "MIC2" };
237 
238 static const struct soc_enum mica_enum =
239         SOC_ENUM_SINGLE(CS42L52_MICA_CTL, 5,
240                         ARRAY_SIZE(cs42l52_mic_text), cs42l52_mic_text);
241 
242 static const struct soc_enum micb_enum =
243         SOC_ENUM_SINGLE(CS42L52_MICB_CTL, 5,
244                         ARRAY_SIZE(cs42l52_mic_text), cs42l52_mic_text);
245 
246 static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
247 
248 static const struct soc_enum digital_output_mux_enum =
249         SOC_ENUM_SINGLE(CS42L52_ADC_MISC_CTL, 6,
250                         ARRAY_SIZE(digital_output_mux_text),
251                         digital_output_mux_text);
252 
253 static const struct snd_kcontrol_new digital_output_mux =
254         SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
255 
256 static const char * const hp_gain_num_text[] = {
257         "0.3959", "0.4571", "0.5111", "0.6047",
258         "0.7099", "0.8399", "1.000", "1.1430"
259 };
260 
261 static const struct soc_enum hp_gain_enum =
262         SOC_ENUM_SINGLE(CS42L52_PB_CTL1, 5,
263                 ARRAY_SIZE(hp_gain_num_text), hp_gain_num_text);
264 
265 static const char * const beep_pitch_text[] = {
266         "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
267         "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
268 };
269 
270 static const struct soc_enum beep_pitch_enum =
271         SOC_ENUM_SINGLE(CS42L52_BEEP_FREQ, 4,
272                         ARRAY_SIZE(beep_pitch_text), beep_pitch_text);
273 
274 static const char * const beep_ontime_text[] = {
275         "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
276         "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
277         "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
278 };
279 
280 static const struct soc_enum beep_ontime_enum =
281         SOC_ENUM_SINGLE(CS42L52_BEEP_FREQ, 0,
282                         ARRAY_SIZE(beep_ontime_text), beep_ontime_text);
283 
284 static const char * const beep_offtime_text[] = {
285         "1.23 s", "2.58 s", "3.90 s", "5.20 s",
286         "6.60 s", "8.05 s", "9.35 s", "10.80 s"
287 };
288 
289 static const struct soc_enum beep_offtime_enum =
290         SOC_ENUM_SINGLE(CS42L52_BEEP_VOL, 5,
291                         ARRAY_SIZE(beep_offtime_text), beep_offtime_text);
292 
293 static const char * const beep_config_text[] = {
294         "Off", "Single", "Multiple", "Continuous"
295 };
296 
297 static const struct soc_enum beep_config_enum =
298         SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 6,
299                         ARRAY_SIZE(beep_config_text), beep_config_text);
300 
301 static const char * const beep_bass_text[] = {
302         "50 Hz", "100 Hz", "200 Hz", "250 Hz"
303 };
304 
305 static const struct soc_enum beep_bass_enum =
306         SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 1,
307                         ARRAY_SIZE(beep_bass_text), beep_bass_text);
308 
309 static const char * const beep_treble_text[] = {
310         "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
311 };
312 
313 static const struct soc_enum beep_treble_enum =
314         SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 3,
315                         ARRAY_SIZE(beep_treble_text), beep_treble_text);
316 
317 static const char * const ng_threshold_text[] = {
318         "-34dB", "-37dB", "-40dB", "-43dB",
319         "-46dB", "-52dB", "-58dB", "-64dB"
320 };
321 
322 static const struct soc_enum ng_threshold_enum =
323         SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 2,
324                 ARRAY_SIZE(ng_threshold_text), ng_threshold_text);
325 
326 static const char * const cs42l52_ng_delay_text[] = {
327         "50ms", "100ms", "150ms", "200ms"};
328 
329 static const struct soc_enum ng_delay_enum =
330         SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 0,
331                 ARRAY_SIZE(cs42l52_ng_delay_text), cs42l52_ng_delay_text);
332 
333 static const char * const cs42l52_ng_type_text[] = {
334         "Apply Specific", "Apply All"
335 };
336 
337 static const struct soc_enum ng_type_enum =
338         SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 6,
339                 ARRAY_SIZE(cs42l52_ng_type_text), cs42l52_ng_type_text);
340 
341 static const char * const left_swap_text[] = {
342         "Left", "LR 2", "Right"};
343 
344 static const char * const right_swap_text[] = {
345         "Right", "LR 2", "Left"};
346 
347 static const unsigned int swap_values[] = { 0, 1, 3 };
348 
349 static const struct soc_enum adca_swap_enum =
350         SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 1,
351                               ARRAY_SIZE(left_swap_text),
352                               left_swap_text,
353                               swap_values);
354 
355 static const struct snd_kcontrol_new adca_mixer =
356         SOC_DAPM_ENUM("Route", adca_swap_enum);
357 
358 static const struct soc_enum pcma_swap_enum =
359         SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 1,
360                               ARRAY_SIZE(left_swap_text),
361                               left_swap_text,
362                               swap_values);
363 
364 static const struct snd_kcontrol_new pcma_mixer =
365         SOC_DAPM_ENUM("Route", pcma_swap_enum);
366 
367 static const struct soc_enum adcb_swap_enum =
368         SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 1,
369                               ARRAY_SIZE(right_swap_text),
370                               right_swap_text,
371                               swap_values);
372 
373 static const struct snd_kcontrol_new adcb_mixer =
374         SOC_DAPM_ENUM("Route", adcb_swap_enum);
375 
376 static const struct soc_enum pcmb_swap_enum =
377         SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 1,
378                               ARRAY_SIZE(right_swap_text),
379                               right_swap_text,
380                               swap_values);
381 
382 static const struct snd_kcontrol_new pcmb_mixer =
383         SOC_DAPM_ENUM("Route", pcmb_swap_enum);
384 
385 
386 static const struct snd_kcontrol_new passthrul_ctl =
387         SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
388 
389 static const struct snd_kcontrol_new passthrur_ctl =
390         SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
391 
392 static const struct snd_kcontrol_new spkl_ctl =
393         SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
394 
395 static const struct snd_kcontrol_new spkr_ctl =
396         SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
397 
398 static const struct snd_kcontrol_new hpl_ctl =
399         SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
400 
401 static const struct snd_kcontrol_new hpr_ctl =
402         SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
403 
404 static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
405 
406         SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
407                               CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
408 
409         SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
410                               CS42L52_HPB_VOL, 0, 0x34, 0xCC, hpd_tlv),
411 
412         SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
413 
414         SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
415                               CS42L52_SPKB_VOL, 0, 0x1, 0xff, hl_tlv),
416 
417         SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
418                               CS42L52_PASSTHRUB_VOL, 6, 0x18, 0x90, pga_tlv),
419 
420         SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
421 
422         SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
423                               CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
424 
425         SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
426 
427         SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
428                               CS42L52_ADCB_VOL, 7, 0x80, 0xA0, ipd_tlv),
429         SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
430                              CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
431                                 6, 0x7f, 0x19, ipd_tlv),
432 
433         SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
434 
435         SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
436                      CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
437 
438         SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
439                             CS42L52_PGAB_CTL, 0, 0x28, 0x30, pga_tlv),
440 
441         SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
442                             CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
443                                 0, 0x7f, 0x19, mix_tlv),
444         SOC_DOUBLE_R("PCM Mixer Switch",
445                      CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
446 
447         SOC_ENUM("Beep Config", beep_config_enum),
448         SOC_ENUM("Beep Pitch", beep_pitch_enum),
449         SOC_ENUM("Beep on Time", beep_ontime_enum),
450         SOC_ENUM("Beep off Time", beep_offtime_enum),
451         SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL,
452                         0, 0x07, 0x1f, beep_tlv),
453         SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
454         SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
455         SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
456 
457         SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
458         SOC_SINGLE_TLV("Treble Gain Volume",
459                             CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
460         SOC_SINGLE_TLV("Bass Gain Volume",
461                             CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
462 
463         /* Limiter */
464         SOC_SINGLE_TLV("Limiter Max Threshold Volume",
465                        CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
466         SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
467                        CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
468         SOC_SINGLE_TLV("Limiter Release Rate Volume",
469                        CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
470         SOC_SINGLE_TLV("Limiter Attack Rate Volume",
471                        CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
472 
473         SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
474         SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
475         SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
476 
477         /* ALC */
478         SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
479                        0, 63, 0, limiter_tlv),
480         SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
481                        0, 63, 0, limiter_tlv),
482         SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
483                        5, 7, 0, limiter_tlv),
484         SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
485                        2, 7, 0, limiter_tlv),
486 
487         SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
488                      CS42L52_PGAB_CTL, 7, 1, 1),
489         SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
490                      CS42L52_PGAB_CTL, 6, 1, 1),
491         SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
492 
493         /* Noise gate */
494         SOC_ENUM("NG Type Switch", ng_type_enum),
495         SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
496         SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
497         SOC_ENUM("NG Threshold", ng_threshold_enum),
498         SOC_ENUM("NG Delay", ng_delay_enum),
499 
500         SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
501 
502         SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
503         SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
504         SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
505         SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
506         SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
507 
508         SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
509         SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
510         SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
511 
512         SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
513         SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
514         SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
515         SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
516 
517         SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
518         SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
519 
520         SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
521         SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
522 
523         SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
524         SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
525 
526 };
527 
528 static const struct snd_kcontrol_new cs42l52_mica_controls[] = {
529         SOC_ENUM("MICA Select", mica_enum),
530 };
531 
532 static const struct snd_kcontrol_new cs42l52_micb_controls[] = {
533         SOC_ENUM("MICB Select", micb_enum),
534 };
535 
536 static int cs42l52_add_mic_controls(struct snd_soc_codec *codec)
537 {
538         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
539         struct cs42l52_platform_data *pdata = &cs42l52->pdata;
540 
541         if (!pdata->mica_diff_cfg)
542                 snd_soc_add_codec_controls(codec, cs42l52_mica_controls,
543                                      ARRAY_SIZE(cs42l52_mica_controls));
544 
545         if (!pdata->micb_diff_cfg)
546                 snd_soc_add_codec_controls(codec, cs42l52_micb_controls,
547                                      ARRAY_SIZE(cs42l52_micb_controls));
548 
549         return 0;
550 }
551 
552 static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
553 
554         SND_SOC_DAPM_INPUT("AIN1L"),
555         SND_SOC_DAPM_INPUT("AIN1R"),
556         SND_SOC_DAPM_INPUT("AIN2L"),
557         SND_SOC_DAPM_INPUT("AIN2R"),
558         SND_SOC_DAPM_INPUT("AIN3L"),
559         SND_SOC_DAPM_INPUT("AIN3R"),
560         SND_SOC_DAPM_INPUT("AIN4L"),
561         SND_SOC_DAPM_INPUT("AIN4R"),
562         SND_SOC_DAPM_INPUT("MICA"),
563         SND_SOC_DAPM_INPUT("MICB"),
564         SND_SOC_DAPM_SIGGEN("Beep"),
565 
566         SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL,  0,
567                         SND_SOC_NOPM, 0, 0),
568         SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL,  0,
569                         SND_SOC_NOPM, 0, 0),
570 
571         SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
572         SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
573         SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
574         SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
575 
576         SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
577         SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
578 
579         SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
580                          0, 0, &adca_mixer),
581         SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
582                          0, 0, &adcb_mixer),
583 
584         SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
585                          0, 0, &digital_output_mux),
586 
587         SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
588         SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
589 
590         SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
591         SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
592 
593         SND_SOC_DAPM_AIF_IN("AIFINL", NULL,  0,
594                         SND_SOC_NOPM, 0, 0),
595         SND_SOC_DAPM_AIF_IN("AIFINR", NULL,  0,
596                         SND_SOC_NOPM, 0, 0),
597 
598         SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
599         SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
600 
601         SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
602                             6, 0, &passthrul_ctl),
603         SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
604                             7, 0, &passthrur_ctl),
605 
606         SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
607                          0, 0, &pcma_mixer),
608         SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
609                          0, 0, &pcmb_mixer),
610 
611         SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
612         SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
613 
614         SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
615         SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
616 
617         SND_SOC_DAPM_OUTPUT("HPOUTA"),
618         SND_SOC_DAPM_OUTPUT("HPOUTB"),
619         SND_SOC_DAPM_OUTPUT("SPKOUTA"),
620         SND_SOC_DAPM_OUTPUT("SPKOUTB"),
621 
622 };
623 
624 static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
625 
626         {"Capture", NULL, "AIFOUTL"},
627         {"Capture", NULL, "AIFOUTL"},
628 
629         {"AIFOUTL", NULL, "Output Mux"},
630         {"AIFOUTR", NULL, "Output Mux"},
631 
632         {"Output Mux", "ADC", "ADC Left"},
633         {"Output Mux", "ADC", "ADC Right"},
634 
635         {"ADC Left", NULL, "Charge Pump"},
636         {"ADC Right", NULL, "Charge Pump"},
637 
638         {"Charge Pump", NULL, "ADC Left Mux"},
639         {"Charge Pump", NULL, "ADC Right Mux"},
640 
641         {"ADC Left Mux", "Input1A", "AIN1L"},
642         {"ADC Right Mux", "Input1B", "AIN1R"},
643         {"ADC Left Mux", "Input2A", "AIN2L"},
644         {"ADC Right Mux", "Input2B", "AIN2R"},
645         {"ADC Left Mux", "Input3A", "AIN3L"},
646         {"ADC Right Mux", "Input3B", "AIN3R"},
647         {"ADC Left Mux", "Input4A", "AIN4L"},
648         {"ADC Right Mux", "Input4B", "AIN4R"},
649         {"ADC Left Mux", "PGA Input Left", "PGA Left"},
650         {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
651 
652         {"PGA Left", "Switch", "AIN1L"},
653         {"PGA Right", "Switch", "AIN1R"},
654         {"PGA Left", "Switch", "AIN2L"},
655         {"PGA Right", "Switch", "AIN2R"},
656         {"PGA Left", "Switch", "AIN3L"},
657         {"PGA Right", "Switch", "AIN3R"},
658         {"PGA Left", "Switch", "AIN4L"},
659         {"PGA Right", "Switch", "AIN4R"},
660 
661         {"PGA Left", "Switch", "PGA MICA"},
662         {"PGA MICA", NULL, "MICA"},
663 
664         {"PGA Right", "Switch", "PGA MICB"},
665         {"PGA MICB", NULL, "MICB"},
666 
667         {"HPOUTA", NULL, "HP Left Amp"},
668         {"HPOUTB", NULL, "HP Right Amp"},
669         {"HP Left Amp", NULL, "Bypass Left"},
670         {"HP Right Amp", NULL, "Bypass Right"},
671         {"Bypass Left", "Switch", "PGA Left"},
672         {"Bypass Right", "Switch", "PGA Right"},
673         {"HP Left Amp", "Switch", "DAC Left"},
674         {"HP Right Amp", "Switch", "DAC Right"},
675 
676         {"SPKOUTA", NULL, "SPK Left Amp"},
677         {"SPKOUTB", NULL, "SPK Right Amp"},
678 
679         {"SPK Left Amp", NULL, "Beep"},
680         {"SPK Right Amp", NULL, "Beep"},
681         {"SPK Left Amp", "Switch", "Playback"},
682         {"SPK Right Amp", "Switch", "Playback"},
683 
684         {"DAC Left", NULL, "Beep"},
685         {"DAC Right", NULL, "Beep"},
686         {"DAC Left", NULL, "Playback"},
687         {"DAC Right", NULL, "Playback"},
688 
689         {"Output Mux", "DSP", "Playback"},
690         {"Output Mux", "DSP", "Playback"},
691 
692         {"AIFINL", NULL, "Playback"},
693         {"AIFINR", NULL, "Playback"},
694 
695 };
696 
697 struct cs42l52_clk_para {
698         u32 mclk;
699         u32 rate;
700         u8 speed;
701         u8 group;
702         u8 videoclk;
703         u8 ratio;
704         u8 mclkdiv2;
705 };
706 
707 static const struct cs42l52_clk_para clk_map_table[] = {
708         /*8k*/
709         {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
710         {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
711         {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
712         {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
713         {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
714 
715         /*11.025k*/
716         {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
717         {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
718 
719         /*16k*/
720         {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
721         {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
722         {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
723         {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
724         {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
725 
726         /*22.05k*/
727         {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
728         {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
729 
730         /* 32k */
731         {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
732         {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
733         {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
734         {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
735         {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
736 
737         /* 44.1k */
738         {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
739         {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
740 
741         /* 48k */
742         {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
743         {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
744         {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
745         {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
746         {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
747 
748         /* 88.2k */
749         {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
750         {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
751 
752         /* 96k */
753         {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
754         {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
755         {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
756         {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
757 };
758 
759 static int cs42l52_get_clk(int mclk, int rate)
760 {
761         int i, ret = -EINVAL;
762         u_int mclk1, mclk2 = 0;
763 
764         for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
765                 if (clk_map_table[i].rate == rate) {
766                         mclk1 = clk_map_table[i].mclk;
767                         if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
768                                 mclk2 = mclk1;
769                                 ret = i;
770                         }
771                 }
772         }
773         return ret;
774 }
775 
776 static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
777                         int clk_id, unsigned int freq, int dir)
778 {
779         struct snd_soc_codec *codec = codec_dai->codec;
780         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
781 
782         if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
783                 cs42l52->sysclk = freq;
784         } else {
785                 dev_err(codec->dev, "Invalid freq parameter\n");
786                 return -EINVAL;
787         }
788         return 0;
789 }
790 
791 static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
792 {
793         struct snd_soc_codec *codec = codec_dai->codec;
794         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
795         u8 iface = 0;
796 
797         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
798         case SND_SOC_DAIFMT_CBM_CFM:
799                 iface = CS42L52_IFACE_CTL1_MASTER;
800                 break;
801         case SND_SOC_DAIFMT_CBS_CFS:
802                 iface = CS42L52_IFACE_CTL1_SLAVE;
803                 break;
804         default:
805                 return -EINVAL;
806         }
807 
808          /* interface format */
809         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
810         case SND_SOC_DAIFMT_I2S:
811                 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
812                                 CS42L52_IFACE_CTL1_DAC_FMT_I2S;
813                 break;
814         case SND_SOC_DAIFMT_RIGHT_J:
815                 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
816                 break;
817         case SND_SOC_DAIFMT_LEFT_J:
818                 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
819                                 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
820                 break;
821         case SND_SOC_DAIFMT_DSP_A:
822                 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
823                 break;
824         case SND_SOC_DAIFMT_DSP_B:
825                 break;
826         default:
827                 return -EINVAL;
828         }
829 
830         /* clock inversion */
831         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
832         case SND_SOC_DAIFMT_NB_NF:
833                 break;
834         case SND_SOC_DAIFMT_IB_IF:
835                 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
836                 break;
837         case SND_SOC_DAIFMT_IB_NF:
838                 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
839                 break;
840         case SND_SOC_DAIFMT_NB_IF:
841                 break;
842         default:
843                 return -EINVAL;
844         }
845         cs42l52->config.format = iface;
846         snd_soc_write(codec, CS42L52_IFACE_CTL1, cs42l52->config.format);
847 
848         return 0;
849 }
850 
851 static int cs42l52_digital_mute(struct snd_soc_dai *dai, int mute)
852 {
853         struct snd_soc_codec *codec = dai->codec;
854 
855         if (mute)
856                 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
857                                     CS42L52_PB_CTL1_MUTE_MASK,
858                                 CS42L52_PB_CTL1_MUTE);
859         else
860                 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
861                                     CS42L52_PB_CTL1_MUTE_MASK,
862                                 CS42L52_PB_CTL1_UNMUTE);
863 
864         return 0;
865 }
866 
867 static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
868                                      struct snd_pcm_hw_params *params,
869                                      struct snd_soc_dai *dai)
870 {
871         struct snd_soc_codec *codec = dai->codec;
872         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
873         u32 clk = 0;
874         int index;
875 
876         index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
877         if (index >= 0) {
878                 cs42l52->sysclk = clk_map_table[index].mclk;
879 
880                 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
881                 (clk_map_table[index].group << CLK_32K_SR_SHIFT) |
882                 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
883                 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
884                 clk_map_table[index].mclkdiv2;
885 
886                 snd_soc_write(codec, CS42L52_CLK_CTL, clk);
887         } else {
888                 dev_err(codec->dev, "can't get correct mclk\n");
889                 return -EINVAL;
890         }
891 
892         return 0;
893 }
894 
895 static int cs42l52_set_bias_level(struct snd_soc_codec *codec,
896                                         enum snd_soc_bias_level level)
897 {
898         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
899 
900         switch (level) {
901         case SND_SOC_BIAS_ON:
902                 break;
903         case SND_SOC_BIAS_PREPARE:
904                 snd_soc_update_bits(codec, CS42L52_PWRCTL1,
905                                     CS42L52_PWRCTL1_PDN_CODEC, 0);
906                 break;
907         case SND_SOC_BIAS_STANDBY:
908                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
909                         regcache_cache_only(cs42l52->regmap, false);
910                         regcache_sync(cs42l52->regmap);
911                 }
912                 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
913                 break;
914         case SND_SOC_BIAS_OFF:
915                 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
916                 regcache_cache_only(cs42l52->regmap, true);
917                 break;
918         }
919         codec->dapm.bias_level = level;
920 
921         return 0;
922 }
923 
924 #define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
925 
926 #define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
927                         SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
928                         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
929                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
930 
931 static struct snd_soc_dai_ops cs42l52_ops = {
932         .hw_params      = cs42l52_pcm_hw_params,
933         .digital_mute   = cs42l52_digital_mute,
934         .set_fmt        = cs42l52_set_fmt,
935         .set_sysclk     = cs42l52_set_sysclk,
936 };
937 
938 static struct snd_soc_dai_driver cs42l52_dai = {
939                 .name = "cs42l52",
940                 .playback = {
941                         .stream_name = "Playback",
942                         .channels_min = 1,
943                         .channels_max = 2,
944                         .rates = CS42L52_RATES,
945                         .formats = CS42L52_FORMATS,
946                 },
947                 .capture = {
948                         .stream_name = "Capture",
949                         .channels_min = 1,
950                         .channels_max = 2,
951                         .rates = CS42L52_RATES,
952                         .formats = CS42L52_FORMATS,
953                 },
954                 .ops = &cs42l52_ops,
955 };
956 
957 static int cs42l52_suspend(struct snd_soc_codec *codec)
958 {
959         cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
960 
961         return 0;
962 }
963 
964 static int cs42l52_resume(struct snd_soc_codec *codec)
965 {
966         cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
967 
968         return 0;
969 }
970 
971 #if IS_ENABLED(CONFIG_INPUT)
972 static int beep_rates[] = {
973         261, 522, 585, 667, 706, 774, 889, 1000,
974         1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
975 };
976 
977 static void cs42l52_beep_work(struct work_struct *work)
978 {
979         struct cs42l52_private *cs42l52 =
980                 container_of(work, struct cs42l52_private, beep_work);
981         struct snd_soc_codec *codec = cs42l52->codec;
982         struct snd_soc_dapm_context *dapm = &codec->dapm;
983         int i;
984         int val = 0;
985         int best = 0;
986 
987         if (cs42l52->beep_rate) {
988                 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
989                         if (abs(cs42l52->beep_rate - beep_rates[i]) <
990                             abs(cs42l52->beep_rate - beep_rates[best]))
991                                 best = i;
992                 }
993 
994                 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
995                         beep_rates[best], cs42l52->beep_rate);
996 
997                 val = (best << CS42L52_BEEP_RATE_SHIFT);
998 
999                 snd_soc_dapm_enable_pin(dapm, "Beep");
1000         } else {
1001                 dev_dbg(codec->dev, "Disabling beep\n");
1002                 snd_soc_dapm_disable_pin(dapm, "Beep");
1003         }
1004 
1005         snd_soc_update_bits(codec, CS42L52_BEEP_FREQ,
1006                             CS42L52_BEEP_RATE_MASK, val);
1007 
1008         snd_soc_dapm_sync(dapm);
1009 }
1010 
1011 /* For usability define a way of injecting beep events for the device -
1012  * many systems will not have a keyboard.
1013  */
1014 static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
1015                              unsigned int code, int hz)
1016 {
1017         struct snd_soc_codec *codec = input_get_drvdata(dev);
1018         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1019 
1020         dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1021 
1022         switch (code) {
1023         case SND_BELL:
1024                 if (hz)
1025                         hz = 261;
1026         case SND_TONE:
1027                 break;
1028         default:
1029                 return -1;
1030         }
1031 
1032         /* Kick the beep from a workqueue */
1033         cs42l52->beep_rate = hz;
1034         schedule_work(&cs42l52->beep_work);
1035         return 0;
1036 }
1037 
1038 static ssize_t cs42l52_beep_set(struct device *dev,
1039                                struct device_attribute *attr,
1040                                const char *buf, size_t count)
1041 {
1042         struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
1043         long int time;
1044         int ret;
1045 
1046         ret = kstrtol(buf, 10, &time);
1047         if (ret != 0)
1048                 return ret;
1049 
1050         input_event(cs42l52->beep, EV_SND, SND_TONE, time);
1051 
1052         return count;
1053 }
1054 
1055 static DEVICE_ATTR(beep, 0200, NULL, cs42l52_beep_set);
1056 
1057 static void cs42l52_init_beep(struct snd_soc_codec *codec)
1058 {
1059         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1060         int ret;
1061 
1062         cs42l52->beep = devm_input_allocate_device(codec->dev);
1063         if (!cs42l52->beep) {
1064                 dev_err(codec->dev, "Failed to allocate beep device\n");
1065                 return;
1066         }
1067 
1068         INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
1069         cs42l52->beep_rate = 0;
1070 
1071         cs42l52->beep->name = "CS42L52 Beep Generator";
1072         cs42l52->beep->phys = dev_name(codec->dev);
1073         cs42l52->beep->id.bustype = BUS_I2C;
1074 
1075         cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
1076         cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1077         cs42l52->beep->event = cs42l52_beep_event;
1078         cs42l52->beep->dev.parent = codec->dev;
1079         input_set_drvdata(cs42l52->beep, codec);
1080 
1081         ret = input_register_device(cs42l52->beep);
1082         if (ret != 0) {
1083                 cs42l52->beep = NULL;
1084                 dev_err(codec->dev, "Failed to register beep device\n");
1085         }
1086 
1087         ret = device_create_file(codec->dev, &dev_attr_beep);
1088         if (ret != 0) {
1089                 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1090                         ret);
1091         }
1092 }
1093 
1094 static void cs42l52_free_beep(struct snd_soc_codec *codec)
1095 {
1096         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1097 
1098         device_remove_file(codec->dev, &dev_attr_beep);
1099         cancel_work_sync(&cs42l52->beep_work);
1100         cs42l52->beep = NULL;
1101 
1102         snd_soc_update_bits(codec, CS42L52_BEEP_TONE_CTL,
1103                             CS42L52_BEEP_EN_MASK, 0);
1104 }
1105 #else
1106 static void cs42l52_init_beep(struct snd_soc_codec *codec)
1107 {
1108 }
1109 
1110 static void cs42l52_free_beep(struct snd_soc_codec *codec)
1111 {
1112 }
1113 #endif
1114 
1115 static int cs42l52_probe(struct snd_soc_codec *codec)
1116 {
1117         struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1118         int ret;
1119 
1120         codec->control_data = cs42l52->regmap;
1121         ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1122         if (ret < 0) {
1123                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1124                 return ret;
1125         }
1126         regcache_cache_only(cs42l52->regmap, true);
1127 
1128         cs42l52_add_mic_controls(codec);
1129 
1130         cs42l52_init_beep(codec);
1131 
1132         cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1133 
1134         cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1135         cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1136 
1137         return ret;
1138 }
1139 
1140 static int cs42l52_remove(struct snd_soc_codec *codec)
1141 {
1142         cs42l52_free_beep(codec);
1143         cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
1144 
1145         return 0;
1146 }
1147 
1148 static struct snd_soc_codec_driver soc_codec_dev_cs42l52 = {
1149         .probe = cs42l52_probe,
1150         .remove = cs42l52_remove,
1151         .suspend = cs42l52_suspend,
1152         .resume = cs42l52_resume,
1153         .set_bias_level = cs42l52_set_bias_level,
1154 
1155         .dapm_widgets = cs42l52_dapm_widgets,
1156         .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
1157         .dapm_routes = cs42l52_audio_map,
1158         .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
1159 
1160         .controls = cs42l52_snd_controls,
1161         .num_controls = ARRAY_SIZE(cs42l52_snd_controls),
1162 };
1163 
1164 /* Current and threshold powerup sequence Pg37 */
1165 static const struct reg_default cs42l52_threshold_patch[] = {
1166 
1167         { 0x00, 0x99 },
1168         { 0x3E, 0xBA },
1169         { 0x47, 0x80 },
1170         { 0x32, 0xBB },
1171         { 0x32, 0x3B },
1172         { 0x00, 0x00 },
1173 
1174 };
1175 
1176 static struct regmap_config cs42l52_regmap = {
1177         .reg_bits = 8,
1178         .val_bits = 8,
1179 
1180         .max_register = CS42L52_MAX_REGISTER,
1181         .reg_defaults = cs42l52_reg_defaults,
1182         .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
1183         .readable_reg = cs42l52_readable_register,
1184         .volatile_reg = cs42l52_volatile_register,
1185         .cache_type = REGCACHE_RBTREE,
1186 };
1187 
1188 static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1189                              const struct i2c_device_id *id)
1190 {
1191         struct cs42l52_private *cs42l52;
1192         struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1193         int ret;
1194         unsigned int devid = 0;
1195         unsigned int reg;
1196         u32 val32;
1197 
1198         cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l52_private),
1199                                GFP_KERNEL);
1200         if (cs42l52 == NULL)
1201                 return -ENOMEM;
1202         cs42l52->dev = &i2c_client->dev;
1203 
1204         cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
1205         if (IS_ERR(cs42l52->regmap)) {
1206                 ret = PTR_ERR(cs42l52->regmap);
1207                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1208                 return ret;
1209         }
1210         if (pdata) {
1211                 cs42l52->pdata = *pdata;
1212         } else {
1213                 pdata = devm_kzalloc(&i2c_client->dev,
1214                                      sizeof(struct cs42l52_platform_data),
1215                                 GFP_KERNEL);
1216                 if (!pdata) {
1217                         dev_err(&i2c_client->dev, "could not allocate pdata\n");
1218                         return -ENOMEM;
1219                 }
1220                 if (i2c_client->dev.of_node) {
1221                         if (of_property_read_bool(i2c_client->dev.of_node,
1222                                 "cirrus,mica-differential-cfg"))
1223                                 pdata->mica_diff_cfg = true;
1224 
1225                         if (of_property_read_bool(i2c_client->dev.of_node,
1226                                 "cirrus,micb-differential-cfg"))
1227                                 pdata->micb_diff_cfg = true;
1228 
1229                         if (of_property_read_u32(i2c_client->dev.of_node,
1230                                 "cirrus,micbias-lvl", &val32) >= 0)
1231                                 pdata->micbias_lvl = val32;
1232 
1233                         if (of_property_read_u32(i2c_client->dev.of_node,
1234                                 "cirrus,chgfreq-divisor", &val32) >= 0)
1235                                 pdata->chgfreq = val32;
1236 
1237                         pdata->reset_gpio =
1238                                 of_get_named_gpio(i2c_client->dev.of_node,
1239                                                 "cirrus,reset-gpio", 0);
1240                 }
1241                 cs42l52->pdata = *pdata;
1242         }
1243 
1244         if (cs42l52->pdata.reset_gpio) {
1245                 ret = gpio_request_one(cs42l52->pdata.reset_gpio,
1246                                        GPIOF_OUT_INIT_HIGH, "CS42L52 /RST");
1247                 if (ret < 0) {
1248                         dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1249                                 cs42l52->pdata.reset_gpio, ret);
1250                         return ret;
1251                 }
1252                 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
1253                 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
1254         }
1255 
1256         i2c_set_clientdata(i2c_client, cs42l52);
1257 
1258         ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1259                                     ARRAY_SIZE(cs42l52_threshold_patch));
1260         if (ret != 0)
1261                 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1262                          ret);
1263 
1264         ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, &reg);
1265         devid = reg & CS42L52_CHIP_ID_MASK;
1266         if (devid != CS42L52_CHIP_ID) {
1267                 ret = -ENODEV;
1268                 dev_err(&i2c_client->dev,
1269                         "CS42L52 Device ID (%X). Expected %X\n",
1270                         devid, CS42L52_CHIP_ID);
1271                 return ret;
1272         }
1273 
1274         dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
1275                         reg & 0xFF);
1276 
1277         /* Set Platform Data */
1278         if (cs42l52->pdata.mica_diff_cfg)
1279                 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1280                                    CS42L52_MIC_CTL_TYPE_MASK,
1281                                 cs42l52->pdata.mica_diff_cfg <<
1282                                 CS42L52_MIC_CTL_TYPE_SHIFT);
1283 
1284         if (cs42l52->pdata.micb_diff_cfg)
1285                 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1286                                    CS42L52_MIC_CTL_TYPE_MASK,
1287                                 cs42l52->pdata.micb_diff_cfg <<
1288                                 CS42L52_MIC_CTL_TYPE_SHIFT);
1289 
1290         if (cs42l52->pdata.chgfreq)
1291                 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
1292                                    CS42L52_CHARGE_PUMP_MASK,
1293                                 cs42l52->pdata.chgfreq <<
1294                                 CS42L52_CHARGE_PUMP_SHIFT);
1295 
1296         if (cs42l52->pdata.micbias_lvl)
1297                 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
1298                                    CS42L52_IFACE_CTL2_BIAS_LVL,
1299                                 cs42l52->pdata.micbias_lvl);
1300 
1301         ret =  snd_soc_register_codec(&i2c_client->dev,
1302                         &soc_codec_dev_cs42l52, &cs42l52_dai, 1);
1303         if (ret < 0)
1304                 return ret;
1305         return 0;
1306 }
1307 
1308 static int cs42l52_i2c_remove(struct i2c_client *client)
1309 {
1310         snd_soc_unregister_codec(&client->dev);
1311         return 0;
1312 }
1313 
1314 static const struct of_device_id cs42l52_of_match[] = {
1315         { .compatible = "cirrus,cs42l52", },
1316         {},
1317 };
1318 MODULE_DEVICE_TABLE(of, cs42l52_of_match);
1319 
1320 
1321 static const struct i2c_device_id cs42l52_id[] = {
1322         { "cs42l52", 0 },
1323         { }
1324 };
1325 MODULE_DEVICE_TABLE(i2c, cs42l52_id);
1326 
1327 static struct i2c_driver cs42l52_i2c_driver = {
1328         .driver = {
1329                 .name = "cs42l52",
1330                 .owner = THIS_MODULE,
1331                 .of_match_table = cs42l52_of_match,
1332         },
1333         .id_table = cs42l52_id,
1334         .probe =    cs42l52_i2c_probe,
1335         .remove =   cs42l52_i2c_remove,
1336 };
1337 
1338 module_i2c_driver(cs42l52_i2c_driver);
1339 
1340 MODULE_DESCRIPTION("ASoC CS42L52 driver");
1341 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1342 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1343 MODULE_LICENSE("GPL");
1344 

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