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Linux/sound/soc/codecs/cs4271.c

  1 /*
  2  * CS4271 ASoC codec driver
  3  *
  4  * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License
  8  * as published by the Free Software Foundation; either version 2
  9  * of the License, or (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  *
 16  * This driver support CS4271 codec being master or slave, working
 17  * in control port mode, connected either via SPI or I2C.
 18  * The data format accepted is I2S or left-justified.
 19  * DAPM support not implemented.
 20  */
 21 
 22 #include <linux/module.h>
 23 #include <linux/slab.h>
 24 #include <linux/delay.h>
 25 #include <linux/gpio.h>
 26 #include <linux/i2c.h>
 27 #include <linux/spi/spi.h>
 28 #include <linux/of.h>
 29 #include <linux/of_device.h>
 30 #include <linux/of_gpio.h>
 31 #include <sound/pcm.h>
 32 #include <sound/soc.h>
 33 #include <sound/tlv.h>
 34 #include <sound/cs4271.h>
 35 
 36 #define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
 37                             SNDRV_PCM_FMTBIT_S24_LE | \
 38                             SNDRV_PCM_FMTBIT_S32_LE)
 39 #define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000
 40 
 41 /*
 42  * CS4271 registers
 43  */
 44 #define CS4271_MODE1    0x01    /* Mode Control 1 */
 45 #define CS4271_DACCTL   0x02    /* DAC Control */
 46 #define CS4271_DACVOL   0x03    /* DAC Volume & Mixing Control */
 47 #define CS4271_VOLA     0x04    /* DAC Channel A Volume Control */
 48 #define CS4271_VOLB     0x05    /* DAC Channel B Volume Control */
 49 #define CS4271_ADCCTL   0x06    /* ADC Control */
 50 #define CS4271_MODE2    0x07    /* Mode Control 2 */
 51 #define CS4271_CHIPID   0x08    /* Chip ID */
 52 
 53 #define CS4271_FIRSTREG CS4271_MODE1
 54 #define CS4271_LASTREG  CS4271_MODE2
 55 #define CS4271_NR_REGS  ((CS4271_LASTREG & 0xFF) + 1)
 56 
 57 /* Bit masks for the CS4271 registers */
 58 #define CS4271_MODE1_MODE_MASK  0xC0
 59 #define CS4271_MODE1_MODE_1X    0x00
 60 #define CS4271_MODE1_MODE_2X    0x80
 61 #define CS4271_MODE1_MODE_4X    0xC0
 62 
 63 #define CS4271_MODE1_DIV_MASK   0x30
 64 #define CS4271_MODE1_DIV_1      0x00
 65 #define CS4271_MODE1_DIV_15     0x10
 66 #define CS4271_MODE1_DIV_2      0x20
 67 #define CS4271_MODE1_DIV_3      0x30
 68 
 69 #define CS4271_MODE1_MASTER     0x08
 70 
 71 #define CS4271_MODE1_DAC_DIF_MASK       0x07
 72 #define CS4271_MODE1_DAC_DIF_LJ         0x00
 73 #define CS4271_MODE1_DAC_DIF_I2S        0x01
 74 #define CS4271_MODE1_DAC_DIF_RJ16       0x02
 75 #define CS4271_MODE1_DAC_DIF_RJ24       0x03
 76 #define CS4271_MODE1_DAC_DIF_RJ20       0x04
 77 #define CS4271_MODE1_DAC_DIF_RJ18       0x05
 78 
 79 #define CS4271_DACCTL_AMUTE     0x80
 80 #define CS4271_DACCTL_IF_SLOW   0x40
 81 
 82 #define CS4271_DACCTL_DEM_MASK  0x30
 83 #define CS4271_DACCTL_DEM_DIS   0x00
 84 #define CS4271_DACCTL_DEM_441   0x10
 85 #define CS4271_DACCTL_DEM_48    0x20
 86 #define CS4271_DACCTL_DEM_32    0x30
 87 
 88 #define CS4271_DACCTL_SVRU      0x08
 89 #define CS4271_DACCTL_SRD       0x04
 90 #define CS4271_DACCTL_INVA      0x02
 91 #define CS4271_DACCTL_INVB      0x01
 92 
 93 #define CS4271_DACVOL_BEQUA     0x40
 94 #define CS4271_DACVOL_SOFT      0x20
 95 #define CS4271_DACVOL_ZEROC     0x10
 96 
 97 #define CS4271_DACVOL_ATAPI_MASK        0x0F
 98 #define CS4271_DACVOL_ATAPI_M_M         0x00
 99 #define CS4271_DACVOL_ATAPI_M_BR        0x01
100 #define CS4271_DACVOL_ATAPI_M_BL        0x02
101 #define CS4271_DACVOL_ATAPI_M_BLR2      0x03
102 #define CS4271_DACVOL_ATAPI_AR_M        0x04
103 #define CS4271_DACVOL_ATAPI_AR_BR       0x05
104 #define CS4271_DACVOL_ATAPI_AR_BL       0x06
105 #define CS4271_DACVOL_ATAPI_AR_BLR2     0x07
106 #define CS4271_DACVOL_ATAPI_AL_M        0x08
107 #define CS4271_DACVOL_ATAPI_AL_BR       0x09
108 #define CS4271_DACVOL_ATAPI_AL_BL       0x0A
109 #define CS4271_DACVOL_ATAPI_AL_BLR2     0x0B
110 #define CS4271_DACVOL_ATAPI_ALR2_M      0x0C
111 #define CS4271_DACVOL_ATAPI_ALR2_BR     0x0D
112 #define CS4271_DACVOL_ATAPI_ALR2_BL     0x0E
113 #define CS4271_DACVOL_ATAPI_ALR2_BLR2   0x0F
114 
115 #define CS4271_VOLA_MUTE        0x80
116 #define CS4271_VOLA_VOL_MASK    0x7F
117 #define CS4271_VOLB_MUTE        0x80
118 #define CS4271_VOLB_VOL_MASK    0x7F
119 
120 #define CS4271_ADCCTL_DITHER16  0x20
121 
122 #define CS4271_ADCCTL_ADC_DIF_MASK      0x10
123 #define CS4271_ADCCTL_ADC_DIF_LJ        0x00
124 #define CS4271_ADCCTL_ADC_DIF_I2S       0x10
125 
126 #define CS4271_ADCCTL_MUTEA     0x08
127 #define CS4271_ADCCTL_MUTEB     0x04
128 #define CS4271_ADCCTL_HPFDA     0x02
129 #define CS4271_ADCCTL_HPFDB     0x01
130 
131 #define CS4271_MODE2_LOOP       0x10
132 #define CS4271_MODE2_MUTECAEQUB 0x08
133 #define CS4271_MODE2_FREEZE     0x04
134 #define CS4271_MODE2_CPEN       0x02
135 #define CS4271_MODE2_PDN        0x01
136 
137 #define CS4271_CHIPID_PART_MASK 0xF0
138 #define CS4271_CHIPID_REV_MASK  0x0F
139 
140 /*
141  * Default CS4271 power-up configuration
142  * Array contains non-existing in hw register at address 0
143  * Array do not include Chip ID, as codec driver does not use
144  * registers read operations at all
145  */
146 static const struct reg_default cs4271_reg_defaults[] = {
147         { CS4271_MODE1,         0, },
148         { CS4271_DACCTL,        CS4271_DACCTL_AMUTE, },
149         { CS4271_DACVOL,        CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, },
150         { CS4271_VOLA,          0, },
151         { CS4271_VOLB,          0, },
152         { CS4271_ADCCTL,        0, },
153         { CS4271_MODE2,         0, },
154 };
155 
156 static bool cs4271_volatile_reg(struct device *dev, unsigned int reg)
157 {
158         return reg == CS4271_CHIPID;
159 }
160 
161 struct cs4271_private {
162         /* SND_SOC_I2C or SND_SOC_SPI */
163         unsigned int                    mclk;
164         bool                            master;
165         bool                            deemph;
166         struct regmap                   *regmap;
167         /* Current sample rate for de-emphasis control */
168         int                             rate;
169         /* GPIO driving Reset pin, if any */
170         int                             gpio_nreset;
171         /* GPIO that disable serial bus, if any */
172         int                             gpio_disable;
173         /* enable soft reset workaround */
174         bool                            enable_soft_reset;
175 };
176 
177 static const struct snd_soc_dapm_widget cs4271_dapm_widgets[] = {
178 SND_SOC_DAPM_INPUT("AINA"),
179 SND_SOC_DAPM_INPUT("AINB"),
180 
181 SND_SOC_DAPM_OUTPUT("AOUTA+"),
182 SND_SOC_DAPM_OUTPUT("AOUTA-"),
183 SND_SOC_DAPM_OUTPUT("AOUTB+"),
184 SND_SOC_DAPM_OUTPUT("AOUTB-"),
185 };
186 
187 static const struct snd_soc_dapm_route cs4271_dapm_routes[] = {
188         { "Capture", NULL, "AINA" },
189         { "Capture", NULL, "AINB" },
190 
191         { "AOUTA+", NULL, "Playback" },
192         { "AOUTA-", NULL, "Playback" },
193         { "AOUTB+", NULL, "Playback" },
194         { "AOUTB-", NULL, "Playback" },
195 };
196 
197 /*
198  * @freq is the desired MCLK rate
199  * MCLK rate should (c) be the sample rate, multiplied by one of the
200  * ratios listed in cs4271_mclk_fs_ratios table
201  */
202 static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai,
203                                  int clk_id, unsigned int freq, int dir)
204 {
205         struct snd_soc_codec *codec = codec_dai->codec;
206         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
207 
208         cs4271->mclk = freq;
209         return 0;
210 }
211 
212 static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai,
213                               unsigned int format)
214 {
215         struct snd_soc_codec *codec = codec_dai->codec;
216         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
217         unsigned int val = 0;
218         int ret;
219 
220         switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
221         case SND_SOC_DAIFMT_CBS_CFS:
222                 cs4271->master = 0;
223                 break;
224         case SND_SOC_DAIFMT_CBM_CFM:
225                 cs4271->master = 1;
226                 val |= CS4271_MODE1_MASTER;
227                 break;
228         default:
229                 dev_err(codec->dev, "Invalid DAI format\n");
230                 return -EINVAL;
231         }
232 
233         switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
234         case SND_SOC_DAIFMT_LEFT_J:
235                 val |= CS4271_MODE1_DAC_DIF_LJ;
236                 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
237                         CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ);
238                 if (ret < 0)
239                         return ret;
240                 break;
241         case SND_SOC_DAIFMT_I2S:
242                 val |= CS4271_MODE1_DAC_DIF_I2S;
243                 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
244                         CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S);
245                 if (ret < 0)
246                         return ret;
247                 break;
248         default:
249                 dev_err(codec->dev, "Invalid DAI format\n");
250                 return -EINVAL;
251         }
252 
253         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
254                 CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val);
255         if (ret < 0)
256                 return ret;
257         return 0;
258 }
259 
260 static int cs4271_deemph[] = {0, 44100, 48000, 32000};
261 
262 static int cs4271_set_deemph(struct snd_soc_codec *codec)
263 {
264         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
265         int i, ret;
266         int val = CS4271_DACCTL_DEM_DIS;
267 
268         if (cs4271->deemph) {
269                 /* Find closest de-emphasis freq */
270                 val = 1;
271                 for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++)
272                         if (abs(cs4271_deemph[i] - cs4271->rate) <
273                             abs(cs4271_deemph[val] - cs4271->rate))
274                                 val = i;
275                 val <<= 4;
276         }
277 
278         ret = regmap_update_bits(cs4271->regmap, CS4271_DACCTL,
279                 CS4271_DACCTL_DEM_MASK, val);
280         if (ret < 0)
281                 return ret;
282         return 0;
283 }
284 
285 static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
286                              struct snd_ctl_elem_value *ucontrol)
287 {
288         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
289         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
290 
291         ucontrol->value.enumerated.item[0] = cs4271->deemph;
292         return 0;
293 }
294 
295 static int cs4271_put_deemph(struct snd_kcontrol *kcontrol,
296                              struct snd_ctl_elem_value *ucontrol)
297 {
298         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
299         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
300 
301         cs4271->deemph = ucontrol->value.enumerated.item[0];
302         return cs4271_set_deemph(codec);
303 }
304 
305 struct cs4271_clk_cfg {
306         bool            master;         /* codec mode */
307         u8              speed_mode;     /* codec speed mode: 1x, 2x, 4x */
308         unsigned short  ratio;          /* MCLK / sample rate */
309         u8              ratio_mask;     /* ratio bit mask for Master mode */
310 };
311 
312 static struct cs4271_clk_cfg cs4271_clk_tab[] = {
313         {1, CS4271_MODE1_MODE_1X, 256,  CS4271_MODE1_DIV_1},
314         {1, CS4271_MODE1_MODE_1X, 384,  CS4271_MODE1_DIV_15},
315         {1, CS4271_MODE1_MODE_1X, 512,  CS4271_MODE1_DIV_2},
316         {1, CS4271_MODE1_MODE_1X, 768,  CS4271_MODE1_DIV_3},
317         {1, CS4271_MODE1_MODE_2X, 128,  CS4271_MODE1_DIV_1},
318         {1, CS4271_MODE1_MODE_2X, 192,  CS4271_MODE1_DIV_15},
319         {1, CS4271_MODE1_MODE_2X, 256,  CS4271_MODE1_DIV_2},
320         {1, CS4271_MODE1_MODE_2X, 384,  CS4271_MODE1_DIV_3},
321         {1, CS4271_MODE1_MODE_4X, 64,   CS4271_MODE1_DIV_1},
322         {1, CS4271_MODE1_MODE_4X, 96,   CS4271_MODE1_DIV_15},
323         {1, CS4271_MODE1_MODE_4X, 128,  CS4271_MODE1_DIV_2},
324         {1, CS4271_MODE1_MODE_4X, 192,  CS4271_MODE1_DIV_3},
325         {0, CS4271_MODE1_MODE_1X, 256,  CS4271_MODE1_DIV_1},
326         {0, CS4271_MODE1_MODE_1X, 384,  CS4271_MODE1_DIV_1},
327         {0, CS4271_MODE1_MODE_1X, 512,  CS4271_MODE1_DIV_1},
328         {0, CS4271_MODE1_MODE_1X, 768,  CS4271_MODE1_DIV_2},
329         {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2},
330         {0, CS4271_MODE1_MODE_2X, 128,  CS4271_MODE1_DIV_1},
331         {0, CS4271_MODE1_MODE_2X, 192,  CS4271_MODE1_DIV_1},
332         {0, CS4271_MODE1_MODE_2X, 256,  CS4271_MODE1_DIV_1},
333         {0, CS4271_MODE1_MODE_2X, 384,  CS4271_MODE1_DIV_2},
334         {0, CS4271_MODE1_MODE_2X, 512,  CS4271_MODE1_DIV_2},
335         {0, CS4271_MODE1_MODE_4X, 64,   CS4271_MODE1_DIV_1},
336         {0, CS4271_MODE1_MODE_4X, 96,   CS4271_MODE1_DIV_1},
337         {0, CS4271_MODE1_MODE_4X, 128,  CS4271_MODE1_DIV_1},
338         {0, CS4271_MODE1_MODE_4X, 192,  CS4271_MODE1_DIV_2},
339         {0, CS4271_MODE1_MODE_4X, 256,  CS4271_MODE1_DIV_2},
340 };
341 
342 #define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab)
343 
344 static int cs4271_hw_params(struct snd_pcm_substream *substream,
345                             struct snd_pcm_hw_params *params,
346                             struct snd_soc_dai *dai)
347 {
348         struct snd_soc_codec *codec = dai->codec;
349         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
350         int i, ret;
351         unsigned int ratio, val;
352 
353         if (cs4271->enable_soft_reset) {
354                 /*
355                  * Put the codec in soft reset and back again in case it's not
356                  * currently streaming data. This way of bringing the codec in
357                  * sync to the current clocks is not explicitly documented in
358                  * the data sheet, but it seems to work fine, and in contrast
359                  * to a read hardware reset, we don't have to sync back all
360                  * registers every time.
361                  */
362 
363                 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
364                      !dai->capture_active) ||
365                     (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
366                      !dai->playback_active)) {
367                         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
368                                                  CS4271_MODE2_PDN,
369                                                  CS4271_MODE2_PDN);
370                         if (ret < 0)
371                                 return ret;
372 
373                         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
374                                                  CS4271_MODE2_PDN, 0);
375                         if (ret < 0)
376                                 return ret;
377                 }
378         }
379 
380         cs4271->rate = params_rate(params);
381 
382         /* Configure DAC */
383         if (cs4271->rate < 50000)
384                 val = CS4271_MODE1_MODE_1X;
385         else if (cs4271->rate < 100000)
386                 val = CS4271_MODE1_MODE_2X;
387         else
388                 val = CS4271_MODE1_MODE_4X;
389 
390         ratio = cs4271->mclk / cs4271->rate;
391         for (i = 0; i < CS4171_NR_RATIOS; i++)
392                 if ((cs4271_clk_tab[i].master == cs4271->master) &&
393                     (cs4271_clk_tab[i].speed_mode == val) &&
394                     (cs4271_clk_tab[i].ratio == ratio))
395                         break;
396 
397         if (i == CS4171_NR_RATIOS) {
398                 dev_err(codec->dev, "Invalid sample rate\n");
399                 return -EINVAL;
400         }
401 
402         val |= cs4271_clk_tab[i].ratio_mask;
403 
404         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
405                 CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val);
406         if (ret < 0)
407                 return ret;
408 
409         return cs4271_set_deemph(codec);
410 }
411 
412 static int cs4271_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
413 {
414         struct snd_soc_codec *codec = dai->codec;
415         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
416         int ret;
417         int val_a = 0;
418         int val_b = 0;
419 
420         if (stream != SNDRV_PCM_STREAM_PLAYBACK)
421                 return 0;
422 
423         if (mute) {
424                 val_a = CS4271_VOLA_MUTE;
425                 val_b = CS4271_VOLB_MUTE;
426         }
427 
428         ret = regmap_update_bits(cs4271->regmap, CS4271_VOLA,
429                                  CS4271_VOLA_MUTE, val_a);
430         if (ret < 0)
431                 return ret;
432 
433         ret = regmap_update_bits(cs4271->regmap, CS4271_VOLB,
434                                  CS4271_VOLB_MUTE, val_b);
435         if (ret < 0)
436                 return ret;
437 
438         return 0;
439 }
440 
441 /* CS4271 controls */
442 static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0);
443 
444 static const struct snd_kcontrol_new cs4271_snd_controls[] = {
445         SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB,
446                 0, 0x7F, 1, cs4271_dac_tlv),
447         SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0),
448         SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0),
449         SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0),
450         SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
451                 cs4271_get_deemph, cs4271_put_deemph),
452         SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0),
453         SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0),
454         SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0),
455         SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0),
456         SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0),
457         SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0),
458         SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1),
459         SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0),
460         SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1),
461         SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB,
462                 7, 1, 1),
463 };
464 
465 static const struct snd_soc_dai_ops cs4271_dai_ops = {
466         .hw_params      = cs4271_hw_params,
467         .set_sysclk     = cs4271_set_dai_sysclk,
468         .set_fmt        = cs4271_set_dai_fmt,
469         .mute_stream    = cs4271_mute_stream,
470 };
471 
472 static struct snd_soc_dai_driver cs4271_dai = {
473         .name = "cs4271-hifi",
474         .playback = {
475                 .stream_name    = "Playback",
476                 .channels_min   = 2,
477                 .channels_max   = 2,
478                 .rates          = CS4271_PCM_RATES,
479                 .formats        = CS4271_PCM_FORMATS,
480         },
481         .capture = {
482                 .stream_name    = "Capture",
483                 .channels_min   = 2,
484                 .channels_max   = 2,
485                 .rates          = CS4271_PCM_RATES,
486                 .formats        = CS4271_PCM_FORMATS,
487         },
488         .ops = &cs4271_dai_ops,
489         .symmetric_rates = 1,
490 };
491 
492 #ifdef CONFIG_PM
493 static int cs4271_soc_suspend(struct snd_soc_codec *codec)
494 {
495         int ret;
496         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
497 
498         /* Set power-down bit */
499         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
500                                  CS4271_MODE2_PDN, CS4271_MODE2_PDN);
501         if (ret < 0)
502                 return ret;
503 
504         return 0;
505 }
506 
507 static int cs4271_soc_resume(struct snd_soc_codec *codec)
508 {
509         int ret;
510         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
511 
512         /* Restore codec state */
513         ret = regcache_sync(cs4271->regmap);
514         if (ret < 0)
515                 return ret;
516 
517         /* then disable the power-down bit */
518         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
519                                  CS4271_MODE2_PDN, 0);
520         if (ret < 0)
521                 return ret;
522 
523         return 0;
524 }
525 #else
526 #define cs4271_soc_suspend      NULL
527 #define cs4271_soc_resume       NULL
528 #endif /* CONFIG_PM */
529 
530 #ifdef CONFIG_OF
531 static const struct of_device_id cs4271_dt_ids[] = {
532         { .compatible = "cirrus,cs4271", },
533         { }
534 };
535 MODULE_DEVICE_TABLE(of, cs4271_dt_ids);
536 #endif
537 
538 static int cs4271_probe(struct snd_soc_codec *codec)
539 {
540         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
541         struct cs4271_platform_data *cs4271plat = codec->dev->platform_data;
542         int ret;
543         int gpio_nreset = -EINVAL;
544         bool amutec_eq_bmutec = false;
545 
546 #ifdef CONFIG_OF
547         if (of_match_device(cs4271_dt_ids, codec->dev)) {
548                 gpio_nreset = of_get_named_gpio(codec->dev->of_node,
549                                                 "reset-gpio", 0);
550 
551                 if (of_get_property(codec->dev->of_node,
552                                      "cirrus,amutec-eq-bmutec", NULL))
553                         amutec_eq_bmutec = true;
554 
555                 if (of_get_property(codec->dev->of_node,
556                                      "cirrus,enable-soft-reset", NULL))
557                         cs4271->enable_soft_reset = true;
558         }
559 #endif
560 
561         if (cs4271plat) {
562                 if (gpio_is_valid(cs4271plat->gpio_nreset))
563                         gpio_nreset = cs4271plat->gpio_nreset;
564 
565                 amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec;
566                 cs4271->enable_soft_reset = cs4271plat->enable_soft_reset;
567         }
568 
569         if (gpio_nreset >= 0)
570                 if (devm_gpio_request(codec->dev, gpio_nreset, "CS4271 Reset"))
571                         gpio_nreset = -EINVAL;
572         if (gpio_nreset >= 0) {
573                 /* Reset codec */
574                 gpio_direction_output(gpio_nreset, 0);
575                 udelay(1);
576                 gpio_set_value(gpio_nreset, 1);
577                 /* Give the codec time to wake up */
578                 udelay(1);
579         }
580 
581         cs4271->gpio_nreset = gpio_nreset;
582 
583         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
584                                  CS4271_MODE2_PDN | CS4271_MODE2_CPEN,
585                                  CS4271_MODE2_PDN | CS4271_MODE2_CPEN);
586         if (ret < 0)
587                 return ret;
588         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
589                                  CS4271_MODE2_PDN, 0);
590         if (ret < 0)
591                 return ret;
592         /* Power-up sequence requires 85 uS */
593         udelay(85);
594 
595         if (amutec_eq_bmutec)
596                 regmap_update_bits(cs4271->regmap, CS4271_MODE2,
597                                    CS4271_MODE2_MUTECAEQUB,
598                                    CS4271_MODE2_MUTECAEQUB);
599 
600         return 0;
601 }
602 
603 static int cs4271_remove(struct snd_soc_codec *codec)
604 {
605         struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
606 
607         if (gpio_is_valid(cs4271->gpio_nreset))
608                 /* Set codec to the reset state */
609                 gpio_set_value(cs4271->gpio_nreset, 0);
610 
611         return 0;
612 };
613 
614 static struct snd_soc_codec_driver soc_codec_dev_cs4271 = {
615         .probe                  = cs4271_probe,
616         .remove                 = cs4271_remove,
617         .suspend                = cs4271_soc_suspend,
618         .resume                 = cs4271_soc_resume,
619 
620         .controls               = cs4271_snd_controls,
621         .num_controls           = ARRAY_SIZE(cs4271_snd_controls),
622         .dapm_widgets           = cs4271_dapm_widgets,
623         .num_dapm_widgets       = ARRAY_SIZE(cs4271_dapm_widgets),
624         .dapm_routes            = cs4271_dapm_routes,
625         .num_dapm_routes        = ARRAY_SIZE(cs4271_dapm_routes),
626 };
627 
628 #if defined(CONFIG_SPI_MASTER)
629 
630 static const struct regmap_config cs4271_spi_regmap = {
631         .reg_bits = 16,
632         .val_bits = 8,
633         .max_register = CS4271_LASTREG,
634         .read_flag_mask = 0x21,
635         .write_flag_mask = 0x20,
636 
637         .reg_defaults = cs4271_reg_defaults,
638         .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults),
639         .cache_type = REGCACHE_RBTREE,
640 
641         .volatile_reg = cs4271_volatile_reg,
642 };
643 
644 static int cs4271_spi_probe(struct spi_device *spi)
645 {
646         struct cs4271_private *cs4271;
647 
648         cs4271 = devm_kzalloc(&spi->dev, sizeof(*cs4271), GFP_KERNEL);
649         if (!cs4271)
650                 return -ENOMEM;
651 
652         spi_set_drvdata(spi, cs4271);
653         cs4271->regmap = devm_regmap_init_spi(spi, &cs4271_spi_regmap);
654         if (IS_ERR(cs4271->regmap))
655                 return PTR_ERR(cs4271->regmap);
656 
657         return snd_soc_register_codec(&spi->dev, &soc_codec_dev_cs4271,
658                 &cs4271_dai, 1);
659 }
660 
661 static int cs4271_spi_remove(struct spi_device *spi)
662 {
663         snd_soc_unregister_codec(&spi->dev);
664         return 0;
665 }
666 
667 static struct spi_driver cs4271_spi_driver = {
668         .driver = {
669                 .name   = "cs4271",
670                 .owner  = THIS_MODULE,
671                 .of_match_table = of_match_ptr(cs4271_dt_ids),
672         },
673         .probe          = cs4271_spi_probe,
674         .remove         = cs4271_spi_remove,
675 };
676 #endif /* defined(CONFIG_SPI_MASTER) */
677 
678 #if IS_ENABLED(CONFIG_I2C)
679 static const struct i2c_device_id cs4271_i2c_id[] = {
680         {"cs4271", 0},
681         {}
682 };
683 MODULE_DEVICE_TABLE(i2c, cs4271_i2c_id);
684 
685 static const struct regmap_config cs4271_i2c_regmap = {
686         .reg_bits = 8,
687         .val_bits = 8,
688         .max_register = CS4271_LASTREG,
689 
690         .reg_defaults = cs4271_reg_defaults,
691         .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults),
692         .cache_type = REGCACHE_RBTREE,
693 
694         .volatile_reg = cs4271_volatile_reg,
695 };
696 
697 static int cs4271_i2c_probe(struct i2c_client *client,
698                             const struct i2c_device_id *id)
699 {
700         struct cs4271_private *cs4271;
701 
702         cs4271 = devm_kzalloc(&client->dev, sizeof(*cs4271), GFP_KERNEL);
703         if (!cs4271)
704                 return -ENOMEM;
705 
706         i2c_set_clientdata(client, cs4271);
707         cs4271->regmap = devm_regmap_init_i2c(client, &cs4271_i2c_regmap);
708         if (IS_ERR(cs4271->regmap))
709                 return PTR_ERR(cs4271->regmap);
710 
711         return snd_soc_register_codec(&client->dev, &soc_codec_dev_cs4271,
712                 &cs4271_dai, 1);
713 }
714 
715 static int cs4271_i2c_remove(struct i2c_client *client)
716 {
717         snd_soc_unregister_codec(&client->dev);
718         return 0;
719 }
720 
721 static struct i2c_driver cs4271_i2c_driver = {
722         .driver = {
723                 .name   = "cs4271",
724                 .owner  = THIS_MODULE,
725                 .of_match_table = of_match_ptr(cs4271_dt_ids),
726         },
727         .id_table       = cs4271_i2c_id,
728         .probe          = cs4271_i2c_probe,
729         .remove         = cs4271_i2c_remove,
730 };
731 #endif /* IS_ENABLED(CONFIG_I2C) */
732 
733 /*
734  * We only register our serial bus driver here without
735  * assignment to particular chip. So if any of the below
736  * fails, there is some problem with I2C or SPI subsystem.
737  * In most cases this module will be compiled with support
738  * of only one serial bus.
739  */
740 static int __init cs4271_modinit(void)
741 {
742         int ret;
743 
744 #if IS_ENABLED(CONFIG_I2C)
745         ret = i2c_add_driver(&cs4271_i2c_driver);
746         if (ret) {
747                 pr_err("Failed to register CS4271 I2C driver: %d\n", ret);
748                 return ret;
749         }
750 #endif
751 
752 #if defined(CONFIG_SPI_MASTER)
753         ret = spi_register_driver(&cs4271_spi_driver);
754         if (ret) {
755                 pr_err("Failed to register CS4271 SPI driver: %d\n", ret);
756                 return ret;
757         }
758 #endif
759 
760         return 0;
761 }
762 module_init(cs4271_modinit);
763 
764 static void __exit cs4271_modexit(void)
765 {
766 #if defined(CONFIG_SPI_MASTER)
767         spi_unregister_driver(&cs4271_spi_driver);
768 #endif
769 
770 #if IS_ENABLED(CONFIG_I2C)
771         i2c_del_driver(&cs4271_i2c_driver);
772 #endif
773 }
774 module_exit(cs4271_modexit);
775 
776 MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
777 MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver");
778 MODULE_LICENSE("GPL");
779 

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