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Linux/sound/soc/atmel/atmel_ssc_dai.c

  1 /*
  2  * atmel_ssc_dai.c  --  ALSA SoC ATMEL SSC Audio Layer Platform driver
  3  *
  4  * Copyright (C) 2005 SAN People
  5  * Copyright (C) 2008 Atmel
  6  *
  7  * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
  8  *         ATMEL CORP.
  9  *
 10  * Based on at91-ssc.c by
 11  * Frank Mandarino <fmandarino@endrelia.com>
 12  * Based on pxa2xx Platform drivers by
 13  * Liam Girdwood <lrg@slimlogic.co.uk>
 14  *
 15  * This program is free software; you can redistribute it and/or modify
 16  * it under the terms of the GNU General Public License as published by
 17  * the Free Software Foundation; either version 2 of the License, or
 18  * (at your option) any later version.
 19  *
 20  * This program is distributed in the hope that it will be useful,
 21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 23  * GNU General Public License for more details.
 24  *
 25  * You should have received a copy of the GNU General Public License
 26  * along with this program; if not, write to the Free Software
 27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 28  */
 29 
 30 #include <linux/init.h>
 31 #include <linux/module.h>
 32 #include <linux/interrupt.h>
 33 #include <linux/device.h>
 34 #include <linux/delay.h>
 35 #include <linux/clk.h>
 36 #include <linux/atmel_pdc.h>
 37 
 38 #include <linux/atmel-ssc.h>
 39 #include <sound/core.h>
 40 #include <sound/pcm.h>
 41 #include <sound/pcm_params.h>
 42 #include <sound/initval.h>
 43 #include <sound/soc.h>
 44 
 45 #include "atmel-pcm.h"
 46 #include "atmel_ssc_dai.h"
 47 
 48 
 49 #define NUM_SSC_DEVICES         3
 50 
 51 /*
 52  * SSC PDC registers required by the PCM DMA engine.
 53  */
 54 static struct atmel_pdc_regs pdc_tx_reg = {
 55         .xpr            = ATMEL_PDC_TPR,
 56         .xcr            = ATMEL_PDC_TCR,
 57         .xnpr           = ATMEL_PDC_TNPR,
 58         .xncr           = ATMEL_PDC_TNCR,
 59 };
 60 
 61 static struct atmel_pdc_regs pdc_rx_reg = {
 62         .xpr            = ATMEL_PDC_RPR,
 63         .xcr            = ATMEL_PDC_RCR,
 64         .xnpr           = ATMEL_PDC_RNPR,
 65         .xncr           = ATMEL_PDC_RNCR,
 66 };
 67 
 68 /*
 69  * SSC & PDC status bits for transmit and receive.
 70  */
 71 static struct atmel_ssc_mask ssc_tx_mask = {
 72         .ssc_enable     = SSC_BIT(CR_TXEN),
 73         .ssc_disable    = SSC_BIT(CR_TXDIS),
 74         .ssc_endx       = SSC_BIT(SR_ENDTX),
 75         .ssc_endbuf     = SSC_BIT(SR_TXBUFE),
 76         .ssc_error      = SSC_BIT(SR_OVRUN),
 77         .pdc_enable     = ATMEL_PDC_TXTEN,
 78         .pdc_disable    = ATMEL_PDC_TXTDIS,
 79 };
 80 
 81 static struct atmel_ssc_mask ssc_rx_mask = {
 82         .ssc_enable     = SSC_BIT(CR_RXEN),
 83         .ssc_disable    = SSC_BIT(CR_RXDIS),
 84         .ssc_endx       = SSC_BIT(SR_ENDRX),
 85         .ssc_endbuf     = SSC_BIT(SR_RXBUFF),
 86         .ssc_error      = SSC_BIT(SR_OVRUN),
 87         .pdc_enable     = ATMEL_PDC_RXTEN,
 88         .pdc_disable    = ATMEL_PDC_RXTDIS,
 89 };
 90 
 91 
 92 /*
 93  * DMA parameters.
 94  */
 95 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
 96         {{
 97         .name           = "SSC0 PCM out",
 98         .pdc            = &pdc_tx_reg,
 99         .mask           = &ssc_tx_mask,
100         },
101         {
102         .name           = "SSC0 PCM in",
103         .pdc            = &pdc_rx_reg,
104         .mask           = &ssc_rx_mask,
105         } },
106         {{
107         .name           = "SSC1 PCM out",
108         .pdc            = &pdc_tx_reg,
109         .mask           = &ssc_tx_mask,
110         },
111         {
112         .name           = "SSC1 PCM in",
113         .pdc            = &pdc_rx_reg,
114         .mask           = &ssc_rx_mask,
115         } },
116         {{
117         .name           = "SSC2 PCM out",
118         .pdc            = &pdc_tx_reg,
119         .mask           = &ssc_tx_mask,
120         },
121         {
122         .name           = "SSC2 PCM in",
123         .pdc            = &pdc_rx_reg,
124         .mask           = &ssc_rx_mask,
125         } },
126 };
127 
128 
129 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
130         {
131         .name           = "ssc0",
132         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
133         .dir_mask       = SSC_DIR_MASK_UNUSED,
134         .initialized    = 0,
135         },
136         {
137         .name           = "ssc1",
138         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
139         .dir_mask       = SSC_DIR_MASK_UNUSED,
140         .initialized    = 0,
141         },
142         {
143         .name           = "ssc2",
144         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
145         .dir_mask       = SSC_DIR_MASK_UNUSED,
146         .initialized    = 0,
147         },
148 };
149 
150 
151 /*
152  * SSC interrupt handler.  Passes PDC interrupts to the DMA
153  * interrupt handler in the PCM driver.
154  */
155 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
156 {
157         struct atmel_ssc_info *ssc_p = dev_id;
158         struct atmel_pcm_dma_params *dma_params;
159         u32 ssc_sr;
160         u32 ssc_substream_mask;
161         int i;
162 
163         ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
164                         & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
165 
166         /*
167          * Loop through the substreams attached to this SSC.  If
168          * a DMA-related interrupt occurred on that substream, call
169          * the DMA interrupt handler function, if one has been
170          * registered in the dma_params structure by the PCM driver.
171          */
172         for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
173                 dma_params = ssc_p->dma_params[i];
174 
175                 if ((dma_params != NULL) &&
176                         (dma_params->dma_intr_handler != NULL)) {
177                         ssc_substream_mask = (dma_params->mask->ssc_endx |
178                                         dma_params->mask->ssc_endbuf);
179                         if (ssc_sr & ssc_substream_mask) {
180                                 dma_params->dma_intr_handler(ssc_sr,
181                                                 dma_params->
182                                                 substream);
183                         }
184                 }
185         }
186 
187         return IRQ_HANDLED;
188 }
189 
190 /*
191  * When the bit clock is input, limit the maximum rate according to the
192  * Serial Clock Ratio Considerations section from the SSC documentation:
193  *
194  *   The Transmitter and the Receiver can be programmed to operate
195  *   with the clock signals provided on either the TK or RK pins.
196  *   This allows the SSC to support many slave-mode data transfers.
197  *   In this case, the maximum clock speed allowed on the RK pin is:
198  *   - Peripheral clock divided by 2 if Receiver Frame Synchro is input
199  *   - Peripheral clock divided by 3 if Receiver Frame Synchro is output
200  *   In addition, the maximum clock speed allowed on the TK pin is:
201  *   - Peripheral clock divided by 6 if Transmit Frame Synchro is input
202  *   - Peripheral clock divided by 2 if Transmit Frame Synchro is output
203  *
204  * When the bit clock is output, limit the rate according to the
205  * SSC divider restrictions.
206  */
207 static int atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params *params,
208                                   struct snd_pcm_hw_rule *rule)
209 {
210         struct atmel_ssc_info *ssc_p = rule->private;
211         struct ssc_device *ssc = ssc_p->ssc;
212         struct snd_interval *i = hw_param_interval(params, rule->var);
213         struct snd_interval t;
214         struct snd_ratnum r = {
215                 .den_min = 1,
216                 .den_max = 4095,
217                 .den_step = 1,
218         };
219         unsigned int num = 0, den = 0;
220         int frame_size;
221         int mck_div = 2;
222         int ret;
223 
224         frame_size = snd_soc_params_to_frame_size(params);
225         if (frame_size < 0)
226                 return frame_size;
227 
228         switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
229         case SND_SOC_DAIFMT_CBM_CFS:
230                 if ((ssc_p->dir_mask & SSC_DIR_MASK_CAPTURE)
231                     && ssc->clk_from_rk_pin)
232                         /* Receiver Frame Synchro (i.e. capture)
233                          * is output (format is _CFS) and the RK pin
234                          * is used for input (format is _CBM_).
235                          */
236                         mck_div = 3;
237                 break;
238 
239         case SND_SOC_DAIFMT_CBM_CFM:
240                 if ((ssc_p->dir_mask & SSC_DIR_MASK_PLAYBACK)
241                     && !ssc->clk_from_rk_pin)
242                         /* Transmit Frame Synchro (i.e. playback)
243                          * is input (format is _CFM) and the TK pin
244                          * is used for input (format _CBM_ but not
245                          * using the RK pin).
246                          */
247                         mck_div = 6;
248                 break;
249         }
250 
251         switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
252         case SND_SOC_DAIFMT_CBS_CFS:
253                 r.num = ssc_p->mck_rate / mck_div / frame_size;
254 
255                 ret = snd_interval_ratnum(i, 1, &r, &num, &den);
256                 if (ret >= 0 && den && rule->var == SNDRV_PCM_HW_PARAM_RATE) {
257                         params->rate_num = num;
258                         params->rate_den = den;
259                 }
260                 break;
261 
262         case SND_SOC_DAIFMT_CBM_CFS:
263         case SND_SOC_DAIFMT_CBM_CFM:
264                 t.min = 8000;
265                 t.max = ssc_p->mck_rate / mck_div / frame_size;
266                 t.openmin = t.openmax = 0;
267                 t.integer = 0;
268                 ret = snd_interval_refine(i, &t);
269                 break;
270 
271         default:
272                 ret = -EINVAL;
273                 break;
274         }
275 
276         return ret;
277 }
278 
279 /*-------------------------------------------------------------------------*\
280  * DAI functions
281 \*-------------------------------------------------------------------------*/
282 /*
283  * Startup.  Only that one substream allowed in each direction.
284  */
285 static int atmel_ssc_startup(struct snd_pcm_substream *substream,
286                              struct snd_soc_dai *dai)
287 {
288         struct platform_device *pdev = to_platform_device(dai->dev);
289         struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
290         struct atmel_pcm_dma_params *dma_params;
291         int dir, dir_mask;
292         int ret;
293 
294         pr_debug("atmel_ssc_startup: SSC_SR=0x%x\n",
295                 ssc_readl(ssc_p->ssc->regs, SR));
296 
297         /* Enable PMC peripheral clock for this SSC */
298         pr_debug("atmel_ssc_dai: Starting clock\n");
299         clk_enable(ssc_p->ssc->clk);
300         ssc_p->mck_rate = clk_get_rate(ssc_p->ssc->clk);
301 
302         /* Reset the SSC to keep it at a clean status */
303         ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
304 
305         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
306                 dir = 0;
307                 dir_mask = SSC_DIR_MASK_PLAYBACK;
308         } else {
309                 dir = 1;
310                 dir_mask = SSC_DIR_MASK_CAPTURE;
311         }
312 
313         ret = snd_pcm_hw_rule_add(substream->runtime, 0,
314                                   SNDRV_PCM_HW_PARAM_RATE,
315                                   atmel_ssc_hw_rule_rate,
316                                   ssc_p,
317                                   SNDRV_PCM_HW_PARAM_FRAME_BITS,
318                                   SNDRV_PCM_HW_PARAM_CHANNELS, -1);
319         if (ret < 0) {
320                 dev_err(dai->dev, "Failed to specify rate rule: %d\n", ret);
321                 return ret;
322         }
323 
324         dma_params = &ssc_dma_params[dai->id][dir];
325         dma_params->ssc = ssc_p->ssc;
326         dma_params->substream = substream;
327 
328         ssc_p->dma_params[dir] = dma_params;
329 
330         snd_soc_dai_set_dma_data(dai, substream, dma_params);
331 
332         spin_lock_irq(&ssc_p->lock);
333         if (ssc_p->dir_mask & dir_mask) {
334                 spin_unlock_irq(&ssc_p->lock);
335                 return -EBUSY;
336         }
337         ssc_p->dir_mask |= dir_mask;
338         spin_unlock_irq(&ssc_p->lock);
339 
340         return 0;
341 }
342 
343 /*
344  * Shutdown.  Clear DMA parameters and shutdown the SSC if there
345  * are no other substreams open.
346  */
347 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
348                                struct snd_soc_dai *dai)
349 {
350         struct platform_device *pdev = to_platform_device(dai->dev);
351         struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
352         struct atmel_pcm_dma_params *dma_params;
353         int dir, dir_mask;
354 
355         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
356                 dir = 0;
357         else
358                 dir = 1;
359 
360         dma_params = ssc_p->dma_params[dir];
361 
362         if (dma_params != NULL) {
363                 dma_params->ssc = NULL;
364                 dma_params->substream = NULL;
365                 ssc_p->dma_params[dir] = NULL;
366         }
367 
368         dir_mask = 1 << dir;
369 
370         spin_lock_irq(&ssc_p->lock);
371         ssc_p->dir_mask &= ~dir_mask;
372         if (!ssc_p->dir_mask) {
373                 if (ssc_p->initialized) {
374                         free_irq(ssc_p->ssc->irq, ssc_p);
375                         ssc_p->initialized = 0;
376                 }
377 
378                 /* Reset the SSC */
379                 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
380                 /* Clear the SSC dividers */
381                 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
382         }
383         spin_unlock_irq(&ssc_p->lock);
384 
385         /* Shutdown the SSC clock. */
386         pr_debug("atmel_ssc_dai: Stopping clock\n");
387         clk_disable(ssc_p->ssc->clk);
388 }
389 
390 
391 /*
392  * Record the DAI format for use in hw_params().
393  */
394 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
395                 unsigned int fmt)
396 {
397         struct platform_device *pdev = to_platform_device(cpu_dai->dev);
398         struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
399 
400         ssc_p->daifmt = fmt;
401         return 0;
402 }
403 
404 /*
405  * Record SSC clock dividers for use in hw_params().
406  */
407 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
408         int div_id, int div)
409 {
410         struct platform_device *pdev = to_platform_device(cpu_dai->dev);
411         struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
412 
413         switch (div_id) {
414         case ATMEL_SSC_CMR_DIV:
415                 /*
416                  * The same master clock divider is used for both
417                  * transmit and receive, so if a value has already
418                  * been set, it must match this value.
419                  */
420                 if (ssc_p->dir_mask !=
421                         (SSC_DIR_MASK_PLAYBACK | SSC_DIR_MASK_CAPTURE))
422                         ssc_p->cmr_div = div;
423                 else if (ssc_p->cmr_div == 0)
424                         ssc_p->cmr_div = div;
425                 else
426                         if (div != ssc_p->cmr_div)
427                                 return -EBUSY;
428                 break;
429 
430         case ATMEL_SSC_TCMR_PERIOD:
431                 ssc_p->tcmr_period = div;
432                 break;
433 
434         case ATMEL_SSC_RCMR_PERIOD:
435                 ssc_p->rcmr_period = div;
436                 break;
437 
438         default:
439                 return -EINVAL;
440         }
441 
442         return 0;
443 }
444 
445 /*
446  * Configure the SSC.
447  */
448 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
449         struct snd_pcm_hw_params *params,
450         struct snd_soc_dai *dai)
451 {
452         struct platform_device *pdev = to_platform_device(dai->dev);
453         int id = pdev->id;
454         struct atmel_ssc_info *ssc_p = &ssc_info[id];
455         struct ssc_device *ssc = ssc_p->ssc;
456         struct atmel_pcm_dma_params *dma_params;
457         int dir, channels, bits;
458         u32 tfmr, rfmr, tcmr, rcmr;
459         int ret;
460         int fslen, fslen_ext;
461 
462         /*
463          * Currently, there is only one set of dma params for
464          * each direction.  If more are added, this code will
465          * have to be changed to select the proper set.
466          */
467         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
468                 dir = 0;
469         else
470                 dir = 1;
471 
472         dma_params = ssc_p->dma_params[dir];
473 
474         channels = params_channels(params);
475 
476         /*
477          * Determine sample size in bits and the PDC increment.
478          */
479         switch (params_format(params)) {
480         case SNDRV_PCM_FORMAT_S8:
481                 bits = 8;
482                 dma_params->pdc_xfer_size = 1;
483                 break;
484         case SNDRV_PCM_FORMAT_S16_LE:
485                 bits = 16;
486                 dma_params->pdc_xfer_size = 2;
487                 break;
488         case SNDRV_PCM_FORMAT_S24_LE:
489                 bits = 24;
490                 dma_params->pdc_xfer_size = 4;
491                 break;
492         case SNDRV_PCM_FORMAT_S32_LE:
493                 bits = 32;
494                 dma_params->pdc_xfer_size = 4;
495                 break;
496         default:
497                 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
498                 return -EINVAL;
499         }
500 
501         /*
502          * Compute SSC register settings.
503          */
504         switch (ssc_p->daifmt
505                 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
506 
507         case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
508                 /*
509                  * I2S format, SSC provides BCLK and LRC clocks.
510                  *
511                  * The SSC transmit and receive clocks are generated
512                  * from the MCK divider, and the BCLK signal
513                  * is output on the SSC TK line.
514                  */
515 
516                 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
517                         dev_err(dai->dev,
518                                 "sample size %d is too large for SSC device\n",
519                                 bits);
520                         return -EINVAL;
521                 }
522 
523                 fslen_ext = (bits - 1) / 16;
524                 fslen = (bits - 1) % 16;
525 
526                 rcmr =    SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
527                         | SSC_BF(RCMR_STTDLY, START_DELAY)
528                         | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
529                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
530                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
531                         | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
532 
533                 rfmr =    SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
534                         | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
535                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
536                         | SSC_BF(RFMR_FSLEN, fslen)
537                         | SSC_BF(RFMR_DATNB, (channels - 1))
538                         | SSC_BIT(RFMR_MSBF)
539                         | SSC_BF(RFMR_LOOP, 0)
540                         | SSC_BF(RFMR_DATLEN, (bits - 1));
541 
542                 tcmr =    SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
543                         | SSC_BF(TCMR_STTDLY, START_DELAY)
544                         | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
545                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
546                         | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
547                         | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
548 
549                 tfmr =    SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
550                         | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
551                         | SSC_BF(TFMR_FSDEN, 0)
552                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
553                         | SSC_BF(TFMR_FSLEN, fslen)
554                         | SSC_BF(TFMR_DATNB, (channels - 1))
555                         | SSC_BIT(TFMR_MSBF)
556                         | SSC_BF(TFMR_DATDEF, 0)
557                         | SSC_BF(TFMR_DATLEN, (bits - 1));
558                 break;
559 
560         case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
561                 /* I2S format, CODEC supplies BCLK and LRC clocks. */
562                 rcmr =    SSC_BF(RCMR_PERIOD, 0)
563                         | SSC_BF(RCMR_STTDLY, START_DELAY)
564                         | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
565                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
566                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
567                         | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
568                                            SSC_CKS_PIN : SSC_CKS_CLOCK);
569 
570                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
571                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
572                         | SSC_BF(RFMR_FSLEN, 0)
573                         | SSC_BF(RFMR_DATNB, (channels - 1))
574                         | SSC_BIT(RFMR_MSBF)
575                         | SSC_BF(RFMR_LOOP, 0)
576                         | SSC_BF(RFMR_DATLEN, (bits - 1));
577 
578                 tcmr =    SSC_BF(TCMR_PERIOD, 0)
579                         | SSC_BF(TCMR_STTDLY, START_DELAY)
580                         | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
581                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
582                         | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
583                         | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
584                                            SSC_CKS_CLOCK : SSC_CKS_PIN);
585 
586                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
587                         | SSC_BF(TFMR_FSDEN, 0)
588                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
589                         | SSC_BF(TFMR_FSLEN, 0)
590                         | SSC_BF(TFMR_DATNB, (channels - 1))
591                         | SSC_BIT(TFMR_MSBF)
592                         | SSC_BF(TFMR_DATDEF, 0)
593                         | SSC_BF(TFMR_DATLEN, (bits - 1));
594                 break;
595 
596         case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS:
597                 /* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */
598                 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
599                         dev_err(dai->dev,
600                                 "sample size %d is too large for SSC device\n",
601                                 bits);
602                         return -EINVAL;
603                 }
604 
605                 fslen_ext = (bits - 1) / 16;
606                 fslen = (bits - 1) % 16;
607 
608                 rcmr =    SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
609                         | SSC_BF(RCMR_STTDLY, START_DELAY)
610                         | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
611                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
612                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
613                         | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
614                                            SSC_CKS_PIN : SSC_CKS_CLOCK);
615 
616                 rfmr =    SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
617                         | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
618                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
619                         | SSC_BF(RFMR_FSLEN, fslen)
620                         | SSC_BF(RFMR_DATNB, (channels - 1))
621                         | SSC_BIT(RFMR_MSBF)
622                         | SSC_BF(RFMR_LOOP, 0)
623                         | SSC_BF(RFMR_DATLEN, (bits - 1));
624 
625                 tcmr =    SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
626                         | SSC_BF(TCMR_STTDLY, START_DELAY)
627                         | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
628                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
629                         | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
630                         | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
631                                            SSC_CKS_CLOCK : SSC_CKS_PIN);
632 
633                 tfmr =    SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
634                         | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE)
635                         | SSC_BF(TFMR_FSDEN, 0)
636                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
637                         | SSC_BF(TFMR_FSLEN, fslen)
638                         | SSC_BF(TFMR_DATNB, (channels - 1))
639                         | SSC_BIT(TFMR_MSBF)
640                         | SSC_BF(TFMR_DATDEF, 0)
641                         | SSC_BF(TFMR_DATLEN, (bits - 1));
642                 break;
643 
644         case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
645                 /*
646                  * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
647                  *
648                  * The SSC transmit and receive clocks are generated from the
649                  * MCK divider, and the BCLK signal is output
650                  * on the SSC TK line.
651                  */
652                 rcmr =    SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
653                         | SSC_BF(RCMR_STTDLY, 1)
654                         | SSC_BF(RCMR_START, SSC_START_RISING_RF)
655                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
656                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
657                         | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
658 
659                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
660                         | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
661                         | SSC_BF(RFMR_FSLEN, 0)
662                         | SSC_BF(RFMR_DATNB, (channels - 1))
663                         | SSC_BIT(RFMR_MSBF)
664                         | SSC_BF(RFMR_LOOP, 0)
665                         | SSC_BF(RFMR_DATLEN, (bits - 1));
666 
667                 tcmr =    SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
668                         | SSC_BF(TCMR_STTDLY, 1)
669                         | SSC_BF(TCMR_START, SSC_START_RISING_RF)
670                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
671                         | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
672                         | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
673 
674                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
675                         | SSC_BF(TFMR_FSDEN, 0)
676                         | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
677                         | SSC_BF(TFMR_FSLEN, 0)
678                         | SSC_BF(TFMR_DATNB, (channels - 1))
679                         | SSC_BIT(TFMR_MSBF)
680                         | SSC_BF(TFMR_DATDEF, 0)
681                         | SSC_BF(TFMR_DATLEN, (bits - 1));
682                 break;
683 
684         case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
685                 /*
686                  * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
687                  *
688                  * Data is transferred on first BCLK after LRC pulse rising
689                  * edge.If stereo, the right channel data is contiguous with
690                  * the left channel data.
691                  */
692                 rcmr =    SSC_BF(RCMR_PERIOD, 0)
693                         | SSC_BF(RCMR_STTDLY, START_DELAY)
694                         | SSC_BF(RCMR_START, SSC_START_RISING_RF)
695                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
696                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
697                         | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
698                                            SSC_CKS_PIN : SSC_CKS_CLOCK);
699 
700                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
701                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
702                         | SSC_BF(RFMR_FSLEN, 0)
703                         | SSC_BF(RFMR_DATNB, (channels - 1))
704                         | SSC_BIT(RFMR_MSBF)
705                         | SSC_BF(RFMR_LOOP, 0)
706                         | SSC_BF(RFMR_DATLEN, (bits - 1));
707 
708                 tcmr =    SSC_BF(TCMR_PERIOD, 0)
709                         | SSC_BF(TCMR_STTDLY, START_DELAY)
710                         | SSC_BF(TCMR_START, SSC_START_RISING_RF)
711                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
712                         | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
713                         | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
714                                            SSC_CKS_CLOCK : SSC_CKS_PIN);
715 
716                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
717                         | SSC_BF(TFMR_FSDEN, 0)
718                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
719                         | SSC_BF(TFMR_FSLEN, 0)
720                         | SSC_BF(TFMR_DATNB, (channels - 1))
721                         | SSC_BIT(TFMR_MSBF)
722                         | SSC_BF(TFMR_DATDEF, 0)
723                         | SSC_BF(TFMR_DATLEN, (bits - 1));
724                 break;
725 
726         default:
727                 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
728                         ssc_p->daifmt);
729                 return -EINVAL;
730         }
731         pr_debug("atmel_ssc_hw_params: "
732                         "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
733                         rcmr, rfmr, tcmr, tfmr);
734 
735         if (!ssc_p->initialized) {
736                 if (!ssc_p->ssc->pdata->use_dma) {
737                         ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
738                         ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
739                         ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
740                         ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
741 
742                         ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
743                         ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
744                         ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
745                         ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
746                 }
747 
748                 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
749                                 ssc_p->name, ssc_p);
750                 if (ret < 0) {
751                         printk(KERN_WARNING
752                                         "atmel_ssc_dai: request_irq failure\n");
753                         pr_debug("Atmel_ssc_dai: Stoping clock\n");
754                         clk_disable(ssc_p->ssc->clk);
755                         return ret;
756                 }
757 
758                 ssc_p->initialized = 1;
759         }
760 
761         /* set SSC clock mode register */
762         ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
763 
764         /* set receive clock mode and format */
765         ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
766         ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
767 
768         /* set transmit clock mode and format */
769         ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
770         ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
771 
772         pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
773         return 0;
774 }
775 
776 
777 static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
778                              struct snd_soc_dai *dai)
779 {
780         struct platform_device *pdev = to_platform_device(dai->dev);
781         struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
782         struct atmel_pcm_dma_params *dma_params;
783         int dir;
784 
785         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
786                 dir = 0;
787         else
788                 dir = 1;
789 
790         dma_params = ssc_p->dma_params[dir];
791 
792         ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
793         ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error);
794 
795         pr_debug("%s enabled SSC_SR=0x%08x\n",
796                         dir ? "receive" : "transmit",
797                         ssc_readl(ssc_p->ssc->regs, SR));
798         return 0;
799 }
800 
801 static int atmel_ssc_trigger(struct snd_pcm_substream *substream,
802                              int cmd, struct snd_soc_dai *dai)
803 {
804         struct platform_device *pdev = to_platform_device(dai->dev);
805         struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
806         struct atmel_pcm_dma_params *dma_params;
807         int dir;
808 
809         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
810                 dir = 0;
811         else
812                 dir = 1;
813 
814         dma_params = ssc_p->dma_params[dir];
815 
816         switch (cmd) {
817         case SNDRV_PCM_TRIGGER_START:
818         case SNDRV_PCM_TRIGGER_RESUME:
819         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
820                 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
821                 break;
822         default:
823                 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
824                 break;
825         }
826 
827         return 0;
828 }
829 
830 #ifdef CONFIG_PM
831 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
832 {
833         struct atmel_ssc_info *ssc_p;
834         struct platform_device *pdev = to_platform_device(cpu_dai->dev);
835 
836         if (!cpu_dai->active)
837                 return 0;
838 
839         ssc_p = &ssc_info[pdev->id];
840 
841         /* Save the status register before disabling transmit and receive */
842         ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
843         ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
844 
845         /* Save the current interrupt mask, then disable unmasked interrupts */
846         ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
847         ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
848 
849         ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
850         ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
851         ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
852         ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
853         ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
854 
855         return 0;
856 }
857 
858 
859 
860 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
861 {
862         struct atmel_ssc_info *ssc_p;
863         struct platform_device *pdev = to_platform_device(cpu_dai->dev);
864         u32 cr;
865 
866         if (!cpu_dai->active)
867                 return 0;
868 
869         ssc_p = &ssc_info[pdev->id];
870 
871         /* restore SSC register settings */
872         ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
873         ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
874         ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
875         ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
876         ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
877 
878         /* re-enable interrupts */
879         ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
880 
881         /* Re-enable receive and transmit as appropriate */
882         cr = 0;
883         cr |=
884             (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
885         cr |=
886             (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
887         ssc_writel(ssc_p->ssc->regs, CR, cr);
888 
889         return 0;
890 }
891 #else /* CONFIG_PM */
892 #  define atmel_ssc_suspend     NULL
893 #  define atmel_ssc_resume      NULL
894 #endif /* CONFIG_PM */
895 
896 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8     | SNDRV_PCM_FMTBIT_S16_LE |\
897                           SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
898 
899 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
900         .startup        = atmel_ssc_startup,
901         .shutdown       = atmel_ssc_shutdown,
902         .prepare        = atmel_ssc_prepare,
903         .trigger        = atmel_ssc_trigger,
904         .hw_params      = atmel_ssc_hw_params,
905         .set_fmt        = atmel_ssc_set_dai_fmt,
906         .set_clkdiv     = atmel_ssc_set_dai_clkdiv,
907 };
908 
909 static struct snd_soc_dai_driver atmel_ssc_dai = {
910                 .suspend = atmel_ssc_suspend,
911                 .resume = atmel_ssc_resume,
912                 .playback = {
913                         .channels_min = 1,
914                         .channels_max = 2,
915                         .rates = SNDRV_PCM_RATE_CONTINUOUS,
916                         .rate_min = 8000,
917                         .rate_max = 384000,
918                         .formats = ATMEL_SSC_FORMATS,},
919                 .capture = {
920                         .channels_min = 1,
921                         .channels_max = 2,
922                         .rates = SNDRV_PCM_RATE_CONTINUOUS,
923                         .rate_min = 8000,
924                         .rate_max = 384000,
925                         .formats = ATMEL_SSC_FORMATS,},
926                 .ops = &atmel_ssc_dai_ops,
927 };
928 
929 static const struct snd_soc_component_driver atmel_ssc_component = {
930         .name           = "atmel-ssc",
931 };
932 
933 static int asoc_ssc_init(struct device *dev)
934 {
935         struct platform_device *pdev = to_platform_device(dev);
936         struct ssc_device *ssc = platform_get_drvdata(pdev);
937         int ret;
938 
939         ret = snd_soc_register_component(dev, &atmel_ssc_component,
940                                          &atmel_ssc_dai, 1);
941         if (ret) {
942                 dev_err(dev, "Could not register DAI: %d\n", ret);
943                 goto err;
944         }
945 
946         if (ssc->pdata->use_dma)
947                 ret = atmel_pcm_dma_platform_register(dev);
948         else
949                 ret = atmel_pcm_pdc_platform_register(dev);
950 
951         if (ret) {
952                 dev_err(dev, "Could not register PCM: %d\n", ret);
953                 goto err_unregister_dai;
954         }
955 
956         return 0;
957 
958 err_unregister_dai:
959         snd_soc_unregister_component(dev);
960 err:
961         return ret;
962 }
963 
964 static void asoc_ssc_exit(struct device *dev)
965 {
966         struct platform_device *pdev = to_platform_device(dev);
967         struct ssc_device *ssc = platform_get_drvdata(pdev);
968 
969         if (ssc->pdata->use_dma)
970                 atmel_pcm_dma_platform_unregister(dev);
971         else
972                 atmel_pcm_pdc_platform_unregister(dev);
973 
974         snd_soc_unregister_component(dev);
975 }
976 
977 /**
978  * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
979  */
980 int atmel_ssc_set_audio(int ssc_id)
981 {
982         struct ssc_device *ssc;
983         int ret;
984 
985         /* If we can grab the SSC briefly to parent the DAI device off it */
986         ssc = ssc_request(ssc_id);
987         if (IS_ERR(ssc)) {
988                 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
989                         PTR_ERR(ssc));
990                 return PTR_ERR(ssc);
991         } else {
992                 ssc_info[ssc_id].ssc = ssc;
993         }
994 
995         ret = asoc_ssc_init(&ssc->pdev->dev);
996 
997         return ret;
998 }
999 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
1000 
1001 void atmel_ssc_put_audio(int ssc_id)
1002 {
1003         struct ssc_device *ssc = ssc_info[ssc_id].ssc;
1004 
1005         asoc_ssc_exit(&ssc->pdev->dev);
1006         ssc_free(ssc);
1007 }
1008 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
1009 
1010 /* Module information */
1011 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
1012 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
1013 MODULE_LICENSE("GPL");
1014 

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