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Linux/sound/pci/rme9652/hdsp.c

  1 /*
  2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
  3  *
  4  *      Copyright (c) 2002  Paul Davis
  5  *                          Marcus Andersson
  6  *                          Thomas Charbonnel
  7  *
  8  *   This program is free software; you can redistribute it and/or modify
  9  *   it under the terms of the GNU General Public License as published by
 10  *   the Free Software Foundation; either version 2 of the License, or
 11  *   (at your option) any later version.
 12  *
 13  *   This program is distributed in the hope that it will be useful,
 14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  *   GNU General Public License for more details.
 17  *
 18  *   You should have received a copy of the GNU General Public License
 19  *   along with this program; if not, write to the Free Software
 20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 21  *
 22  */
 23 
 24 #include <linux/init.h>
 25 #include <linux/delay.h>
 26 #include <linux/interrupt.h>
 27 #include <linux/pci.h>
 28 #include <linux/firmware.h>
 29 #include <linux/module.h>
 30 #include <linux/math64.h>
 31 #include <linux/vmalloc.h>
 32 
 33 #include <sound/core.h>
 34 #include <sound/control.h>
 35 #include <sound/pcm.h>
 36 #include <sound/info.h>
 37 #include <sound/asoundef.h>
 38 #include <sound/rawmidi.h>
 39 #include <sound/hwdep.h>
 40 #include <sound/initval.h>
 41 #include <sound/hdsp.h>
 42 
 43 #include <asm/byteorder.h>
 44 #include <asm/current.h>
 45 #include <asm/io.h>
 46 
 47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 49 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
 50 
 51 module_param_array(index, int, NULL, 0444);
 52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
 53 module_param_array(id, charp, NULL, 0444);
 54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
 55 module_param_array(enable, bool, NULL, 0444);
 56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
 57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
 58 MODULE_DESCRIPTION("RME Hammerfall DSP");
 59 MODULE_LICENSE("GPL");
 60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
 61                 "{RME HDSP-9652},"
 62                 "{RME HDSP-9632}}");
 63 MODULE_FIRMWARE("rpm_firmware.bin");
 64 MODULE_FIRMWARE("multiface_firmware.bin");
 65 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
 66 MODULE_FIRMWARE("digiface_firmware.bin");
 67 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
 68 
 69 #define HDSP_MAX_CHANNELS        26
 70 #define HDSP_MAX_DS_CHANNELS     14
 71 #define HDSP_MAX_QS_CHANNELS     8
 72 #define DIGIFACE_SS_CHANNELS     26
 73 #define DIGIFACE_DS_CHANNELS     14
 74 #define MULTIFACE_SS_CHANNELS    18
 75 #define MULTIFACE_DS_CHANNELS    14
 76 #define H9652_SS_CHANNELS        26
 77 #define H9652_DS_CHANNELS        14
 78 /* This does not include possible Analog Extension Boards
 79    AEBs are detected at card initialization
 80 */
 81 #define H9632_SS_CHANNELS        12
 82 #define H9632_DS_CHANNELS        8
 83 #define H9632_QS_CHANNELS        4
 84 #define RPM_CHANNELS             6
 85 
 86 /* Write registers. These are defined as byte-offsets from the iobase value.
 87  */
 88 #define HDSP_resetPointer               0
 89 #define HDSP_freqReg                    0
 90 #define HDSP_outputBufferAddress        32
 91 #define HDSP_inputBufferAddress         36
 92 #define HDSP_controlRegister            64
 93 #define HDSP_interruptConfirmation      96
 94 #define HDSP_outputEnable               128
 95 #define HDSP_control2Reg                256
 96 #define HDSP_midiDataOut0               352
 97 #define HDSP_midiDataOut1               356
 98 #define HDSP_fifoData                   368
 99 #define HDSP_inputEnable                384
100 
101 /* Read registers. These are defined as byte-offsets from the iobase value
102  */
103 
104 #define HDSP_statusRegister    0
105 #define HDSP_timecode        128
106 #define HDSP_status2Register 192
107 #define HDSP_midiDataIn0     360
108 #define HDSP_midiDataIn1     364
109 #define HDSP_midiStatusOut0  384
110 #define HDSP_midiStatusOut1  388
111 #define HDSP_midiStatusIn0   392
112 #define HDSP_midiStatusIn1   396
113 #define HDSP_fifoStatus      400
114 
115 /* the meters are regular i/o-mapped registers, but offset
116    considerably from the rest. the peak registers are reset
117    when read; the least-significant 4 bits are full-scale counters;
118    the actual peak value is in the most-significant 24 bits.
119 */
120 
121 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
122 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
123 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
124 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
125 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
126 
127 
128 /* This is for H9652 cards
129    Peak values are read downward from the base
130    Rms values are read upward
131    There are rms values for the outputs too
132    26*3 values are read in ss mode
133    14*3 in ds mode, with no gap between values
134 */
135 #define HDSP_9652_peakBase      7164
136 #define HDSP_9652_rmsBase       4096
137 
138 /* c.f. the hdsp_9632_meters_t struct */
139 #define HDSP_9632_metersBase    4096
140 
141 #define HDSP_IO_EXTENT     7168
142 
143 /* control2 register bits */
144 
145 #define HDSP_TMS                0x01
146 #define HDSP_TCK                0x02
147 #define HDSP_TDI                0x04
148 #define HDSP_JTAG               0x08
149 #define HDSP_PWDN               0x10
150 #define HDSP_PROGRAM            0x020
151 #define HDSP_CONFIG_MODE_0      0x040
152 #define HDSP_CONFIG_MODE_1      0x080
153 #define HDSP_VERSION_BIT        (0x100 | HDSP_S_LOAD)
154 #define HDSP_BIGENDIAN_MODE     0x200
155 #define HDSP_RD_MULTIPLE        0x400
156 #define HDSP_9652_ENABLE_MIXER  0x800
157 #define HDSP_S200               0x800
158 #define HDSP_S300               (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
159 #define HDSP_CYCLIC_MODE        0x1000
160 #define HDSP_TDO                0x10000000
161 
162 #define HDSP_S_PROGRAM      (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
163 #define HDSP_S_LOAD         (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
164 
165 /* Control Register bits */
166 
167 #define HDSP_Start                (1<<0)  /* start engine */
168 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
169 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
170 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
171 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
172 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
173 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
174 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
175 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
176 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
177 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
178 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
179 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
180 #define HDSP_SyncRef2             (1<<13)
181 #define HDSP_SPDIFInputSelect0    (1<<14)
182 #define HDSP_SPDIFInputSelect1    (1<<15)
183 #define HDSP_SyncRef0             (1<<16)
184 #define HDSP_SyncRef1             (1<<17)
185 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
186 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
187 #define HDSP_Midi0InterruptEnable (1<<22)
188 #define HDSP_Midi1InterruptEnable (1<<23)
189 #define HDSP_LineOut              (1<<24)
190 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
191 #define HDSP_ADGain1              (1<<26)
192 #define HDSP_DAGain0              (1<<27)
193 #define HDSP_DAGain1              (1<<28)
194 #define HDSP_PhoneGain0           (1<<29)
195 #define HDSP_PhoneGain1           (1<<30)
196 #define HDSP_QuadSpeed            (1<<31)
197 
198 /* RPM uses some of the registers for special purposes */
199 #define HDSP_RPM_Inp12            0x04A00
200 #define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
201 #define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
202 #define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
203 #define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
204 #define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */
205 
206 #define HDSP_RPM_Inp34            0x32000
207 #define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
208 #define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
209 #define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
210 #define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
211 #define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */
212 
213 #define HDSP_RPM_Bypass           0x01000
214 
215 #define HDSP_RPM_Disconnect       0x00001
216 
217 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
218 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
219 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
220 #define HDSP_ADGainLowGain     0
221 
222 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
223 #define HDSP_DAGainHighGain      HDSP_DAGainMask
224 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
225 #define HDSP_DAGainMinus10dBV    0
226 
227 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
228 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
229 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
230 #define HDSP_PhoneGainMinus12dB  0
231 
232 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
233 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
234 
235 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
236 #define HDSP_SPDIFInputADAT1    0
237 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
238 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
239 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
240 
241 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
242 #define HDSP_SyncRef_ADAT1       0
243 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
244 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
245 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
246 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
247 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
248 
249 /* Sample Clock Sources */
250 
251 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
252 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
253 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
254 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
255 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
256 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
257 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
258 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
259 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
260 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
261 
262 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
263 
264 #define HDSP_SYNC_FROM_WORD      0
265 #define HDSP_SYNC_FROM_SPDIF     1
266 #define HDSP_SYNC_FROM_ADAT1     2
267 #define HDSP_SYNC_FROM_ADAT_SYNC 3
268 #define HDSP_SYNC_FROM_ADAT2     4
269 #define HDSP_SYNC_FROM_ADAT3     5
270 
271 /* SyncCheck status */
272 
273 #define HDSP_SYNC_CHECK_NO_LOCK 0
274 #define HDSP_SYNC_CHECK_LOCK    1
275 #define HDSP_SYNC_CHECK_SYNC    2
276 
277 /* AutoSync references - used by "autosync_ref" control switch */
278 
279 #define HDSP_AUTOSYNC_FROM_WORD      0
280 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
281 #define HDSP_AUTOSYNC_FROM_SPDIF     2
282 #define HDSP_AUTOSYNC_FROM_NONE      3
283 #define HDSP_AUTOSYNC_FROM_ADAT1     4
284 #define HDSP_AUTOSYNC_FROM_ADAT2     5
285 #define HDSP_AUTOSYNC_FROM_ADAT3     6
286 
287 /* Possible sources of S/PDIF input */
288 
289 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
290 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
291 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
292 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
293 
294 #define HDSP_Frequency32KHz    HDSP_Frequency0
295 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
296 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
297 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
298 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
299 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
300 /* For H9632 cards */
301 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
302 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
303 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
304 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
305         return 104857600000000 / rate; // 100 MHz
306         return 110100480000000 / rate; // 105 MHz
307 */
308 #define DDS_NUMERATOR 104857600000000ULL;  /*  =  2^20 * 10^8 */
309 
310 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
311 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
312 
313 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
314 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
315 
316 /* Status Register bits */
317 
318 #define HDSP_audioIRQPending    (1<<0)
319 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
320 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
321 #define HDSP_Lock1              (1<<2)
322 #define HDSP_Lock0              (1<<3)
323 #define HDSP_SPDIFSync          (1<<4)
324 #define HDSP_TimecodeLock       (1<<5)
325 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
326 #define HDSP_Sync2              (1<<16)
327 #define HDSP_Sync1              (1<<17)
328 #define HDSP_Sync0              (1<<18)
329 #define HDSP_DoubleSpeedStatus  (1<<19)
330 #define HDSP_ConfigError        (1<<20)
331 #define HDSP_DllError           (1<<21)
332 #define HDSP_spdifFrequency0    (1<<22)
333 #define HDSP_spdifFrequency1    (1<<23)
334 #define HDSP_spdifFrequency2    (1<<24)
335 #define HDSP_SPDIFErrorFlag     (1<<25)
336 #define HDSP_BufferID           (1<<26)
337 #define HDSP_TimecodeSync       (1<<27)
338 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
339 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
340 #define HDSP_midi0IRQPending    (1<<30)
341 #define HDSP_midi1IRQPending    (1<<31)
342 
343 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
344 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
345                                       HDSP_spdifFrequency1|\
346                                       HDSP_spdifFrequency2|\
347                                       HDSP_spdifFrequency3)
348 
349 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
350 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
351 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
352 
353 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
354 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
355 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
356 
357 /* This is for H9632 cards */
358 #define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
359                                      HDSP_spdifFrequency1|\
360                                      HDSP_spdifFrequency2)
361 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
362 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
363 
364 /* Status2 Register bits */
365 
366 #define HDSP_version0     (1<<0)
367 #define HDSP_version1     (1<<1)
368 #define HDSP_version2     (1<<2)
369 #define HDSP_wc_lock      (1<<3)
370 #define HDSP_wc_sync      (1<<4)
371 #define HDSP_inp_freq0    (1<<5)
372 #define HDSP_inp_freq1    (1<<6)
373 #define HDSP_inp_freq2    (1<<7)
374 #define HDSP_SelSyncRef0  (1<<8)
375 #define HDSP_SelSyncRef1  (1<<9)
376 #define HDSP_SelSyncRef2  (1<<10)
377 
378 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
379 
380 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
381 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
382 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
383 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
384 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
385 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
386 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
387 /* FIXME : more values for 9632 cards ? */
388 
389 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
390 #define HDSP_SelSyncRef_ADAT1      0
391 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
392 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
393 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
394 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
395 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
396 
397 /* Card state flags */
398 
399 #define HDSP_InitializationComplete  (1<<0)
400 #define HDSP_FirmwareLoaded          (1<<1)
401 #define HDSP_FirmwareCached          (1<<2)
402 
403 /* FIFO wait times, defined in terms of 1/10ths of msecs */
404 
405 #define HDSP_LONG_WAIT   5000
406 #define HDSP_SHORT_WAIT  30
407 
408 #define UNITY_GAIN                       32768
409 #define MINUS_INFINITY_GAIN              0
410 
411 /* the size of a substream (1 mono data stream) */
412 
413 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
414 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
415 
416 /* the size of the area we need to allocate for DMA transfers. the
417    size is the same regardless of the number of channels - the
418    Multiface still uses the same memory area.
419 
420    Note that we allocate 1 more channel than is apparently needed
421    because the h/w seems to write 1 byte beyond the end of the last
422    page. Sigh.
423 */
424 
425 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
426 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
427 
428 #define HDSP_FIRMWARE_SIZE      (24413 * 4)
429 
430 struct hdsp_9632_meters {
431     u32 input_peak[16];
432     u32 playback_peak[16];
433     u32 output_peak[16];
434     u32 xxx_peak[16];
435     u32 padding[64];
436     u32 input_rms_low[16];
437     u32 playback_rms_low[16];
438     u32 output_rms_low[16];
439     u32 xxx_rms_low[16];
440     u32 input_rms_high[16];
441     u32 playback_rms_high[16];
442     u32 output_rms_high[16];
443     u32 xxx_rms_high[16];
444 };
445 
446 struct hdsp_midi {
447     struct hdsp             *hdsp;
448     int                      id;
449     struct snd_rawmidi           *rmidi;
450     struct snd_rawmidi_substream *input;
451     struct snd_rawmidi_substream *output;
452     char                     istimer; /* timer in use */
453     struct timer_list        timer;
454     spinlock_t               lock;
455     int                      pending;
456 };
457 
458 struct hdsp {
459         spinlock_t            lock;
460         struct snd_pcm_substream *capture_substream;
461         struct snd_pcm_substream *playback_substream;
462         struct hdsp_midi      midi[2];
463         struct tasklet_struct midi_tasklet;
464         int                   use_midi_tasklet;
465         int                   precise_ptr;
466         u32                   control_register;      /* cached value */
467         u32                   control2_register;     /* cached value */
468         u32                   creg_spdif;
469         u32                   creg_spdif_stream;
470         int                   clock_source_locked;
471         char                 *card_name;         /* digiface/multiface/rpm */
472         enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
473         unsigned short        firmware_rev;
474         unsigned short        state;                 /* stores state bits */
475         const struct firmware *firmware;
476         u32                  *fw_uploaded;
477         size_t                period_bytes;          /* guess what this is */
478         unsigned char         max_channels;
479         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
480         unsigned char         ds_in_channels;
481         unsigned char         ss_in_channels;       /* different for multiface/digiface */
482         unsigned char         qs_out_channels;
483         unsigned char         ds_out_channels;
484         unsigned char         ss_out_channels;
485 
486         struct snd_dma_buffer capture_dma_buf;
487         struct snd_dma_buffer playback_dma_buf;
488         unsigned char        *capture_buffer;       /* suitably aligned address */
489         unsigned char        *playback_buffer;      /* suitably aligned address */
490 
491         pid_t                 capture_pid;
492         pid_t                 playback_pid;
493         int                   running;
494         int                   system_sample_rate;
495         char                 *channel_map;
496         int                   dev;
497         int                   irq;
498         unsigned long         port;
499         void __iomem         *iobase;
500         struct snd_card *card;
501         struct snd_pcm *pcm;
502         struct snd_hwdep          *hwdep;
503         struct pci_dev       *pci;
504         struct snd_kcontrol *spdif_ctl;
505         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
506         unsigned int          dds_value; /* last value written to freq register */
507 };
508 
509 /* These tables map the ALSA channels 1..N to the channels that we
510    need to use in order to find the relevant channel buffer. RME
511    refer to this kind of mapping as between "the ADAT channel and
512    the DMA channel." We index it using the logical audio channel,
513    and the value is the DMA channel (i.e. channel buffer number)
514    where the data for that channel can be read/written from/to.
515 */
516 
517 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
518         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
519         18, 19, 20, 21, 22, 23, 24, 25
520 };
521 
522 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
523         /* Analog */
524         0, 1, 2, 3, 4, 5, 6, 7,
525         /* ADAT 2 */
526         16, 17, 18, 19, 20, 21, 22, 23,
527         /* SPDIF */
528         24, 25,
529         -1, -1, -1, -1, -1, -1, -1, -1
530 };
531 
532 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
533         /* ADAT channels are remapped */
534         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
535         /* channels 12 and 13 are S/PDIF */
536         24, 25,
537         /* others don't exist */
538         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
539 };
540 
541 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
542         /* ADAT channels */
543         0, 1, 2, 3, 4, 5, 6, 7,
544         /* SPDIF */
545         8, 9,
546         /* Analog */
547         10, 11,
548         /* AO4S-192 and AI4S-192 extension boards */
549         12, 13, 14, 15,
550         /* others don't exist */
551         -1, -1, -1, -1, -1, -1, -1, -1,
552         -1, -1
553 };
554 
555 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
556         /* ADAT */
557         1, 3, 5, 7,
558         /* SPDIF */
559         8, 9,
560         /* Analog */
561         10, 11,
562         /* AO4S-192 and AI4S-192 extension boards */
563         12, 13, 14, 15,
564         /* others don't exist */
565         -1, -1, -1, -1, -1, -1, -1, -1,
566         -1, -1, -1, -1, -1, -1
567 };
568 
569 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
570         /* ADAT is disabled in this mode */
571         /* SPDIF */
572         8, 9,
573         /* Analog */
574         10, 11,
575         /* AO4S-192 and AI4S-192 extension boards */
576         12, 13, 14, 15,
577         /* others don't exist */
578         -1, -1, -1, -1, -1, -1, -1, -1,
579         -1, -1, -1, -1, -1, -1, -1, -1,
580         -1, -1
581 };
582 
583 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
584 {
585         dmab->dev.type = SNDRV_DMA_TYPE_DEV;
586         dmab->dev.dev = snd_dma_pci_data(pci);
587         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
588                                 size, dmab) < 0)
589                 return -ENOMEM;
590         return 0;
591 }
592 
593 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
594 {
595         if (dmab->area)
596                 snd_dma_free_pages(dmab);
597 }
598 
599 
600 static DEFINE_PCI_DEVICE_TABLE(snd_hdsp_ids) = {
601         {
602                 .vendor = PCI_VENDOR_ID_XILINX,
603                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
604                 .subvendor = PCI_ANY_ID,
605                 .subdevice = PCI_ANY_ID,
606         }, /* RME Hammerfall-DSP */
607         { 0, },
608 };
609 
610 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
611 
612 /* prototypes */
613 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
614 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
615 static int snd_hdsp_enable_io (struct hdsp *hdsp);
616 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
617 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
618 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
619 static int hdsp_autosync_ref(struct hdsp *hdsp);
620 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
621 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
622 
623 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
624 {
625         switch (hdsp->io_type) {
626         case Multiface:
627         case Digiface:
628         case RPM:
629         default:
630                 if (hdsp->firmware_rev == 0xa)
631                         return (64 * out) + (32 + (in));
632                 else
633                         return (52 * out) + (26 + (in));
634         case H9632:
635                 return (32 * out) + (16 + (in));
636         case H9652:
637                 return (52 * out) + (26 + (in));
638         }
639 }
640 
641 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
642 {
643         switch (hdsp->io_type) {
644         case Multiface:
645         case Digiface:
646         case RPM:
647         default:
648                 if (hdsp->firmware_rev == 0xa)
649                         return (64 * out) + in;
650                 else
651                         return (52 * out) + in;
652         case H9632:
653                 return (32 * out) + in;
654         case H9652:
655                 return (52 * out) + in;
656         }
657 }
658 
659 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
660 {
661         writel(val, hdsp->iobase + reg);
662 }
663 
664 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
665 {
666         return readl (hdsp->iobase + reg);
667 }
668 
669 static int hdsp_check_for_iobox (struct hdsp *hdsp)
670 {
671         int i;
672 
673         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
674         for (i = 0; i < 500; i++) {
675                 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
676                                         HDSP_ConfigError)) {
677                         if (i) {
678                                 dev_dbg(hdsp->card->dev,
679                                         "IO box found after %d ms\n",
680                                                 (20 * i));
681                         }
682                         return 0;
683                 }
684                 msleep(20);
685         }
686         dev_err(hdsp->card->dev, "no IO box connected!\n");
687         hdsp->state &= ~HDSP_FirmwareLoaded;
688         return -EIO;
689 }
690 
691 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
692                                unsigned int delay)
693 {
694         unsigned int i;
695 
696         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
697                 return 0;
698 
699         for (i = 0; i != loops; ++i) {
700                 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
701                         msleep(delay);
702                 else {
703                         dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
704                                    i * delay);
705                         return 0;
706                 }
707         }
708 
709         dev_info(hdsp->card->dev, "no IO box connected!\n");
710         hdsp->state &= ~HDSP_FirmwareLoaded;
711         return -EIO;
712 }
713 
714 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
715 
716         int i;
717         unsigned long flags;
718         const u32 *cache;
719 
720         if (hdsp->fw_uploaded)
721                 cache = hdsp->fw_uploaded;
722         else {
723                 if (!hdsp->firmware)
724                         return -ENODEV;
725                 cache = (u32 *)hdsp->firmware->data;
726                 if (!cache)
727                         return -ENODEV;
728         }
729 
730         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
731 
732                 dev_info(hdsp->card->dev, "loading firmware\n");
733 
734                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
735                 hdsp_write (hdsp, HDSP_fifoData, 0);
736 
737                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
738                         dev_info(hdsp->card->dev,
739                                  "timeout waiting for download preparation\n");
740                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
741                         return -EIO;
742                 }
743 
744                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
745 
746                 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
747                         hdsp_write(hdsp, HDSP_fifoData, cache[i]);
748                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
749                                 dev_info(hdsp->card->dev,
750                                          "timeout during firmware loading\n");
751                                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
752                                 return -EIO;
753                         }
754                 }
755 
756                 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
757                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
758 
759                 ssleep(3);
760 #ifdef SNDRV_BIG_ENDIAN
761                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
762 #else
763                 hdsp->control2_register = 0;
764 #endif
765                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
766                 dev_info(hdsp->card->dev, "finished firmware loading\n");
767 
768         }
769         if (hdsp->state & HDSP_InitializationComplete) {
770                 dev_info(hdsp->card->dev,
771                          "firmware loaded from cache, restoring defaults\n");
772                 spin_lock_irqsave(&hdsp->lock, flags);
773                 snd_hdsp_set_defaults(hdsp);
774                 spin_unlock_irqrestore(&hdsp->lock, flags);
775         }
776 
777         hdsp->state |= HDSP_FirmwareLoaded;
778 
779         return 0;
780 }
781 
782 static int hdsp_get_iobox_version (struct hdsp *hdsp)
783 {
784         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
785 
786                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
787                 hdsp_write(hdsp, HDSP_fifoData, 0);
788 
789                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
790                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
791                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
792                 }
793 
794                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
795                 hdsp_write (hdsp, HDSP_fifoData, 0);
796                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
797                         hdsp->io_type = Multiface;
798                         dev_info(hdsp->card->dev, "Multiface found\n");
799                         return 0;
800                 }
801 
802                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
803                 hdsp_write(hdsp, HDSP_fifoData, 0);
804                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
805                         hdsp->io_type = Digiface;
806                         dev_info(hdsp->card->dev, "Digiface found\n");
807                         return 0;
808                 }
809 
810                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
811                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
812                 hdsp_write(hdsp, HDSP_fifoData, 0);
813                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
814                         hdsp->io_type = Multiface;
815                         dev_info(hdsp->card->dev, "Multiface found\n");
816                         return 0;
817                 }
818 
819                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
820                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
821                 hdsp_write(hdsp, HDSP_fifoData, 0);
822                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
823                         hdsp->io_type = Multiface;
824                         dev_info(hdsp->card->dev, "Multiface found\n");
825                         return 0;
826                 }
827 
828                 hdsp->io_type = RPM;
829                 dev_info(hdsp->card->dev, "RPM found\n");
830                 return 0;
831         } else {
832                 /* firmware was already loaded, get iobox type */
833                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
834                         hdsp->io_type = RPM;
835                 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
836                         hdsp->io_type = Multiface;
837                 else
838                         hdsp->io_type = Digiface;
839         }
840         return 0;
841 }
842 
843 
844 static int hdsp_request_fw_loader(struct hdsp *hdsp);
845 
846 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
847 {
848         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
849                 return 0;
850         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
851                 hdsp->state &= ~HDSP_FirmwareLoaded;
852                 if (! load_on_demand)
853                         return -EIO;
854                 dev_err(hdsp->card->dev, "firmware not present.\n");
855                 /* try to load firmware */
856                 if (! (hdsp->state & HDSP_FirmwareCached)) {
857                         if (! hdsp_request_fw_loader(hdsp))
858                                 return 0;
859                         dev_err(hdsp->card->dev,
860                                    "No firmware loaded nor cached, please upload firmware.\n");
861                         return -EIO;
862                 }
863                 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
864                         dev_err(hdsp->card->dev,
865                                    "Firmware loading from cache failed, please upload manually.\n");
866                         return -EIO;
867                 }
868         }
869         return 0;
870 }
871 
872 
873 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
874 {
875         int i;
876 
877         /* the fifoStatus registers reports on how many words
878            are available in the command FIFO.
879         */
880 
881         for (i = 0; i < timeout; i++) {
882 
883                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
884                         return 0;
885 
886                 /* not very friendly, but we only do this during a firmware
887                    load and changing the mixer, so we just put up with it.
888                 */
889 
890                 udelay (100);
891         }
892 
893         dev_warn(hdsp->card->dev,
894                  "wait for FIFO status <= %d failed after %d iterations\n",
895                     count, timeout);
896         return -1;
897 }
898 
899 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
900 {
901         if (addr >= HDSP_MATRIX_MIXER_SIZE)
902                 return 0;
903 
904         return hdsp->mixer_matrix[addr];
905 }
906 
907 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
908 {
909         unsigned int ad;
910 
911         if (addr >= HDSP_MATRIX_MIXER_SIZE)
912                 return -1;
913 
914         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
915 
916                 /* from martin bjornsen:
917 
918                    "You can only write dwords to the
919                    mixer memory which contain two
920                    mixer values in the low and high
921                    word. So if you want to change
922                    value 0 you have to read value 1
923                    from the cache and write both to
924                    the first dword in the mixer
925                    memory."
926                 */
927 
928                 if (hdsp->io_type == H9632 && addr >= 512)
929                         return 0;
930 
931                 if (hdsp->io_type == H9652 && addr >= 1352)
932                         return 0;
933 
934                 hdsp->mixer_matrix[addr] = data;
935 
936 
937                 /* `addr' addresses a 16-bit wide address, but
938                    the address space accessed via hdsp_write
939                    uses byte offsets. put another way, addr
940                    varies from 0 to 1351, but to access the
941                    corresponding memory location, we need
942                    to access 0 to 2703 ...
943                 */
944                 ad = addr/2;
945 
946                 hdsp_write (hdsp, 4096 + (ad*4),
947                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
948                             hdsp->mixer_matrix[addr&0x7fe]);
949 
950                 return 0;
951 
952         } else {
953 
954                 ad = (addr << 16) + data;
955 
956                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
957                         return -1;
958 
959                 hdsp_write (hdsp, HDSP_fifoData, ad);
960                 hdsp->mixer_matrix[addr] = data;
961 
962         }
963 
964         return 0;
965 }
966 
967 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
968 {
969         unsigned long flags;
970         int ret = 1;
971 
972         spin_lock_irqsave(&hdsp->lock, flags);
973         if ((hdsp->playback_pid != hdsp->capture_pid) &&
974             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
975                 ret = 0;
976         spin_unlock_irqrestore(&hdsp->lock, flags);
977         return ret;
978 }
979 
980 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
981 {
982         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
983         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
984 
985         /* For the 9632, the mask is different */
986         if (hdsp->io_type == H9632)
987                  rate_bits = (status & HDSP_spdifFrequencyMask_9632);
988 
989         if (status & HDSP_SPDIFErrorFlag)
990                 return 0;
991 
992         switch (rate_bits) {
993         case HDSP_spdifFrequency32KHz: return 32000;
994         case HDSP_spdifFrequency44_1KHz: return 44100;
995         case HDSP_spdifFrequency48KHz: return 48000;
996         case HDSP_spdifFrequency64KHz: return 64000;
997         case HDSP_spdifFrequency88_2KHz: return 88200;
998         case HDSP_spdifFrequency96KHz: return 96000;
999         case HDSP_spdifFrequency128KHz:
1000                 if (hdsp->io_type == H9632) return 128000;
1001                 break;
1002         case HDSP_spdifFrequency176_4KHz:
1003                 if (hdsp->io_type == H9632) return 176400;
1004                 break;
1005         case HDSP_spdifFrequency192KHz:
1006                 if (hdsp->io_type == H9632) return 192000;
1007                 break;
1008         default:
1009                 break;
1010         }
1011         dev_warn(hdsp->card->dev,
1012                  "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
1013                  rate_bits, status);
1014         return 0;
1015 }
1016 
1017 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1018 {
1019         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1020         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1021 
1022         /* For the 9632 card, there seems to be no bit for indicating external
1023          * sample rate greater than 96kHz. The card reports the corresponding
1024          * single speed. So the best means seems to get spdif rate when
1025          * autosync reference is spdif */
1026         if (hdsp->io_type == H9632 &&
1027             hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1028                  return hdsp_spdif_sample_rate(hdsp);
1029 
1030         switch (rate_bits) {
1031         case HDSP_systemFrequency32:   return 32000;
1032         case HDSP_systemFrequency44_1: return 44100;
1033         case HDSP_systemFrequency48:   return 48000;
1034         case HDSP_systemFrequency64:   return 64000;
1035         case HDSP_systemFrequency88_2: return 88200;
1036         case HDSP_systemFrequency96:   return 96000;
1037         default:
1038                 return 0;
1039         }
1040 }
1041 
1042 static void hdsp_compute_period_size(struct hdsp *hdsp)
1043 {
1044         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1045 }
1046 
1047 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1048 {
1049         int position;
1050 
1051         position = hdsp_read(hdsp, HDSP_statusRegister);
1052 
1053         if (!hdsp->precise_ptr)
1054                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1055 
1056         position &= HDSP_BufferPositionMask;
1057         position /= 4;
1058         position &= (hdsp->period_bytes/2) - 1;
1059         return position;
1060 }
1061 
1062 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1063 {
1064         hdsp_write (hdsp, HDSP_resetPointer, 0);
1065         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1066                 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1067                  * requires (?) to write again DDS value after a reset pointer
1068                  * (at least, it works like this) */
1069                 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1070 }
1071 
1072 static void hdsp_start_audio(struct hdsp *s)
1073 {
1074         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1075         hdsp_write(s, HDSP_controlRegister, s->control_register);
1076 }
1077 
1078 static void hdsp_stop_audio(struct hdsp *s)
1079 {
1080         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1081         hdsp_write(s, HDSP_controlRegister, s->control_register);
1082 }
1083 
1084 static void hdsp_silence_playback(struct hdsp *hdsp)
1085 {
1086         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1087 }
1088 
1089 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1090 {
1091         int n;
1092 
1093         spin_lock_irq(&s->lock);
1094 
1095         frames >>= 7;
1096         n = 0;
1097         while (frames) {
1098                 n++;
1099                 frames >>= 1;
1100         }
1101 
1102         s->control_register &= ~HDSP_LatencyMask;
1103         s->control_register |= hdsp_encode_latency(n);
1104 
1105         hdsp_write(s, HDSP_controlRegister, s->control_register);
1106 
1107         hdsp_compute_period_size(s);
1108 
1109         spin_unlock_irq(&s->lock);
1110 
1111         return 0;
1112 }
1113 
1114 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1115 {
1116         u64 n;
1117 
1118         if (rate >= 112000)
1119                 rate /= 4;
1120         else if (rate >= 56000)
1121                 rate /= 2;
1122 
1123         n = DDS_NUMERATOR;
1124         n = div_u64(n, rate);
1125         /* n should be less than 2^32 for being written to FREQ register */
1126         snd_BUG_ON(n >> 32);
1127         /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1128            value to write it after a reset */
1129         hdsp->dds_value = n;
1130         hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1131 }
1132 
1133 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1134 {
1135         int reject_if_open = 0;
1136         int current_rate;
1137         int rate_bits;
1138 
1139         /* ASSUMPTION: hdsp->lock is either held, or
1140            there is no need for it (e.g. during module
1141            initialization).
1142         */
1143 
1144         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1145                 if (called_internally) {
1146                         /* request from ctl or card initialization */
1147                         dev_err(hdsp->card->dev,
1148                                 "device is not running as a clock master: cannot set sample rate.\n");
1149                         return -1;
1150                 } else {
1151                         /* hw_param request while in AutoSync mode */
1152                         int external_freq = hdsp_external_sample_rate(hdsp);
1153                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1154 
1155                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1156                                 dev_info(hdsp->card->dev,
1157                                          "Detected ADAT in double speed mode\n");
1158                         else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1159                                 dev_info(hdsp->card->dev,
1160                                          "Detected ADAT in quad speed mode\n");
1161                         else if (rate != external_freq) {
1162                                 dev_info(hdsp->card->dev,
1163                                          "No AutoSync source for requested rate\n");
1164                                 return -1;
1165                         }
1166                 }
1167         }
1168 
1169         current_rate = hdsp->system_sample_rate;
1170 
1171         /* Changing from a "single speed" to a "double speed" rate is
1172            not allowed if any substreams are open. This is because
1173            such a change causes a shift in the location of
1174            the DMA buffers and a reduction in the number of available
1175            buffers.
1176 
1177            Note that a similar but essentially insoluble problem
1178            exists for externally-driven rate changes. All we can do
1179            is to flag rate changes in the read/write routines.  */
1180 
1181         if (rate > 96000 && hdsp->io_type != H9632)
1182                 return -EINVAL;
1183 
1184         switch (rate) {
1185         case 32000:
1186                 if (current_rate > 48000)
1187                         reject_if_open = 1;
1188                 rate_bits = HDSP_Frequency32KHz;
1189                 break;
1190         case 44100:
1191                 if (current_rate > 48000)
1192                         reject_if_open = 1;
1193                 rate_bits = HDSP_Frequency44_1KHz;
1194                 break;
1195         case 48000:
1196                 if (current_rate > 48000)
1197                         reject_if_open = 1;
1198                 rate_bits = HDSP_Frequency48KHz;
1199                 break;
1200         case 64000:
1201                 if (current_rate <= 48000 || current_rate > 96000)
1202                         reject_if_open = 1;
1203                 rate_bits = HDSP_Frequency64KHz;
1204                 break;
1205         case 88200:
1206                 if (current_rate <= 48000 || current_rate > 96000)
1207                         reject_if_open = 1;
1208                 rate_bits = HDSP_Frequency88_2KHz;
1209                 break;
1210         case 96000:
1211                 if (current_rate <= 48000 || current_rate > 96000)
1212                         reject_if_open = 1;
1213                 rate_bits = HDSP_Frequency96KHz;
1214                 break;
1215         case 128000:
1216                 if (current_rate < 128000)
1217                         reject_if_open = 1;
1218                 rate_bits = HDSP_Frequency128KHz;
1219                 break;
1220         case 176400:
1221                 if (current_rate < 128000)
1222                         reject_if_open = 1;
1223                 rate_bits = HDSP_Frequency176_4KHz;
1224                 break;
1225         case 192000:
1226                 if (current_rate < 128000)
1227                         reject_if_open = 1;
1228                 rate_bits = HDSP_Frequency192KHz;
1229                 break;
1230         default:
1231                 return -EINVAL;
1232         }
1233 
1234         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1235                 dev_warn(hdsp->card->dev,
1236                          "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1237                             hdsp->capture_pid,
1238                             hdsp->playback_pid);
1239                 return -EBUSY;
1240         }
1241 
1242         hdsp->control_register &= ~HDSP_FrequencyMask;
1243         hdsp->control_register |= rate_bits;
1244         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1245 
1246         /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1247         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1248                 hdsp_set_dds_value(hdsp, rate);
1249 
1250         if (rate >= 128000) {
1251                 hdsp->channel_map = channel_map_H9632_qs;
1252         } else if (rate > 48000) {
1253                 if (hdsp->io_type == H9632)
1254                         hdsp->channel_map = channel_map_H9632_ds;
1255                 else
1256                         hdsp->channel_map = channel_map_ds;
1257         } else {
1258                 switch (hdsp->io_type) {
1259                 case RPM:
1260                 case Multiface:
1261                         hdsp->channel_map = channel_map_mf_ss;
1262                         break;
1263                 case Digiface:
1264                 case H9652:
1265                         hdsp->channel_map = channel_map_df_ss;
1266                         break;
1267                 case H9632:
1268                         hdsp->channel_map = channel_map_H9632_ss;
1269                         break;
1270                 default:
1271                         /* should never happen */
1272                         break;
1273                 }
1274         }
1275 
1276         hdsp->system_sample_rate = rate;
1277 
1278         return 0;
1279 }
1280 
1281 /*----------------------------------------------------------------------------
1282    MIDI
1283   ----------------------------------------------------------------------------*/
1284 
1285 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1286 {
1287         /* the hardware already does the relevant bit-mask with 0xff */
1288         if (id)
1289                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1290         else
1291                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1292 }
1293 
1294 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1295 {
1296         /* the hardware already does the relevant bit-mask with 0xff */
1297         if (id)
1298                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1299         else
1300                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1301 }
1302 
1303 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1304 {
1305         if (id)
1306                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1307         else
1308                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1309 }
1310 
1311 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1312 {
1313         int fifo_bytes_used;
1314 
1315         if (id)
1316                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1317         else
1318                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1319 
1320         if (fifo_bytes_used < 128)
1321                 return  128 - fifo_bytes_used;
1322         else
1323                 return 0;
1324 }
1325 
1326 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1327 {
1328         while (snd_hdsp_midi_input_available (hdsp, id))
1329                 snd_hdsp_midi_read_byte (hdsp, id);
1330 }
1331 
1332 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1333 {
1334         unsigned long flags;
1335         int n_pending;
1336         int to_write;
1337         int i;
1338         unsigned char buf[128];
1339 
1340         /* Output is not interrupt driven */
1341 
1342         spin_lock_irqsave (&hmidi->lock, flags);
1343         if (hmidi->output) {
1344                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1345                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1346                                 if (n_pending > (int)sizeof (buf))
1347                                         n_pending = sizeof (buf);
1348 
1349                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1350                                         for (i = 0; i < to_write; ++i)
1351                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1352                                 }
1353                         }
1354                 }
1355         }
1356         spin_unlock_irqrestore (&hmidi->lock, flags);
1357         return 0;
1358 }
1359 
1360 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1361 {
1362         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1363         unsigned long flags;
1364         int n_pending;
1365         int i;
1366 
1367         spin_lock_irqsave (&hmidi->lock, flags);
1368         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1369                 if (hmidi->input) {
1370                         if (n_pending > (int)sizeof (buf))
1371                                 n_pending = sizeof (buf);
1372                         for (i = 0; i < n_pending; ++i)
1373                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1374                         if (n_pending)
1375                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1376                 } else {
1377                         /* flush the MIDI input FIFO */
1378                         while (--n_pending)
1379                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1380                 }
1381         }
1382         hmidi->pending = 0;
1383         if (hmidi->id)
1384                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1385         else
1386                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1387         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1388         spin_unlock_irqrestore (&hmidi->lock, flags);
1389         return snd_hdsp_midi_output_write (hmidi);
1390 }
1391 
1392 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1393 {
1394         struct hdsp *hdsp;
1395         struct hdsp_midi *hmidi;
1396         unsigned long flags;
1397         u32 ie;
1398 
1399         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1400         hdsp = hmidi->hdsp;
1401         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1402         spin_lock_irqsave (&hdsp->lock, flags);
1403         if (up) {
1404                 if (!(hdsp->control_register & ie)) {
1405                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1406                         hdsp->control_register |= ie;
1407                 }
1408         } else {
1409                 hdsp->control_register &= ~ie;
1410                 tasklet_kill(&hdsp->midi_tasklet);
1411         }
1412 
1413         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1414         spin_unlock_irqrestore (&hdsp->lock, flags);
1415 }
1416 
1417 static void snd_hdsp_midi_output_timer(unsigned long data)
1418 {
1419         struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1420         unsigned long flags;
1421 
1422         snd_hdsp_midi_output_write(hmidi);
1423         spin_lock_irqsave (&hmidi->lock, flags);
1424 
1425         /* this does not bump hmidi->istimer, because the
1426            kernel automatically removed the timer when it
1427            expired, and we are now adding it back, thus
1428            leaving istimer wherever it was set before.
1429         */
1430 
1431         if (hmidi->istimer) {
1432                 hmidi->timer.expires = 1 + jiffies;
1433                 add_timer(&hmidi->timer);
1434         }
1435 
1436         spin_unlock_irqrestore (&hmidi->lock, flags);
1437 }
1438 
1439 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1440 {
1441         struct hdsp_midi *hmidi;
1442         unsigned long flags;
1443 
1444         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1445         spin_lock_irqsave (&hmidi->lock, flags);
1446         if (up) {
1447                 if (!hmidi->istimer) {
1448                         init_timer(&hmidi->timer);
1449                         hmidi->timer.function = snd_hdsp_midi_output_timer;
1450                         hmidi->timer.data = (unsigned long) hmidi;
1451                         hmidi->timer.expires = 1 + jiffies;
1452                         add_timer(&hmidi->timer);
1453                         hmidi->istimer++;
1454                 }
1455         } else {
1456                 if (hmidi->istimer && --hmidi->istimer <= 0)
1457                         del_timer (&hmidi->timer);
1458         }
1459         spin_unlock_irqrestore (&hmidi->lock, flags);
1460         if (up)
1461                 snd_hdsp_midi_output_write(hmidi);
1462 }
1463 
1464 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1465 {
1466         struct hdsp_midi *hmidi;
1467 
1468         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1469         spin_lock_irq (&hmidi->lock);
1470         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1471         hmidi->input = substream;
1472         spin_unlock_irq (&hmidi->lock);
1473 
1474         return 0;
1475 }
1476 
1477 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1478 {
1479         struct hdsp_midi *hmidi;
1480 
1481         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1482         spin_lock_irq (&hmidi->lock);
1483         hmidi->output = substream;
1484         spin_unlock_irq (&hmidi->lock);
1485 
1486         return 0;
1487 }
1488 
1489 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1490 {
1491         struct hdsp_midi *hmidi;
1492 
1493         snd_hdsp_midi_input_trigger (substream, 0);
1494 
1495         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1496         spin_lock_irq (&hmidi->lock);
1497         hmidi->input = NULL;
1498         spin_unlock_irq (&hmidi->lock);
1499 
1500         return 0;
1501 }
1502 
1503 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1504 {
1505         struct hdsp_midi *hmidi;
1506 
1507         snd_hdsp_midi_output_trigger (substream, 0);
1508 
1509         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1510         spin_lock_irq (&hmidi->lock);
1511         hmidi->output = NULL;
1512         spin_unlock_irq (&hmidi->lock);
1513 
1514         return 0;
1515 }
1516 
1517 static struct snd_rawmidi_ops snd_hdsp_midi_output =
1518 {
1519         .open =         snd_hdsp_midi_output_open,
1520         .close =        snd_hdsp_midi_output_close,
1521         .trigger =      snd_hdsp_midi_output_trigger,
1522 };
1523 
1524 static struct snd_rawmidi_ops snd_hdsp_midi_input =
1525 {
1526         .open =         snd_hdsp_midi_input_open,
1527         .close =        snd_hdsp_midi_input_close,
1528         .trigger =      snd_hdsp_midi_input_trigger,
1529 };
1530 
1531 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1532 {
1533         char buf[32];
1534 
1535         hdsp->midi[id].id = id;
1536         hdsp->midi[id].rmidi = NULL;
1537         hdsp->midi[id].input = NULL;
1538         hdsp->midi[id].output = NULL;
1539         hdsp->midi[id].hdsp = hdsp;
1540         hdsp->midi[id].istimer = 0;
1541         hdsp->midi[id].pending = 0;
1542         spin_lock_init (&hdsp->midi[id].lock);
1543 
1544         sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1545         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1546                 return -1;
1547 
1548         sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1549         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1550 
1551         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1552         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1553 
1554         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1555                 SNDRV_RAWMIDI_INFO_INPUT |
1556                 SNDRV_RAWMIDI_INFO_DUPLEX;
1557 
1558         return 0;
1559 }
1560 
1561 /*-----------------------------------------------------------------------------
1562   Control Interface
1563   ----------------------------------------------------------------------------*/
1564 
1565 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1566 {
1567         u32 val = 0;
1568         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1569         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1570         if (val & HDSP_SPDIFProfessional)
1571                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1572         else
1573                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1574         return val;
1575 }
1576 
1577 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1578 {
1579         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1580                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1581         if (val & HDSP_SPDIFProfessional)
1582                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1583         else
1584                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1585 }
1586 
1587 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1588 {
1589         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1590         uinfo->count = 1;
1591         return 0;
1592 }
1593 
1594 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1595 {
1596         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1597 
1598         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1599         return 0;
1600 }
1601 
1602 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1603 {
1604         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1605         int change;
1606         u32 val;
1607 
1608         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1609         spin_lock_irq(&hdsp->lock);
1610         change = val != hdsp->creg_spdif;
1611         hdsp->creg_spdif = val;
1612         spin_unlock_irq(&hdsp->lock);
1613         return change;
1614 }
1615 
1616 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1617 {
1618         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1619         uinfo->count = 1;
1620         return 0;
1621 }
1622 
1623 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1624 {
1625         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1626 
1627         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1628         return 0;
1629 }
1630 
1631 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1632 {
1633         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1634         int change;
1635         u32 val;
1636 
1637         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1638         spin_lock_irq(&hdsp->lock);
1639         change = val != hdsp->creg_spdif_stream;
1640         hdsp->creg_spdif_stream = val;
1641         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1642         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1643         spin_unlock_irq(&hdsp->lock);
1644         return change;
1645 }
1646 
1647 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1648 {
1649         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1650         uinfo->count = 1;
1651         return 0;
1652 }
1653 
1654 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1655 {
1656         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1657         return 0;
1658 }
1659 
1660 #define HDSP_SPDIF_IN(xname, xindex) \
1661 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1662   .name = xname, \
1663   .index = xindex, \
1664   .info = snd_hdsp_info_spdif_in, \
1665   .get = snd_hdsp_get_spdif_in, \
1666   .put = snd_hdsp_put_spdif_in }
1667 
1668 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1669 {
1670         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1671 }
1672 
1673 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1674 {
1675         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1676         hdsp->control_register |= hdsp_encode_spdif_in(in);
1677         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1678         return 0;
1679 }
1680 
1681 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1682 {
1683         static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1684         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1685 
1686         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1687         uinfo->count = 1;
1688         uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1689         if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1690                 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1691         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1692         return 0;
1693 }
1694 
1695 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1696 {
1697         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1698 
1699         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1700         return 0;
1701 }
1702 
1703 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1704 {
1705         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1706         int change;
1707         unsigned int val;
1708 
1709         if (!snd_hdsp_use_is_exclusive(hdsp))
1710                 return -EBUSY;
1711         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1712         spin_lock_irq(&hdsp->lock);
1713         change = val != hdsp_spdif_in(hdsp);
1714         if (change)
1715                 hdsp_set_spdif_input(hdsp, val);
1716         spin_unlock_irq(&hdsp->lock);
1717         return change;
1718 }
1719 
1720 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1721 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1722         .name = xname, \
1723         .private_value = xindex, \
1724         .info = snd_hdsp_info_toggle_setting, \
1725         .get = snd_hdsp_get_toggle_setting, \
1726         .put = snd_hdsp_put_toggle_setting \
1727 }
1728 
1729 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1730 {
1731         return (hdsp->control_register & regmask) ? 1 : 0;
1732 }
1733 
1734 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1735 {
1736         if (out)
1737                 hdsp->control_register |= regmask;
1738         else
1739                 hdsp->control_register &= ~regmask;
1740         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1741 
1742         return 0;
1743 }
1744 
1745 #define snd_hdsp_info_toggle_setting               snd_ctl_boolean_mono_info
1746 
1747 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1748                 struct snd_ctl_elem_value *ucontrol)
1749 {
1750         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1751         u32 regmask = kcontrol->private_value;
1752 
1753         spin_lock_irq(&hdsp->lock);
1754         ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1755         spin_unlock_irq(&hdsp->lock);
1756         return 0;
1757 }
1758 
1759 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1760                 struct snd_ctl_elem_value *ucontrol)
1761 {
1762         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1763         u32 regmask = kcontrol->private_value;
1764         int change;
1765         unsigned int val;
1766 
1767         if (!snd_hdsp_use_is_exclusive(hdsp))
1768                 return -EBUSY;
1769         val = ucontrol->value.integer.value[0] & 1;
1770         spin_lock_irq(&hdsp->lock);
1771         change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1772         if (change)
1773                 hdsp_set_toggle_setting(hdsp, regmask, val);
1774         spin_unlock_irq(&hdsp->lock);
1775         return change;
1776 }
1777 
1778 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1779 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1780   .name = xname, \
1781   .index = xindex, \
1782   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1783   .info = snd_hdsp_info_spdif_sample_rate, \
1784   .get = snd_hdsp_get_spdif_sample_rate \
1785 }
1786 
1787 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1788 {
1789         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1790         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1791 
1792         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1793         uinfo->count = 1;
1794         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1795         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1796                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1797         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1798         return 0;
1799 }
1800 
1801 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1802 {
1803         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1804 
1805         switch (hdsp_spdif_sample_rate(hdsp)) {
1806         case 32000:
1807                 ucontrol->value.enumerated.item[0] = 0;
1808                 break;
1809         case 44100:
1810                 ucontrol->value.enumerated.item[0] = 1;
1811                 break;
1812         case 48000:
1813                 ucontrol->value.enumerated.item[0] = 2;
1814                 break;
1815         case 64000:
1816                 ucontrol->value.enumerated.item[0] = 3;
1817                 break;
1818         case 88200:
1819                 ucontrol->value.enumerated.item[0] = 4;
1820                 break;
1821         case 96000:
1822                 ucontrol->value.enumerated.item[0] = 5;
1823                 break;
1824         case 128000:
1825                 ucontrol->value.enumerated.item[0] = 7;
1826                 break;
1827         case 176400:
1828                 ucontrol->value.enumerated.item[0] = 8;
1829                 break;
1830         case 192000:
1831                 ucontrol->value.enumerated.item[0] = 9;
1832                 break;
1833         default:
1834                 ucontrol->value.enumerated.item[0] = 6;
1835         }
1836         return 0;
1837 }
1838 
1839 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1840 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1841   .name = xname, \
1842   .index = xindex, \
1843   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1844   .info = snd_hdsp_info_system_sample_rate, \
1845   .get = snd_hdsp_get_system_sample_rate \
1846 }
1847 
1848 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1849 {
1850         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1851         uinfo->count = 1;
1852         return 0;
1853 }
1854 
1855 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1856 {
1857         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1858 
1859         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1860         return 0;
1861 }
1862 
1863 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1864 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1865   .name = xname, \
1866   .index = xindex, \
1867   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1868   .info = snd_hdsp_info_autosync_sample_rate, \
1869   .get = snd_hdsp_get_autosync_sample_rate \
1870 }
1871 
1872 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1873 {
1874         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1875         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1876         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1877         uinfo->count = 1;
1878         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1879         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1880                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1881         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1882         return 0;
1883 }
1884 
1885 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1886 {
1887         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1888 
1889         switch (hdsp_external_sample_rate(hdsp)) {
1890         case 32000:
1891                 ucontrol->value.enumerated.item[0] = 0;
1892                 break;
1893         case 44100:
1894                 ucontrol->value.enumerated.item[0] = 1;
1895                 break;
1896         case 48000:
1897                 ucontrol->value.enumerated.item[0] = 2;
1898                 break;
1899         case 64000:
1900                 ucontrol->value.enumerated.item[0] = 3;
1901                 break;
1902         case 88200:
1903                 ucontrol->value.enumerated.item[0] = 4;
1904                 break;
1905         case 96000:
1906                 ucontrol->value.enumerated.item[0] = 5;
1907                 break;
1908         case 128000:
1909                 ucontrol->value.enumerated.item[0] = 7;
1910                 break;
1911         case 176400:
1912                 ucontrol->value.enumerated.item[0] = 8;
1913                 break;
1914         case 192000:
1915                 ucontrol->value.enumerated.item[0] = 9;
1916                 break;
1917         default:
1918                 ucontrol->value.enumerated.item[0] = 6;
1919         }
1920         return 0;
1921 }
1922 
1923 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1924 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1925   .name = xname, \
1926   .index = xindex, \
1927   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1928   .info = snd_hdsp_info_system_clock_mode, \
1929   .get = snd_hdsp_get_system_clock_mode \
1930 }
1931 
1932 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1933 {
1934         if (hdsp->control_register & HDSP_ClockModeMaster)
1935                 return 0;
1936         else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1937                         return 0;
1938         return 1;
1939 }
1940 
1941 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1942 {
1943         static char *texts[] = {"Master", "Slave" };
1944 
1945         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1946         uinfo->count = 1;
1947         uinfo->value.enumerated.items = 2;
1948         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1949                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1950         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1951         return 0;
1952 }
1953 
1954 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1955 {
1956         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1957 
1958         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1959         return 0;
1960 }
1961 
1962 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1963 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1964   .name = xname, \
1965   .index = xindex, \
1966   .info = snd_hdsp_info_clock_source, \
1967   .get = snd_hdsp_get_clock_source, \
1968   .put = snd_hdsp_put_clock_source \
1969 }
1970 
1971 static int hdsp_clock_source(struct hdsp *hdsp)
1972 {
1973         if (hdsp->control_register & HDSP_ClockModeMaster) {
1974                 switch (hdsp->system_sample_rate) {
1975                 case 32000:
1976                         return 1;
1977                 case 44100:
1978                         return 2;
1979                 case 48000:
1980                         return 3;
1981                 case 64000:
1982                         return 4;
1983                 case 88200:
1984                         return 5;
1985                 case 96000:
1986                         return 6;
1987                 case 128000:
1988                         return 7;
1989                 case 176400:
1990                         return 8;
1991                 case 192000:
1992                         return 9;
1993                 default:
1994                         return 3;
1995                 }
1996         } else {
1997                 return 0;
1998         }
1999 }
2000 
2001 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
2002 {
2003         int rate;
2004         switch (mode) {
2005         case HDSP_CLOCK_SOURCE_AUTOSYNC:
2006                 if (hdsp_external_sample_rate(hdsp) != 0) {
2007                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2008                         hdsp->control_register &= ~HDSP_ClockModeMaster;
2009                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2010                         return 0;
2011                     }
2012                 }
2013                 return -1;
2014         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2015                 rate = 32000;
2016                 break;
2017         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2018                 rate = 44100;
2019                 break;
2020         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2021                 rate = 48000;
2022                 break;
2023         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2024                 rate = 64000;
2025                 break;
2026         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2027                 rate = 88200;
2028                 break;
2029         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2030                 rate = 96000;
2031                 break;
2032         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2033                 rate = 128000;
2034                 break;
2035         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2036                 rate = 176400;
2037                 break;
2038         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2039                 rate = 192000;
2040                 break;
2041         default:
2042                 rate = 48000;
2043         }
2044         hdsp->control_register |= HDSP_ClockModeMaster;
2045         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2046         hdsp_set_rate(hdsp, rate, 1);
2047         return 0;
2048 }
2049 
2050 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2051 {
2052         static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2053         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2054 
2055         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2056         uinfo->count = 1;
2057         if (hdsp->io_type == H9632)
2058             uinfo->value.enumerated.items = 10;
2059         else
2060             uinfo->value.enumerated.items = 7;
2061         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2062                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2063         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2064         return 0;
2065 }
2066 
2067 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2068 {
2069         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2070 
2071         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2072         return 0;
2073 }
2074 
2075 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2076 {
2077         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2078         int change;
2079         int val;
2080 
2081         if (!snd_hdsp_use_is_exclusive(hdsp))
2082                 return -EBUSY;
2083         val = ucontrol->value.enumerated.item[0];
2084         if (val < 0) val = 0;
2085         if (hdsp->io_type == H9632) {
2086                 if (val > 9)
2087                         val = 9;
2088         } else {
2089                 if (val > 6)
2090                         val = 6;
2091         }
2092         spin_lock_irq(&hdsp->lock);
2093         if (val != hdsp_clock_source(hdsp))
2094                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2095         else
2096                 change = 0;
2097         spin_unlock_irq(&hdsp->lock);
2098         return change;
2099 }
2100 
2101 #define snd_hdsp_info_clock_source_lock         snd_ctl_boolean_mono_info
2102 
2103 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2104 {
2105         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2106 
2107         ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2108         return 0;
2109 }
2110 
2111 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2112 {
2113         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2114         int change;
2115 
2116         change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2117         if (change)
2118                 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2119         return change;
2120 }
2121 
2122 #define HDSP_DA_GAIN(xname, xindex) \
2123 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2124   .name = xname, \
2125   .index = xindex, \
2126   .info = snd_hdsp_info_da_gain, \
2127   .get = snd_hdsp_get_da_gain, \
2128   .put = snd_hdsp_put_da_gain \
2129 }
2130 
2131 static int hdsp_da_gain(struct hdsp *hdsp)
2132 {
2133         switch (hdsp->control_register & HDSP_DAGainMask) {
2134         case HDSP_DAGainHighGain:
2135                 return 0;
2136         case HDSP_DAGainPlus4dBu:
2137                 return 1;
2138         case HDSP_DAGainMinus10dBV:
2139                 return 2;
2140         default:
2141                 return 1;
2142         }
2143 }
2144 
2145 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2146 {
2147         hdsp->control_register &= ~HDSP_DAGainMask;
2148         switch (mode) {
2149         case 0:
2150                 hdsp->control_register |= HDSP_DAGainHighGain;
2151                 break;
2152         case 1:
2153                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2154                 break;
2155         case 2:
2156                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2157                 break;
2158         default:
2159                 return -1;
2160 
2161         }
2162         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2163         return 0;
2164 }
2165 
2166 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2167 {
2168         static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2169 
2170         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2171         uinfo->count = 1;
2172         uinfo->value.enumerated.items = 3;
2173         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2174                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2175         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2176         return 0;
2177 }
2178 
2179 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2180 {
2181         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2182 
2183         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2184         return 0;
2185 }
2186 
2187 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2188 {
2189         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2190         int change;
2191         int val;
2192 
2193         if (!snd_hdsp_use_is_exclusive(hdsp))
2194                 return -EBUSY;
2195         val = ucontrol->value.enumerated.item[0];
2196         if (val < 0) val = 0;
2197         if (val > 2) val = 2;
2198         spin_lock_irq(&hdsp->lock);
2199         if (val != hdsp_da_gain(hdsp))
2200                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2201         else
2202                 change = 0;
2203         spin_unlock_irq(&hdsp->lock);
2204         return change;
2205 }
2206 
2207 #define HDSP_AD_GAIN(xname, xindex) \
2208 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2209   .name = xname, \
2210   .index = xindex, \
2211   .info = snd_hdsp_info_ad_gain, \
2212   .get = snd_hdsp_get_ad_gain, \
2213   .put = snd_hdsp_put_ad_gain \
2214 }
2215 
2216 static int hdsp_ad_gain(struct hdsp *hdsp)
2217 {
2218         switch (hdsp->control_register & HDSP_ADGainMask) {
2219         case HDSP_ADGainMinus10dBV:
2220                 return 0;
2221         case HDSP_ADGainPlus4dBu:
2222                 return 1;
2223         case HDSP_ADGainLowGain:
2224                 return 2;
2225         default:
2226                 return 1;
2227         }
2228 }
2229 
2230 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2231 {
2232         hdsp->control_register &= ~HDSP_ADGainMask;
2233         switch (mode) {
2234         case 0:
2235                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2236                 break;
2237         case 1:
2238                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2239                 break;
2240         case 2:
2241                 hdsp->control_register |= HDSP_ADGainLowGain;
2242                 break;
2243         default:
2244                 return -1;
2245 
2246         }
2247         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2248         return 0;
2249 }
2250 
2251 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2252 {
2253         static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2254 
2255         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2256         uinfo->count = 1;
2257         uinfo->value.enumerated.items = 3;
2258         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2259                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2260         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2261         return 0;
2262 }
2263 
2264 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2265 {
2266         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2267 
2268         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2269         return 0;
2270 }
2271 
2272 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2273 {
2274         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2275         int change;
2276         int val;
2277 
2278         if (!snd_hdsp_use_is_exclusive(hdsp))
2279                 return -EBUSY;
2280         val = ucontrol->value.enumerated.item[0];
2281         if (val < 0) val = 0;
2282         if (val > 2) val = 2;
2283         spin_lock_irq(&hdsp->lock);
2284         if (val != hdsp_ad_gain(hdsp))
2285                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2286         else
2287                 change = 0;
2288         spin_unlock_irq(&hdsp->lock);
2289         return change;
2290 }
2291 
2292 #define HDSP_PHONE_GAIN(xname, xindex) \
2293 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2294   .name = xname, \
2295   .index = xindex, \
2296   .info = snd_hdsp_info_phone_gain, \
2297   .get = snd_hdsp_get_phone_gain, \
2298   .put = snd_hdsp_put_phone_gain \
2299 }
2300 
2301 static int hdsp_phone_gain(struct hdsp *hdsp)
2302 {
2303         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2304         case HDSP_PhoneGain0dB:
2305                 return 0;
2306         case HDSP_PhoneGainMinus6dB:
2307                 return 1;
2308         case HDSP_PhoneGainMinus12dB:
2309                 return 2;
2310         default:
2311                 return 0;
2312         }
2313 }
2314 
2315 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2316 {
2317         hdsp->control_register &= ~HDSP_PhoneGainMask;
2318         switch (mode) {
2319         case 0:
2320                 hdsp->control_register |= HDSP_PhoneGain0dB;
2321                 break;
2322         case 1:
2323                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2324                 break;
2325         case 2:
2326                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2327                 break;
2328         default:
2329                 return -1;
2330 
2331         }
2332         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2333         return 0;
2334 }
2335 
2336 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2337 {
2338         static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2339 
2340         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2341         uinfo->count = 1;
2342         uinfo->value.enumerated.items = 3;
2343         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2344                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2345         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2346         return 0;
2347 }
2348 
2349 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2350 {
2351         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2352 
2353         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2354         return 0;
2355 }
2356 
2357 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2358 {
2359         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2360         int change;
2361         int val;
2362 
2363         if (!snd_hdsp_use_is_exclusive(hdsp))
2364                 return -EBUSY;
2365         val = ucontrol->value.enumerated.item[0];
2366         if (val < 0) val = 0;
2367         if (val > 2) val = 2;
2368         spin_lock_irq(&hdsp->lock);
2369         if (val != hdsp_phone_gain(hdsp))
2370                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2371         else
2372                 change = 0;
2373         spin_unlock_irq(&hdsp->lock);
2374         return change;
2375 }
2376 
2377 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2378 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2379   .name = xname, \
2380   .index = xindex, \
2381   .info = snd_hdsp_info_pref_sync_ref, \
2382   .get = snd_hdsp_get_pref_sync_ref, \
2383   .put = snd_hdsp_put_pref_sync_ref \
2384 }
2385 
2386 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2387 {
2388         /* Notice that this looks at the requested sync source,
2389            not the one actually in use.
2390         */
2391 
2392         switch (hdsp->control_register & HDSP_SyncRefMask) {
2393         case HDSP_SyncRef_ADAT1:
2394                 return HDSP_SYNC_FROM_ADAT1;
2395         case HDSP_SyncRef_ADAT2:
2396                 return HDSP_SYNC_FROM_ADAT2;
2397         case HDSP_SyncRef_ADAT3:
2398                 return HDSP_SYNC_FROM_ADAT3;
2399         case HDSP_SyncRef_SPDIF:
2400                 return HDSP_SYNC_FROM_SPDIF;
2401         case HDSP_SyncRef_WORD:
2402                 return HDSP_SYNC_FROM_WORD;
2403         case HDSP_SyncRef_ADAT_SYNC:
2404                 return HDSP_SYNC_FROM_ADAT_SYNC;
2405         default:
2406                 return HDSP_SYNC_FROM_WORD;
2407         }
2408         return 0;
2409 }
2410 
2411 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2412 {
2413         hdsp->control_register &= ~HDSP_SyncRefMask;
2414         switch (pref) {
2415         case HDSP_SYNC_FROM_ADAT1:
2416                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2417                 break;
2418         case HDSP_SYNC_FROM_ADAT2:
2419                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2420                 break;
2421         case HDSP_SYNC_FROM_ADAT3:
2422                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2423                 break;
2424         case HDSP_SYNC_FROM_SPDIF:
2425                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2426                 break;
2427         case HDSP_SYNC_FROM_WORD:
2428                 hdsp->control_register |= HDSP_SyncRef_WORD;
2429                 break;
2430         case HDSP_SYNC_FROM_ADAT_SYNC:
2431                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2432                 break;
2433         default:
2434                 return -1;
2435         }
2436         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2437         return 0;
2438 }
2439 
2440 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2441 {
2442         static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2443         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2444 
2445         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2446         uinfo->count = 1;
2447 
2448         switch (hdsp->io_type) {
2449         case Digiface:
2450         case H9652:
2451                 uinfo->value.enumerated.items = 6;
2452                 break;
2453         case Multiface:
2454                 uinfo->value.enumerated.items = 4;
2455                 break;
2456         case H9632:
2457                 uinfo->value.enumerated.items = 3;
2458                 break;
2459         default:
2460                 return -EINVAL;
2461         }
2462 
2463         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2464                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2465         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2466         return 0;
2467 }
2468 
2469 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2470 {
2471         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2472 
2473         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2474         return 0;
2475 }
2476 
2477 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2478 {
2479         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2480         int change, max;
2481         unsigned int val;
2482 
2483         if (!snd_hdsp_use_is_exclusive(hdsp))
2484                 return -EBUSY;
2485 
2486         switch (hdsp->io_type) {
2487         case Digiface:
2488         case H9652:
2489                 max = 6;
2490                 break;
2491         case Multiface:
2492                 max = 4;
2493                 break;
2494         case H9632:
2495                 max = 3;
2496                 break;
2497         default:
2498                 return -EIO;
2499         }
2500 
2501         val = ucontrol->value.enumerated.item[0] % max;
2502         spin_lock_irq(&hdsp->lock);
2503         change = (int)val != hdsp_pref_sync_ref(hdsp);
2504         hdsp_set_pref_sync_ref(hdsp, val);
2505         spin_unlock_irq(&hdsp->lock);
2506         return change;
2507 }
2508 
2509 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2510 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2511   .name = xname, \
2512   .index = xindex, \
2513   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2514   .info = snd_hdsp_info_autosync_ref, \
2515   .get = snd_hdsp_get_autosync_ref, \
2516 }
2517 
2518 static int hdsp_autosync_ref(struct hdsp *hdsp)
2519 {
2520         /* This looks at the autosync selected sync reference */
2521         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2522 
2523         switch (status2 & HDSP_SelSyncRefMask) {
2524         case HDSP_SelSyncRef_WORD:
2525                 return HDSP_AUTOSYNC_FROM_WORD;
2526         case HDSP_SelSyncRef_ADAT_SYNC:
2527                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2528         case HDSP_SelSyncRef_SPDIF:
2529                 return HDSP_AUTOSYNC_FROM_SPDIF;
2530         case HDSP_SelSyncRefMask:
2531                 return HDSP_AUTOSYNC_FROM_NONE;
2532         case HDSP_SelSyncRef_ADAT1:
2533                 return HDSP_AUTOSYNC_FROM_ADAT1;
2534         case HDSP_SelSyncRef_ADAT2:
2535                 return HDSP_AUTOSYNC_FROM_ADAT2;
2536         case HDSP_SelSyncRef_ADAT3:
2537                 return HDSP_AUTOSYNC_FROM_ADAT3;
2538         default:
2539                 return HDSP_AUTOSYNC_FROM_WORD;
2540         }
2541         return 0;
2542 }
2543 
2544 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2545 {
2546         static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2547 
2548         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2549         uinfo->count = 1;
2550         uinfo->value.enumerated.items = 7;
2551         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2552                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2553         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2554         return 0;
2555 }
2556 
2557 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2558 {
2559         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2560 
2561         ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2562         return 0;
2563 }
2564 
2565 #define HDSP_PRECISE_POINTER(xname, xindex) \
2566 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2567   .name = xname, \
2568   .index = xindex, \
2569   .info = snd_hdsp_info_precise_pointer, \
2570   .get = snd_hdsp_get_precise_pointer, \
2571   .put = snd_hdsp_put_precise_pointer \
2572 }
2573 
2574 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2575 {
2576         if (precise)
2577                 hdsp->precise_ptr = 1;
2578         else
2579                 hdsp->precise_ptr = 0;
2580         return 0;
2581 }
2582 
2583 #define snd_hdsp_info_precise_pointer           snd_ctl_boolean_mono_info
2584 
2585 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2586 {
2587         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2588 
2589         spin_lock_irq(&hdsp->lock);
2590         ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2591         spin_unlock_irq(&hdsp->lock);
2592         return 0;
2593 }
2594 
2595 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2596 {
2597         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2598         int change;
2599         unsigned int val;
2600 
2601         if (!snd_hdsp_use_is_exclusive(hdsp))
2602                 return -EBUSY;
2603         val = ucontrol->value.integer.value[0] & 1;
2604         spin_lock_irq(&hdsp->lock);
2605         change = (int)val != hdsp->precise_ptr;
2606         hdsp_set_precise_pointer(hdsp, val);
2607         spin_unlock_irq(&hdsp->lock);
2608         return change;
2609 }
2610 
2611 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2612 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2613   .name = xname, \
2614   .index = xindex, \
2615   .info = snd_hdsp_info_use_midi_tasklet, \
2616   .get = snd_hdsp_get_use_midi_tasklet, \
2617   .put = snd_hdsp_put_use_midi_tasklet \
2618 }
2619 
2620 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2621 {
2622         if (use_tasklet)
2623                 hdsp->use_midi_tasklet = 1;
2624         else
2625                 hdsp->use_midi_tasklet = 0;
2626         return 0;
2627 }
2628 
2629 #define snd_hdsp_info_use_midi_tasklet          snd_ctl_boolean_mono_info
2630 
2631 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2632 {
2633         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2634 
2635         spin_lock_irq(&hdsp->lock);
2636         ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2637         spin_unlock_irq(&hdsp->lock);
2638         return 0;
2639 }
2640 
2641 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2642 {
2643         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2644         int change;
2645         unsigned int val;
2646 
2647         if (!snd_hdsp_use_is_exclusive(hdsp))
2648                 return -EBUSY;
2649         val = ucontrol->value.integer.value[0] & 1;
2650         spin_lock_irq(&hdsp->lock);
2651         change = (int)val != hdsp->use_midi_tasklet;
2652         hdsp_set_use_midi_tasklet(hdsp, val);
2653         spin_unlock_irq(&hdsp->lock);
2654         return change;
2655 }
2656 
2657 #define HDSP_MIXER(xname, xindex) \
2658 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2659   .name = xname, \
2660   .index = xindex, \
2661   .device = 0, \
2662   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2663                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2664   .info = snd_hdsp_info_mixer, \
2665   .get = snd_hdsp_get_mixer, \
2666   .put = snd_hdsp_put_mixer \
2667 }
2668 
2669 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2670 {
2671         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2672         uinfo->count = 3;
2673         uinfo->value.integer.min = 0;
2674         uinfo->value.integer.max = 65536;
2675         uinfo->value.integer.step = 1;
2676         return 0;
2677 }
2678 
2679 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2680 {
2681         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2682         int source;
2683         int destination;
2684         int addr;
2685 
2686         source = ucontrol->value.integer.value[0];
2687         destination = ucontrol->value.integer.value[1];
2688 
2689         if (source >= hdsp->max_channels)
2690                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2691         else
2692                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2693 
2694         spin_lock_irq(&hdsp->lock);
2695         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2696         spin_unlock_irq(&hdsp->lock);
2697         return 0;
2698 }
2699 
2700 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2701 {
2702         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2703         int change;
2704         int source;
2705         int destination;
2706         int gain;
2707         int addr;
2708 
2709         if (!snd_hdsp_use_is_exclusive(hdsp))
2710                 return -EBUSY;
2711 
2712         source = ucontrol->value.integer.value[0];
2713         destination = ucontrol->value.integer.value[1];
2714 
2715         if (source >= hdsp->max_channels)
2716                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2717         else
2718                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2719 
2720         gain = ucontrol->value.integer.value[2];
2721 
2722         spin_lock_irq(&hdsp->lock);
2723         change = gain != hdsp_read_gain(hdsp, addr);
2724         if (change)
2725                 hdsp_write_gain(hdsp, addr, gain);
2726         spin_unlock_irq(&hdsp->lock);
2727         return change;
2728 }
2729 
2730 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2731 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2732   .name = xname, \
2733   .index = xindex, \
2734   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2735   .info = snd_hdsp_info_sync_check, \
2736   .get = snd_hdsp_get_wc_sync_check \
2737 }
2738 
2739 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2740 {
2741         static char *texts[] = {"No Lock", "Lock", "Sync" };
2742         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2743         uinfo->count = 1;
2744         uinfo->value.enumerated.items = 3;
2745         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2746                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2747         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2748         return 0;
2749 }
2750 
2751 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2752 {
2753         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2754         if (status2 & HDSP_wc_lock) {
2755                 if (status2 & HDSP_wc_sync)
2756                         return 2;
2757                 else
2758                          return 1;
2759         } else
2760                 return 0;
2761         return 0;
2762 }
2763 
2764 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2765 {
2766         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2767 
2768         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2769         return 0;
2770 }
2771 
2772 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2773 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2774   .name = xname, \
2775   .index = xindex, \
2776   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2777   .info = snd_hdsp_info_sync_check, \
2778   .get = snd_hdsp_get_spdif_sync_check \
2779 }
2780 
2781 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2782 {
2783         int status = hdsp_read(hdsp, HDSP_statusRegister);
2784         if (status & HDSP_SPDIFErrorFlag)
2785                 return 0;
2786         else {
2787                 if (status & HDSP_SPDIFSync)
2788                         return 2;
2789                 else
2790                         return 1;
2791         }
2792         return 0;
2793 }
2794 
2795 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2796 {
2797         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2798 
2799         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2800         return 0;
2801 }
2802 
2803 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2804 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2805   .name = xname, \
2806   .index = xindex, \
2807   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2808   .info = snd_hdsp_info_sync_check, \
2809   .get = snd_hdsp_get_adatsync_sync_check \
2810 }
2811 
2812 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2813 {
2814         int status = hdsp_read(hdsp, HDSP_statusRegister);
2815         if (status & HDSP_TimecodeLock) {
2816                 if (status & HDSP_TimecodeSync)
2817                         return 2;
2818                 else
2819                         return 1;
2820         } else
2821                 return 0;
2822 }
2823 
2824 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2825 {
2826         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2827 
2828         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2829         return 0;
2830 }
2831 
2832 #define HDSP_ADAT_SYNC_CHECK \
2833 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2834   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2835   .info = snd_hdsp_info_sync_check, \
2836   .get = snd_hdsp_get_adat_sync_check \
2837 }
2838 
2839 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2840 {
2841         int status = hdsp_read(hdsp, HDSP_statusRegister);
2842 
2843         if (status & (HDSP_Lock0>>idx)) {
2844                 if (status & (HDSP_Sync0>>idx))
2845                         return 2;
2846                 else
2847                         return 1;
2848         } else
2849                 return 0;
2850 }
2851 
2852 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2853 {
2854         int offset;
2855         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2856 
2857         offset = ucontrol->id.index - 1;
2858         snd_BUG_ON(offset < 0);
2859 
2860         switch (hdsp->io_type) {
2861         case Digiface:
2862         case H9652:
2863                 if (offset >= 3)
2864                         return -EINVAL;
2865                 break;
2866         case Multiface:
2867         case H9632:
2868                 if (offset >= 1)
2869                         return -EINVAL;
2870                 break;
2871         default:
2872                 return -EIO;
2873         }
2874 
2875         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2876         return 0;
2877 }
2878 
2879 #define HDSP_DDS_OFFSET(xname, xindex) \
2880 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2881   .name = xname, \
2882   .index = xindex, \
2883   .info = snd_hdsp_info_dds_offset, \
2884   .get = snd_hdsp_get_dds_offset, \
2885   .put = snd_hdsp_put_dds_offset \
2886 }
2887 
2888 static int hdsp_dds_offset(struct hdsp *hdsp)
2889 {
2890         u64 n;
2891         unsigned int dds_value = hdsp->dds_value;
2892         int system_sample_rate = hdsp->system_sample_rate;
2893 
2894         if (!dds_value)
2895                 return 0;
2896 
2897         n = DDS_NUMERATOR;
2898         /*
2899          * dds_value = n / rate
2900          * rate = n / dds_value
2901          */
2902         n = div_u64(n, dds_value);
2903         if (system_sample_rate >= 112000)
2904                 n *= 4;
2905         else if (system_sample_rate >= 56000)
2906                 n *= 2;
2907         return ((int)n) - system_sample_rate;
2908 }
2909 
2910 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2911 {
2912         int rate = hdsp->system_sample_rate + offset_hz;
2913         hdsp_set_dds_value(hdsp, rate);
2914         return 0;
2915 }
2916 
2917 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2918 {
2919         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2920         uinfo->count = 1;
2921         uinfo->value.integer.min = -5000;
2922         uinfo->value.integer.max = 5000;
2923         return 0;
2924 }
2925 
2926 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2927 {
2928         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2929 
2930         ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp);
2931         return 0;
2932 }
2933 
2934 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2935 {
2936         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2937         int change;
2938         int val;
2939 
2940         if (!snd_hdsp_use_is_exclusive(hdsp))
2941                 return -EBUSY;
2942         val = ucontrol->value.enumerated.item[0];
2943         spin_lock_irq(&hdsp->lock);
2944         if (val != hdsp_dds_offset(hdsp))
2945                 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2946         else
2947                 change = 0;
2948         spin_unlock_irq(&hdsp->lock);
2949         return change;
2950 }
2951 
2952 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2953 HDSP_DA_GAIN("DA Gain", 0),
2954 HDSP_AD_GAIN("AD Gain", 0),
2955 HDSP_PHONE_GAIN("Phones Gain", 0),
2956 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2957 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2958 };
2959 
2960 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2961 {
2962         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2963         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2964         .info =         snd_hdsp_control_spdif_info,
2965         .get =          snd_hdsp_control_spdif_get,
2966         .put =          snd_hdsp_control_spdif_put,
2967 },
2968 {
2969         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2970         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2971         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2972         .info =         snd_hdsp_control_spdif_stream_info,
2973         .get =          snd_hdsp_control_spdif_stream_get,
2974         .put =          snd_hdsp_control_spdif_stream_put,
2975 },
2976 {
2977         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2978         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2979         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2980         .info =         snd_hdsp_control_spdif_mask_info,
2981         .get =          snd_hdsp_control_spdif_mask_get,
2982         .private_value = IEC958_AES0_NONAUDIO |
2983                          IEC958_AES0_PROFESSIONAL |
2984                          IEC958_AES0_CON_EMPHASIS,
2985 },
2986 {
2987         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2988         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2989         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2990         .info =         snd_hdsp_control_spdif_mask_info,
2991         .get =          snd_hdsp_control_spdif_mask_get,
2992         .private_value = IEC958_AES0_NONAUDIO |
2993                          IEC958_AES0_PROFESSIONAL |
2994                          IEC958_AES0_PRO_EMPHASIS,
2995 },
2996 HDSP_MIXER("Mixer", 0),
2997 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2998 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2999 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
3000 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
3001 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
3002 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3003 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3004 {
3005         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3006         .name = "Sample Clock Source Locking",
3007         .info = snd_hdsp_info_clock_source_lock,
3008         .get = snd_hdsp_get_clock_source_lock,
3009         .put = snd_hdsp_put_clock_source_lock,
3010 },
3011 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3012 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3013 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3014 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3015 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3016 /* 'External Rate' complies with the alsa control naming scheme */
3017 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3018 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3019 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3020 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3021 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
3022 HDSP_PRECISE_POINTER("Precise Pointer", 0),
3023 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
3024 };
3025 
3026 
3027 static int hdsp_rpm_input12(struct hdsp *hdsp)
3028 {
3029         switch (hdsp->control_register & HDSP_RPM_Inp12) {
3030         case HDSP_RPM_Inp12_Phon_6dB:
3031                 return 0;
3032         case HDSP_RPM_Inp12_Phon_n6dB:
3033                 return 2;
3034         case HDSP_RPM_Inp12_Line_0dB:
3035                 return 3;
3036         case HDSP_RPM_Inp12_Line_n6dB:
3037                 return 4;
3038         }
3039         return 1;
3040 }
3041 
3042 
3043 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3044 {
3045         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3046 
3047         ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
3048         return 0;
3049 }
3050 
3051 
3052 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
3053 {
3054         hdsp->control_register &= ~HDSP_RPM_Inp12;
3055         switch (mode) {
3056         case 0:
3057                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
3058                 break;
3059         case 1:
3060                 break;
3061         case 2:
3062                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3063                 break;
3064         case 3:
3065                 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3066                 break;
3067         case 4:
3068                 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3069                 break;
3070         default:
3071                 return -1;
3072         }
3073 
3074         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3075         return 0;
3076 }
3077 
3078 
3079 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3080 {
3081         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3082         int change;
3083         int val;
3084 
3085         if (!snd_hdsp_use_is_exclusive(hdsp))
3086                 return -EBUSY;
3087         val = ucontrol->value.enumerated.item[0];
3088         if (val < 0)
3089                 val = 0;
3090         if (val > 4)
3091                 val = 4;
3092         spin_lock_irq(&hdsp->lock);
3093         if (val != hdsp_rpm_input12(hdsp))
3094                 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3095         else
3096                 change = 0;
3097         spin_unlock_irq(&hdsp->lock);
3098         return change;
3099 }
3100 
3101 
3102 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3103 {
3104         static char *texts[] = {"Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"};
3105 
3106         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3107         uinfo->count = 1;
3108         uinfo->value.enumerated.items = 5;
3109         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3110                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
3111         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
3112         return 0;
3113 }
3114 
3115 
3116 static int hdsp_rpm_input34(struct hdsp *hdsp)
3117 {
3118         switch (hdsp->control_register & HDSP_RPM_Inp34) {
3119         case HDSP_RPM_Inp34_Phon_6dB:
3120                 return 0;
3121         case HDSP_RPM_Inp34_Phon_n6dB:
3122                 return 2;
3123         case HDSP_RPM_Inp34_Line_0dB:
3124                 return 3;
3125         case HDSP_RPM_Inp34_Line_n6dB:
3126                 return 4;
3127         }
3128         return 1;
3129 }
3130 
3131 
3132 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3133 {
3134         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3135 
3136         ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3137         return 0;
3138 }
3139 
3140 
3141 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3142 {
3143         hdsp->control_register &= ~HDSP_RPM_Inp34;
3144         switch (mode) {
3145         case 0:
3146                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3147                 break;
3148         case 1:
3149                 break;
3150         case 2:
3151                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3152                 break;
3153         case 3:
3154                 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3155                 break;
3156         case 4:
3157                 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3158                 break;
3159         default:
3160                 return -1;
3161         }
3162 
3163         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3164         return 0;
3165 }
3166 
3167 
3168 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3169 {
3170         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3171         int change;
3172         int val;
3173 
3174         if (!snd_hdsp_use_is_exclusive(hdsp))
3175                 return -EBUSY;
3176         val = ucontrol->value.enumerated.item[0];
3177         if (val < 0)
3178                 val = 0;
3179         if (val > 4)
3180                 val = 4;
3181         spin_lock_irq(&hdsp->lock);
3182         if (val != hdsp_rpm_input34(hdsp))
3183                 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3184         else
3185                 change = 0;
3186         spin_unlock_irq(&hdsp->lock);
3187         return change;
3188 }
3189 
3190 
3191 /* RPM Bypass switch */
3192 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3193 {
3194         return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3195 }
3196 
3197 
3198 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3199 {
3200         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3201 
3202         ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3203         return 0;
3204 }
3205 
3206 
3207 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3208 {
3209         if (on)
3210                 hdsp->control_register |= HDSP_RPM_Bypass;
3211         else
3212                 hdsp->control_register &= ~HDSP_RPM_Bypass;
3213         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3214         return 0;
3215 }
3216 
3217 
3218 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3219 {
3220         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3221         int change;
3222         unsigned int val;
3223 
3224         if (!snd_hdsp_use_is_exclusive(hdsp))
3225                 return -EBUSY;
3226         val = ucontrol->value.integer.value[0] & 1;
3227         spin_lock_irq(&hdsp->lock);
3228         change = (int)val != hdsp_rpm_bypass(hdsp);
3229         hdsp_set_rpm_bypass(hdsp, val);
3230         spin_unlock_irq(&hdsp->lock);
3231         return change;
3232 }
3233 
3234 
3235 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3236 {
3237         static char *texts[] = {"On", "Off"};
3238 
3239         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3240         uinfo->count = 1;
3241         uinfo->value.enumerated.items = 2;
3242         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3243                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
3244         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
3245         return 0;
3246 }
3247 
3248 
3249 /* RPM Disconnect switch */
3250 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3251 {
3252         return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3253 }
3254 
3255 
3256 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3257 {
3258         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3259 
3260         ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3261         return 0;
3262 }
3263 
3264 
3265 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3266 {
3267         if (on)
3268                 hdsp->control_register |= HDSP_RPM_Disconnect;
3269         else
3270                 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3271         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3272         return 0;
3273 }
3274 
3275 
3276 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3277 {
3278         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3279         int change;
3280         unsigned int val;
3281 
3282         if (!snd_hdsp_use_is_exclusive(hdsp))
3283                 return -EBUSY;
3284         val = ucontrol->value.integer.value[0] & 1;
3285         spin_lock_irq(&hdsp->lock);
3286         change = (int)val != hdsp_rpm_disconnect(hdsp);
3287         hdsp_set_rpm_disconnect(hdsp, val);
3288         spin_unlock_irq(&hdsp->lock);
3289         return change;
3290 }
3291 
3292 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3293 {
3294         static char *texts[] = {"On", "Off"};
3295 
3296         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3297         uinfo->count = 1;
3298         uinfo->value.enumerated.items = 2;
3299         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3300                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
3301         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
3302         return 0;
3303 }
3304 
3305 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3306         {
3307                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3308                 .name = "RPM Bypass",
3309                 .get = snd_hdsp_get_rpm_bypass,
3310                 .put = snd_hdsp_put_rpm_bypass,
3311                 .info = snd_hdsp_info_rpm_bypass
3312         },
3313         {
3314                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3315                 .name = "RPM Disconnect",
3316                 .get = snd_hdsp_get_rpm_disconnect,
3317                 .put = snd_hdsp_put_rpm_disconnect,
3318                 .info = snd_hdsp_info_rpm_disconnect
3319         },
3320         {
3321                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3322                 .name = "Input 1/2",
3323                 .get = snd_hdsp_get_rpm_input12,
3324                 .put = snd_hdsp_put_rpm_input12,
3325                 .info = snd_hdsp_info_rpm_input
3326         },
3327         {
3328                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3329                 .name = "Input 3/4",
3330                 .get = snd_hdsp_get_rpm_input34,
3331                 .put = snd_hdsp_put_rpm_input34,
3332                 .info = snd_hdsp_info_rpm_input
3333         },
3334         HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3335         HDSP_MIXER("Mixer", 0)
3336 };
3337 
3338 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3339         HDSP_TOGGLE_SETTING("Analog Extension Board",
3340                         HDSP_AnalogExtensionBoard);
3341 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3342 
3343 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3344 {
3345         unsigned int idx;
3346         int err;
3347         struct snd_kcontrol *kctl;
3348 
3349         if (hdsp->io_type == RPM) {
3350                 /* RPM Bypass, Disconnect and Input switches */
3351                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3352                         err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3353                         if (err < 0)
3354                                 return err;
3355                 }
3356                 return 0;
3357         }
3358 
3359         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3360                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3361                         return err;
3362                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3363                         hdsp->spdif_ctl = kctl;
3364         }
3365 
3366         /* ADAT SyncCheck status */
3367         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3368         snd_hdsp_adat_sync_check.index = 1;
3369         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3370                 return err;
3371         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3372                 for (idx = 1; idx < 3; ++idx) {
3373                         snd_hdsp_adat_sync_check.index = idx+1;
3374                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3375                                 return err;
3376                 }
3377         }
3378 
3379         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3380         if (hdsp->io_type == H9632) {
3381                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3382                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3383                                 return err;
3384                 }
3385         }
3386 
3387         /* AEB control for H96xx card */
3388         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3389                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3390                                 return err;
3391         }
3392 
3393         return 0;
3394 }
3395 
3396 /*------------------------------------------------------------
3397    /proc interface
3398  ------------------------------------------------------------*/
3399 
3400 static void
3401 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3402 {
3403         struct hdsp *hdsp = entry->private_data;
3404         unsigned int status;
3405         unsigned int status2;
3406         char *pref_sync_ref;
3407         char *autosync_ref;
3408         char *system_clock_mode;
3409         char *clock_source;
3410         int x;
3411 
3412         status = hdsp_read(hdsp, HDSP_statusRegister);
3413         status2 = hdsp_read(hdsp, HDSP_status2Register);
3414 
3415         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3416                     hdsp->card->number + 1);
3417         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3418                     hdsp->capture_buffer, hdsp->playback_buffer);
3419         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3420                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3421         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3422         snd_iprintf(buffer, "Control2 register: 0x%x\n",
3423                     hdsp->control2_register);
3424         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3425         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3426 
3427         if (hdsp_check_for_iobox(hdsp)) {
3428                 snd_iprintf(buffer, "No I/O box connected.\n"
3429                             "Please connect one and upload firmware.\n");
3430                 return;
3431         }
3432 
3433         if (hdsp_check_for_firmware(hdsp, 0)) {
3434                 if (hdsp->state & HDSP_FirmwareCached) {
3435                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3436                                 snd_iprintf(buffer, "Firmware loading from "
3437                                             "cache failed, "
3438                                             "please upload manually.\n");
3439                                 return;
3440                         }
3441                 } else {
3442                         int err = -EINVAL;
3443                         err = hdsp_request_fw_loader(hdsp);
3444                         if (err < 0) {
3445                                 snd_iprintf(buffer,
3446                                             "No firmware loaded nor cached, "
3447                                             "please upload firmware.\n");
3448                                 return;
3449                         }
3450                 }
3451         }
3452 
3453         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3454         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3455         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3456         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3457         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3458         snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3459 
3460         snd_iprintf(buffer, "\n");
3461 
3462         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3463 
3464         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3465         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3466         snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3467         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3468 
3469         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3470 
3471         snd_iprintf(buffer, "\n");
3472 
3473         switch (hdsp_clock_source(hdsp)) {
3474         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3475                 clock_source = "AutoSync";
3476                 break;
3477         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3478                 clock_source = "Internal 32 kHz";
3479                 break;
3480         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3481                 clock_source = "Internal 44.1 kHz";
3482                 break;
3483         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3484                 clock_source = "Internal 48 kHz";
3485                 break;
3486         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3487                 clock_source = "Internal 64 kHz";
3488                 break;
3489         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3490                 clock_source = "Internal 88.2 kHz";
3491                 break;
3492         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3493                 clock_source = "Internal 96 kHz";
3494                 break;
3495         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3496                 clock_source = "Internal 128 kHz";
3497                 break;
3498         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3499                 clock_source = "Internal 176.4 kHz";
3500                 break;
3501                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3502                 clock_source = "Internal 192 kHz";
3503                 break;
3504         default:
3505                 clock_source = "Error";
3506         }
3507         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3508 
3509         if (hdsp_system_clock_mode(hdsp))
3510                 system_clock_mode = "Slave";
3511         else
3512                 system_clock_mode = "Master";
3513 
3514         switch (hdsp_pref_sync_ref (hdsp)) {
3515         case HDSP_SYNC_FROM_WORD:
3516                 pref_sync_ref = "Word Clock";
3517                 break;
3518         case HDSP_SYNC_FROM_ADAT_SYNC:
3519                 pref_sync_ref = "ADAT Sync";
3520                 break;
3521         case HDSP_SYNC_FROM_SPDIF:
3522                 pref_sync_ref = "SPDIF";
3523                 break;
3524         case HDSP_SYNC_FROM_ADAT1:
3525                 pref_sync_ref = "ADAT1";
3526                 break;
3527         case HDSP_SYNC_FROM_ADAT2:
3528                 pref_sync_ref = "ADAT2";
3529                 break;
3530         case HDSP_SYNC_FROM_ADAT3:
3531                 pref_sync_ref = "ADAT3";
3532                 break;
3533         default:
3534                 pref_sync_ref = "Word Clock";
3535                 break;
3536         }
3537         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3538 
3539         switch (hdsp_autosync_ref (hdsp)) {
3540         case HDSP_AUTOSYNC_FROM_WORD:
3541                 autosync_ref = "Word Clock";
3542                 break;
3543         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3544                 autosync_ref = "ADAT Sync";
3545                 break;
3546         case HDSP_AUTOSYNC_FROM_SPDIF:
3547                 autosync_ref = "SPDIF";
3548                 break;
3549         case HDSP_AUTOSYNC_FROM_NONE:
3550                 autosync_ref = "None";
3551                 break;
3552         case HDSP_AUTOSYNC_FROM_ADAT1:
3553                 autosync_ref = "ADAT1";
3554                 break;
3555         case HDSP_AUTOSYNC_FROM_ADAT2:
3556                 autosync_ref = "ADAT2";
3557                 break;
3558         case HDSP_AUTOSYNC_FROM_ADAT3:
3559                 autosync_ref = "ADAT3";
3560                 break;
3561         default:
3562                 autosync_ref = "---";
3563                 break;
3564         }
3565         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3566 
3567         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3568 
3569         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3570 
3571         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3572         snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3573 
3574         snd_iprintf(buffer, "\n");
3575 
3576         if (hdsp->io_type != RPM) {
3577                 switch (hdsp_spdif_in(hdsp)) {
3578                 case HDSP_SPDIFIN_OPTICAL:
3579                         snd_iprintf(buffer, "IEC958 input: Optical\n");
3580                         break;
3581                 case HDSP_SPDIFIN_COAXIAL:
3582                         snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3583                         break;
3584                 case HDSP_SPDIFIN_INTERNAL:
3585                         snd_iprintf(buffer, "IEC958 input: Internal\n");
3586                         break;
3587                 case HDSP_SPDIFIN_AES:
3588                         snd_iprintf(buffer, "IEC958 input: AES\n");
3589                         break;
3590                 default:
3591                         snd_iprintf(buffer, "IEC958 input: ???\n");
3592                         break;
3593                 }
3594         }
3595 
3596         if (RPM == hdsp->io_type) {
3597                 if (hdsp->control_register & HDSP_RPM_Bypass)
3598                         snd_iprintf(buffer, "RPM Bypass: disabled\n");
3599                 else
3600                         snd_iprintf(buffer, "RPM Bypass: enabled\n");
3601                 if (hdsp->control_register & HDSP_RPM_Disconnect)
3602                         snd_iprintf(buffer, "RPM disconnected\n");
3603                 else
3604                         snd_iprintf(buffer, "RPM connected\n");
3605 
3606                 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3607                 case HDSP_RPM_Inp12_Phon_6dB:
3608                         snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3609                         break;
3610                 case HDSP_RPM_Inp12_Phon_0dB:
3611                         snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3612                         break;
3613                 case HDSP_RPM_Inp12_Phon_n6dB:
3614                         snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3615                         break;
3616                 case HDSP_RPM_Inp12_Line_0dB:
3617                         snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3618                         break;
3619                 case HDSP_RPM_Inp12_Line_n6dB:
3620                         snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3621                         break;
3622                 default:
3623                         snd_iprintf(buffer, "Input 1/2: ???\n");
3624                 }
3625 
3626                 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3627                 case HDSP_RPM_Inp34_Phon_6dB:
3628                         snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3629                         break;
3630                 case HDSP_RPM_Inp34_Phon_0dB:
3631                         snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3632                         break;
3633                 case HDSP_RPM_Inp34_Phon_n6dB:
3634                         snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3635                         break;
3636                 case HDSP_RPM_Inp34_Line_0dB:
3637                         snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3638                         break;
3639                 case HDSP_RPM_Inp34_Line_n6dB:
3640                         snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3641                         break;
3642                 default:
3643                         snd_iprintf(buffer, "Input 3/4: ???\n");
3644                 }
3645 
3646         } else {
3647                 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3648                         snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3649                 else
3650                         snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3651 
3652                 if (hdsp->control_register & HDSP_SPDIFProfessional)
3653                         snd_iprintf(buffer, "IEC958 quality: Professional\n");
3654                 else
3655                         snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3656 
3657                 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3658                         snd_iprintf(buffer, "IEC958 emphasis: on\n");
3659                 else
3660                         snd_iprintf(buffer, "IEC958 emphasis: off\n");
3661 
3662                 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3663                         snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3664                 else
3665                         snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3666                 x = hdsp_spdif_sample_rate(hdsp);
3667                 if (x != 0)
3668                         snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3669                 else
3670                         snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3671         }
3672         snd_iprintf(buffer, "\n");
3673 
3674         /* Sync Check */
3675         x = status & HDSP_Sync0;
3676         if (status & HDSP_Lock0)
3677                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3678         else
3679                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3680 
3681         switch (hdsp->io_type) {
3682         case Digiface:
3683         case H9652:
3684                 x = status & HDSP_Sync1;
3685                 if (status & HDSP_Lock1)
3686                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3687                 else
3688                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3689                 x = status & HDSP_Sync2;
3690                 if (status & HDSP_Lock2)
3691                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3692                 else
3693                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3694                 break;
3695         default:
3696                 /* relax */
3697                 break;
3698         }
3699 
3700         x = status & HDSP_SPDIFSync;
3701         if (status & HDSP_SPDIFErrorFlag)
3702                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3703         else
3704                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3705 
3706         x = status2 & HDSP_wc_sync;
3707         if (status2 & HDSP_wc_lock)
3708                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3709         else
3710                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3711 
3712         x = status & HDSP_TimecodeSync;
3713         if (status & HDSP_TimecodeLock)
3714                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3715         else
3716                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3717 
3718         snd_iprintf(buffer, "\n");
3719 
3720         /* Informations about H9632 specific controls */
3721         if (hdsp->io_type == H9632) {
3722                 char *tmp;
3723 
3724                 switch (hdsp_ad_gain(hdsp)) {
3725                 case 0:
3726                         tmp = "-10 dBV";
3727                         break;
3728                 case 1:
3729                         tmp = "+4 dBu";
3730                         break;
3731                 default:
3732                         tmp = "Lo Gain";
3733                         break;
3734                 }
3735                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3736 
3737                 switch (hdsp_da_gain(hdsp)) {
3738                 case 0:
3739                         tmp = "Hi Gain";
3740                         break;
3741                 case 1:
3742                         tmp = "+4 dBu";
3743                         break;
3744                 default:
3745                         tmp = "-10 dBV";
3746                         break;
3747                 }
3748                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3749 
3750                 switch (hdsp_phone_gain(hdsp)) {
3751                 case 0:
3752                         tmp = "0 dB";
3753                         break;
3754                 case 1:
3755                         tmp = "-6 dB";
3756                         break;
3757                 default:
3758                         tmp = "-12 dB";
3759                         break;
3760                 }
3761                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3762 
3763                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3764                         hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3765                         "yes" : "no");
3766 
3767                 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3768                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3769                 else
3770                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3771                 snd_iprintf(buffer, "\n");
3772         }
3773 
3774 }
3775 
3776 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3777 {
3778         struct snd_info_entry *entry;
3779 
3780         if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3781                 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3782 }
3783 
3784 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3785 {
3786         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3787         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3788 }
3789 
3790 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3791 {
3792         unsigned long pb_bus, cb_bus;
3793 
3794         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3795             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3796                 if (hdsp->capture_dma_buf.area)
3797                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3798                 dev_err(hdsp->card->dev,
3799                         "%s: no buffers available\n", hdsp->card_name);
3800                 return -ENOMEM;
3801         }
3802 
3803         /* Align to bus-space 64K boundary */
3804 
3805         cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3806         pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3807 
3808         /* Tell the card where it is */
3809 
3810         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3811         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3812 
3813         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3814         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3815 
3816         return 0;
3817 }
3818 
3819 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3820 {
3821         unsigned int i;
3822 
3823         /* ASSUMPTION: hdsp->lock is either held, or
3824            there is no need to hold it (e.g. during module
3825            initialization).
3826          */
3827 
3828         /* set defaults:
3829 
3830            SPDIF Input via Coax
3831            Master clock mode
3832            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3833                             which implies 2 4096 sample, 32Kbyte periods).
3834            Enable line out.
3835          */
3836 
3837         hdsp->control_register = HDSP_ClockModeMaster |
3838                                  HDSP_SPDIFInputCoaxial |
3839                                  hdsp_encode_latency(7) |
3840                                  HDSP_LineOut;
3841 
3842 
3843         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3844 
3845 #ifdef SNDRV_BIG_ENDIAN
3846         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3847 #else
3848         hdsp->control2_register = 0;
3849 #endif
3850         if (hdsp->io_type == H9652)
3851                 snd_hdsp_9652_enable_mixer (hdsp);
3852         else
3853                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3854 
3855         hdsp_reset_hw_pointer(hdsp);
3856         hdsp_compute_period_size(hdsp);
3857 
3858         /* silence everything */
3859 
3860         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3861                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3862 
3863         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3864                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3865                         return -EIO;
3866         }
3867 
3868         /* H9632 specific defaults */
3869         if (hdsp->io_type == H9632) {
3870                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3871                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3872         }
3873 
3874         /* set a default rate so that the channel map is set up.
3875          */
3876 
3877         hdsp_set_rate(hdsp, 48000, 1);
3878 
3879         return 0;
3880 }
3881 
3882 static void hdsp_midi_tasklet(unsigned long arg)
3883 {
3884         struct hdsp *hdsp = (struct hdsp *)arg;
3885 
3886         if (hdsp->midi[0].pending)
3887                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3888         if (hdsp->midi[1].pending)
3889                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3890 }
3891 
3892 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3893 {
3894         struct hdsp *hdsp = (struct hdsp *) dev_id;
3895         unsigned int status;
3896         int audio;
3897         int midi0;
3898         int midi1;
3899         unsigned int midi0status;
3900         unsigned int midi1status;
3901         int schedule = 0;
3902 
3903         status = hdsp_read(hdsp, HDSP_statusRegister);
3904 
3905         audio = status & HDSP_audioIRQPending;
3906         midi0 = status & HDSP_midi0IRQPending;
3907         midi1 = status & HDSP_midi1IRQPending;
3908 
3909         if (!audio && !midi0 && !midi1)
3910                 return IRQ_NONE;
3911 
3912         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3913 
3914         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3915         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3916 
3917         if (!(hdsp->state & HDSP_InitializationComplete))
3918                 return IRQ_HANDLED;
3919 
3920         if (audio) {
3921                 if (hdsp->capture_substream)
3922                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3923 
3924                 if (hdsp->playback_substream)
3925                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3926         }
3927 
3928         if (midi0 && midi0status) {
3929                 if (hdsp->use_midi_tasklet) {
3930                         /* we disable interrupts for this input until processing is done */
3931                         hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3932                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3933                         hdsp->midi[0].pending = 1;
3934                         schedule = 1;
3935                 } else {
3936                         snd_hdsp_midi_input_read (&hdsp->midi[0]);
3937                 }
3938         }
3939         if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3940                 if (hdsp->use_midi_tasklet) {
3941                         /* we disable interrupts for this input until processing is done */
3942                         hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3943                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3944                         hdsp->midi[1].pending = 1;
3945                         schedule = 1;
3946                 } else {
3947                         snd_hdsp_midi_input_read (&hdsp->midi[1]);
3948                 }
3949         }
3950         if (hdsp->use_midi_tasklet && schedule)
3951                 tasklet_schedule(&hdsp->midi_tasklet);
3952         return IRQ_HANDLED;
3953 }
3954 
3955 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3956 {
3957         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3958         return hdsp_hw_pointer(hdsp);
3959 }
3960 
3961 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3962                                              int stream,
3963                                              int channel)
3964 
3965 {
3966         int mapped_channel;
3967 
3968         if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3969                 return NULL;
3970 
3971         if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3972                 return NULL;
3973 
3974         if (stream == SNDRV_PCM_STREAM_CAPTURE)
3975                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3976         else
3977                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3978 }
3979 
3980 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
3981                                   snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3982 {
3983         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3984         char *channel_buf;
3985 
3986         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3987                 return -EINVAL;
3988 
3989         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3990         if (snd_BUG_ON(!channel_buf))
3991                 return -EIO;
3992         if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3993                 return -EFAULT;
3994         return count;
3995 }
3996 
3997 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
3998                                  snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3999 {
4000         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4001         char *channel_buf;
4002 
4003         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
4004                 return -EINVAL;
4005 
4006         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4007         if (snd_BUG_ON(!channel_buf))
4008                 return -EIO;
4009         if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
4010                 return -EFAULT;
4011         return count;
4012 }
4013 
4014 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
4015                                   snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
4016 {
4017         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4018         char *channel_buf;
4019 
4020         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4021         if (snd_BUG_ON(!channel_buf))
4022                 return -EIO;
4023         memset(channel_buf + pos * 4, 0, count * 4);
4024         return count;
4025 }
4026 
4027 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
4028 {
4029         struct snd_pcm_runtime *runtime = substream->runtime;
4030         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4031         struct snd_pcm_substream *other;
4032         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4033                 other = hdsp->capture_substream;
4034         else
4035                 other = hdsp->playback_substream;
4036         if (hdsp->running)
4037                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
4038         else
4039                 runtime->status->hw_ptr = 0;
4040         if (other) {
4041                 struct snd_pcm_substream *s;
4042                 struct snd_pcm_runtime *oruntime = other->runtime;
4043                 snd_pcm_group_for_each_entry(s, substream) {
4044                         if (s == other) {
4045                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4046                                 break;
4047                         }
4048                 }
4049         }
4050         return 0;
4051 }
4052 
4053 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4054                                  struct snd_pcm_hw_params *params)
4055 {
4056         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4057         int err;
4058         pid_t this_pid;
4059         pid_t other_pid;
4060 
4061         if (hdsp_check_for_iobox (hdsp))
4062                 return -EIO;
4063 
4064         if (hdsp_check_for_firmware(hdsp, 1))
4065                 return -EIO;
4066 
4067         spin_lock_irq(&hdsp->lock);
4068 
4069         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4070                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4071                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4072                 this_pid = hdsp->playback_pid;
4073                 other_pid = hdsp->capture_pid;
4074         } else {
4075                 this_pid = hdsp->capture_pid;
4076                 other_pid = hdsp->playback_pid;
4077         }
4078 
4079         if ((other_pid > 0) && (this_pid != other_pid)) {
4080 
4081                 /* The other stream is open, and not by the same
4082                    task as this one. Make sure that the parameters
4083                    that matter are the same.
4084                  */
4085 
4086                 if (params_rate(params) != hdsp->system_sample_rate) {
4087                         spin_unlock_irq(&hdsp->lock);
4088                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4089                         return -EBUSY;
4090                 }
4091 
4092                 if (params_period_size(params) != hdsp->period_bytes / 4) {
4093                         spin_unlock_irq(&hdsp->lock);
4094                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4095                         return -EBUSY;
4096                 }
4097 
4098                 /* We're fine. */
4099 
4100                 spin_unlock_irq(&hdsp->lock);
4101                 return 0;
4102 
4103         } else {
4104                 spin_unlock_irq(&hdsp->lock);
4105         }
4106 
4107         /* how to make sure that the rate matches an externally-set one ?
4108          */
4109 
4110         spin_lock_irq(&hdsp->lock);
4111         if (! hdsp->clock_source_locked) {
4112                 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4113                         spin_unlock_irq(&hdsp->lock);
4114                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4115                         return err;
4116                 }
4117         }
4118         spin_unlock_irq(&hdsp->lock);
4119 
4120         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4121                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4122                 return err;
4123         }
4124 
4125         return 0;
4126 }
4127 
4128 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4129                                     struct snd_pcm_channel_info *info)
4130 {
4131         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4132         int mapped_channel;
4133 
4134         if (snd_BUG_ON(info->channel >= hdsp->max_channels))
4135                 return -EINVAL;
4136 
4137         if ((mapped_channel = hdsp->channel_map[info->channel]) < 0)
4138                 return -EINVAL;
4139 
4140         info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
4141         info->first = 0;
4142         info->step = 32;
4143         return 0;
4144 }
4145 
4146 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4147                              unsigned int cmd, void *arg)
4148 {
4149         switch (cmd) {
4150         case SNDRV_PCM_IOCTL1_RESET:
4151                 return snd_hdsp_reset(substream);
4152         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4153                 return snd_hdsp_channel_info(substream, arg);
4154         default:
4155                 break;
4156         }
4157 
4158         return snd_pcm_lib_ioctl(substream, cmd, arg);
4159 }
4160 
4161 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4162 {
4163         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4164         struct snd_pcm_substream *other;
4165         int running;
4166 
4167         if (hdsp_check_for_iobox (hdsp))
4168                 return -EIO;
4169 
4170         if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4171                 return -EIO;
4172 
4173         spin_lock(&hdsp->lock);
4174         running = hdsp->running;
4175         switch (cmd) {
4176         case SNDRV_PCM_TRIGGER_START:
4177                 running |= 1 << substream->stream;
4178                 break;
4179         case SNDRV_PCM_TRIGGER_STOP:
4180                 running &= ~(1 << substream->stream);
4181                 break;
4182         default:
4183                 snd_BUG();
4184                 spin_unlock(&hdsp->lock);
4185                 return -EINVAL;
4186         }
4187         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4188                 other = hdsp->capture_substream;
4189         else
4190                 other = hdsp->playback_substream;
4191 
4192         if (other) {
4193                 struct snd_pcm_substream *s;
4194                 snd_pcm_group_for_each_entry(s, substream) {
4195                         if (s == other) {
4196                                 snd_pcm_trigger_done(s, substream);
4197                                 if (cmd == SNDRV_PCM_TRIGGER_START)
4198                                         running |= 1 << s->stream;
4199                                 else
4200                                         running &= ~(1 << s->stream);
4201                                 goto _ok;
4202                         }
4203                 }
4204                 if (cmd == SNDRV_PCM_TRIGGER_START) {
4205                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4206                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4207                                 hdsp_silence_playback(hdsp);
4208                 } else {
4209                         if (running &&
4210                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4211                                 hdsp_silence_playback(hdsp);
4212                 }
4213         } else {
4214                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4215                                 hdsp_silence_playback(hdsp);
4216         }
4217  _ok:
4218         snd_pcm_trigger_done(substream, substream);
4219         if (!hdsp->running && running)
4220                 hdsp_start_audio(hdsp);
4221         else if (hdsp->running && !running)
4222                 hdsp_stop_audio(hdsp);
4223         hdsp->running = running;
4224         spin_unlock(&hdsp->lock);
4225 
4226         return 0;
4227 }
4228 
4229 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4230 {
4231         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4232         int result = 0;
4233 
4234         if (hdsp_check_for_iobox (hdsp))
4235                 return -EIO;
4236 
4237         if (hdsp_check_for_firmware(hdsp, 1))
4238                 return -EIO;
4239 
4240         spin_lock_irq(&hdsp->lock);
4241         if (!hdsp->running)
4242                 hdsp_reset_hw_pointer(hdsp);
4243         spin_unlock_irq(&hdsp->lock);
4244         return result;
4245 }
4246 
4247 static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4248 {
4249         .info =                 (SNDRV_PCM_INFO_MMAP |
4250                                  SNDRV_PCM_INFO_MMAP_VALID |
4251                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4252                                  SNDRV_PCM_INFO_SYNC_START |
4253                                  SNDRV_PCM_INFO_DOUBLE),
4254 #ifdef SNDRV_BIG_ENDIAN
4255         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4256 #else
4257         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4258 #endif
4259         .rates =                (SNDRV_PCM_RATE_32000 |
4260                                  SNDRV_PCM_RATE_44100 |
4261                                  SNDRV_PCM_RATE_48000 |
4262                                  SNDRV_PCM_RATE_64000 |
4263                                  SNDRV_PCM_RATE_88200 |
4264                                  SNDRV_PCM_RATE_96000),
4265         .rate_min =             32000,
4266         .rate_max =             96000,
4267         .channels_min =         6,
4268         .channels_max =         HDSP_MAX_CHANNELS,
4269         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4270         .period_bytes_min =     (64 * 4) * 10,
4271         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4272         .periods_min =          2,
4273         .periods_max =          2,
4274         .fifo_size =            0
4275 };
4276 
4277 static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4278 {
4279         .info =                 (SNDRV_PCM_INFO_MMAP |
4280                                  SNDRV_PCM_INFO_MMAP_VALID |
4281                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4282                                  SNDRV_PCM_INFO_SYNC_START),
4283 #ifdef SNDRV_BIG_ENDIAN
4284         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4285 #else
4286         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4287 #endif
4288         .rates =                (SNDRV_PCM_RATE_32000 |
4289                                  SNDRV_PCM_RATE_44100 |
4290                                  SNDRV_PCM_RATE_48000 |
4291                                  SNDRV_PCM_RATE_64000 |
4292                                  SNDRV_PCM_RATE_88200 |
4293                                  SNDRV_PCM_RATE_96000),
4294         .rate_min =             32000,
4295         .rate_max =             96000,
4296         .channels_min =         5,
4297         .channels_max =         HDSP_MAX_CHANNELS,
4298         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4299         .period_bytes_min =     (64 * 4) * 10,
4300         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4301         .periods_min =          2,
4302         .periods_max =          2,
4303         .fifo_size =            0
4304 };
4305 
4306 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4307 
4308 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4309         .count = ARRAY_SIZE(hdsp_period_sizes),
4310         .list = hdsp_period_sizes,
4311         .mask = 0
4312 };
4313 
4314 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4315 
4316 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4317         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4318         .list = hdsp_9632_sample_rates,
4319         .mask = 0
4320 };
4321 
4322 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4323                                         struct snd_pcm_hw_rule *rule)
4324 {
4325         struct hdsp *hdsp = rule->private;
4326         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4327         if (hdsp->io_type == H9632) {
4328                 unsigned int list[3];
4329                 list[0] = hdsp->qs_in_channels;
4330                 list[1] = hdsp->ds_in_channels;
4331                 list[2] = hdsp->ss_in_channels;
4332                 return snd_interval_list(c, 3, list, 0);
4333         } else {
4334                 unsigned int list[2];
4335                 list[0] = hdsp->ds_in_channels;
4336                 list[1] = hdsp->ss_in_channels;
4337                 return snd_interval_list(c, 2, list, 0);
4338         }
4339 }
4340 
4341 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4342                                         struct snd_pcm_hw_rule *rule)
4343 {
4344         unsigned int list[3];
4345         struct hdsp *hdsp = rule->private;
4346         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4347         if (hdsp->io_type == H9632) {
4348                 list[0] = hdsp->qs_out_channels;
4349                 list[1] = hdsp->ds_out_channels;
4350                 list[2] = hdsp->ss_out_channels;
4351                 return snd_interval_list(c, 3, list, 0);
4352         } else {
4353                 list[0] = hdsp->ds_out_channels;
4354                 list[1] = hdsp->ss_out_channels;
4355         }
4356         return snd_interval_list(c, 2, list, 0);
4357 }
4358 
4359 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4360                                              struct snd_pcm_hw_rule *rule)
4361 {
4362         struct hdsp *hdsp = rule->private;
4363         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4364         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4365         if (r->min > 96000 && hdsp->io_type == H9632) {
4366                 struct snd_interval t = {
4367                         .min = hdsp->qs_in_channels,
4368                         .max = hdsp->qs_in_channels,
4369                         .integer = 1,
4370                 };
4371                 return snd_interval_refine(c, &t);
4372         } else if (r->min > 48000 && r->max <= 96000) {
4373                 struct snd_interval t = {
4374                         .min = hdsp->ds_in_channels,
4375                         .max = hdsp->ds_in_channels,
4376                         .integer = 1,
4377                 };
4378                 return snd_interval_refine(c, &t);
4379         } else if (r->max < 64000) {
4380                 struct snd_interval t = {
4381                         .min = hdsp->ss_in_channels,
4382                         .max = hdsp->ss_in_channels,
4383                         .integer = 1,
4384                 };
4385                 return snd_interval_refine(c, &t);
4386         }
4387         return 0;
4388 }
4389 
4390 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4391                                              struct snd_pcm_hw_rule *rule)
4392 {
4393         struct hdsp *hdsp = rule->private;
4394         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4395         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4396         if (r->min > 96000 && hdsp->io_type == H9632) {
4397                 struct snd_interval t = {
4398                         .min = hdsp->qs_out_channels,
4399                         .max = hdsp->qs_out_channels,
4400                         .integer = 1,
4401                 };
4402                 return snd_interval_refine(c, &t);
4403         } else if (r->min > 48000 && r->max <= 96000) {
4404                 struct snd_interval t = {
4405                         .min = hdsp->ds_out_channels,
4406                         .max = hdsp->ds_out_channels,
4407                         .integer = 1,
4408                 };
4409                 return snd_interval_refine(c, &t);
4410         } else if (r->max < 64000) {
4411                 struct snd_interval t = {
4412                         .min = hdsp->ss_out_channels,
4413                         .max = hdsp->ss_out_channels,
4414                         .integer = 1,
4415                 };
4416                 return snd_interval_refine(c, &t);
4417         }
4418         return 0;
4419 }
4420 
4421 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4422                                              struct snd_pcm_hw_rule *rule)
4423 {
4424         struct hdsp *hdsp = rule->private;
4425         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4426         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4427         if (c->min >= hdsp->ss_out_channels) {
4428                 struct snd_interval t = {
4429                         .min = 32000,
4430                         .max = 48000,
4431                         .integer = 1,
4432                 };
4433                 return snd_interval_refine(r, &t);
4434         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4435                 struct snd_interval t = {
4436                         .min = 128000,
4437                         .max = 192000,
4438                         .integer = 1,
4439                 };
4440                 return snd_interval_refine(r, &t);
4441         } else if (c->max <= hdsp->ds_out_channels) {
4442                 struct snd_interval t = {
4443                         .min = 64000,
4444                         .max = 96000,
4445                         .integer = 1,
4446                 };
4447                 return snd_interval_refine(r, &t);
4448         }
4449         return 0;
4450 }
4451 
4452 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4453                                              struct snd_pcm_hw_rule *rule)
4454 {
4455         struct hdsp *hdsp = rule->private;
4456         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4457         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4458         if (c->min >= hdsp->ss_in_channels) {
4459                 struct snd_interval t = {
4460                         .min = 32000,
4461                         .max = 48000,
4462                         .integer = 1,
4463                 };
4464                 return snd_interval_refine(r, &t);
4465         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4466                 struct snd_interval t = {
4467                         .min = 128000,
4468                         .max = 192000,
4469                         .integer = 1,
4470                 };
4471                 return snd_interval_refine(r, &t);
4472         } else if (c->max <= hdsp->ds_in_channels) {
4473                 struct snd_interval t = {
4474                         .min = 64000,
4475                         .max = 96000,
4476                         .integer = 1,
4477                 };
4478                 return snd_interval_refine(r, &t);
4479         }
4480         return 0;
4481 }
4482 
4483 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4484 {
4485         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4486         struct snd_pcm_runtime *runtime = substream->runtime;
4487 
4488         if (hdsp_check_for_iobox (hdsp))
4489                 return -EIO;
4490 
4491         if (hdsp_check_for_firmware(hdsp, 1))
4492                 return -EIO;
4493 
4494         spin_lock_irq(&hdsp->lock);
4495 
4496         snd_pcm_set_sync(substream);
4497 
4498         runtime->hw = snd_hdsp_playback_subinfo;
4499         runtime->dma_area = hdsp->playback_buffer;
4500         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4501 
4502         hdsp->playback_pid = current->pid;
4503         hdsp->playback_substream = substream;
4504 
4505         spin_unlock_irq(&hdsp->lock);
4506 
4507         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4508         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4509         if (hdsp->clock_source_locked) {
4510                 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4511         } else if (hdsp->io_type == H9632) {
4512                 runtime->hw.rate_max = 192000;
4513                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4514                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4515         }
4516         if (hdsp->io_type == H9632) {
4517                 runtime->hw.channels_min = hdsp->qs_out_channels;
4518                 runtime->hw.channels_max = hdsp->ss_out_channels;
4519         }
4520 
4521         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4522                              snd_hdsp_hw_rule_out_channels, hdsp,
4523                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4524         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4525                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4526                              SNDRV_PCM_HW_PARAM_RATE, -1);
4527         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4528                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4529                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4530 
4531         if (RPM != hdsp->io_type) {
4532                 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4533                 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4534                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4535                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4536         }
4537         return 0;
4538 }
4539 
4540 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4541 {
4542         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4543 
4544         spin_lock_irq(&hdsp->lock);
4545 
4546         hdsp->playback_pid = -1;
4547         hdsp->playback_substream = NULL;
4548 
4549         spin_unlock_irq(&hdsp->lock);
4550 
4551         if (RPM != hdsp->io_type) {
4552                 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4553                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4554                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4555         }
4556         return 0;
4557 }
4558 
4559 
4560 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4561 {
4562         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4563         struct snd_pcm_runtime *runtime = substream->runtime;
4564 
4565         if (hdsp_check_for_iobox (hdsp))
4566                 return -EIO;
4567 
4568         if (hdsp_check_for_firmware(hdsp, 1))
4569                 return -EIO;
4570 
4571         spin_lock_irq(&hdsp->lock);
4572 
4573         snd_pcm_set_sync(substream);
4574 
4575         runtime->hw = snd_hdsp_capture_subinfo;
4576         runtime->dma_area = hdsp->capture_buffer;
4577         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4578 
4579         hdsp->capture_pid = current->pid;
4580         hdsp->capture_substream = substream;
4581 
4582         spin_unlock_irq(&hdsp->lock);
4583 
4584         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4585         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4586         if (hdsp->io_type == H9632) {
4587                 runtime->hw.channels_min = hdsp->qs_in_channels;
4588                 runtime->hw.channels_max = hdsp->ss_in_channels;
4589                 runtime->hw.rate_max = 192000;
4590                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4591                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4592         }
4593         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4594                              snd_hdsp_hw_rule_in_channels, hdsp,
4595                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4596         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4597                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4598                              SNDRV_PCM_HW_PARAM_RATE, -1);
4599         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4600                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4601                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4602         return 0;
4603 }
4604 
4605 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4606 {
4607         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4608 
4609         spin_lock_irq(&hdsp->lock);
4610 
4611         hdsp->capture_pid = -1;
4612         hdsp->capture_substream = NULL;
4613 
4614         spin_unlock_irq(&hdsp->lock);
4615         return 0;
4616 }
4617 
4618 /* helper functions for copying meter values */
4619 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4620 {
4621         u32 val = readl(src);
4622         return copy_to_user(dest, &val, 4);
4623 }
4624 
4625 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4626 {
4627         u32 rms_low, rms_high;
4628         u64 rms;
4629         rms_low = readl(src_low);
4630         rms_high = readl(src_high);
4631         rms = ((u64)rms_high << 32) | rms_low;
4632         return copy_to_user(dest, &rms, 8);
4633 }
4634 
4635 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4636 {
4637         u32 rms_low, rms_high;
4638         u64 rms;
4639         rms_low = readl(src_low) & 0xffffff00;
4640         rms_high = readl(src_high) & 0xffffff00;
4641         rms = ((u64)rms_high << 32) | rms_low;
4642         return copy_to_user(dest, &rms, 8);
4643 }
4644 
4645 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4646 {
4647         int doublespeed = 0;
4648         int i, j, channels, ofs;
4649 
4650         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4651                 doublespeed = 1;
4652         channels = doublespeed ? 14 : 26;
4653         for (i = 0, j = 0; i < 26; ++i) {
4654                 if (doublespeed && (i & 4))
4655                         continue;
4656                 ofs = HDSP_9652_peakBase - j * 4;
4657                 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4658                         return -EFAULT;
4659                 ofs -= channels * 4;
4660                 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4661                         return -EFAULT;
4662                 ofs -= channels * 4;
4663                 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4664                         return -EFAULT;
4665                 ofs = HDSP_9652_rmsBase + j * 8;
4666                 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4667                                 hdsp->iobase + ofs + 4))
4668                         return -EFAULT;
4669                 ofs += channels * 8;
4670                 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4671                                 hdsp->iobase + ofs + 4))
4672                         return -EFAULT;
4673                 ofs += channels * 8;
4674                 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4675                                 hdsp->iobase + ofs + 4))
4676                         return -EFAULT;
4677                 j++;
4678         }
4679         return 0;
4680 }
4681 
4682 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4683 {
4684         int i, j;
4685         struct hdsp_9632_meters __iomem *m;
4686         int doublespeed = 0;
4687 
4688         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4689                 doublespeed = 1;
4690         m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4691         for (i = 0, j = 0; i < 16; ++i, ++j) {
4692                 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4693                         return -EFAULT;
4694                 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4695                         return -EFAULT;
4696                 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4697                         return -EFAULT;
4698                 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4699                                 &m->input_rms_high[j]))
4700                         return -EFAULT;
4701                 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4702                                 &m->playback_rms_high[j]))
4703                         return -EFAULT;
4704                 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4705                                 &m->output_rms_high[j]))
4706                         return -EFAULT;
4707                 if (doublespeed && i == 3) i += 4;
4708         }
4709         return 0;
4710 }
4711 
4712 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4713 {
4714         int i;
4715 
4716         for (i = 0; i < 26; i++) {
4717                 if (copy_u32_le(&peak_rms->playback_peaks[i],
4718                                 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4719                         return -EFAULT;
4720                 if (copy_u32_le(&peak_rms->input_peaks[i],
4721                                 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4722                         return -EFAULT;
4723         }
4724         for (i = 0; i < 28; i++) {
4725                 if (copy_u32_le(&peak_rms->output_peaks[i],
4726                                 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4727                         return -EFAULT;
4728         }
4729         for (i = 0; i < 26; ++i) {
4730                 if (copy_u64_le(&peak_rms->playback_rms[i],
4731                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4732                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4733                         return -EFAULT;
4734                 if (copy_u64_le(&peak_rms->input_rms[i],
4735                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4736                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4737                         return -EFAULT;
4738         }
4739         return 0;
4740 }
4741 
4742 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4743 {
4744         struct hdsp *hdsp = hw->private_data;
4745         void __user *argp = (void __user *)arg;
4746         int err;
4747 
4748         switch (cmd) {
4749         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4750                 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4751 
4752                 err = hdsp_check_for_iobox(hdsp);
4753                 if (err < 0)
4754                         return err;
4755 
4756                 err = hdsp_check_for_firmware(hdsp, 1);
4757                 if (err < 0)
4758                         return err;
4759 
4760                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4761                         dev_err(hdsp->card->dev,
4762                                 "firmware needs to be uploaded to the card.\n");
4763                         return -EINVAL;
4764                 }
4765 
4766                 switch (hdsp->io_type) {
4767                 case H9652:
4768                         return hdsp_9652_get_peak(hdsp, peak_rms);
4769                 case H9632:
4770                         return hdsp_9632_get_peak(hdsp, peak_rms);
4771                 default:
4772                         return hdsp_get_peak(hdsp, peak_rms);
4773                 }
4774         }
4775         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4776                 struct hdsp_config_info info;
4777                 unsigned long flags;
4778                 int i;
4779 
4780                 err = hdsp_check_for_iobox(hdsp);
4781                 if (err < 0)
4782                         return err;
4783 
4784                 err = hdsp_check_for_firmware(hdsp, 1);
4785                 if (err < 0)
4786                         return err;
4787 
4788                 memset(&info, 0, sizeof(info));
4789                 spin_lock_irqsave(&hdsp->lock, flags);
4790                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4791                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4792                 if (hdsp->io_type != H9632)
4793                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4794                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4795                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4796                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4797                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4798                 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4799                                 HDSP_SPDIFOpticalOut);
4800                 info.spdif_professional = (unsigned char)
4801                         hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4802                 info.spdif_emphasis = (unsigned char)
4803                         hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4804                 info.spdif_nonaudio = (unsigned char)
4805                         hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4806                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4807                 info.system_sample_rate = hdsp->system_sample_rate;
4808                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4809                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4810                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4811                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4812                 info.line_out = (unsigned char)
4813                         hdsp_toggle_setting(hdsp, HDSP_LineOut);
4814                 if (hdsp->io_type == H9632) {
4815                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4816                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4817                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4818                         info.xlr_breakout_cable =
4819                                 (unsigned char)hdsp_toggle_setting(hdsp,
4820                                         HDSP_XLRBreakoutCable);
4821 
4822                 } else if (hdsp->io_type == RPM) {
4823                         info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4824                         info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4825                 }
4826                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4827                         info.analog_extension_board =
4828                                 (unsigned char)hdsp_toggle_setting(hdsp,
4829                                             HDSP_AnalogExtensionBoard);
4830                 spin_unlock_irqrestore(&hdsp->lock, flags);
4831                 if (copy_to_user(argp, &info, sizeof(info)))
4832                         return -EFAULT;
4833                 break;
4834         }
4835         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4836                 struct hdsp_9632_aeb h9632_aeb;
4837 
4838                 if (hdsp->io_type != H9632) return -EINVAL;
4839                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4840                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4841                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4842                         return -EFAULT;
4843                 break;
4844         }
4845         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4846                 struct hdsp_version hdsp_version;
4847                 int err;
4848 
4849                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4850                 if (hdsp->io_type == Undefined) {
4851                         if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4852                                 return err;
4853                 }
4854                 memset(&hdsp_version, 0, sizeof(hdsp_version));
4855                 hdsp_version.io_type = hdsp->io_type;
4856                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4857                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4858                         return -EFAULT;
4859                 break;
4860         }
4861         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4862                 struct hdsp_firmware __user *firmware;
4863                 u32 __user *firmware_data;
4864                 int err;
4865 
4866                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4867                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4868                 if (hdsp->io_type == Undefined) return -EINVAL;
4869 
4870                 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4871                         return -EBUSY;
4872 
4873                 dev_info(hdsp->card->dev,
4874                          "initializing firmware upload\n");
4875                 firmware = (struct hdsp_firmware __user *)argp;
4876 
4877                 if (get_user(firmware_data, &firmware->firmware_data))
4878                         return -EFAULT;
4879 
4880                 if (hdsp_check_for_iobox (hdsp))
4881                         return -EIO;
4882 
4883                 if (!hdsp->fw_uploaded) {
4884                         hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4885                         if (!hdsp->fw_uploaded)
4886                                 return -ENOMEM;
4887                 }
4888 
4889                 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4890                                    HDSP_FIRMWARE_SIZE)) {
4891                         vfree(hdsp->fw_uploaded);
4892                         hdsp->fw_uploaded = NULL;
4893                         return -EFAULT;
4894                 }
4895 
4896                 hdsp->state |= HDSP_FirmwareCached;
4897 
4898                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4899                         return err;
4900 
4901                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4902                         if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4903                                 return err;
4904 
4905                         snd_hdsp_initialize_channels(hdsp);
4906                         snd_hdsp_initialize_midi_flush(hdsp);
4907 
4908                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4909                                 dev_err(hdsp->card->dev,
4910                                         "error creating alsa devices\n");
4911                                 return err;
4912                         }
4913                 }
4914                 break;
4915         }
4916         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4917                 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4918                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4919                         return -EFAULT;
4920                 break;
4921         }
4922         default:
4923                 return -EINVAL;
4924         }
4925         return 0;
4926 }
4927 
4928 static struct snd_pcm_ops snd_hdsp_playback_ops = {
4929         .open =         snd_hdsp_playback_open,
4930         .close =        snd_hdsp_playback_release,
4931         .ioctl =        snd_hdsp_ioctl,
4932         .hw_params =    snd_hdsp_hw_params,
4933         .prepare =      snd_hdsp_prepare,
4934         .trigger =      snd_hdsp_trigger,
4935         .pointer =      snd_hdsp_hw_pointer,
4936         .copy =         snd_hdsp_playback_copy,
4937         .silence =      snd_hdsp_hw_silence,
4938 };
4939 
4940 static struct snd_pcm_ops snd_hdsp_capture_ops = {
4941         .open =         snd_hdsp_capture_open,
4942         .close =        snd_hdsp_capture_release,
4943         .ioctl =        snd_hdsp_ioctl,
4944         .hw_params =    snd_hdsp_hw_params,
4945         .prepare =      snd_hdsp_prepare,
4946         .trigger =      snd_hdsp_trigger,
4947         .pointer =      snd_hdsp_hw_pointer,
4948         .copy =         snd_hdsp_capture_copy,
4949 };
4950 
4951 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4952 {
4953         struct snd_hwdep *hw;
4954         int err;
4955 
4956         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4957                 return err;
4958 
4959         hdsp->hwdep = hw;
4960         hw->private_data = hdsp;
4961         strcpy(hw->name, "HDSP hwdep interface");
4962 
4963         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4964         hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4965 
4966         return 0;
4967 }
4968 
4969 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4970 {
4971         struct snd_pcm *pcm;
4972         int err;
4973 
4974         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4975                 return err;
4976 
4977         hdsp->pcm = pcm;
4978         pcm->private_data = hdsp;
4979         strcpy(pcm->name, hdsp->card_name);
4980 
4981         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4982         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4983 
4984         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4985 
4986         return 0;
4987 }
4988 
4989 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4990 {
4991         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4992         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4993 }
4994 
4995 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4996 {
4997         int i;
4998 
4999         if (hdsp_fifo_wait (hdsp, 0, 100)) {
5000                 dev_err(hdsp->card->dev,
5001                         "enable_io fifo_wait failed\n");
5002                 return -EIO;
5003         }
5004 
5005         for (i = 0; i < hdsp->max_channels; ++i) {
5006                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
5007                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
5008         }
5009 
5010         return 0;
5011 }
5012 
5013 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
5014 {
5015         int status, aebi_channels, aebo_channels;
5016 
5017         switch (hdsp->io_type) {
5018         case Digiface:
5019                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
5020                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
5021                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
5022                 break;
5023 
5024         case H9652:
5025                 hdsp->card_name = "RME Hammerfall HDSP 9652";
5026                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
5027                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
5028                 break;
5029 
5030         case H9632:
5031                 status = hdsp_read(hdsp, HDSP_statusRegister);
5032                 /* HDSP_AEBx bits are low when AEB are connected */
5033                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
5034                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
5035                 hdsp->card_name = "RME Hammerfall HDSP 9632";
5036                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5037                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5038                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5039                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5040                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5041                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5042                 break;
5043 
5044         case Multiface:
5045                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
5046                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5047                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5048                 break;
5049 
5050         case RPM:
5051                 hdsp->card_name = "RME Hammerfall DSP + RPM";
5052                 hdsp->ss_in_channels = RPM_CHANNELS-1;
5053                 hdsp->ss_out_channels = RPM_CHANNELS;
5054                 hdsp->ds_in_channels = RPM_CHANNELS-1;
5055                 hdsp->ds_out_channels = RPM_CHANNELS;
5056                 break;
5057 
5058         default:
5059                 /* should never get here */
5060                 break;
5061         }
5062 }
5063 
5064 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5065 {
5066         snd_hdsp_flush_midi_input (hdsp, 0);
5067         snd_hdsp_flush_midi_input (hdsp, 1);
5068 }
5069 
5070 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5071 {
5072         int err;
5073 
5074         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5075                 dev_err(card->dev,
5076                         "Error creating pcm interface\n");
5077                 return err;
5078         }
5079 
5080 
5081         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5082                 dev_err(card->dev,
5083                         "Error creating first midi interface\n");
5084                 return err;
5085         }
5086 
5087         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5088                 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5089                         dev_err(card->dev,
5090                                 "Error creating second midi interface\n");
5091                         return err;
5092                 }
5093         }
5094 
5095         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5096                 dev_err(card->dev,
5097                         "Error creating ctl interface\n");
5098                 return err;
5099         }
5100 
5101         snd_hdsp_proc_init(hdsp);
5102 
5103         hdsp->system_sample_rate = -1;
5104         hdsp->playback_pid = -1;
5105         hdsp->capture_pid = -1;
5106         hdsp->capture_substream = NULL;
5107         hdsp->playback_substream = NULL;
5108 
5109         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5110                 dev_err(card->dev,
5111                         "Error setting default values\n");
5112                 return err;
5113         }
5114 
5115         if (!(hdsp->state & HDSP_InitializationComplete)) {
5116                 strcpy(card->shortname, "Hammerfall DSP");
5117                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5118                         hdsp->port, hdsp->irq);
5119 
5120                 if ((err = snd_card_register(card)) < 0) {
5121                         dev_err(card->dev,
5122                                 "error registering card\n");
5123                         return err;
5124                 }
5125                 hdsp->state |= HDSP_InitializationComplete;
5126         }
5127 
5128         return 0;
5129 }
5130 
5131 /* load firmware via hotplug fw loader */
5132 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5133 {
5134         const char *fwfile;
5135         const struct firmware *fw;
5136         int err;
5137 
5138         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5139                 return 0;
5140         if (hdsp->io_type == Undefined) {
5141                 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5142                         return err;
5143                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5144                         return 0;
5145         }
5146 
5147         /* caution: max length of firmware filename is 30! */
5148         switch (hdsp->io_type) {
5149         case RPM:
5150                 fwfile = "rpm_firmware.bin";
5151                 break;
5152         case Multiface:
5153                 if (hdsp->firmware_rev == 0xa)
5154                         fwfile = "multiface_firmware.bin";
5155                 else
5156                         fwfile = "multiface_firmware_rev11.bin";
5157                 break;
5158         case Digiface:
5159                 if (hdsp->firmware_rev == 0xa)
5160                         fwfile = "digiface_firmware.bin";
5161                 else
5162                         fwfile = "digiface_firmware_rev11.bin";
5163                 break;
5164         default:
5165                 dev_err(hdsp->card->dev,
5166                         "invalid io_type %d\n", hdsp->io_type);
5167                 return -EINVAL;
5168         }
5169 
5170         if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5171                 dev_err(hdsp->card->dev,
5172                         "cannot load firmware %s\n", fwfile);
5173                 return -ENOENT;
5174         }
5175         if (fw->size < HDSP_FIRMWARE_SIZE) {
5176                 dev_err(hdsp->card->dev,
5177                         "too short firmware size %d (expected %d)\n",
5178                            (int)fw->size, HDSP_FIRMWARE_SIZE);
5179                 return -EINVAL;
5180         }
5181 
5182         hdsp->firmware = fw;
5183 
5184         hdsp->state |= HDSP_FirmwareCached;
5185 
5186         if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5187                 return err;
5188 
5189         if (!(hdsp->state & HDSP_InitializationComplete)) {
5190                 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5191                         return err;
5192 
5193                 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5194                         dev_err(hdsp->card->dev,
5195                                 "error creating hwdep device\n");
5196                         return err;
5197                 }
5198                 snd_hdsp_initialize_channels(hdsp);
5199                 snd_hdsp_initialize_midi_flush(hdsp);
5200                 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5201                         dev_err(hdsp->card->dev,
5202                                 "error creating alsa devices\n");
5203                         return err;
5204                 }
5205         }
5206         return 0;
5207 }
5208 
5209 static int snd_hdsp_create(struct snd_card *card,
5210                            struct hdsp *hdsp)
5211 {
5212         struct pci_dev *pci = hdsp->pci;
5213         int err;
5214         int is_9652 = 0;
5215         int is_9632 = 0;
5216 
5217         hdsp->irq = -1;
5218         hdsp->state = 0;
5219         hdsp->midi[0].rmidi = NULL;
5220         hdsp->midi[1].rmidi = NULL;
5221         hdsp->midi[0].input = NULL;
5222         hdsp->midi[1].input = NULL;
5223         hdsp->midi[0].output = NULL;
5224         hdsp->midi[1].output = NULL;
5225         hdsp->midi[0].pending = 0;
5226         hdsp->midi[1].pending = 0;
5227         spin_lock_init(&hdsp->midi[0].lock);
5228         spin_lock_init(&hdsp->midi[1].lock);
5229         hdsp->iobase = NULL;
5230         hdsp->control_register = 0;
5231         hdsp->control2_register = 0;
5232         hdsp->io_type = Undefined;
5233         hdsp->max_channels = 26;
5234 
5235         hdsp->card = card;
5236 
5237         spin_lock_init(&hdsp->lock);
5238 
5239         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5240 
5241         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5242         hdsp->firmware_rev &= 0xff;
5243 
5244         /* From Martin Bjoernsen :
5245             "It is important that the card's latency timer register in
5246             the PCI configuration space is set to a value much larger
5247             than 0 by the computer's BIOS or the driver.
5248             The windows driver always sets this 8 bit register [...]
5249             to its maximum 255 to avoid problems with some computers."
5250         */
5251         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5252 
5253         strcpy(card->driver, "H-DSP");
5254         strcpy(card->mixername, "Xilinx FPGA");
5255 
5256         if (hdsp->firmware_rev < 0xa)
5257                 return -ENODEV;
5258         else if (hdsp->firmware_rev < 0x64)
5259                 hdsp->card_name = "RME Hammerfall DSP";
5260         else if (hdsp->firmware_rev < 0x96) {
5261                 hdsp->card_name = "RME HDSP 9652";
5262                 is_9652 = 1;
5263         } else {
5264                 hdsp->card_name = "RME HDSP 9632";
5265                 hdsp->max_channels = 16;
5266                 is_9632 = 1;
5267         }
5268 
5269         if ((err = pci_enable_device(pci)) < 0)
5270                 return err;
5271 
5272         pci_set_master(hdsp->pci);
5273 
5274         if ((err = pci_request_regions(pci, "hdsp")) < 0)
5275                 return err;
5276         hdsp->port = pci_resource_start(pci, 0);
5277         if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5278                 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5279                         hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5280                 return -EBUSY;
5281         }
5282 
5283         if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5284                         KBUILD_MODNAME, hdsp)) {
5285                 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5286                 return -EBUSY;
5287         }
5288 
5289         hdsp->irq = pci->irq;
5290         hdsp->precise_ptr = 0;
5291         hdsp->use_midi_tasklet = 1;
5292         hdsp->dds_value = 0;
5293 
5294         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5295                 return err;
5296 
5297         if (!is_9652 && !is_9632) {
5298                 /* we wait a maximum of 10 seconds to let freshly
5299                  * inserted cardbus cards do their hardware init */
5300                 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5301 
5302                 if (err < 0)
5303                         return err;
5304 
5305                 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5306                         if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5307                                 /* we don't fail as this can happen
5308                                    if userspace is not ready for
5309                                    firmware upload
5310                                 */
5311                                 dev_err(hdsp->card->dev,
5312                                         "couldn't get firmware from userspace. try using hdsploader\n");
5313                         else
5314                                 /* init is complete, we return */
5315                                 return 0;
5316                         /* we defer initialization */
5317                         dev_info(hdsp->card->dev,
5318                                  "card initialization pending : waiting for firmware\n");
5319                         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5320                                 return err;
5321                         return 0;
5322                 } else {
5323                         dev_info(hdsp->card->dev,
5324                                  "Firmware already present, initializing card.\n");
5325                         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5326                                 hdsp->io_type = RPM;
5327                         else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5328                                 hdsp->io_type = Multiface;
5329                         else
5330                                 hdsp->io_type = Digiface;
5331                 }
5332         }
5333 
5334         if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5335                 return err;
5336 
5337         if (is_9652)
5338                 hdsp->io_type = H9652;
5339 
5340         if (is_9632)
5341                 hdsp->io_type = H9632;
5342 
5343         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5344                 return err;
5345 
5346         snd_hdsp_initialize_channels(hdsp);
5347         snd_hdsp_initialize_midi_flush(hdsp);
5348 
5349         hdsp->state |= HDSP_FirmwareLoaded;
5350 
5351         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5352                 return err;
5353 
5354         return 0;
5355 }
5356 
5357 static int snd_hdsp_free(struct hdsp *hdsp)
5358 {
5359         if (hdsp->port) {
5360                 /* stop the audio, and cancel all interrupts */
5361                 tasklet_kill(&hdsp->midi_tasklet);
5362                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5363                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5364         }
5365 
5366         if (hdsp->irq >= 0)
5367                 free_irq(hdsp->irq, (void *)hdsp);
5368 
5369         snd_hdsp_free_buffers(hdsp);
5370 
5371         if (hdsp->firmware)
5372                 release_firmware(hdsp->firmware);
5373         vfree(hdsp->fw_uploaded);
5374 
5375         if (hdsp->iobase)
5376                 iounmap(hdsp->iobase);
5377 
5378         if (hdsp->port)
5379                 pci_release_regions(hdsp->pci);
5380 
5381         pci_disable_device(hdsp->pci);
5382         return 0;
5383 }
5384 
5385 static void snd_hdsp_card_free(struct snd_card *card)
5386 {
5387         struct hdsp *hdsp = card->private_data;
5388 
5389         if (hdsp)
5390                 snd_hdsp_free(hdsp);
5391 }
5392 
5393 static int snd_hdsp_probe(struct pci_dev *pci,
5394                           const struct pci_device_id *pci_id)
5395 {
5396         static int dev;
5397         struct hdsp *hdsp;
5398         struct snd_card *card;
5399         int err;
5400 
5401         if (dev >= SNDRV_CARDS)
5402                 return -ENODEV;
5403         if (!enable[dev]) {
5404                 dev++;
5405                 return -ENOENT;
5406         }
5407 
5408         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5409                            sizeof(struct hdsp), &card);
5410         if (err < 0)
5411                 return err;
5412 
5413         hdsp = card->private_data;
5414         card->private_free = snd_hdsp_card_free;
5415         hdsp->dev = dev;
5416         hdsp->pci = pci;
5417 
5418         if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5419                 snd_card_free(card);
5420                 return err;
5421         }
5422 
5423         strcpy(card->shortname, "Hammerfall DSP");
5424         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5425                 hdsp->port, hdsp->irq);
5426 
5427         if ((err = snd_card_register(card)) < 0) {
5428                 snd_card_free(card);
5429                 return err;
5430         }
5431         pci_set_drvdata(pci, card);
5432         dev++;
5433         return 0;
5434 }
5435 
5436 static void snd_hdsp_remove(struct pci_dev *pci)
5437 {
5438         snd_card_free(pci_get_drvdata(pci));
5439 }
5440 
5441 static struct pci_driver hdsp_driver = {
5442         .name =     KBUILD_MODNAME,
5443         .id_table = snd_hdsp_ids,
5444         .probe =    snd_hdsp_probe,
5445         .remove = snd_hdsp_remove,
5446 };
5447 
5448 module_pci_driver(hdsp_driver);
5449 

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