Version:  2.0.40 2.2.26 2.4.37 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Linux/sound/pci/rme9652/hdsp.c

  1 /*
  2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
  3  *
  4  *      Copyright (c) 2002  Paul Davis
  5  *                          Marcus Andersson
  6  *                          Thomas Charbonnel
  7  *
  8  *   This program is free software; you can redistribute it and/or modify
  9  *   it under the terms of the GNU General Public License as published by
 10  *   the Free Software Foundation; either version 2 of the License, or
 11  *   (at your option) any later version.
 12  *
 13  *   This program is distributed in the hope that it will be useful,
 14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  *   GNU General Public License for more details.
 17  *
 18  *   You should have received a copy of the GNU General Public License
 19  *   along with this program; if not, write to the Free Software
 20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 21  *
 22  */
 23 
 24 #include <linux/init.h>
 25 #include <linux/delay.h>
 26 #include <linux/interrupt.h>
 27 #include <linux/pci.h>
 28 #include <linux/firmware.h>
 29 #include <linux/module.h>
 30 #include <linux/math64.h>
 31 #include <linux/vmalloc.h>
 32 
 33 #include <sound/core.h>
 34 #include <sound/control.h>
 35 #include <sound/pcm.h>
 36 #include <sound/info.h>
 37 #include <sound/asoundef.h>
 38 #include <sound/rawmidi.h>
 39 #include <sound/hwdep.h>
 40 #include <sound/initval.h>
 41 #include <sound/hdsp.h>
 42 
 43 #include <asm/byteorder.h>
 44 #include <asm/current.h>
 45 #include <asm/io.h>
 46 
 47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 49 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
 50 
 51 module_param_array(index, int, NULL, 0444);
 52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
 53 module_param_array(id, charp, NULL, 0444);
 54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
 55 module_param_array(enable, bool, NULL, 0444);
 56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
 57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
 58 MODULE_DESCRIPTION("RME Hammerfall DSP");
 59 MODULE_LICENSE("GPL");
 60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
 61                 "{RME HDSP-9652},"
 62                 "{RME HDSP-9632}}");
 63 MODULE_FIRMWARE("rpm_firmware.bin");
 64 MODULE_FIRMWARE("multiface_firmware.bin");
 65 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
 66 MODULE_FIRMWARE("digiface_firmware.bin");
 67 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
 68 
 69 #define HDSP_MAX_CHANNELS        26
 70 #define HDSP_MAX_DS_CHANNELS     14
 71 #define HDSP_MAX_QS_CHANNELS     8
 72 #define DIGIFACE_SS_CHANNELS     26
 73 #define DIGIFACE_DS_CHANNELS     14
 74 #define MULTIFACE_SS_CHANNELS    18
 75 #define MULTIFACE_DS_CHANNELS    14
 76 #define H9652_SS_CHANNELS        26
 77 #define H9652_DS_CHANNELS        14
 78 /* This does not include possible Analog Extension Boards
 79    AEBs are detected at card initialization
 80 */
 81 #define H9632_SS_CHANNELS        12
 82 #define H9632_DS_CHANNELS        8
 83 #define H9632_QS_CHANNELS        4
 84 #define RPM_CHANNELS             6
 85 
 86 /* Write registers. These are defined as byte-offsets from the iobase value.
 87  */
 88 #define HDSP_resetPointer               0
 89 #define HDSP_freqReg                    0
 90 #define HDSP_outputBufferAddress        32
 91 #define HDSP_inputBufferAddress         36
 92 #define HDSP_controlRegister            64
 93 #define HDSP_interruptConfirmation      96
 94 #define HDSP_outputEnable               128
 95 #define HDSP_control2Reg                256
 96 #define HDSP_midiDataOut0               352
 97 #define HDSP_midiDataOut1               356
 98 #define HDSP_fifoData                   368
 99 #define HDSP_inputEnable                384
100 
101 /* Read registers. These are defined as byte-offsets from the iobase value
102  */
103 
104 #define HDSP_statusRegister    0
105 #define HDSP_timecode        128
106 #define HDSP_status2Register 192
107 #define HDSP_midiDataIn0     360
108 #define HDSP_midiDataIn1     364
109 #define HDSP_midiStatusOut0  384
110 #define HDSP_midiStatusOut1  388
111 #define HDSP_midiStatusIn0   392
112 #define HDSP_midiStatusIn1   396
113 #define HDSP_fifoStatus      400
114 
115 /* the meters are regular i/o-mapped registers, but offset
116    considerably from the rest. the peak registers are reset
117    when read; the least-significant 4 bits are full-scale counters;
118    the actual peak value is in the most-significant 24 bits.
119 */
120 
121 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
122 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
123 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
124 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
125 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
126 
127 
128 /* This is for H9652 cards
129    Peak values are read downward from the base
130    Rms values are read upward
131    There are rms values for the outputs too
132    26*3 values are read in ss mode
133    14*3 in ds mode, with no gap between values
134 */
135 #define HDSP_9652_peakBase      7164
136 #define HDSP_9652_rmsBase       4096
137 
138 /* c.f. the hdsp_9632_meters_t struct */
139 #define HDSP_9632_metersBase    4096
140 
141 #define HDSP_IO_EXTENT     7168
142 
143 /* control2 register bits */
144 
145 #define HDSP_TMS                0x01
146 #define HDSP_TCK                0x02
147 #define HDSP_TDI                0x04
148 #define HDSP_JTAG               0x08
149 #define HDSP_PWDN               0x10
150 #define HDSP_PROGRAM            0x020
151 #define HDSP_CONFIG_MODE_0      0x040
152 #define HDSP_CONFIG_MODE_1      0x080
153 #define HDSP_VERSION_BIT        (0x100 | HDSP_S_LOAD)
154 #define HDSP_BIGENDIAN_MODE     0x200
155 #define HDSP_RD_MULTIPLE        0x400
156 #define HDSP_9652_ENABLE_MIXER  0x800
157 #define HDSP_S200               0x800
158 #define HDSP_S300               (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
159 #define HDSP_CYCLIC_MODE        0x1000
160 #define HDSP_TDO                0x10000000
161 
162 #define HDSP_S_PROGRAM      (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
163 #define HDSP_S_LOAD         (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
164 
165 /* Control Register bits */
166 
167 #define HDSP_Start                (1<<0)  /* start engine */
168 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
169 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
170 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
171 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
172 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
173 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
174 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
175 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
176 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
177 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
178 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
179 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
180 #define HDSP_SyncRef2             (1<<13)
181 #define HDSP_SPDIFInputSelect0    (1<<14)
182 #define HDSP_SPDIFInputSelect1    (1<<15)
183 #define HDSP_SyncRef0             (1<<16)
184 #define HDSP_SyncRef1             (1<<17)
185 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
186 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
187 #define HDSP_Midi0InterruptEnable (1<<22)
188 #define HDSP_Midi1InterruptEnable (1<<23)
189 #define HDSP_LineOut              (1<<24)
190 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
191 #define HDSP_ADGain1              (1<<26)
192 #define HDSP_DAGain0              (1<<27)
193 #define HDSP_DAGain1              (1<<28)
194 #define HDSP_PhoneGain0           (1<<29)
195 #define HDSP_PhoneGain1           (1<<30)
196 #define HDSP_QuadSpeed            (1<<31)
197 
198 /* RPM uses some of the registers for special purposes */
199 #define HDSP_RPM_Inp12            0x04A00
200 #define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
201 #define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
202 #define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
203 #define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
204 #define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */
205 
206 #define HDSP_RPM_Inp34            0x32000
207 #define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
208 #define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
209 #define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
210 #define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
211 #define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */
212 
213 #define HDSP_RPM_Bypass           0x01000
214 
215 #define HDSP_RPM_Disconnect       0x00001
216 
217 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
218 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
219 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
220 #define HDSP_ADGainLowGain     0
221 
222 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
223 #define HDSP_DAGainHighGain      HDSP_DAGainMask
224 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
225 #define HDSP_DAGainMinus10dBV    0
226 
227 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
228 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
229 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
230 #define HDSP_PhoneGainMinus12dB  0
231 
232 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
233 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
234 
235 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
236 #define HDSP_SPDIFInputADAT1    0
237 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
238 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
239 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
240 
241 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
242 #define HDSP_SyncRef_ADAT1       0
243 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
244 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
245 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
246 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
247 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
248 
249 /* Sample Clock Sources */
250 
251 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
252 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
253 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
254 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
255 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
256 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
257 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
258 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
259 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
260 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
261 
262 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
263 
264 #define HDSP_SYNC_FROM_WORD      0
265 #define HDSP_SYNC_FROM_SPDIF     1
266 #define HDSP_SYNC_FROM_ADAT1     2
267 #define HDSP_SYNC_FROM_ADAT_SYNC 3
268 #define HDSP_SYNC_FROM_ADAT2     4
269 #define HDSP_SYNC_FROM_ADAT3     5
270 
271 /* SyncCheck status */
272 
273 #define HDSP_SYNC_CHECK_NO_LOCK 0
274 #define HDSP_SYNC_CHECK_LOCK    1
275 #define HDSP_SYNC_CHECK_SYNC    2
276 
277 /* AutoSync references - used by "autosync_ref" control switch */
278 
279 #define HDSP_AUTOSYNC_FROM_WORD      0
280 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
281 #define HDSP_AUTOSYNC_FROM_SPDIF     2
282 #define HDSP_AUTOSYNC_FROM_NONE      3
283 #define HDSP_AUTOSYNC_FROM_ADAT1     4
284 #define HDSP_AUTOSYNC_FROM_ADAT2     5
285 #define HDSP_AUTOSYNC_FROM_ADAT3     6
286 
287 /* Possible sources of S/PDIF input */
288 
289 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
290 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
291 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
292 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
293 
294 #define HDSP_Frequency32KHz    HDSP_Frequency0
295 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
296 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
297 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
298 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
299 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
300 /* For H9632 cards */
301 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
302 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
303 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
304 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
305         return 104857600000000 / rate; // 100 MHz
306         return 110100480000000 / rate; // 105 MHz
307 */
308 #define DDS_NUMERATOR 104857600000000ULL;  /*  =  2^20 * 10^8 */
309 
310 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
311 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
312 
313 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
314 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
315 
316 /* Status Register bits */
317 
318 #define HDSP_audioIRQPending    (1<<0)
319 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
320 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
321 #define HDSP_Lock1              (1<<2)
322 #define HDSP_Lock0              (1<<3)
323 #define HDSP_SPDIFSync          (1<<4)
324 #define HDSP_TimecodeLock       (1<<5)
325 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
326 #define HDSP_Sync2              (1<<16)
327 #define HDSP_Sync1              (1<<17)
328 #define HDSP_Sync0              (1<<18)
329 #define HDSP_DoubleSpeedStatus  (1<<19)
330 #define HDSP_ConfigError        (1<<20)
331 #define HDSP_DllError           (1<<21)
332 #define HDSP_spdifFrequency0    (1<<22)
333 #define HDSP_spdifFrequency1    (1<<23)
334 #define HDSP_spdifFrequency2    (1<<24)
335 #define HDSP_SPDIFErrorFlag     (1<<25)
336 #define HDSP_BufferID           (1<<26)
337 #define HDSP_TimecodeSync       (1<<27)
338 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
339 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
340 #define HDSP_midi0IRQPending    (1<<30)
341 #define HDSP_midi1IRQPending    (1<<31)
342 
343 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
344 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
345                                       HDSP_spdifFrequency1|\
346                                       HDSP_spdifFrequency2|\
347                                       HDSP_spdifFrequency3)
348 
349 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
350 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
351 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
352 
353 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
354 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
355 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
356 
357 /* This is for H9632 cards */
358 #define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
359                                      HDSP_spdifFrequency1|\
360                                      HDSP_spdifFrequency2)
361 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
362 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
363 
364 /* Status2 Register bits */
365 
366 #define HDSP_version0     (1<<0)
367 #define HDSP_version1     (1<<1)
368 #define HDSP_version2     (1<<2)
369 #define HDSP_wc_lock      (1<<3)
370 #define HDSP_wc_sync      (1<<4)
371 #define HDSP_inp_freq0    (1<<5)
372 #define HDSP_inp_freq1    (1<<6)
373 #define HDSP_inp_freq2    (1<<7)
374 #define HDSP_SelSyncRef0  (1<<8)
375 #define HDSP_SelSyncRef1  (1<<9)
376 #define HDSP_SelSyncRef2  (1<<10)
377 
378 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
379 
380 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
381 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
382 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
383 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
384 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
385 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
386 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
387 /* FIXME : more values for 9632 cards ? */
388 
389 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
390 #define HDSP_SelSyncRef_ADAT1      0
391 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
392 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
393 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
394 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
395 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
396 
397 /* Card state flags */
398 
399 #define HDSP_InitializationComplete  (1<<0)
400 #define HDSP_FirmwareLoaded          (1<<1)
401 #define HDSP_FirmwareCached          (1<<2)
402 
403 /* FIFO wait times, defined in terms of 1/10ths of msecs */
404 
405 #define HDSP_LONG_WAIT   5000
406 #define HDSP_SHORT_WAIT  30
407 
408 #define UNITY_GAIN                       32768
409 #define MINUS_INFINITY_GAIN              0
410 
411 /* the size of a substream (1 mono data stream) */
412 
413 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
414 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
415 
416 /* the size of the area we need to allocate for DMA transfers. the
417    size is the same regardless of the number of channels - the
418    Multiface still uses the same memory area.
419 
420    Note that we allocate 1 more channel than is apparently needed
421    because the h/w seems to write 1 byte beyond the end of the last
422    page. Sigh.
423 */
424 
425 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
426 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
427 
428 #define HDSP_FIRMWARE_SIZE      (24413 * 4)
429 
430 struct hdsp_9632_meters {
431     u32 input_peak[16];
432     u32 playback_peak[16];
433     u32 output_peak[16];
434     u32 xxx_peak[16];
435     u32 padding[64];
436     u32 input_rms_low[16];
437     u32 playback_rms_low[16];
438     u32 output_rms_low[16];
439     u32 xxx_rms_low[16];
440     u32 input_rms_high[16];
441     u32 playback_rms_high[16];
442     u32 output_rms_high[16];
443     u32 xxx_rms_high[16];
444 };
445 
446 struct hdsp_midi {
447     struct hdsp             *hdsp;
448     int                      id;
449     struct snd_rawmidi           *rmidi;
450     struct snd_rawmidi_substream *input;
451     struct snd_rawmidi_substream *output;
452     char                     istimer; /* timer in use */
453     struct timer_list        timer;
454     spinlock_t               lock;
455     int                      pending;
456 };
457 
458 struct hdsp {
459         spinlock_t            lock;
460         struct snd_pcm_substream *capture_substream;
461         struct snd_pcm_substream *playback_substream;
462         struct hdsp_midi      midi[2];
463         struct tasklet_struct midi_tasklet;
464         int                   use_midi_tasklet;
465         int                   precise_ptr;
466         u32                   control_register;      /* cached value */
467         u32                   control2_register;     /* cached value */
468         u32                   creg_spdif;
469         u32                   creg_spdif_stream;
470         int                   clock_source_locked;
471         char                 *card_name;         /* digiface/multiface/rpm */
472         enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
473         unsigned short        firmware_rev;
474         unsigned short        state;                 /* stores state bits */
475         const struct firmware *firmware;
476         u32                  *fw_uploaded;
477         size_t                period_bytes;          /* guess what this is */
478         unsigned char         max_channels;
479         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
480         unsigned char         ds_in_channels;
481         unsigned char         ss_in_channels;       /* different for multiface/digiface */
482         unsigned char         qs_out_channels;
483         unsigned char         ds_out_channels;
484         unsigned char         ss_out_channels;
485 
486         struct snd_dma_buffer capture_dma_buf;
487         struct snd_dma_buffer playback_dma_buf;
488         unsigned char        *capture_buffer;       /* suitably aligned address */
489         unsigned char        *playback_buffer;      /* suitably aligned address */
490 
491         pid_t                 capture_pid;
492         pid_t                 playback_pid;
493         int                   running;
494         int                   system_sample_rate;
495         char                 *channel_map;
496         int                   dev;
497         int                   irq;
498         unsigned long         port;
499         void __iomem         *iobase;
500         struct snd_card *card;
501         struct snd_pcm *pcm;
502         struct snd_hwdep          *hwdep;
503         struct pci_dev       *pci;
504         struct snd_kcontrol *spdif_ctl;
505         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
506         unsigned int          dds_value; /* last value written to freq register */
507 };
508 
509 /* These tables map the ALSA channels 1..N to the channels that we
510    need to use in order to find the relevant channel buffer. RME
511    refer to this kind of mapping as between "the ADAT channel and
512    the DMA channel." We index it using the logical audio channel,
513    and the value is the DMA channel (i.e. channel buffer number)
514    where the data for that channel can be read/written from/to.
515 */
516 
517 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
518         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
519         18, 19, 20, 21, 22, 23, 24, 25
520 };
521 
522 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
523         /* Analog */
524         0, 1, 2, 3, 4, 5, 6, 7,
525         /* ADAT 2 */
526         16, 17, 18, 19, 20, 21, 22, 23,
527         /* SPDIF */
528         24, 25,
529         -1, -1, -1, -1, -1, -1, -1, -1
530 };
531 
532 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
533         /* ADAT channels are remapped */
534         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
535         /* channels 12 and 13 are S/PDIF */
536         24, 25,
537         /* others don't exist */
538         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
539 };
540 
541 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
542         /* ADAT channels */
543         0, 1, 2, 3, 4, 5, 6, 7,
544         /* SPDIF */
545         8, 9,
546         /* Analog */
547         10, 11,
548         /* AO4S-192 and AI4S-192 extension boards */
549         12, 13, 14, 15,
550         /* others don't exist */
551         -1, -1, -1, -1, -1, -1, -1, -1,
552         -1, -1
553 };
554 
555 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
556         /* ADAT */
557         1, 3, 5, 7,
558         /* SPDIF */
559         8, 9,
560         /* Analog */
561         10, 11,
562         /* AO4S-192 and AI4S-192 extension boards */
563         12, 13, 14, 15,
564         /* others don't exist */
565         -1, -1, -1, -1, -1, -1, -1, -1,
566         -1, -1, -1, -1, -1, -1
567 };
568 
569 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
570         /* ADAT is disabled in this mode */
571         /* SPDIF */
572         8, 9,
573         /* Analog */
574         10, 11,
575         /* AO4S-192 and AI4S-192 extension boards */
576         12, 13, 14, 15,
577         /* others don't exist */
578         -1, -1, -1, -1, -1, -1, -1, -1,
579         -1, -1, -1, -1, -1, -1, -1, -1,
580         -1, -1
581 };
582 
583 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
584 {
585         dmab->dev.type = SNDRV_DMA_TYPE_DEV;
586         dmab->dev.dev = snd_dma_pci_data(pci);
587         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
588                                 size, dmab) < 0)
589                 return -ENOMEM;
590         return 0;
591 }
592 
593 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
594 {
595         if (dmab->area)
596                 snd_dma_free_pages(dmab);
597 }
598 
599 
600 static const struct pci_device_id snd_hdsp_ids[] = {
601         {
602                 .vendor = PCI_VENDOR_ID_XILINX,
603                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
604                 .subvendor = PCI_ANY_ID,
605                 .subdevice = PCI_ANY_ID,
606         }, /* RME Hammerfall-DSP */
607         { 0, },
608 };
609 
610 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
611 
612 /* prototypes */
613 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
614 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
615 static int snd_hdsp_enable_io (struct hdsp *hdsp);
616 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
617 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
618 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
619 static int hdsp_autosync_ref(struct hdsp *hdsp);
620 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
621 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
622 
623 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
624 {
625         switch (hdsp->io_type) {
626         case Multiface:
627         case Digiface:
628         case RPM:
629         default:
630                 if (hdsp->firmware_rev == 0xa)
631                         return (64 * out) + (32 + (in));
632                 else
633                         return (52 * out) + (26 + (in));
634         case H9632:
635                 return (32 * out) + (16 + (in));
636         case H9652:
637                 return (52 * out) + (26 + (in));
638         }
639 }
640 
641 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
642 {
643         switch (hdsp->io_type) {
644         case Multiface:
645         case Digiface:
646         case RPM:
647         default:
648                 if (hdsp->firmware_rev == 0xa)
649                         return (64 * out) + in;
650                 else
651                         return (52 * out) + in;
652         case H9632:
653                 return (32 * out) + in;
654         case H9652:
655                 return (52 * out) + in;
656         }
657 }
658 
659 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
660 {
661         writel(val, hdsp->iobase + reg);
662 }
663 
664 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
665 {
666         return readl (hdsp->iobase + reg);
667 }
668 
669 static int hdsp_check_for_iobox (struct hdsp *hdsp)
670 {
671         int i;
672 
673         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
674         for (i = 0; i < 500; i++) {
675                 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
676                                         HDSP_ConfigError)) {
677                         if (i) {
678                                 dev_dbg(hdsp->card->dev,
679                                         "IO box found after %d ms\n",
680                                                 (20 * i));
681                         }
682                         return 0;
683                 }
684                 msleep(20);
685         }
686         dev_err(hdsp->card->dev, "no IO box connected!\n");
687         hdsp->state &= ~HDSP_FirmwareLoaded;
688         return -EIO;
689 }
690 
691 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
692                                unsigned int delay)
693 {
694         unsigned int i;
695 
696         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
697                 return 0;
698 
699         for (i = 0; i != loops; ++i) {
700                 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
701                         msleep(delay);
702                 else {
703                         dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
704                                    i * delay);
705                         return 0;
706                 }
707         }
708 
709         dev_info(hdsp->card->dev, "no IO box connected!\n");
710         hdsp->state &= ~HDSP_FirmwareLoaded;
711         return -EIO;
712 }
713 
714 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
715 
716         int i;
717         unsigned long flags;
718         const u32 *cache;
719 
720         if (hdsp->fw_uploaded)
721                 cache = hdsp->fw_uploaded;
722         else {
723                 if (!hdsp->firmware)
724                         return -ENODEV;
725                 cache = (u32 *)hdsp->firmware->data;
726                 if (!cache)
727                         return -ENODEV;
728         }
729 
730         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
731 
732                 dev_info(hdsp->card->dev, "loading firmware\n");
733 
734                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
735                 hdsp_write (hdsp, HDSP_fifoData, 0);
736 
737                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
738                         dev_info(hdsp->card->dev,
739                                  "timeout waiting for download preparation\n");
740                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
741                         return -EIO;
742                 }
743 
744                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
745 
746                 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
747                         hdsp_write(hdsp, HDSP_fifoData, cache[i]);
748                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
749                                 dev_info(hdsp->card->dev,
750                                          "timeout during firmware loading\n");
751                                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
752                                 return -EIO;
753                         }
754                 }
755 
756                 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
757                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
758 
759                 ssleep(3);
760 #ifdef SNDRV_BIG_ENDIAN
761                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
762 #else
763                 hdsp->control2_register = 0;
764 #endif
765                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
766                 dev_info(hdsp->card->dev, "finished firmware loading\n");
767 
768         }
769         if (hdsp->state & HDSP_InitializationComplete) {
770                 dev_info(hdsp->card->dev,
771                          "firmware loaded from cache, restoring defaults\n");
772                 spin_lock_irqsave(&hdsp->lock, flags);
773                 snd_hdsp_set_defaults(hdsp);
774                 spin_unlock_irqrestore(&hdsp->lock, flags);
775         }
776 
777         hdsp->state |= HDSP_FirmwareLoaded;
778 
779         return 0;
780 }
781 
782 static int hdsp_get_iobox_version (struct hdsp *hdsp)
783 {
784         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
785 
786                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
787                 hdsp_write(hdsp, HDSP_fifoData, 0);
788 
789                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
790                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
791                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
792                 }
793 
794                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
795                 hdsp_write (hdsp, HDSP_fifoData, 0);
796                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
797                         hdsp->io_type = Multiface;
798                         dev_info(hdsp->card->dev, "Multiface found\n");
799                         return 0;
800                 }
801 
802                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
803                 hdsp_write(hdsp, HDSP_fifoData, 0);
804                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
805                         hdsp->io_type = Digiface;
806                         dev_info(hdsp->card->dev, "Digiface found\n");
807                         return 0;
808                 }
809 
810                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
811                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
812                 hdsp_write(hdsp, HDSP_fifoData, 0);
813                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
814                         hdsp->io_type = Multiface;
815                         dev_info(hdsp->card->dev, "Multiface found\n");
816                         return 0;
817                 }
818 
819                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
820                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
821                 hdsp_write(hdsp, HDSP_fifoData, 0);
822                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
823                         hdsp->io_type = Multiface;
824                         dev_info(hdsp->card->dev, "Multiface found\n");
825                         return 0;
826                 }
827 
828                 hdsp->io_type = RPM;
829                 dev_info(hdsp->card->dev, "RPM found\n");
830                 return 0;
831         } else {
832                 /* firmware was already loaded, get iobox type */
833                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
834                         hdsp->io_type = RPM;
835                 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
836                         hdsp->io_type = Multiface;
837                 else
838                         hdsp->io_type = Digiface;
839         }
840         return 0;
841 }
842 
843 
844 static int hdsp_request_fw_loader(struct hdsp *hdsp);
845 
846 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
847 {
848         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
849                 return 0;
850         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
851                 hdsp->state &= ~HDSP_FirmwareLoaded;
852                 if (! load_on_demand)
853                         return -EIO;
854                 dev_err(hdsp->card->dev, "firmware not present.\n");
855                 /* try to load firmware */
856                 if (! (hdsp->state & HDSP_FirmwareCached)) {
857                         if (! hdsp_request_fw_loader(hdsp))
858                                 return 0;
859                         dev_err(hdsp->card->dev,
860                                    "No firmware loaded nor cached, please upload firmware.\n");
861                         return -EIO;
862                 }
863                 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
864                         dev_err(hdsp->card->dev,
865                                    "Firmware loading from cache failed, please upload manually.\n");
866                         return -EIO;
867                 }
868         }
869         return 0;
870 }
871 
872 
873 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
874 {
875         int i;
876 
877         /* the fifoStatus registers reports on how many words
878            are available in the command FIFO.
879         */
880 
881         for (i = 0; i < timeout; i++) {
882 
883                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
884                         return 0;
885 
886                 /* not very friendly, but we only do this during a firmware
887                    load and changing the mixer, so we just put up with it.
888                 */
889 
890                 udelay (100);
891         }
892 
893         dev_warn(hdsp->card->dev,
894                  "wait for FIFO status <= %d failed after %d iterations\n",
895                     count, timeout);
896         return -1;
897 }
898 
899 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
900 {
901         if (addr >= HDSP_MATRIX_MIXER_SIZE)
902                 return 0;
903 
904         return hdsp->mixer_matrix[addr];
905 }
906 
907 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
908 {
909         unsigned int ad;
910 
911         if (addr >= HDSP_MATRIX_MIXER_SIZE)
912                 return -1;
913 
914         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
915 
916                 /* from martin bjornsen:
917 
918                    "You can only write dwords to the
919                    mixer memory which contain two
920                    mixer values in the low and high
921                    word. So if you want to change
922                    value 0 you have to read value 1
923                    from the cache and write both to
924                    the first dword in the mixer
925                    memory."
926                 */
927 
928                 if (hdsp->io_type == H9632 && addr >= 512)
929                         return 0;
930 
931                 if (hdsp->io_type == H9652 && addr >= 1352)
932                         return 0;
933 
934                 hdsp->mixer_matrix[addr] = data;
935 
936 
937                 /* `addr' addresses a 16-bit wide address, but
938                    the address space accessed via hdsp_write
939                    uses byte offsets. put another way, addr
940                    varies from 0 to 1351, but to access the
941                    corresponding memory location, we need
942                    to access 0 to 2703 ...
943                 */
944                 ad = addr/2;
945 
946                 hdsp_write (hdsp, 4096 + (ad*4),
947                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
948                             hdsp->mixer_matrix[addr&0x7fe]);
949 
950                 return 0;
951 
952         } else {
953 
954                 ad = (addr << 16) + data;
955 
956                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
957                         return -1;
958 
959                 hdsp_write (hdsp, HDSP_fifoData, ad);
960                 hdsp->mixer_matrix[addr] = data;
961 
962         }
963 
964         return 0;
965 }
966 
967 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
968 {
969         unsigned long flags;
970         int ret = 1;
971 
972         spin_lock_irqsave(&hdsp->lock, flags);
973         if ((hdsp->playback_pid != hdsp->capture_pid) &&
974             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
975                 ret = 0;
976         spin_unlock_irqrestore(&hdsp->lock, flags);
977         return ret;
978 }
979 
980 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
981 {
982         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
983         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
984 
985         /* For the 9632, the mask is different */
986         if (hdsp->io_type == H9632)
987                  rate_bits = (status & HDSP_spdifFrequencyMask_9632);
988 
989         if (status & HDSP_SPDIFErrorFlag)
990                 return 0;
991 
992         switch (rate_bits) {
993         case HDSP_spdifFrequency32KHz: return 32000;
994         case HDSP_spdifFrequency44_1KHz: return 44100;
995         case HDSP_spdifFrequency48KHz: return 48000;
996         case HDSP_spdifFrequency64KHz: return 64000;
997         case HDSP_spdifFrequency88_2KHz: return 88200;
998         case HDSP_spdifFrequency96KHz: return 96000;
999         case HDSP_spdifFrequency128KHz:
1000                 if (hdsp->io_type == H9632) return 128000;
1001                 break;
1002         case HDSP_spdifFrequency176_4KHz:
1003                 if (hdsp->io_type == H9632) return 176400;
1004                 break;
1005         case HDSP_spdifFrequency192KHz:
1006                 if (hdsp->io_type == H9632) return 192000;
1007                 break;
1008         default:
1009                 break;
1010         }
1011         dev_warn(hdsp->card->dev,
1012                  "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
1013                  rate_bits, status);
1014         return 0;
1015 }
1016 
1017 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1018 {
1019         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1020         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1021 
1022         /* For the 9632 card, there seems to be no bit for indicating external
1023          * sample rate greater than 96kHz. The card reports the corresponding
1024          * single speed. So the best means seems to get spdif rate when
1025          * autosync reference is spdif */
1026         if (hdsp->io_type == H9632 &&
1027             hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1028                  return hdsp_spdif_sample_rate(hdsp);
1029 
1030         switch (rate_bits) {
1031         case HDSP_systemFrequency32:   return 32000;
1032         case HDSP_systemFrequency44_1: return 44100;
1033         case HDSP_systemFrequency48:   return 48000;
1034         case HDSP_systemFrequency64:   return 64000;
1035         case HDSP_systemFrequency88_2: return 88200;
1036         case HDSP_systemFrequency96:   return 96000;
1037         default:
1038                 return 0;
1039         }
1040 }
1041 
1042 static void hdsp_compute_period_size(struct hdsp *hdsp)
1043 {
1044         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1045 }
1046 
1047 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1048 {
1049         int position;
1050 
1051         position = hdsp_read(hdsp, HDSP_statusRegister);
1052 
1053         if (!hdsp->precise_ptr)
1054                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1055 
1056         position &= HDSP_BufferPositionMask;
1057         position /= 4;
1058         position &= (hdsp->period_bytes/2) - 1;
1059         return position;
1060 }
1061 
1062 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1063 {
1064         hdsp_write (hdsp, HDSP_resetPointer, 0);
1065         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1066                 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1067                  * requires (?) to write again DDS value after a reset pointer
1068                  * (at least, it works like this) */
1069                 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1070 }
1071 
1072 static void hdsp_start_audio(struct hdsp *s)
1073 {
1074         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1075         hdsp_write(s, HDSP_controlRegister, s->control_register);
1076 }
1077 
1078 static void hdsp_stop_audio(struct hdsp *s)
1079 {
1080         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1081         hdsp_write(s, HDSP_controlRegister, s->control_register);
1082 }
1083 
1084 static void hdsp_silence_playback(struct hdsp *hdsp)
1085 {
1086         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1087 }
1088 
1089 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1090 {
1091         int n;
1092 
1093         spin_lock_irq(&s->lock);
1094 
1095         frames >>= 7;
1096         n = 0;
1097         while (frames) {
1098                 n++;
1099                 frames >>= 1;
1100         }
1101 
1102         s->control_register &= ~HDSP_LatencyMask;
1103         s->control_register |= hdsp_encode_latency(n);
1104 
1105         hdsp_write(s, HDSP_controlRegister, s->control_register);
1106 
1107         hdsp_compute_period_size(s);
1108 
1109         spin_unlock_irq(&s->lock);
1110 
1111         return 0;
1112 }
1113 
1114 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1115 {
1116         u64 n;
1117 
1118         if (rate >= 112000)
1119                 rate /= 4;
1120         else if (rate >= 56000)
1121                 rate /= 2;
1122 
1123         n = DDS_NUMERATOR;
1124         n = div_u64(n, rate);
1125         /* n should be less than 2^32 for being written to FREQ register */
1126         snd_BUG_ON(n >> 32);
1127         /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1128            value to write it after a reset */
1129         hdsp->dds_value = n;
1130         hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1131 }
1132 
1133 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1134 {
1135         int reject_if_open = 0;
1136         int current_rate;
1137         int rate_bits;
1138 
1139         /* ASSUMPTION: hdsp->lock is either held, or
1140            there is no need for it (e.g. during module
1141            initialization).
1142         */
1143 
1144         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1145                 if (called_internally) {
1146                         /* request from ctl or card initialization */
1147                         dev_err(hdsp->card->dev,
1148                                 "device is not running as a clock master: cannot set sample rate.\n");
1149                         return -1;
1150                 } else {
1151                         /* hw_param request while in AutoSync mode */
1152                         int external_freq = hdsp_external_sample_rate(hdsp);
1153                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1154 
1155                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1156                                 dev_info(hdsp->card->dev,
1157                                          "Detected ADAT in double speed mode\n");
1158                         else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1159                                 dev_info(hdsp->card->dev,
1160                                          "Detected ADAT in quad speed mode\n");
1161                         else if (rate != external_freq) {
1162                                 dev_info(hdsp->card->dev,
1163                                          "No AutoSync source for requested rate\n");
1164                                 return -1;
1165                         }
1166                 }
1167         }
1168 
1169         current_rate = hdsp->system_sample_rate;
1170 
1171         /* Changing from a "single speed" to a "double speed" rate is
1172            not allowed if any substreams are open. This is because
1173            such a change causes a shift in the location of
1174            the DMA buffers and a reduction in the number of available
1175            buffers.
1176 
1177            Note that a similar but essentially insoluble problem
1178            exists for externally-driven rate changes. All we can do
1179            is to flag rate changes in the read/write routines.  */
1180 
1181         if (rate > 96000 && hdsp->io_type != H9632)
1182                 return -EINVAL;
1183 
1184         switch (rate) {
1185         case 32000:
1186                 if (current_rate > 48000)
1187                         reject_if_open = 1;
1188                 rate_bits = HDSP_Frequency32KHz;
1189                 break;
1190         case 44100:
1191                 if (current_rate > 48000)
1192                         reject_if_open = 1;
1193                 rate_bits = HDSP_Frequency44_1KHz;
1194                 break;
1195         case 48000:
1196                 if (current_rate > 48000)
1197                         reject_if_open = 1;
1198                 rate_bits = HDSP_Frequency48KHz;
1199                 break;
1200         case 64000:
1201                 if (current_rate <= 48000 || current_rate > 96000)
1202                         reject_if_open = 1;
1203                 rate_bits = HDSP_Frequency64KHz;
1204                 break;
1205         case 88200:
1206                 if (current_rate <= 48000 || current_rate > 96000)
1207                         reject_if_open = 1;
1208                 rate_bits = HDSP_Frequency88_2KHz;
1209                 break;
1210         case 96000:
1211                 if (current_rate <= 48000 || current_rate > 96000)
1212                         reject_if_open = 1;
1213                 rate_bits = HDSP_Frequency96KHz;
1214                 break;
1215         case 128000:
1216                 if (current_rate < 128000)
1217                         reject_if_open = 1;
1218                 rate_bits = HDSP_Frequency128KHz;
1219                 break;
1220         case 176400:
1221                 if (current_rate < 128000)
1222                         reject_if_open = 1;
1223                 rate_bits = HDSP_Frequency176_4KHz;
1224                 break;
1225         case 192000:
1226                 if (current_rate < 128000)
1227                         reject_if_open = 1;
1228                 rate_bits = HDSP_Frequency192KHz;
1229                 break;
1230         default:
1231                 return -EINVAL;
1232         }
1233 
1234         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1235                 dev_warn(hdsp->card->dev,
1236                          "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1237                             hdsp->capture_pid,
1238                             hdsp->playback_pid);
1239                 return -EBUSY;
1240         }
1241 
1242         hdsp->control_register &= ~HDSP_FrequencyMask;
1243         hdsp->control_register |= rate_bits;
1244         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1245 
1246         /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1247         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1248                 hdsp_set_dds_value(hdsp, rate);
1249 
1250         if (rate >= 128000) {
1251                 hdsp->channel_map = channel_map_H9632_qs;
1252         } else if (rate > 48000) {
1253                 if (hdsp->io_type == H9632)
1254                         hdsp->channel_map = channel_map_H9632_ds;
1255                 else
1256                         hdsp->channel_map = channel_map_ds;
1257         } else {
1258                 switch (hdsp->io_type) {
1259                 case RPM:
1260                 case Multiface:
1261                         hdsp->channel_map = channel_map_mf_ss;
1262                         break;
1263                 case Digiface:
1264                 case H9652:
1265                         hdsp->channel_map = channel_map_df_ss;
1266                         break;
1267                 case H9632:
1268                         hdsp->channel_map = channel_map_H9632_ss;
1269                         break;
1270                 default:
1271                         /* should never happen */
1272                         break;
1273                 }
1274         }
1275 
1276         hdsp->system_sample_rate = rate;
1277 
1278         return 0;
1279 }
1280 
1281 /*----------------------------------------------------------------------------
1282    MIDI
1283   ----------------------------------------------------------------------------*/
1284 
1285 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1286 {
1287         /* the hardware already does the relevant bit-mask with 0xff */
1288         if (id)
1289                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1290         else
1291                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1292 }
1293 
1294 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1295 {
1296         /* the hardware already does the relevant bit-mask with 0xff */
1297         if (id)
1298                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1299         else
1300                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1301 }
1302 
1303 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1304 {
1305         if (id)
1306                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1307         else
1308                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1309 }
1310 
1311 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1312 {
1313         int fifo_bytes_used;
1314 
1315         if (id)
1316                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1317         else
1318                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1319 
1320         if (fifo_bytes_used < 128)
1321                 return  128 - fifo_bytes_used;
1322         else
1323                 return 0;
1324 }
1325 
1326 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1327 {
1328         while (snd_hdsp_midi_input_available (hdsp, id))
1329                 snd_hdsp_midi_read_byte (hdsp, id);
1330 }
1331 
1332 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1333 {
1334         unsigned long flags;
1335         int n_pending;
1336         int to_write;
1337         int i;
1338         unsigned char buf[128];
1339 
1340         /* Output is not interrupt driven */
1341 
1342         spin_lock_irqsave (&hmidi->lock, flags);
1343         if (hmidi->output) {
1344                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1345                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1346                                 if (n_pending > (int)sizeof (buf))
1347                                         n_pending = sizeof (buf);
1348 
1349                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1350                                         for (i = 0; i < to_write; ++i)
1351                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1352                                 }
1353                         }
1354                 }
1355         }
1356         spin_unlock_irqrestore (&hmidi->lock, flags);
1357         return 0;
1358 }
1359 
1360 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1361 {
1362         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1363         unsigned long flags;
1364         int n_pending;
1365         int i;
1366 
1367         spin_lock_irqsave (&hmidi->lock, flags);
1368         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1369                 if (hmidi->input) {
1370                         if (n_pending > (int)sizeof (buf))
1371                                 n_pending = sizeof (buf);
1372                         for (i = 0; i < n_pending; ++i)
1373                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1374                         if (n_pending)
1375                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1376                 } else {
1377                         /* flush the MIDI input FIFO */
1378                         while (--n_pending)
1379                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1380                 }
1381         }
1382         hmidi->pending = 0;
1383         if (hmidi->id)
1384                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1385         else
1386                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1387         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1388         spin_unlock_irqrestore (&hmidi->lock, flags);
1389         return snd_hdsp_midi_output_write (hmidi);
1390 }
1391 
1392 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1393 {
1394         struct hdsp *hdsp;
1395         struct hdsp_midi *hmidi;
1396         unsigned long flags;
1397         u32 ie;
1398 
1399         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1400         hdsp = hmidi->hdsp;
1401         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1402         spin_lock_irqsave (&hdsp->lock, flags);
1403         if (up) {
1404                 if (!(hdsp->control_register & ie)) {
1405                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1406                         hdsp->control_register |= ie;
1407                 }
1408         } else {
1409                 hdsp->control_register &= ~ie;
1410                 tasklet_kill(&hdsp->midi_tasklet);
1411         }
1412 
1413         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1414         spin_unlock_irqrestore (&hdsp->lock, flags);
1415 }
1416 
1417 static void snd_hdsp_midi_output_timer(unsigned long data)
1418 {
1419         struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1420         unsigned long flags;
1421 
1422         snd_hdsp_midi_output_write(hmidi);
1423         spin_lock_irqsave (&hmidi->lock, flags);
1424 
1425         /* this does not bump hmidi->istimer, because the
1426            kernel automatically removed the timer when it
1427            expired, and we are now adding it back, thus
1428            leaving istimer wherever it was set before.
1429         */
1430 
1431         if (hmidi->istimer) {
1432                 hmidi->timer.expires = 1 + jiffies;
1433                 add_timer(&hmidi->timer);
1434         }
1435 
1436         spin_unlock_irqrestore (&hmidi->lock, flags);
1437 }
1438 
1439 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1440 {
1441         struct hdsp_midi *hmidi;
1442         unsigned long flags;
1443 
1444         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1445         spin_lock_irqsave (&hmidi->lock, flags);
1446         if (up) {
1447                 if (!hmidi->istimer) {
1448                         init_timer(&hmidi->timer);
1449                         hmidi->timer.function = snd_hdsp_midi_output_timer;
1450                         hmidi->timer.data = (unsigned long) hmidi;
1451                         hmidi->timer.expires = 1 + jiffies;
1452                         add_timer(&hmidi->timer);
1453                         hmidi->istimer++;
1454                 }
1455         } else {
1456                 if (hmidi->istimer && --hmidi->istimer <= 0)
1457                         del_timer (&hmidi->timer);
1458         }
1459         spin_unlock_irqrestore (&hmidi->lock, flags);
1460         if (up)
1461                 snd_hdsp_midi_output_write(hmidi);
1462 }
1463 
1464 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1465 {
1466         struct hdsp_midi *hmidi;
1467 
1468         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1469         spin_lock_irq (&hmidi->lock);
1470         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1471         hmidi->input = substream;
1472         spin_unlock_irq (&hmidi->lock);
1473 
1474         return 0;
1475 }
1476 
1477 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1478 {
1479         struct hdsp_midi *hmidi;
1480 
1481         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1482         spin_lock_irq (&hmidi->lock);
1483         hmidi->output = substream;
1484         spin_unlock_irq (&hmidi->lock);
1485 
1486         return 0;
1487 }
1488 
1489 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1490 {
1491         struct hdsp_midi *hmidi;
1492 
1493         snd_hdsp_midi_input_trigger (substream, 0);
1494 
1495         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1496         spin_lock_irq (&hmidi->lock);
1497         hmidi->input = NULL;
1498         spin_unlock_irq (&hmidi->lock);
1499 
1500         return 0;
1501 }
1502 
1503 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1504 {
1505         struct hdsp_midi *hmidi;
1506 
1507         snd_hdsp_midi_output_trigger (substream, 0);
1508 
1509         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1510         spin_lock_irq (&hmidi->lock);
1511         hmidi->output = NULL;
1512         spin_unlock_irq (&hmidi->lock);
1513 
1514         return 0;
1515 }
1516 
1517 static struct snd_rawmidi_ops snd_hdsp_midi_output =
1518 {
1519         .open =         snd_hdsp_midi_output_open,
1520         .close =        snd_hdsp_midi_output_close,
1521         .trigger =      snd_hdsp_midi_output_trigger,
1522 };
1523 
1524 static struct snd_rawmidi_ops snd_hdsp_midi_input =
1525 {
1526         .open =         snd_hdsp_midi_input_open,
1527         .close =        snd_hdsp_midi_input_close,
1528         .trigger =      snd_hdsp_midi_input_trigger,
1529 };
1530 
1531 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1532 {
1533         char buf[32];
1534 
1535         hdsp->midi[id].id = id;
1536         hdsp->midi[id].rmidi = NULL;
1537         hdsp->midi[id].input = NULL;
1538         hdsp->midi[id].output = NULL;
1539         hdsp->midi[id].hdsp = hdsp;
1540         hdsp->midi[id].istimer = 0;
1541         hdsp->midi[id].pending = 0;
1542         spin_lock_init (&hdsp->midi[id].lock);
1543 
1544         sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1545         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1546                 return -1;
1547 
1548         sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1549         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1550 
1551         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1552         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1553 
1554         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1555                 SNDRV_RAWMIDI_INFO_INPUT |
1556                 SNDRV_RAWMIDI_INFO_DUPLEX;
1557 
1558         return 0;
1559 }
1560 
1561 /*-----------------------------------------------------------------------------
1562   Control Interface
1563   ----------------------------------------------------------------------------*/
1564 
1565 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1566 {
1567         u32 val = 0;
1568         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1569         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1570         if (val & HDSP_SPDIFProfessional)
1571                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1572         else
1573                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1574         return val;
1575 }
1576 
1577 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1578 {
1579         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1580                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1581         if (val & HDSP_SPDIFProfessional)
1582                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1583         else
1584                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1585 }
1586 
1587 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1588 {
1589         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1590         uinfo->count = 1;
1591         return 0;
1592 }
1593 
1594 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1595 {
1596         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1597 
1598         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1599         return 0;
1600 }
1601 
1602 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1603 {
1604         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1605         int change;
1606         u32 val;
1607 
1608         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1609         spin_lock_irq(&hdsp->lock);
1610         change = val != hdsp->creg_spdif;
1611         hdsp->creg_spdif = val;
1612         spin_unlock_irq(&hdsp->lock);
1613         return change;
1614 }
1615 
1616 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1617 {
1618         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1619         uinfo->count = 1;
1620         return 0;
1621 }
1622 
1623 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1624 {
1625         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1626 
1627         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1628         return 0;
1629 }
1630 
1631 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1632 {
1633         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1634         int change;
1635         u32 val;
1636 
1637         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1638         spin_lock_irq(&hdsp->lock);
1639         change = val != hdsp->creg_spdif_stream;
1640         hdsp->creg_spdif_stream = val;
1641         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1642         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1643         spin_unlock_irq(&hdsp->lock);
1644         return change;
1645 }
1646 
1647 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1648 {
1649         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1650         uinfo->count = 1;
1651         return 0;
1652 }
1653 
1654 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1655 {
1656         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1657         return 0;
1658 }
1659 
1660 #define HDSP_SPDIF_IN(xname, xindex) \
1661 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1662   .name = xname, \
1663   .index = xindex, \
1664   .info = snd_hdsp_info_spdif_in, \
1665   .get = snd_hdsp_get_spdif_in, \
1666   .put = snd_hdsp_put_spdif_in }
1667 
1668 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1669 {
1670         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1671 }
1672 
1673 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1674 {
1675         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1676         hdsp->control_register |= hdsp_encode_spdif_in(in);
1677         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1678         return 0;
1679 }
1680 
1681 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1682 {
1683         static const char * const texts[4] = {
1684                 "Optical", "Coaxial", "Internal", "AES"
1685         };
1686         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1687 
1688         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1689                                  texts);
1690 }
1691 
1692 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1693 {
1694         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1695 
1696         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1697         return 0;
1698 }
1699 
1700 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1701 {
1702         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1703         int change;
1704         unsigned int val;
1705 
1706         if (!snd_hdsp_use_is_exclusive(hdsp))
1707                 return -EBUSY;
1708         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1709         spin_lock_irq(&hdsp->lock);
1710         change = val != hdsp_spdif_in(hdsp);
1711         if (change)
1712                 hdsp_set_spdif_input(hdsp, val);
1713         spin_unlock_irq(&hdsp->lock);
1714         return change;
1715 }
1716 
1717 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1718 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1719         .name = xname, \
1720         .private_value = xindex, \
1721         .info = snd_hdsp_info_toggle_setting, \
1722         .get = snd_hdsp_get_toggle_setting, \
1723         .put = snd_hdsp_put_toggle_setting \
1724 }
1725 
1726 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1727 {
1728         return (hdsp->control_register & regmask) ? 1 : 0;
1729 }
1730 
1731 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1732 {
1733         if (out)
1734                 hdsp->control_register |= regmask;
1735         else
1736                 hdsp->control_register &= ~regmask;
1737         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1738 
1739         return 0;
1740 }
1741 
1742 #define snd_hdsp_info_toggle_setting               snd_ctl_boolean_mono_info
1743 
1744 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1745                 struct snd_ctl_elem_value *ucontrol)
1746 {
1747         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1748         u32 regmask = kcontrol->private_value;
1749 
1750         spin_lock_irq(&hdsp->lock);
1751         ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1752         spin_unlock_irq(&hdsp->lock);
1753         return 0;
1754 }
1755 
1756 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1757                 struct snd_ctl_elem_value *ucontrol)
1758 {
1759         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1760         u32 regmask = kcontrol->private_value;
1761         int change;
1762         unsigned int val;
1763 
1764         if (!snd_hdsp_use_is_exclusive(hdsp))
1765                 return -EBUSY;
1766         val = ucontrol->value.integer.value[0] & 1;
1767         spin_lock_irq(&hdsp->lock);
1768         change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1769         if (change)
1770                 hdsp_set_toggle_setting(hdsp, regmask, val);
1771         spin_unlock_irq(&hdsp->lock);
1772         return change;
1773 }
1774 
1775 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1776 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1777   .name = xname, \
1778   .index = xindex, \
1779   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1780   .info = snd_hdsp_info_spdif_sample_rate, \
1781   .get = snd_hdsp_get_spdif_sample_rate \
1782 }
1783 
1784 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1785 {
1786         static const char * const texts[] = {
1787                 "32000", "44100", "48000", "64000", "88200", "96000",
1788                 "None", "128000", "176400", "192000"
1789         };
1790         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1791 
1792         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1793                                  texts);
1794 }
1795 
1796 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1797 {
1798         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1799 
1800         switch (hdsp_spdif_sample_rate(hdsp)) {
1801         case 32000:
1802                 ucontrol->value.enumerated.item[0] = 0;
1803                 break;
1804         case 44100:
1805                 ucontrol->value.enumerated.item[0] = 1;
1806                 break;
1807         case 48000:
1808                 ucontrol->value.enumerated.item[0] = 2;
1809                 break;
1810         case 64000:
1811                 ucontrol->value.enumerated.item[0] = 3;
1812                 break;
1813         case 88200:
1814                 ucontrol->value.enumerated.item[0] = 4;
1815                 break;
1816         case 96000:
1817                 ucontrol->value.enumerated.item[0] = 5;
1818                 break;
1819         case 128000:
1820                 ucontrol->value.enumerated.item[0] = 7;
1821                 break;
1822         case 176400:
1823                 ucontrol->value.enumerated.item[0] = 8;
1824                 break;
1825         case 192000:
1826                 ucontrol->value.enumerated.item[0] = 9;
1827                 break;
1828         default:
1829                 ucontrol->value.enumerated.item[0] = 6;
1830         }
1831         return 0;
1832 }
1833 
1834 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1835 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1836   .name = xname, \
1837   .index = xindex, \
1838   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1839   .info = snd_hdsp_info_system_sample_rate, \
1840   .get = snd_hdsp_get_system_sample_rate \
1841 }
1842 
1843 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1844 {
1845         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1846         uinfo->count = 1;
1847         return 0;
1848 }
1849 
1850 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1851 {
1852         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1853 
1854         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1855         return 0;
1856 }
1857 
1858 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1859 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1860   .name = xname, \
1861   .index = xindex, \
1862   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1863   .info = snd_hdsp_info_autosync_sample_rate, \
1864   .get = snd_hdsp_get_autosync_sample_rate \
1865 }
1866 
1867 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1868 {
1869         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1870         static const char * const texts[] = {
1871                 "32000", "44100", "48000", "64000", "88200", "96000",
1872                 "None", "128000", "176400", "192000"
1873         };
1874 
1875         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1876                                  texts);
1877 }
1878 
1879 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1880 {
1881         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1882 
1883         switch (hdsp_external_sample_rate(hdsp)) {
1884         case 32000:
1885                 ucontrol->value.enumerated.item[0] = 0;
1886                 break;
1887         case 44100:
1888                 ucontrol->value.enumerated.item[0] = 1;
1889                 break;
1890         case 48000:
1891                 ucontrol->value.enumerated.item[0] = 2;
1892                 break;
1893         case 64000:
1894                 ucontrol->value.enumerated.item[0] = 3;
1895                 break;
1896         case 88200:
1897                 ucontrol->value.enumerated.item[0] = 4;
1898                 break;
1899         case 96000:
1900                 ucontrol->value.enumerated.item[0] = 5;
1901                 break;
1902         case 128000:
1903                 ucontrol->value.enumerated.item[0] = 7;
1904                 break;
1905         case 176400:
1906                 ucontrol->value.enumerated.item[0] = 8;
1907                 break;
1908         case 192000:
1909                 ucontrol->value.enumerated.item[0] = 9;
1910                 break;
1911         default:
1912                 ucontrol->value.enumerated.item[0] = 6;
1913         }
1914         return 0;
1915 }
1916 
1917 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1918 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1919   .name = xname, \
1920   .index = xindex, \
1921   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1922   .info = snd_hdsp_info_system_clock_mode, \
1923   .get = snd_hdsp_get_system_clock_mode \
1924 }
1925 
1926 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1927 {
1928         if (hdsp->control_register & HDSP_ClockModeMaster)
1929                 return 0;
1930         else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1931                         return 0;
1932         return 1;
1933 }
1934 
1935 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1936 {
1937         static const char * const texts[] = {"Master", "Slave" };
1938 
1939         return snd_ctl_enum_info(uinfo, 1, 2, texts);
1940 }
1941 
1942 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1943 {
1944         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1945 
1946         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1947         return 0;
1948 }
1949 
1950 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1951 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1952   .name = xname, \
1953   .index = xindex, \
1954   .info = snd_hdsp_info_clock_source, \
1955   .get = snd_hdsp_get_clock_source, \
1956   .put = snd_hdsp_put_clock_source \
1957 }
1958 
1959 static int hdsp_clock_source(struct hdsp *hdsp)
1960 {
1961         if (hdsp->control_register & HDSP_ClockModeMaster) {
1962                 switch (hdsp->system_sample_rate) {
1963                 case 32000:
1964                         return 1;
1965                 case 44100:
1966                         return 2;
1967                 case 48000:
1968                         return 3;
1969                 case 64000:
1970                         return 4;
1971                 case 88200:
1972                         return 5;
1973                 case 96000:
1974                         return 6;
1975                 case 128000:
1976                         return 7;
1977                 case 176400:
1978                         return 8;
1979                 case 192000:
1980                         return 9;
1981                 default:
1982                         return 3;
1983                 }
1984         } else {
1985                 return 0;
1986         }
1987 }
1988 
1989 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1990 {
1991         int rate;
1992         switch (mode) {
1993         case HDSP_CLOCK_SOURCE_AUTOSYNC:
1994                 if (hdsp_external_sample_rate(hdsp) != 0) {
1995                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1996                         hdsp->control_register &= ~HDSP_ClockModeMaster;
1997                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1998                         return 0;
1999                     }
2000                 }
2001                 return -1;
2002         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2003                 rate = 32000;
2004                 break;
2005         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2006                 rate = 44100;
2007                 break;
2008         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2009                 rate = 48000;
2010                 break;
2011         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2012                 rate = 64000;
2013                 break;
2014         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2015                 rate = 88200;
2016                 break;
2017         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2018                 rate = 96000;
2019                 break;
2020         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2021                 rate = 128000;
2022                 break;
2023         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2024                 rate = 176400;
2025                 break;
2026         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2027                 rate = 192000;
2028                 break;
2029         default:
2030                 rate = 48000;
2031         }
2032         hdsp->control_register |= HDSP_ClockModeMaster;
2033         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2034         hdsp_set_rate(hdsp, rate, 1);
2035         return 0;
2036 }
2037 
2038 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2039 {
2040         static const char * const texts[] = {
2041                 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2042                 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2043                 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2044                 "Internal 192.0 KHz"
2045         };
2046         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2047 
2048         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2049                                  texts);
2050 }
2051 
2052 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2053 {
2054         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2055 
2056         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2057         return 0;
2058 }
2059 
2060 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2061 {
2062         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2063         int change;
2064         int val;
2065 
2066         if (!snd_hdsp_use_is_exclusive(hdsp))
2067                 return -EBUSY;
2068         val = ucontrol->value.enumerated.item[0];
2069         if (val < 0) val = 0;
2070         if (hdsp->io_type == H9632) {
2071                 if (val > 9)
2072                         val = 9;
2073         } else {
2074                 if (val > 6)
2075                         val = 6;
2076         }
2077         spin_lock_irq(&hdsp->lock);
2078         if (val != hdsp_clock_source(hdsp))
2079                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2080         else
2081                 change = 0;
2082         spin_unlock_irq(&hdsp->lock);
2083         return change;
2084 }
2085 
2086 #define snd_hdsp_info_clock_source_lock         snd_ctl_boolean_mono_info
2087 
2088 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2089 {
2090         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2091 
2092         ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2093         return 0;
2094 }
2095 
2096 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2097 {
2098         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2099         int change;
2100 
2101         change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2102         if (change)
2103                 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2104         return change;
2105 }
2106 
2107 #define HDSP_DA_GAIN(xname, xindex) \
2108 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2109   .name = xname, \
2110   .index = xindex, \
2111   .info = snd_hdsp_info_da_gain, \
2112   .get = snd_hdsp_get_da_gain, \
2113   .put = snd_hdsp_put_da_gain \
2114 }
2115 
2116 static int hdsp_da_gain(struct hdsp *hdsp)
2117 {
2118         switch (hdsp->control_register & HDSP_DAGainMask) {
2119         case HDSP_DAGainHighGain:
2120                 return 0;
2121         case HDSP_DAGainPlus4dBu:
2122                 return 1;
2123         case HDSP_DAGainMinus10dBV:
2124                 return 2;
2125         default:
2126                 return 1;
2127         }
2128 }
2129 
2130 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2131 {
2132         hdsp->control_register &= ~HDSP_DAGainMask;
2133         switch (mode) {
2134         case 0:
2135                 hdsp->control_register |= HDSP_DAGainHighGain;
2136                 break;
2137         case 1:
2138                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2139                 break;
2140         case 2:
2141                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2142                 break;
2143         default:
2144                 return -1;
2145 
2146         }
2147         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2148         return 0;
2149 }
2150 
2151 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2152 {
2153         static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2154 
2155         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2156 }
2157 
2158 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2159 {
2160         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2161 
2162         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2163         return 0;
2164 }
2165 
2166 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2167 {
2168         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2169         int change;
2170         int val;
2171 
2172         if (!snd_hdsp_use_is_exclusive(hdsp))
2173                 return -EBUSY;
2174         val = ucontrol->value.enumerated.item[0];
2175         if (val < 0) val = 0;
2176         if (val > 2) val = 2;
2177         spin_lock_irq(&hdsp->lock);
2178         if (val != hdsp_da_gain(hdsp))
2179                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2180         else
2181                 change = 0;
2182         spin_unlock_irq(&hdsp->lock);
2183         return change;
2184 }
2185 
2186 #define HDSP_AD_GAIN(xname, xindex) \
2187 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2188   .name = xname, \
2189   .index = xindex, \
2190   .info = snd_hdsp_info_ad_gain, \
2191   .get = snd_hdsp_get_ad_gain, \
2192   .put = snd_hdsp_put_ad_gain \
2193 }
2194 
2195 static int hdsp_ad_gain(struct hdsp *hdsp)
2196 {
2197         switch (hdsp->control_register & HDSP_ADGainMask) {
2198         case HDSP_ADGainMinus10dBV:
2199                 return 0;
2200         case HDSP_ADGainPlus4dBu:
2201                 return 1;
2202         case HDSP_ADGainLowGain:
2203                 return 2;
2204         default:
2205                 return 1;
2206         }
2207 }
2208 
2209 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2210 {
2211         hdsp->control_register &= ~HDSP_ADGainMask;
2212         switch (mode) {
2213         case 0:
2214                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2215                 break;
2216         case 1:
2217                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2218                 break;
2219         case 2:
2220                 hdsp->control_register |= HDSP_ADGainLowGain;
2221                 break;
2222         default:
2223                 return -1;
2224 
2225         }
2226         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2227         return 0;
2228 }
2229 
2230 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2231 {
2232         static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2233 
2234         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2235 }
2236 
2237 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2238 {
2239         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2240 
2241         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2242         return 0;
2243 }
2244 
2245 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2246 {
2247         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2248         int change;
2249         int val;
2250 
2251         if (!snd_hdsp_use_is_exclusive(hdsp))
2252                 return -EBUSY;
2253         val = ucontrol->value.enumerated.item[0];
2254         if (val < 0) val = 0;
2255         if (val > 2) val = 2;
2256         spin_lock_irq(&hdsp->lock);
2257         if (val != hdsp_ad_gain(hdsp))
2258                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2259         else
2260                 change = 0;
2261         spin_unlock_irq(&hdsp->lock);
2262         return change;
2263 }
2264 
2265 #define HDSP_PHONE_GAIN(xname, xindex) \
2266 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2267   .name = xname, \
2268   .index = xindex, \
2269   .info = snd_hdsp_info_phone_gain, \
2270   .get = snd_hdsp_get_phone_gain, \
2271   .put = snd_hdsp_put_phone_gain \
2272 }
2273 
2274 static int hdsp_phone_gain(struct hdsp *hdsp)
2275 {
2276         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2277         case HDSP_PhoneGain0dB:
2278                 return 0;
2279         case HDSP_PhoneGainMinus6dB:
2280                 return 1;
2281         case HDSP_PhoneGainMinus12dB:
2282                 return 2;
2283         default:
2284                 return 0;
2285         }
2286 }
2287 
2288 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2289 {
2290         hdsp->control_register &= ~HDSP_PhoneGainMask;
2291         switch (mode) {
2292         case 0:
2293                 hdsp->control_register |= HDSP_PhoneGain0dB;
2294                 break;
2295         case 1:
2296                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2297                 break;
2298         case 2:
2299                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2300                 break;
2301         default:
2302                 return -1;
2303 
2304         }
2305         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2306         return 0;
2307 }
2308 
2309 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2310 {
2311         static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2312 
2313         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2314 }
2315 
2316 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2317 {
2318         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2319 
2320         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2321         return 0;
2322 }
2323 
2324 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2325 {
2326         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2327         int change;
2328         int val;
2329 
2330         if (!snd_hdsp_use_is_exclusive(hdsp))
2331                 return -EBUSY;
2332         val = ucontrol->value.enumerated.item[0];
2333         if (val < 0) val = 0;
2334         if (val > 2) val = 2;
2335         spin_lock_irq(&hdsp->lock);
2336         if (val != hdsp_phone_gain(hdsp))
2337                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2338         else
2339                 change = 0;
2340         spin_unlock_irq(&hdsp->lock);
2341         return change;
2342 }
2343 
2344 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2345 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2346   .name = xname, \
2347   .index = xindex, \
2348   .info = snd_hdsp_info_pref_sync_ref, \
2349   .get = snd_hdsp_get_pref_sync_ref, \
2350   .put = snd_hdsp_put_pref_sync_ref \
2351 }
2352 
2353 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2354 {
2355         /* Notice that this looks at the requested sync source,
2356            not the one actually in use.
2357         */
2358 
2359         switch (hdsp->control_register & HDSP_SyncRefMask) {
2360         case HDSP_SyncRef_ADAT1:
2361                 return HDSP_SYNC_FROM_ADAT1;
2362         case HDSP_SyncRef_ADAT2:
2363                 return HDSP_SYNC_FROM_ADAT2;
2364         case HDSP_SyncRef_ADAT3:
2365                 return HDSP_SYNC_FROM_ADAT3;
2366         case HDSP_SyncRef_SPDIF:
2367                 return HDSP_SYNC_FROM_SPDIF;
2368         case HDSP_SyncRef_WORD:
2369                 return HDSP_SYNC_FROM_WORD;
2370         case HDSP_SyncRef_ADAT_SYNC:
2371                 return HDSP_SYNC_FROM_ADAT_SYNC;
2372         default:
2373                 return HDSP_SYNC_FROM_WORD;
2374         }
2375         return 0;
2376 }
2377 
2378 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2379 {
2380         hdsp->control_register &= ~HDSP_SyncRefMask;
2381         switch (pref) {
2382         case HDSP_SYNC_FROM_ADAT1:
2383                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2384                 break;
2385         case HDSP_SYNC_FROM_ADAT2:
2386                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2387                 break;
2388         case HDSP_SYNC_FROM_ADAT3:
2389                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2390                 break;
2391         case HDSP_SYNC_FROM_SPDIF:
2392                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2393                 break;
2394         case HDSP_SYNC_FROM_WORD:
2395                 hdsp->control_register |= HDSP_SyncRef_WORD;
2396                 break;
2397         case HDSP_SYNC_FROM_ADAT_SYNC:
2398                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2399                 break;
2400         default:
2401                 return -1;
2402         }
2403         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2404         return 0;
2405 }
2406 
2407 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2408 {
2409         static const char * const texts[] = {
2410                 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2411         };
2412         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2413         int num_items;
2414 
2415         switch (hdsp->io_type) {
2416         case Digiface:
2417         case H9652:
2418                 num_items = 6;
2419                 break;
2420         case Multiface:
2421                 num_items = 4;
2422                 break;
2423         case H9632:
2424                 num_items = 3;
2425                 break;
2426         default:
2427                 return -EINVAL;
2428         }
2429 
2430         return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2431 }
2432 
2433 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2434 {
2435         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2436 
2437         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2438         return 0;
2439 }
2440 
2441 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2442 {
2443         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2444         int change, max;
2445         unsigned int val;
2446 
2447         if (!snd_hdsp_use_is_exclusive(hdsp))
2448                 return -EBUSY;
2449 
2450         switch (hdsp->io_type) {
2451         case Digiface:
2452         case H9652:
2453                 max = 6;
2454                 break;
2455         case Multiface:
2456                 max = 4;
2457                 break;
2458         case H9632:
2459                 max = 3;
2460                 break;
2461         default:
2462                 return -EIO;
2463         }
2464 
2465         val = ucontrol->value.enumerated.item[0] % max;
2466         spin_lock_irq(&hdsp->lock);
2467         change = (int)val != hdsp_pref_sync_ref(hdsp);
2468         hdsp_set_pref_sync_ref(hdsp, val);
2469         spin_unlock_irq(&hdsp->lock);
2470         return change;
2471 }
2472 
2473 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2474 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2475   .name = xname, \
2476   .index = xindex, \
2477   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2478   .info = snd_hdsp_info_autosync_ref, \
2479   .get = snd_hdsp_get_autosync_ref, \
2480 }
2481 
2482 static int hdsp_autosync_ref(struct hdsp *hdsp)
2483 {
2484         /* This looks at the autosync selected sync reference */
2485         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2486 
2487         switch (status2 & HDSP_SelSyncRefMask) {
2488         case HDSP_SelSyncRef_WORD:
2489                 return HDSP_AUTOSYNC_FROM_WORD;
2490         case HDSP_SelSyncRef_ADAT_SYNC:
2491                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2492         case HDSP_SelSyncRef_SPDIF:
2493                 return HDSP_AUTOSYNC_FROM_SPDIF;
2494         case HDSP_SelSyncRefMask:
2495                 return HDSP_AUTOSYNC_FROM_NONE;
2496         case HDSP_SelSyncRef_ADAT1:
2497                 return HDSP_AUTOSYNC_FROM_ADAT1;
2498         case HDSP_SelSyncRef_ADAT2:
2499                 return HDSP_AUTOSYNC_FROM_ADAT2;
2500         case HDSP_SelSyncRef_ADAT3:
2501                 return HDSP_AUTOSYNC_FROM_ADAT3;
2502         default:
2503                 return HDSP_AUTOSYNC_FROM_WORD;
2504         }
2505         return 0;
2506 }
2507 
2508 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2509 {
2510         static const char * const texts[] = {
2511                 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2512         };
2513 
2514         return snd_ctl_enum_info(uinfo, 1, 7, texts);
2515 }
2516 
2517 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2518 {
2519         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2520 
2521         ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2522         return 0;
2523 }
2524 
2525 #define HDSP_PRECISE_POINTER(xname, xindex) \
2526 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2527   .name = xname, \
2528   .index = xindex, \
2529   .info = snd_hdsp_info_precise_pointer, \
2530   .get = snd_hdsp_get_precise_pointer, \
2531   .put = snd_hdsp_put_precise_pointer \
2532 }
2533 
2534 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2535 {
2536         if (precise)
2537                 hdsp->precise_ptr = 1;
2538         else
2539                 hdsp->precise_ptr = 0;
2540         return 0;
2541 }
2542 
2543 #define snd_hdsp_info_precise_pointer           snd_ctl_boolean_mono_info
2544 
2545 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2546 {
2547         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2548 
2549         spin_lock_irq(&hdsp->lock);
2550         ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2551         spin_unlock_irq(&hdsp->lock);
2552         return 0;
2553 }
2554 
2555 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2556 {
2557         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2558         int change;
2559         unsigned int val;
2560 
2561         if (!snd_hdsp_use_is_exclusive(hdsp))
2562                 return -EBUSY;
2563         val = ucontrol->value.integer.value[0] & 1;
2564         spin_lock_irq(&hdsp->lock);
2565         change = (int)val != hdsp->precise_ptr;
2566         hdsp_set_precise_pointer(hdsp, val);
2567         spin_unlock_irq(&hdsp->lock);
2568         return change;
2569 }
2570 
2571 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2572 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2573   .name = xname, \
2574   .index = xindex, \
2575   .info = snd_hdsp_info_use_midi_tasklet, \
2576   .get = snd_hdsp_get_use_midi_tasklet, \
2577   .put = snd_hdsp_put_use_midi_tasklet \
2578 }
2579 
2580 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2581 {
2582         if (use_tasklet)
2583                 hdsp->use_midi_tasklet = 1;
2584         else
2585                 hdsp->use_midi_tasklet = 0;
2586         return 0;
2587 }
2588 
2589 #define snd_hdsp_info_use_midi_tasklet          snd_ctl_boolean_mono_info
2590 
2591 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2592 {
2593         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2594 
2595         spin_lock_irq(&hdsp->lock);
2596         ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2597         spin_unlock_irq(&hdsp->lock);
2598         return 0;
2599 }
2600 
2601 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2602 {
2603         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2604         int change;
2605         unsigned int val;
2606 
2607         if (!snd_hdsp_use_is_exclusive(hdsp))
2608                 return -EBUSY;
2609         val = ucontrol->value.integer.value[0] & 1;
2610         spin_lock_irq(&hdsp->lock);
2611         change = (int)val != hdsp->use_midi_tasklet;
2612         hdsp_set_use_midi_tasklet(hdsp, val);
2613         spin_unlock_irq(&hdsp->lock);
2614         return change;
2615 }
2616 
2617 #define HDSP_MIXER(xname, xindex) \
2618 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2619   .name = xname, \
2620   .index = xindex, \
2621   .device = 0, \
2622   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2623                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2624   .info = snd_hdsp_info_mixer, \
2625   .get = snd_hdsp_get_mixer, \
2626   .put = snd_hdsp_put_mixer \
2627 }
2628 
2629 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2630 {
2631         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2632         uinfo->count = 3;
2633         uinfo->value.integer.min = 0;
2634         uinfo->value.integer.max = 65536;
2635         uinfo->value.integer.step = 1;
2636         return 0;
2637 }
2638 
2639 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2640 {
2641         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2642         int source;
2643         int destination;
2644         int addr;
2645 
2646         source = ucontrol->value.integer.value[0];
2647         destination = ucontrol->value.integer.value[1];
2648 
2649         if (source >= hdsp->max_channels)
2650                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2651         else
2652                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2653 
2654         spin_lock_irq(&hdsp->lock);
2655         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2656         spin_unlock_irq(&hdsp->lock);
2657         return 0;
2658 }
2659 
2660 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2661 {
2662         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2663         int change;
2664         int source;
2665         int destination;
2666         int gain;
2667         int addr;
2668 
2669         if (!snd_hdsp_use_is_exclusive(hdsp))
2670                 return -EBUSY;
2671 
2672         source = ucontrol->value.integer.value[0];
2673         destination = ucontrol->value.integer.value[1];
2674 
2675         if (source >= hdsp->max_channels)
2676                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2677         else
2678                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2679 
2680         gain = ucontrol->value.integer.value[2];
2681 
2682         spin_lock_irq(&hdsp->lock);
2683         change = gain != hdsp_read_gain(hdsp, addr);
2684         if (change)
2685                 hdsp_write_gain(hdsp, addr, gain);
2686         spin_unlock_irq(&hdsp->lock);
2687         return change;
2688 }
2689 
2690 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2691 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2692   .name = xname, \
2693   .index = xindex, \
2694   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2695   .info = snd_hdsp_info_sync_check, \
2696   .get = snd_hdsp_get_wc_sync_check \
2697 }
2698 
2699 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2700 {
2701         static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2702 
2703         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2704 }
2705 
2706 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2707 {
2708         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2709         if (status2 & HDSP_wc_lock) {
2710                 if (status2 & HDSP_wc_sync)
2711                         return 2;
2712                 else
2713                          return 1;
2714         } else
2715                 return 0;
2716         return 0;
2717 }
2718 
2719 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2720 {
2721         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2722 
2723         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2724         return 0;
2725 }
2726 
2727 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2728 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2729   .name = xname, \
2730   .index = xindex, \
2731   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2732   .info = snd_hdsp_info_sync_check, \
2733   .get = snd_hdsp_get_spdif_sync_check \
2734 }
2735 
2736 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2737 {
2738         int status = hdsp_read(hdsp, HDSP_statusRegister);
2739         if (status & HDSP_SPDIFErrorFlag)
2740                 return 0;
2741         else {
2742                 if (status & HDSP_SPDIFSync)
2743                         return 2;
2744                 else
2745                         return 1;
2746         }
2747         return 0;
2748 }
2749 
2750 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2751 {
2752         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2753 
2754         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2755         return 0;
2756 }
2757 
2758 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2759 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2760   .name = xname, \
2761   .index = xindex, \
2762   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2763   .info = snd_hdsp_info_sync_check, \
2764   .get = snd_hdsp_get_adatsync_sync_check \
2765 }
2766 
2767 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2768 {
2769         int status = hdsp_read(hdsp, HDSP_statusRegister);
2770         if (status & HDSP_TimecodeLock) {
2771                 if (status & HDSP_TimecodeSync)
2772                         return 2;
2773                 else
2774                         return 1;
2775         } else
2776                 return 0;
2777 }
2778 
2779 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2780 {
2781         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2782 
2783         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2784         return 0;
2785 }
2786 
2787 #define HDSP_ADAT_SYNC_CHECK \
2788 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2789   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2790   .info = snd_hdsp_info_sync_check, \
2791   .get = snd_hdsp_get_adat_sync_check \
2792 }
2793 
2794 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2795 {
2796         int status = hdsp_read(hdsp, HDSP_statusRegister);
2797 
2798         if (status & (HDSP_Lock0>>idx)) {
2799                 if (status & (HDSP_Sync0>>idx))
2800                         return 2;
2801                 else
2802                         return 1;
2803         } else
2804                 return 0;
2805 }
2806 
2807 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2808 {
2809         int offset;
2810         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2811 
2812         offset = ucontrol->id.index - 1;
2813         snd_BUG_ON(offset < 0);
2814 
2815         switch (hdsp->io_type) {
2816         case Digiface:
2817         case H9652:
2818                 if (offset >= 3)
2819                         return -EINVAL;
2820                 break;
2821         case Multiface:
2822         case H9632:
2823                 if (offset >= 1)
2824                         return -EINVAL;
2825                 break;
2826         default:
2827                 return -EIO;
2828         }
2829 
2830         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2831         return 0;
2832 }
2833 
2834 #define HDSP_DDS_OFFSET(xname, xindex) \
2835 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2836   .name = xname, \
2837   .index = xindex, \
2838   .info = snd_hdsp_info_dds_offset, \
2839   .get = snd_hdsp_get_dds_offset, \
2840   .put = snd_hdsp_put_dds_offset \
2841 }
2842 
2843 static int hdsp_dds_offset(struct hdsp *hdsp)
2844 {
2845         u64 n;
2846         unsigned int dds_value = hdsp->dds_value;
2847         int system_sample_rate = hdsp->system_sample_rate;
2848 
2849         if (!dds_value)
2850                 return 0;
2851 
2852         n = DDS_NUMERATOR;
2853         /*
2854          * dds_value = n / rate
2855          * rate = n / dds_value
2856          */
2857         n = div_u64(n, dds_value);
2858         if (system_sample_rate >= 112000)
2859                 n *= 4;
2860         else if (system_sample_rate >= 56000)
2861                 n *= 2;
2862         return ((int)n) - system_sample_rate;
2863 }
2864 
2865 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2866 {
2867         int rate = hdsp->system_sample_rate + offset_hz;
2868         hdsp_set_dds_value(hdsp, rate);
2869         return 0;
2870 }
2871 
2872 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2873 {
2874         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2875         uinfo->count = 1;
2876         uinfo->value.integer.min = -5000;
2877         uinfo->value.integer.max = 5000;
2878         return 0;
2879 }
2880 
2881 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2882 {
2883         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2884 
2885         ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp);
2886         return 0;
2887 }
2888 
2889 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2890 {
2891         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2892         int change;
2893         int val;
2894 
2895         if (!snd_hdsp_use_is_exclusive(hdsp))
2896                 return -EBUSY;
2897         val = ucontrol->value.enumerated.item[0];
2898         spin_lock_irq(&hdsp->lock);
2899         if (val != hdsp_dds_offset(hdsp))
2900                 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2901         else
2902                 change = 0;
2903         spin_unlock_irq(&hdsp->lock);
2904         return change;
2905 }
2906 
2907 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2908 HDSP_DA_GAIN("DA Gain", 0),
2909 HDSP_AD_GAIN("AD Gain", 0),
2910 HDSP_PHONE_GAIN("Phones Gain", 0),
2911 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2912 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2913 };
2914 
2915 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2916 {
2917         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2918         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2919         .info =         snd_hdsp_control_spdif_info,
2920         .get =          snd_hdsp_control_spdif_get,
2921         .put =          snd_hdsp_control_spdif_put,
2922 },
2923 {
2924         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2925         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2926         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2927         .info =         snd_hdsp_control_spdif_stream_info,
2928         .get =          snd_hdsp_control_spdif_stream_get,
2929         .put =          snd_hdsp_control_spdif_stream_put,
2930 },
2931 {
2932         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2933         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2934         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2935         .info =         snd_hdsp_control_spdif_mask_info,
2936         .get =          snd_hdsp_control_spdif_mask_get,
2937         .private_value = IEC958_AES0_NONAUDIO |
2938                          IEC958_AES0_PROFESSIONAL |
2939                          IEC958_AES0_CON_EMPHASIS,
2940 },
2941 {
2942         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2943         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2944         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2945         .info =         snd_hdsp_control_spdif_mask_info,
2946         .get =          snd_hdsp_control_spdif_mask_get,
2947         .private_value = IEC958_AES0_NONAUDIO |
2948                          IEC958_AES0_PROFESSIONAL |
2949                          IEC958_AES0_PRO_EMPHASIS,
2950 },
2951 HDSP_MIXER("Mixer", 0),
2952 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2953 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2954 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2955 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2956 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2957 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2958 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2959 {
2960         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2961         .name = "Sample Clock Source Locking",
2962         .info = snd_hdsp_info_clock_source_lock,
2963         .get = snd_hdsp_get_clock_source_lock,
2964         .put = snd_hdsp_put_clock_source_lock,
2965 },
2966 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2967 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2968 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2969 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2970 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2971 /* 'External Rate' complies with the alsa control naming scheme */
2972 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2973 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2974 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2975 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2976 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2977 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2978 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2979 };
2980 
2981 
2982 static int hdsp_rpm_input12(struct hdsp *hdsp)
2983 {
2984         switch (hdsp->control_register & HDSP_RPM_Inp12) {
2985         case HDSP_RPM_Inp12_Phon_6dB:
2986                 return 0;
2987         case HDSP_RPM_Inp12_Phon_n6dB:
2988                 return 2;
2989         case HDSP_RPM_Inp12_Line_0dB:
2990                 return 3;
2991         case HDSP_RPM_Inp12_Line_n6dB:
2992                 return 4;
2993         }
2994         return 1;
2995 }
2996 
2997 
2998 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2999 {
3000         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3001 
3002         ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
3003         return 0;
3004 }
3005 
3006 
3007 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
3008 {
3009         hdsp->control_register &= ~HDSP_RPM_Inp12;
3010         switch (mode) {
3011         case 0:
3012                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
3013                 break;
3014         case 1:
3015                 break;
3016         case 2:
3017                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3018                 break;
3019         case 3:
3020                 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3021                 break;
3022         case 4:
3023                 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3024                 break;
3025         default:
3026                 return -1;
3027         }
3028 
3029         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3030         return 0;
3031 }
3032 
3033 
3034 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3035 {
3036         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3037         int change;
3038         int val;
3039 
3040         if (!snd_hdsp_use_is_exclusive(hdsp))
3041                 return -EBUSY;
3042         val = ucontrol->value.enumerated.item[0];
3043         if (val < 0)
3044                 val = 0;
3045         if (val > 4)
3046                 val = 4;
3047         spin_lock_irq(&hdsp->lock);
3048         if (val != hdsp_rpm_input12(hdsp))
3049                 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3050         else
3051                 change = 0;
3052         spin_unlock_irq(&hdsp->lock);
3053         return change;
3054 }
3055 
3056 
3057 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3058 {
3059         static const char * const texts[] = {
3060                 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3061         };
3062 
3063         return snd_ctl_enum_info(uinfo, 1, 5, texts);
3064 }
3065 
3066 
3067 static int hdsp_rpm_input34(struct hdsp *hdsp)
3068 {
3069         switch (hdsp->control_register & HDSP_RPM_Inp34) {
3070         case HDSP_RPM_Inp34_Phon_6dB:
3071                 return 0;
3072         case HDSP_RPM_Inp34_Phon_n6dB:
3073                 return 2;
3074         case HDSP_RPM_Inp34_Line_0dB:
3075                 return 3;
3076         case HDSP_RPM_Inp34_Line_n6dB:
3077                 return 4;
3078         }
3079         return 1;
3080 }
3081 
3082 
3083 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3084 {
3085         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3086 
3087         ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3088         return 0;
3089 }
3090 
3091 
3092 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3093 {
3094         hdsp->control_register &= ~HDSP_RPM_Inp34;
3095         switch (mode) {
3096         case 0:
3097                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3098                 break;
3099         case 1:
3100                 break;
3101         case 2:
3102                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3103                 break;
3104         case 3:
3105                 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3106                 break;
3107         case 4:
3108                 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3109                 break;
3110         default:
3111                 return -1;
3112         }
3113 
3114         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3115         return 0;
3116 }
3117 
3118 
3119 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3120 {
3121         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3122         int change;
3123         int val;
3124 
3125         if (!snd_hdsp_use_is_exclusive(hdsp))
3126                 return -EBUSY;
3127         val = ucontrol->value.enumerated.item[0];
3128         if (val < 0)
3129                 val = 0;
3130         if (val > 4)
3131                 val = 4;
3132         spin_lock_irq(&hdsp->lock);
3133         if (val != hdsp_rpm_input34(hdsp))
3134                 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3135         else
3136                 change = 0;
3137         spin_unlock_irq(&hdsp->lock);
3138         return change;
3139 }
3140 
3141 
3142 /* RPM Bypass switch */
3143 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3144 {
3145         return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3146 }
3147 
3148 
3149 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3150 {
3151         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3152 
3153         ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3154         return 0;
3155 }
3156 
3157 
3158 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3159 {
3160         if (on)
3161                 hdsp->control_register |= HDSP_RPM_Bypass;
3162         else
3163                 hdsp->control_register &= ~HDSP_RPM_Bypass;
3164         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3165         return 0;
3166 }
3167 
3168 
3169 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3170 {
3171         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3172         int change;
3173         unsigned int val;
3174 
3175         if (!snd_hdsp_use_is_exclusive(hdsp))
3176                 return -EBUSY;
3177         val = ucontrol->value.integer.value[0] & 1;
3178         spin_lock_irq(&hdsp->lock);
3179         change = (int)val != hdsp_rpm_bypass(hdsp);
3180         hdsp_set_rpm_bypass(hdsp, val);
3181         spin_unlock_irq(&hdsp->lock);
3182         return change;
3183 }
3184 
3185 
3186 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3187 {
3188         static const char * const texts[] = {"On", "Off"};
3189 
3190         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3191 }
3192 
3193 
3194 /* RPM Disconnect switch */
3195 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3196 {
3197         return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3198 }
3199 
3200 
3201 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3202 {
3203         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3204 
3205         ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3206         return 0;
3207 }
3208 
3209 
3210 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3211 {
3212         if (on)
3213                 hdsp->control_register |= HDSP_RPM_Disconnect;
3214         else
3215                 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3216         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3217         return 0;
3218 }
3219 
3220 
3221 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3222 {
3223         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3224         int change;
3225         unsigned int val;
3226 
3227         if (!snd_hdsp_use_is_exclusive(hdsp))
3228                 return -EBUSY;
3229         val = ucontrol->value.integer.value[0] & 1;
3230         spin_lock_irq(&hdsp->lock);
3231         change = (int)val != hdsp_rpm_disconnect(hdsp);
3232         hdsp_set_rpm_disconnect(hdsp, val);
3233         spin_unlock_irq(&hdsp->lock);
3234         return change;
3235 }
3236 
3237 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3238 {
3239         static const char * const texts[] = {"On", "Off"};
3240 
3241         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3242 }
3243 
3244 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3245         {
3246                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3247                 .name = "RPM Bypass",
3248                 .get = snd_hdsp_get_rpm_bypass,
3249                 .put = snd_hdsp_put_rpm_bypass,
3250                 .info = snd_hdsp_info_rpm_bypass
3251         },
3252         {
3253                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3254                 .name = "RPM Disconnect",
3255                 .get = snd_hdsp_get_rpm_disconnect,
3256                 .put = snd_hdsp_put_rpm_disconnect,
3257                 .info = snd_hdsp_info_rpm_disconnect
3258         },
3259         {
3260                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3261                 .name = "Input 1/2",
3262                 .get = snd_hdsp_get_rpm_input12,
3263                 .put = snd_hdsp_put_rpm_input12,
3264                 .info = snd_hdsp_info_rpm_input
3265         },
3266         {
3267                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3268                 .name = "Input 3/4",
3269                 .get = snd_hdsp_get_rpm_input34,
3270                 .put = snd_hdsp_put_rpm_input34,
3271                 .info = snd_hdsp_info_rpm_input
3272         },
3273         HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3274         HDSP_MIXER("Mixer", 0)
3275 };
3276 
3277 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3278         HDSP_TOGGLE_SETTING("Analog Extension Board",
3279                         HDSP_AnalogExtensionBoard);
3280 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3281 
3282 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3283 {
3284         unsigned int idx;
3285         int err;
3286         struct snd_kcontrol *kctl;
3287 
3288         if (hdsp->io_type == RPM) {
3289                 /* RPM Bypass, Disconnect and Input switches */
3290                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3291                         err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3292                         if (err < 0)
3293                                 return err;
3294                 }
3295                 return 0;
3296         }
3297 
3298         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3299                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3300                         return err;
3301                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3302                         hdsp->spdif_ctl = kctl;
3303         }
3304 
3305         /* ADAT SyncCheck status */
3306         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3307         snd_hdsp_adat_sync_check.index = 1;
3308         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3309                 return err;
3310         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3311                 for (idx = 1; idx < 3; ++idx) {
3312                         snd_hdsp_adat_sync_check.index = idx+1;
3313                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3314                                 return err;
3315                 }
3316         }
3317 
3318         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3319         if (hdsp->io_type == H9632) {
3320                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3321                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3322                                 return err;
3323                 }
3324         }
3325 
3326         /* AEB control for H96xx card */
3327         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3328                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3329                                 return err;
3330         }
3331 
3332         return 0;
3333 }
3334 
3335 /*------------------------------------------------------------
3336    /proc interface
3337  ------------------------------------------------------------*/
3338 
3339 static void
3340 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3341 {
3342         struct hdsp *hdsp = entry->private_data;
3343         unsigned int status;
3344         unsigned int status2;
3345         char *pref_sync_ref;
3346         char *autosync_ref;
3347         char *system_clock_mode;
3348         char *clock_source;
3349         int x;
3350 
3351         status = hdsp_read(hdsp, HDSP_statusRegister);
3352         status2 = hdsp_read(hdsp, HDSP_status2Register);
3353 
3354         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3355                     hdsp->card->number + 1);
3356         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3357                     hdsp->capture_buffer, hdsp->playback_buffer);
3358         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3359                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3360         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3361         snd_iprintf(buffer, "Control2 register: 0x%x\n",
3362                     hdsp->control2_register);
3363         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3364         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3365 
3366         if (hdsp_check_for_iobox(hdsp)) {
3367                 snd_iprintf(buffer, "No I/O box connected.\n"
3368                             "Please connect one and upload firmware.\n");
3369                 return;
3370         }
3371 
3372         if (hdsp_check_for_firmware(hdsp, 0)) {
3373                 if (hdsp->state & HDSP_FirmwareCached) {
3374                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3375                                 snd_iprintf(buffer, "Firmware loading from "
3376                                             "cache failed, "
3377                                             "please upload manually.\n");
3378                                 return;
3379                         }
3380                 } else {
3381                         int err = -EINVAL;
3382                         err = hdsp_request_fw_loader(hdsp);
3383                         if (err < 0) {
3384                                 snd_iprintf(buffer,
3385                                             "No firmware loaded nor cached, "
3386                                             "please upload firmware.\n");
3387                                 return;
3388                         }
3389                 }
3390         }
3391 
3392         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3393         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3394         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3395         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3396         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3397         snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3398 
3399         snd_iprintf(buffer, "\n");
3400 
3401         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3402 
3403         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3404         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3405         snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3406         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3407 
3408         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3409 
3410         snd_iprintf(buffer, "\n");
3411 
3412         switch (hdsp_clock_source(hdsp)) {
3413         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3414                 clock_source = "AutoSync";
3415                 break;
3416         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3417                 clock_source = "Internal 32 kHz";
3418                 break;
3419         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3420                 clock_source = "Internal 44.1 kHz";
3421                 break;
3422         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3423                 clock_source = "Internal 48 kHz";
3424                 break;
3425         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3426                 clock_source = "Internal 64 kHz";
3427                 break;
3428         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3429                 clock_source = "Internal 88.2 kHz";
3430                 break;
3431         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3432                 clock_source = "Internal 96 kHz";
3433                 break;
3434         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3435                 clock_source = "Internal 128 kHz";
3436                 break;
3437         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3438                 clock_source = "Internal 176.4 kHz";
3439                 break;
3440                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3441                 clock_source = "Internal 192 kHz";
3442                 break;
3443         default:
3444                 clock_source = "Error";
3445         }
3446         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3447 
3448         if (hdsp_system_clock_mode(hdsp))
3449                 system_clock_mode = "Slave";
3450         else
3451                 system_clock_mode = "Master";
3452 
3453         switch (hdsp_pref_sync_ref (hdsp)) {
3454         case HDSP_SYNC_FROM_WORD:
3455                 pref_sync_ref = "Word Clock";
3456                 break;
3457         case HDSP_SYNC_FROM_ADAT_SYNC:
3458                 pref_sync_ref = "ADAT Sync";
3459                 break;
3460         case HDSP_SYNC_FROM_SPDIF:
3461                 pref_sync_ref = "SPDIF";
3462                 break;
3463         case HDSP_SYNC_FROM_ADAT1:
3464                 pref_sync_ref = "ADAT1";
3465                 break;
3466         case HDSP_SYNC_FROM_ADAT2:
3467                 pref_sync_ref = "ADAT2";
3468                 break;
3469         case HDSP_SYNC_FROM_ADAT3:
3470                 pref_sync_ref = "ADAT3";
3471                 break;
3472         default:
3473                 pref_sync_ref = "Word Clock";
3474                 break;
3475         }
3476         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3477 
3478         switch (hdsp_autosync_ref (hdsp)) {
3479         case HDSP_AUTOSYNC_FROM_WORD:
3480                 autosync_ref = "Word Clock";
3481                 break;
3482         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3483                 autosync_ref = "ADAT Sync";
3484                 break;
3485         case HDSP_AUTOSYNC_FROM_SPDIF:
3486                 autosync_ref = "SPDIF";
3487                 break;
3488         case HDSP_AUTOSYNC_FROM_NONE:
3489                 autosync_ref = "None";
3490                 break;
3491         case HDSP_AUTOSYNC_FROM_ADAT1:
3492                 autosync_ref = "ADAT1";
3493                 break;
3494         case HDSP_AUTOSYNC_FROM_ADAT2:
3495                 autosync_ref = "ADAT2";
3496                 break;
3497         case HDSP_AUTOSYNC_FROM_ADAT3:
3498                 autosync_ref = "ADAT3";
3499                 break;
3500         default:
3501                 autosync_ref = "---";
3502                 break;
3503         }
3504         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3505 
3506         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3507 
3508         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3509 
3510         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3511         snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3512 
3513         snd_iprintf(buffer, "\n");
3514 
3515         if (hdsp->io_type != RPM) {
3516                 switch (hdsp_spdif_in(hdsp)) {
3517                 case HDSP_SPDIFIN_OPTICAL:
3518                         snd_iprintf(buffer, "IEC958 input: Optical\n");
3519                         break;
3520                 case HDSP_SPDIFIN_COAXIAL:
3521                         snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3522                         break;
3523                 case HDSP_SPDIFIN_INTERNAL:
3524                         snd_iprintf(buffer, "IEC958 input: Internal\n");
3525                         break;
3526                 case HDSP_SPDIFIN_AES:
3527                         snd_iprintf(buffer, "IEC958 input: AES\n");
3528                         break;
3529                 default:
3530                         snd_iprintf(buffer, "IEC958 input: ???\n");
3531                         break;
3532                 }
3533         }
3534 
3535         if (RPM == hdsp->io_type) {
3536                 if (hdsp->control_register & HDSP_RPM_Bypass)
3537                         snd_iprintf(buffer, "RPM Bypass: disabled\n");
3538                 else
3539                         snd_iprintf(buffer, "RPM Bypass: enabled\n");
3540                 if (hdsp->control_register & HDSP_RPM_Disconnect)
3541                         snd_iprintf(buffer, "RPM disconnected\n");
3542                 else
3543                         snd_iprintf(buffer, "RPM connected\n");
3544 
3545                 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3546                 case HDSP_RPM_Inp12_Phon_6dB:
3547                         snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3548                         break;
3549                 case HDSP_RPM_Inp12_Phon_0dB:
3550                         snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3551                         break;
3552                 case HDSP_RPM_Inp12_Phon_n6dB:
3553                         snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3554                         break;
3555                 case HDSP_RPM_Inp12_Line_0dB:
3556                         snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3557                         break;
3558                 case HDSP_RPM_Inp12_Line_n6dB:
3559                         snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3560                         break;
3561                 default:
3562                         snd_iprintf(buffer, "Input 1/2: ???\n");
3563                 }
3564 
3565                 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3566                 case HDSP_RPM_Inp34_Phon_6dB:
3567                         snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3568                         break;
3569                 case HDSP_RPM_Inp34_Phon_0dB:
3570                         snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3571                         break;
3572                 case HDSP_RPM_Inp34_Phon_n6dB:
3573                         snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3574                         break;
3575                 case HDSP_RPM_Inp34_Line_0dB:
3576                         snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3577                         break;
3578                 case HDSP_RPM_Inp34_Line_n6dB:
3579                         snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3580                         break;
3581                 default:
3582                         snd_iprintf(buffer, "Input 3/4: ???\n");
3583                 }
3584 
3585         } else {
3586                 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3587                         snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3588                 else
3589                         snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3590 
3591                 if (hdsp->control_register & HDSP_SPDIFProfessional)
3592                         snd_iprintf(buffer, "IEC958 quality: Professional\n");
3593                 else
3594                         snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3595 
3596                 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3597                         snd_iprintf(buffer, "IEC958 emphasis: on\n");
3598                 else
3599                         snd_iprintf(buffer, "IEC958 emphasis: off\n");
3600 
3601                 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3602                         snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3603                 else
3604                         snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3605                 x = hdsp_spdif_sample_rate(hdsp);
3606                 if (x != 0)
3607                         snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3608                 else
3609                         snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3610         }
3611         snd_iprintf(buffer, "\n");
3612 
3613         /* Sync Check */
3614         x = status & HDSP_Sync0;
3615         if (status & HDSP_Lock0)
3616                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3617         else
3618                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3619 
3620         switch (hdsp->io_type) {
3621         case Digiface:
3622         case H9652:
3623                 x = status & HDSP_Sync1;
3624                 if (status & HDSP_Lock1)
3625                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3626                 else
3627                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3628                 x = status & HDSP_Sync2;
3629                 if (status & HDSP_Lock2)
3630                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3631                 else
3632                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3633                 break;
3634         default:
3635                 /* relax */
3636                 break;
3637         }
3638 
3639         x = status & HDSP_SPDIFSync;
3640         if (status & HDSP_SPDIFErrorFlag)
3641                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3642         else
3643                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3644 
3645         x = status2 & HDSP_wc_sync;
3646         if (status2 & HDSP_wc_lock)
3647                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3648         else
3649                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3650 
3651         x = status & HDSP_TimecodeSync;
3652         if (status & HDSP_TimecodeLock)
3653                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3654         else
3655                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3656 
3657         snd_iprintf(buffer, "\n");
3658 
3659         /* Informations about H9632 specific controls */
3660         if (hdsp->io_type == H9632) {
3661                 char *tmp;
3662 
3663                 switch (hdsp_ad_gain(hdsp)) {
3664                 case 0:
3665                         tmp = "-10 dBV";
3666                         break;
3667                 case 1:
3668                         tmp = "+4 dBu";
3669                         break;
3670                 default:
3671                         tmp = "Lo Gain";
3672                         break;
3673                 }
3674                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3675 
3676                 switch (hdsp_da_gain(hdsp)) {
3677                 case 0:
3678                         tmp = "Hi Gain";
3679                         break;
3680                 case 1:
3681                         tmp = "+4 dBu";
3682                         break;
3683                 default:
3684                         tmp = "-10 dBV";
3685                         break;
3686                 }
3687                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3688 
3689                 switch (hdsp_phone_gain(hdsp)) {
3690                 case 0:
3691                         tmp = "0 dB";
3692                         break;
3693                 case 1:
3694                         tmp = "-6 dB";
3695                         break;
3696                 default:
3697                         tmp = "-12 dB";
3698                         break;
3699                 }
3700                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3701 
3702                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3703                         hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3704                         "yes" : "no");
3705 
3706                 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3707                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3708                 else
3709                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3710                 snd_iprintf(buffer, "\n");
3711         }
3712 
3713 }
3714 
3715 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3716 {
3717         struct snd_info_entry *entry;
3718 
3719         if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3720                 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3721 }
3722 
3723 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3724 {
3725         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3726         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3727 }
3728 
3729 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3730 {
3731         unsigned long pb_bus, cb_bus;
3732 
3733         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3734             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3735                 if (hdsp->capture_dma_buf.area)
3736                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3737                 dev_err(hdsp->card->dev,
3738                         "%s: no buffers available\n", hdsp->card_name);
3739                 return -ENOMEM;
3740         }
3741 
3742         /* Align to bus-space 64K boundary */
3743 
3744         cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3745         pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3746 
3747         /* Tell the card where it is */
3748 
3749         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3750         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3751 
3752         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3753         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3754 
3755         return 0;
3756 }
3757 
3758 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3759 {
3760         unsigned int i;
3761 
3762         /* ASSUMPTION: hdsp->lock is either held, or
3763            there is no need to hold it (e.g. during module
3764            initialization).
3765          */
3766 
3767         /* set defaults:
3768 
3769            SPDIF Input via Coax
3770            Master clock mode
3771            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3772                             which implies 2 4096 sample, 32Kbyte periods).
3773            Enable line out.
3774          */
3775 
3776         hdsp->control_register = HDSP_ClockModeMaster |
3777                                  HDSP_SPDIFInputCoaxial |
3778                                  hdsp_encode_latency(7) |
3779                                  HDSP_LineOut;
3780 
3781 
3782         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3783 
3784 #ifdef SNDRV_BIG_ENDIAN
3785         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3786 #else
3787         hdsp->control2_register = 0;
3788 #endif
3789         if (hdsp->io_type == H9652)
3790                 snd_hdsp_9652_enable_mixer (hdsp);
3791         else
3792                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3793 
3794         hdsp_reset_hw_pointer(hdsp);
3795         hdsp_compute_period_size(hdsp);
3796 
3797         /* silence everything */
3798 
3799         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3800                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3801 
3802         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3803                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3804                         return -EIO;
3805         }
3806 
3807         /* H9632 specific defaults */
3808         if (hdsp->io_type == H9632) {
3809                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3810                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3811         }
3812 
3813         /* set a default rate so that the channel map is set up.
3814          */
3815 
3816         hdsp_set_rate(hdsp, 48000, 1);
3817 
3818         return 0;
3819 }
3820 
3821 static void hdsp_midi_tasklet(unsigned long arg)
3822 {
3823         struct hdsp *hdsp = (struct hdsp *)arg;
3824 
3825         if (hdsp->midi[0].pending)
3826                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3827         if (hdsp->midi[1].pending)
3828                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3829 }
3830 
3831 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3832 {
3833         struct hdsp *hdsp = (struct hdsp *) dev_id;
3834         unsigned int status;
3835         int audio;
3836         int midi0;
3837         int midi1;
3838         unsigned int midi0status;
3839         unsigned int midi1status;
3840         int schedule = 0;
3841 
3842         status = hdsp_read(hdsp, HDSP_statusRegister);
3843 
3844         audio = status & HDSP_audioIRQPending;
3845         midi0 = status & HDSP_midi0IRQPending;
3846         midi1 = status & HDSP_midi1IRQPending;
3847 
3848         if (!audio && !midi0 && !midi1)
3849                 return IRQ_NONE;
3850 
3851         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3852 
3853         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3854         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3855 
3856         if (!(hdsp->state & HDSP_InitializationComplete))
3857                 return IRQ_HANDLED;
3858 
3859         if (audio) {
3860                 if (hdsp->capture_substream)
3861                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3862 
3863                 if (hdsp->playback_substream)
3864                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3865         }
3866 
3867         if (midi0 && midi0status) {
3868                 if (hdsp->use_midi_tasklet) {
3869                         /* we disable interrupts for this input until processing is done */
3870                         hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3871                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3872                         hdsp->midi[0].pending = 1;
3873                         schedule = 1;
3874                 } else {
3875                         snd_hdsp_midi_input_read (&hdsp->midi[0]);
3876                 }
3877         }
3878         if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3879                 if (hdsp->use_midi_tasklet) {
3880                         /* we disable interrupts for this input until processing is done */
3881                         hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3882                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3883                         hdsp->midi[1].pending = 1;
3884                         schedule = 1;
3885                 } else {
3886                         snd_hdsp_midi_input_read (&hdsp->midi[1]);
3887                 }
3888         }
3889         if (hdsp->use_midi_tasklet && schedule)
3890                 tasklet_schedule(&hdsp->midi_tasklet);
3891         return IRQ_HANDLED;
3892 }
3893 
3894 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3895 {
3896         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3897         return hdsp_hw_pointer(hdsp);
3898 }
3899 
3900 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3901                                              int stream,
3902                                              int channel)
3903 
3904 {
3905         int mapped_channel;
3906 
3907         if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3908                 return NULL;
3909 
3910         if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3911                 return NULL;
3912 
3913         if (stream == SNDRV_PCM_STREAM_CAPTURE)
3914                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3915         else
3916                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3917 }
3918 
3919 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
3920                                   snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3921 {
3922         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3923         char *channel_buf;
3924 
3925         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3926                 return -EINVAL;
3927 
3928         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3929         if (snd_BUG_ON(!channel_buf))
3930                 return -EIO;
3931         if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3932                 return -EFAULT;
3933         return count;
3934 }
3935 
3936 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
3937                                  snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3938 {
3939         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3940         char *channel_buf;
3941 
3942         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3943                 return -EINVAL;
3944 
3945         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3946         if (snd_BUG_ON(!channel_buf))
3947                 return -EIO;
3948         if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3949                 return -EFAULT;
3950         return count;
3951 }
3952 
3953 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
3954                                   snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3955 {
3956         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3957         char *channel_buf;
3958 
3959         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3960         if (snd_BUG_ON(!channel_buf))
3961                 return -EIO;
3962         memset(channel_buf + pos * 4, 0, count * 4);
3963         return count;
3964 }
3965 
3966 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3967 {
3968         struct snd_pcm_runtime *runtime = substream->runtime;
3969         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3970         struct snd_pcm_substream *other;
3971         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3972                 other = hdsp->capture_substream;
3973         else
3974                 other = hdsp->playback_substream;
3975         if (hdsp->running)
3976                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3977         else
3978                 runtime->status->hw_ptr = 0;
3979         if (other) {
3980                 struct snd_pcm_substream *s;
3981                 struct snd_pcm_runtime *oruntime = other->runtime;
3982                 snd_pcm_group_for_each_entry(s, substream) {
3983                         if (s == other) {
3984                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3985                                 break;
3986                         }
3987                 }
3988         }
3989         return 0;
3990 }
3991 
3992 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3993                                  struct snd_pcm_hw_params *params)
3994 {
3995         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3996         int err;
3997         pid_t this_pid;
3998         pid_t other_pid;
3999 
4000         if (hdsp_check_for_iobox (hdsp))
4001                 return -EIO;
4002 
4003         if (hdsp_check_for_firmware(hdsp, 1))
4004                 return -EIO;
4005 
4006         spin_lock_irq(&hdsp->lock);
4007 
4008         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4009                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4010                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4011                 this_pid = hdsp->playback_pid;
4012                 other_pid = hdsp->capture_pid;
4013         } else {
4014                 this_pid = hdsp->capture_pid;
4015                 other_pid = hdsp->playback_pid;
4016         }
4017 
4018         if ((other_pid > 0) && (this_pid != other_pid)) {
4019 
4020                 /* The other stream is open, and not by the same
4021                    task as this one. Make sure that the parameters
4022                    that matter are the same.
4023                  */
4024 
4025                 if (params_rate(params) != hdsp->system_sample_rate) {
4026                         spin_unlock_irq(&hdsp->lock);
4027                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4028                         return -EBUSY;
4029                 }
4030 
4031                 if (params_period_size(params) != hdsp->period_bytes / 4) {
4032                         spin_unlock_irq(&hdsp->lock);
4033                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4034                         return -EBUSY;
4035                 }
4036 
4037                 /* We're fine. */
4038 
4039                 spin_unlock_irq(&hdsp->lock);
4040                 return 0;
4041 
4042         } else {
4043                 spin_unlock_irq(&hdsp->lock);
4044         }
4045 
4046         /* how to make sure that the rate matches an externally-set one ?
4047          */
4048 
4049         spin_lock_irq(&hdsp->lock);
4050         if (! hdsp->clock_source_locked) {
4051                 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4052                         spin_unlock_irq(&hdsp->lock);
4053                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4054                         return err;
4055                 }
4056         }
4057         spin_unlock_irq(&hdsp->lock);
4058 
4059         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4060                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4061                 return err;
4062         }
4063 
4064         return 0;
4065 }
4066 
4067 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4068                                     struct snd_pcm_channel_info *info)
4069 {
4070         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4071         int mapped_channel;
4072 
4073         if (snd_BUG_ON(info->channel >= hdsp->max_channels))
4074                 return -EINVAL;
4075 
4076         if ((mapped_channel = hdsp->channel_map[info->channel]) < 0)
4077                 return -EINVAL;
4078 
4079         info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
4080         info->first = 0;
4081         info->step = 32;
4082         return 0;
4083 }
4084 
4085 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4086                              unsigned int cmd, void *arg)
4087 {
4088         switch (cmd) {
4089         case SNDRV_PCM_IOCTL1_RESET:
4090                 return snd_hdsp_reset(substream);
4091         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4092                 return snd_hdsp_channel_info(substream, arg);
4093         default:
4094                 break;
4095         }
4096 
4097         return snd_pcm_lib_ioctl(substream, cmd, arg);
4098 }
4099 
4100 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4101 {
4102         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4103         struct snd_pcm_substream *other;
4104         int running;
4105 
4106         if (hdsp_check_for_iobox (hdsp))
4107                 return -EIO;
4108 
4109         if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4110                 return -EIO;
4111 
4112         spin_lock(&hdsp->lock);
4113         running = hdsp->running;
4114         switch (cmd) {
4115         case SNDRV_PCM_TRIGGER_START:
4116                 running |= 1 << substream->stream;
4117                 break;
4118         case SNDRV_PCM_TRIGGER_STOP:
4119                 running &= ~(1 << substream->stream);
4120                 break;
4121         default:
4122                 snd_BUG();
4123                 spin_unlock(&hdsp->lock);
4124                 return -EINVAL;
4125         }
4126         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4127                 other = hdsp->capture_substream;
4128         else
4129                 other = hdsp->playback_substream;
4130 
4131         if (other) {
4132                 struct snd_pcm_substream *s;
4133                 snd_pcm_group_for_each_entry(s, substream) {
4134                         if (s == other) {
4135                                 snd_pcm_trigger_done(s, substream);
4136                                 if (cmd == SNDRV_PCM_TRIGGER_START)
4137                                         running |= 1 << s->stream;
4138                                 else
4139                                         running &= ~(1 << s->stream);
4140                                 goto _ok;
4141                         }
4142                 }
4143                 if (cmd == SNDRV_PCM_TRIGGER_START) {
4144                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4145                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4146                                 hdsp_silence_playback(hdsp);
4147                 } else {
4148                         if (running &&
4149                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4150                                 hdsp_silence_playback(hdsp);
4151                 }
4152         } else {
4153                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4154                                 hdsp_silence_playback(hdsp);
4155         }
4156  _ok:
4157         snd_pcm_trigger_done(substream, substream);
4158         if (!hdsp->running && running)
4159                 hdsp_start_audio(hdsp);
4160         else if (hdsp->running && !running)
4161                 hdsp_stop_audio(hdsp);
4162         hdsp->running = running;
4163         spin_unlock(&hdsp->lock);
4164 
4165         return 0;
4166 }
4167 
4168 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4169 {
4170         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4171         int result = 0;
4172 
4173         if (hdsp_check_for_iobox (hdsp))
4174                 return -EIO;
4175 
4176         if (hdsp_check_for_firmware(hdsp, 1))
4177                 return -EIO;
4178 
4179         spin_lock_irq(&hdsp->lock);
4180         if (!hdsp->running)
4181                 hdsp_reset_hw_pointer(hdsp);
4182         spin_unlock_irq(&hdsp->lock);
4183         return result;
4184 }
4185 
4186 static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4187 {
4188         .info =                 (SNDRV_PCM_INFO_MMAP |
4189                                  SNDRV_PCM_INFO_MMAP_VALID |
4190                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4191                                  SNDRV_PCM_INFO_SYNC_START |
4192                                  SNDRV_PCM_INFO_DOUBLE),
4193 #ifdef SNDRV_BIG_ENDIAN
4194         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4195 #else
4196         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4197 #endif
4198         .rates =                (SNDRV_PCM_RATE_32000 |
4199                                  SNDRV_PCM_RATE_44100 |
4200                                  SNDRV_PCM_RATE_48000 |
4201                                  SNDRV_PCM_RATE_64000 |
4202                                  SNDRV_PCM_RATE_88200 |
4203                                  SNDRV_PCM_RATE_96000),
4204         .rate_min =             32000,
4205         .rate_max =             96000,
4206         .channels_min =         6,
4207         .channels_max =         HDSP_MAX_CHANNELS,
4208         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4209         .period_bytes_min =     (64 * 4) * 10,
4210         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4211         .periods_min =          2,
4212         .periods_max =          2,
4213         .fifo_size =            0
4214 };
4215 
4216 static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4217 {
4218         .info =                 (SNDRV_PCM_INFO_MMAP |
4219                                  SNDRV_PCM_INFO_MMAP_VALID |
4220                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4221                                  SNDRV_PCM_INFO_SYNC_START),
4222 #ifdef SNDRV_BIG_ENDIAN
4223         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4224 #else
4225         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4226 #endif
4227         .rates =                (SNDRV_PCM_RATE_32000 |
4228                                  SNDRV_PCM_RATE_44100 |
4229                                  SNDRV_PCM_RATE_48000 |
4230                                  SNDRV_PCM_RATE_64000 |
4231                                  SNDRV_PCM_RATE_88200 |
4232                                  SNDRV_PCM_RATE_96000),
4233         .rate_min =             32000,
4234         .rate_max =             96000,
4235         .channels_min =         5,
4236         .channels_max =         HDSP_MAX_CHANNELS,
4237         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4238         .period_bytes_min =     (64 * 4) * 10,
4239         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4240         .periods_min =          2,
4241         .periods_max =          2,
4242         .fifo_size =            0
4243 };
4244 
4245 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4246 
4247 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4248         .count = ARRAY_SIZE(hdsp_period_sizes),
4249         .list = hdsp_period_sizes,
4250         .mask = 0
4251 };
4252 
4253 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4254 
4255 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4256         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4257         .list = hdsp_9632_sample_rates,
4258         .mask = 0
4259 };
4260 
4261 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4262                                         struct snd_pcm_hw_rule *rule)
4263 {
4264         struct hdsp *hdsp = rule->private;
4265         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4266         if (hdsp->io_type == H9632) {
4267                 unsigned int list[3];
4268                 list[0] = hdsp->qs_in_channels;
4269                 list[1] = hdsp->ds_in_channels;
4270                 list[2] = hdsp->ss_in_channels;
4271                 return snd_interval_list(c, 3, list, 0);
4272         } else {
4273                 unsigned int list[2];
4274                 list[0] = hdsp->ds_in_channels;
4275                 list[1] = hdsp->ss_in_channels;
4276                 return snd_interval_list(c, 2, list, 0);
4277         }
4278 }
4279 
4280 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4281                                         struct snd_pcm_hw_rule *rule)
4282 {
4283         unsigned int list[3];
4284         struct hdsp *hdsp = rule->private;
4285         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4286         if (hdsp->io_type == H9632) {
4287                 list[0] = hdsp->qs_out_channels;
4288                 list[1] = hdsp->ds_out_channels;
4289                 list[2] = hdsp->ss_out_channels;
4290                 return snd_interval_list(c, 3, list, 0);
4291         } else {
4292                 list[0] = hdsp->ds_out_channels;
4293                 list[1] = hdsp->ss_out_channels;
4294         }
4295         return snd_interval_list(c, 2, list, 0);
4296 }
4297 
4298 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4299                                              struct snd_pcm_hw_rule *rule)
4300 {
4301         struct hdsp *hdsp = rule->private;
4302         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4303         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4304         if (r->min > 96000 && hdsp->io_type == H9632) {
4305                 struct snd_interval t = {
4306                         .min = hdsp->qs_in_channels,
4307                         .max = hdsp->qs_in_channels,
4308                         .integer = 1,
4309                 };
4310                 return snd_interval_refine(c, &t);
4311         } else if (r->min > 48000 && r->max <= 96000) {
4312                 struct snd_interval t = {
4313                         .min = hdsp->ds_in_channels,
4314                         .max = hdsp->ds_in_channels,
4315                         .integer = 1,
4316                 };
4317                 return snd_interval_refine(c, &t);
4318         } else if (r->max < 64000) {
4319                 struct snd_interval t = {
4320                         .min = hdsp->ss_in_channels,
4321                         .max = hdsp->ss_in_channels,
4322                         .integer = 1,
4323                 };
4324                 return snd_interval_refine(c, &t);
4325         }
4326         return 0;
4327 }
4328 
4329 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4330                                              struct snd_pcm_hw_rule *rule)
4331 {
4332         struct hdsp *hdsp = rule->private;
4333         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4334         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4335         if (r->min > 96000 && hdsp->io_type == H9632) {
4336                 struct snd_interval t = {
4337                         .min = hdsp->qs_out_channels,
4338                         .max = hdsp->qs_out_channels,
4339                         .integer = 1,
4340                 };
4341                 return snd_interval_refine(c, &t);
4342         } else if (r->min > 48000 && r->max <= 96000) {
4343                 struct snd_interval t = {
4344                         .min = hdsp->ds_out_channels,
4345                         .max = hdsp->ds_out_channels,
4346                         .integer = 1,
4347                 };
4348                 return snd_interval_refine(c, &t);
4349         } else if (r->max < 64000) {
4350                 struct snd_interval t = {
4351                         .min = hdsp->ss_out_channels,
4352                         .max = hdsp->ss_out_channels,
4353                         .integer = 1,
4354                 };
4355                 return snd_interval_refine(c, &t);
4356         }
4357         return 0;
4358 }
4359 
4360 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4361                                              struct snd_pcm_hw_rule *rule)
4362 {
4363         struct hdsp *hdsp = rule->private;
4364         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4365         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4366         if (c->min >= hdsp->ss_out_channels) {
4367                 struct snd_interval t = {
4368                         .min = 32000,
4369                         .max = 48000,
4370                         .integer = 1,
4371                 };
4372                 return snd_interval_refine(r, &t);
4373         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4374                 struct snd_interval t = {
4375                         .min = 128000,
4376                         .max = 192000,
4377                         .integer = 1,
4378                 };
4379                 return snd_interval_refine(r, &t);
4380         } else if (c->max <= hdsp->ds_out_channels) {
4381                 struct snd_interval t = {
4382                         .min = 64000,
4383                         .max = 96000,
4384                         .integer = 1,
4385                 };
4386                 return snd_interval_refine(r, &t);
4387         }
4388         return 0;
4389 }
4390 
4391 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4392                                              struct snd_pcm_hw_rule *rule)
4393 {
4394         struct hdsp *hdsp = rule->private;
4395         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4396         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4397         if (c->min >= hdsp->ss_in_channels) {
4398                 struct snd_interval t = {
4399                         .min = 32000,
4400                         .max = 48000,
4401                         .integer = 1,
4402                 };
4403                 return snd_interval_refine(r, &t);
4404         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4405                 struct snd_interval t = {
4406                         .min = 128000,
4407                         .max = 192000,
4408                         .integer = 1,
4409                 };
4410                 return snd_interval_refine(r, &t);
4411         } else if (c->max <= hdsp->ds_in_channels) {
4412                 struct snd_interval t = {
4413                         .min = 64000,
4414                         .max = 96000,
4415                         .integer = 1,
4416                 };
4417                 return snd_interval_refine(r, &t);
4418         }
4419         return 0;
4420 }
4421 
4422 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4423 {
4424         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4425         struct snd_pcm_runtime *runtime = substream->runtime;
4426 
4427         if (hdsp_check_for_iobox (hdsp))
4428                 return -EIO;
4429 
4430         if (hdsp_check_for_firmware(hdsp, 1))
4431                 return -EIO;
4432 
4433         spin_lock_irq(&hdsp->lock);
4434 
4435         snd_pcm_set_sync(substream);
4436 
4437         runtime->hw = snd_hdsp_playback_subinfo;
4438         runtime->dma_area = hdsp->playback_buffer;
4439         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4440 
4441         hdsp->playback_pid = current->pid;
4442         hdsp->playback_substream = substream;
4443 
4444         spin_unlock_irq(&hdsp->lock);
4445 
4446         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4447         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4448         if (hdsp->clock_source_locked) {
4449                 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4450         } else if (hdsp->io_type == H9632) {
4451                 runtime->hw.rate_max = 192000;
4452                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4453                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4454         }
4455         if (hdsp->io_type == H9632) {
4456                 runtime->hw.channels_min = hdsp->qs_out_channels;
4457                 runtime->hw.channels_max = hdsp->ss_out_channels;
4458         }
4459 
4460         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4461                              snd_hdsp_hw_rule_out_channels, hdsp,
4462                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4463         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4464                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4465                              SNDRV_PCM_HW_PARAM_RATE, -1);
4466         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4467                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4468                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4469 
4470         if (RPM != hdsp->io_type) {
4471                 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4472                 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4473                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4474                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4475         }
4476         return 0;
4477 }
4478 
4479 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4480 {
4481         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4482 
4483         spin_lock_irq(&hdsp->lock);
4484 
4485         hdsp->playback_pid = -1;
4486         hdsp->playback_substream = NULL;
4487 
4488         spin_unlock_irq(&hdsp->lock);
4489 
4490         if (RPM != hdsp->io_type) {
4491                 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4492                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4493                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4494         }
4495         return 0;
4496 }
4497 
4498 
4499 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4500 {
4501         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4502         struct snd_pcm_runtime *runtime = substream->runtime;
4503 
4504         if (hdsp_check_for_iobox (hdsp))
4505                 return -EIO;
4506 
4507         if (hdsp_check_for_firmware(hdsp, 1))
4508                 return -EIO;
4509 
4510         spin_lock_irq(&hdsp->lock);
4511 
4512         snd_pcm_set_sync(substream);
4513 
4514         runtime->hw = snd_hdsp_capture_subinfo;
4515         runtime->dma_area = hdsp->capture_buffer;
4516         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4517 
4518         hdsp->capture_pid = current->pid;
4519         hdsp->capture_substream = substream;
4520 
4521         spin_unlock_irq(&hdsp->lock);
4522 
4523         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4524         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4525         if (hdsp->io_type == H9632) {
4526                 runtime->hw.channels_min = hdsp->qs_in_channels;
4527                 runtime->hw.channels_max = hdsp->ss_in_channels;
4528                 runtime->hw.rate_max = 192000;
4529                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4530                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4531         }
4532         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4533                              snd_hdsp_hw_rule_in_channels, hdsp,
4534                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4535         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4536                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4537                              SNDRV_PCM_HW_PARAM_RATE, -1);
4538         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4539                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4540                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4541         return 0;
4542 }
4543 
4544 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4545 {
4546         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4547 
4548         spin_lock_irq(&hdsp->lock);
4549 
4550         hdsp->capture_pid = -1;
4551         hdsp->capture_substream = NULL;
4552 
4553         spin_unlock_irq(&hdsp->lock);
4554         return 0;
4555 }
4556 
4557 /* helper functions for copying meter values */
4558 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4559 {
4560         u32 val = readl(src);
4561         return copy_to_user(dest, &val, 4);
4562 }
4563 
4564 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4565 {
4566         u32 rms_low, rms_high;
4567         u64 rms;
4568         rms_low = readl(src_low);
4569         rms_high = readl(src_high);
4570         rms = ((u64)rms_high << 32) | rms_low;
4571         return copy_to_user(dest, &rms, 8);
4572 }
4573 
4574 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4575 {
4576         u32 rms_low, rms_high;
4577         u64 rms;
4578         rms_low = readl(src_low) & 0xffffff00;
4579         rms_high = readl(src_high) & 0xffffff00;
4580         rms = ((u64)rms_high << 32) | rms_low;
4581         return copy_to_user(dest, &rms, 8);
4582 }
4583 
4584 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4585 {
4586         int doublespeed = 0;
4587         int i, j, channels, ofs;
4588 
4589         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4590                 doublespeed = 1;
4591         channels = doublespeed ? 14 : 26;
4592         for (i = 0, j = 0; i < 26; ++i) {
4593                 if (doublespeed && (i & 4))
4594                         continue;
4595                 ofs = HDSP_9652_peakBase - j * 4;
4596                 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4597                         return -EFAULT;
4598                 ofs -= channels * 4;
4599                 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4600                         return -EFAULT;
4601                 ofs -= channels * 4;
4602                 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4603                         return -EFAULT;
4604                 ofs = HDSP_9652_rmsBase + j * 8;
4605                 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4606                                 hdsp->iobase + ofs + 4))
4607                         return -EFAULT;
4608                 ofs += channels * 8;
4609                 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4610                                 hdsp->iobase + ofs + 4))
4611                         return -EFAULT;
4612                 ofs += channels * 8;
4613                 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4614                                 hdsp->iobase + ofs + 4))
4615                         return -EFAULT;
4616                 j++;
4617         }
4618         return 0;
4619 }
4620 
4621 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4622 {
4623         int i, j;
4624         struct hdsp_9632_meters __iomem *m;
4625         int doublespeed = 0;
4626 
4627         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4628                 doublespeed = 1;
4629         m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4630         for (i = 0, j = 0; i < 16; ++i, ++j) {
4631                 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4632                         return -EFAULT;
4633                 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4634                         return -EFAULT;
4635                 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4636                         return -EFAULT;
4637                 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4638                                 &m->input_rms_high[j]))
4639                         return -EFAULT;
4640                 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4641                                 &m->playback_rms_high[j]))
4642                         return -EFAULT;
4643                 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4644                                 &m->output_rms_high[j]))
4645                         return -EFAULT;
4646                 if (doublespeed && i == 3) i += 4;
4647         }
4648         return 0;
4649 }
4650 
4651 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4652 {
4653         int i;
4654 
4655         for (i = 0; i < 26; i++) {
4656                 if (copy_u32_le(&peak_rms->playback_peaks[i],
4657                                 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4658                         return -EFAULT;
4659                 if (copy_u32_le(&peak_rms->input_peaks[i],
4660                                 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4661                         return -EFAULT;
4662         }
4663         for (i = 0; i < 28; i++) {
4664                 if (copy_u32_le(&peak_rms->output_peaks[i],
4665                                 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4666                         return -EFAULT;
4667         }
4668         for (i = 0; i < 26; ++i) {
4669                 if (copy_u64_le(&peak_rms->playback_rms[i],
4670                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4671                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4672                         return -EFAULT;
4673                 if (copy_u64_le(&peak_rms->input_rms[i],
4674                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4675                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4676                         return -EFAULT;
4677         }
4678         return 0;
4679 }
4680 
4681 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4682 {
4683         struct hdsp *hdsp = hw->private_data;
4684         void __user *argp = (void __user *)arg;
4685         int err;
4686 
4687         switch (cmd) {
4688         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4689                 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4690 
4691                 err = hdsp_check_for_iobox(hdsp);
4692                 if (err < 0)
4693                         return err;
4694 
4695                 err = hdsp_check_for_firmware(hdsp, 1);
4696                 if (err < 0)
4697                         return err;
4698 
4699                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4700                         dev_err(hdsp->card->dev,
4701                                 "firmware needs to be uploaded to the card.\n");
4702                         return -EINVAL;
4703                 }
4704 
4705                 switch (hdsp->io_type) {
4706                 case H9652:
4707                         return hdsp_9652_get_peak(hdsp, peak_rms);
4708                 case H9632:
4709                         return hdsp_9632_get_peak(hdsp, peak_rms);
4710                 default:
4711                         return hdsp_get_peak(hdsp, peak_rms);
4712                 }
4713         }
4714         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4715                 struct hdsp_config_info info;
4716                 unsigned long flags;
4717                 int i;
4718 
4719                 err = hdsp_check_for_iobox(hdsp);
4720                 if (err < 0)
4721                         return err;
4722 
4723                 err = hdsp_check_for_firmware(hdsp, 1);
4724                 if (err < 0)
4725                         return err;
4726 
4727                 memset(&info, 0, sizeof(info));
4728                 spin_lock_irqsave(&hdsp->lock, flags);
4729                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4730                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4731                 if (hdsp->io_type != H9632)
4732                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4733                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4734                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4735                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4736                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4737                 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4738                                 HDSP_SPDIFOpticalOut);
4739                 info.spdif_professional = (unsigned char)
4740                         hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4741                 info.spdif_emphasis = (unsigned char)
4742                         hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4743                 info.spdif_nonaudio = (unsigned char)
4744                         hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4745                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4746                 info.system_sample_rate = hdsp->system_sample_rate;
4747                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4748                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4749                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4750                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4751                 info.line_out = (unsigned char)
4752                         hdsp_toggle_setting(hdsp, HDSP_LineOut);
4753                 if (hdsp->io_type == H9632) {
4754                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4755                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4756                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4757                         info.xlr_breakout_cable =
4758                                 (unsigned char)hdsp_toggle_setting(hdsp,
4759                                         HDSP_XLRBreakoutCable);
4760 
4761                 } else if (hdsp->io_type == RPM) {
4762                         info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4763                         info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4764                 }
4765                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4766                         info.analog_extension_board =
4767                                 (unsigned char)hdsp_toggle_setting(hdsp,
4768                                             HDSP_AnalogExtensionBoard);
4769                 spin_unlock_irqrestore(&hdsp->lock, flags);
4770                 if (copy_to_user(argp, &info, sizeof(info)))
4771                         return -EFAULT;
4772                 break;
4773         }
4774         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4775                 struct hdsp_9632_aeb h9632_aeb;
4776 
4777                 if (hdsp->io_type != H9632) return -EINVAL;
4778                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4779                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4780                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4781                         return -EFAULT;
4782                 break;
4783         }
4784         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4785                 struct hdsp_version hdsp_version;
4786                 int err;
4787 
4788                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4789                 if (hdsp->io_type == Undefined) {
4790                         if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4791                                 return err;
4792                 }
4793                 memset(&hdsp_version, 0, sizeof(hdsp_version));
4794                 hdsp_version.io_type = hdsp->io_type;
4795                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4796                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4797                         return -EFAULT;
4798                 break;
4799         }
4800         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4801                 struct hdsp_firmware __user *firmware;
4802                 u32 __user *firmware_data;
4803                 int err;
4804 
4805                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4806                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4807                 if (hdsp->io_type == Undefined) return -EINVAL;
4808 
4809                 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4810                         return -EBUSY;
4811 
4812                 dev_info(hdsp->card->dev,
4813                          "initializing firmware upload\n");
4814                 firmware = (struct hdsp_firmware __user *)argp;
4815 
4816                 if (get_user(firmware_data, &firmware->firmware_data))
4817                         return -EFAULT;
4818 
4819                 if (hdsp_check_for_iobox (hdsp))
4820                         return -EIO;
4821 
4822                 if (!hdsp->fw_uploaded) {
4823                         hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4824                         if (!hdsp->fw_uploaded)
4825                                 return -ENOMEM;
4826                 }
4827 
4828                 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4829                                    HDSP_FIRMWARE_SIZE)) {
4830                         vfree(hdsp->fw_uploaded);
4831                         hdsp->fw_uploaded = NULL;
4832                         return -EFAULT;
4833                 }
4834 
4835                 hdsp->state |= HDSP_FirmwareCached;
4836 
4837                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4838                         return err;
4839 
4840                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4841                         if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4842                                 return err;
4843 
4844                         snd_hdsp_initialize_channels(hdsp);
4845                         snd_hdsp_initialize_midi_flush(hdsp);
4846 
4847                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4848                                 dev_err(hdsp->card->dev,
4849                                         "error creating alsa devices\n");
4850                                 return err;
4851                         }
4852                 }
4853                 break;
4854         }
4855         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4856                 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4857                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4858                         return -EFAULT;
4859                 break;
4860         }
4861         default:
4862                 return -EINVAL;
4863         }
4864         return 0;
4865 }
4866 
4867 static struct snd_pcm_ops snd_hdsp_playback_ops = {
4868         .open =         snd_hdsp_playback_open,
4869         .close =        snd_hdsp_playback_release,
4870         .ioctl =        snd_hdsp_ioctl,
4871         .hw_params =    snd_hdsp_hw_params,
4872         .prepare =      snd_hdsp_prepare,
4873         .trigger =      snd_hdsp_trigger,
4874         .pointer =      snd_hdsp_hw_pointer,
4875         .copy =         snd_hdsp_playback_copy,
4876         .silence =      snd_hdsp_hw_silence,
4877 };
4878 
4879 static struct snd_pcm_ops snd_hdsp_capture_ops = {
4880         .open =         snd_hdsp_capture_open,
4881         .close =        snd_hdsp_capture_release,
4882         .ioctl =        snd_hdsp_ioctl,
4883         .hw_params =    snd_hdsp_hw_params,
4884         .prepare =      snd_hdsp_prepare,
4885         .trigger =      snd_hdsp_trigger,
4886         .pointer =      snd_hdsp_hw_pointer,
4887         .copy =         snd_hdsp_capture_copy,
4888 };
4889 
4890 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4891 {
4892         struct snd_hwdep *hw;
4893         int err;
4894 
4895         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4896                 return err;
4897 
4898         hdsp->hwdep = hw;
4899         hw->private_data = hdsp;
4900         strcpy(hw->name, "HDSP hwdep interface");
4901 
4902         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4903         hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4904 
4905         return 0;
4906 }
4907 
4908 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4909 {
4910         struct snd_pcm *pcm;
4911         int err;
4912 
4913         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4914                 return err;
4915 
4916         hdsp->pcm = pcm;
4917         pcm->private_data = hdsp;
4918         strcpy(pcm->name, hdsp->card_name);
4919 
4920         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4921         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4922 
4923         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4924 
4925         return 0;
4926 }
4927 
4928 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4929 {
4930         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4931         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4932 }
4933 
4934 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4935 {
4936         int i;
4937 
4938         if (hdsp_fifo_wait (hdsp, 0, 100)) {
4939                 dev_err(hdsp->card->dev,
4940                         "enable_io fifo_wait failed\n");
4941                 return -EIO;
4942         }
4943 
4944         for (i = 0; i < hdsp->max_channels; ++i) {
4945                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4946                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4947         }
4948 
4949         return 0;
4950 }
4951 
4952 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4953 {
4954         int status, aebi_channels, aebo_channels;
4955 
4956         switch (hdsp->io_type) {
4957         case Digiface:
4958                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4959                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4960                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4961                 break;
4962 
4963         case H9652:
4964                 hdsp->card_name = "RME Hammerfall HDSP 9652";
4965                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4966                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4967                 break;
4968 
4969         case H9632:
4970                 status = hdsp_read(hdsp, HDSP_statusRegister);
4971                 /* HDSP_AEBx bits are low when AEB are connected */
4972                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4973                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4974                 hdsp->card_name = "RME Hammerfall HDSP 9632";
4975                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4976                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4977                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4978                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4979                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4980                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4981                 break;
4982 
4983         case Multiface:
4984                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4985                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4986                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4987                 break;
4988 
4989         case RPM:
4990                 hdsp->card_name = "RME Hammerfall DSP + RPM";
4991                 hdsp->ss_in_channels = RPM_CHANNELS-1;
4992                 hdsp->ss_out_channels = RPM_CHANNELS;
4993                 hdsp->ds_in_channels = RPM_CHANNELS-1;
4994                 hdsp->ds_out_channels = RPM_CHANNELS;
4995                 break;
4996 
4997         default:
4998                 /* should never get here */
4999                 break;
5000         }
5001 }
5002 
5003 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5004 {
5005         snd_hdsp_flush_midi_input (hdsp, 0);
5006         snd_hdsp_flush_midi_input (hdsp, 1);
5007 }
5008 
5009 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5010 {
5011         int err;
5012 
5013         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5014                 dev_err(card->dev,
5015                         "Error creating pcm interface\n");
5016                 return err;
5017         }
5018 
5019 
5020         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5021                 dev_err(card->dev,
5022                         "Error creating first midi interface\n");
5023                 return err;
5024         }
5025 
5026         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5027                 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5028                         dev_err(card->dev,
5029                                 "Error creating second midi interface\n");
5030                         return err;
5031                 }
5032         }
5033 
5034         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5035                 dev_err(card->dev,
5036                         "Error creating ctl interface\n");
5037                 return err;
5038         }
5039 
5040         snd_hdsp_proc_init(hdsp);
5041 
5042         hdsp->system_sample_rate = -1;
5043         hdsp->playback_pid = -1;
5044         hdsp->capture_pid = -1;
5045         hdsp->capture_substream = NULL;
5046         hdsp->playback_substream = NULL;
5047 
5048         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5049                 dev_err(card->dev,
5050                         "Error setting default values\n");
5051                 return err;
5052         }
5053 
5054         if (!(hdsp->state & HDSP_InitializationComplete)) {
5055                 strcpy(card->shortname, "Hammerfall DSP");
5056                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5057                         hdsp->port, hdsp->irq);
5058 
5059                 if ((err = snd_card_register(card)) < 0) {
5060                         dev_err(card->dev,
5061                                 "error registering card\n");
5062                         return err;
5063                 }
5064                 hdsp->state |= HDSP_InitializationComplete;
5065         }
5066 
5067         return 0;
5068 }
5069 
5070 /* load firmware via hotplug fw loader */
5071 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5072 {
5073         const char *fwfile;
5074         const struct firmware *fw;
5075         int err;
5076 
5077         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5078                 return 0;
5079         if (hdsp->io_type == Undefined) {
5080                 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5081                         return err;
5082                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5083                         return 0;
5084         }
5085 
5086         /* caution: max length of firmware filename is 30! */
5087         switch (hdsp->io_type) {
5088         case RPM:
5089                 fwfile = "rpm_firmware.bin";
5090                 break;
5091         case Multiface:
5092                 if (hdsp->firmware_rev == 0xa)
5093                         fwfile = "multiface_firmware.bin";
5094                 else
5095                         fwfile = "multiface_firmware_rev11.bin";
5096                 break;
5097         case Digiface:
5098                 if (hdsp->firmware_rev == 0xa)
5099                         fwfile = "digiface_firmware.bin";
5100                 else
5101                         fwfile = "digiface_firmware_rev11.bin";
5102                 break;
5103         default:
5104                 dev_err(hdsp->card->dev,
5105                         "invalid io_type %d\n", hdsp->io_type);
5106                 return -EINVAL;
5107         }
5108 
5109         if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5110                 dev_err(hdsp->card->dev,
5111                         "cannot load firmware %s\n", fwfile);
5112                 return -ENOENT;
5113         }
5114         if (fw->size < HDSP_FIRMWARE_SIZE) {
5115                 dev_err(hdsp->card->dev,
5116                         "too short firmware size %d (expected %d)\n",
5117                            (int)fw->size, HDSP_FIRMWARE_SIZE);
5118                 return -EINVAL;
5119         }
5120 
5121         hdsp->firmware = fw;
5122 
5123         hdsp->state |= HDSP_FirmwareCached;
5124 
5125         if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5126                 return err;
5127 
5128         if (!(hdsp->state & HDSP_InitializationComplete)) {
5129                 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5130                         return err;
5131 
5132                 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5133                         dev_err(hdsp->card->dev,
5134                                 "error creating hwdep device\n");
5135                         return err;
5136                 }
5137                 snd_hdsp_initialize_channels(hdsp);
5138                 snd_hdsp_initialize_midi_flush(hdsp);
5139                 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5140                         dev_err(hdsp->card->dev,
5141                                 "error creating alsa devices\n");
5142                         return err;
5143                 }
5144         }
5145         return 0;
5146 }
5147 
5148 static int snd_hdsp_create(struct snd_card *card,
5149                            struct hdsp *hdsp)
5150 {
5151         struct pci_dev *pci = hdsp->pci;
5152         int err;
5153         int is_9652 = 0;
5154         int is_9632 = 0;
5155 
5156         hdsp->irq = -1;
5157         hdsp->state = 0;
5158         hdsp->midi[0].rmidi = NULL;
5159         hdsp->midi[1].rmidi = NULL;
5160         hdsp->midi[0].input = NULL;
5161         hdsp->midi[1].input = NULL;
5162         hdsp->midi[0].output = NULL;
5163         hdsp->midi[1].output = NULL;
5164         hdsp->midi[0].pending = 0;
5165         hdsp->midi[1].pending = 0;
5166         spin_lock_init(&hdsp->midi[0].lock);
5167         spin_lock_init(&hdsp->midi[1].lock);
5168         hdsp->iobase = NULL;
5169         hdsp->control_register = 0;
5170         hdsp->control2_register = 0;
5171         hdsp->io_type = Undefined;
5172         hdsp->max_channels = 26;
5173 
5174         hdsp->card = card;
5175 
5176         spin_lock_init(&hdsp->lock);
5177 
5178         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5179 
5180         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5181         hdsp->firmware_rev &= 0xff;
5182 
5183         /* From Martin Bjoernsen :
5184             "It is important that the card's latency timer register in
5185             the PCI configuration space is set to a value much larger
5186             than 0 by the computer's BIOS or the driver.
5187             The windows driver always sets this 8 bit register [...]
5188             to its maximum 255 to avoid problems with some computers."
5189         */
5190         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5191 
5192         strcpy(card->driver, "H-DSP");
5193         strcpy(card->mixername, "Xilinx FPGA");
5194 
5195         if (hdsp->firmware_rev < 0xa)
5196                 return -ENODEV;
5197         else if (hdsp->firmware_rev < 0x64)
5198                 hdsp->card_name = "RME Hammerfall DSP";
5199         else if (hdsp->firmware_rev < 0x96) {
5200                 hdsp->card_name = "RME HDSP 9652";
5201                 is_9652 = 1;
5202         } else {
5203                 hdsp->card_name = "RME HDSP 9632";
5204                 hdsp->max_channels = 16;
5205                 is_9632 = 1;
5206         }
5207 
5208         if ((err = pci_enable_device(pci)) < 0)
5209                 return err;
5210 
5211         pci_set_master(hdsp->pci);
5212 
5213         if ((err = pci_request_regions(pci, "hdsp")) < 0)
5214                 return err;
5215         hdsp->port = pci_resource_start(pci, 0);
5216         if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5217                 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5218                         hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5219                 return -EBUSY;
5220         }
5221 
5222         if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5223                         KBUILD_MODNAME, hdsp)) {
5224                 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5225                 return -EBUSY;
5226         }
5227 
5228         hdsp->irq = pci->irq;
5229         hdsp->precise_ptr = 0;
5230         hdsp->use_midi_tasklet = 1;
5231         hdsp->dds_value = 0;
5232 
5233         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5234                 return err;
5235 
5236         if (!is_9652 && !is_9632) {
5237                 /* we wait a maximum of 10 seconds to let freshly
5238                  * inserted cardbus cards do their hardware init */
5239                 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5240 
5241                 if (err < 0)
5242                         return err;
5243 
5244                 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5245                         if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5246                                 /* we don't fail as this can happen
5247                                    if userspace is not ready for
5248                                    firmware upload
5249                                 */
5250                                 dev_err(hdsp->card->dev,
5251                                         "couldn't get firmware from userspace. try using hdsploader\n");
5252                         else
5253                                 /* init is complete, we return */
5254                                 return 0;
5255                         /* we defer initialization */
5256                         dev_info(hdsp->card->dev,
5257                                  "card initialization pending : waiting for firmware\n");
5258                         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5259                                 return err;
5260                         return 0;
5261                 } else {
5262                         dev_info(hdsp->card->dev,
5263                                  "Firmware already present, initializing card.\n");
5264                         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5265                                 hdsp->io_type = RPM;
5266                         else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5267                                 hdsp->io_type = Multiface;
5268                         else
5269                                 hdsp->io_type = Digiface;
5270                 }
5271         }
5272 
5273         if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5274                 return err;
5275 
5276         if (is_9652)
5277                 hdsp->io_type = H9652;
5278 
5279         if (is_9632)
5280                 hdsp->io_type = H9632;
5281 
5282         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5283                 return err;
5284 
5285         snd_hdsp_initialize_channels(hdsp);
5286         snd_hdsp_initialize_midi_flush(hdsp);
5287 
5288         hdsp->state |= HDSP_FirmwareLoaded;
5289 
5290         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5291                 return err;
5292 
5293         return 0;
5294 }
5295 
5296 static int snd_hdsp_free(struct hdsp *hdsp)
5297 {
5298         if (hdsp->port) {
5299                 /* stop the audio, and cancel all interrupts */
5300                 tasklet_kill(&hdsp->midi_tasklet);
5301                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5302                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5303         }
5304 
5305         if (hdsp->irq >= 0)
5306                 free_irq(hdsp->irq, (void *)hdsp);
5307 
5308         snd_hdsp_free_buffers(hdsp);
5309 
5310         release_firmware(hdsp->firmware);
5311         vfree(hdsp->fw_uploaded);
5312 
5313         if (hdsp->iobase)
5314                 iounmap(hdsp->iobase);
5315 
5316         if (hdsp->port)
5317                 pci_release_regions(hdsp->pci);
5318 
5319         pci_disable_device(hdsp->pci);
5320         return 0;
5321 }
5322 
5323 static void snd_hdsp_card_free(struct snd_card *card)
5324 {
5325         struct hdsp *hdsp = card->private_data;
5326 
5327         if (hdsp)
5328                 snd_hdsp_free(hdsp);
5329 }
5330 
5331 static int snd_hdsp_probe(struct pci_dev *pci,
5332                           const struct pci_device_id *pci_id)
5333 {
5334         static int dev;
5335         struct hdsp *hdsp;
5336         struct snd_card *card;
5337         int err;
5338 
5339         if (dev >= SNDRV_CARDS)
5340                 return -ENODEV;
5341         if (!enable[dev]) {
5342                 dev++;
5343                 return -ENOENT;
5344         }
5345 
5346         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5347                            sizeof(struct hdsp), &card);
5348         if (err < 0)
5349                 return err;
5350 
5351         hdsp = card->private_data;
5352         card->private_free = snd_hdsp_card_free;
5353         hdsp->dev = dev;
5354         hdsp->pci = pci;
5355 
5356         if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5357                 snd_card_free(card);
5358                 return err;
5359         }
5360 
5361         strcpy(card->shortname, "Hammerfall DSP");
5362         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5363                 hdsp->port, hdsp->irq);
5364 
5365         if ((err = snd_card_register(card)) < 0) {
5366                 snd_card_free(card);
5367                 return err;
5368         }
5369         pci_set_drvdata(pci, card);
5370         dev++;
5371         return 0;
5372 }
5373 
5374 static void snd_hdsp_remove(struct pci_dev *pci)
5375 {
5376         snd_card_free(pci_get_drvdata(pci));
5377 }
5378 
5379 static struct pci_driver hdsp_driver = {
5380         .name =     KBUILD_MODNAME,
5381         .id_table = snd_hdsp_ids,
5382         .probe =    snd_hdsp_probe,
5383         .remove = snd_hdsp_remove,
5384 };
5385 
5386 module_pci_driver(hdsp_driver);
5387 

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