Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/sound/pci/hda/patch_ca0132.c

  1 /*
  2  * HD audio interface patch for Creative CA0132 chip
  3  *
  4  * Copyright (c) 2011, Creative Technology Ltd.
  5  *
  6  * Based on patch_ca0110.c
  7  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
  8  *
  9  *  This driver is free software; you can redistribute it and/or modify
 10  *  it under the terms of the GNU General Public License as published by
 11  *  the Free Software Foundation; either version 2 of the License, or
 12  *  (at your option) any later version.
 13  *
 14  *  This driver is distributed in the hope that it will be useful,
 15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  *  GNU General Public License for more details.
 18  *
 19  *  You should have received a copy of the GNU General Public License
 20  *  along with this program; if not, write to the Free Software
 21  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 22  */
 23 
 24 #include <linux/init.h>
 25 #include <linux/delay.h>
 26 #include <linux/slab.h>
 27 #include <linux/mutex.h>
 28 #include <linux/module.h>
 29 #include <linux/firmware.h>
 30 #include <sound/core.h>
 31 #include "hda_codec.h"
 32 #include "hda_local.h"
 33 #include "hda_auto_parser.h"
 34 #include "hda_jack.h"
 35 
 36 #include "ca0132_regs.h"
 37 
 38 /* Enable this to see controls for tuning purpose. */
 39 /*#define ENABLE_TUNING_CONTROLS*/
 40 
 41 #define FLOAT_ZERO      0x00000000
 42 #define FLOAT_ONE       0x3f800000
 43 #define FLOAT_TWO       0x40000000
 44 #define FLOAT_MINUS_5   0xc0a00000
 45 
 46 #define UNSOL_TAG_DSP   0x16
 47 
 48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
 49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
 50 
 51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
 52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
 53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
 54 
 55 #define MASTERCONTROL                           0x80
 56 #define MASTERCONTROL_ALLOC_DMA_CHAN            10
 57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
 58 
 59 #define WIDGET_CHIP_CTRL      0x15
 60 #define WIDGET_DSP_CTRL       0x16
 61 
 62 #define MEM_CONNID_MICIN1     3
 63 #define MEM_CONNID_MICIN2     5
 64 #define MEM_CONNID_MICOUT1    12
 65 #define MEM_CONNID_MICOUT2    14
 66 #define MEM_CONNID_WUH        10
 67 #define MEM_CONNID_DSP        16
 68 #define MEM_CONNID_DMIC       100
 69 
 70 #define SCP_SET    0
 71 #define SCP_GET    1
 72 
 73 #define EFX_FILE   "ctefx.bin"
 74 
 75 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
 76 MODULE_FIRMWARE(EFX_FILE);
 77 #endif
 78 
 79 static char *dirstr[2] = { "Playback", "Capture" };
 80 
 81 enum {
 82         SPEAKER_OUT,
 83         HEADPHONE_OUT
 84 };
 85 
 86 enum {
 87         DIGITAL_MIC,
 88         LINE_MIC_IN
 89 };
 90 
 91 enum {
 92 #define VNODE_START_NID    0x80
 93         VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
 94         VNID_MIC,
 95         VNID_HP_SEL,
 96         VNID_AMIC1_SEL,
 97         VNID_HP_ASEL,
 98         VNID_AMIC1_ASEL,
 99         VNODE_END_NID,
100 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
101 
102 #define EFFECT_START_NID    0x90
103 #define OUT_EFFECT_START_NID    EFFECT_START_NID
104         SURROUND = OUT_EFFECT_START_NID,
105         CRYSTALIZER,
106         DIALOG_PLUS,
107         SMART_VOLUME,
108         X_BASS,
109         EQUALIZER,
110         OUT_EFFECT_END_NID,
111 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
112 
113 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
114         ECHO_CANCELLATION = IN_EFFECT_START_NID,
115         VOICE_FOCUS,
116         MIC_SVM,
117         NOISE_REDUCTION,
118         IN_EFFECT_END_NID,
119 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
120 
121         VOICEFX = IN_EFFECT_END_NID,
122         PLAY_ENHANCEMENT,
123         CRYSTAL_VOICE,
124         EFFECT_END_NID
125 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
126 };
127 
128 /* Effects values size*/
129 #define EFFECT_VALS_MAX_COUNT 12
130 
131 /* Latency introduced by DSP blocks in milliseconds. */
132 #define DSP_CAPTURE_INIT_LATENCY        0
133 #define DSP_CRYSTAL_VOICE_LATENCY       124
134 #define DSP_PLAYBACK_INIT_LATENCY       13
135 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
136 #define DSP_SPEAKER_OUT_LATENCY         7
137 
138 struct ct_effect {
139         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
140         hda_nid_t nid;
141         int mid; /*effect module ID*/
142         int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
143         int direct; /* 0:output; 1:input*/
144         int params; /* number of default non-on/off params */
145         /*effect default values, 1st is on/off. */
146         unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
147 };
148 
149 #define EFX_DIR_OUT 0
150 #define EFX_DIR_IN  1
151 
152 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
153         { .name = "Surround",
154           .nid = SURROUND,
155           .mid = 0x96,
156           .reqs = {0, 1},
157           .direct = EFX_DIR_OUT,
158           .params = 1,
159           .def_vals = {0x3F800000, 0x3F2B851F}
160         },
161         { .name = "Crystalizer",
162           .nid = CRYSTALIZER,
163           .mid = 0x96,
164           .reqs = {7, 8},
165           .direct = EFX_DIR_OUT,
166           .params = 1,
167           .def_vals = {0x3F800000, 0x3F266666}
168         },
169         { .name = "Dialog Plus",
170           .nid = DIALOG_PLUS,
171           .mid = 0x96,
172           .reqs = {2, 3},
173           .direct = EFX_DIR_OUT,
174           .params = 1,
175           .def_vals = {0x00000000, 0x3F000000}
176         },
177         { .name = "Smart Volume",
178           .nid = SMART_VOLUME,
179           .mid = 0x96,
180           .reqs = {4, 5, 6},
181           .direct = EFX_DIR_OUT,
182           .params = 2,
183           .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
184         },
185         { .name = "X-Bass",
186           .nid = X_BASS,
187           .mid = 0x96,
188           .reqs = {24, 23, 25},
189           .direct = EFX_DIR_OUT,
190           .params = 2,
191           .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
192         },
193         { .name = "Equalizer",
194           .nid = EQUALIZER,
195           .mid = 0x96,
196           .reqs = {9, 10, 11, 12, 13, 14,
197                         15, 16, 17, 18, 19, 20},
198           .direct = EFX_DIR_OUT,
199           .params = 11,
200           .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
201                        0x00000000, 0x00000000, 0x00000000, 0x00000000,
202                        0x00000000, 0x00000000, 0x00000000, 0x00000000}
203         },
204         { .name = "Echo Cancellation",
205           .nid = ECHO_CANCELLATION,
206           .mid = 0x95,
207           .reqs = {0, 1, 2, 3},
208           .direct = EFX_DIR_IN,
209           .params = 3,
210           .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
211         },
212         { .name = "Voice Focus",
213           .nid = VOICE_FOCUS,
214           .mid = 0x95,
215           .reqs = {6, 7, 8, 9},
216           .direct = EFX_DIR_IN,
217           .params = 3,
218           .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
219         },
220         { .name = "Mic SVM",
221           .nid = MIC_SVM,
222           .mid = 0x95,
223           .reqs = {44, 45},
224           .direct = EFX_DIR_IN,
225           .params = 1,
226           .def_vals = {0x00000000, 0x3F3D70A4}
227         },
228         { .name = "Noise Reduction",
229           .nid = NOISE_REDUCTION,
230           .mid = 0x95,
231           .reqs = {4, 5},
232           .direct = EFX_DIR_IN,
233           .params = 1,
234           .def_vals = {0x3F800000, 0x3F000000}
235         },
236         { .name = "VoiceFX",
237           .nid = VOICEFX,
238           .mid = 0x95,
239           .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
240           .direct = EFX_DIR_IN,
241           .params = 8,
242           .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
243                        0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
244                        0x00000000}
245         }
246 };
247 
248 /* Tuning controls */
249 #ifdef ENABLE_TUNING_CONTROLS
250 
251 enum {
252 #define TUNING_CTL_START_NID  0xC0
253         WEDGE_ANGLE = TUNING_CTL_START_NID,
254         SVM_LEVEL,
255         EQUALIZER_BAND_0,
256         EQUALIZER_BAND_1,
257         EQUALIZER_BAND_2,
258         EQUALIZER_BAND_3,
259         EQUALIZER_BAND_4,
260         EQUALIZER_BAND_5,
261         EQUALIZER_BAND_6,
262         EQUALIZER_BAND_7,
263         EQUALIZER_BAND_8,
264         EQUALIZER_BAND_9,
265         TUNING_CTL_END_NID
266 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
267 };
268 
269 struct ct_tuning_ctl {
270         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
271         hda_nid_t parent_nid;
272         hda_nid_t nid;
273         int mid; /*effect module ID*/
274         int req; /*effect module request*/
275         int direct; /* 0:output; 1:input*/
276         unsigned int def_val;/*effect default values*/
277 };
278 
279 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
280         { .name = "Wedge Angle",
281           .parent_nid = VOICE_FOCUS,
282           .nid = WEDGE_ANGLE,
283           .mid = 0x95,
284           .req = 8,
285           .direct = EFX_DIR_IN,
286           .def_val = 0x41F00000
287         },
288         { .name = "SVM Level",
289           .parent_nid = MIC_SVM,
290           .nid = SVM_LEVEL,
291           .mid = 0x95,
292           .req = 45,
293           .direct = EFX_DIR_IN,
294           .def_val = 0x3F3D70A4
295         },
296         { .name = "EQ Band0",
297           .parent_nid = EQUALIZER,
298           .nid = EQUALIZER_BAND_0,
299           .mid = 0x96,
300           .req = 11,
301           .direct = EFX_DIR_OUT,
302           .def_val = 0x00000000
303         },
304         { .name = "EQ Band1",
305           .parent_nid = EQUALIZER,
306           .nid = EQUALIZER_BAND_1,
307           .mid = 0x96,
308           .req = 12,
309           .direct = EFX_DIR_OUT,
310           .def_val = 0x00000000
311         },
312         { .name = "EQ Band2",
313           .parent_nid = EQUALIZER,
314           .nid = EQUALIZER_BAND_2,
315           .mid = 0x96,
316           .req = 13,
317           .direct = EFX_DIR_OUT,
318           .def_val = 0x00000000
319         },
320         { .name = "EQ Band3",
321           .parent_nid = EQUALIZER,
322           .nid = EQUALIZER_BAND_3,
323           .mid = 0x96,
324           .req = 14,
325           .direct = EFX_DIR_OUT,
326           .def_val = 0x00000000
327         },
328         { .name = "EQ Band4",
329           .parent_nid = EQUALIZER,
330           .nid = EQUALIZER_BAND_4,
331           .mid = 0x96,
332           .req = 15,
333           .direct = EFX_DIR_OUT,
334           .def_val = 0x00000000
335         },
336         { .name = "EQ Band5",
337           .parent_nid = EQUALIZER,
338           .nid = EQUALIZER_BAND_5,
339           .mid = 0x96,
340           .req = 16,
341           .direct = EFX_DIR_OUT,
342           .def_val = 0x00000000
343         },
344         { .name = "EQ Band6",
345           .parent_nid = EQUALIZER,
346           .nid = EQUALIZER_BAND_6,
347           .mid = 0x96,
348           .req = 17,
349           .direct = EFX_DIR_OUT,
350           .def_val = 0x00000000
351         },
352         { .name = "EQ Band7",
353           .parent_nid = EQUALIZER,
354           .nid = EQUALIZER_BAND_7,
355           .mid = 0x96,
356           .req = 18,
357           .direct = EFX_DIR_OUT,
358           .def_val = 0x00000000
359         },
360         { .name = "EQ Band8",
361           .parent_nid = EQUALIZER,
362           .nid = EQUALIZER_BAND_8,
363           .mid = 0x96,
364           .req = 19,
365           .direct = EFX_DIR_OUT,
366           .def_val = 0x00000000
367         },
368         { .name = "EQ Band9",
369           .parent_nid = EQUALIZER,
370           .nid = EQUALIZER_BAND_9,
371           .mid = 0x96,
372           .req = 20,
373           .direct = EFX_DIR_OUT,
374           .def_val = 0x00000000
375         }
376 };
377 #endif
378 
379 /* Voice FX Presets */
380 #define VOICEFX_MAX_PARAM_COUNT 9
381 
382 struct ct_voicefx {
383         char *name;
384         hda_nid_t nid;
385         int mid;
386         int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
387 };
388 
389 struct ct_voicefx_preset {
390         char *name; /*preset name*/
391         unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
392 };
393 
394 static struct ct_voicefx ca0132_voicefx = {
395         .name = "VoiceFX Capture Switch",
396         .nid = VOICEFX,
397         .mid = 0x95,
398         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
399 };
400 
401 static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
402         { .name = "Neutral",
403           .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
404                     0x44FA0000, 0x3F800000, 0x3F800000,
405                     0x3F800000, 0x00000000, 0x00000000 }
406         },
407         { .name = "Female2Male",
408           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
409                     0x44FA0000, 0x3F19999A, 0x3F866666,
410                     0x3F800000, 0x00000000, 0x00000000 }
411         },
412         { .name = "Male2Female",
413           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
414                     0x450AC000, 0x4017AE14, 0x3F6B851F,
415                     0x3F800000, 0x00000000, 0x00000000 }
416         },
417         { .name = "ScrappyKid",
418           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
419                     0x44FA0000, 0x40400000, 0x3F28F5C3,
420                     0x3F800000, 0x00000000, 0x00000000 }
421         },
422         { .name = "Elderly",
423           .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
424                     0x44E10000, 0x3FB33333, 0x3FB9999A,
425                     0x3F800000, 0x3E3A2E43, 0x00000000 }
426         },
427         { .name = "Orc",
428           .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
429                     0x45098000, 0x3F266666, 0x3FC00000,
430                     0x3F800000, 0x00000000, 0x00000000 }
431         },
432         { .name = "Elf",
433           .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
434                     0x45193000, 0x3F8E147B, 0x3F75C28F,
435                     0x3F800000, 0x00000000, 0x00000000 }
436         },
437         { .name = "Dwarf",
438           .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
439                     0x45007000, 0x3F451EB8, 0x3F7851EC,
440                     0x3F800000, 0x00000000, 0x00000000 }
441         },
442         { .name = "AlienBrute",
443           .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
444                     0x451F6000, 0x3F266666, 0x3FA7D945,
445                     0x3F800000, 0x3CF5C28F, 0x00000000 }
446         },
447         { .name = "Robot",
448           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449                     0x44FA0000, 0x3FB2718B, 0x3F800000,
450                     0xBC07010E, 0x00000000, 0x00000000 }
451         },
452         { .name = "Marine",
453           .vals = { 0x3F800000, 0x43C20000, 0x44906000,
454                     0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
455                     0x3F0A3D71, 0x00000000, 0x00000000 }
456         },
457         { .name = "Emo",
458           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459                     0x44FA0000, 0x3F800000, 0x3F800000,
460                     0x3E4CCCCD, 0x00000000, 0x00000000 }
461         },
462         { .name = "DeepVoice",
463           .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
464                     0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
465                     0x3F800000, 0x00000000, 0x00000000 }
466         },
467         { .name = "Munchkin",
468           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
469                     0x44FA0000, 0x3F800000, 0x3F1A043C,
470                     0x3F800000, 0x00000000, 0x00000000 }
471         }
472 };
473 
474 enum hda_cmd_vendor_io {
475         /* for DspIO node */
476         VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
477         VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
478 
479         VENDOR_DSPIO_STATUS                  = 0xF01,
480         VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
481         VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
482         VENDOR_DSPIO_DSP_INIT                = 0x703,
483         VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
484         VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
485 
486         /* for ChipIO node */
487         VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
488         VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
489         VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
490         VENDOR_CHIPIO_DATA_LOW               = 0x300,
491         VENDOR_CHIPIO_DATA_HIGH              = 0x400,
492 
493         VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
494         VENDOR_CHIPIO_STATUS                 = 0xF01,
495         VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
496         VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
497 
498         VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
499         VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
500 
501         VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
502         VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
503 
504         VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
505         VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
506         VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
507         VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
508         VENDOR_CHIPIO_FLAG_SET               = 0x70F,
509         VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
510         VENDOR_CHIPIO_PARAM_SET              = 0x710,
511         VENDOR_CHIPIO_PARAM_GET              = 0xF10,
512 
513         VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
514         VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
515         VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
516         VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
517 
518         VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
519         VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
520         VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
521         VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
522 
523         VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
524         VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
525         VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
526         VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
527         VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
528         VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
529 
530         VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
531 };
532 
533 /*
534  *  Control flag IDs
535  */
536 enum control_flag_id {
537         /* Connection manager stream setup is bypassed/enabled */
538         CONTROL_FLAG_C_MGR                  = 0,
539         /* DSP DMA is bypassed/enabled */
540         CONTROL_FLAG_DMA                    = 1,
541         /* 8051 'idle' mode is disabled/enabled */
542         CONTROL_FLAG_IDLE_ENABLE            = 2,
543         /* Tracker for the SPDIF-in path is bypassed/enabled */
544         CONTROL_FLAG_TRACKER                = 3,
545         /* DigitalOut to Spdif2Out connection is disabled/enabled */
546         CONTROL_FLAG_SPDIF2OUT              = 4,
547         /* Digital Microphone is disabled/enabled */
548         CONTROL_FLAG_DMIC                   = 5,
549         /* ADC_B rate is 48 kHz/96 kHz */
550         CONTROL_FLAG_ADC_B_96KHZ            = 6,
551         /* ADC_C rate is 48 kHz/96 kHz */
552         CONTROL_FLAG_ADC_C_96KHZ            = 7,
553         /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
554         CONTROL_FLAG_DAC_96KHZ              = 8,
555         /* DSP rate is 48 kHz/96 kHz */
556         CONTROL_FLAG_DSP_96KHZ              = 9,
557         /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
558         CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
559         /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
560         CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
561         /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
562         CONTROL_FLAG_DECODE_LOOP            = 12,
563         /* De-emphasis filter on DAC-1 disabled/enabled */
564         CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
565         /* De-emphasis filter on DAC-2 disabled/enabled */
566         CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
567         /* De-emphasis filter on DAC-3 disabled/enabled */
568         CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
569         /* High-pass filter on ADC_B disabled/enabled */
570         CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
571         /* High-pass filter on ADC_C disabled/enabled */
572         CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
573         /* Common mode on Port_A disabled/enabled */
574         CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
575         /* Common mode on Port_D disabled/enabled */
576         CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
577         /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
578         CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
579         /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
580         CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
581         /* ASI rate is 48kHz/96kHz */
582         CONTROL_FLAG_ASI_96KHZ              = 22,
583         /* DAC power settings able to control attached ports no/yes */
584         CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
585         /* Clock Stop OK reporting is disabled/enabled */
586         CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
587         /* Number of control flags */
588         CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
589 };
590 
591 /*
592  * Control parameter IDs
593  */
594 enum control_param_id {
595         /* 0: None, 1: Mic1In*/
596         CONTROL_PARAM_VIP_SOURCE               = 1,
597         /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
598         CONTROL_PARAM_SPDIF1_SOURCE            = 2,
599         /* Port A output stage gain setting to use when 16 Ohm output
600          * impedance is selected*/
601         CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
602         /* Port D output stage gain setting to use when 16 Ohm output
603          * impedance is selected*/
604         CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
605 
606         /* Stream Control */
607 
608         /* Select stream with the given ID */
609         CONTROL_PARAM_STREAM_ID                = 24,
610         /* Source connection point for the selected stream */
611         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
612         /* Destination connection point for the selected stream */
613         CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
614         /* Number of audio channels in the selected stream */
615         CONTROL_PARAM_STREAMS_CHANNELS         = 27,
616         /*Enable control for the selected stream */
617         CONTROL_PARAM_STREAM_CONTROL           = 28,
618 
619         /* Connection Point Control */
620 
621         /* Select connection point with the given ID */
622         CONTROL_PARAM_CONN_POINT_ID            = 29,
623         /* Connection point sample rate */
624         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
625 
626         /* Node Control */
627 
628         /* Select HDA node with the given ID */
629         CONTROL_PARAM_NODE_ID                  = 31
630 };
631 
632 /*
633  *  Dsp Io Status codes
634  */
635 enum hda_vendor_status_dspio {
636         /* Success */
637         VENDOR_STATUS_DSPIO_OK                       = 0x00,
638         /* Busy, unable to accept new command, the host must retry */
639         VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
640         /* SCP command queue is full */
641         VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
642         /* SCP response queue is empty */
643         VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
644 };
645 
646 /*
647  *  Chip Io Status codes
648  */
649 enum hda_vendor_status_chipio {
650         /* Success */
651         VENDOR_STATUS_CHIPIO_OK   = 0x00,
652         /* Busy, unable to accept new command, the host must retry */
653         VENDOR_STATUS_CHIPIO_BUSY = 0x01
654 };
655 
656 /*
657  *  CA0132 sample rate
658  */
659 enum ca0132_sample_rate {
660         SR_6_000        = 0x00,
661         SR_8_000        = 0x01,
662         SR_9_600        = 0x02,
663         SR_11_025       = 0x03,
664         SR_16_000       = 0x04,
665         SR_22_050       = 0x05,
666         SR_24_000       = 0x06,
667         SR_32_000       = 0x07,
668         SR_44_100       = 0x08,
669         SR_48_000       = 0x09,
670         SR_88_200       = 0x0A,
671         SR_96_000       = 0x0B,
672         SR_144_000      = 0x0C,
673         SR_176_400      = 0x0D,
674         SR_192_000      = 0x0E,
675         SR_384_000      = 0x0F,
676 
677         SR_COUNT        = 0x10,
678 
679         SR_RATE_UNKNOWN = 0x1F
680 };
681 
682 enum dsp_download_state {
683         DSP_DOWNLOAD_FAILED = -1,
684         DSP_DOWNLOAD_INIT   = 0,
685         DSP_DOWNLOADING     = 1,
686         DSP_DOWNLOADED      = 2
687 };
688 
689 /* retrieve parameters from hda format */
690 #define get_hdafmt_chs(fmt)     (fmt & 0xf)
691 #define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
692 #define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
693 #define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
694 
695 /*
696  * CA0132 specific
697  */
698 
699 struct ca0132_spec {
700         struct snd_kcontrol_new *mixers[5];
701         unsigned int num_mixers;
702         const struct hda_verb *base_init_verbs;
703         const struct hda_verb *base_exit_verbs;
704         const struct hda_verb *chip_init_verbs;
705         struct hda_verb *spec_init_verbs;
706         struct auto_pin_cfg autocfg;
707 
708         /* Nodes configurations */
709         struct hda_multi_out multiout;
710         hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
711         hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
712         unsigned int num_outputs;
713         hda_nid_t input_pins[AUTO_PIN_LAST];
714         hda_nid_t adcs[AUTO_PIN_LAST];
715         hda_nid_t dig_out;
716         hda_nid_t dig_in;
717         unsigned int num_inputs;
718         hda_nid_t shared_mic_nid;
719         hda_nid_t shared_out_nid;
720         hda_nid_t unsol_tag_hp;
721         hda_nid_t unsol_tag_amic1;
722 
723         /* chip access */
724         struct mutex chipio_mutex; /* chip access mutex */
725         u32 curr_chip_addx;
726 
727         /* DSP download related */
728         enum dsp_download_state dsp_state;
729         unsigned int dsp_stream_id;
730         unsigned int wait_scp;
731         unsigned int wait_scp_header;
732         unsigned int wait_num_data;
733         unsigned int scp_resp_header;
734         unsigned int scp_resp_data[4];
735         unsigned int scp_resp_count;
736 
737         /* mixer and effects related */
738         unsigned char dmic_ctl;
739         int cur_out_type;
740         int cur_mic_type;
741         long vnode_lvol[VNODES_COUNT];
742         long vnode_rvol[VNODES_COUNT];
743         long vnode_lswitch[VNODES_COUNT];
744         long vnode_rswitch[VNODES_COUNT];
745         long effects_switch[EFFECTS_COUNT];
746         long voicefx_val;
747         long cur_mic_boost;
748 
749         struct hda_codec *codec;
750         struct delayed_work unsol_hp_work;
751         int quirk;
752 
753 #ifdef ENABLE_TUNING_CONTROLS
754         long cur_ctl_vals[TUNING_CTLS_COUNT];
755 #endif
756 };
757 
758 /*
759  * CA0132 quirks table
760  */
761 enum {
762         QUIRK_NONE,
763         QUIRK_ALIENWARE,
764 };
765 
766 static const struct hda_pintbl alienware_pincfgs[] = {
767         { 0x0b, 0x90170110 }, /* Builtin Speaker */
768         { 0x0c, 0x411111f0 }, /* N/A */
769         { 0x0d, 0x411111f0 }, /* N/A */
770         { 0x0e, 0x411111f0 }, /* N/A */
771         { 0x0f, 0x0321101f }, /* HP */
772         { 0x10, 0x411111f0 }, /* Headset?  disabled for now */
773         { 0x11, 0x03a11021 }, /* Mic */
774         { 0x12, 0xd5a30140 }, /* Builtin Mic */
775         { 0x13, 0x411111f0 }, /* N/A */
776         { 0x18, 0x411111f0 }, /* N/A */
777         {}
778 };
779 
780 static const struct snd_pci_quirk ca0132_quirks[] = {
781         SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
782         SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
783         SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
784         {}
785 };
786 
787 /*
788  * CA0132 codec access
789  */
790 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
791                 unsigned int verb, unsigned int parm, unsigned int *res)
792 {
793         unsigned int response;
794         response = snd_hda_codec_read(codec, nid, 0, verb, parm);
795         *res = response;
796 
797         return ((response == -1) ? -1 : 0);
798 }
799 
800 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
801                 unsigned short converter_format, unsigned int *res)
802 {
803         return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
804                                 converter_format & 0xffff, res);
805 }
806 
807 static int codec_set_converter_stream_channel(struct hda_codec *codec,
808                                 hda_nid_t nid, unsigned char stream,
809                                 unsigned char channel, unsigned int *res)
810 {
811         unsigned char converter_stream_channel = 0;
812 
813         converter_stream_channel = (stream << 4) | (channel & 0x0f);
814         return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
815                                 converter_stream_channel, res);
816 }
817 
818 /* Chip access helper function */
819 static int chipio_send(struct hda_codec *codec,
820                        unsigned int reg,
821                        unsigned int data)
822 {
823         unsigned int res;
824         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
825 
826         /* send bits of data specified by reg */
827         do {
828                 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
829                                          reg, data);
830                 if (res == VENDOR_STATUS_CHIPIO_OK)
831                         return 0;
832                 msleep(20);
833         } while (time_before(jiffies, timeout));
834 
835         return -EIO;
836 }
837 
838 /*
839  * Write chip address through the vendor widget -- NOT protected by the Mutex!
840  */
841 static int chipio_write_address(struct hda_codec *codec,
842                                 unsigned int chip_addx)
843 {
844         struct ca0132_spec *spec = codec->spec;
845         int res;
846 
847         if (spec->curr_chip_addx == chip_addx)
848                         return 0;
849 
850         /* send low 16 bits of the address */
851         res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
852                           chip_addx & 0xffff);
853 
854         if (res != -EIO) {
855                 /* send high 16 bits of the address */
856                 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
857                                   chip_addx >> 16);
858         }
859 
860         spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
861 
862         return res;
863 }
864 
865 /*
866  * Write data through the vendor widget -- NOT protected by the Mutex!
867  */
868 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
869 {
870         struct ca0132_spec *spec = codec->spec;
871         int res;
872 
873         /* send low 16 bits of the data */
874         res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
875 
876         if (res != -EIO) {
877                 /* send high 16 bits of the data */
878                 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
879                                   data >> 16);
880         }
881 
882         /*If no error encountered, automatically increment the address
883         as per chip behaviour*/
884         spec->curr_chip_addx = (res != -EIO) ?
885                                         (spec->curr_chip_addx + 4) : ~0UL;
886         return res;
887 }
888 
889 /*
890  * Write multiple data through the vendor widget -- NOT protected by the Mutex!
891  */
892 static int chipio_write_data_multiple(struct hda_codec *codec,
893                                       const u32 *data,
894                                       unsigned int count)
895 {
896         int status = 0;
897 
898         if (data == NULL) {
899                 codec_dbg(codec, "chipio_write_data null ptr\n");
900                 return -EINVAL;
901         }
902 
903         while ((count-- != 0) && (status == 0))
904                 status = chipio_write_data(codec, *data++);
905 
906         return status;
907 }
908 
909 
910 /*
911  * Read data through the vendor widget -- NOT protected by the Mutex!
912  */
913 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
914 {
915         struct ca0132_spec *spec = codec->spec;
916         int res;
917 
918         /* post read */
919         res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
920 
921         if (res != -EIO) {
922                 /* read status */
923                 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
924         }
925 
926         if (res != -EIO) {
927                 /* read data */
928                 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
929                                            VENDOR_CHIPIO_HIC_READ_DATA,
930                                            0);
931         }
932 
933         /*If no error encountered, automatically increment the address
934         as per chip behaviour*/
935         spec->curr_chip_addx = (res != -EIO) ?
936                                         (spec->curr_chip_addx + 4) : ~0UL;
937         return res;
938 }
939 
940 /*
941  * Write given value to the given address through the chip I/O widget.
942  * protected by the Mutex
943  */
944 static int chipio_write(struct hda_codec *codec,
945                 unsigned int chip_addx, const unsigned int data)
946 {
947         struct ca0132_spec *spec = codec->spec;
948         int err;
949 
950         mutex_lock(&spec->chipio_mutex);
951 
952         /* write the address, and if successful proceed to write data */
953         err = chipio_write_address(codec, chip_addx);
954         if (err < 0)
955                 goto exit;
956 
957         err = chipio_write_data(codec, data);
958         if (err < 0)
959                 goto exit;
960 
961 exit:
962         mutex_unlock(&spec->chipio_mutex);
963         return err;
964 }
965 
966 /*
967  * Write multiple values to the given address through the chip I/O widget.
968  * protected by the Mutex
969  */
970 static int chipio_write_multiple(struct hda_codec *codec,
971                                  u32 chip_addx,
972                                  const u32 *data,
973                                  unsigned int count)
974 {
975         struct ca0132_spec *spec = codec->spec;
976         int status;
977 
978         mutex_lock(&spec->chipio_mutex);
979         status = chipio_write_address(codec, chip_addx);
980         if (status < 0)
981                 goto error;
982 
983         status = chipio_write_data_multiple(codec, data, count);
984 error:
985         mutex_unlock(&spec->chipio_mutex);
986 
987         return status;
988 }
989 
990 /*
991  * Read the given address through the chip I/O widget
992  * protected by the Mutex
993  */
994 static int chipio_read(struct hda_codec *codec,
995                 unsigned int chip_addx, unsigned int *data)
996 {
997         struct ca0132_spec *spec = codec->spec;
998         int err;
999 
1000         mutex_lock(&spec->chipio_mutex);
1001 
1002         /* write the address, and if successful proceed to write data */
1003         err = chipio_write_address(codec, chip_addx);
1004         if (err < 0)
1005                 goto exit;
1006 
1007         err = chipio_read_data(codec, data);
1008         if (err < 0)
1009                 goto exit;
1010 
1011 exit:
1012         mutex_unlock(&spec->chipio_mutex);
1013         return err;
1014 }
1015 
1016 /*
1017  * Set chip control flags through the chip I/O widget.
1018  */
1019 static void chipio_set_control_flag(struct hda_codec *codec,
1020                                     enum control_flag_id flag_id,
1021                                     bool flag_state)
1022 {
1023         unsigned int val;
1024         unsigned int flag_bit;
1025 
1026         flag_bit = (flag_state ? 1 : 0);
1027         val = (flag_bit << 7) | (flag_id);
1028         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1029                             VENDOR_CHIPIO_FLAG_SET, val);
1030 }
1031 
1032 /*
1033  * Set chip parameters through the chip I/O widget.
1034  */
1035 static void chipio_set_control_param(struct hda_codec *codec,
1036                 enum control_param_id param_id, int param_val)
1037 {
1038         struct ca0132_spec *spec = codec->spec;
1039         int val;
1040 
1041         if ((param_id < 32) && (param_val < 8)) {
1042                 val = (param_val << 5) | (param_id);
1043                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1044                                     VENDOR_CHIPIO_PARAM_SET, val);
1045         } else {
1046                 mutex_lock(&spec->chipio_mutex);
1047                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1048                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1049                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1050                                             param_id);
1051                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1052                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1053                                             param_val);
1054                 }
1055                 mutex_unlock(&spec->chipio_mutex);
1056         }
1057 }
1058 
1059 /*
1060  * Set sampling rate of the connection point.
1061  */
1062 static void chipio_set_conn_rate(struct hda_codec *codec,
1063                                 int connid, enum ca0132_sample_rate rate)
1064 {
1065         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1066         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1067                                  rate);
1068 }
1069 
1070 /*
1071  * Enable clocks.
1072  */
1073 static void chipio_enable_clocks(struct hda_codec *codec)
1074 {
1075         struct ca0132_spec *spec = codec->spec;
1076 
1077         mutex_lock(&spec->chipio_mutex);
1078         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1079                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1080         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1081                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1082         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1083                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1084         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1085                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1086         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1087                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1088         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1089                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1090         mutex_unlock(&spec->chipio_mutex);
1091 }
1092 
1093 /*
1094  * CA0132 DSP IO stuffs
1095  */
1096 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1097                       unsigned int data)
1098 {
1099         int res;
1100         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1101 
1102         /* send bits of data specified by reg to dsp */
1103         do {
1104                 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1105                 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1106                         return res;
1107                 msleep(20);
1108         } while (time_before(jiffies, timeout));
1109 
1110         return -EIO;
1111 }
1112 
1113 /*
1114  * Wait for DSP to be ready for commands
1115  */
1116 static void dspio_write_wait(struct hda_codec *codec)
1117 {
1118         int status;
1119         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1120 
1121         do {
1122                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1123                                                 VENDOR_DSPIO_STATUS, 0);
1124                 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1125                     (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1126                         break;
1127                 msleep(1);
1128         } while (time_before(jiffies, timeout));
1129 }
1130 
1131 /*
1132  * Write SCP data to DSP
1133  */
1134 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1135 {
1136         struct ca0132_spec *spec = codec->spec;
1137         int status;
1138 
1139         dspio_write_wait(codec);
1140 
1141         mutex_lock(&spec->chipio_mutex);
1142         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1143                             scp_data & 0xffff);
1144         if (status < 0)
1145                 goto error;
1146 
1147         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1148                                     scp_data >> 16);
1149         if (status < 0)
1150                 goto error;
1151 
1152         /* OK, now check if the write itself has executed*/
1153         status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1154                                     VENDOR_DSPIO_STATUS, 0);
1155 error:
1156         mutex_unlock(&spec->chipio_mutex);
1157 
1158         return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1159                         -EIO : 0;
1160 }
1161 
1162 /*
1163  * Write multiple SCP data to DSP
1164  */
1165 static int dspio_write_multiple(struct hda_codec *codec,
1166                                 unsigned int *buffer, unsigned int size)
1167 {
1168         int status = 0;
1169         unsigned int count;
1170 
1171         if ((buffer == NULL))
1172                 return -EINVAL;
1173 
1174         count = 0;
1175         while (count < size) {
1176                 status = dspio_write(codec, *buffer++);
1177                 if (status != 0)
1178                         break;
1179                 count++;
1180         }
1181 
1182         return status;
1183 }
1184 
1185 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1186 {
1187         int status;
1188 
1189         status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1190         if (status == -EIO)
1191                 return status;
1192 
1193         status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1194         if (status == -EIO ||
1195             status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1196                 return -EIO;
1197 
1198         *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1199                                    VENDOR_DSPIO_SCP_READ_DATA, 0);
1200 
1201         return 0;
1202 }
1203 
1204 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1205                                unsigned int *buf_size, unsigned int size_count)
1206 {
1207         int status = 0;
1208         unsigned int size = *buf_size;
1209         unsigned int count;
1210         unsigned int skip_count;
1211         unsigned int dummy;
1212 
1213         if ((buffer == NULL))
1214                 return -1;
1215 
1216         count = 0;
1217         while (count < size && count < size_count) {
1218                 status = dspio_read(codec, buffer++);
1219                 if (status != 0)
1220                         break;
1221                 count++;
1222         }
1223 
1224         skip_count = count;
1225         if (status == 0) {
1226                 while (skip_count < size) {
1227                         status = dspio_read(codec, &dummy);
1228                         if (status != 0)
1229                                 break;
1230                         skip_count++;
1231                 }
1232         }
1233         *buf_size = count;
1234 
1235         return status;
1236 }
1237 
1238 /*
1239  * Construct the SCP header using corresponding fields
1240  */
1241 static inline unsigned int
1242 make_scp_header(unsigned int target_id, unsigned int source_id,
1243                 unsigned int get_flag, unsigned int req,
1244                 unsigned int device_flag, unsigned int resp_flag,
1245                 unsigned int error_flag, unsigned int data_size)
1246 {
1247         unsigned int header = 0;
1248 
1249         header = (data_size & 0x1f) << 27;
1250         header |= (error_flag & 0x01) << 26;
1251         header |= (resp_flag & 0x01) << 25;
1252         header |= (device_flag & 0x01) << 24;
1253         header |= (req & 0x7f) << 17;
1254         header |= (get_flag & 0x01) << 16;
1255         header |= (source_id & 0xff) << 8;
1256         header |= target_id & 0xff;
1257 
1258         return header;
1259 }
1260 
1261 /*
1262  * Extract corresponding fields from SCP header
1263  */
1264 static inline void
1265 extract_scp_header(unsigned int header,
1266                    unsigned int *target_id, unsigned int *source_id,
1267                    unsigned int *get_flag, unsigned int *req,
1268                    unsigned int *device_flag, unsigned int *resp_flag,
1269                    unsigned int *error_flag, unsigned int *data_size)
1270 {
1271         if (data_size)
1272                 *data_size = (header >> 27) & 0x1f;
1273         if (error_flag)
1274                 *error_flag = (header >> 26) & 0x01;
1275         if (resp_flag)
1276                 *resp_flag = (header >> 25) & 0x01;
1277         if (device_flag)
1278                 *device_flag = (header >> 24) & 0x01;
1279         if (req)
1280                 *req = (header >> 17) & 0x7f;
1281         if (get_flag)
1282                 *get_flag = (header >> 16) & 0x01;
1283         if (source_id)
1284                 *source_id = (header >> 8) & 0xff;
1285         if (target_id)
1286                 *target_id = header & 0xff;
1287 }
1288 
1289 #define SCP_MAX_DATA_WORDS  (16)
1290 
1291 /* Structure to contain any SCP message */
1292 struct scp_msg {
1293         unsigned int hdr;
1294         unsigned int data[SCP_MAX_DATA_WORDS];
1295 };
1296 
1297 static void dspio_clear_response_queue(struct hda_codec *codec)
1298 {
1299         unsigned int dummy = 0;
1300         int status = -1;
1301 
1302         /* clear all from the response queue */
1303         do {
1304                 status = dspio_read(codec, &dummy);
1305         } while (status == 0);
1306 }
1307 
1308 static int dspio_get_response_data(struct hda_codec *codec)
1309 {
1310         struct ca0132_spec *spec = codec->spec;
1311         unsigned int data = 0;
1312         unsigned int count;
1313 
1314         if (dspio_read(codec, &data) < 0)
1315                 return -EIO;
1316 
1317         if ((data & 0x00ffffff) == spec->wait_scp_header) {
1318                 spec->scp_resp_header = data;
1319                 spec->scp_resp_count = data >> 27;
1320                 count = spec->wait_num_data;
1321                 dspio_read_multiple(codec, spec->scp_resp_data,
1322                                     &spec->scp_resp_count, count);
1323                 return 0;
1324         }
1325 
1326         return -EIO;
1327 }
1328 
1329 /*
1330  * Send SCP message to DSP
1331  */
1332 static int dspio_send_scp_message(struct hda_codec *codec,
1333                                   unsigned char *send_buf,
1334                                   unsigned int send_buf_size,
1335                                   unsigned char *return_buf,
1336                                   unsigned int return_buf_size,
1337                                   unsigned int *bytes_returned)
1338 {
1339         struct ca0132_spec *spec = codec->spec;
1340         int status = -1;
1341         unsigned int scp_send_size = 0;
1342         unsigned int total_size;
1343         bool waiting_for_resp = false;
1344         unsigned int header;
1345         struct scp_msg *ret_msg;
1346         unsigned int resp_src_id, resp_target_id;
1347         unsigned int data_size, src_id, target_id, get_flag, device_flag;
1348 
1349         if (bytes_returned)
1350                 *bytes_returned = 0;
1351 
1352         /* get scp header from buffer */
1353         header = *((unsigned int *)send_buf);
1354         extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1355                            &device_flag, NULL, NULL, &data_size);
1356         scp_send_size = data_size + 1;
1357         total_size = (scp_send_size * 4);
1358 
1359         if (send_buf_size < total_size)
1360                 return -EINVAL;
1361 
1362         if (get_flag || device_flag) {
1363                 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1364                         return -EINVAL;
1365 
1366                 spec->wait_scp_header = *((unsigned int *)send_buf);
1367 
1368                 /* swap source id with target id */
1369                 resp_target_id = src_id;
1370                 resp_src_id = target_id;
1371                 spec->wait_scp_header &= 0xffff0000;
1372                 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1373                 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1374                 spec->wait_scp = 1;
1375                 waiting_for_resp = true;
1376         }
1377 
1378         status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1379                                       scp_send_size);
1380         if (status < 0) {
1381                 spec->wait_scp = 0;
1382                 return status;
1383         }
1384 
1385         if (waiting_for_resp) {
1386                 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1387                 memset(return_buf, 0, return_buf_size);
1388                 do {
1389                         msleep(20);
1390                 } while (spec->wait_scp && time_before(jiffies, timeout));
1391                 waiting_for_resp = false;
1392                 if (!spec->wait_scp) {
1393                         ret_msg = (struct scp_msg *)return_buf;
1394                         memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1395                         memcpy(&ret_msg->data, spec->scp_resp_data,
1396                                spec->wait_num_data);
1397                         *bytes_returned = (spec->scp_resp_count + 1) * 4;
1398                         status = 0;
1399                 } else {
1400                         status = -EIO;
1401                 }
1402                 spec->wait_scp = 0;
1403         }
1404 
1405         return status;
1406 }
1407 
1408 /**
1409  * Prepare and send the SCP message to DSP
1410  * @codec: the HDA codec
1411  * @mod_id: ID of the DSP module to send the command
1412  * @req: ID of request to send to the DSP module
1413  * @dir: SET or GET
1414  * @data: pointer to the data to send with the request, request specific
1415  * @len: length of the data, in bytes
1416  * @reply: point to the buffer to hold data returned for a reply
1417  * @reply_len: length of the reply buffer returned from GET
1418  *
1419  * Returns zero or a negative error code.
1420  */
1421 static int dspio_scp(struct hda_codec *codec,
1422                 int mod_id, int req, int dir, void *data, unsigned int len,
1423                 void *reply, unsigned int *reply_len)
1424 {
1425         int status = 0;
1426         struct scp_msg scp_send, scp_reply;
1427         unsigned int ret_bytes, send_size, ret_size;
1428         unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1429         unsigned int reply_data_size;
1430 
1431         memset(&scp_send, 0, sizeof(scp_send));
1432         memset(&scp_reply, 0, sizeof(scp_reply));
1433 
1434         if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1435                 return -EINVAL;
1436 
1437         if (dir == SCP_GET && reply == NULL) {
1438                 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1439                 return -EINVAL;
1440         }
1441 
1442         if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1443                 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1444                 return -EINVAL;
1445         }
1446 
1447         scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1448                                        0, 0, 0, len/sizeof(unsigned int));
1449         if (data != NULL && len > 0) {
1450                 len = min((unsigned int)(sizeof(scp_send.data)), len);
1451                 memcpy(scp_send.data, data, len);
1452         }
1453 
1454         ret_bytes = 0;
1455         send_size = sizeof(unsigned int) + len;
1456         status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1457                                         send_size, (unsigned char *)&scp_reply,
1458                                         sizeof(scp_reply), &ret_bytes);
1459 
1460         if (status < 0) {
1461                 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1462                 return status;
1463         }
1464 
1465         /* extract send and reply headers members */
1466         extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1467                            NULL, NULL, NULL, NULL, NULL);
1468         extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1469                            &reply_resp_flag, &reply_error_flag,
1470                            &reply_data_size);
1471 
1472         if (!send_get_flag)
1473                 return 0;
1474 
1475         if (reply_resp_flag && !reply_error_flag) {
1476                 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1477                                         / sizeof(unsigned int);
1478 
1479                 if (*reply_len < ret_size*sizeof(unsigned int)) {
1480                         codec_dbg(codec, "reply too long for buf\n");
1481                         return -EINVAL;
1482                 } else if (ret_size != reply_data_size) {
1483                         codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1484                         return -EINVAL;
1485                 } else {
1486                         *reply_len = ret_size*sizeof(unsigned int);
1487                         memcpy(reply, scp_reply.data, *reply_len);
1488                 }
1489         } else {
1490                 codec_dbg(codec, "reply ill-formed or errflag set\n");
1491                 return -EIO;
1492         }
1493 
1494         return status;
1495 }
1496 
1497 /*
1498  * Set DSP parameters
1499  */
1500 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1501                         int req, void *data, unsigned int len)
1502 {
1503         return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1504 }
1505 
1506 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1507                         int req, unsigned int data)
1508 {
1509         return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1510 }
1511 
1512 /*
1513  * Allocate a DSP DMA channel via an SCP message
1514  */
1515 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1516 {
1517         int status = 0;
1518         unsigned int size = sizeof(dma_chan);
1519 
1520         codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
1521         status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1522                         SCP_GET, NULL, 0, dma_chan, &size);
1523 
1524         if (status < 0) {
1525                 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1526                 return status;
1527         }
1528 
1529         if ((*dma_chan + 1) == 0) {
1530                 codec_dbg(codec, "no free dma channels to allocate\n");
1531                 return -EBUSY;
1532         }
1533 
1534         codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1535         codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
1536 
1537         return status;
1538 }
1539 
1540 /*
1541  * Free a DSP DMA via an SCP message
1542  */
1543 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1544 {
1545         int status = 0;
1546         unsigned int dummy = 0;
1547 
1548         codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
1549         codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1550 
1551         status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1552                            SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1553 
1554         if (status < 0) {
1555                 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1556                 return status;
1557         }
1558 
1559         codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
1560 
1561         return status;
1562 }
1563 
1564 /*
1565  * (Re)start the DSP
1566  */
1567 static int dsp_set_run_state(struct hda_codec *codec)
1568 {
1569         unsigned int dbg_ctrl_reg;
1570         unsigned int halt_state;
1571         int err;
1572 
1573         err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1574         if (err < 0)
1575                 return err;
1576 
1577         halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1578                       DSP_DBGCNTL_STATE_LOBIT;
1579 
1580         if (halt_state != 0) {
1581                 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1582                                   DSP_DBGCNTL_SS_MASK);
1583                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1584                                    dbg_ctrl_reg);
1585                 if (err < 0)
1586                         return err;
1587 
1588                 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1589                                 DSP_DBGCNTL_EXEC_MASK;
1590                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1591                                    dbg_ctrl_reg);
1592                 if (err < 0)
1593                         return err;
1594         }
1595 
1596         return 0;
1597 }
1598 
1599 /*
1600  * Reset the DSP
1601  */
1602 static int dsp_reset(struct hda_codec *codec)
1603 {
1604         unsigned int res;
1605         int retry = 20;
1606 
1607         codec_dbg(codec, "dsp_reset\n");
1608         do {
1609                 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1610                 retry--;
1611         } while (res == -EIO && retry);
1612 
1613         if (!retry) {
1614                 codec_dbg(codec, "dsp_reset timeout\n");
1615                 return -EIO;
1616         }
1617 
1618         return 0;
1619 }
1620 
1621 /*
1622  * Convert chip address to DSP address
1623  */
1624 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1625                                         bool *code, bool *yram)
1626 {
1627         *code = *yram = false;
1628 
1629         if (UC_RANGE(chip_addx, 1)) {
1630                 *code = true;
1631                 return UC_OFF(chip_addx);
1632         } else if (X_RANGE_ALL(chip_addx, 1)) {
1633                 return X_OFF(chip_addx);
1634         } else if (Y_RANGE_ALL(chip_addx, 1)) {
1635                 *yram = true;
1636                 return Y_OFF(chip_addx);
1637         }
1638 
1639         return INVALID_CHIP_ADDRESS;
1640 }
1641 
1642 /*
1643  * Check if the DSP DMA is active
1644  */
1645 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1646 {
1647         unsigned int dma_chnlstart_reg;
1648 
1649         chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1650 
1651         return ((dma_chnlstart_reg & (1 <<
1652                         (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1653 }
1654 
1655 static int dsp_dma_setup_common(struct hda_codec *codec,
1656                                 unsigned int chip_addx,
1657                                 unsigned int dma_chan,
1658                                 unsigned int port_map_mask,
1659                                 bool ovly)
1660 {
1661         int status = 0;
1662         unsigned int chnl_prop;
1663         unsigned int dsp_addx;
1664         unsigned int active;
1665         bool code, yram;
1666 
1667         codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
1668 
1669         if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1670                 codec_dbg(codec, "dma chan num invalid\n");
1671                 return -EINVAL;
1672         }
1673 
1674         if (dsp_is_dma_active(codec, dma_chan)) {
1675                 codec_dbg(codec, "dma already active\n");
1676                 return -EBUSY;
1677         }
1678 
1679         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1680 
1681         if (dsp_addx == INVALID_CHIP_ADDRESS) {
1682                 codec_dbg(codec, "invalid chip addr\n");
1683                 return -ENXIO;
1684         }
1685 
1686         chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1687         active = 0;
1688 
1689         codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
1690 
1691         if (ovly) {
1692                 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1693                                      &chnl_prop);
1694 
1695                 if (status < 0) {
1696                         codec_dbg(codec, "read CHNLPROP Reg fail\n");
1697                         return status;
1698                 }
1699                 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
1700         }
1701 
1702         if (!code)
1703                 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1704         else
1705                 chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1706 
1707         chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1708 
1709         status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1710         if (status < 0) {
1711                 codec_dbg(codec, "write CHNLPROP Reg fail\n");
1712                 return status;
1713         }
1714         codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
1715 
1716         if (ovly) {
1717                 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1718                                      &active);
1719 
1720                 if (status < 0) {
1721                         codec_dbg(codec, "read ACTIVE Reg fail\n");
1722                         return status;
1723                 }
1724                 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
1725         }
1726 
1727         active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1728                 DSPDMAC_ACTIVE_AAR_MASK;
1729 
1730         status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1731         if (status < 0) {
1732                 codec_dbg(codec, "write ACTIVE Reg fail\n");
1733                 return status;
1734         }
1735 
1736         codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
1737 
1738         status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1739                               port_map_mask);
1740         if (status < 0) {
1741                 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
1742                 return status;
1743         }
1744         codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
1745 
1746         status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1747                         DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1748         if (status < 0) {
1749                 codec_dbg(codec, "write IRQCNT Reg fail\n");
1750                 return status;
1751         }
1752         codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
1753 
1754         codec_dbg(codec,
1755                    "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1756                    "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1757                    chip_addx, dsp_addx, dma_chan,
1758                    port_map_mask, chnl_prop, active);
1759 
1760         codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
1761 
1762         return 0;
1763 }
1764 
1765 /*
1766  * Setup the DSP DMA per-transfer-specific registers
1767  */
1768 static int dsp_dma_setup(struct hda_codec *codec,
1769                         unsigned int chip_addx,
1770                         unsigned int count,
1771                         unsigned int dma_chan)
1772 {
1773         int status = 0;
1774         bool code, yram;
1775         unsigned int dsp_addx;
1776         unsigned int addr_field;
1777         unsigned int incr_field;
1778         unsigned int base_cnt;
1779         unsigned int cur_cnt;
1780         unsigned int dma_cfg = 0;
1781         unsigned int adr_ofs = 0;
1782         unsigned int xfr_cnt = 0;
1783         const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1784                                                 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1785 
1786         codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
1787 
1788         if (count > max_dma_count) {
1789                 codec_dbg(codec, "count too big\n");
1790                 return -EINVAL;
1791         }
1792 
1793         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1794         if (dsp_addx == INVALID_CHIP_ADDRESS) {
1795                 codec_dbg(codec, "invalid chip addr\n");
1796                 return -ENXIO;
1797         }
1798 
1799         codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
1800 
1801         addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1802         incr_field   = 0;
1803 
1804         if (!code) {
1805                 addr_field <<= 1;
1806                 if (yram)
1807                         addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1808 
1809                 incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1810         }
1811 
1812         dma_cfg = addr_field + incr_field;
1813         status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1814                                 dma_cfg);
1815         if (status < 0) {
1816                 codec_dbg(codec, "write DMACFG Reg fail\n");
1817                 return status;
1818         }
1819         codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
1820 
1821         adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1822                                                         (code ? 0 : 1));
1823 
1824         status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1825                                 adr_ofs);
1826         if (status < 0) {
1827                 codec_dbg(codec, "write DSPADROFS Reg fail\n");
1828                 return status;
1829         }
1830         codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
1831 
1832         base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1833 
1834         cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1835 
1836         xfr_cnt = base_cnt | cur_cnt;
1837 
1838         status = chipio_write(codec,
1839                                 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1840         if (status < 0) {
1841                 codec_dbg(codec, "write XFRCNT Reg fail\n");
1842                 return status;
1843         }
1844         codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
1845 
1846         codec_dbg(codec,
1847                    "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1848                    "ADROFS=0x%x, XFRCNT=0x%x\n",
1849                    chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1850 
1851         codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
1852 
1853         return 0;
1854 }
1855 
1856 /*
1857  * Start the DSP DMA
1858  */
1859 static int dsp_dma_start(struct hda_codec *codec,
1860                          unsigned int dma_chan, bool ovly)
1861 {
1862         unsigned int reg = 0;
1863         int status = 0;
1864 
1865         codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
1866 
1867         if (ovly) {
1868                 status = chipio_read(codec,
1869                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1870 
1871                 if (status < 0) {
1872                         codec_dbg(codec, "read CHNLSTART reg fail\n");
1873                         return status;
1874                 }
1875                 codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
1876 
1877                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1878                                 DSPDMAC_CHNLSTART_DIS_MASK);
1879         }
1880 
1881         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1882                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1883         if (status < 0) {
1884                 codec_dbg(codec, "write CHNLSTART reg fail\n");
1885                 return status;
1886         }
1887         codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
1888 
1889         return status;
1890 }
1891 
1892 /*
1893  * Stop the DSP DMA
1894  */
1895 static int dsp_dma_stop(struct hda_codec *codec,
1896                         unsigned int dma_chan, bool ovly)
1897 {
1898         unsigned int reg = 0;
1899         int status = 0;
1900 
1901         codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
1902 
1903         if (ovly) {
1904                 status = chipio_read(codec,
1905                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1906 
1907                 if (status < 0) {
1908                         codec_dbg(codec, "read CHNLSTART reg fail\n");
1909                         return status;
1910                 }
1911                 codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
1912                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1913                                 DSPDMAC_CHNLSTART_DIS_MASK);
1914         }
1915 
1916         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1917                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1918         if (status < 0) {
1919                 codec_dbg(codec, "write CHNLSTART reg fail\n");
1920                 return status;
1921         }
1922         codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
1923 
1924         return status;
1925 }
1926 
1927 /**
1928  * Allocate router ports
1929  *
1930  * @codec: the HDA codec
1931  * @num_chans: number of channels in the stream
1932  * @ports_per_channel: number of ports per channel
1933  * @start_device: start device
1934  * @port_map: pointer to the port list to hold the allocated ports
1935  *
1936  * Returns zero or a negative error code.
1937  */
1938 static int dsp_allocate_router_ports(struct hda_codec *codec,
1939                                      unsigned int num_chans,
1940                                      unsigned int ports_per_channel,
1941                                      unsigned int start_device,
1942                                      unsigned int *port_map)
1943 {
1944         int status = 0;
1945         int res;
1946         u8 val;
1947 
1948         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1949         if (status < 0)
1950                 return status;
1951 
1952         val = start_device << 6;
1953         val |= (ports_per_channel - 1) << 4;
1954         val |= num_chans - 1;
1955 
1956         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1957                             VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1958                             val);
1959 
1960         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1961                             VENDOR_CHIPIO_PORT_ALLOC_SET,
1962                             MEM_CONNID_DSP);
1963 
1964         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1965         if (status < 0)
1966                 return status;
1967 
1968         res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1969                                 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1970 
1971         *port_map = res;
1972 
1973         return (res < 0) ? res : 0;
1974 }
1975 
1976 /*
1977  * Free router ports
1978  */
1979 static int dsp_free_router_ports(struct hda_codec *codec)
1980 {
1981         int status = 0;
1982 
1983         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1984         if (status < 0)
1985                 return status;
1986 
1987         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1988                             VENDOR_CHIPIO_PORT_FREE_SET,
1989                             MEM_CONNID_DSP);
1990 
1991         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1992 
1993         return status;
1994 }
1995 
1996 /*
1997  * Allocate DSP ports for the download stream
1998  */
1999 static int dsp_allocate_ports(struct hda_codec *codec,
2000                         unsigned int num_chans,
2001                         unsigned int rate_multi, unsigned int *port_map)
2002 {
2003         int status;
2004 
2005         codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
2006 
2007         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2008                 codec_dbg(codec, "bad rate multiple\n");
2009                 return -EINVAL;
2010         }
2011 
2012         status = dsp_allocate_router_ports(codec, num_chans,
2013                                            rate_multi, 0, port_map);
2014 
2015         codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2016 
2017         return status;
2018 }
2019 
2020 static int dsp_allocate_ports_format(struct hda_codec *codec,
2021                         const unsigned short fmt,
2022                         unsigned int *port_map)
2023 {
2024         int status;
2025         unsigned int num_chans;
2026 
2027         unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2028         unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2029         unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2030 
2031         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2032                 codec_dbg(codec, "bad rate multiple\n");
2033                 return -EINVAL;
2034         }
2035 
2036         num_chans = get_hdafmt_chs(fmt) + 1;
2037 
2038         status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2039 
2040         return status;
2041 }
2042 
2043 /*
2044  * free DSP ports
2045  */
2046 static int dsp_free_ports(struct hda_codec *codec)
2047 {
2048         int status;
2049 
2050         codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2051 
2052         status = dsp_free_router_ports(codec);
2053         if (status < 0) {
2054                 codec_dbg(codec, "free router ports fail\n");
2055                 return status;
2056         }
2057         codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2058 
2059         return status;
2060 }
2061 
2062 /*
2063  *  HDA DMA engine stuffs for DSP code download
2064  */
2065 struct dma_engine {
2066         struct hda_codec *codec;
2067         unsigned short m_converter_format;
2068         struct snd_dma_buffer *dmab;
2069         unsigned int buf_size;
2070 };
2071 
2072 
2073 enum dma_state {
2074         DMA_STATE_STOP  = 0,
2075         DMA_STATE_RUN   = 1
2076 };
2077 
2078 static int dma_convert_to_hda_format(struct hda_codec *codec,
2079                 unsigned int sample_rate,
2080                 unsigned short channels,
2081                 unsigned short *hda_format)
2082 {
2083         unsigned int format_val;
2084 
2085         format_val = snd_hdac_calc_stream_format(sample_rate,
2086                                 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2087 
2088         if (hda_format)
2089                 *hda_format = (unsigned short)format_val;
2090 
2091         return 0;
2092 }
2093 
2094 /*
2095  *  Reset DMA for DSP download
2096  */
2097 static int dma_reset(struct dma_engine *dma)
2098 {
2099         struct hda_codec *codec = dma->codec;
2100         struct ca0132_spec *spec = codec->spec;
2101         int status;
2102 
2103         if (dma->dmab->area)
2104                 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2105 
2106         status = snd_hda_codec_load_dsp_prepare(codec,
2107                         dma->m_converter_format,
2108                         dma->buf_size,
2109                         dma->dmab);
2110         if (status < 0)
2111                 return status;
2112         spec->dsp_stream_id = status;
2113         return 0;
2114 }
2115 
2116 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2117 {
2118         bool cmd;
2119 
2120         switch (state) {
2121         case DMA_STATE_STOP:
2122                 cmd = false;
2123                 break;
2124         case DMA_STATE_RUN:
2125                 cmd = true;
2126                 break;
2127         default:
2128                 return 0;
2129         }
2130 
2131         snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2132         return 0;
2133 }
2134 
2135 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2136 {
2137         return dma->dmab->bytes;
2138 }
2139 
2140 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2141 {
2142         return dma->dmab->area;
2143 }
2144 
2145 static int dma_xfer(struct dma_engine *dma,
2146                 const unsigned int *data,
2147                 unsigned int count)
2148 {
2149         memcpy(dma->dmab->area, data, count);
2150         return 0;
2151 }
2152 
2153 static void dma_get_converter_format(
2154                 struct dma_engine *dma,
2155                 unsigned short *format)
2156 {
2157         if (format)
2158                 *format = dma->m_converter_format;
2159 }
2160 
2161 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2162 {
2163         struct ca0132_spec *spec = dma->codec->spec;
2164 
2165         return spec->dsp_stream_id;
2166 }
2167 
2168 struct dsp_image_seg {
2169         u32 magic;
2170         u32 chip_addr;
2171         u32 count;
2172         u32 data[0];
2173 };
2174 
2175 static const u32 g_magic_value = 0x4c46584d;
2176 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2177 
2178 static bool is_valid(const struct dsp_image_seg *p)
2179 {
2180         return p->magic == g_magic_value;
2181 }
2182 
2183 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2184 {
2185         return g_chip_addr_magic_value == p->chip_addr;
2186 }
2187 
2188 static bool is_last(const struct dsp_image_seg *p)
2189 {
2190         return p->count == 0;
2191 }
2192 
2193 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2194 {
2195         return sizeof(*p) + p->count*sizeof(u32);
2196 }
2197 
2198 static const struct dsp_image_seg *get_next_seg_ptr(
2199                                 const struct dsp_image_seg *p)
2200 {
2201         return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2202 }
2203 
2204 /*
2205  * CA0132 chip DSP transfer stuffs.  For DSP download.
2206  */
2207 #define INVALID_DMA_CHANNEL (~0U)
2208 
2209 /*
2210  * Program a list of address/data pairs via the ChipIO widget.
2211  * The segment data is in the format of successive pairs of words.
2212  * These are repeated as indicated by the segment's count field.
2213  */
2214 static int dspxfr_hci_write(struct hda_codec *codec,
2215                         const struct dsp_image_seg *fls)
2216 {
2217         int status;
2218         const u32 *data;
2219         unsigned int count;
2220 
2221         if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2222                 codec_dbg(codec, "hci_write invalid params\n");
2223                 return -EINVAL;
2224         }
2225 
2226         count = fls->count;
2227         data = (u32 *)(fls->data);
2228         while (count >= 2) {
2229                 status = chipio_write(codec, data[0], data[1]);
2230                 if (status < 0) {
2231                         codec_dbg(codec, "hci_write chipio failed\n");
2232                         return status;
2233                 }
2234                 count -= 2;
2235                 data  += 2;
2236         }
2237         return 0;
2238 }
2239 
2240 /**
2241  * Write a block of data into DSP code or data RAM using pre-allocated
2242  * DMA engine.
2243  *
2244  * @codec: the HDA codec
2245  * @fls: pointer to a fast load image
2246  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2247  *         no relocation
2248  * @dma_engine: pointer to DMA engine to be used for DSP download
2249  * @dma_chan: The number of DMA channels used for DSP download
2250  * @port_map_mask: port mapping
2251  * @ovly: TRUE if overlay format is required
2252  *
2253  * Returns zero or a negative error code.
2254  */
2255 static int dspxfr_one_seg(struct hda_codec *codec,
2256                         const struct dsp_image_seg *fls,
2257                         unsigned int reloc,
2258                         struct dma_engine *dma_engine,
2259                         unsigned int dma_chan,
2260                         unsigned int port_map_mask,
2261                         bool ovly)
2262 {
2263         int status = 0;
2264         bool comm_dma_setup_done = false;
2265         const unsigned int *data;
2266         unsigned int chip_addx;
2267         unsigned int words_to_write;
2268         unsigned int buffer_size_words;
2269         unsigned char *buffer_addx;
2270         unsigned short hda_format;
2271         unsigned int sample_rate_div;
2272         unsigned int sample_rate_mul;
2273         unsigned int num_chans;
2274         unsigned int hda_frame_size_words;
2275         unsigned int remainder_words;
2276         const u32 *data_remainder;
2277         u32 chip_addx_remainder;
2278         unsigned int run_size_words;
2279         const struct dsp_image_seg *hci_write = NULL;
2280         unsigned long timeout;
2281         bool dma_active;
2282 
2283         if (fls == NULL)
2284                 return -EINVAL;
2285         if (is_hci_prog_list_seg(fls)) {
2286                 hci_write = fls;
2287                 fls = get_next_seg_ptr(fls);
2288         }
2289 
2290         if (hci_write && (!fls || is_last(fls))) {
2291                 codec_dbg(codec, "hci_write\n");
2292                 return dspxfr_hci_write(codec, hci_write);
2293         }
2294 
2295         if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2296                 codec_dbg(codec, "Invalid Params\n");
2297                 return -EINVAL;
2298         }
2299 
2300         data = fls->data;
2301         chip_addx = fls->chip_addr,
2302         words_to_write = fls->count;
2303 
2304         if (!words_to_write)
2305                 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2306         if (reloc)
2307                 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2308 
2309         if (!UC_RANGE(chip_addx, words_to_write) &&
2310             !X_RANGE_ALL(chip_addx, words_to_write) &&
2311             !Y_RANGE_ALL(chip_addx, words_to_write)) {
2312                 codec_dbg(codec, "Invalid chip_addx Params\n");
2313                 return -EINVAL;
2314         }
2315 
2316         buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2317                                         sizeof(u32);
2318 
2319         buffer_addx = dma_get_buffer_addr(dma_engine);
2320 
2321         if (buffer_addx == NULL) {
2322                 codec_dbg(codec, "dma_engine buffer NULL\n");
2323                 return -EINVAL;
2324         }
2325 
2326         dma_get_converter_format(dma_engine, &hda_format);
2327         sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2328         sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2329         num_chans = get_hdafmt_chs(hda_format) + 1;
2330 
2331         hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2332                         (num_chans * sample_rate_mul / sample_rate_div));
2333 
2334         if (hda_frame_size_words == 0) {
2335                 codec_dbg(codec, "frmsz zero\n");
2336                 return -EINVAL;
2337         }
2338 
2339         buffer_size_words = min(buffer_size_words,
2340                                 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2341                                 65536 : 32768));
2342         buffer_size_words -= buffer_size_words % hda_frame_size_words;
2343         codec_dbg(codec,
2344                    "chpadr=0x%08x frmsz=%u nchan=%u "
2345                    "rate_mul=%u div=%u bufsz=%u\n",
2346                    chip_addx, hda_frame_size_words, num_chans,
2347                    sample_rate_mul, sample_rate_div, buffer_size_words);
2348 
2349         if (buffer_size_words < hda_frame_size_words) {
2350                 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2351                 return -EINVAL;
2352         }
2353 
2354         remainder_words = words_to_write % hda_frame_size_words;
2355         data_remainder = data;
2356         chip_addx_remainder = chip_addx;
2357 
2358         data += remainder_words;
2359         chip_addx += remainder_words*sizeof(u32);
2360         words_to_write -= remainder_words;
2361 
2362         while (words_to_write != 0) {
2363                 run_size_words = min(buffer_size_words, words_to_write);
2364                 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2365                             words_to_write, run_size_words, remainder_words);
2366                 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2367                 if (!comm_dma_setup_done) {
2368                         status = dsp_dma_stop(codec, dma_chan, ovly);
2369                         if (status < 0)
2370                                 return status;
2371                         status = dsp_dma_setup_common(codec, chip_addx,
2372                                                 dma_chan, port_map_mask, ovly);
2373                         if (status < 0)
2374                                 return status;
2375                         comm_dma_setup_done = true;
2376                 }
2377 
2378                 status = dsp_dma_setup(codec, chip_addx,
2379                                                 run_size_words, dma_chan);
2380                 if (status < 0)
2381                         return status;
2382                 status = dsp_dma_start(codec, dma_chan, ovly);
2383                 if (status < 0)
2384                         return status;
2385                 if (!dsp_is_dma_active(codec, dma_chan)) {
2386                         codec_dbg(codec, "dspxfr:DMA did not start\n");
2387                         return -EIO;
2388                 }
2389                 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2390                 if (status < 0)
2391                         return status;
2392                 if (remainder_words != 0) {
2393                         status = chipio_write_multiple(codec,
2394                                                 chip_addx_remainder,
2395                                                 data_remainder,
2396                                                 remainder_words);
2397                         if (status < 0)
2398                                 return status;
2399                         remainder_words = 0;
2400                 }
2401                 if (hci_write) {
2402                         status = dspxfr_hci_write(codec, hci_write);
2403                         if (status < 0)
2404                                 return status;
2405                         hci_write = NULL;
2406                 }
2407 
2408                 timeout = jiffies + msecs_to_jiffies(2000);
2409                 do {
2410                         dma_active = dsp_is_dma_active(codec, dma_chan);
2411                         if (!dma_active)
2412                                 break;
2413                         msleep(20);
2414                 } while (time_before(jiffies, timeout));
2415                 if (dma_active)
2416                         break;
2417 
2418                 codec_dbg(codec, "+++++ DMA complete\n");
2419                 dma_set_state(dma_engine, DMA_STATE_STOP);
2420                 status = dma_reset(dma_engine);
2421 
2422                 if (status < 0)
2423                         return status;
2424 
2425                 data += run_size_words;
2426                 chip_addx += run_size_words*sizeof(u32);
2427                 words_to_write -= run_size_words;
2428         }
2429 
2430         if (remainder_words != 0) {
2431                 status = chipio_write_multiple(codec, chip_addx_remainder,
2432                                         data_remainder, remainder_words);
2433         }
2434 
2435         return status;
2436 }
2437 
2438 /**
2439  * Write the entire DSP image of a DSP code/data overlay to DSP memories
2440  *
2441  * @codec: the HDA codec
2442  * @fls_data: pointer to a fast load image
2443  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2444  *         no relocation
2445  * @sample_rate: sampling rate of the stream used for DSP download
2446  * @channels: channels of the stream used for DSP download
2447  * @ovly: TRUE if overlay format is required
2448  *
2449  * Returns zero or a negative error code.
2450  */
2451 static int dspxfr_image(struct hda_codec *codec,
2452                         const struct dsp_image_seg *fls_data,
2453                         unsigned int reloc,
2454                         unsigned int sample_rate,
2455                         unsigned short channels,
2456                         bool ovly)
2457 {
2458         struct ca0132_spec *spec = codec->spec;
2459         int status;
2460         unsigned short hda_format = 0;
2461         unsigned int response;
2462         unsigned char stream_id = 0;
2463         struct dma_engine *dma_engine;
2464         unsigned int dma_chan;
2465         unsigned int port_map_mask;
2466 
2467         if (fls_data == NULL)
2468                 return -EINVAL;
2469 
2470         dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2471         if (!dma_engine)
2472                 return -ENOMEM;
2473 
2474         dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2475         if (!dma_engine->dmab) {
2476                 kfree(dma_engine);
2477                 return -ENOMEM;
2478         }
2479 
2480         dma_engine->codec = codec;
2481         dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2482         dma_engine->m_converter_format = hda_format;
2483         dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2484                         DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2485 
2486         dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2487 
2488         status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2489                                         hda_format, &response);
2490 
2491         if (status < 0) {
2492                 codec_dbg(codec, "set converter format fail\n");
2493                 goto exit;
2494         }
2495 
2496         status = snd_hda_codec_load_dsp_prepare(codec,
2497                                 dma_engine->m_converter_format,
2498                                 dma_engine->buf_size,
2499                                 dma_engine->dmab);
2500         if (status < 0)
2501                 goto exit;
2502         spec->dsp_stream_id = status;
2503 
2504         if (ovly) {
2505                 status = dspio_alloc_dma_chan(codec, &dma_chan);
2506                 if (status < 0) {
2507                         codec_dbg(codec, "alloc dmachan fail\n");
2508                         dma_chan = INVALID_DMA_CHANNEL;
2509                         goto exit;
2510                 }
2511         }
2512 
2513         port_map_mask = 0;
2514         status = dsp_allocate_ports_format(codec, hda_format,
2515                                         &port_map_mask);
2516         if (status < 0) {
2517                 codec_dbg(codec, "alloc ports fail\n");
2518                 goto exit;
2519         }
2520 
2521         stream_id = dma_get_stream_id(dma_engine);
2522         status = codec_set_converter_stream_channel(codec,
2523                         WIDGET_CHIP_CTRL, stream_id, 0, &response);
2524         if (status < 0) {
2525                 codec_dbg(codec, "set stream chan fail\n");
2526                 goto exit;
2527         }
2528 
2529         while ((fls_data != NULL) && !is_last(fls_data)) {
2530                 if (!is_valid(fls_data)) {
2531                         codec_dbg(codec, "FLS check fail\n");
2532                         status = -EINVAL;
2533                         goto exit;
2534                 }
2535                 status = dspxfr_one_seg(codec, fls_data, reloc,
2536                                         dma_engine, dma_chan,
2537                                         port_map_mask, ovly);
2538                 if (status < 0)
2539                         break;
2540 
2541                 if (is_hci_prog_list_seg(fls_data))
2542                         fls_data = get_next_seg_ptr(fls_data);
2543 
2544                 if ((fls_data != NULL) && !is_last(fls_data))
2545                         fls_data = get_next_seg_ptr(fls_data);
2546         }
2547 
2548         if (port_map_mask != 0)
2549                 status = dsp_free_ports(codec);
2550 
2551         if (status < 0)
2552                 goto exit;
2553 
2554         status = codec_set_converter_stream_channel(codec,
2555                                 WIDGET_CHIP_CTRL, 0, 0, &response);
2556 
2557 exit:
2558         if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2559                 dspio_free_dma_chan(codec, dma_chan);
2560 
2561         if (dma_engine->dmab->area)
2562                 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2563         kfree(dma_engine->dmab);
2564         kfree(dma_engine);
2565 
2566         return status;
2567 }
2568 
2569 /*
2570  * CA0132 DSP download stuffs.
2571  */
2572 static void dspload_post_setup(struct hda_codec *codec)
2573 {
2574         codec_dbg(codec, "---- dspload_post_setup ------\n");
2575 
2576         /*set DSP speaker to 2.0 configuration*/
2577         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2578         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2579 
2580         /*update write pointer*/
2581         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2582 }
2583 
2584 /**
2585  * dspload_image - Download DSP from a DSP Image Fast Load structure.
2586  *
2587  * @codec: the HDA codec
2588  * @fls: pointer to a fast load image
2589  * @ovly: TRUE if overlay format is required
2590  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2591  *         no relocation
2592  * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2593  * @router_chans: number of audio router channels to be allocated (0 means use
2594  *                internal defaults; max is 32)
2595  *
2596  * Download DSP from a DSP Image Fast Load structure. This structure is a
2597  * linear, non-constant sized element array of structures, each of which
2598  * contain the count of the data to be loaded, the data itself, and the
2599  * corresponding starting chip address of the starting data location.
2600  * Returns zero or a negative error code.
2601  */
2602 static int dspload_image(struct hda_codec *codec,
2603                         const struct dsp_image_seg *fls,
2604                         bool ovly,
2605                         unsigned int reloc,
2606                         bool autostart,
2607                         int router_chans)
2608 {
2609         int status = 0;
2610         unsigned int sample_rate;
2611         unsigned short channels;
2612 
2613         codec_dbg(codec, "---- dspload_image begin ------\n");
2614         if (router_chans == 0) {
2615                 if (!ovly)
2616                         router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2617                 else
2618                         router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2619         }
2620 
2621         sample_rate = 48000;
2622         channels = (unsigned short)router_chans;
2623 
2624         while (channels > 16) {
2625                 sample_rate *= 2;
2626                 channels /= 2;
2627         }
2628 
2629         do {
2630                 codec_dbg(codec, "Ready to program DMA\n");
2631                 if (!ovly)
2632                         status = dsp_reset(codec);
2633 
2634                 if (status < 0)
2635                         break;
2636 
2637                 codec_dbg(codec, "dsp_reset() complete\n");
2638                 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2639                                       ovly);
2640 
2641                 if (status < 0)
2642                         break;
2643 
2644                 codec_dbg(codec, "dspxfr_image() complete\n");
2645                 if (autostart && !ovly) {
2646                         dspload_post_setup(codec);
2647                         status = dsp_set_run_state(codec);
2648                 }
2649 
2650                 codec_dbg(codec, "LOAD FINISHED\n");
2651         } while (0);
2652 
2653         return status;
2654 }
2655 
2656 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
2657 static bool dspload_is_loaded(struct hda_codec *codec)
2658 {
2659         unsigned int data = 0;
2660         int status = 0;
2661 
2662         status = chipio_read(codec, 0x40004, &data);
2663         if ((status < 0) || (data != 1))
2664                 return false;
2665 
2666         return true;
2667 }
2668 #else
2669 #define dspload_is_loaded(codec)        false
2670 #endif
2671 
2672 static bool dspload_wait_loaded(struct hda_codec *codec)
2673 {
2674         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
2675 
2676         do {
2677                 if (dspload_is_loaded(codec)) {
2678                         codec_info(codec, "ca0132 DSP downloaded and running\n");
2679                         return true;
2680                 }
2681                 msleep(20);
2682         } while (time_before(jiffies, timeout));
2683 
2684         codec_err(codec, "ca0132 failed to download DSP\n");
2685         return false;
2686 }
2687 
2688 /*
2689  * PCM callbacks
2690  */
2691 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2692                         struct hda_codec *codec,
2693                         unsigned int stream_tag,
2694                         unsigned int format,
2695                         struct snd_pcm_substream *substream)
2696 {
2697         struct ca0132_spec *spec = codec->spec;
2698 
2699         snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2700 
2701         return 0;
2702 }
2703 
2704 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2705                         struct hda_codec *codec,
2706                         struct snd_pcm_substream *substream)
2707 {
2708         struct ca0132_spec *spec = codec->spec;
2709 
2710         if (spec->dsp_state == DSP_DOWNLOADING)
2711                 return 0;
2712 
2713         /*If Playback effects are on, allow stream some time to flush
2714          *effects tail*/
2715         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2716                 msleep(50);
2717 
2718         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
2719 
2720         return 0;
2721 }
2722 
2723 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2724                         struct hda_codec *codec,
2725                         struct snd_pcm_substream *substream)
2726 {
2727         struct ca0132_spec *spec = codec->spec;
2728         unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2729         struct snd_pcm_runtime *runtime = substream->runtime;
2730 
2731         if (spec->dsp_state != DSP_DOWNLOADED)
2732                 return 0;
2733 
2734         /* Add latency if playback enhancement and either effect is enabled. */
2735         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2736                 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2737                     (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2738                         latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2739         }
2740 
2741         /* Applying Speaker EQ adds latency as well. */
2742         if (spec->cur_out_type == SPEAKER_OUT)
2743                 latency += DSP_SPEAKER_OUT_LATENCY;
2744 
2745         return (latency * runtime->rate) / 1000;
2746 }
2747 
2748 /*
2749  * Digital out
2750  */
2751 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2752                                         struct hda_codec *codec,
2753                                         struct snd_pcm_substream *substream)
2754 {
2755         struct ca0132_spec *spec = codec->spec;
2756         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2757 }
2758 
2759 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2760                         struct hda_codec *codec,
2761                         unsigned int stream_tag,
2762                         unsigned int format,
2763                         struct snd_pcm_substream *substream)
2764 {
2765         struct ca0132_spec *spec = codec->spec;
2766         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2767                                              stream_tag, format, substream);
2768 }
2769 
2770 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2771                         struct hda_codec *codec,
2772                         struct snd_pcm_substream *substream)
2773 {
2774         struct ca0132_spec *spec = codec->spec;
2775         return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
2776 }
2777 
2778 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2779                                          struct hda_codec *codec,
2780                                          struct snd_pcm_substream *substream)
2781 {
2782         struct ca0132_spec *spec = codec->spec;
2783         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2784 }
2785 
2786 /*
2787  * Analog capture
2788  */
2789 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2790                                         struct hda_codec *codec,
2791                                         unsigned int stream_tag,
2792                                         unsigned int format,
2793                                         struct snd_pcm_substream *substream)
2794 {
2795         snd_hda_codec_setup_stream(codec, hinfo->nid,
2796                                    stream_tag, 0, format);
2797 
2798         return 0;
2799 }
2800 
2801 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2802                         struct hda_codec *codec,
2803                         struct snd_pcm_substream *substream)
2804 {
2805         struct ca0132_spec *spec = codec->spec;
2806 
2807         if (spec->dsp_state == DSP_DOWNLOADING)
2808                 return 0;
2809 
2810         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2811         return 0;
2812 }
2813 
2814 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2815                         struct hda_codec *codec,
2816                         struct snd_pcm_substream *substream)
2817 {
2818         struct ca0132_spec *spec = codec->spec;
2819         unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2820         struct snd_pcm_runtime *runtime = substream->runtime;
2821 
2822         if (spec->dsp_state != DSP_DOWNLOADED)
2823                 return 0;
2824 
2825         if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2826                 latency += DSP_CRYSTAL_VOICE_LATENCY;
2827 
2828         return (latency * runtime->rate) / 1000;
2829 }
2830 
2831 /*
2832  * Controls stuffs.
2833  */
2834 
2835 /*
2836  * Mixer controls helpers.
2837  */
2838 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2839         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2840           .name = xname, \
2841           .subdevice = HDA_SUBDEV_AMP_FLAG, \
2842           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2843                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2844                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2845           .info = ca0132_volume_info, \
2846           .get = ca0132_volume_get, \
2847           .put = ca0132_volume_put, \
2848           .tlv = { .c = ca0132_volume_tlv }, \
2849           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2850 
2851 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2852         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2853           .name = xname, \
2854           .subdevice = HDA_SUBDEV_AMP_FLAG, \
2855           .info = snd_hda_mixer_amp_switch_info, \
2856           .get = ca0132_switch_get, \
2857           .put = ca0132_switch_put, \
2858           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2859 
2860 /* stereo */
2861 #define CA0132_CODEC_VOL(xname, nid, dir) \
2862         CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2863 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2864         CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2865 
2866 /* The followings are for tuning of products */
2867 #ifdef ENABLE_TUNING_CONTROLS
2868 
2869 static unsigned int voice_focus_vals_lookup[] = {
2870 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2871 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2872 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2873 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2874 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2875 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2876 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2877 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2878 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2879 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2880 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2881 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2882 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2883 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2884 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2885 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2886 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2887 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2888 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2889 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2890 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2891 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2892 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2893 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2894 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2895 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2896 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2897 };
2898 
2899 static unsigned int mic_svm_vals_lookup[] = {
2900 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2901 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2902 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2903 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2904 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2905 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2906 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2907 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2908 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2909 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2910 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2911 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2912 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2913 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2914 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2915 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2916 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2917 };
2918 
2919 static unsigned int equalizer_vals_lookup[] = {
2920 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2921 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2922 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2923 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2924 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2925 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2926 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2927 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2928 0x41C00000
2929 };
2930 
2931 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2932                           unsigned int *lookup, int idx)
2933 {
2934         int i = 0;
2935 
2936         for (i = 0; i < TUNING_CTLS_COUNT; i++)
2937                 if (nid == ca0132_tuning_ctls[i].nid)
2938                         break;
2939 
2940         snd_hda_power_up(codec);
2941         dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2942                         ca0132_tuning_ctls[i].req,
2943                         &(lookup[idx]), sizeof(unsigned int));
2944         snd_hda_power_down(codec);
2945 
2946         return 1;
2947 }
2948 
2949 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2950                           struct snd_ctl_elem_value *ucontrol)
2951 {
2952         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2953         struct ca0132_spec *spec = codec->spec;
2954         hda_nid_t nid = get_amp_nid(kcontrol);
2955         long *valp = ucontrol->value.integer.value;
2956         int idx = nid - TUNING_CTL_START_NID;
2957 
2958         *valp = spec->cur_ctl_vals[idx];
2959         return 0;
2960 }
2961 
2962 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2963                               struct snd_ctl_elem_info *uinfo)
2964 {
2965         int chs = get_amp_channels(kcontrol);
2966         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2967         uinfo->count = chs == 3 ? 2 : 1;
2968         uinfo->value.integer.min = 20;
2969         uinfo->value.integer.max = 180;
2970         uinfo->value.integer.step = 1;
2971 
2972         return 0;
2973 }
2974 
2975 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2976                                 struct snd_ctl_elem_value *ucontrol)
2977 {
2978         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2979         struct ca0132_spec *spec = codec->spec;
2980         hda_nid_t nid = get_amp_nid(kcontrol);
2981         long *valp = ucontrol->value.integer.value;
2982         int idx;
2983 
2984         idx = nid - TUNING_CTL_START_NID;
2985         /* any change? */
2986         if (spec->cur_ctl_vals[idx] == *valp)
2987                 return 0;
2988 
2989         spec->cur_ctl_vals[idx] = *valp;
2990 
2991         idx = *valp - 20;
2992         tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2993 
2994         return 1;
2995 }
2996 
2997 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2998                               struct snd_ctl_elem_info *uinfo)
2999 {
3000         int chs = get_amp_channels(kcontrol);
3001         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3002         uinfo->count = chs == 3 ? 2 : 1;
3003         uinfo->value.integer.min = 0;
3004         uinfo->value.integer.max = 100;
3005         uinfo->value.integer.step = 1;
3006 
3007         return 0;
3008 }
3009 
3010 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3011                                 struct snd_ctl_elem_value *ucontrol)
3012 {
3013         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3014         struct ca0132_spec *spec = codec->spec;
3015         hda_nid_t nid = get_amp_nid(kcontrol);
3016         long *valp = ucontrol->value.integer.value;
3017         int idx;
3018 
3019         idx = nid - TUNING_CTL_START_NID;
3020         /* any change? */
3021         if (spec->cur_ctl_vals[idx] == *valp)
3022                 return 0;
3023 
3024         spec->cur_ctl_vals[idx] = *valp;
3025 
3026         idx = *valp;
3027         tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3028 
3029         return 0;
3030 }
3031 
3032 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3033                               struct snd_ctl_elem_info *uinfo)
3034 {
3035         int chs = get_amp_channels(kcontrol);
3036         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3037         uinfo->count = chs == 3 ? 2 : 1;
3038         uinfo->value.integer.min = 0;
3039         uinfo->value.integer.max = 48;
3040         uinfo->value.integer.step = 1;
3041 
3042         return 0;
3043 }
3044 
3045 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3046                                 struct snd_ctl_elem_value *ucontrol)
3047 {
3048         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3049         struct ca0132_spec *spec = codec->spec;
3050         hda_nid_t nid = get_amp_nid(kcontrol);
3051         long *valp = ucontrol->value.integer.value;
3052         int idx;
3053 
3054         idx = nid - TUNING_CTL_START_NID;
3055         /* any change? */
3056         if (spec->cur_ctl_vals[idx] == *valp)
3057                 return 0;
3058 
3059         spec->cur_ctl_vals[idx] = *valp;
3060 
3061         idx = *valp;
3062         tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3063 
3064         return 1;
3065 }
3066 
3067 static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3068 static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3069 
3070 static int add_tuning_control(struct hda_codec *codec,
3071                                 hda_nid_t pnid, hda_nid_t nid,
3072                                 const char *name, int dir)
3073 {
3074         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3075         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3076         struct snd_kcontrol_new knew =
3077                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3078 
3079         knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3080                         SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3081         knew.tlv.c = 0;
3082         knew.tlv.p = 0;
3083         switch (pnid) {
3084         case VOICE_FOCUS:
3085                 knew.info = voice_focus_ctl_info;
3086                 knew.get = tuning_ctl_get;
3087                 knew.put = voice_focus_ctl_put;
3088                 knew.tlv.p = voice_focus_db_scale;
3089                 break;
3090         case MIC_SVM:
3091                 knew.info = mic_svm_ctl_info;
3092                 knew.get = tuning_ctl_get;
3093                 knew.put = mic_svm_ctl_put;
3094                 break;
3095         case EQUALIZER:
3096                 knew.info = equalizer_ctl_info;
3097                 knew.get = tuning_ctl_get;
3098                 knew.put = equalizer_ctl_put;
3099                 knew.tlv.p = eq_db_scale;
3100                 break;
3101         default:
3102                 return 0;
3103         }
3104         knew.private_value =
3105                 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3106         sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3107         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3108 }
3109 
3110 static int add_tuning_ctls(struct hda_codec *codec)
3111 {
3112         int i;
3113         int err;
3114 
3115         for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3116                 err = add_tuning_control(codec,
3117                                         ca0132_tuning_ctls[i].parent_nid,
3118                                         ca0132_tuning_ctls[i].nid,
3119                                         ca0132_tuning_ctls[i].name,
3120                                         ca0132_tuning_ctls[i].direct);
3121                 if (err < 0)
3122                         return err;
3123         }
3124 
3125         return 0;
3126 }
3127 
3128 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3129 {
3130         struct ca0132_spec *spec = codec->spec;
3131         int i;
3132 
3133         /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
3134         spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3135         /* SVM level defaults to 0.74. */
3136         spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3137 
3138         /* EQ defaults to 0dB. */
3139         for (i = 2; i < TUNING_CTLS_COUNT; i++)
3140                 spec->cur_ctl_vals[i] = 24;
3141 }
3142 #endif /*ENABLE_TUNING_CONTROLS*/
3143 
3144 /*
3145  * Select the active output.
3146  * If autodetect is enabled, output will be selected based on jack detection.
3147  * If jack inserted, headphone will be selected, else built-in speakers
3148  * If autodetect is disabled, output will be selected based on selection.
3149  */
3150 static int ca0132_select_out(struct hda_codec *codec)
3151 {
3152         struct ca0132_spec *spec = codec->spec;
3153         unsigned int pin_ctl;
3154         int jack_present;
3155         int auto_jack;
3156         unsigned int tmp;
3157         int err;
3158 
3159         codec_dbg(codec, "ca0132_select_out\n");
3160 
3161         snd_hda_power_up_pm(codec);
3162 
3163         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3164 
3165         if (auto_jack)
3166                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
3167         else
3168                 jack_present =
3169                         spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3170 
3171         if (jack_present)
3172                 spec->cur_out_type = HEADPHONE_OUT;
3173         else
3174                 spec->cur_out_type = SPEAKER_OUT;
3175 
3176         if (spec->cur_out_type == SPEAKER_OUT) {
3177                 codec_dbg(codec, "ca0132_select_out speaker\n");
3178                 /*speaker out config*/
3179                 tmp = FLOAT_ONE;
3180                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3181                 if (err < 0)
3182                         goto exit;
3183                 /*enable speaker EQ*/
3184                 tmp = FLOAT_ONE;
3185                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3186                 if (err < 0)
3187                         goto exit;
3188 
3189                 /* Setup EAPD */
3190                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3191                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3192                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3193                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3194                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3195                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3196                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3197                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3198 
3199                 /* disable headphone node */
3200                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3201                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3202                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3203                                     pin_ctl & ~PIN_HP);
3204                 /* enable speaker node */
3205                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3206                                              AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3207                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3208                                     pin_ctl | PIN_OUT);
3209         } else {
3210                 codec_dbg(codec, "ca0132_select_out hp\n");
3211                 /*headphone out config*/
3212                 tmp = FLOAT_ZERO;
3213                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3214                 if (err < 0)
3215                         goto exit;
3216                 /*disable speaker EQ*/
3217                 tmp = FLOAT_ZERO;
3218                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3219                 if (err < 0)
3220                         goto exit;
3221 
3222                 /* Setup EAPD */
3223                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3224                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3225                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3226                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3227                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3228                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3229                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3230                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3231 
3232                 /* disable speaker*/
3233                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3234                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3235                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3236                                     pin_ctl & ~PIN_HP);
3237                 /* enable headphone*/
3238                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3239                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3240                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3241                                     pin_ctl | PIN_HP);
3242         }
3243 
3244 exit:
3245         snd_hda_power_down_pm(codec);
3246 
3247         return err < 0 ? err : 0;
3248 }
3249 
3250 static void ca0132_unsol_hp_delayed(struct work_struct *work)
3251 {
3252         struct ca0132_spec *spec = container_of(
3253                 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
3254         struct hda_jack_tbl *jack;
3255 
3256         ca0132_select_out(spec->codec);
3257         jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
3258         if (jack) {
3259                 jack->block_report = 0;
3260                 snd_hda_jack_report_sync(spec->codec);
3261         }
3262 }
3263 
3264 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3265 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3266 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3267 
3268 /*
3269  * Select the active VIP source
3270  */
3271 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3272 {
3273         struct ca0132_spec *spec = codec->spec;
3274         unsigned int tmp;
3275 
3276         if (spec->dsp_state != DSP_DOWNLOADED)
3277                 return 0;
3278 
3279         /* if CrystalVoice if off, vipsource should be 0 */
3280         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3281             (val == 0)) {
3282                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3283                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3284                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3285                 if (spec->cur_mic_type == DIGITAL_MIC)
3286                         tmp = FLOAT_TWO;
3287                 else
3288                         tmp = FLOAT_ONE;
3289                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3290                 tmp = FLOAT_ZERO;
3291                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3292         } else {
3293                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3294                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3295                 if (spec->cur_mic_type == DIGITAL_MIC)
3296                         tmp = FLOAT_TWO;
3297                 else
3298                         tmp = FLOAT_ONE;
3299                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3300                 tmp = FLOAT_ONE;
3301                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3302                 msleep(20);
3303                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3304         }
3305 
3306         return 1;
3307 }
3308 
3309 /*
3310  * Select the active microphone.
3311  * If autodetect is enabled, mic will be selected based on jack detection.
3312  * If jack inserted, ext.mic will be selected, else built-in mic
3313  * If autodetect is disabled, mic will be selected based on selection.
3314  */
3315 static int ca0132_select_mic(struct hda_codec *codec)
3316 {
3317         struct ca0132_spec *spec = codec->spec;
3318         int jack_present;
3319         int auto_jack;
3320 
3321         codec_dbg(codec, "ca0132_select_mic\n");
3322 
3323         snd_hda_power_up_pm(codec);
3324 
3325         auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3326 
3327         if (auto_jack)
3328                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
3329         else
3330                 jack_present =
3331                         spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3332 
3333         if (jack_present)
3334                 spec->cur_mic_type = LINE_MIC_IN;
3335         else
3336                 spec->cur_mic_type = DIGITAL_MIC;
3337 
3338         if (spec->cur_mic_type == DIGITAL_MIC) {
3339                 /* enable digital Mic */
3340                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3341                 ca0132_set_dmic(codec, 1);
3342                 ca0132_mic_boost_set(codec, 0);
3343                 /* set voice focus */
3344                 ca0132_effects_set(codec, VOICE_FOCUS,
3345                                    spec->effects_switch
3346                                    [VOICE_FOCUS - EFFECT_START_NID]);
3347         } else {
3348                 /* disable digital Mic */
3349                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3350                 ca0132_set_dmic(codec, 0);
3351                 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3352                 /* disable voice focus */
3353                 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3354         }
3355 
3356         snd_hda_power_down_pm(codec);
3357 
3358         return 0;
3359 }
3360 
3361 /*
3362  * Check if VNODE settings take effect immediately.
3363  */
3364 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3365                                      hda_nid_t vnid,
3366                                      hda_nid_t *shared_nid)
3367 {
3368         struct ca0132_spec *spec = codec->spec;
3369         hda_nid_t nid;
3370 
3371         switch (vnid) {
3372         case VNID_SPK:
3373                 nid = spec->shared_out_nid;
3374                 break;
3375         case VNID_MIC:
3376                 nid = spec->shared_mic_nid;
3377                 break;
3378         default:
3379                 return false;
3380         }
3381 
3382         if (shared_nid)
3383                 *shared_nid = nid;
3384 
3385         return true;
3386 }
3387 
3388 /*
3389 * The following functions are control change helpers.
3390 * They return 0 if no changed.  Return 1 if changed.
3391 */
3392 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3393 {
3394         struct ca0132_spec *spec = codec->spec;
3395         unsigned int tmp;
3396 
3397         /* based on CrystalVoice state to enable VoiceFX. */
3398         if (enable) {
3399                 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3400                         FLOAT_ONE : FLOAT_ZERO;
3401         } else {
3402                 tmp = FLOAT_ZERO;
3403         }
3404 
3405         dspio_set_uint_param(codec, ca0132_voicefx.mid,
3406                              ca0132_voicefx.reqs[0], tmp);
3407 
3408         return 1;
3409 }
3410 
3411 /*
3412  * Set the effects parameters
3413  */
3414 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3415 {
3416         struct ca0132_spec *spec = codec->spec;
3417         unsigned int on;
3418         int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3419         int err = 0;
3420         int idx = nid - EFFECT_START_NID;
3421 
3422         if ((idx < 0) || (idx >= num_fx))
3423                 return 0; /* no changed */
3424 
3425         /* for out effect, qualify with PE */
3426         if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3427                 /* if PE if off, turn off out effects. */
3428                 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3429                         val = 0;
3430         }
3431 
3432         /* for in effect, qualify with CrystalVoice */
3433         if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3434                 /* if CrystalVoice if off, turn off in effects. */
3435                 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3436                         val = 0;
3437 
3438                 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3439                 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3440                         val = 0;
3441         }
3442 
3443         codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
3444                     nid, val);
3445 
3446         on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3447         err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3448                                    ca0132_effects[idx].reqs[0], on);
3449 
3450         if (err < 0)
3451                 return 0; /* no changed */
3452 
3453         return 1;
3454 }
3455 
3456 /*
3457  * Turn on/off Playback Enhancements
3458  */
3459 static int ca0132_pe_switch_set(struct hda_codec *codec)
3460 {
3461         struct ca0132_spec *spec = codec->spec;
3462         hda_nid_t nid;
3463         int i, ret = 0;
3464 
3465         codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
3466                     spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3467 
3468         i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3469         nid = OUT_EFFECT_START_NID;
3470         /* PE affects all out effects */
3471         for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3472                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3473 
3474         return ret;
3475 }
3476 
3477 /* Check if Mic1 is streaming, if so, stop streaming */
3478 static int stop_mic1(struct hda_codec *codec)
3479 {
3480         struct ca0132_spec *spec = codec->spec;
3481         unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3482                                                  AC_VERB_GET_CONV, 0);
3483         if (oldval != 0)
3484                 snd_hda_codec_write(codec, spec->adcs[0], 0,
3485                                     AC_VERB_SET_CHANNEL_STREAMID,
3486                                     0);
3487         return oldval;
3488 }
3489 
3490 /* Resume Mic1 streaming if it was stopped. */
3491 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3492 {
3493         struct ca0132_spec *spec = codec->spec;
3494         /* Restore the previous stream and channel */
3495         if (oldval != 0)
3496                 snd_hda_codec_write(codec, spec->adcs[0], 0,
3497                                     AC_VERB_SET_CHANNEL_STREAMID,
3498                                     oldval);
3499 }
3500 
3501 /*
3502  * Turn on/off CrystalVoice
3503  */
3504 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3505 {
3506         struct ca0132_spec *spec = codec->spec;
3507         hda_nid_t nid;
3508         int i, ret = 0;
3509         unsigned int oldval;
3510 
3511         codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
3512                     spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3513 
3514         i = IN_EFFECT_START_NID - EFFECT_START_NID;
3515         nid = IN_EFFECT_START_NID;
3516         /* CrystalVoice affects all in effects */
3517         for (; nid < IN_EFFECT_END_NID; nid++, i++)
3518                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3519 
3520         /* including VoiceFX */
3521         ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3522 
3523         /* set correct vipsource */
3524         oldval = stop_mic1(codec);
3525         ret |= ca0132_set_vipsource(codec, 1);
3526         resume_mic1(codec, oldval);
3527         return ret;
3528 }
3529 
3530 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3531 {
3532         struct ca0132_spec *spec = codec->spec;
3533         int ret = 0;
3534 
3535         if (val) /* on */
3536                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3537                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3538         else /* off */
3539                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3540                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3541 
3542         return ret;
3543 }
3544 
3545 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3546                                 struct snd_ctl_elem_value *ucontrol)
3547 {
3548         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3549         hda_nid_t nid = get_amp_nid(kcontrol);
3550         hda_nid_t shared_nid = 0;
3551         bool effective;
3552         int ret = 0;
3553         struct ca0132_spec *spec = codec->spec;
3554         int auto_jack;
3555 
3556         if (nid == VNID_HP_SEL) {
3557                 auto_jack =
3558                         spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3559                 if (!auto_jack)
3560                         ca0132_select_out(codec);
3561                 return 1;
3562         }
3563 
3564         if (nid == VNID_AMIC1_SEL) {
3565                 auto_jack =
3566                         spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3567                 if (!auto_jack)
3568                         ca0132_select_mic(codec);
3569                 return 1;
3570         }
3571 
3572         if (nid == VNID_HP_ASEL) {
3573                 ca0132_select_out(codec);
3574                 return 1;
3575         }
3576 
3577         if (nid == VNID_AMIC1_ASEL) {
3578                 ca0132_select_mic(codec);
3579                 return 1;
3580         }
3581 
3582         /* if effective conditions, then update hw immediately. */
3583         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3584         if (effective) {
3585                 int dir = get_amp_direction(kcontrol);
3586                 int ch = get_amp_channels(kcontrol);
3587                 unsigned long pval;
3588 
3589                 mutex_lock(&codec->control_mutex);
3590                 pval = kcontrol->private_value;
3591                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3592                                                                 0, dir);
3593                 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3594                 kcontrol->private_value = pval;
3595                 mutex_unlock(&codec->control_mutex);
3596         }
3597 
3598         return ret;
3599 }
3600 /* End of control change helpers. */
3601 
3602 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3603                                  struct snd_ctl_elem_info *uinfo)
3604 {
3605         unsigned int items = sizeof(ca0132_voicefx_presets)
3606                                 / sizeof(struct ct_voicefx_preset);
3607 
3608         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3609         uinfo->count = 1;
3610         uinfo->value.enumerated.items = items;
3611         if (uinfo->value.enumerated.item >= items)
3612                 uinfo->value.enumerated.item = items - 1;
3613         strcpy(uinfo->value.enumerated.name,
3614                ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3615         return 0;
3616 }
3617 
3618 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3619                                 struct snd_ctl_elem_value *ucontrol)
3620 {
3621         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3622         struct ca0132_spec *spec = codec->spec;
3623 
3624         ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3625         return 0;
3626 }
3627 
3628 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3629                                 struct snd_ctl_elem_value *ucontrol)
3630 {
3631         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3632         struct ca0132_spec *spec = codec->spec;
3633         int i, err = 0;
3634         int sel = ucontrol->value.enumerated.item[0];
3635         unsigned int items = sizeof(ca0132_voicefx_presets)
3636                                 / sizeof(struct ct_voicefx_preset);
3637 
3638         if (sel >= items)
3639                 return 0;
3640 
3641         codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
3642                     sel, ca0132_voicefx_presets[sel].name);
3643 
3644         /*
3645          * Idx 0 is default.
3646          * Default needs to qualify with CrystalVoice state.
3647          */
3648         for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3649                 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3650                                 ca0132_voicefx.reqs[i],
3651                                 ca0132_voicefx_presets[sel].vals[i]);
3652                 if (err < 0)
3653                         break;
3654         }
3655 
3656         if (err >= 0) {
3657                 spec->voicefx_val = sel;
3658                 /* enable voice fx */
3659                 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3660         }
3661 
3662         return 1;
3663 }
3664 
3665 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3666                                 struct snd_ctl_elem_value *ucontrol)
3667 {
3668         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3669         struct ca0132_spec *spec = codec->spec;
3670         hda_nid_t nid = get_amp_nid(kcontrol);
3671         int ch = get_amp_channels(kcontrol);
3672         long *valp = ucontrol->value.integer.value;
3673 
3674         /* vnode */
3675         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3676                 if (ch & 1) {
3677                         *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3678                         valp++;
3679                 }
3680                 if (ch & 2) {
3681                         *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3682                         valp++;
3683                 }
3684                 return 0;
3685         }
3686 
3687         /* effects, include PE and CrystalVoice */
3688         if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3689                 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3690                 return 0;
3691         }
3692 
3693         /* mic boost */
3694         if (nid == spec->input_pins[0]) {
3695                 *valp = spec->cur_mic_boost;
3696                 return 0;
3697         }
3698 
3699         return 0;
3700 }
3701 
3702 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3703                              struct snd_ctl_elem_value *ucontrol)
3704 {
3705         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3706         struct ca0132_spec *spec = codec->spec;
3707         hda_nid_t nid = get_amp_nid(kcontrol);
3708         int ch = get_amp_channels(kcontrol);
3709         long *valp = ucontrol->value.integer.value;
3710         int changed = 1;
3711 
3712         codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
3713                     nid, *valp);
3714 
3715         snd_hda_power_up(codec);
3716         /* vnode */
3717         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3718                 if (ch & 1) {
3719                         spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3720                         valp++;
3721                 }
3722                 if (ch & 2) {
3723                         spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3724                         valp++;
3725                 }
3726                 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3727                 goto exit;
3728         }
3729 
3730         /* PE */
3731         if (nid == PLAY_ENHANCEMENT) {
3732                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3733                 changed = ca0132_pe_switch_set(codec);
3734                 goto exit;
3735         }
3736 
3737         /* CrystalVoice */
3738         if (nid == CRYSTAL_VOICE) {
3739                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3740                 changed = ca0132_cvoice_switch_set(codec);
3741                 goto exit;
3742         }
3743 
3744         /* out and in effects */
3745         if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3746             ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3747                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3748                 changed = ca0132_effects_set(codec, nid, *valp);
3749                 goto exit;
3750         }
3751 
3752         /* mic boost */
3753         if (nid == spec->input_pins[0]) {
3754                 spec->cur_mic_boost = *valp;
3755 
3756                 /* Mic boost does not apply to Digital Mic */
3757                 if (spec->cur_mic_type != DIGITAL_MIC)
3758                         changed = ca0132_mic_boost_set(codec, *valp);
3759                 goto exit;
3760         }
3761 
3762 exit:
3763         snd_hda_power_down(codec);
3764         return changed;
3765 }
3766 
3767 /*
3768  * Volume related
3769  */
3770 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3771                               struct snd_ctl_elem_info *uinfo)
3772 {
3773         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3774         struct ca0132_spec *spec = codec->spec;
3775         hda_nid_t nid = get_amp_nid(kcontrol);
3776         int ch = get_amp_channels(kcontrol);
3777         int dir = get_amp_direction(kcontrol);
3778         unsigned long pval;
3779         int err;
3780 
3781         switch (nid) {
3782         case VNID_SPK:
3783                 /* follow shared_out info */
3784                 nid = spec->shared_out_nid;
3785                 mutex_lock(&codec->control_mutex);
3786                 pval = kcontrol->private_value;
3787                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3788                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3789                 kcontrol->private_value = pval;
3790                 mutex_unlock(&codec->control_mutex);
3791                 break;
3792         case VNID_MIC:
3793                 /* follow shared_mic info */
3794                 nid = spec->shared_mic_nid;
3795                 mutex_lock(&codec->control_mutex);
3796                 pval = kcontrol->private_value;
3797                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3798                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3799                 kcontrol->private_value = pval;
3800                 mutex_unlock(&codec->control_mutex);
3801                 break;
3802         default:
3803                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3804         }
3805         return err;
3806 }
3807 
3808 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3809                                 struct snd_ctl_elem_value *ucontrol)
3810 {
3811         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3812         struct ca0132_spec *spec = codec->spec;
3813         hda_nid_t nid = get_amp_nid(kcontrol);
3814         int ch = get_amp_channels(kcontrol);
3815         long *valp = ucontrol->value.integer.value;
3816 
3817         /* store the left and right volume */
3818         if (ch & 1) {
3819                 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3820                 valp++;
3821         }
3822         if (ch & 2) {
3823                 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3824                 valp++;
3825         }
3826         return 0;
3827 }
3828 
3829 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3830                                 struct snd_ctl_elem_value *ucontrol)
3831 {
3832         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3833         struct ca0132_spec *spec = codec->spec;
3834         hda_nid_t nid = get_amp_nid(kcontrol);
3835         int ch = get_amp_channels(kcontrol);
3836         long *valp = ucontrol->value.integer.value;
3837         hda_nid_t shared_nid = 0;
3838         bool effective;
3839         int changed = 1;
3840 
3841         /* store the left and right volume */
3842         if (ch & 1) {
3843                 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3844                 valp++;
3845         }
3846         if (ch & 2) {
3847                 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3848                 valp++;
3849         }
3850 
3851         /* if effective conditions, then update hw immediately. */
3852         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3853         if (effective) {
3854                 int dir = get_amp_direction(kcontrol);
3855                 unsigned long pval;
3856 
3857                 snd_hda_power_up(codec);
3858                 mutex_lock(&codec->control_mutex);
3859                 pval = kcontrol->private_value;
3860                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3861                                                                 0, dir);
3862                 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3863                 kcontrol->private_value = pval;
3864                 mutex_unlock(&codec->control_mutex);
3865                 snd_hda_power_down(codec);
3866         }
3867 
3868         return changed;
3869 }
3870 
3871 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3872                              unsigned int size, unsigned int __user *tlv)
3873 {
3874         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3875         struct ca0132_spec *spec = codec->spec;
3876         hda_nid_t nid = get_amp_nid(kcontrol);
3877         int ch = get_amp_channels(kcontrol);
3878         int dir = get_amp_direction(kcontrol);
3879         unsigned long pval;
3880         int err;
3881 
3882         switch (nid) {
3883         case VNID_SPK:
3884                 /* follow shared_out tlv */
3885                 nid = spec->shared_out_nid;
3886                 mutex_lock(&codec->control_mutex);
3887                 pval = kcontrol->private_value;
3888                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3889                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3890                 kcontrol->private_value = pval;
3891                 mutex_unlock(&codec->control_mutex);
3892                 break;
3893         case VNID_MIC:
3894                 /* follow shared_mic tlv */
3895                 nid = spec->shared_mic_nid;
3896                 mutex_lock(&codec->control_mutex);
3897                 pval = kcontrol->private_value;
3898                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3899                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3900                 kcontrol->private_value = pval;
3901                 mutex_unlock(&codec->control_mutex);
3902                 break;
3903         default:
3904                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3905         }
3906         return err;
3907 }
3908 
3909 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3910                          const char *pfx, int dir)
3911 {
3912         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3913         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3914         struct snd_kcontrol_new knew =
3915                 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3916         sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3917         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3918 }
3919 
3920 static int add_voicefx(struct hda_codec *codec)
3921 {
3922         struct snd_kcontrol_new knew =
3923                 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3924                                     VOICEFX, 1, 0, HDA_INPUT);
3925         knew.info = ca0132_voicefx_info;
3926         knew.get = ca0132_voicefx_get;
3927         knew.put = ca0132_voicefx_put;
3928         return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3929 }
3930 
3931 /*
3932  * When changing Node IDs for Mixer Controls below, make sure to update
3933  * Node IDs in ca0132_config() as well.
3934  */
3935 static struct snd_kcontrol_new ca0132_mixer[] = {
3936         CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3937         CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3938         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3939         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3940         HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3941         HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3942         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3943         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3944         CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3945                                0x12, 1, HDA_INPUT),
3946         CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3947                                VNID_HP_SEL, 1, HDA_OUTPUT),
3948         CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3949                                VNID_AMIC1_SEL, 1, HDA_INPUT),
3950         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3951                                VNID_HP_ASEL, 1, HDA_OUTPUT),
3952         CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3953                                VNID_AMIC1_ASEL, 1, HDA_INPUT),
3954         { } /* end */
3955 };
3956 
3957 static int ca0132_build_controls(struct hda_codec *codec)
3958 {
3959         struct ca0132_spec *spec = codec->spec;
3960         int i, num_fx;
3961         int err = 0;
3962 
3963         /* Add Mixer controls */
3964         for (i = 0; i < spec->num_mixers; i++) {
3965                 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3966                 if (err < 0)
3967                         return err;
3968         }
3969 
3970         /* Add in and out effects controls.
3971          * VoiceFX, PE and CrystalVoice are added separately.
3972          */
3973         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3974         for (i = 0; i < num_fx; i++) {
3975                 err = add_fx_switch(codec, ca0132_effects[i].nid,
3976                                     ca0132_effects[i].name,
3977                                     ca0132_effects[i].direct);
3978                 if (err < 0)
3979                         return err;
3980         }
3981 
3982         err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3983         if (err < 0)
3984                 return err;
3985 
3986         err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3987         if (err < 0)
3988                 return err;
3989 
3990         add_voicefx(codec);
3991 
3992 #ifdef ENABLE_TUNING_CONTROLS
3993         add_tuning_ctls(codec);
3994 #endif
3995 
3996         err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3997         if (err < 0)
3998                 return err;
3999 
4000         if (spec->dig_out) {
4001                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
4002                                                     spec->dig_out);
4003                 if (err < 0)
4004                         return err;
4005                 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
4006                 if (err < 0)
4007                         return err;
4008                 /* spec->multiout.share_spdif = 1; */
4009         }
4010 
4011         if (spec->dig_in) {
4012                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4013                 if (err < 0)
4014                         return err;
4015         }
4016         return 0;
4017 }
4018 
4019 /*
4020  * PCM
4021  */
4022 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
4023         .substreams = 1,
4024         .channels_min = 2,
4025         .channels_max = 6,
4026         .ops = {
4027                 .prepare = ca0132_playback_pcm_prepare,
4028                 .cleanup = ca0132_playback_pcm_cleanup,
4029                 .get_delay = ca0132_playback_pcm_delay,
4030         },
4031 };
4032 
4033 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
4034         .substreams = 1,
4035         .channels_min = 2,
4036         .channels_max = 2,
4037         .ops = {
4038                 .prepare = ca0132_capture_pcm_prepare,
4039                 .cleanup = ca0132_capture_pcm_cleanup,
4040                 .get_delay = ca0132_capture_pcm_delay,
4041         },
4042 };
4043 
4044 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
4045         .substreams = 1,
4046         .channels_min = 2,
4047         .channels_max = 2,
4048         .ops = {
4049                 .open = ca0132_dig_playback_pcm_open,
4050                 .close = ca0132_dig_playback_pcm_close,
4051                 .prepare = ca0132_dig_playback_pcm_prepare,
4052                 .cleanup = ca0132_dig_playback_pcm_cleanup
4053         },
4054 };
4055 
4056 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
4057         .substreams = 1,
4058         .channels_min = 2,
4059         .channels_max = 2,
4060 };
4061 
4062 static int ca0132_build_pcms(struct hda_codec *codec)
4063 {
4064         struct ca0132_spec *spec = codec->spec;
4065         struct hda_pcm *info;
4066 
4067         info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4068         if (!info)
4069                 return -ENOMEM;
4070         info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4071         info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4072         info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4073                 spec->multiout.max_channels;
4074         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4075         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4076         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4077 
4078         info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4079         if (!info)
4080                 return -ENOMEM;
4081         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4082         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4083         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4084 
4085         info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4086         if (!info)
4087                 return -ENOMEM;
4088         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4089         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4090         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4091 
4092         if (!spec->dig_out && !spec->dig_in)
4093                 return 0;
4094 
4095         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4096         if (!info)
4097                 return -ENOMEM;
4098         info->pcm_type = HDA_PCM_TYPE_SPDIF;
4099         if (spec->dig_out) {
4100                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4101                         ca0132_pcm_digital_playback;
4102                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4103         }
4104         if (spec->dig_in) {
4105                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4106                         ca0132_pcm_digital_capture;
4107                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4108         }
4109 
4110         return 0;
4111 }
4112 
4113 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4114 {
4115         if (pin) {
4116                 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
4117                 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4118                         snd_hda_codec_write(codec, pin, 0,
4119                                             AC_VERB_SET_AMP_GAIN_MUTE,
4120                                             AMP_OUT_UNMUTE);
4121         }
4122         if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4123                 snd_hda_codec_write(codec, dac, 0,
4124                                     AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4125 }
4126 
4127 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4128 {
4129         if (pin) {
4130                 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
4131                 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4132                         snd_hda_codec_write(codec, pin, 0,
4133                                             AC_VERB_SET_AMP_GAIN_MUTE,
4134                                             AMP_IN_UNMUTE(0));
4135         }
4136         if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4137                 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4138                                     AMP_IN_UNMUTE(0));
4139 
4140                 /* init to 0 dB and unmute. */
4141                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4142                                          HDA_AMP_VOLMASK, 0x5a);
4143                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4144                                          HDA_AMP_MUTE, 0);
4145         }
4146 }
4147 
4148 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4149 {
4150         unsigned int caps;
4151 
4152         caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4153                                   AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4154         snd_hda_override_amp_caps(codec, nid, dir, caps);
4155 }
4156 
4157 /*
4158  * Switch between Digital built-in mic and analog mic.
4159  */
4160 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4161 {
4162         struct ca0132_spec *spec = codec->spec;
4163         unsigned int tmp;
4164         u8 val;
4165         unsigned int oldval;
4166 
4167         codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
4168 
4169         oldval = stop_mic1(codec);
4170         ca0132_set_vipsource(codec, 0);
4171         if (enable) {
4172                 /* set DMic input as 2-ch */
4173                 tmp = FLOAT_TWO;
4174                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4175 
4176                 val = spec->dmic_ctl;
4177                 val |= 0x80;
4178                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4179                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
4180 
4181                 if (!(spec->dmic_ctl & 0x20))
4182                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4183         } else {
4184                 /* set AMic input as mono */
4185                 tmp = FLOAT_ONE;
4186                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4187 
4188                 val = spec->dmic_ctl;
4189                 /* clear bit7 and bit5 to disable dmic */
4190                 val &= 0x5f;
4191                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4192                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
4193 
4194                 if (!(spec->dmic_ctl & 0x20))
4195                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4196         }
4197         ca0132_set_vipsource(codec, 1);
4198         resume_mic1(codec, oldval);
4199 }
4200 
4201 /*
4202  * Initialization for Digital Mic.
4203  */
4204 static void ca0132_init_dmic(struct hda_codec *codec)
4205 {
4206         struct ca0132_spec *spec = codec->spec;
4207         u8 val;
4208 
4209         /* Setup Digital Mic here, but don't enable.
4210          * Enable based on jack detect.
4211          */
4212 
4213         /* MCLK uses MPIO1, set to enable.
4214          * Bit 2-0: MPIO select
4215          * Bit   3: set to disable
4216          * Bit 7-4: reserved
4217          */
4218         val = 0x01;
4219         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4220                             VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4221 
4222         /* Data1 uses MPIO3. Data2 not use
4223          * Bit 2-0: Data1 MPIO select
4224          * Bit   3: set disable Data1
4225          * Bit 6-4: Data2 MPIO select
4226          * Bit   7: set disable Data2
4227          */
4228         val = 0x83;
4229         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4230                             VENDOR_CHIPIO_DMIC_PIN_SET, val);
4231 
4232         /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4233          * Bit 3-0: Channel mask
4234          * Bit   4: set for 48KHz, clear for 32KHz
4235          * Bit   5: mode
4236          * Bit   6: set to select Data2, clear for Data1
4237          * Bit   7: set to enable DMic, clear for AMic
4238          */
4239         val = 0x23;
4240         /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4241         spec->dmic_ctl = val;
4242         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4243                             VENDOR_CHIPIO_DMIC_CTL_SET, val);
4244 }
4245 
4246 /*
4247  * Initialization for Analog Mic 2
4248  */
4249 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4250 {
4251         struct ca0132_spec *spec = codec->spec;
4252 
4253         mutex_lock(&spec->chipio_mutex);
4254         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4255                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4256         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4257                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4258         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4259                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4260         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4261                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4262         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4263                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4264         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4265                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4266         mutex_unlock(&spec->chipio_mutex);
4267 }
4268 
4269 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4270 {
4271         struct ca0132_spec *spec = codec->spec;
4272         int i;
4273 
4274         codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
4275         snd_hda_codec_update_widgets(codec);
4276 
4277         for (i = 0; i < spec->multiout.num_dacs; i++)
4278                 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4279 
4280         for (i = 0; i < spec->num_outputs; i++)
4281                 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4282 
4283         for (i = 0; i < spec->num_inputs; i++) {
4284                 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4285                 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4286         }
4287 }
4288 
4289 /*
4290  * Setup default parameters for DSP
4291  */
4292 static void ca0132_setup_defaults(struct hda_codec *codec)
4293 {
4294         struct ca0132_spec *spec = codec->spec;
4295         unsigned int tmp;
4296         int num_fx;
4297         int idx, i;
4298 
4299         if (spec->dsp_state != DSP_DOWNLOADED)
4300                 return;
4301 
4302         /* out, in effects + voicefx */
4303         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4304         for (idx = 0; idx < num_fx; idx++) {
4305                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4306                         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4307                                              ca0132_effects[idx].reqs[i],
4308                                              ca0132_effects[idx].def_vals[i]);
4309                 }
4310         }
4311 
4312         /*remove DSP headroom*/
4313         tmp = FLOAT_ZERO;
4314         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4315 
4316         /*set speaker EQ bypass attenuation*/
4317         dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4318 
4319         /* set AMic1 and AMic2 as mono mic */
4320         tmp = FLOAT_ONE;
4321         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4322         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4323 
4324         /* set AMic1 as CrystalVoice input */
4325         tmp = FLOAT_ONE;
4326         dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4327 
4328         /* set WUH source */
4329         tmp = FLOAT_TWO;
4330         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4331 }
4332 
4333 /*
4334  * Initialization of flags in chip
4335  */
4336 static void ca0132_init_flags(struct hda_codec *codec)
4337 {
4338         chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4339         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4340         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4341         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4342         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4343         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4344 }
4345 
4346 /*
4347  * Initialization of parameters in chip
4348  */
4349 static void ca0132_init_params(struct hda_codec *codec)
4350 {
4351         chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4352         chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4353 }
4354 
4355 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4356 {
4357         chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4358         chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4359         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4360         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4361         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4362         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4363 
4364         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4365         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4366         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4367 }
4368 
4369 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4370 {
4371         bool dsp_loaded = false;
4372         const struct dsp_image_seg *dsp_os_image;
4373         const struct firmware *fw_entry;
4374 
4375         if (request_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0)
4376                 return false;
4377 
4378         dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
4379         if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
4380                 codec_err(codec, "ca0132 DSP load image failed\n");
4381                 goto exit_download;
4382         }
4383 
4384         dsp_loaded = dspload_wait_loaded(codec);
4385 
4386 exit_download:
4387         release_firmware(fw_entry);
4388 
4389         return dsp_loaded;
4390 }
4391 
4392 static void ca0132_download_dsp(struct hda_codec *codec)
4393 {
4394         struct ca0132_spec *spec = codec->spec;
4395 
4396 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4397         return; /* NOP */
4398 #endif
4399 
4400         if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4401                 return; /* don't retry failures */
4402 
4403         chipio_enable_clocks(codec);
4404         spec->dsp_state = DSP_DOWNLOADING;
4405         if (!ca0132_download_dsp_images(codec))
4406                 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4407         else
4408                 spec->dsp_state = DSP_DOWNLOADED;
4409 
4410         if (spec->dsp_state == DSP_DOWNLOADED)
4411                 ca0132_set_dsp_msr(codec, true);
4412 }
4413 
4414 static void ca0132_process_dsp_response(struct hda_codec *codec,
4415                                         struct hda_jack_callback *callback)
4416 {
4417         struct ca0132_spec *spec = codec->spec;
4418 
4419         codec_dbg(codec, "ca0132_process_dsp_response\n");
4420         if (spec->wait_scp) {
4421                 if (dspio_get_response_data(codec) >= 0)
4422                         spec->wait_scp = 0;
4423         }
4424 
4425         dspio_clear_response_queue(codec);
4426 }
4427 
4428 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4429 {
4430         struct ca0132_spec *spec = codec->spec;
4431         struct hda_jack_tbl *tbl;
4432 
4433         /* Delay enabling the HP amp, to let the mic-detection
4434          * state machine run.
4435          */
4436         cancel_delayed_work_sync(&spec->unsol_hp_work);
4437         schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
4438         tbl = snd_hda_jack_tbl_get(codec, cb->nid);
4439         if (tbl)
4440                 tbl->block_report = 1;
4441 }
4442 
4443 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4444 {
4445         ca0132_select_mic(codec);
4446 }
4447 
4448 static void ca0132_init_unsol(struct hda_codec *codec)
4449 {
4450         struct ca0132_spec *spec = codec->spec;
4451         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
4452         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
4453                                             amic_callback);
4454         snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4455                                             ca0132_process_dsp_response);
4456 }
4457 
4458 /*
4459  * Verbs tables.
4460  */
4461 
4462 /* Sends before DSP download. */
4463 static struct hda_verb ca0132_base_init_verbs[] = {
4464         /*enable ct extension*/
4465         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4466         {}
4467 };
4468 
4469 /* Send at exit. */
4470 static struct hda_verb ca0132_base_exit_verbs[] = {
4471         /*set afg to D3*/
4472         {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4473         /*disable ct extension*/
4474         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4475         {}
4476 };
4477 
4478 /* Other verbs tables.  Sends after DSP download. */
4479 static struct hda_verb ca0132_init_verbs0[] = {
4480         /* chip init verbs */
4481         {0x15, 0x70D, 0xF0},
4482         {0x15, 0x70E, 0xFE},
4483         {0x15, 0x707, 0x75},
4484         {0x15, 0x707, 0xD3},
4485         {0x15, 0x707, 0x09},
4486         {0x15, 0x707, 0x53},
4487         {0x15, 0x707, 0xD4},
4488         {0x15, 0x707, 0xEF},
4489         {0x15, 0x707, 0x75},
4490         {0x15, 0x707, 0xD3},
4491         {0x15, 0x707, 0x09},
4492         {0x15, 0x707, 0x02},
4493         {0x15, 0x707, 0x37},
4494         {0x15, 0x707, 0x78},
4495         {0x15, 0x53C, 0xCE},
4496         {0x15, 0x575, 0xC9},
4497         {0x15, 0x53D, 0xCE},
4498         {0x15, 0x5B7, 0xC9},
4499         {0x15, 0x70D, 0xE8},
4500         {0x15, 0x70E, 0xFE},
4501         {0x15, 0x707, 0x02},
4502         {0x15, 0x707, 0x68},
4503         {0x15, 0x707, 0x62},
4504         {0x15, 0x53A, 0xCE},
4505         {0x15, 0x546, 0xC9},
4506         {0x15, 0x53B, 0xCE},
4507         {0x15, 0x5E8, 0xC9},
4508         {0x15, 0x717, 0x0D},
4509         {0x15, 0x718, 0x20},
4510         {}
4511 };
4512 
4513 static void ca0132_init_chip(struct hda_codec *codec)
4514 {
4515         struct ca0132_spec *spec = codec->spec;
4516         int num_fx;
4517         int i;
4518         unsigned int on;
4519 
4520         mutex_init(&spec->chipio_mutex);
4521 
4522         spec->cur_out_type = SPEAKER_OUT;
4523         spec->cur_mic_type = DIGITAL_MIC;
4524         spec->cur_mic_boost = 0;
4525 
4526         for (i = 0; i < VNODES_COUNT; i++) {
4527                 spec->vnode_lvol[i] = 0x5a;
4528                 spec->vnode_rvol[i] = 0x5a;
4529                 spec->vnode_lswitch[i] = 0;
4530                 spec->vnode_rswitch[i] = 0;
4531         }
4532 
4533         /*
4534          * Default states for effects are in ca0132_effects[].
4535          */
4536         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4537         for (i = 0; i < num_fx; i++) {
4538                 on = (unsigned int)ca0132_effects[i].reqs[0];
4539                 spec->effects_switch[i] = on ? 1 : 0;
4540         }
4541 
4542         spec->voicefx_val = 0;
4543         spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4544         spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4545 
4546 #ifdef ENABLE_TUNING_CONTROLS
4547         ca0132_init_tuning_defaults(codec);
4548 #endif
4549 }
4550 
4551 static void ca0132_exit_chip(struct hda_codec *codec)
4552 {
4553         /* put any chip cleanup stuffs here. */
4554 
4555         if (dspload_is_loaded(codec))
4556                 dsp_reset(codec);
4557 }
4558 
4559 static int ca0132_init(struct hda_codec *codec)
4560 {
4561         struct ca0132_spec *spec = codec->spec;
4562         struct auto_pin_cfg *cfg = &spec->autocfg;
4563         int i;
4564 
4565         if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4566                 spec->dsp_state = DSP_DOWNLOAD_INIT;
4567         spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
4568 
4569         snd_hda_power_up_pm(codec);
4570 
4571         ca0132_init_unsol(codec);
4572 
4573         ca0132_init_params(codec);
4574         ca0132_init_flags(codec);
4575         snd_hda_sequence_write(codec, spec->base_init_verbs);
4576         ca0132_download_dsp(codec);
4577         ca0132_refresh_widget_caps(codec);
4578         ca0132_setup_defaults(codec);
4579         ca0132_init_analog_mic2(codec);
4580         ca0132_init_dmic(codec);
4581 
4582         for (i = 0; i < spec->num_outputs; i++)
4583                 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4584 
4585         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4586 
4587         for (i = 0; i < spec->num_inputs; i++)
4588                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4589 
4590         init_input(codec, cfg->dig_in_pin, spec->dig_in);
4591 
4592         snd_hda_sequence_write(codec, spec->chip_init_verbs);
4593         snd_hda_sequence_write(codec, spec->spec_init_verbs);
4594 
4595         ca0132_select_out(codec);
4596         ca0132_select_mic(codec);
4597 
4598         snd_hda_jack_report_sync(codec);
4599 
4600         snd_hda_power_down_pm(codec);
4601 
4602         return 0;
4603 }
4604 
4605 static void ca0132_free(struct hda_codec *codec)
4606 {
4607         struct ca0132_spec *spec = codec->spec;
4608 
4609         cancel_delayed_work_sync(&spec->unsol_hp_work);
4610         snd_hda_power_up(codec);
4611         snd_hda_sequence_write(codec, spec->base_exit_verbs);
4612         ca0132_exit_chip(codec);
4613         snd_hda_power_down(codec);
4614         kfree(spec->spec_init_verbs);
4615         kfree(codec->spec);
4616 }
4617 
4618 static const struct hda_codec_ops ca0132_patch_ops = {
4619         .build_controls = ca0132_build_controls,
4620         .build_pcms = ca0132_build_pcms,
4621         .init = ca0132_init,
4622         .free = ca0132_free,
4623         .unsol_event = snd_hda_jack_unsol_event,
4624 };
4625 
4626 static void ca0132_config(struct hda_codec *codec)
4627 {
4628         struct ca0132_spec *spec = codec->spec;
4629         struct auto_pin_cfg *cfg = &spec->autocfg;
4630 
4631         spec->dacs[0] = 0x2;
4632         spec->dacs[1] = 0x3;
4633         spec->dacs[2] = 0x4;
4634 
4635         spec->multiout.dac_nids = spec->dacs;
4636         spec->multiout.num_dacs = 3;
4637         spec->multiout.max_channels = 2;
4638 
4639         if (spec->quirk == QUIRK_ALIENWARE) {
4640                 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
4641                 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
4642 
4643                 spec->num_outputs = 2;
4644                 spec->out_pins[0] = 0x0b; /* speaker out */
4645                 spec->out_pins[1] = 0x0f;
4646                 spec->shared_out_nid = 0x2;
4647                 spec->unsol_tag_hp = 0x0f;
4648 
4649                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4650                 spec->adcs[1] = 0x8; /* analog mic2 */
4651                 spec->adcs[2] = 0xa; /* what u hear */
4652 
4653                 spec->num_inputs = 3;
4654                 spec->input_pins[0] = 0x12;
4655                 spec->input_pins[1] = 0x11;
4656                 spec->input_pins[2] = 0x13;
4657                 spec->shared_mic_nid = 0x7;
4658                 spec->unsol_tag_amic1 = 0x11;
4659         } else {
4660                 spec->num_outputs = 2;
4661                 spec->out_pins[0] = 0x0b; /* speaker out */
4662                 spec->out_pins[1] = 0x10; /* headphone out */
4663                 spec->shared_out_nid = 0x2;
4664                 spec->unsol_tag_hp = spec->out_pins[1];
4665 
4666                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4667                 spec->adcs[1] = 0x8; /* analog mic2 */
4668                 spec->adcs[2] = 0xa; /* what u hear */
4669 
4670                 spec->num_inputs = 3;
4671                 spec->input_pins[0] = 0x12;
4672                 spec->input_pins[1] = 0x11;
4673                 spec->input_pins[2] = 0x13;
4674                 spec->shared_mic_nid = 0x7;
4675                 spec->unsol_tag_amic1 = spec->input_pins[0];
4676 
4677                 /* SPDIF I/O */
4678                 spec->dig_out = 0x05;
4679                 spec->multiout.dig_out_nid = spec->dig_out;
4680                 cfg->dig_out_pins[0] = 0x0c;
4681                 cfg->dig_outs = 1;
4682                 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4683                 spec->dig_in = 0x09;
4684                 cfg->dig_in_pin = 0x0e;
4685                 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4686         }
4687 }
4688 
4689 static int ca0132_prepare_verbs(struct hda_codec *codec)
4690 {
4691 /* Verbs + terminator (an empty element) */
4692 #define NUM_SPEC_VERBS 4
4693         struct ca0132_spec *spec = codec->spec;
4694 
4695         spec->chip_init_verbs = ca0132_init_verbs0;
4696         spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
4697         if (!spec->spec_init_verbs)
4698                 return -ENOMEM;
4699 
4700         /* HP jack autodetection */
4701         spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
4702         spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4703         spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
4704 
4705         /* MIC1 jack autodetection */
4706         spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
4707         spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4708         spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
4709 
4710         /* config EAPD */
4711         spec->spec_init_verbs[2].nid = 0x0b;
4712         spec->spec_init_verbs[2].param = 0x78D;
4713         spec->spec_init_verbs[2].verb = 0x00;
4714 
4715         /* Previously commented configuration */
4716         /*
4717         spec->spec_init_verbs[3].nid = 0x0b;
4718         spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
4719         spec->spec_init_verbs[3].verb = 0x02;
4720 
4721         spec->spec_init_verbs[4].nid = 0x10;
4722         spec->spec_init_verbs[4].param = 0x78D;
4723         spec->spec_init_verbs[4].verb = 0x02;
4724 
4725         spec->spec_init_verbs[5].nid = 0x10;
4726         spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
4727         spec->spec_init_verbs[5].verb = 0x02;
4728         */
4729 
4730         /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
4731         return 0;
4732 }
4733 
4734 static int patch_ca0132(struct hda_codec *codec)
4735 {
4736         struct ca0132_spec *spec;
4737         int err;
4738         const struct snd_pci_quirk *quirk;
4739 
4740         codec_dbg(codec, "patch_ca0132\n");
4741 
4742         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4743         if (!spec)
4744                 return -ENOMEM;
4745         codec->spec = spec;
4746         spec->codec = codec;
4747 
4748         codec->patch_ops = ca0132_patch_ops;
4749         codec->pcm_format_first = 1;
4750         codec->no_sticky_stream = 1;
4751 
4752         /* Detect codec quirk */
4753         quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
4754         if (quirk)
4755                 spec->quirk = quirk->value;
4756         else
4757                 spec->quirk = QUIRK_NONE;
4758 
4759         spec->dsp_state = DSP_DOWNLOAD_INIT;
4760         spec->num_mixers = 1;
4761         spec->mixers[0] = ca0132_mixer;
4762 
4763         spec->base_init_verbs = ca0132_base_init_verbs;
4764         spec->base_exit_verbs = ca0132_base_exit_verbs;
4765 
4766         INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4767 
4768         ca0132_init_chip(codec);
4769 
4770         ca0132_config(codec);
4771 
4772         err = ca0132_prepare_verbs(codec);
4773         if (err < 0)
4774                 return err;
4775 
4776         err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4777         if (err < 0)
4778                 return err;
4779 
4780         return 0;
4781 }
4782 
4783 /*
4784  * patch entries
4785  */
4786 static struct hda_device_id snd_hda_id_ca0132[] = {
4787         HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
4788         {} /* terminator */
4789 };
4790 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
4791 
4792 MODULE_LICENSE("GPL");
4793 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4794 
4795 static struct hda_codec_driver ca0132_driver = {
4796         .id = snd_hda_id_ca0132,
4797 };
4798 
4799 module_hda_codec_driver(ca0132_driver);
4800 

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