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Linux/sound/pci/hda/hda_intel.c

  1 /*
  2  *
  3  *  hda_intel.c - Implementation of primary alsa driver code base
  4  *                for Intel HD Audio.
  5  *
  6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
  7  *
  8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  9  *                     PeiSen Hou <pshou@realtek.com.tw>
 10  *
 11  *  This program is free software; you can redistribute it and/or modify it
 12  *  under the terms of the GNU General Public License as published by the Free
 13  *  Software Foundation; either version 2 of the License, or (at your option)
 14  *  any later version.
 15  *
 16  *  This program is distributed in the hope that it will be useful, but WITHOUT
 17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 19  *  more details.
 20  *
 21  *  You should have received a copy of the GNU General Public License along with
 22  *  this program; if not, write to the Free Software Foundation, Inc., 59
 23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 24  *
 25  *  CONTACTS:
 26  *
 27  *  Matt Jared          matt.jared@intel.com
 28  *  Andy Kopp           andy.kopp@intel.com
 29  *  Dan Kogan           dan.d.kogan@intel.com
 30  *
 31  *  CHANGES:
 32  *
 33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
 34  * 
 35  */
 36 
 37 #include <linux/delay.h>
 38 #include <linux/interrupt.h>
 39 #include <linux/kernel.h>
 40 #include <linux/module.h>
 41 #include <linux/dma-mapping.h>
 42 #include <linux/moduleparam.h>
 43 #include <linux/init.h>
 44 #include <linux/slab.h>
 45 #include <linux/pci.h>
 46 #include <linux/mutex.h>
 47 #include <linux/io.h>
 48 #include <linux/pm_runtime.h>
 49 #include <linux/clocksource.h>
 50 #include <linux/time.h>
 51 #include <linux/completion.h>
 52 
 53 #ifdef CONFIG_X86
 54 /* for snoop control */
 55 #include <asm/pgtable.h>
 56 #include <asm/cacheflush.h>
 57 #endif
 58 #include <sound/core.h>
 59 #include <sound/initval.h>
 60 #include <sound/hdaudio.h>
 61 #include <sound/hda_i915.h>
 62 #include <linux/vgaarb.h>
 63 #include <linux/vga_switcheroo.h>
 64 #include <linux/firmware.h>
 65 #include "hda_codec.h"
 66 #include "hda_controller.h"
 67 #include "hda_intel.h"
 68 
 69 #define CREATE_TRACE_POINTS
 70 #include "hda_intel_trace.h"
 71 
 72 /* position fix mode */
 73 enum {
 74         POS_FIX_AUTO,
 75         POS_FIX_LPIB,
 76         POS_FIX_POSBUF,
 77         POS_FIX_VIACOMBO,
 78         POS_FIX_COMBO,
 79 };
 80 
 81 /* Defines for ATI HD Audio support in SB450 south bridge */
 82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 84 
 85 /* Defines for Nvidia HDA support */
 86 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 87 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 88 #define NVIDIA_HDA_ISTRM_COH          0x4d
 89 #define NVIDIA_HDA_OSTRM_COH          0x4c
 90 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 91 
 92 /* Defines for Intel SCH HDA snoop control */
 93 #define INTEL_SCH_HDA_DEVC      0x78
 94 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 95 
 96 /* Define IN stream 0 FIFO size offset in VIA controller */
 97 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 98 /* Define VIA HD Audio Device ID*/
 99 #define VIA_HDAC_DEVICE_ID              0x3288
100 
101 /* max number of SDs */
102 /* ICH, ATI and VIA have 4 playback and 4 capture */
103 #define ICH6_NUM_CAPTURE        4
104 #define ICH6_NUM_PLAYBACK       4
105 
106 /* ULI has 6 playback and 5 capture */
107 #define ULI_NUM_CAPTURE         5
108 #define ULI_NUM_PLAYBACK        6
109 
110 /* ATI HDMI may have up to 8 playbacks and 0 capture */
111 #define ATIHDMI_NUM_CAPTURE     0
112 #define ATIHDMI_NUM_PLAYBACK    8
113 
114 /* TERA has 4 playback and 3 capture */
115 #define TERA_NUM_CAPTURE        3
116 #define TERA_NUM_PLAYBACK       4
117 
118 
119 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
120 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
121 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
122 static char *model[SNDRV_CARDS];
123 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
124 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
125 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
126 static int probe_only[SNDRV_CARDS];
127 static int jackpoll_ms[SNDRV_CARDS];
128 static bool single_cmd;
129 static int enable_msi = -1;
130 #ifdef CONFIG_SND_HDA_PATCH_LOADER
131 static char *patch[SNDRV_CARDS];
132 #endif
133 #ifdef CONFIG_SND_HDA_INPUT_BEEP
134 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
135                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
136 #endif
137 
138 module_param_array(index, int, NULL, 0444);
139 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
140 module_param_array(id, charp, NULL, 0444);
141 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
142 module_param_array(enable, bool, NULL, 0444);
143 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
144 module_param_array(model, charp, NULL, 0444);
145 MODULE_PARM_DESC(model, "Use the given board model.");
146 module_param_array(position_fix, int, NULL, 0444);
147 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
148                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
149 module_param_array(bdl_pos_adj, int, NULL, 0644);
150 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
151 module_param_array(probe_mask, int, NULL, 0444);
152 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
153 module_param_array(probe_only, int, NULL, 0444);
154 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
155 module_param_array(jackpoll_ms, int, NULL, 0444);
156 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
157 module_param(single_cmd, bool, 0444);
158 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
159                  "(for debugging only).");
160 module_param(enable_msi, bint, 0444);
161 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
162 #ifdef CONFIG_SND_HDA_PATCH_LOADER
163 module_param_array(patch, charp, NULL, 0444);
164 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
165 #endif
166 #ifdef CONFIG_SND_HDA_INPUT_BEEP
167 module_param_array(beep_mode, bool, NULL, 0444);
168 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
169                             "(0=off, 1=on) (default=1).");
170 #endif
171 
172 #ifdef CONFIG_PM
173 static int param_set_xint(const char *val, const struct kernel_param *kp);
174 static const struct kernel_param_ops param_ops_xint = {
175         .set = param_set_xint,
176         .get = param_get_int,
177 };
178 #define param_check_xint param_check_int
179 
180 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
181 module_param(power_save, xint, 0644);
182 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
183                  "(in second, 0 = disable).");
184 
185 /* reset the HD-audio controller in power save mode.
186  * this may give more power-saving, but will take longer time to
187  * wake up.
188  */
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
192 #else
193 #define power_save      0
194 #endif /* CONFIG_PM */
195 
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199                 "Force buffer and period sizes to be multiple of 128 bytes.");
200 
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop               true
207 #endif
208 
209 
210 MODULE_LICENSE("GPL");
211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212                          "{Intel, ICH6M},"
213                          "{Intel, ICH7},"
214                          "{Intel, ESB2},"
215                          "{Intel, ICH8},"
216                          "{Intel, ICH9},"
217                          "{Intel, ICH10},"
218                          "{Intel, PCH},"
219                          "{Intel, CPT},"
220                          "{Intel, PPT},"
221                          "{Intel, LPT},"
222                          "{Intel, LPT_LP},"
223                          "{Intel, WPT_LP},"
224                          "{Intel, SPT},"
225                          "{Intel, SPT_LP},"
226                          "{Intel, HPT},"
227                          "{Intel, PBG},"
228                          "{Intel, SCH},"
229                          "{ATI, SB450},"
230                          "{ATI, SB600},"
231                          "{ATI, RS600},"
232                          "{ATI, RS690},"
233                          "{ATI, RS780},"
234                          "{ATI, R600},"
235                          "{ATI, RV630},"
236                          "{ATI, RV610},"
237                          "{ATI, RV670},"
238                          "{ATI, RV635},"
239                          "{ATI, RV620},"
240                          "{ATI, RV770},"
241                          "{VIA, VT8251},"
242                          "{VIA, VT8237A},"
243                          "{SiS, SIS966},"
244                          "{ULI, M5461}}");
245 MODULE_DESCRIPTION("Intel HDA driver");
246 
247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
249 #define SUPPORT_VGA_SWITCHEROO
250 #endif
251 #endif
252 
253 
254 /*
255  */
256 
257 /* driver types */
258 enum {
259         AZX_DRIVER_ICH,
260         AZX_DRIVER_PCH,
261         AZX_DRIVER_SCH,
262         AZX_DRIVER_HDMI,
263         AZX_DRIVER_ATI,
264         AZX_DRIVER_ATIHDMI,
265         AZX_DRIVER_ATIHDMI_NS,
266         AZX_DRIVER_VIA,
267         AZX_DRIVER_SIS,
268         AZX_DRIVER_ULI,
269         AZX_DRIVER_NVIDIA,
270         AZX_DRIVER_TERA,
271         AZX_DRIVER_CTX,
272         AZX_DRIVER_CTHDA,
273         AZX_DRIVER_CMEDIA,
274         AZX_DRIVER_GENERIC,
275         AZX_NUM_DRIVERS, /* keep this as last entry */
276 };
277 
278 #define azx_get_snoop_type(chip) \
279         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281 
282 /* quirks for old Intel chipsets */
283 #define AZX_DCAPS_INTEL_ICH \
284         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
285 
286 /* quirks for Intel PCH */
287 #define AZX_DCAPS_INTEL_PCH_NOPM \
288         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
289          AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
290 
291 #define AZX_DCAPS_INTEL_PCH \
292         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
293 
294 #define AZX_DCAPS_INTEL_HASWELL \
295         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
296          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
297          AZX_DCAPS_SNOOP_TYPE(SCH))
298 
299 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
300 #define AZX_DCAPS_INTEL_BROADWELL \
301         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
302          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
303          AZX_DCAPS_SNOOP_TYPE(SCH))
304 
305 #define AZX_DCAPS_INTEL_BAYTRAIL \
306         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
307 
308 #define AZX_DCAPS_INTEL_BRASWELL \
309         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
310 
311 #define AZX_DCAPS_INTEL_SKYLAKE \
312         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
313          AZX_DCAPS_I915_POWERWELL)
314 
315 /* quirks for ATI SB / AMD Hudson */
316 #define AZX_DCAPS_PRESET_ATI_SB \
317         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
318          AZX_DCAPS_SNOOP_TYPE(ATI))
319 
320 /* quirks for ATI/AMD HDMI */
321 #define AZX_DCAPS_PRESET_ATI_HDMI \
322         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
323          AZX_DCAPS_NO_MSI64)
324 
325 /* quirks for ATI HDMI with snoop off */
326 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
327         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
328 
329 /* quirks for Nvidia */
330 #define AZX_DCAPS_PRESET_NVIDIA \
331         (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
332          AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
333          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
334 
335 #define AZX_DCAPS_PRESET_CTHDA \
336         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
337          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
338 
339 /*
340  * VGA-switcher support
341  */
342 #ifdef SUPPORT_VGA_SWITCHEROO
343 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
344 #else
345 #define use_vga_switcheroo(chip)        0
346 #endif
347 
348 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
349                                         ((pci)->device == 0x0c0c) || \
350                                         ((pci)->device == 0x0d0c) || \
351                                         ((pci)->device == 0x160c))
352 
353 static char *driver_short_names[] = {
354         [AZX_DRIVER_ICH] = "HDA Intel",
355         [AZX_DRIVER_PCH] = "HDA Intel PCH",
356         [AZX_DRIVER_SCH] = "HDA Intel MID",
357         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
358         [AZX_DRIVER_ATI] = "HDA ATI SB",
359         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
360         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
361         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
362         [AZX_DRIVER_SIS] = "HDA SIS966",
363         [AZX_DRIVER_ULI] = "HDA ULI M5461",
364         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
365         [AZX_DRIVER_TERA] = "HDA Teradici", 
366         [AZX_DRIVER_CTX] = "HDA Creative", 
367         [AZX_DRIVER_CTHDA] = "HDA Creative",
368         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
369         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
370 };
371 
372 #ifdef CONFIG_X86
373 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
374 {
375         int pages;
376 
377         if (azx_snoop(chip))
378                 return;
379         if (!dmab || !dmab->area || !dmab->bytes)
380                 return;
381 
382 #ifdef CONFIG_SND_DMA_SGBUF
383         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
384                 struct snd_sg_buf *sgbuf = dmab->private_data;
385                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
386                         return; /* deal with only CORB/RIRB buffers */
387                 if (on)
388                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
389                 else
390                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
391                 return;
392         }
393 #endif
394 
395         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
396         if (on)
397                 set_memory_wc((unsigned long)dmab->area, pages);
398         else
399                 set_memory_wb((unsigned long)dmab->area, pages);
400 }
401 
402 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
403                                  bool on)
404 {
405         __mark_pages_wc(chip, buf, on);
406 }
407 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
408                                    struct snd_pcm_substream *substream, bool on)
409 {
410         if (azx_dev->wc_marked != on) {
411                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
412                 azx_dev->wc_marked = on;
413         }
414 }
415 #else
416 /* NOP for other archs */
417 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
418                                  bool on)
419 {
420 }
421 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
422                                    struct snd_pcm_substream *substream, bool on)
423 {
424 }
425 #endif
426 
427 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
428 
429 /*
430  * initialize the PCI registers
431  */
432 /* update bits in a PCI register byte */
433 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
434                             unsigned char mask, unsigned char val)
435 {
436         unsigned char data;
437 
438         pci_read_config_byte(pci, reg, &data);
439         data &= ~mask;
440         data |= (val & mask);
441         pci_write_config_byte(pci, reg, data);
442 }
443 
444 static void azx_init_pci(struct azx *chip)
445 {
446         int snoop_type = azx_get_snoop_type(chip);
447 
448         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
449          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
450          * Ensuring these bits are 0 clears playback static on some HD Audio
451          * codecs.
452          * The PCI register TCSEL is defined in the Intel manuals.
453          */
454         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
455                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
456                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
457         }
458 
459         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
460          * we need to enable snoop.
461          */
462         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
463                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
464                         azx_snoop(chip));
465                 update_pci_byte(chip->pci,
466                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
467                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
468         }
469 
470         /* For NVIDIA HDA, enable snoop */
471         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
472                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
473                         azx_snoop(chip));
474                 update_pci_byte(chip->pci,
475                                 NVIDIA_HDA_TRANSREG_ADDR,
476                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
477                 update_pci_byte(chip->pci,
478                                 NVIDIA_HDA_ISTRM_COH,
479                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
480                 update_pci_byte(chip->pci,
481                                 NVIDIA_HDA_OSTRM_COH,
482                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
483         }
484 
485         /* Enable SCH/PCH snoop if needed */
486         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
487                 unsigned short snoop;
488                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
489                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
490                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
491                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
492                         if (!azx_snoop(chip))
493                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
494                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
495                         pci_read_config_word(chip->pci,
496                                 INTEL_SCH_HDA_DEVC, &snoop);
497                 }
498                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
499                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
500                         "Disabled" : "Enabled");
501         }
502 }
503 
504 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
505 {
506         struct hdac_bus *bus = azx_bus(chip);
507 
508         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
509                 snd_hdac_set_codec_wakeup(bus, true);
510         azx_init_chip(chip, full_reset);
511         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
512                 snd_hdac_set_codec_wakeup(bus, false);
513 }
514 
515 /* calculate runtime delay from LPIB */
516 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
517                                    unsigned int pos)
518 {
519         struct snd_pcm_substream *substream = azx_dev->core.substream;
520         int stream = substream->stream;
521         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
522         int delay;
523 
524         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
525                 delay = pos - lpib_pos;
526         else
527                 delay = lpib_pos - pos;
528         if (delay < 0) {
529                 if (delay >= azx_dev->core.delay_negative_threshold)
530                         delay = 0;
531                 else
532                         delay += azx_dev->core.bufsize;
533         }
534 
535         if (delay >= azx_dev->core.period_bytes) {
536                 dev_info(chip->card->dev,
537                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
538                          delay, azx_dev->core.period_bytes);
539                 delay = 0;
540                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
541                 chip->get_delay[stream] = NULL;
542         }
543 
544         return bytes_to_frames(substream->runtime, delay);
545 }
546 
547 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
548 
549 /* called from IRQ */
550 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
551 {
552         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
553         int ok;
554 
555         ok = azx_position_ok(chip, azx_dev);
556         if (ok == 1) {
557                 azx_dev->irq_pending = 0;
558                 return ok;
559         } else if (ok == 0) {
560                 /* bogus IRQ, process it later */
561                 azx_dev->irq_pending = 1;
562                 schedule_work(&hda->irq_pending_work);
563         }
564         return 0;
565 }
566 
567 /* Enable/disable i915 display power for the link */
568 static int azx_intel_link_power(struct azx *chip, bool enable)
569 {
570         struct hdac_bus *bus = azx_bus(chip);
571 
572         return snd_hdac_display_power(bus, enable);
573 }
574 
575 /*
576  * Check whether the current DMA position is acceptable for updating
577  * periods.  Returns non-zero if it's OK.
578  *
579  * Many HD-audio controllers appear pretty inaccurate about
580  * the update-IRQ timing.  The IRQ is issued before actually the
581  * data is processed.  So, we need to process it afterwords in a
582  * workqueue.
583  */
584 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
585 {
586         struct snd_pcm_substream *substream = azx_dev->core.substream;
587         int stream = substream->stream;
588         u32 wallclk;
589         unsigned int pos;
590 
591         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
592         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
593                 return -1;      /* bogus (too early) interrupt */
594 
595         if (chip->get_position[stream])
596                 pos = chip->get_position[stream](chip, azx_dev);
597         else { /* use the position buffer as default */
598                 pos = azx_get_pos_posbuf(chip, azx_dev);
599                 if (!pos || pos == (u32)-1) {
600                         dev_info(chip->card->dev,
601                                  "Invalid position buffer, using LPIB read method instead.\n");
602                         chip->get_position[stream] = azx_get_pos_lpib;
603                         if (chip->get_position[0] == azx_get_pos_lpib &&
604                             chip->get_position[1] == azx_get_pos_lpib)
605                                 azx_bus(chip)->use_posbuf = false;
606                         pos = azx_get_pos_lpib(chip, azx_dev);
607                         chip->get_delay[stream] = NULL;
608                 } else {
609                         chip->get_position[stream] = azx_get_pos_posbuf;
610                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
611                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
612                 }
613         }
614 
615         if (pos >= azx_dev->core.bufsize)
616                 pos = 0;
617 
618         if (WARN_ONCE(!azx_dev->core.period_bytes,
619                       "hda-intel: zero azx_dev->period_bytes"))
620                 return -1; /* this shouldn't happen! */
621         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
622             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
623                 /* NG - it's below the first next period boundary */
624                 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
625         azx_dev->core.start_wallclk += wallclk;
626         return 1; /* OK, it's fine */
627 }
628 
629 /*
630  * The work for pending PCM period updates.
631  */
632 static void azx_irq_pending_work(struct work_struct *work)
633 {
634         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
635         struct azx *chip = &hda->chip;
636         struct hdac_bus *bus = azx_bus(chip);
637         struct hdac_stream *s;
638         int pending, ok;
639 
640         if (!hda->irq_pending_warned) {
641                 dev_info(chip->card->dev,
642                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
643                          chip->card->number);
644                 hda->irq_pending_warned = 1;
645         }
646 
647         for (;;) {
648                 pending = 0;
649                 spin_lock_irq(&bus->reg_lock);
650                 list_for_each_entry(s, &bus->stream_list, list) {
651                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
652                         if (!azx_dev->irq_pending ||
653                             !s->substream ||
654                             !s->running)
655                                 continue;
656                         ok = azx_position_ok(chip, azx_dev);
657                         if (ok > 0) {
658                                 azx_dev->irq_pending = 0;
659                                 spin_unlock(&bus->reg_lock);
660                                 snd_pcm_period_elapsed(s->substream);
661                                 spin_lock(&bus->reg_lock);
662                         } else if (ok < 0) {
663                                 pending = 0;    /* too early */
664                         } else
665                                 pending++;
666                 }
667                 spin_unlock_irq(&bus->reg_lock);
668                 if (!pending)
669                         return;
670                 msleep(1);
671         }
672 }
673 
674 /* clear irq_pending flags and assure no on-going workq */
675 static void azx_clear_irq_pending(struct azx *chip)
676 {
677         struct hdac_bus *bus = azx_bus(chip);
678         struct hdac_stream *s;
679 
680         spin_lock_irq(&bus->reg_lock);
681         list_for_each_entry(s, &bus->stream_list, list) {
682                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
683                 azx_dev->irq_pending = 0;
684         }
685         spin_unlock_irq(&bus->reg_lock);
686 }
687 
688 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
689 {
690         struct hdac_bus *bus = azx_bus(chip);
691 
692         if (request_irq(chip->pci->irq, azx_interrupt,
693                         chip->msi ? 0 : IRQF_SHARED,
694                         KBUILD_MODNAME, chip)) {
695                 dev_err(chip->card->dev,
696                         "unable to grab IRQ %d, disabling device\n",
697                         chip->pci->irq);
698                 if (do_disconnect)
699                         snd_card_disconnect(chip->card);
700                 return -1;
701         }
702         bus->irq = chip->pci->irq;
703         pci_intx(chip->pci, !chip->msi);
704         return 0;
705 }
706 
707 /* get the current DMA position with correction on VIA chips */
708 static unsigned int azx_via_get_position(struct azx *chip,
709                                          struct azx_dev *azx_dev)
710 {
711         unsigned int link_pos, mini_pos, bound_pos;
712         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
713         unsigned int fifo_size;
714 
715         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
716         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
717                 /* Playback, no problem using link position */
718                 return link_pos;
719         }
720 
721         /* Capture */
722         /* For new chipset,
723          * use mod to get the DMA position just like old chipset
724          */
725         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
726         mod_dma_pos %= azx_dev->core.period_bytes;
727 
728         /* azx_dev->fifo_size can't get FIFO size of in stream.
729          * Get from base address + offset.
730          */
731         fifo_size = readw(azx_bus(chip)->remap_addr +
732                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
733 
734         if (azx_dev->insufficient) {
735                 /* Link position never gather than FIFO size */
736                 if (link_pos <= fifo_size)
737                         return 0;
738 
739                 azx_dev->insufficient = 0;
740         }
741 
742         if (link_pos <= fifo_size)
743                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
744         else
745                 mini_pos = link_pos - fifo_size;
746 
747         /* Find nearest previous boudary */
748         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
749         mod_link_pos = link_pos % azx_dev->core.period_bytes;
750         if (mod_link_pos >= fifo_size)
751                 bound_pos = link_pos - mod_link_pos;
752         else if (mod_dma_pos >= mod_mini_pos)
753                 bound_pos = mini_pos - mod_mini_pos;
754         else {
755                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
756                 if (bound_pos >= azx_dev->core.bufsize)
757                         bound_pos = 0;
758         }
759 
760         /* Calculate real DMA position we want */
761         return bound_pos + mod_dma_pos;
762 }
763 
764 #ifdef CONFIG_PM
765 static DEFINE_MUTEX(card_list_lock);
766 static LIST_HEAD(card_list);
767 
768 static void azx_add_card_list(struct azx *chip)
769 {
770         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
771         mutex_lock(&card_list_lock);
772         list_add(&hda->list, &card_list);
773         mutex_unlock(&card_list_lock);
774 }
775 
776 static void azx_del_card_list(struct azx *chip)
777 {
778         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
779         mutex_lock(&card_list_lock);
780         list_del_init(&hda->list);
781         mutex_unlock(&card_list_lock);
782 }
783 
784 /* trigger power-save check at writing parameter */
785 static int param_set_xint(const char *val, const struct kernel_param *kp)
786 {
787         struct hda_intel *hda;
788         struct azx *chip;
789         int prev = power_save;
790         int ret = param_set_int(val, kp);
791 
792         if (ret || prev == power_save)
793                 return ret;
794 
795         mutex_lock(&card_list_lock);
796         list_for_each_entry(hda, &card_list, list) {
797                 chip = &hda->chip;
798                 if (!hda->probe_continued || chip->disabled)
799                         continue;
800                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
801         }
802         mutex_unlock(&card_list_lock);
803         return 0;
804 }
805 #else
806 #define azx_add_card_list(chip) /* NOP */
807 #define azx_del_card_list(chip) /* NOP */
808 #endif /* CONFIG_PM */
809 
810 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
811  * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
812  * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
813  * BCLK = CDCLK * M / N
814  * The values will be lost when the display power well is disabled and need to
815  * be restored to avoid abnormal playback speed.
816  */
817 static void haswell_set_bclk(struct hda_intel *hda)
818 {
819         struct azx *chip = &hda->chip;
820         int cdclk_freq;
821         unsigned int bclk_m, bclk_n;
822 
823         if (!hda->need_i915_power)
824                 return;
825 
826         cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
827         switch (cdclk_freq) {
828         case 337500:
829                 bclk_m = 16;
830                 bclk_n = 225;
831                 break;
832 
833         case 450000:
834         default: /* default CDCLK 450MHz */
835                 bclk_m = 4;
836                 bclk_n = 75;
837                 break;
838 
839         case 540000:
840                 bclk_m = 4;
841                 bclk_n = 90;
842                 break;
843 
844         case 675000:
845                 bclk_m = 8;
846                 bclk_n = 225;
847                 break;
848         }
849 
850         azx_writew(chip, HSW_EM4, bclk_m);
851         azx_writew(chip, HSW_EM5, bclk_n);
852 }
853 
854 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
855 /*
856  * power management
857  */
858 static int azx_suspend(struct device *dev)
859 {
860         struct snd_card *card = dev_get_drvdata(dev);
861         struct azx *chip;
862         struct hda_intel *hda;
863         struct hdac_bus *bus;
864 
865         if (!card)
866                 return 0;
867 
868         chip = card->private_data;
869         hda = container_of(chip, struct hda_intel, chip);
870         if (chip->disabled || hda->init_failed || !chip->running)
871                 return 0;
872 
873         bus = azx_bus(chip);
874         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
875         azx_clear_irq_pending(chip);
876         azx_stop_chip(chip);
877         azx_enter_link_reset(chip);
878         if (bus->irq >= 0) {
879                 free_irq(bus->irq, chip);
880                 bus->irq = -1;
881         }
882 
883         if (chip->msi)
884                 pci_disable_msi(chip->pci);
885         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
886                 && hda->need_i915_power)
887                 snd_hdac_display_power(bus, false);
888 
889         trace_azx_suspend(chip);
890         return 0;
891 }
892 
893 static int azx_resume(struct device *dev)
894 {
895         struct pci_dev *pci = to_pci_dev(dev);
896         struct snd_card *card = dev_get_drvdata(dev);
897         struct azx *chip;
898         struct hda_intel *hda;
899 
900         if (!card)
901                 return 0;
902 
903         chip = card->private_data;
904         hda = container_of(chip, struct hda_intel, chip);
905         if (chip->disabled || hda->init_failed || !chip->running)
906                 return 0;
907 
908         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
909                 && hda->need_i915_power) {
910                 snd_hdac_display_power(azx_bus(chip), true);
911                 haswell_set_bclk(hda);
912         }
913         if (chip->msi)
914                 if (pci_enable_msi(pci) < 0)
915                         chip->msi = 0;
916         if (azx_acquire_irq(chip, 1) < 0)
917                 return -EIO;
918         azx_init_pci(chip);
919 
920         hda_intel_init_chip(chip, true);
921 
922         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
923 
924         trace_azx_resume(chip);
925         return 0;
926 }
927 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
928 
929 #ifdef CONFIG_PM
930 static int azx_runtime_suspend(struct device *dev)
931 {
932         struct snd_card *card = dev_get_drvdata(dev);
933         struct azx *chip;
934         struct hda_intel *hda;
935 
936         if (!card)
937                 return 0;
938 
939         chip = card->private_data;
940         hda = container_of(chip, struct hda_intel, chip);
941         if (chip->disabled || hda->init_failed)
942                 return 0;
943 
944         if (!azx_has_pm_runtime(chip))
945                 return 0;
946 
947         /* enable controller wake up event */
948         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
949                   STATESTS_INT_MASK);
950 
951         azx_stop_chip(chip);
952         azx_enter_link_reset(chip);
953         azx_clear_irq_pending(chip);
954         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
955                 && hda->need_i915_power)
956                 snd_hdac_display_power(azx_bus(chip), false);
957 
958         trace_azx_runtime_suspend(chip);
959         return 0;
960 }
961 
962 static int azx_runtime_resume(struct device *dev)
963 {
964         struct snd_card *card = dev_get_drvdata(dev);
965         struct azx *chip;
966         struct hda_intel *hda;
967         struct hdac_bus *bus;
968         struct hda_codec *codec;
969         int status;
970 
971         if (!card)
972                 return 0;
973 
974         chip = card->private_data;
975         hda = container_of(chip, struct hda_intel, chip);
976         if (chip->disabled || hda->init_failed)
977                 return 0;
978 
979         if (!azx_has_pm_runtime(chip))
980                 return 0;
981 
982         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
983                 bus = azx_bus(chip);
984                 if (hda->need_i915_power) {
985                         snd_hdac_display_power(bus, true);
986                         haswell_set_bclk(hda);
987                 } else {
988                         /* toggle codec wakeup bit for STATESTS read */
989                         snd_hdac_set_codec_wakeup(bus, true);
990                         snd_hdac_set_codec_wakeup(bus, false);
991                 }
992         }
993 
994         /* Read STATESTS before controller reset */
995         status = azx_readw(chip, STATESTS);
996 
997         azx_init_pci(chip);
998         hda_intel_init_chip(chip, true);
999 
1000         if (status) {
1001                 list_for_each_codec(codec, &chip->bus)
1002                         if (status & (1 << codec->addr))
1003                                 schedule_delayed_work(&codec->jackpoll_work,
1004                                                       codec->jackpoll_interval);
1005         }
1006 
1007         /* disable controller Wake Up event*/
1008         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1009                         ~STATESTS_INT_MASK);
1010 
1011         trace_azx_runtime_resume(chip);
1012         return 0;
1013 }
1014 
1015 static int azx_runtime_idle(struct device *dev)
1016 {
1017         struct snd_card *card = dev_get_drvdata(dev);
1018         struct azx *chip;
1019         struct hda_intel *hda;
1020 
1021         if (!card)
1022                 return 0;
1023 
1024         chip = card->private_data;
1025         hda = container_of(chip, struct hda_intel, chip);
1026         if (chip->disabled || hda->init_failed)
1027                 return 0;
1028 
1029         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1030             azx_bus(chip)->codec_powered || !chip->running)
1031                 return -EBUSY;
1032 
1033         return 0;
1034 }
1035 
1036 static const struct dev_pm_ops azx_pm = {
1037         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1038         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1039 };
1040 
1041 #define AZX_PM_OPS      &azx_pm
1042 #else
1043 #define AZX_PM_OPS      NULL
1044 #endif /* CONFIG_PM */
1045 
1046 
1047 static int azx_probe_continue(struct azx *chip);
1048 
1049 #ifdef SUPPORT_VGA_SWITCHEROO
1050 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1051 
1052 static void azx_vs_set_state(struct pci_dev *pci,
1053                              enum vga_switcheroo_state state)
1054 {
1055         struct snd_card *card = pci_get_drvdata(pci);
1056         struct azx *chip = card->private_data;
1057         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1058         bool disabled;
1059 
1060         wait_for_completion(&hda->probe_wait);
1061         if (hda->init_failed)
1062                 return;
1063 
1064         disabled = (state == VGA_SWITCHEROO_OFF);
1065         if (chip->disabled == disabled)
1066                 return;
1067 
1068         if (!hda->probe_continued) {
1069                 chip->disabled = disabled;
1070                 if (!disabled) {
1071                         dev_info(chip->card->dev,
1072                                  "Start delayed initialization\n");
1073                         if (azx_probe_continue(chip) < 0) {
1074                                 dev_err(chip->card->dev, "initialization error\n");
1075                                 hda->init_failed = true;
1076                         }
1077                 }
1078         } else {
1079                 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1080                          disabled ? "Disabling" : "Enabling");
1081                 if (disabled) {
1082                         pm_runtime_put_sync_suspend(card->dev);
1083                         azx_suspend(card->dev);
1084                         /* when we get suspended by vga switcheroo we end up in D3cold,
1085                          * however we have no ACPI handle, so pci/acpi can't put us there,
1086                          * put ourselves there */
1087                         pci->current_state = PCI_D3cold;
1088                         chip->disabled = true;
1089                         if (snd_hda_lock_devices(&chip->bus))
1090                                 dev_warn(chip->card->dev,
1091                                          "Cannot lock devices!\n");
1092                 } else {
1093                         snd_hda_unlock_devices(&chip->bus);
1094                         pm_runtime_get_noresume(card->dev);
1095                         chip->disabled = false;
1096                         azx_resume(card->dev);
1097                 }
1098         }
1099 }
1100 
1101 static bool azx_vs_can_switch(struct pci_dev *pci)
1102 {
1103         struct snd_card *card = pci_get_drvdata(pci);
1104         struct azx *chip = card->private_data;
1105         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1106 
1107         wait_for_completion(&hda->probe_wait);
1108         if (hda->init_failed)
1109                 return false;
1110         if (chip->disabled || !hda->probe_continued)
1111                 return true;
1112         if (snd_hda_lock_devices(&chip->bus))
1113                 return false;
1114         snd_hda_unlock_devices(&chip->bus);
1115         return true;
1116 }
1117 
1118 static void init_vga_switcheroo(struct azx *chip)
1119 {
1120         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1121         struct pci_dev *p = get_bound_vga(chip->pci);
1122         if (p) {
1123                 dev_info(chip->card->dev,
1124                          "Handle VGA-switcheroo audio client\n");
1125                 hda->use_vga_switcheroo = 1;
1126                 pci_dev_put(p);
1127         }
1128 }
1129 
1130 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1131         .set_gpu_state = azx_vs_set_state,
1132         .can_switch = azx_vs_can_switch,
1133 };
1134 
1135 static int register_vga_switcheroo(struct azx *chip)
1136 {
1137         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1138         int err;
1139 
1140         if (!hda->use_vga_switcheroo)
1141                 return 0;
1142         /* FIXME: currently only handling DIS controller
1143          * is there any machine with two switchable HDMI audio controllers?
1144          */
1145         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1146                                                     VGA_SWITCHEROO_DIS,
1147                                                     hda->probe_continued);
1148         if (err < 0)
1149                 return err;
1150         hda->vga_switcheroo_registered = 1;
1151 
1152         /* register as an optimus hdmi audio power domain */
1153         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1154                                                          &hda->hdmi_pm_domain);
1155         return 0;
1156 }
1157 #else
1158 #define init_vga_switcheroo(chip)               /* NOP */
1159 #define register_vga_switcheroo(chip)           0
1160 #define check_hdmi_disabled(pci)        false
1161 #endif /* SUPPORT_VGA_SWITCHER */
1162 
1163 /*
1164  * destructor
1165  */
1166 static int azx_free(struct azx *chip)
1167 {
1168         struct pci_dev *pci = chip->pci;
1169         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1170         struct hdac_bus *bus = azx_bus(chip);
1171 
1172         if (azx_has_pm_runtime(chip) && chip->running)
1173                 pm_runtime_get_noresume(&pci->dev);
1174 
1175         azx_del_card_list(chip);
1176 
1177         hda->init_failed = 1; /* to be sure */
1178         complete_all(&hda->probe_wait);
1179 
1180         if (use_vga_switcheroo(hda)) {
1181                 if (chip->disabled && hda->probe_continued)
1182                         snd_hda_unlock_devices(&chip->bus);
1183                 if (hda->vga_switcheroo_registered)
1184                         vga_switcheroo_unregister_client(chip->pci);
1185         }
1186 
1187         if (bus->chip_init) {
1188                 azx_clear_irq_pending(chip);
1189                 azx_stop_all_streams(chip);
1190                 azx_stop_chip(chip);
1191         }
1192 
1193         if (bus->irq >= 0)
1194                 free_irq(bus->irq, (void*)chip);
1195         if (chip->msi)
1196                 pci_disable_msi(chip->pci);
1197         iounmap(bus->remap_addr);
1198 
1199         azx_free_stream_pages(chip);
1200         azx_free_streams(chip);
1201         snd_hdac_bus_exit(bus);
1202 
1203         if (chip->region_requested)
1204                 pci_release_regions(chip->pci);
1205 
1206         pci_disable_device(chip->pci);
1207 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1208         release_firmware(chip->fw);
1209 #endif
1210 
1211         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1212                 if (hda->need_i915_power)
1213                         snd_hdac_display_power(bus, false);
1214                 snd_hdac_i915_exit(bus);
1215         }
1216         kfree(hda);
1217 
1218         return 0;
1219 }
1220 
1221 static int azx_dev_disconnect(struct snd_device *device)
1222 {
1223         struct azx *chip = device->device_data;
1224 
1225         chip->bus.shutdown = 1;
1226         return 0;
1227 }
1228 
1229 static int azx_dev_free(struct snd_device *device)
1230 {
1231         return azx_free(device->device_data);
1232 }
1233 
1234 #ifdef SUPPORT_VGA_SWITCHEROO
1235 /*
1236  * Check of disabled HDMI controller by vga-switcheroo
1237  */
1238 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1239 {
1240         struct pci_dev *p;
1241 
1242         /* check only discrete GPU */
1243         switch (pci->vendor) {
1244         case PCI_VENDOR_ID_ATI:
1245         case PCI_VENDOR_ID_AMD:
1246         case PCI_VENDOR_ID_NVIDIA:
1247                 if (pci->devfn == 1) {
1248                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1249                                                         pci->bus->number, 0);
1250                         if (p) {
1251                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1252                                         return p;
1253                                 pci_dev_put(p);
1254                         }
1255                 }
1256                 break;
1257         }
1258         return NULL;
1259 }
1260 
1261 static bool check_hdmi_disabled(struct pci_dev *pci)
1262 {
1263         bool vga_inactive = false;
1264         struct pci_dev *p = get_bound_vga(pci);
1265 
1266         if (p) {
1267                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1268                         vga_inactive = true;
1269                 pci_dev_put(p);
1270         }
1271         return vga_inactive;
1272 }
1273 #endif /* SUPPORT_VGA_SWITCHEROO */
1274 
1275 /*
1276  * white/black-listing for position_fix
1277  */
1278 static struct snd_pci_quirk position_fix_list[] = {
1279         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1280         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1281         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1282         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1283         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1284         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1285         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1286         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1287         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1288         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1289         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1290         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1291         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1292         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1293         {}
1294 };
1295 
1296 static int check_position_fix(struct azx *chip, int fix)
1297 {
1298         const struct snd_pci_quirk *q;
1299 
1300         switch (fix) {
1301         case POS_FIX_AUTO:
1302         case POS_FIX_LPIB:
1303         case POS_FIX_POSBUF:
1304         case POS_FIX_VIACOMBO:
1305         case POS_FIX_COMBO:
1306                 return fix;
1307         }
1308 
1309         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1310         if (q) {
1311                 dev_info(chip->card->dev,
1312                          "position_fix set to %d for device %04x:%04x\n",
1313                          q->value, q->subvendor, q->subdevice);
1314                 return q->value;
1315         }
1316 
1317         /* Check VIA/ATI HD Audio Controller exist */
1318         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1319                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1320                 return POS_FIX_VIACOMBO;
1321         }
1322         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1323                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1324                 return POS_FIX_LPIB;
1325         }
1326         return POS_FIX_AUTO;
1327 }
1328 
1329 static void assign_position_fix(struct azx *chip, int fix)
1330 {
1331         static azx_get_pos_callback_t callbacks[] = {
1332                 [POS_FIX_AUTO] = NULL,
1333                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1334                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1335                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1336                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1337         };
1338 
1339         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1340 
1341         /* combo mode uses LPIB only for playback */
1342         if (fix == POS_FIX_COMBO)
1343                 chip->get_position[1] = NULL;
1344 
1345         if (fix == POS_FIX_POSBUF &&
1346             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1347                 chip->get_delay[0] = chip->get_delay[1] =
1348                         azx_get_delay_from_lpib;
1349         }
1350 
1351 }
1352 
1353 /*
1354  * black-lists for probe_mask
1355  */
1356 static struct snd_pci_quirk probe_mask_list[] = {
1357         /* Thinkpad often breaks the controller communication when accessing
1358          * to the non-working (or non-existing) modem codec slot.
1359          */
1360         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1361         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1362         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1363         /* broken BIOS */
1364         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1365         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1366         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1367         /* forced codec slots */
1368         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1369         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1370         /* WinFast VP200 H (Teradici) user reported broken communication */
1371         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1372         {}
1373 };
1374 
1375 #define AZX_FORCE_CODEC_MASK    0x100
1376 
1377 static void check_probe_mask(struct azx *chip, int dev)
1378 {
1379         const struct snd_pci_quirk *q;
1380 
1381         chip->codec_probe_mask = probe_mask[dev];
1382         if (chip->codec_probe_mask == -1) {
1383                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1384                 if (q) {
1385                         dev_info(chip->card->dev,
1386                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1387                                  q->value, q->subvendor, q->subdevice);
1388                         chip->codec_probe_mask = q->value;
1389                 }
1390         }
1391 
1392         /* check forced option */
1393         if (chip->codec_probe_mask != -1 &&
1394             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1395                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1396                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1397                          (int)azx_bus(chip)->codec_mask);
1398         }
1399 }
1400 
1401 /*
1402  * white/black-list for enable_msi
1403  */
1404 static struct snd_pci_quirk msi_black_list[] = {
1405         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1406         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1407         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1408         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1409         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1410         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1411         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1412         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1413         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1414         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1415         {}
1416 };
1417 
1418 static void check_msi(struct azx *chip)
1419 {
1420         const struct snd_pci_quirk *q;
1421 
1422         if (enable_msi >= 0) {
1423                 chip->msi = !!enable_msi;
1424                 return;
1425         }
1426         chip->msi = 1;  /* enable MSI as default */
1427         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1428         if (q) {
1429                 dev_info(chip->card->dev,
1430                          "msi for device %04x:%04x set to %d\n",
1431                          q->subvendor, q->subdevice, q->value);
1432                 chip->msi = q->value;
1433                 return;
1434         }
1435 
1436         /* NVidia chipsets seem to cause troubles with MSI */
1437         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1438                 dev_info(chip->card->dev, "Disabling MSI\n");
1439                 chip->msi = 0;
1440         }
1441 }
1442 
1443 /* check the snoop mode availability */
1444 static void azx_check_snoop_available(struct azx *chip)
1445 {
1446         int snoop = hda_snoop;
1447 
1448         if (snoop >= 0) {
1449                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1450                          snoop ? "snoop" : "non-snoop");
1451                 chip->snoop = snoop;
1452                 return;
1453         }
1454 
1455         snoop = true;
1456         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1457             chip->driver_type == AZX_DRIVER_VIA) {
1458                 /* force to non-snoop mode for a new VIA controller
1459                  * when BIOS is set
1460                  */
1461                 u8 val;
1462                 pci_read_config_byte(chip->pci, 0x42, &val);
1463                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1464                         snoop = false;
1465         }
1466 
1467         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1468                 snoop = false;
1469 
1470         chip->snoop = snoop;
1471         if (!snoop)
1472                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1473 }
1474 
1475 static void azx_probe_work(struct work_struct *work)
1476 {
1477         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1478         azx_probe_continue(&hda->chip);
1479 }
1480 
1481 /*
1482  * constructor
1483  */
1484 static const struct hdac_io_ops pci_hda_io_ops;
1485 static const struct hda_controller_ops pci_hda_ops;
1486 
1487 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1488                       int dev, unsigned int driver_caps,
1489                       struct azx **rchip)
1490 {
1491         static struct snd_device_ops ops = {
1492                 .dev_disconnect = azx_dev_disconnect,
1493                 .dev_free = azx_dev_free,
1494         };
1495         struct hda_intel *hda;
1496         struct azx *chip;
1497         int err;
1498 
1499         *rchip = NULL;
1500 
1501         err = pci_enable_device(pci);
1502         if (err < 0)
1503                 return err;
1504 
1505         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1506         if (!hda) {
1507                 pci_disable_device(pci);
1508                 return -ENOMEM;
1509         }
1510 
1511         chip = &hda->chip;
1512         mutex_init(&chip->open_mutex);
1513         chip->card = card;
1514         chip->pci = pci;
1515         chip->ops = &pci_hda_ops;
1516         chip->driver_caps = driver_caps;
1517         chip->driver_type = driver_caps & 0xff;
1518         check_msi(chip);
1519         chip->dev_index = dev;
1520         chip->jackpoll_ms = jackpoll_ms;
1521         INIT_LIST_HEAD(&chip->pcm_list);
1522         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1523         INIT_LIST_HEAD(&hda->list);
1524         init_vga_switcheroo(chip);
1525         init_completion(&hda->probe_wait);
1526 
1527         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1528 
1529         check_probe_mask(chip, dev);
1530 
1531         chip->single_cmd = single_cmd;
1532         azx_check_snoop_available(chip);
1533 
1534         if (bdl_pos_adj[dev] < 0) {
1535                 switch (chip->driver_type) {
1536                 case AZX_DRIVER_ICH:
1537                 case AZX_DRIVER_PCH:
1538                         bdl_pos_adj[dev] = 1;
1539                         break;
1540                 default:
1541                         bdl_pos_adj[dev] = 32;
1542                         break;
1543                 }
1544         }
1545         chip->bdl_pos_adj = bdl_pos_adj;
1546 
1547         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1548         if (err < 0) {
1549                 kfree(hda);
1550                 pci_disable_device(pci);
1551                 return err;
1552         }
1553 
1554         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1555         if (err < 0) {
1556                 dev_err(card->dev, "Error creating device [card]!\n");
1557                 azx_free(chip);
1558                 return err;
1559         }
1560 
1561         /* continue probing in work context as may trigger request module */
1562         INIT_WORK(&hda->probe_work, azx_probe_work);
1563 
1564         *rchip = chip;
1565 
1566         return 0;
1567 }
1568 
1569 static int azx_first_init(struct azx *chip)
1570 {
1571         int dev = chip->dev_index;
1572         struct pci_dev *pci = chip->pci;
1573         struct snd_card *card = chip->card;
1574         struct hdac_bus *bus = azx_bus(chip);
1575         int err;
1576         unsigned short gcap;
1577         unsigned int dma_bits = 64;
1578 
1579 #if BITS_PER_LONG != 64
1580         /* Fix up base address on ULI M5461 */
1581         if (chip->driver_type == AZX_DRIVER_ULI) {
1582                 u16 tmp3;
1583                 pci_read_config_word(pci, 0x40, &tmp3);
1584                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1585                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1586         }
1587 #endif
1588 
1589         err = pci_request_regions(pci, "ICH HD audio");
1590         if (err < 0)
1591                 return err;
1592         chip->region_requested = 1;
1593 
1594         bus->addr = pci_resource_start(pci, 0);
1595         bus->remap_addr = pci_ioremap_bar(pci, 0);
1596         if (bus->remap_addr == NULL) {
1597                 dev_err(card->dev, "ioremap error\n");
1598                 return -ENXIO;
1599         }
1600 
1601         if (chip->msi) {
1602                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1603                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1604                         pci->no_64bit_msi = true;
1605                 }
1606                 if (pci_enable_msi(pci) < 0)
1607                         chip->msi = 0;
1608         }
1609 
1610         if (azx_acquire_irq(chip, 0) < 0)
1611                 return -EBUSY;
1612 
1613         pci_set_master(pci);
1614         synchronize_irq(bus->irq);
1615 
1616         gcap = azx_readw(chip, GCAP);
1617         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1618 
1619         /* AMD devices support 40 or 48bit DMA, take the safe one */
1620         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1621                 dma_bits = 40;
1622 
1623         /* disable SB600 64bit support for safety */
1624         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1625                 struct pci_dev *p_smbus;
1626                 dma_bits = 40;
1627                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1628                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1629                                          NULL);
1630                 if (p_smbus) {
1631                         if (p_smbus->revision < 0x30)
1632                                 gcap &= ~AZX_GCAP_64OK;
1633                         pci_dev_put(p_smbus);
1634                 }
1635         }
1636 
1637         /* disable 64bit DMA address on some devices */
1638         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1639                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1640                 gcap &= ~AZX_GCAP_64OK;
1641         }
1642 
1643         /* disable buffer size rounding to 128-byte multiples if supported */
1644         if (align_buffer_size >= 0)
1645                 chip->align_buffer_size = !!align_buffer_size;
1646         else {
1647                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1648                         chip->align_buffer_size = 0;
1649                 else
1650                         chip->align_buffer_size = 1;
1651         }
1652 
1653         /* allow 64bit DMA address if supported by H/W */
1654         if (!(gcap & AZX_GCAP_64OK))
1655                 dma_bits = 32;
1656         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1657                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1658         } else {
1659                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1660                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1661         }
1662 
1663         /* read number of streams from GCAP register instead of using
1664          * hardcoded value
1665          */
1666         chip->capture_streams = (gcap >> 8) & 0x0f;
1667         chip->playback_streams = (gcap >> 12) & 0x0f;
1668         if (!chip->playback_streams && !chip->capture_streams) {
1669                 /* gcap didn't give any info, switching to old method */
1670 
1671                 switch (chip->driver_type) {
1672                 case AZX_DRIVER_ULI:
1673                         chip->playback_streams = ULI_NUM_PLAYBACK;
1674                         chip->capture_streams = ULI_NUM_CAPTURE;
1675                         break;
1676                 case AZX_DRIVER_ATIHDMI:
1677                 case AZX_DRIVER_ATIHDMI_NS:
1678                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1679                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1680                         break;
1681                 case AZX_DRIVER_GENERIC:
1682                 default:
1683                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1684                         chip->capture_streams = ICH6_NUM_CAPTURE;
1685                         break;
1686                 }
1687         }
1688         chip->capture_index_offset = 0;
1689         chip->playback_index_offset = chip->capture_streams;
1690         chip->num_streams = chip->playback_streams + chip->capture_streams;
1691 
1692         /* initialize streams */
1693         err = azx_init_streams(chip);
1694         if (err < 0)
1695                 return err;
1696 
1697         err = azx_alloc_stream_pages(chip);
1698         if (err < 0)
1699                 return err;
1700 
1701         /* initialize chip */
1702         azx_init_pci(chip);
1703 
1704         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1705                 struct hda_intel *hda;
1706 
1707                 hda = container_of(chip, struct hda_intel, chip);
1708                 haswell_set_bclk(hda);
1709         }
1710 
1711         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1712 
1713         /* codec detection */
1714         if (!azx_bus(chip)->codec_mask) {
1715                 dev_err(card->dev, "no codecs found!\n");
1716                 return -ENODEV;
1717         }
1718 
1719         strcpy(card->driver, "HDA-Intel");
1720         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1721                 sizeof(card->shortname));
1722         snprintf(card->longname, sizeof(card->longname),
1723                  "%s at 0x%lx irq %i",
1724                  card->shortname, bus->addr, bus->irq);
1725 
1726         return 0;
1727 }
1728 
1729 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1730 /* callback from request_firmware_nowait() */
1731 static void azx_firmware_cb(const struct firmware *fw, void *context)
1732 {
1733         struct snd_card *card = context;
1734         struct azx *chip = card->private_data;
1735         struct pci_dev *pci = chip->pci;
1736 
1737         if (!fw) {
1738                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1739                 goto error;
1740         }
1741 
1742         chip->fw = fw;
1743         if (!chip->disabled) {
1744                 /* continue probing */
1745                 if (azx_probe_continue(chip))
1746                         goto error;
1747         }
1748         return; /* OK */
1749 
1750  error:
1751         snd_card_free(card);
1752         pci_set_drvdata(pci, NULL);
1753 }
1754 #endif
1755 
1756 /*
1757  * HDA controller ops.
1758  */
1759 
1760 /* PCI register access. */
1761 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1762 {
1763         writel(value, addr);
1764 }
1765 
1766 static u32 pci_azx_readl(u32 __iomem *addr)
1767 {
1768         return readl(addr);
1769 }
1770 
1771 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1772 {
1773         writew(value, addr);
1774 }
1775 
1776 static u16 pci_azx_readw(u16 __iomem *addr)
1777 {
1778         return readw(addr);
1779 }
1780 
1781 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1782 {
1783         writeb(value, addr);
1784 }
1785 
1786 static u8 pci_azx_readb(u8 __iomem *addr)
1787 {
1788         return readb(addr);
1789 }
1790 
1791 static int disable_msi_reset_irq(struct azx *chip)
1792 {
1793         struct hdac_bus *bus = azx_bus(chip);
1794         int err;
1795 
1796         free_irq(bus->irq, chip);
1797         bus->irq = -1;
1798         pci_disable_msi(chip->pci);
1799         chip->msi = 0;
1800         err = azx_acquire_irq(chip, 1);
1801         if (err < 0)
1802                 return err;
1803 
1804         return 0;
1805 }
1806 
1807 /* DMA page allocation helpers.  */
1808 static int dma_alloc_pages(struct hdac_bus *bus,
1809                            int type,
1810                            size_t size,
1811                            struct snd_dma_buffer *buf)
1812 {
1813         struct azx *chip = bus_to_azx(bus);
1814         int err;
1815 
1816         err = snd_dma_alloc_pages(type,
1817                                   bus->dev,
1818                                   size, buf);
1819         if (err < 0)
1820                 return err;
1821         mark_pages_wc(chip, buf, true);
1822         return 0;
1823 }
1824 
1825 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1826 {
1827         struct azx *chip = bus_to_azx(bus);
1828 
1829         mark_pages_wc(chip, buf, false);
1830         snd_dma_free_pages(buf);
1831 }
1832 
1833 static int substream_alloc_pages(struct azx *chip,
1834                                  struct snd_pcm_substream *substream,
1835                                  size_t size)
1836 {
1837         struct azx_dev *azx_dev = get_azx_dev(substream);
1838         int ret;
1839 
1840         mark_runtime_wc(chip, azx_dev, substream, false);
1841         ret = snd_pcm_lib_malloc_pages(substream, size);
1842         if (ret < 0)
1843                 return ret;
1844         mark_runtime_wc(chip, azx_dev, substream, true);
1845         return 0;
1846 }
1847 
1848 static int substream_free_pages(struct azx *chip,
1849                                 struct snd_pcm_substream *substream)
1850 {
1851         struct azx_dev *azx_dev = get_azx_dev(substream);
1852         mark_runtime_wc(chip, azx_dev, substream, false);
1853         return snd_pcm_lib_free_pages(substream);
1854 }
1855 
1856 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1857                              struct vm_area_struct *area)
1858 {
1859 #ifdef CONFIG_X86
1860         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1861         struct azx *chip = apcm->chip;
1862         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1863                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1864 #endif
1865 }
1866 
1867 static const struct hdac_io_ops pci_hda_io_ops = {
1868         .reg_writel = pci_azx_writel,
1869         .reg_readl = pci_azx_readl,
1870         .reg_writew = pci_azx_writew,
1871         .reg_readw = pci_azx_readw,
1872         .reg_writeb = pci_azx_writeb,
1873         .reg_readb = pci_azx_readb,
1874         .dma_alloc_pages = dma_alloc_pages,
1875         .dma_free_pages = dma_free_pages,
1876 };
1877 
1878 static const struct hda_controller_ops pci_hda_ops = {
1879         .disable_msi_reset_irq = disable_msi_reset_irq,
1880         .substream_alloc_pages = substream_alloc_pages,
1881         .substream_free_pages = substream_free_pages,
1882         .pcm_mmap_prepare = pcm_mmap_prepare,
1883         .position_check = azx_position_check,
1884         .link_power = azx_intel_link_power,
1885 };
1886 
1887 static int azx_probe(struct pci_dev *pci,
1888                      const struct pci_device_id *pci_id)
1889 {
1890         static int dev;
1891         struct snd_card *card;
1892         struct hda_intel *hda;
1893         struct azx *chip;
1894         bool schedule_probe;
1895         int err;
1896 
1897         if (dev >= SNDRV_CARDS)
1898                 return -ENODEV;
1899         if (!enable[dev]) {
1900                 dev++;
1901                 return -ENOENT;
1902         }
1903 
1904         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1905                            0, &card);
1906         if (err < 0) {
1907                 dev_err(&pci->dev, "Error creating card!\n");
1908                 return err;
1909         }
1910 
1911         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1912         if (err < 0)
1913                 goto out_free;
1914         card->private_data = chip;
1915         hda = container_of(chip, struct hda_intel, chip);
1916 
1917         pci_set_drvdata(pci, card);
1918 
1919         err = register_vga_switcheroo(chip);
1920         if (err < 0) {
1921                 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1922                 goto out_free;
1923         }
1924 
1925         if (check_hdmi_disabled(pci)) {
1926                 dev_info(card->dev, "VGA controller is disabled\n");
1927                 dev_info(card->dev, "Delaying initialization\n");
1928                 chip->disabled = true;
1929         }
1930 
1931         schedule_probe = !chip->disabled;
1932 
1933 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1934         if (patch[dev] && *patch[dev]) {
1935                 dev_info(card->dev, "Applying patch firmware '%s'\n",
1936                          patch[dev]);
1937                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1938                                               &pci->dev, GFP_KERNEL, card,
1939                                               azx_firmware_cb);
1940                 if (err < 0)
1941                         goto out_free;
1942                 schedule_probe = false; /* continued in azx_firmware_cb() */
1943         }
1944 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1945 
1946 #ifndef CONFIG_SND_HDA_I915
1947         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1948                 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1949 #endif
1950 
1951         if (schedule_probe)
1952                 schedule_work(&hda->probe_work);
1953 
1954         dev++;
1955         if (chip->disabled)
1956                 complete_all(&hda->probe_wait);
1957         return 0;
1958 
1959 out_free:
1960         snd_card_free(card);
1961         return err;
1962 }
1963 
1964 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1965 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1966         [AZX_DRIVER_NVIDIA] = 8,
1967         [AZX_DRIVER_TERA] = 1,
1968 };
1969 
1970 static int azx_probe_continue(struct azx *chip)
1971 {
1972         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1973         struct hdac_bus *bus = azx_bus(chip);
1974         struct pci_dev *pci = chip->pci;
1975         int dev = chip->dev_index;
1976         int err;
1977 
1978         hda->probe_continued = 1;
1979 
1980         /* Request display power well for the HDA controller or codec. For
1981          * Haswell/Broadwell, both the display HDA controller and codec need
1982          * this power. For other platforms, like Baytrail/Braswell, only the
1983          * display codec needs the power and it can be released after probe.
1984          */
1985         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1986                 /* HSW/BDW controllers need this power */
1987                 if (CONTROLLER_IN_GPU(pci))
1988                         hda->need_i915_power = 1;
1989 
1990                 err = snd_hdac_i915_init(bus);
1991                 if (err < 0) {
1992                         /* if the controller is bound only with HDMI/DP
1993                          * (for HSW and BDW), we need to abort the probe;
1994                          * for other chips, still continue probing as other
1995                          * codecs can be on the same link.
1996                          */
1997                         if (CONTROLLER_IN_GPU(pci))
1998                                 goto out_free;
1999                         else
2000                                 goto skip_i915;
2001                 }
2002 
2003                 err = snd_hdac_display_power(bus, true);
2004                 if (err < 0) {
2005                         dev_err(chip->card->dev,
2006                                 "Cannot turn on display power on i915\n");
2007                         goto i915_power_fail;
2008                 }
2009         }
2010 
2011  skip_i915:
2012         err = azx_first_init(chip);
2013         if (err < 0)
2014                 goto out_free;
2015 
2016 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2017         chip->beep_mode = beep_mode[dev];
2018 #endif
2019 
2020         /* create codec instances */
2021         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2022         if (err < 0)
2023                 goto out_free;
2024 
2025 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2026         if (chip->fw) {
2027                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2028                                          chip->fw->data);
2029                 if (err < 0)
2030                         goto out_free;
2031 #ifndef CONFIG_PM
2032                 release_firmware(chip->fw); /* no longer needed */
2033                 chip->fw = NULL;
2034 #endif
2035         }
2036 #endif
2037         if ((probe_only[dev] & 1) == 0) {
2038                 err = azx_codec_configure(chip);
2039                 if (err < 0)
2040                         goto out_free;
2041         }
2042 
2043         err = snd_card_register(chip->card);
2044         if (err < 0)
2045                 goto out_free;
2046 
2047         chip->running = 1;
2048         azx_add_card_list(chip);
2049         snd_hda_set_power_save(&chip->bus, power_save * 1000);
2050         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2051                 pm_runtime_put_noidle(&pci->dev);
2052 
2053 out_free:
2054         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2055                 && !hda->need_i915_power)
2056                 snd_hdac_display_power(bus, false);
2057 
2058 i915_power_fail:
2059         if (err < 0)
2060                 hda->init_failed = 1;
2061         complete_all(&hda->probe_wait);
2062         return err;
2063 }
2064 
2065 static void azx_remove(struct pci_dev *pci)
2066 {
2067         struct snd_card *card = pci_get_drvdata(pci);
2068 
2069         if (card)
2070                 snd_card_free(card);
2071 }
2072 
2073 static void azx_shutdown(struct pci_dev *pci)
2074 {
2075         struct snd_card *card = pci_get_drvdata(pci);
2076         struct azx *chip;
2077 
2078         if (!card)
2079                 return;
2080         chip = card->private_data;
2081         if (chip && chip->running)
2082                 azx_stop_chip(chip);
2083 }
2084 
2085 /* PCI IDs */
2086 static const struct pci_device_id azx_ids[] = {
2087         /* CPT */
2088         { PCI_DEVICE(0x8086, 0x1c20),
2089           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2090         /* PBG */
2091         { PCI_DEVICE(0x8086, 0x1d20),
2092           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2093         /* Panther Point */
2094         { PCI_DEVICE(0x8086, 0x1e20),
2095           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2096         /* Lynx Point */
2097         { PCI_DEVICE(0x8086, 0x8c20),
2098           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2099         /* 9 Series */
2100         { PCI_DEVICE(0x8086, 0x8ca0),
2101           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2102         /* Wellsburg */
2103         { PCI_DEVICE(0x8086, 0x8d20),
2104           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2105         { PCI_DEVICE(0x8086, 0x8d21),
2106           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2107         /* Lynx Point-LP */
2108         { PCI_DEVICE(0x8086, 0x9c20),
2109           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2110         /* Lynx Point-LP */
2111         { PCI_DEVICE(0x8086, 0x9c21),
2112           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2113         /* Wildcat Point-LP */
2114         { PCI_DEVICE(0x8086, 0x9ca0),
2115           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2116         /* Sunrise Point */
2117         { PCI_DEVICE(0x8086, 0xa170),
2118           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2119         /* Sunrise Point-LP */
2120         { PCI_DEVICE(0x8086, 0x9d70),
2121           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2122         /* Haswell */
2123         { PCI_DEVICE(0x8086, 0x0a0c),
2124           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2125         { PCI_DEVICE(0x8086, 0x0c0c),
2126           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2127         { PCI_DEVICE(0x8086, 0x0d0c),
2128           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2129         /* Broadwell */
2130         { PCI_DEVICE(0x8086, 0x160c),
2131           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2132         /* 5 Series/3400 */
2133         { PCI_DEVICE(0x8086, 0x3b56),
2134           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2135         /* Poulsbo */
2136         { PCI_DEVICE(0x8086, 0x811b),
2137           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2138         /* Oaktrail */
2139         { PCI_DEVICE(0x8086, 0x080a),
2140           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2141         /* BayTrail */
2142         { PCI_DEVICE(0x8086, 0x0f04),
2143           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2144         /* Braswell */
2145         { PCI_DEVICE(0x8086, 0x2284),
2146           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2147         /* ICH6 */
2148         { PCI_DEVICE(0x8086, 0x2668),
2149           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2150         /* ICH7 */
2151         { PCI_DEVICE(0x8086, 0x27d8),
2152           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2153         /* ESB2 */
2154         { PCI_DEVICE(0x8086, 0x269a),
2155           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2156         /* ICH8 */
2157         { PCI_DEVICE(0x8086, 0x284b),
2158           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2159         /* ICH9 */
2160         { PCI_DEVICE(0x8086, 0x293e),
2161           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2162         /* ICH9 */
2163         { PCI_DEVICE(0x8086, 0x293f),
2164           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2165         /* ICH10 */
2166         { PCI_DEVICE(0x8086, 0x3a3e),
2167           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2168         /* ICH10 */
2169         { PCI_DEVICE(0x8086, 0x3a6e),
2170           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2171         /* Generic Intel */
2172         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2173           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2174           .class_mask = 0xffffff,
2175           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2176         /* ATI SB 450/600/700/800/900 */
2177         { PCI_DEVICE(0x1002, 0x437b),
2178           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2179         { PCI_DEVICE(0x1002, 0x4383),
2180           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2181         /* AMD Hudson */
2182         { PCI_DEVICE(0x1022, 0x780d),
2183           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2184         /* ATI HDMI */
2185         { PCI_DEVICE(0x1002, 0x1308),
2186           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2187         { PCI_DEVICE(0x1002, 0x157a),
2188           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2189         { PCI_DEVICE(0x1002, 0x793b),
2190           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2191         { PCI_DEVICE(0x1002, 0x7919),
2192           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2193         { PCI_DEVICE(0x1002, 0x960f),
2194           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2195         { PCI_DEVICE(0x1002, 0x970f),
2196           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2197         { PCI_DEVICE(0x1002, 0x9840),
2198           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2199         { PCI_DEVICE(0x1002, 0xaa00),
2200           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2201         { PCI_DEVICE(0x1002, 0xaa08),
2202           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2203         { PCI_DEVICE(0x1002, 0xaa10),
2204           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2205         { PCI_DEVICE(0x1002, 0xaa18),
2206           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2207         { PCI_DEVICE(0x1002, 0xaa20),
2208           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2209         { PCI_DEVICE(0x1002, 0xaa28),
2210           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2211         { PCI_DEVICE(0x1002, 0xaa30),
2212           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2213         { PCI_DEVICE(0x1002, 0xaa38),
2214           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2215         { PCI_DEVICE(0x1002, 0xaa40),
2216           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2217         { PCI_DEVICE(0x1002, 0xaa48),
2218           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2219         { PCI_DEVICE(0x1002, 0xaa50),
2220           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2221         { PCI_DEVICE(0x1002, 0xaa58),
2222           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2223         { PCI_DEVICE(0x1002, 0xaa60),
2224           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2225         { PCI_DEVICE(0x1002, 0xaa68),
2226           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2227         { PCI_DEVICE(0x1002, 0xaa80),
2228           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2229         { PCI_DEVICE(0x1002, 0xaa88),
2230           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2231         { PCI_DEVICE(0x1002, 0xaa90),
2232           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2233         { PCI_DEVICE(0x1002, 0xaa98),
2234           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2235         { PCI_DEVICE(0x1002, 0x9902),
2236           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2237         { PCI_DEVICE(0x1002, 0xaaa0),
2238           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2239         { PCI_DEVICE(0x1002, 0xaaa8),
2240           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2241         { PCI_DEVICE(0x1002, 0xaab0),
2242           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2243         { PCI_DEVICE(0x1002, 0xaac0),
2244           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2245         { PCI_DEVICE(0x1002, 0xaac8),
2246           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2247         { PCI_DEVICE(0x1002, 0xaad8),
2248           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2249         { PCI_DEVICE(0x1002, 0xaae8),
2250           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2251         /* VIA VT8251/VT8237A */
2252         { PCI_DEVICE(0x1106, 0x3288),
2253           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2254         /* VIA GFX VT7122/VX900 */
2255         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2256         /* VIA GFX VT6122/VX11 */
2257         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2258         /* SIS966 */
2259         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2260         /* ULI M5461 */
2261         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2262         /* NVIDIA MCP */
2263         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2264           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2265           .class_mask = 0xffffff,
2266           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2267         /* Teradici */
2268         { PCI_DEVICE(0x6549, 0x1200),
2269           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2270         { PCI_DEVICE(0x6549, 0x2200),
2271           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2272         /* Creative X-Fi (CA0110-IBG) */
2273         /* CTHDA chips */
2274         { PCI_DEVICE(0x1102, 0x0010),
2275           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2276         { PCI_DEVICE(0x1102, 0x0012),
2277           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2278 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2279         /* the following entry conflicts with snd-ctxfi driver,
2280          * as ctxfi driver mutates from HD-audio to native mode with
2281          * a special command sequence.
2282          */
2283         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2284           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2285           .class_mask = 0xffffff,
2286           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2287           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2288 #else
2289         /* this entry seems still valid -- i.e. without emu20kx chip */
2290         { PCI_DEVICE(0x1102, 0x0009),
2291           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2292           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2293 #endif
2294         /* CM8888 */
2295         { PCI_DEVICE(0x13f6, 0x5011),
2296           .driver_data = AZX_DRIVER_CMEDIA |
2297           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2298         /* Vortex86MX */
2299         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2300         /* VMware HDAudio */
2301         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2302         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2303         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2304           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2305           .class_mask = 0xffffff,
2306           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2307         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2308           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2309           .class_mask = 0xffffff,
2310           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2311         { 0, }
2312 };
2313 MODULE_DEVICE_TABLE(pci, azx_ids);
2314 
2315 /* pci_driver definition */
2316 static struct pci_driver azx_driver = {
2317         .name = KBUILD_MODNAME,
2318         .id_table = azx_ids,
2319         .probe = azx_probe,
2320         .remove = azx_remove,
2321         .shutdown = azx_shutdown,
2322         .driver = {
2323                 .pm = AZX_PM_OPS,
2324         },
2325 };
2326 
2327 module_pci_driver(azx_driver);
2328 

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