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Linux/sound/pci/hda/hda_intel.c

  1 /*
  2  *
  3  *  hda_intel.c - Implementation of primary alsa driver code base
  4  *                for Intel HD Audio.
  5  *
  6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
  7  *
  8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  9  *                     PeiSen Hou <pshou@realtek.com.tw>
 10  *
 11  *  This program is free software; you can redistribute it and/or modify it
 12  *  under the terms of the GNU General Public License as published by the Free
 13  *  Software Foundation; either version 2 of the License, or (at your option)
 14  *  any later version.
 15  *
 16  *  This program is distributed in the hope that it will be useful, but WITHOUT
 17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 19  *  more details.
 20  *
 21  *  You should have received a copy of the GNU General Public License along with
 22  *  this program; if not, write to the Free Software Foundation, Inc., 59
 23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 24  *
 25  *  CONTACTS:
 26  *
 27  *  Matt Jared          matt.jared@intel.com
 28  *  Andy Kopp           andy.kopp@intel.com
 29  *  Dan Kogan           dan.d.kogan@intel.com
 30  *
 31  *  CHANGES:
 32  *
 33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
 34  * 
 35  */
 36 
 37 #include <linux/delay.h>
 38 #include <linux/interrupt.h>
 39 #include <linux/kernel.h>
 40 #include <linux/module.h>
 41 #include <linux/dma-mapping.h>
 42 #include <linux/moduleparam.h>
 43 #include <linux/init.h>
 44 #include <linux/slab.h>
 45 #include <linux/pci.h>
 46 #include <linux/mutex.h>
 47 #include <linux/io.h>
 48 #include <linux/pm_runtime.h>
 49 #include <linux/clocksource.h>
 50 #include <linux/time.h>
 51 #include <linux/completion.h>
 52 
 53 #ifdef CONFIG_X86
 54 /* for snoop control */
 55 #include <asm/pgtable.h>
 56 #include <asm/cacheflush.h>
 57 #endif
 58 #include <sound/core.h>
 59 #include <sound/initval.h>
 60 #include <sound/hdaudio.h>
 61 #include <sound/hda_i915.h>
 62 #include <linux/vgaarb.h>
 63 #include <linux/vga_switcheroo.h>
 64 #include <linux/firmware.h>
 65 #include "hda_codec.h"
 66 #include "hda_controller.h"
 67 #include "hda_intel.h"
 68 
 69 #define CREATE_TRACE_POINTS
 70 #include "hda_intel_trace.h"
 71 
 72 /* position fix mode */
 73 enum {
 74         POS_FIX_AUTO,
 75         POS_FIX_LPIB,
 76         POS_FIX_POSBUF,
 77         POS_FIX_VIACOMBO,
 78         POS_FIX_COMBO,
 79 };
 80 
 81 /* Defines for ATI HD Audio support in SB450 south bridge */
 82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 84 
 85 /* Defines for Nvidia HDA support */
 86 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 87 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 88 #define NVIDIA_HDA_ISTRM_COH          0x4d
 89 #define NVIDIA_HDA_OSTRM_COH          0x4c
 90 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 91 
 92 /* Defines for Intel SCH HDA snoop control */
 93 #define INTEL_SCH_HDA_DEVC      0x78
 94 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 95 
 96 /* Define IN stream 0 FIFO size offset in VIA controller */
 97 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 98 /* Define VIA HD Audio Device ID*/
 99 #define VIA_HDAC_DEVICE_ID              0x3288
100 
101 /* max number of SDs */
102 /* ICH, ATI and VIA have 4 playback and 4 capture */
103 #define ICH6_NUM_CAPTURE        4
104 #define ICH6_NUM_PLAYBACK       4
105 
106 /* ULI has 6 playback and 5 capture */
107 #define ULI_NUM_CAPTURE         5
108 #define ULI_NUM_PLAYBACK        6
109 
110 /* ATI HDMI may have up to 8 playbacks and 0 capture */
111 #define ATIHDMI_NUM_CAPTURE     0
112 #define ATIHDMI_NUM_PLAYBACK    8
113 
114 /* TERA has 4 playback and 3 capture */
115 #define TERA_NUM_CAPTURE        3
116 #define TERA_NUM_PLAYBACK       4
117 
118 
119 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
120 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
121 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
122 static char *model[SNDRV_CARDS];
123 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
124 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
125 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
126 static int probe_only[SNDRV_CARDS];
127 static int jackpoll_ms[SNDRV_CARDS];
128 static bool single_cmd;
129 static int enable_msi = -1;
130 #ifdef CONFIG_SND_HDA_PATCH_LOADER
131 static char *patch[SNDRV_CARDS];
132 #endif
133 #ifdef CONFIG_SND_HDA_INPUT_BEEP
134 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
135                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
136 #endif
137 
138 module_param_array(index, int, NULL, 0444);
139 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
140 module_param_array(id, charp, NULL, 0444);
141 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
142 module_param_array(enable, bool, NULL, 0444);
143 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
144 module_param_array(model, charp, NULL, 0444);
145 MODULE_PARM_DESC(model, "Use the given board model.");
146 module_param_array(position_fix, int, NULL, 0444);
147 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
148                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
149 module_param_array(bdl_pos_adj, int, NULL, 0644);
150 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
151 module_param_array(probe_mask, int, NULL, 0444);
152 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
153 module_param_array(probe_only, int, NULL, 0444);
154 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
155 module_param_array(jackpoll_ms, int, NULL, 0444);
156 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
157 module_param(single_cmd, bool, 0444);
158 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
159                  "(for debugging only).");
160 module_param(enable_msi, bint, 0444);
161 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
162 #ifdef CONFIG_SND_HDA_PATCH_LOADER
163 module_param_array(patch, charp, NULL, 0444);
164 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
165 #endif
166 #ifdef CONFIG_SND_HDA_INPUT_BEEP
167 module_param_array(beep_mode, bool, NULL, 0444);
168 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
169                             "(0=off, 1=on) (default=1).");
170 #endif
171 
172 #ifdef CONFIG_PM
173 static int param_set_xint(const char *val, const struct kernel_param *kp);
174 static const struct kernel_param_ops param_ops_xint = {
175         .set = param_set_xint,
176         .get = param_get_int,
177 };
178 #define param_check_xint param_check_int
179 
180 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
181 module_param(power_save, xint, 0644);
182 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
183                  "(in second, 0 = disable).");
184 
185 /* reset the HD-audio controller in power save mode.
186  * this may give more power-saving, but will take longer time to
187  * wake up.
188  */
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
192 #else
193 #define power_save      0
194 #endif /* CONFIG_PM */
195 
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199                 "Force buffer and period sizes to be multiple of 128 bytes.");
200 
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop               true
207 #endif
208 
209 
210 MODULE_LICENSE("GPL");
211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212                          "{Intel, ICH6M},"
213                          "{Intel, ICH7},"
214                          "{Intel, ESB2},"
215                          "{Intel, ICH8},"
216                          "{Intel, ICH9},"
217                          "{Intel, ICH10},"
218                          "{Intel, PCH},"
219                          "{Intel, CPT},"
220                          "{Intel, PPT},"
221                          "{Intel, LPT},"
222                          "{Intel, LPT_LP},"
223                          "{Intel, WPT_LP},"
224                          "{Intel, SPT},"
225                          "{Intel, SPT_LP},"
226                          "{Intel, HPT},"
227                          "{Intel, PBG},"
228                          "{Intel, SCH},"
229                          "{ATI, SB450},"
230                          "{ATI, SB600},"
231                          "{ATI, RS600},"
232                          "{ATI, RS690},"
233                          "{ATI, RS780},"
234                          "{ATI, R600},"
235                          "{ATI, RV630},"
236                          "{ATI, RV610},"
237                          "{ATI, RV670},"
238                          "{ATI, RV635},"
239                          "{ATI, RV620},"
240                          "{ATI, RV770},"
241                          "{VIA, VT8251},"
242                          "{VIA, VT8237A},"
243                          "{SiS, SIS966},"
244                          "{ULI, M5461}}");
245 MODULE_DESCRIPTION("Intel HDA driver");
246 
247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
249 #define SUPPORT_VGA_SWITCHEROO
250 #endif
251 #endif
252 
253 
254 /*
255  */
256 
257 /* driver types */
258 enum {
259         AZX_DRIVER_ICH,
260         AZX_DRIVER_PCH,
261         AZX_DRIVER_SCH,
262         AZX_DRIVER_HDMI,
263         AZX_DRIVER_ATI,
264         AZX_DRIVER_ATIHDMI,
265         AZX_DRIVER_ATIHDMI_NS,
266         AZX_DRIVER_VIA,
267         AZX_DRIVER_SIS,
268         AZX_DRIVER_ULI,
269         AZX_DRIVER_NVIDIA,
270         AZX_DRIVER_TERA,
271         AZX_DRIVER_CTX,
272         AZX_DRIVER_CTHDA,
273         AZX_DRIVER_CMEDIA,
274         AZX_DRIVER_GENERIC,
275         AZX_NUM_DRIVERS, /* keep this as last entry */
276 };
277 
278 #define azx_get_snoop_type(chip) \
279         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281 
282 /* quirks for old Intel chipsets */
283 #define AZX_DCAPS_INTEL_ICH \
284         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
285 
286 /* quirks for Intel PCH */
287 #define AZX_DCAPS_INTEL_PCH_NOPM \
288         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
289          AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
290 
291 #define AZX_DCAPS_INTEL_PCH \
292         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
293 
294 #define AZX_DCAPS_INTEL_HASWELL \
295         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
296          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
297          AZX_DCAPS_SNOOP_TYPE(SCH))
298 
299 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
300 #define AZX_DCAPS_INTEL_BROADWELL \
301         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
302          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
303          AZX_DCAPS_SNOOP_TYPE(SCH))
304 
305 #define AZX_DCAPS_INTEL_BAYTRAIL \
306         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
307 
308 #define AZX_DCAPS_INTEL_BRASWELL \
309         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
310 
311 #define AZX_DCAPS_INTEL_SKYLAKE \
312         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
313          AZX_DCAPS_I915_POWERWELL)
314 
315 #define AZX_DCAPS_INTEL_BROXTON \
316         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
317          AZX_DCAPS_I915_POWERWELL)
318 
319 /* quirks for ATI SB / AMD Hudson */
320 #define AZX_DCAPS_PRESET_ATI_SB \
321         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
322          AZX_DCAPS_SNOOP_TYPE(ATI))
323 
324 /* quirks for ATI/AMD HDMI */
325 #define AZX_DCAPS_PRESET_ATI_HDMI \
326         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
327          AZX_DCAPS_NO_MSI64)
328 
329 /* quirks for ATI HDMI with snoop off */
330 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
331         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
332 
333 /* quirks for Nvidia */
334 #define AZX_DCAPS_PRESET_NVIDIA \
335         (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
336          AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
337          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
338 
339 #define AZX_DCAPS_PRESET_CTHDA \
340         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
341          AZX_DCAPS_NO_64BIT |\
342          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
343 
344 /*
345  * vga_switcheroo support
346  */
347 #ifdef SUPPORT_VGA_SWITCHEROO
348 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
349 #else
350 #define use_vga_switcheroo(chip)        0
351 #endif
352 
353 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
354                                         ((pci)->device == 0x0c0c) || \
355                                         ((pci)->device == 0x0d0c) || \
356                                         ((pci)->device == 0x160c))
357 
358 #define IS_BROXTON(pci) ((pci)->device == 0x5a98)
359 
360 static char *driver_short_names[] = {
361         [AZX_DRIVER_ICH] = "HDA Intel",
362         [AZX_DRIVER_PCH] = "HDA Intel PCH",
363         [AZX_DRIVER_SCH] = "HDA Intel MID",
364         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
365         [AZX_DRIVER_ATI] = "HDA ATI SB",
366         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
367         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
368         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
369         [AZX_DRIVER_SIS] = "HDA SIS966",
370         [AZX_DRIVER_ULI] = "HDA ULI M5461",
371         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
372         [AZX_DRIVER_TERA] = "HDA Teradici", 
373         [AZX_DRIVER_CTX] = "HDA Creative", 
374         [AZX_DRIVER_CTHDA] = "HDA Creative",
375         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
376         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
377 };
378 
379 #ifdef CONFIG_X86
380 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
381 {
382         int pages;
383 
384         if (azx_snoop(chip))
385                 return;
386         if (!dmab || !dmab->area || !dmab->bytes)
387                 return;
388 
389 #ifdef CONFIG_SND_DMA_SGBUF
390         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
391                 struct snd_sg_buf *sgbuf = dmab->private_data;
392                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
393                         return; /* deal with only CORB/RIRB buffers */
394                 if (on)
395                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
396                 else
397                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
398                 return;
399         }
400 #endif
401 
402         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
403         if (on)
404                 set_memory_wc((unsigned long)dmab->area, pages);
405         else
406                 set_memory_wb((unsigned long)dmab->area, pages);
407 }
408 
409 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
410                                  bool on)
411 {
412         __mark_pages_wc(chip, buf, on);
413 }
414 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
415                                    struct snd_pcm_substream *substream, bool on)
416 {
417         if (azx_dev->wc_marked != on) {
418                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
419                 azx_dev->wc_marked = on;
420         }
421 }
422 #else
423 /* NOP for other archs */
424 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
425                                  bool on)
426 {
427 }
428 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
429                                    struct snd_pcm_substream *substream, bool on)
430 {
431 }
432 #endif
433 
434 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
435 
436 /*
437  * initialize the PCI registers
438  */
439 /* update bits in a PCI register byte */
440 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
441                             unsigned char mask, unsigned char val)
442 {
443         unsigned char data;
444 
445         pci_read_config_byte(pci, reg, &data);
446         data &= ~mask;
447         data |= (val & mask);
448         pci_write_config_byte(pci, reg, data);
449 }
450 
451 static void azx_init_pci(struct azx *chip)
452 {
453         int snoop_type = azx_get_snoop_type(chip);
454 
455         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
456          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
457          * Ensuring these bits are 0 clears playback static on some HD Audio
458          * codecs.
459          * The PCI register TCSEL is defined in the Intel manuals.
460          */
461         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
462                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
463                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
464         }
465 
466         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
467          * we need to enable snoop.
468          */
469         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
470                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
471                         azx_snoop(chip));
472                 update_pci_byte(chip->pci,
473                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
474                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
475         }
476 
477         /* For NVIDIA HDA, enable snoop */
478         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
479                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
480                         azx_snoop(chip));
481                 update_pci_byte(chip->pci,
482                                 NVIDIA_HDA_TRANSREG_ADDR,
483                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
484                 update_pci_byte(chip->pci,
485                                 NVIDIA_HDA_ISTRM_COH,
486                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
487                 update_pci_byte(chip->pci,
488                                 NVIDIA_HDA_OSTRM_COH,
489                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
490         }
491 
492         /* Enable SCH/PCH snoop if needed */
493         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
494                 unsigned short snoop;
495                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
496                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
497                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
498                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
499                         if (!azx_snoop(chip))
500                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
501                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
502                         pci_read_config_word(chip->pci,
503                                 INTEL_SCH_HDA_DEVC, &snoop);
504                 }
505                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
506                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
507                         "Disabled" : "Enabled");
508         }
509 }
510 
511 /*
512  * In BXT-P A0, HD-Audio DMA requests is later than expected,
513  * and makes an audio stream sensitive to system latencies when
514  * 24/32 bits are playing.
515  * Adjusting threshold of DMA fifo to force the DMA request
516  * sooner to improve latency tolerance at the expense of power.
517  */
518 static void bxt_reduce_dma_latency(struct azx *chip)
519 {
520         u32 val;
521 
522         val = azx_readl(chip, SKL_EM4L);
523         val &= (0x3 << 20);
524         azx_writel(chip, SKL_EM4L, val);
525 }
526 
527 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
528 {
529         struct hdac_bus *bus = azx_bus(chip);
530         struct pci_dev *pci = chip->pci;
531 
532         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
533                 snd_hdac_set_codec_wakeup(bus, true);
534         azx_init_chip(chip, full_reset);
535         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
536                 snd_hdac_set_codec_wakeup(bus, false);
537 
538         /* reduce dma latency to avoid noise */
539         if (IS_BROXTON(pci))
540                 bxt_reduce_dma_latency(chip);
541 }
542 
543 /* calculate runtime delay from LPIB */
544 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
545                                    unsigned int pos)
546 {
547         struct snd_pcm_substream *substream = azx_dev->core.substream;
548         int stream = substream->stream;
549         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
550         int delay;
551 
552         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
553                 delay = pos - lpib_pos;
554         else
555                 delay = lpib_pos - pos;
556         if (delay < 0) {
557                 if (delay >= azx_dev->core.delay_negative_threshold)
558                         delay = 0;
559                 else
560                         delay += azx_dev->core.bufsize;
561         }
562 
563         if (delay >= azx_dev->core.period_bytes) {
564                 dev_info(chip->card->dev,
565                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
566                          delay, azx_dev->core.period_bytes);
567                 delay = 0;
568                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
569                 chip->get_delay[stream] = NULL;
570         }
571 
572         return bytes_to_frames(substream->runtime, delay);
573 }
574 
575 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
576 
577 /* called from IRQ */
578 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
579 {
580         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
581         int ok;
582 
583         ok = azx_position_ok(chip, azx_dev);
584         if (ok == 1) {
585                 azx_dev->irq_pending = 0;
586                 return ok;
587         } else if (ok == 0) {
588                 /* bogus IRQ, process it later */
589                 azx_dev->irq_pending = 1;
590                 schedule_work(&hda->irq_pending_work);
591         }
592         return 0;
593 }
594 
595 /* Enable/disable i915 display power for the link */
596 static int azx_intel_link_power(struct azx *chip, bool enable)
597 {
598         struct hdac_bus *bus = azx_bus(chip);
599 
600         return snd_hdac_display_power(bus, enable);
601 }
602 
603 /*
604  * Check whether the current DMA position is acceptable for updating
605  * periods.  Returns non-zero if it's OK.
606  *
607  * Many HD-audio controllers appear pretty inaccurate about
608  * the update-IRQ timing.  The IRQ is issued before actually the
609  * data is processed.  So, we need to process it afterwords in a
610  * workqueue.
611  */
612 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
613 {
614         struct snd_pcm_substream *substream = azx_dev->core.substream;
615         int stream = substream->stream;
616         u32 wallclk;
617         unsigned int pos;
618 
619         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
620         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
621                 return -1;      /* bogus (too early) interrupt */
622 
623         if (chip->get_position[stream])
624                 pos = chip->get_position[stream](chip, azx_dev);
625         else { /* use the position buffer as default */
626                 pos = azx_get_pos_posbuf(chip, azx_dev);
627                 if (!pos || pos == (u32)-1) {
628                         dev_info(chip->card->dev,
629                                  "Invalid position buffer, using LPIB read method instead.\n");
630                         chip->get_position[stream] = azx_get_pos_lpib;
631                         if (chip->get_position[0] == azx_get_pos_lpib &&
632                             chip->get_position[1] == azx_get_pos_lpib)
633                                 azx_bus(chip)->use_posbuf = false;
634                         pos = azx_get_pos_lpib(chip, azx_dev);
635                         chip->get_delay[stream] = NULL;
636                 } else {
637                         chip->get_position[stream] = azx_get_pos_posbuf;
638                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
639                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
640                 }
641         }
642 
643         if (pos >= azx_dev->core.bufsize)
644                 pos = 0;
645 
646         if (WARN_ONCE(!azx_dev->core.period_bytes,
647                       "hda-intel: zero azx_dev->period_bytes"))
648                 return -1; /* this shouldn't happen! */
649         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
650             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
651                 /* NG - it's below the first next period boundary */
652                 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
653         azx_dev->core.start_wallclk += wallclk;
654         return 1; /* OK, it's fine */
655 }
656 
657 /*
658  * The work for pending PCM period updates.
659  */
660 static void azx_irq_pending_work(struct work_struct *work)
661 {
662         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
663         struct azx *chip = &hda->chip;
664         struct hdac_bus *bus = azx_bus(chip);
665         struct hdac_stream *s;
666         int pending, ok;
667 
668         if (!hda->irq_pending_warned) {
669                 dev_info(chip->card->dev,
670                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
671                          chip->card->number);
672                 hda->irq_pending_warned = 1;
673         }
674 
675         for (;;) {
676                 pending = 0;
677                 spin_lock_irq(&bus->reg_lock);
678                 list_for_each_entry(s, &bus->stream_list, list) {
679                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
680                         if (!azx_dev->irq_pending ||
681                             !s->substream ||
682                             !s->running)
683                                 continue;
684                         ok = azx_position_ok(chip, azx_dev);
685                         if (ok > 0) {
686                                 azx_dev->irq_pending = 0;
687                                 spin_unlock(&bus->reg_lock);
688                                 snd_pcm_period_elapsed(s->substream);
689                                 spin_lock(&bus->reg_lock);
690                         } else if (ok < 0) {
691                                 pending = 0;    /* too early */
692                         } else
693                                 pending++;
694                 }
695                 spin_unlock_irq(&bus->reg_lock);
696                 if (!pending)
697                         return;
698                 msleep(1);
699         }
700 }
701 
702 /* clear irq_pending flags and assure no on-going workq */
703 static void azx_clear_irq_pending(struct azx *chip)
704 {
705         struct hdac_bus *bus = azx_bus(chip);
706         struct hdac_stream *s;
707 
708         spin_lock_irq(&bus->reg_lock);
709         list_for_each_entry(s, &bus->stream_list, list) {
710                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
711                 azx_dev->irq_pending = 0;
712         }
713         spin_unlock_irq(&bus->reg_lock);
714 }
715 
716 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
717 {
718         struct hdac_bus *bus = azx_bus(chip);
719 
720         if (request_irq(chip->pci->irq, azx_interrupt,
721                         chip->msi ? 0 : IRQF_SHARED,
722                         KBUILD_MODNAME, chip)) {
723                 dev_err(chip->card->dev,
724                         "unable to grab IRQ %d, disabling device\n",
725                         chip->pci->irq);
726                 if (do_disconnect)
727                         snd_card_disconnect(chip->card);
728                 return -1;
729         }
730         bus->irq = chip->pci->irq;
731         pci_intx(chip->pci, !chip->msi);
732         return 0;
733 }
734 
735 /* get the current DMA position with correction on VIA chips */
736 static unsigned int azx_via_get_position(struct azx *chip,
737                                          struct azx_dev *azx_dev)
738 {
739         unsigned int link_pos, mini_pos, bound_pos;
740         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
741         unsigned int fifo_size;
742 
743         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
744         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
745                 /* Playback, no problem using link position */
746                 return link_pos;
747         }
748 
749         /* Capture */
750         /* For new chipset,
751          * use mod to get the DMA position just like old chipset
752          */
753         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
754         mod_dma_pos %= azx_dev->core.period_bytes;
755 
756         /* azx_dev->fifo_size can't get FIFO size of in stream.
757          * Get from base address + offset.
758          */
759         fifo_size = readw(azx_bus(chip)->remap_addr +
760                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
761 
762         if (azx_dev->insufficient) {
763                 /* Link position never gather than FIFO size */
764                 if (link_pos <= fifo_size)
765                         return 0;
766 
767                 azx_dev->insufficient = 0;
768         }
769 
770         if (link_pos <= fifo_size)
771                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
772         else
773                 mini_pos = link_pos - fifo_size;
774 
775         /* Find nearest previous boudary */
776         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
777         mod_link_pos = link_pos % azx_dev->core.period_bytes;
778         if (mod_link_pos >= fifo_size)
779                 bound_pos = link_pos - mod_link_pos;
780         else if (mod_dma_pos >= mod_mini_pos)
781                 bound_pos = mini_pos - mod_mini_pos;
782         else {
783                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
784                 if (bound_pos >= azx_dev->core.bufsize)
785                         bound_pos = 0;
786         }
787 
788         /* Calculate real DMA position we want */
789         return bound_pos + mod_dma_pos;
790 }
791 
792 #ifdef CONFIG_PM
793 static DEFINE_MUTEX(card_list_lock);
794 static LIST_HEAD(card_list);
795 
796 static void azx_add_card_list(struct azx *chip)
797 {
798         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
799         mutex_lock(&card_list_lock);
800         list_add(&hda->list, &card_list);
801         mutex_unlock(&card_list_lock);
802 }
803 
804 static void azx_del_card_list(struct azx *chip)
805 {
806         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
807         mutex_lock(&card_list_lock);
808         list_del_init(&hda->list);
809         mutex_unlock(&card_list_lock);
810 }
811 
812 /* trigger power-save check at writing parameter */
813 static int param_set_xint(const char *val, const struct kernel_param *kp)
814 {
815         struct hda_intel *hda;
816         struct azx *chip;
817         int prev = power_save;
818         int ret = param_set_int(val, kp);
819 
820         if (ret || prev == power_save)
821                 return ret;
822 
823         mutex_lock(&card_list_lock);
824         list_for_each_entry(hda, &card_list, list) {
825                 chip = &hda->chip;
826                 if (!hda->probe_continued || chip->disabled)
827                         continue;
828                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
829         }
830         mutex_unlock(&card_list_lock);
831         return 0;
832 }
833 #else
834 #define azx_add_card_list(chip) /* NOP */
835 #define azx_del_card_list(chip) /* NOP */
836 #endif /* CONFIG_PM */
837 
838 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
839  * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
840  * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
841  * BCLK = CDCLK * M / N
842  * The values will be lost when the display power well is disabled and need to
843  * be restored to avoid abnormal playback speed.
844  */
845 static void haswell_set_bclk(struct hda_intel *hda)
846 {
847         struct azx *chip = &hda->chip;
848         int cdclk_freq;
849         unsigned int bclk_m, bclk_n;
850 
851         if (!hda->need_i915_power)
852                 return;
853 
854         cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
855         switch (cdclk_freq) {
856         case 337500:
857                 bclk_m = 16;
858                 bclk_n = 225;
859                 break;
860 
861         case 450000:
862         default: /* default CDCLK 450MHz */
863                 bclk_m = 4;
864                 bclk_n = 75;
865                 break;
866 
867         case 540000:
868                 bclk_m = 4;
869                 bclk_n = 90;
870                 break;
871 
872         case 675000:
873                 bclk_m = 8;
874                 bclk_n = 225;
875                 break;
876         }
877 
878         azx_writew(chip, HSW_EM4, bclk_m);
879         azx_writew(chip, HSW_EM5, bclk_n);
880 }
881 
882 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
883 /*
884  * power management
885  */
886 static int azx_suspend(struct device *dev)
887 {
888         struct snd_card *card = dev_get_drvdata(dev);
889         struct azx *chip;
890         struct hda_intel *hda;
891         struct hdac_bus *bus;
892 
893         if (!card)
894                 return 0;
895 
896         chip = card->private_data;
897         hda = container_of(chip, struct hda_intel, chip);
898         if (chip->disabled || hda->init_failed || !chip->running)
899                 return 0;
900 
901         bus = azx_bus(chip);
902         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
903         azx_clear_irq_pending(chip);
904         azx_stop_chip(chip);
905         azx_enter_link_reset(chip);
906         if (bus->irq >= 0) {
907                 free_irq(bus->irq, chip);
908                 bus->irq = -1;
909         }
910 
911         if (chip->msi)
912                 pci_disable_msi(chip->pci);
913         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
914                 && hda->need_i915_power)
915                 snd_hdac_display_power(bus, false);
916 
917         trace_azx_suspend(chip);
918         return 0;
919 }
920 
921 static int azx_resume(struct device *dev)
922 {
923         struct pci_dev *pci = to_pci_dev(dev);
924         struct snd_card *card = dev_get_drvdata(dev);
925         struct azx *chip;
926         struct hda_intel *hda;
927 
928         if (!card)
929                 return 0;
930 
931         chip = card->private_data;
932         hda = container_of(chip, struct hda_intel, chip);
933         if (chip->disabled || hda->init_failed || !chip->running)
934                 return 0;
935 
936         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
937                 && hda->need_i915_power) {
938                 snd_hdac_display_power(azx_bus(chip), true);
939                 haswell_set_bclk(hda);
940         }
941         if (chip->msi)
942                 if (pci_enable_msi(pci) < 0)
943                         chip->msi = 0;
944         if (azx_acquire_irq(chip, 1) < 0)
945                 return -EIO;
946         azx_init_pci(chip);
947 
948         hda_intel_init_chip(chip, true);
949 
950         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
951 
952         trace_azx_resume(chip);
953         return 0;
954 }
955 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
956 
957 #ifdef CONFIG_PM_SLEEP
958 /* put codec down to D3 at hibernation for Intel SKL+;
959  * otherwise BIOS may still access the codec and screw up the driver
960  */
961 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
962 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
963 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
964 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci))
965 
966 static int azx_freeze_noirq(struct device *dev)
967 {
968         struct pci_dev *pci = to_pci_dev(dev);
969 
970         if (IS_SKL_PLUS(pci))
971                 pci_set_power_state(pci, PCI_D3hot);
972 
973         return 0;
974 }
975 
976 static int azx_thaw_noirq(struct device *dev)
977 {
978         struct pci_dev *pci = to_pci_dev(dev);
979 
980         if (IS_SKL_PLUS(pci))
981                 pci_set_power_state(pci, PCI_D0);
982 
983         return 0;
984 }
985 #endif /* CONFIG_PM_SLEEP */
986 
987 #ifdef CONFIG_PM
988 static int azx_runtime_suspend(struct device *dev)
989 {
990         struct snd_card *card = dev_get_drvdata(dev);
991         struct azx *chip;
992         struct hda_intel *hda;
993 
994         if (!card)
995                 return 0;
996 
997         chip = card->private_data;
998         hda = container_of(chip, struct hda_intel, chip);
999         if (chip->disabled || hda->init_failed)
1000                 return 0;
1001 
1002         if (!azx_has_pm_runtime(chip))
1003                 return 0;
1004 
1005         /* enable controller wake up event */
1006         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1007                   STATESTS_INT_MASK);
1008 
1009         azx_stop_chip(chip);
1010         azx_enter_link_reset(chip);
1011         azx_clear_irq_pending(chip);
1012         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1013                 && hda->need_i915_power)
1014                 snd_hdac_display_power(azx_bus(chip), false);
1015 
1016         trace_azx_runtime_suspend(chip);
1017         return 0;
1018 }
1019 
1020 static int azx_runtime_resume(struct device *dev)
1021 {
1022         struct snd_card *card = dev_get_drvdata(dev);
1023         struct azx *chip;
1024         struct hda_intel *hda;
1025         struct hdac_bus *bus;
1026         struct hda_codec *codec;
1027         int status;
1028 
1029         if (!card)
1030                 return 0;
1031 
1032         chip = card->private_data;
1033         hda = container_of(chip, struct hda_intel, chip);
1034         if (chip->disabled || hda->init_failed)
1035                 return 0;
1036 
1037         if (!azx_has_pm_runtime(chip))
1038                 return 0;
1039 
1040         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1041                 bus = azx_bus(chip);
1042                 if (hda->need_i915_power) {
1043                         snd_hdac_display_power(bus, true);
1044                         haswell_set_bclk(hda);
1045                 } else {
1046                         /* toggle codec wakeup bit for STATESTS read */
1047                         snd_hdac_set_codec_wakeup(bus, true);
1048                         snd_hdac_set_codec_wakeup(bus, false);
1049                 }
1050         }
1051 
1052         /* Read STATESTS before controller reset */
1053         status = azx_readw(chip, STATESTS);
1054 
1055         azx_init_pci(chip);
1056         hda_intel_init_chip(chip, true);
1057 
1058         if (status) {
1059                 list_for_each_codec(codec, &chip->bus)
1060                         if (status & (1 << codec->addr))
1061                                 schedule_delayed_work(&codec->jackpoll_work,
1062                                                       codec->jackpoll_interval);
1063         }
1064 
1065         /* disable controller Wake Up event*/
1066         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1067                         ~STATESTS_INT_MASK);
1068 
1069         trace_azx_runtime_resume(chip);
1070         return 0;
1071 }
1072 
1073 static int azx_runtime_idle(struct device *dev)
1074 {
1075         struct snd_card *card = dev_get_drvdata(dev);
1076         struct azx *chip;
1077         struct hda_intel *hda;
1078 
1079         if (!card)
1080                 return 0;
1081 
1082         chip = card->private_data;
1083         hda = container_of(chip, struct hda_intel, chip);
1084         if (chip->disabled || hda->init_failed)
1085                 return 0;
1086 
1087         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1088             azx_bus(chip)->codec_powered || !chip->running)
1089                 return -EBUSY;
1090 
1091         return 0;
1092 }
1093 
1094 static const struct dev_pm_ops azx_pm = {
1095         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1096 #ifdef CONFIG_PM_SLEEP
1097         .freeze_noirq = azx_freeze_noirq,
1098         .thaw_noirq = azx_thaw_noirq,
1099 #endif
1100         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1101 };
1102 
1103 #define AZX_PM_OPS      &azx_pm
1104 #else
1105 #define AZX_PM_OPS      NULL
1106 #endif /* CONFIG_PM */
1107 
1108 
1109 static int azx_probe_continue(struct azx *chip);
1110 
1111 #ifdef SUPPORT_VGA_SWITCHEROO
1112 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1113 
1114 static void azx_vs_set_state(struct pci_dev *pci,
1115                              enum vga_switcheroo_state state)
1116 {
1117         struct snd_card *card = pci_get_drvdata(pci);
1118         struct azx *chip = card->private_data;
1119         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1120         bool disabled;
1121 
1122         wait_for_completion(&hda->probe_wait);
1123         if (hda->init_failed)
1124                 return;
1125 
1126         disabled = (state == VGA_SWITCHEROO_OFF);
1127         if (chip->disabled == disabled)
1128                 return;
1129 
1130         if (!hda->probe_continued) {
1131                 chip->disabled = disabled;
1132                 if (!disabled) {
1133                         dev_info(chip->card->dev,
1134                                  "Start delayed initialization\n");
1135                         if (azx_probe_continue(chip) < 0) {
1136                                 dev_err(chip->card->dev, "initialization error\n");
1137                                 hda->init_failed = true;
1138                         }
1139                 }
1140         } else {
1141                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1142                          disabled ? "Disabling" : "Enabling");
1143                 if (disabled) {
1144                         pm_runtime_put_sync_suspend(card->dev);
1145                         azx_suspend(card->dev);
1146                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1147                          * however we have no ACPI handle, so pci/acpi can't put us there,
1148                          * put ourselves there */
1149                         pci->current_state = PCI_D3cold;
1150                         chip->disabled = true;
1151                         if (snd_hda_lock_devices(&chip->bus))
1152                                 dev_warn(chip->card->dev,
1153                                          "Cannot lock devices!\n");
1154                 } else {
1155                         snd_hda_unlock_devices(&chip->bus);
1156                         pm_runtime_get_noresume(card->dev);
1157                         chip->disabled = false;
1158                         azx_resume(card->dev);
1159                 }
1160         }
1161 }
1162 
1163 static bool azx_vs_can_switch(struct pci_dev *pci)
1164 {
1165         struct snd_card *card = pci_get_drvdata(pci);
1166         struct azx *chip = card->private_data;
1167         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1168 
1169         wait_for_completion(&hda->probe_wait);
1170         if (hda->init_failed)
1171                 return false;
1172         if (chip->disabled || !hda->probe_continued)
1173                 return true;
1174         if (snd_hda_lock_devices(&chip->bus))
1175                 return false;
1176         snd_hda_unlock_devices(&chip->bus);
1177         return true;
1178 }
1179 
1180 static void init_vga_switcheroo(struct azx *chip)
1181 {
1182         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1183         struct pci_dev *p = get_bound_vga(chip->pci);
1184         if (p) {
1185                 dev_info(chip->card->dev,
1186                          "Handle vga_switcheroo audio client\n");
1187                 hda->use_vga_switcheroo = 1;
1188                 pci_dev_put(p);
1189         }
1190 }
1191 
1192 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1193         .set_gpu_state = azx_vs_set_state,
1194         .can_switch = azx_vs_can_switch,
1195 };
1196 
1197 static int register_vga_switcheroo(struct azx *chip)
1198 {
1199         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1200         int err;
1201 
1202         if (!hda->use_vga_switcheroo)
1203                 return 0;
1204         /* FIXME: currently only handling DIS controller
1205          * is there any machine with two switchable HDMI audio controllers?
1206          */
1207         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1208                                                    VGA_SWITCHEROO_DIS);
1209         if (err < 0)
1210                 return err;
1211         hda->vga_switcheroo_registered = 1;
1212 
1213         /* register as an optimus hdmi audio power domain */
1214         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1215                                                          &hda->hdmi_pm_domain);
1216         return 0;
1217 }
1218 #else
1219 #define init_vga_switcheroo(chip)               /* NOP */
1220 #define register_vga_switcheroo(chip)           0
1221 #define check_hdmi_disabled(pci)        false
1222 #endif /* SUPPORT_VGA_SWITCHER */
1223 
1224 /*
1225  * destructor
1226  */
1227 static int azx_free(struct azx *chip)
1228 {
1229         struct pci_dev *pci = chip->pci;
1230         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1231         struct hdac_bus *bus = azx_bus(chip);
1232 
1233         if (azx_has_pm_runtime(chip) && chip->running)
1234                 pm_runtime_get_noresume(&pci->dev);
1235 
1236         azx_del_card_list(chip);
1237 
1238         hda->init_failed = 1; /* to be sure */
1239         complete_all(&hda->probe_wait);
1240 
1241         if (use_vga_switcheroo(hda)) {
1242                 if (chip->disabled && hda->probe_continued)
1243                         snd_hda_unlock_devices(&chip->bus);
1244                 if (hda->vga_switcheroo_registered)
1245                         vga_switcheroo_unregister_client(chip->pci);
1246         }
1247 
1248         if (bus->chip_init) {
1249                 azx_clear_irq_pending(chip);
1250                 azx_stop_all_streams(chip);
1251                 azx_stop_chip(chip);
1252         }
1253 
1254         if (bus->irq >= 0)
1255                 free_irq(bus->irq, (void*)chip);
1256         if (chip->msi)
1257                 pci_disable_msi(chip->pci);
1258         iounmap(bus->remap_addr);
1259 
1260         azx_free_stream_pages(chip);
1261         azx_free_streams(chip);
1262         snd_hdac_bus_exit(bus);
1263 
1264         if (chip->region_requested)
1265                 pci_release_regions(chip->pci);
1266 
1267         pci_disable_device(chip->pci);
1268 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1269         release_firmware(chip->fw);
1270 #endif
1271 
1272         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1273                 if (hda->need_i915_power)
1274                         snd_hdac_display_power(bus, false);
1275                 snd_hdac_i915_exit(bus);
1276         }
1277         kfree(hda);
1278 
1279         return 0;
1280 }
1281 
1282 static int azx_dev_disconnect(struct snd_device *device)
1283 {
1284         struct azx *chip = device->device_data;
1285 
1286         chip->bus.shutdown = 1;
1287         return 0;
1288 }
1289 
1290 static int azx_dev_free(struct snd_device *device)
1291 {
1292         return azx_free(device->device_data);
1293 }
1294 
1295 #ifdef SUPPORT_VGA_SWITCHEROO
1296 /*
1297  * Check of disabled HDMI controller by vga_switcheroo
1298  */
1299 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1300 {
1301         struct pci_dev *p;
1302 
1303         /* check only discrete GPU */
1304         switch (pci->vendor) {
1305         case PCI_VENDOR_ID_ATI:
1306         case PCI_VENDOR_ID_AMD:
1307         case PCI_VENDOR_ID_NVIDIA:
1308                 if (pci->devfn == 1) {
1309                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1310                                                         pci->bus->number, 0);
1311                         if (p) {
1312                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1313                                         return p;
1314                                 pci_dev_put(p);
1315                         }
1316                 }
1317                 break;
1318         }
1319         return NULL;
1320 }
1321 
1322 static bool check_hdmi_disabled(struct pci_dev *pci)
1323 {
1324         bool vga_inactive = false;
1325         struct pci_dev *p = get_bound_vga(pci);
1326 
1327         if (p) {
1328                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1329                         vga_inactive = true;
1330                 pci_dev_put(p);
1331         }
1332         return vga_inactive;
1333 }
1334 #endif /* SUPPORT_VGA_SWITCHEROO */
1335 
1336 /*
1337  * white/black-listing for position_fix
1338  */
1339 static struct snd_pci_quirk position_fix_list[] = {
1340         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1341         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1342         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1343         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1344         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1345         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1346         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1347         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1348         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1349         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1350         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1351         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1352         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1353         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1354         {}
1355 };
1356 
1357 static int check_position_fix(struct azx *chip, int fix)
1358 {
1359         const struct snd_pci_quirk *q;
1360 
1361         switch (fix) {
1362         case POS_FIX_AUTO:
1363         case POS_FIX_LPIB:
1364         case POS_FIX_POSBUF:
1365         case POS_FIX_VIACOMBO:
1366         case POS_FIX_COMBO:
1367                 return fix;
1368         }
1369 
1370         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1371         if (q) {
1372                 dev_info(chip->card->dev,
1373                          "position_fix set to %d for device %04x:%04x\n",
1374                          q->value, q->subvendor, q->subdevice);
1375                 return q->value;
1376         }
1377 
1378         /* Check VIA/ATI HD Audio Controller exist */
1379         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1380                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1381                 return POS_FIX_VIACOMBO;
1382         }
1383         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1384                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1385                 return POS_FIX_LPIB;
1386         }
1387         return POS_FIX_AUTO;
1388 }
1389 
1390 static void assign_position_fix(struct azx *chip, int fix)
1391 {
1392         static azx_get_pos_callback_t callbacks[] = {
1393                 [POS_FIX_AUTO] = NULL,
1394                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1395                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1396                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1397                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1398         };
1399 
1400         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1401 
1402         /* combo mode uses LPIB only for playback */
1403         if (fix == POS_FIX_COMBO)
1404                 chip->get_position[1] = NULL;
1405 
1406         if (fix == POS_FIX_POSBUF &&
1407             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1408                 chip->get_delay[0] = chip->get_delay[1] =
1409                         azx_get_delay_from_lpib;
1410         }
1411 
1412 }
1413 
1414 /*
1415  * black-lists for probe_mask
1416  */
1417 static struct snd_pci_quirk probe_mask_list[] = {
1418         /* Thinkpad often breaks the controller communication when accessing
1419          * to the non-working (or non-existing) modem codec slot.
1420          */
1421         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1422         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1423         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1424         /* broken BIOS */
1425         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1426         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1427         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1428         /* forced codec slots */
1429         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1430         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1431         /* WinFast VP200 H (Teradici) user reported broken communication */
1432         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1433         {}
1434 };
1435 
1436 #define AZX_FORCE_CODEC_MASK    0x100
1437 
1438 static void check_probe_mask(struct azx *chip, int dev)
1439 {
1440         const struct snd_pci_quirk *q;
1441 
1442         chip->codec_probe_mask = probe_mask[dev];
1443         if (chip->codec_probe_mask == -1) {
1444                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1445                 if (q) {
1446                         dev_info(chip->card->dev,
1447                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1448                                  q->value, q->subvendor, q->subdevice);
1449                         chip->codec_probe_mask = q->value;
1450                 }
1451         }
1452 
1453         /* check forced option */
1454         if (chip->codec_probe_mask != -1 &&
1455             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1456                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1457                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1458                          (int)azx_bus(chip)->codec_mask);
1459         }
1460 }
1461 
1462 /*
1463  * white/black-list for enable_msi
1464  */
1465 static struct snd_pci_quirk msi_black_list[] = {
1466         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1467         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1468         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1469         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1470         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1471         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1472         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1473         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1474         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1475         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1476         {}
1477 };
1478 
1479 static void check_msi(struct azx *chip)
1480 {
1481         const struct snd_pci_quirk *q;
1482 
1483         if (enable_msi >= 0) {
1484                 chip->msi = !!enable_msi;
1485                 return;
1486         }
1487         chip->msi = 1;  /* enable MSI as default */
1488         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1489         if (q) {
1490                 dev_info(chip->card->dev,
1491                          "msi for device %04x:%04x set to %d\n",
1492                          q->subvendor, q->subdevice, q->value);
1493                 chip->msi = q->value;
1494                 return;
1495         }
1496 
1497         /* NVidia chipsets seem to cause troubles with MSI */
1498         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1499                 dev_info(chip->card->dev, "Disabling MSI\n");
1500                 chip->msi = 0;
1501         }
1502 }
1503 
1504 /* check the snoop mode availability */
1505 static void azx_check_snoop_available(struct azx *chip)
1506 {
1507         int snoop = hda_snoop;
1508 
1509         if (snoop >= 0) {
1510                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1511                          snoop ? "snoop" : "non-snoop");
1512                 chip->snoop = snoop;
1513                 return;
1514         }
1515 
1516         snoop = true;
1517         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1518             chip->driver_type == AZX_DRIVER_VIA) {
1519                 /* force to non-snoop mode for a new VIA controller
1520                  * when BIOS is set
1521                  */
1522                 u8 val;
1523                 pci_read_config_byte(chip->pci, 0x42, &val);
1524                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1525                         snoop = false;
1526         }
1527 
1528         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1529                 snoop = false;
1530 
1531         chip->snoop = snoop;
1532         if (!snoop)
1533                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1534 }
1535 
1536 static void azx_probe_work(struct work_struct *work)
1537 {
1538         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1539         azx_probe_continue(&hda->chip);
1540 }
1541 
1542 /*
1543  * constructor
1544  */
1545 static const struct hdac_io_ops pci_hda_io_ops;
1546 static const struct hda_controller_ops pci_hda_ops;
1547 
1548 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1549                       int dev, unsigned int driver_caps,
1550                       struct azx **rchip)
1551 {
1552         static struct snd_device_ops ops = {
1553                 .dev_disconnect = azx_dev_disconnect,
1554                 .dev_free = azx_dev_free,
1555         };
1556         struct hda_intel *hda;
1557         struct azx *chip;
1558         int err;
1559 
1560         *rchip = NULL;
1561 
1562         err = pci_enable_device(pci);
1563         if (err < 0)
1564                 return err;
1565 
1566         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1567         if (!hda) {
1568                 pci_disable_device(pci);
1569                 return -ENOMEM;
1570         }
1571 
1572         chip = &hda->chip;
1573         mutex_init(&chip->open_mutex);
1574         chip->card = card;
1575         chip->pci = pci;
1576         chip->ops = &pci_hda_ops;
1577         chip->driver_caps = driver_caps;
1578         chip->driver_type = driver_caps & 0xff;
1579         check_msi(chip);
1580         chip->dev_index = dev;
1581         chip->jackpoll_ms = jackpoll_ms;
1582         INIT_LIST_HEAD(&chip->pcm_list);
1583         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1584         INIT_LIST_HEAD(&hda->list);
1585         init_vga_switcheroo(chip);
1586         init_completion(&hda->probe_wait);
1587 
1588         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1589 
1590         check_probe_mask(chip, dev);
1591 
1592         chip->single_cmd = single_cmd;
1593         azx_check_snoop_available(chip);
1594 
1595         if (bdl_pos_adj[dev] < 0) {
1596                 switch (chip->driver_type) {
1597                 case AZX_DRIVER_ICH:
1598                 case AZX_DRIVER_PCH:
1599                         bdl_pos_adj[dev] = 1;
1600                         break;
1601                 default:
1602                         bdl_pos_adj[dev] = 32;
1603                         break;
1604                 }
1605         }
1606         chip->bdl_pos_adj = bdl_pos_adj;
1607 
1608         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1609         if (err < 0) {
1610                 kfree(hda);
1611                 pci_disable_device(pci);
1612                 return err;
1613         }
1614 
1615         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1616         if (err < 0) {
1617                 dev_err(card->dev, "Error creating device [card]!\n");
1618                 azx_free(chip);
1619                 return err;
1620         }
1621 
1622         /* continue probing in work context as may trigger request module */
1623         INIT_WORK(&hda->probe_work, azx_probe_work);
1624 
1625         *rchip = chip;
1626 
1627         return 0;
1628 }
1629 
1630 static int azx_first_init(struct azx *chip)
1631 {
1632         int dev = chip->dev_index;
1633         struct pci_dev *pci = chip->pci;
1634         struct snd_card *card = chip->card;
1635         struct hdac_bus *bus = azx_bus(chip);
1636         int err;
1637         unsigned short gcap;
1638         unsigned int dma_bits = 64;
1639 
1640 #if BITS_PER_LONG != 64
1641         /* Fix up base address on ULI M5461 */
1642         if (chip->driver_type == AZX_DRIVER_ULI) {
1643                 u16 tmp3;
1644                 pci_read_config_word(pci, 0x40, &tmp3);
1645                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1646                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1647         }
1648 #endif
1649 
1650         err = pci_request_regions(pci, "ICH HD audio");
1651         if (err < 0)
1652                 return err;
1653         chip->region_requested = 1;
1654 
1655         bus->addr = pci_resource_start(pci, 0);
1656         bus->remap_addr = pci_ioremap_bar(pci, 0);
1657         if (bus->remap_addr == NULL) {
1658                 dev_err(card->dev, "ioremap error\n");
1659                 return -ENXIO;
1660         }
1661 
1662         if (chip->msi) {
1663                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1664                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1665                         pci->no_64bit_msi = true;
1666                 }
1667                 if (pci_enable_msi(pci) < 0)
1668                         chip->msi = 0;
1669         }
1670 
1671         if (azx_acquire_irq(chip, 0) < 0)
1672                 return -EBUSY;
1673 
1674         pci_set_master(pci);
1675         synchronize_irq(bus->irq);
1676 
1677         gcap = azx_readw(chip, GCAP);
1678         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1679 
1680         /* AMD devices support 40 or 48bit DMA, take the safe one */
1681         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1682                 dma_bits = 40;
1683 
1684         /* disable SB600 64bit support for safety */
1685         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1686                 struct pci_dev *p_smbus;
1687                 dma_bits = 40;
1688                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1689                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1690                                          NULL);
1691                 if (p_smbus) {
1692                         if (p_smbus->revision < 0x30)
1693                                 gcap &= ~AZX_GCAP_64OK;
1694                         pci_dev_put(p_smbus);
1695                 }
1696         }
1697 
1698         /* disable 64bit DMA address on some devices */
1699         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1700                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1701                 gcap &= ~AZX_GCAP_64OK;
1702         }
1703 
1704         /* disable buffer size rounding to 128-byte multiples if supported */
1705         if (align_buffer_size >= 0)
1706                 chip->align_buffer_size = !!align_buffer_size;
1707         else {
1708                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1709                         chip->align_buffer_size = 0;
1710                 else
1711                         chip->align_buffer_size = 1;
1712         }
1713 
1714         /* allow 64bit DMA address if supported by H/W */
1715         if (!(gcap & AZX_GCAP_64OK))
1716                 dma_bits = 32;
1717         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1718                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1719         } else {
1720                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1721                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1722         }
1723 
1724         /* read number of streams from GCAP register instead of using
1725          * hardcoded value
1726          */
1727         chip->capture_streams = (gcap >> 8) & 0x0f;
1728         chip->playback_streams = (gcap >> 12) & 0x0f;
1729         if (!chip->playback_streams && !chip->capture_streams) {
1730                 /* gcap didn't give any info, switching to old method */
1731 
1732                 switch (chip->driver_type) {
1733                 case AZX_DRIVER_ULI:
1734                         chip->playback_streams = ULI_NUM_PLAYBACK;
1735                         chip->capture_streams = ULI_NUM_CAPTURE;
1736                         break;
1737                 case AZX_DRIVER_ATIHDMI:
1738                 case AZX_DRIVER_ATIHDMI_NS:
1739                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1740                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1741                         break;
1742                 case AZX_DRIVER_GENERIC:
1743                 default:
1744                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1745                         chip->capture_streams = ICH6_NUM_CAPTURE;
1746                         break;
1747                 }
1748         }
1749         chip->capture_index_offset = 0;
1750         chip->playback_index_offset = chip->capture_streams;
1751         chip->num_streams = chip->playback_streams + chip->capture_streams;
1752 
1753         /* initialize streams */
1754         err = azx_init_streams(chip);
1755         if (err < 0)
1756                 return err;
1757 
1758         err = azx_alloc_stream_pages(chip);
1759         if (err < 0)
1760                 return err;
1761 
1762         /* initialize chip */
1763         azx_init_pci(chip);
1764 
1765         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1766                 struct hda_intel *hda;
1767 
1768                 hda = container_of(chip, struct hda_intel, chip);
1769                 haswell_set_bclk(hda);
1770         }
1771 
1772         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1773 
1774         /* codec detection */
1775         if (!azx_bus(chip)->codec_mask) {
1776                 dev_err(card->dev, "no codecs found!\n");
1777                 return -ENODEV;
1778         }
1779 
1780         strcpy(card->driver, "HDA-Intel");
1781         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1782                 sizeof(card->shortname));
1783         snprintf(card->longname, sizeof(card->longname),
1784                  "%s at 0x%lx irq %i",
1785                  card->shortname, bus->addr, bus->irq);
1786 
1787         return 0;
1788 }
1789 
1790 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1791 /* callback from request_firmware_nowait() */
1792 static void azx_firmware_cb(const struct firmware *fw, void *context)
1793 {
1794         struct snd_card *card = context;
1795         struct azx *chip = card->private_data;
1796         struct pci_dev *pci = chip->pci;
1797 
1798         if (!fw) {
1799                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1800                 goto error;
1801         }
1802 
1803         chip->fw = fw;
1804         if (!chip->disabled) {
1805                 /* continue probing */
1806                 if (azx_probe_continue(chip))
1807                         goto error;
1808         }
1809         return; /* OK */
1810 
1811  error:
1812         snd_card_free(card);
1813         pci_set_drvdata(pci, NULL);
1814 }
1815 #endif
1816 
1817 /*
1818  * HDA controller ops.
1819  */
1820 
1821 /* PCI register access. */
1822 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1823 {
1824         writel(value, addr);
1825 }
1826 
1827 static u32 pci_azx_readl(u32 __iomem *addr)
1828 {
1829         return readl(addr);
1830 }
1831 
1832 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1833 {
1834         writew(value, addr);
1835 }
1836 
1837 static u16 pci_azx_readw(u16 __iomem *addr)
1838 {
1839         return readw(addr);
1840 }
1841 
1842 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1843 {
1844         writeb(value, addr);
1845 }
1846 
1847 static u8 pci_azx_readb(u8 __iomem *addr)
1848 {
1849         return readb(addr);
1850 }
1851 
1852 static int disable_msi_reset_irq(struct azx *chip)
1853 {
1854         struct hdac_bus *bus = azx_bus(chip);
1855         int err;
1856 
1857         free_irq(bus->irq, chip);
1858         bus->irq = -1;
1859         pci_disable_msi(chip->pci);
1860         chip->msi = 0;
1861         err = azx_acquire_irq(chip, 1);
1862         if (err < 0)
1863                 return err;
1864 
1865         return 0;
1866 }
1867 
1868 /* DMA page allocation helpers.  */
1869 static int dma_alloc_pages(struct hdac_bus *bus,
1870                            int type,
1871                            size_t size,
1872                            struct snd_dma_buffer *buf)
1873 {
1874         struct azx *chip = bus_to_azx(bus);
1875         int err;
1876 
1877         err = snd_dma_alloc_pages(type,
1878                                   bus->dev,
1879                                   size, buf);
1880         if (err < 0)
1881                 return err;
1882         mark_pages_wc(chip, buf, true);
1883         return 0;
1884 }
1885 
1886 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1887 {
1888         struct azx *chip = bus_to_azx(bus);
1889 
1890         mark_pages_wc(chip, buf, false);
1891         snd_dma_free_pages(buf);
1892 }
1893 
1894 static int substream_alloc_pages(struct azx *chip,
1895                                  struct snd_pcm_substream *substream,
1896                                  size_t size)
1897 {
1898         struct azx_dev *azx_dev = get_azx_dev(substream);
1899         int ret;
1900 
1901         mark_runtime_wc(chip, azx_dev, substream, false);
1902         ret = snd_pcm_lib_malloc_pages(substream, size);
1903         if (ret < 0)
1904                 return ret;
1905         mark_runtime_wc(chip, azx_dev, substream, true);
1906         return 0;
1907 }
1908 
1909 static int substream_free_pages(struct azx *chip,
1910                                 struct snd_pcm_substream *substream)
1911 {
1912         struct azx_dev *azx_dev = get_azx_dev(substream);
1913         mark_runtime_wc(chip, azx_dev, substream, false);
1914         return snd_pcm_lib_free_pages(substream);
1915 }
1916 
1917 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1918                              struct vm_area_struct *area)
1919 {
1920 #ifdef CONFIG_X86
1921         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1922         struct azx *chip = apcm->chip;
1923         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1924                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1925 #endif
1926 }
1927 
1928 static const struct hdac_io_ops pci_hda_io_ops = {
1929         .reg_writel = pci_azx_writel,
1930         .reg_readl = pci_azx_readl,
1931         .reg_writew = pci_azx_writew,
1932         .reg_readw = pci_azx_readw,
1933         .reg_writeb = pci_azx_writeb,
1934         .reg_readb = pci_azx_readb,
1935         .dma_alloc_pages = dma_alloc_pages,
1936         .dma_free_pages = dma_free_pages,
1937 };
1938 
1939 static const struct hda_controller_ops pci_hda_ops = {
1940         .disable_msi_reset_irq = disable_msi_reset_irq,
1941         .substream_alloc_pages = substream_alloc_pages,
1942         .substream_free_pages = substream_free_pages,
1943         .pcm_mmap_prepare = pcm_mmap_prepare,
1944         .position_check = azx_position_check,
1945         .link_power = azx_intel_link_power,
1946 };
1947 
1948 static int azx_probe(struct pci_dev *pci,
1949                      const struct pci_device_id *pci_id)
1950 {
1951         static int dev;
1952         struct snd_card *card;
1953         struct hda_intel *hda;
1954         struct azx *chip;
1955         bool schedule_probe;
1956         int err;
1957 
1958         if (dev >= SNDRV_CARDS)
1959                 return -ENODEV;
1960         if (!enable[dev]) {
1961                 dev++;
1962                 return -ENOENT;
1963         }
1964 
1965         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1966                            0, &card);
1967         if (err < 0) {
1968                 dev_err(&pci->dev, "Error creating card!\n");
1969                 return err;
1970         }
1971 
1972         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1973         if (err < 0)
1974                 goto out_free;
1975         card->private_data = chip;
1976         hda = container_of(chip, struct hda_intel, chip);
1977 
1978         pci_set_drvdata(pci, card);
1979 
1980         err = register_vga_switcheroo(chip);
1981         if (err < 0) {
1982                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
1983                 goto out_free;
1984         }
1985 
1986         if (check_hdmi_disabled(pci)) {
1987                 dev_info(card->dev, "VGA controller is disabled\n");
1988                 dev_info(card->dev, "Delaying initialization\n");
1989                 chip->disabled = true;
1990         }
1991 
1992         schedule_probe = !chip->disabled;
1993 
1994 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1995         if (patch[dev] && *patch[dev]) {
1996                 dev_info(card->dev, "Applying patch firmware '%s'\n",
1997                          patch[dev]);
1998                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1999                                               &pci->dev, GFP_KERNEL, card,
2000                                               azx_firmware_cb);
2001                 if (err < 0)
2002                         goto out_free;
2003                 schedule_probe = false; /* continued in azx_firmware_cb() */
2004         }
2005 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2006 
2007 #ifndef CONFIG_SND_HDA_I915
2008         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2009                 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
2010 #endif
2011 
2012         if (schedule_probe)
2013                 schedule_work(&hda->probe_work);
2014 
2015         dev++;
2016         if (chip->disabled)
2017                 complete_all(&hda->probe_wait);
2018         return 0;
2019 
2020 out_free:
2021         snd_card_free(card);
2022         return err;
2023 }
2024 
2025 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2026 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2027         [AZX_DRIVER_NVIDIA] = 8,
2028         [AZX_DRIVER_TERA] = 1,
2029 };
2030 
2031 static int azx_probe_continue(struct azx *chip)
2032 {
2033         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2034         struct hdac_bus *bus = azx_bus(chip);
2035         struct pci_dev *pci = chip->pci;
2036         int dev = chip->dev_index;
2037         int err;
2038 
2039         hda->probe_continued = 1;
2040 
2041         /* Request display power well for the HDA controller or codec. For
2042          * Haswell/Broadwell, both the display HDA controller and codec need
2043          * this power. For other platforms, like Baytrail/Braswell, only the
2044          * display codec needs the power and it can be released after probe.
2045          */
2046         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2047                 /* HSW/BDW controllers need this power */
2048                 if (CONTROLLER_IN_GPU(pci))
2049                         hda->need_i915_power = 1;
2050 
2051                 err = snd_hdac_i915_init(bus);
2052                 if (err < 0) {
2053                         /* if the controller is bound only with HDMI/DP
2054                          * (for HSW and BDW), we need to abort the probe;
2055                          * for other chips, still continue probing as other
2056                          * codecs can be on the same link.
2057                          */
2058                         if (CONTROLLER_IN_GPU(pci))
2059                                 goto out_free;
2060                         else
2061                                 goto skip_i915;
2062                 }
2063 
2064                 err = snd_hdac_display_power(bus, true);
2065                 if (err < 0) {
2066                         dev_err(chip->card->dev,
2067                                 "Cannot turn on display power on i915\n");
2068                         goto i915_power_fail;
2069                 }
2070         }
2071 
2072  skip_i915:
2073         err = azx_first_init(chip);
2074         if (err < 0)
2075                 goto out_free;
2076 
2077 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2078         chip->beep_mode = beep_mode[dev];
2079 #endif
2080 
2081         /* create codec instances */
2082         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2083         if (err < 0)
2084                 goto out_free;
2085 
2086 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2087         if (chip->fw) {
2088                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2089                                          chip->fw->data);
2090                 if (err < 0)
2091                         goto out_free;
2092 #ifndef CONFIG_PM
2093                 release_firmware(chip->fw); /* no longer needed */
2094                 chip->fw = NULL;
2095 #endif
2096         }
2097 #endif
2098         if ((probe_only[dev] & 1) == 0) {
2099                 err = azx_codec_configure(chip);
2100                 if (err < 0)
2101                         goto out_free;
2102         }
2103 
2104         err = snd_card_register(chip->card);
2105         if (err < 0)
2106                 goto out_free;
2107 
2108         chip->running = 1;
2109         azx_add_card_list(chip);
2110         snd_hda_set_power_save(&chip->bus, power_save * 1000);
2111         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2112                 pm_runtime_put_noidle(&pci->dev);
2113 
2114 out_free:
2115         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2116                 && !hda->need_i915_power)
2117                 snd_hdac_display_power(bus, false);
2118 
2119 i915_power_fail:
2120         if (err < 0)
2121                 hda->init_failed = 1;
2122         complete_all(&hda->probe_wait);
2123         return err;
2124 }
2125 
2126 static void azx_remove(struct pci_dev *pci)
2127 {
2128         struct snd_card *card = pci_get_drvdata(pci);
2129 
2130         if (card)
2131                 snd_card_free(card);
2132 }
2133 
2134 static void azx_shutdown(struct pci_dev *pci)
2135 {
2136         struct snd_card *card = pci_get_drvdata(pci);
2137         struct azx *chip;
2138 
2139         if (!card)
2140                 return;
2141         chip = card->private_data;
2142         if (chip && chip->running)
2143                 azx_stop_chip(chip);
2144 }
2145 
2146 /* PCI IDs */
2147 static const struct pci_device_id azx_ids[] = {
2148         /* CPT */
2149         { PCI_DEVICE(0x8086, 0x1c20),
2150           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2151         /* PBG */
2152         { PCI_DEVICE(0x8086, 0x1d20),
2153           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2154         /* Panther Point */
2155         { PCI_DEVICE(0x8086, 0x1e20),
2156           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2157         /* Lynx Point */
2158         { PCI_DEVICE(0x8086, 0x8c20),
2159           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2160         /* 9 Series */
2161         { PCI_DEVICE(0x8086, 0x8ca0),
2162           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2163         /* Wellsburg */
2164         { PCI_DEVICE(0x8086, 0x8d20),
2165           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2166         { PCI_DEVICE(0x8086, 0x8d21),
2167           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2168         /* Lewisburg */
2169         { PCI_DEVICE(0x8086, 0xa1f0),
2170           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2171         { PCI_DEVICE(0x8086, 0xa270),
2172           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2173         /* Lynx Point-LP */
2174         { PCI_DEVICE(0x8086, 0x9c20),
2175           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2176         /* Lynx Point-LP */
2177         { PCI_DEVICE(0x8086, 0x9c21),
2178           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2179         /* Wildcat Point-LP */
2180         { PCI_DEVICE(0x8086, 0x9ca0),
2181           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2182         /* Sunrise Point */
2183         { PCI_DEVICE(0x8086, 0xa170),
2184           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2185         /* Sunrise Point-LP */
2186         { PCI_DEVICE(0x8086, 0x9d70),
2187           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2188         /* Broxton-P(Apollolake) */
2189         { PCI_DEVICE(0x8086, 0x5a98),
2190           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2191         /* Haswell */
2192         { PCI_DEVICE(0x8086, 0x0a0c),
2193           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2194         { PCI_DEVICE(0x8086, 0x0c0c),
2195           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2196         { PCI_DEVICE(0x8086, 0x0d0c),
2197           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2198         /* Broadwell */
2199         { PCI_DEVICE(0x8086, 0x160c),
2200           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2201         /* 5 Series/3400 */
2202         { PCI_DEVICE(0x8086, 0x3b56),
2203           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2204         /* Poulsbo */
2205         { PCI_DEVICE(0x8086, 0x811b),
2206           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2207         /* Oaktrail */
2208         { PCI_DEVICE(0x8086, 0x080a),
2209           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2210         /* BayTrail */
2211         { PCI_DEVICE(0x8086, 0x0f04),
2212           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2213         /* Braswell */
2214         { PCI_DEVICE(0x8086, 0x2284),
2215           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2216         /* ICH6 */
2217         { PCI_DEVICE(0x8086, 0x2668),
2218           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2219         /* ICH7 */
2220         { PCI_DEVICE(0x8086, 0x27d8),
2221           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2222         /* ESB2 */
2223         { PCI_DEVICE(0x8086, 0x269a),
2224           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2225         /* ICH8 */
2226         { PCI_DEVICE(0x8086, 0x284b),
2227           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2228         /* ICH9 */
2229         { PCI_DEVICE(0x8086, 0x293e),
2230           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2231         /* ICH9 */
2232         { PCI_DEVICE(0x8086, 0x293f),
2233           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2234         /* ICH10 */
2235         { PCI_DEVICE(0x8086, 0x3a3e),
2236           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2237         /* ICH10 */
2238         { PCI_DEVICE(0x8086, 0x3a6e),
2239           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2240         /* Generic Intel */
2241         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2242           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2243           .class_mask = 0xffffff,
2244           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2245         /* ATI SB 450/600/700/800/900 */
2246         { PCI_DEVICE(0x1002, 0x437b),
2247           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2248         { PCI_DEVICE(0x1002, 0x4383),
2249           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2250         /* AMD Hudson */
2251         { PCI_DEVICE(0x1022, 0x780d),
2252           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2253         /* ATI HDMI */
2254         { PCI_DEVICE(0x1002, 0x1308),
2255           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2256         { PCI_DEVICE(0x1002, 0x157a),
2257           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2258         { PCI_DEVICE(0x1002, 0x793b),
2259           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2260         { PCI_DEVICE(0x1002, 0x7919),
2261           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2262         { PCI_DEVICE(0x1002, 0x960f),
2263           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2264         { PCI_DEVICE(0x1002, 0x970f),
2265           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2266         { PCI_DEVICE(0x1002, 0x9840),
2267           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2268         { PCI_DEVICE(0x1002, 0xaa00),
2269           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2270         { PCI_DEVICE(0x1002, 0xaa08),
2271           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2272         { PCI_DEVICE(0x1002, 0xaa10),
2273           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2274         { PCI_DEVICE(0x1002, 0xaa18),
2275           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2276         { PCI_DEVICE(0x1002, 0xaa20),
2277           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2278         { PCI_DEVICE(0x1002, 0xaa28),
2279           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2280         { PCI_DEVICE(0x1002, 0xaa30),
2281           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2282         { PCI_DEVICE(0x1002, 0xaa38),
2283           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2284         { PCI_DEVICE(0x1002, 0xaa40),
2285           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2286         { PCI_DEVICE(0x1002, 0xaa48),
2287           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2288         { PCI_DEVICE(0x1002, 0xaa50),
2289           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2290         { PCI_DEVICE(0x1002, 0xaa58),
2291           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2292         { PCI_DEVICE(0x1002, 0xaa60),
2293           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2294         { PCI_DEVICE(0x1002, 0xaa68),
2295           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2296         { PCI_DEVICE(0x1002, 0xaa80),
2297           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2298         { PCI_DEVICE(0x1002, 0xaa88),
2299           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2300         { PCI_DEVICE(0x1002, 0xaa90),
2301           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2302         { PCI_DEVICE(0x1002, 0xaa98),
2303           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2304         { PCI_DEVICE(0x1002, 0x9902),
2305           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2306         { PCI_DEVICE(0x1002, 0xaaa0),
2307           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2308         { PCI_DEVICE(0x1002, 0xaaa8),
2309           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2310         { PCI_DEVICE(0x1002, 0xaab0),
2311           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2312         { PCI_DEVICE(0x1002, 0xaac0),
2313           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2314         { PCI_DEVICE(0x1002, 0xaac8),
2315           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2316         { PCI_DEVICE(0x1002, 0xaad8),
2317           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2318         { PCI_DEVICE(0x1002, 0xaae8),
2319           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2320         /* VIA VT8251/VT8237A */
2321         { PCI_DEVICE(0x1106, 0x3288),
2322           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2323         /* VIA GFX VT7122/VX900 */
2324         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2325         /* VIA GFX VT6122/VX11 */
2326         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2327         /* SIS966 */
2328         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2329         /* ULI M5461 */
2330         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2331         /* NVIDIA MCP */
2332         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2333           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2334           .class_mask = 0xffffff,
2335           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2336         /* Teradici */
2337         { PCI_DEVICE(0x6549, 0x1200),
2338           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2339         { PCI_DEVICE(0x6549, 0x2200),
2340           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2341         /* Creative X-Fi (CA0110-IBG) */
2342         /* CTHDA chips */
2343         { PCI_DEVICE(0x1102, 0x0010),
2344           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2345         { PCI_DEVICE(0x1102, 0x0012),
2346           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2347 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2348         /* the following entry conflicts with snd-ctxfi driver,
2349          * as ctxfi driver mutates from HD-audio to native mode with
2350          * a special command sequence.
2351          */
2352         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2353           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2354           .class_mask = 0xffffff,
2355           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2356           AZX_DCAPS_NO_64BIT |
2357           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2358 #else
2359         /* this entry seems still valid -- i.e. without emu20kx chip */
2360         { PCI_DEVICE(0x1102, 0x0009),
2361           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2362           AZX_DCAPS_NO_64BIT |
2363           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2364 #endif
2365         /* CM8888 */
2366         { PCI_DEVICE(0x13f6, 0x5011),
2367           .driver_data = AZX_DRIVER_CMEDIA |
2368           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2369         /* Vortex86MX */
2370         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2371         /* VMware HDAudio */
2372         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2373         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2374         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2375           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2376           .class_mask = 0xffffff,
2377           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2378         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2379           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2380           .class_mask = 0xffffff,
2381           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2382         { 0, }
2383 };
2384 MODULE_DEVICE_TABLE(pci, azx_ids);
2385 
2386 /* pci_driver definition */
2387 static struct pci_driver azx_driver = {
2388         .name = KBUILD_MODNAME,
2389         .id_table = azx_ids,
2390         .probe = azx_probe,
2391         .remove = azx_remove,
2392         .shutdown = azx_shutdown,
2393         .driver = {
2394                 .pm = AZX_PM_OPS,
2395         },
2396 };
2397 
2398 module_pci_driver(azx_driver);
2399 

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