Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/sound/pci/cs4281.c

  1 /*
  2  *  Driver for Cirrus Logic CS4281 based PCI soundcard
  3  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
  4  *
  5  *
  6  *   This program is free software; you can redistribute it and/or modify
  7  *   it under the terms of the GNU General Public License as published by
  8  *   the Free Software Foundation; either version 2 of the License, or
  9  *   (at your option) any later version.
 10  *
 11  *   This program is distributed in the hope that it will be useful,
 12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  *   GNU General Public License for more details.
 15  *
 16  *   You should have received a copy of the GNU General Public License
 17  *   along with this program; if not, write to the Free Software
 18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 19  *
 20  */
 21 
 22 #include <linux/io.h>
 23 #include <linux/delay.h>
 24 #include <linux/interrupt.h>
 25 #include <linux/init.h>
 26 #include <linux/pci.h>
 27 #include <linux/slab.h>
 28 #include <linux/gameport.h>
 29 #include <linux/module.h>
 30 #include <sound/core.h>
 31 #include <sound/control.h>
 32 #include <sound/pcm.h>
 33 #include <sound/rawmidi.h>
 34 #include <sound/ac97_codec.h>
 35 #include <sound/tlv.h>
 36 #include <sound/opl3.h>
 37 #include <sound/initval.h>
 38 
 39 
 40 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
 41 MODULE_DESCRIPTION("Cirrus Logic CS4281");
 42 MODULE_LICENSE("GPL");
 43 MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
 44 
 45 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 46 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 47 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
 48 static bool dual_codec[SNDRV_CARDS];    /* dual codec */
 49 
 50 module_param_array(index, int, NULL, 0444);
 51 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
 52 module_param_array(id, charp, NULL, 0444);
 53 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
 54 module_param_array(enable, bool, NULL, 0444);
 55 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
 56 module_param_array(dual_codec, bool, NULL, 0444);
 57 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
 58 
 59 /*
 60  *  Direct registers
 61  */
 62 
 63 #define CS4281_BA0_SIZE         0x1000
 64 #define CS4281_BA1_SIZE         0x10000
 65 
 66 /*
 67  *  BA0 registers
 68  */
 69 #define BA0_HISR                0x0000  /* Host Interrupt Status Register */
 70 #define BA0_HISR_INTENA         (1<<31) /* Internal Interrupt Enable Bit */
 71 #define BA0_HISR_MIDI           (1<<22) /* MIDI port interrupt */
 72 #define BA0_HISR_FIFOI          (1<<20) /* FIFO polled interrupt */
 73 #define BA0_HISR_DMAI           (1<<18) /* DMA interrupt (half or end) */
 74 #define BA0_HISR_FIFO(c)        (1<<(12+(c))) /* FIFO channel interrupt */
 75 #define BA0_HISR_DMA(c)         (1<<(8+(c)))  /* DMA channel interrupt */
 76 #define BA0_HISR_GPPI           (1<<5)  /* General Purpose Input (Primary chip) */
 77 #define BA0_HISR_GPSI           (1<<4)  /* General Purpose Input (Secondary chip) */
 78 #define BA0_HISR_GP3I           (1<<3)  /* GPIO3 pin Interrupt */
 79 #define BA0_HISR_GP1I           (1<<2)  /* GPIO1 pin Interrupt */
 80 #define BA0_HISR_VUPI           (1<<1)  /* VOLUP pin Interrupt */
 81 #define BA0_HISR_VDNI           (1<<0)  /* VOLDN pin Interrupt */
 82 
 83 #define BA0_HICR                0x0008  /* Host Interrupt Control Register */
 84 #define BA0_HICR_CHGM           (1<<1)  /* INTENA Change Mask */
 85 #define BA0_HICR_IEV            (1<<0)  /* INTENA Value */
 86 #define BA0_HICR_EOI            (3<<0)  /* End of Interrupt command */
 87 
 88 #define BA0_HIMR                0x000c  /* Host Interrupt Mask Register */
 89                                         /* Use same contants as for BA0_HISR */
 90 
 91 #define BA0_IIER                0x0010  /* ISA Interrupt Enable Register */
 92 
 93 #define BA0_HDSR0               0x00f0  /* Host DMA Engine 0 Status Register */
 94 #define BA0_HDSR1               0x00f4  /* Host DMA Engine 1 Status Register */
 95 #define BA0_HDSR2               0x00f8  /* Host DMA Engine 2 Status Register */
 96 #define BA0_HDSR3               0x00fc  /* Host DMA Engine 3 Status Register */
 97 
 98 #define BA0_HDSR_CH1P           (1<<25) /* Channel 1 Pending */
 99 #define BA0_HDSR_CH2P           (1<<24) /* Channel 2 Pending */
100 #define BA0_HDSR_DHTC           (1<<17) /* DMA Half Terminal Count */
101 #define BA0_HDSR_DTC            (1<<16) /* DMA Terminal Count */
102 #define BA0_HDSR_DRUN           (1<<15) /* DMA Running */
103 #define BA0_HDSR_RQ             (1<<7)  /* Pending Request */
104 
105 #define BA0_DCA0                0x0110  /* Host DMA Engine 0 Current Address */
106 #define BA0_DCC0                0x0114  /* Host DMA Engine 0 Current Count */
107 #define BA0_DBA0                0x0118  /* Host DMA Engine 0 Base Address */
108 #define BA0_DBC0                0x011c  /* Host DMA Engine 0 Base Count */
109 #define BA0_DCA1                0x0120  /* Host DMA Engine 1 Current Address */
110 #define BA0_DCC1                0x0124  /* Host DMA Engine 1 Current Count */
111 #define BA0_DBA1                0x0128  /* Host DMA Engine 1 Base Address */
112 #define BA0_DBC1                0x012c  /* Host DMA Engine 1 Base Count */
113 #define BA0_DCA2                0x0130  /* Host DMA Engine 2 Current Address */
114 #define BA0_DCC2                0x0134  /* Host DMA Engine 2 Current Count */
115 #define BA0_DBA2                0x0138  /* Host DMA Engine 2 Base Address */
116 #define BA0_DBC2                0x013c  /* Host DMA Engine 2 Base Count */
117 #define BA0_DCA3                0x0140  /* Host DMA Engine 3 Current Address */
118 #define BA0_DCC3                0x0144  /* Host DMA Engine 3 Current Count */
119 #define BA0_DBA3                0x0148  /* Host DMA Engine 3 Base Address */
120 #define BA0_DBC3                0x014c  /* Host DMA Engine 3 Base Count */
121 #define BA0_DMR0                0x0150  /* Host DMA Engine 0 Mode */
122 #define BA0_DCR0                0x0154  /* Host DMA Engine 0 Command */
123 #define BA0_DMR1                0x0158  /* Host DMA Engine 1 Mode */
124 #define BA0_DCR1                0x015c  /* Host DMA Engine 1 Command */
125 #define BA0_DMR2                0x0160  /* Host DMA Engine 2 Mode */
126 #define BA0_DCR2                0x0164  /* Host DMA Engine 2 Command */
127 #define BA0_DMR3                0x0168  /* Host DMA Engine 3 Mode */
128 #define BA0_DCR3                0x016c  /* Host DMA Engine 3 Command */
129 
130 #define BA0_DMR_DMA             (1<<29) /* Enable DMA mode */
131 #define BA0_DMR_POLL            (1<<28) /* Enable poll mode */
132 #define BA0_DMR_TBC             (1<<25) /* Transfer By Channel */
133 #define BA0_DMR_CBC             (1<<24) /* Count By Channel (0 = frame resolution) */
134 #define BA0_DMR_SWAPC           (1<<22) /* Swap Left/Right Channels */
135 #define BA0_DMR_SIZE20          (1<<20) /* Sample is 20-bit */
136 #define BA0_DMR_USIGN           (1<<19) /* Unsigned */
137 #define BA0_DMR_BEND            (1<<18) /* Big Endian */
138 #define BA0_DMR_MONO            (1<<17) /* Mono */
139 #define BA0_DMR_SIZE8           (1<<16) /* Sample is 8-bit */
140 #define BA0_DMR_TYPE_DEMAND     (0<<6)
141 #define BA0_DMR_TYPE_SINGLE     (1<<6)
142 #define BA0_DMR_TYPE_BLOCK      (2<<6)
143 #define BA0_DMR_TYPE_CASCADE    (3<<6)  /* Not supported */
144 #define BA0_DMR_DEC             (1<<5)  /* Access Increment (0) or Decrement (1) */
145 #define BA0_DMR_AUTO            (1<<4)  /* Auto-Initialize */
146 #define BA0_DMR_TR_VERIFY       (0<<2)  /* Verify Transfer */
147 #define BA0_DMR_TR_WRITE        (1<<2)  /* Write Transfer */
148 #define BA0_DMR_TR_READ         (2<<2)  /* Read Transfer */
149 
150 #define BA0_DCR_HTCIE           (1<<17) /* Half Terminal Count Interrupt */
151 #define BA0_DCR_TCIE            (1<<16) /* Terminal Count Interrupt */
152 #define BA0_DCR_MSK             (1<<0)  /* DMA Mask bit */
153 
154 #define BA0_FCR0                0x0180  /* FIFO Control 0 */
155 #define BA0_FCR1                0x0184  /* FIFO Control 1 */
156 #define BA0_FCR2                0x0188  /* FIFO Control 2 */
157 #define BA0_FCR3                0x018c  /* FIFO Control 3 */
158 
159 #define BA0_FCR_FEN             (1<<31) /* FIFO Enable bit */
160 #define BA0_FCR_DACZ            (1<<30) /* DAC Zero */
161 #define BA0_FCR_PSH             (1<<29) /* Previous Sample Hold */
162 #define BA0_FCR_RS(x)           (((x)&0x1f)<<24) /* Right Slot Mapping */
163 #define BA0_FCR_LS(x)           (((x)&0x1f)<<16) /* Left Slot Mapping */
164 #define BA0_FCR_SZ(x)           (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
165 #define BA0_FCR_OF(x)           (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
166 
167 #define BA0_FPDR0               0x0190  /* FIFO Polled Data 0 */
168 #define BA0_FPDR1               0x0194  /* FIFO Polled Data 1 */
169 #define BA0_FPDR2               0x0198  /* FIFO Polled Data 2 */
170 #define BA0_FPDR3               0x019c  /* FIFO Polled Data 3 */
171 
172 #define BA0_FCHS                0x020c  /* FIFO Channel Status */
173 #define BA0_FCHS_RCO(x)         (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
174 #define BA0_FCHS_LCO(x)         (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
175 #define BA0_FCHS_MRP(x)         (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
176 #define BA0_FCHS_FE(x)          (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
177 #define BA0_FCHS_FF(x)          (1<<(3+(((x)&3)<<3))) /* FIFO Full */
178 #define BA0_FCHS_IOR(x)         (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
179 #define BA0_FCHS_RCI(x)         (1<<(1+(((x)&3)<<3))) /* Right Channel In */
180 #define BA0_FCHS_LCI(x)         (1<<(0+(((x)&3)<<3))) /* Left Channel In */
181 
182 #define BA0_FSIC0               0x0210  /* FIFO Status and Interrupt Control 0 */
183 #define BA0_FSIC1               0x0214  /* FIFO Status and Interrupt Control 1 */
184 #define BA0_FSIC2               0x0218  /* FIFO Status and Interrupt Control 2 */
185 #define BA0_FSIC3               0x021c  /* FIFO Status and Interrupt Control 3 */
186 
187 #define BA0_FSIC_FIC(x)         (((x)&0x7f)<<24) /* FIFO Interrupt Count */
188 #define BA0_FSIC_FORIE          (1<<23) /* FIFO OverRun Interrupt Enable */
189 #define BA0_FSIC_FURIE          (1<<22) /* FIFO UnderRun Interrupt Enable */
190 #define BA0_FSIC_FSCIE          (1<<16) /* FIFO Sample Count Interrupt Enable */
191 #define BA0_FSIC_FSC(x)         (((x)&0x7f)<<8) /* FIFO Sample Count */
192 #define BA0_FSIC_FOR            (1<<7)  /* FIFO OverRun */
193 #define BA0_FSIC_FUR            (1<<6)  /* FIFO UnderRun */
194 #define BA0_FSIC_FSCR           (1<<0)  /* FIFO Sample Count Reached */
195 
196 #define BA0_PMCS                0x0344  /* Power Management Control/Status */
197 #define BA0_CWPR                0x03e0  /* Configuration Write Protect */
198 
199 #define BA0_EPPMC               0x03e4  /* Extended PCI Power Management Control */
200 #define BA0_EPPMC_FPDN          (1<<14) /* Full Power DowN */
201 
202 #define BA0_GPIOR               0x03e8  /* GPIO Pin Interface Register */
203 
204 #define BA0_SPMC                0x03ec  /* Serial Port Power Management Control (& ASDIN2 enable) */
205 #define BA0_SPMC_GIPPEN         (1<<15) /* GP INT Primary PME# Enable */
206 #define BA0_SPMC_GISPEN         (1<<14) /* GP INT Secondary PME# Enable */
207 #define BA0_SPMC_EESPD          (1<<9)  /* EEPROM Serial Port Disable */
208 #define BA0_SPMC_ASDI2E         (1<<8)  /* ASDIN2 Enable */
209 #define BA0_SPMC_ASDO           (1<<7)  /* Asynchronous ASDOUT Assertion */
210 #define BA0_SPMC_WUP2           (1<<3)  /* Wakeup for Secondary Input */
211 #define BA0_SPMC_WUP1           (1<<2)  /* Wakeup for Primary Input */
212 #define BA0_SPMC_ASYNC          (1<<1)  /* Asynchronous ASYNC Assertion */
213 #define BA0_SPMC_RSTN           (1<<0)  /* Reset Not! */
214 
215 #define BA0_CFLR                0x03f0  /* Configuration Load Register (EEPROM or BIOS) */
216 #define BA0_CFLR_DEFAULT        0x00000001 /* CFLR must be in AC97 link mode */
217 #define BA0_IISR                0x03f4  /* ISA Interrupt Select */
218 #define BA0_TMS                 0x03f8  /* Test Register */
219 #define BA0_SSVID               0x03fc  /* Subsystem ID register */
220 
221 #define BA0_CLKCR1              0x0400  /* Clock Control Register 1 */
222 #define BA0_CLKCR1_CLKON        (1<<25) /* Read Only */
223 #define BA0_CLKCR1_DLLRDY       (1<<24) /* DLL Ready */
224 #define BA0_CLKCR1_DLLOS        (1<<6)  /* DLL Output Select */
225 #define BA0_CLKCR1_SWCE         (1<<5)  /* Clock Enable */
226 #define BA0_CLKCR1_DLLP         (1<<4)  /* DLL PowerUp */
227 #define BA0_CLKCR1_DLLSS        (((x)&3)<<3) /* DLL Source Select */
228 
229 #define BA0_FRR                 0x0410  /* Feature Reporting Register */
230 #define BA0_SLT12O              0x041c  /* Slot 12 GPIO Output Register for AC-Link */
231 
232 #define BA0_SERMC               0x0420  /* Serial Port Master Control */
233 #define BA0_SERMC_FCRN          (1<<27) /* Force Codec Ready Not */
234 #define BA0_SERMC_ODSEN2        (1<<25) /* On-Demand Support Enable ASDIN2 */
235 #define BA0_SERMC_ODSEN1        (1<<24) /* On-Demand Support Enable ASDIN1 */
236 #define BA0_SERMC_SXLB          (1<<21) /* ASDIN2 to ASDOUT Loopback */
237 #define BA0_SERMC_SLB           (1<<20) /* ASDOUT to ASDIN2 Loopback */
238 #define BA0_SERMC_LOVF          (1<<19) /* Loopback Output Valid Frame bit */
239 #define BA0_SERMC_TCID(x)       (((x)&3)<<16) /* Target Secondary Codec ID */
240 #define BA0_SERMC_PXLB          (5<<1)  /* Primary Port External Loopback */
241 #define BA0_SERMC_PLB           (4<<1)  /* Primary Port Internal Loopback */
242 #define BA0_SERMC_PTC           (7<<1)  /* Port Timing Configuration */
243 #define BA0_SERMC_PTC_AC97      (1<<1)  /* AC97 mode */
244 #define BA0_SERMC_MSPE          (1<<0)  /* Master Serial Port Enable */
245 
246 #define BA0_SERC1               0x0428  /* Serial Port Configuration 1 */
247 #define BA0_SERC1_SO1F(x)       (((x)&7)>>1) /* Primary Output Port Format */
248 #define BA0_SERC1_AC97          (1<<1)
249 #define BA0_SERC1_SO1EN         (1<<0)  /* Primary Output Port Enable */
250 
251 #define BA0_SERC2               0x042c  /* Serial Port Configuration 2 */
252 #define BA0_SERC2_SI1F(x)       (((x)&7)>>1) /* Primary Input Port Format */
253 #define BA0_SERC2_AC97          (1<<1)
254 #define BA0_SERC2_SI1EN         (1<<0)  /* Primary Input Port Enable */
255 
256 #define BA0_SLT12M              0x045c  /* Slot 12 Monitor Register for Primary AC-Link */
257 
258 #define BA0_ACCTL               0x0460  /* AC'97 Control */
259 #define BA0_ACCTL_TC            (1<<6)  /* Target Codec */
260 #define BA0_ACCTL_CRW           (1<<4)  /* 0=Write, 1=Read Command */
261 #define BA0_ACCTL_DCV           (1<<3)  /* Dynamic Command Valid */
262 #define BA0_ACCTL_VFRM          (1<<2)  /* Valid Frame */
263 #define BA0_ACCTL_ESYN          (1<<1)  /* Enable Sync */
264 
265 #define BA0_ACSTS               0x0464  /* AC'97 Status */
266 #define BA0_ACSTS_VSTS          (1<<1)  /* Valid Status */
267 #define BA0_ACSTS_CRDY          (1<<0)  /* Codec Ready */
268 
269 #define BA0_ACOSV               0x0468  /* AC'97 Output Slot Valid */
270 #define BA0_ACOSV_SLV(x)        (1<<((x)-3))
271 
272 #define BA0_ACCAD               0x046c  /* AC'97 Command Address */
273 #define BA0_ACCDA               0x0470  /* AC'97 Command Data */
274 
275 #define BA0_ACISV               0x0474  /* AC'97 Input Slot Valid */
276 #define BA0_ACISV_SLV(x)        (1<<((x)-3))
277 
278 #define BA0_ACSAD               0x0478  /* AC'97 Status Address */
279 #define BA0_ACSDA               0x047c  /* AC'97 Status Data */
280 #define BA0_JSPT                0x0480  /* Joystick poll/trigger */
281 #define BA0_JSCTL               0x0484  /* Joystick control */
282 #define BA0_JSC1                0x0488  /* Joystick control */
283 #define BA0_JSC2                0x048c  /* Joystick control */
284 #define BA0_JSIO                0x04a0
285 
286 #define BA0_MIDCR               0x0490  /* MIDI Control */
287 #define BA0_MIDCR_MRST          (1<<5)  /* Reset MIDI Interface */
288 #define BA0_MIDCR_MLB           (1<<4)  /* MIDI Loop Back Enable */
289 #define BA0_MIDCR_TIE           (1<<3)  /* MIDI Transmuit Interrupt Enable */
290 #define BA0_MIDCR_RIE           (1<<2)  /* MIDI Receive Interrupt Enable */
291 #define BA0_MIDCR_RXE           (1<<1)  /* MIDI Receive Enable */
292 #define BA0_MIDCR_TXE           (1<<0)  /* MIDI Transmit Enable */
293 
294 #define BA0_MIDCMD              0x0494  /* MIDI Command (wo) */
295 
296 #define BA0_MIDSR               0x0494  /* MIDI Status (ro) */
297 #define BA0_MIDSR_RDA           (1<<15) /* Sticky bit (RBE 1->0) */
298 #define BA0_MIDSR_TBE           (1<<14) /* Sticky bit (TBF 0->1) */
299 #define BA0_MIDSR_RBE           (1<<7)  /* Receive Buffer Empty */
300 #define BA0_MIDSR_TBF           (1<<6)  /* Transmit Buffer Full */
301 
302 #define BA0_MIDWP               0x0498  /* MIDI Write */
303 #define BA0_MIDRP               0x049c  /* MIDI Read (ro) */
304 
305 #define BA0_AODSD1              0x04a8  /* AC'97 On-Demand Slot Disable for primary link (ro) */
306 #define BA0_AODSD1_NDS(x)       (1<<((x)-3))
307 
308 #define BA0_AODSD2              0x04ac  /* AC'97 On-Demand Slot Disable for secondary link (ro) */
309 #define BA0_AODSD2_NDS(x)       (1<<((x)-3))
310 
311 #define BA0_CFGI                0x04b0  /* Configure Interface (EEPROM interface) */
312 #define BA0_SLT12M2             0x04dc  /* Slot 12 Monitor Register 2 for secondary AC-link */
313 #define BA0_ACSTS2              0x04e4  /* AC'97 Status Register 2 */
314 #define BA0_ACISV2              0x04f4  /* AC'97 Input Slot Valid Register 2 */
315 #define BA0_ACSAD2              0x04f8  /* AC'97 Status Address Register 2 */
316 #define BA0_ACSDA2              0x04fc  /* AC'97 Status Data Register 2 */
317 #define BA0_FMSR                0x0730  /* FM Synthesis Status (ro) */
318 #define BA0_B0AP                0x0730  /* FM Bank 0 Address Port (wo) */
319 #define BA0_FMDP                0x0734  /* FM Data Port */
320 #define BA0_B1AP                0x0738  /* FM Bank 1 Address Port */
321 #define BA0_B1DP                0x073c  /* FM Bank 1 Data Port */
322 
323 #define BA0_SSPM                0x0740  /* Sound System Power Management */
324 #define BA0_SSPM_MIXEN          (1<<6)  /* Playback SRC + FM/Wavetable MIX */
325 #define BA0_SSPM_CSRCEN         (1<<5)  /* Capture Sample Rate Converter Enable */
326 #define BA0_SSPM_PSRCEN         (1<<4)  /* Playback Sample Rate Converter Enable */
327 #define BA0_SSPM_JSEN           (1<<3)  /* Joystick Enable */
328 #define BA0_SSPM_ACLEN          (1<<2)  /* Serial Port Engine and AC-Link Enable */
329 #define BA0_SSPM_FMEN           (1<<1)  /* FM Synthesis Block Enable */
330 
331 #define BA0_DACSR               0x0744  /* DAC Sample Rate - Playback SRC */
332 #define BA0_ADCSR               0x0748  /* ADC Sample Rate - Capture SRC */
333 
334 #define BA0_SSCR                0x074c  /* Sound System Control Register */
335 #define BA0_SSCR_HVS1           (1<<23) /* Hardwave Volume Step (0=1,1=2) */
336 #define BA0_SSCR_MVCS           (1<<19) /* Master Volume Codec Select */
337 #define BA0_SSCR_MVLD           (1<<18) /* Master Volume Line Out Disable */
338 #define BA0_SSCR_MVAD           (1<<17) /* Master Volume Alternate Out Disable */
339 #define BA0_SSCR_MVMD           (1<<16) /* Master Volume Mono Out Disable */
340 #define BA0_SSCR_XLPSRC         (1<<8)  /* External SRC Loopback Mode */
341 #define BA0_SSCR_LPSRC          (1<<7)  /* SRC Loopback Mode */
342 #define BA0_SSCR_CDTX           (1<<5)  /* CD Transfer Data */
343 #define BA0_SSCR_HVC            (1<<3)  /* Harware Volume Control Enable */
344 
345 #define BA0_FMLVC               0x0754  /* FM Synthesis Left Volume Control */
346 #define BA0_FMRVC               0x0758  /* FM Synthesis Right Volume Control */
347 #define BA0_SRCSA               0x075c  /* SRC Slot Assignments */
348 #define BA0_PPLVC               0x0760  /* PCM Playback Left Volume Control */
349 #define BA0_PPRVC               0x0764  /* PCM Playback Right Volume Control */
350 #define BA0_PASR                0x0768  /* playback sample rate */
351 #define BA0_CASR                0x076C  /* capture sample rate */
352 
353 /* Source Slot Numbers - Playback */
354 #define SRCSLOT_LEFT_PCM_PLAYBACK               0
355 #define SRCSLOT_RIGHT_PCM_PLAYBACK              1
356 #define SRCSLOT_PHONE_LINE_1_DAC                2
357 #define SRCSLOT_CENTER_PCM_PLAYBACK             3
358 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK      4
359 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK     5
360 #define SRCSLOT_LFE_PCM_PLAYBACK                6
361 #define SRCSLOT_PHONE_LINE_2_DAC                7
362 #define SRCSLOT_HEADSET_DAC                     8
363 #define SRCSLOT_LEFT_WT                         29  /* invalid for BA0_SRCSA */
364 #define SRCSLOT_RIGHT_WT                        30  /* invalid for BA0_SRCSA */
365 
366 /* Source Slot Numbers - Capture */
367 #define SRCSLOT_LEFT_PCM_RECORD                 10
368 #define SRCSLOT_RIGHT_PCM_RECORD                11
369 #define SRCSLOT_PHONE_LINE_1_ADC                12
370 #define SRCSLOT_MIC_ADC                         13
371 #define SRCSLOT_PHONE_LINE_2_ADC                17
372 #define SRCSLOT_HEADSET_ADC                     18
373 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD       20
374 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD      21
375 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC      22
376 #define SRCSLOT_SECONDARY_MIC_ADC               23
377 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC      27
378 #define SRCSLOT_SECONDARY_HEADSET_ADC           28
379 
380 /* Source Slot Numbers - Others */
381 #define SRCSLOT_POWER_DOWN                      31
382 
383 /* MIDI modes */
384 #define CS4281_MODE_OUTPUT              (1<<0)
385 #define CS4281_MODE_INPUT               (1<<1)
386 
387 /* joystick bits */
388 /* Bits for JSPT */
389 #define JSPT_CAX                                0x00000001
390 #define JSPT_CAY                                0x00000002
391 #define JSPT_CBX                                0x00000004
392 #define JSPT_CBY                                0x00000008
393 #define JSPT_BA1                                0x00000010
394 #define JSPT_BA2                                0x00000020
395 #define JSPT_BB1                                0x00000040
396 #define JSPT_BB2                                0x00000080
397 
398 /* Bits for JSCTL */
399 #define JSCTL_SP_MASK                           0x00000003
400 #define JSCTL_SP_SLOW                           0x00000000
401 #define JSCTL_SP_MEDIUM_SLOW                    0x00000001
402 #define JSCTL_SP_MEDIUM_FAST                    0x00000002
403 #define JSCTL_SP_FAST                           0x00000003
404 #define JSCTL_ARE                               0x00000004
405 
406 /* Data register pairs masks */
407 #define JSC1_Y1V_MASK                           0x0000FFFF
408 #define JSC1_X1V_MASK                           0xFFFF0000
409 #define JSC1_Y1V_SHIFT                          0
410 #define JSC1_X1V_SHIFT                          16
411 #define JSC2_Y2V_MASK                           0x0000FFFF
412 #define JSC2_X2V_MASK                           0xFFFF0000
413 #define JSC2_Y2V_SHIFT                          0
414 #define JSC2_X2V_SHIFT                          16
415 
416 /* JS GPIO */
417 #define JSIO_DAX                                0x00000001
418 #define JSIO_DAY                                0x00000002
419 #define JSIO_DBX                                0x00000004
420 #define JSIO_DBY                                0x00000008
421 #define JSIO_AXOE                               0x00000010
422 #define JSIO_AYOE                               0x00000020
423 #define JSIO_BXOE                               0x00000040
424 #define JSIO_BYOE                               0x00000080
425 
426 /*
427  *
428  */
429 
430 struct cs4281_dma {
431         struct snd_pcm_substream *substream;
432         unsigned int regDBA;            /* offset to DBA register */
433         unsigned int regDCA;            /* offset to DCA register */
434         unsigned int regDBC;            /* offset to DBC register */
435         unsigned int regDCC;            /* offset to DCC register */
436         unsigned int regDMR;            /* offset to DMR register */
437         unsigned int regDCR;            /* offset to DCR register */
438         unsigned int regHDSR;           /* offset to HDSR register */
439         unsigned int regFCR;            /* offset to FCR register */
440         unsigned int regFSIC;           /* offset to FSIC register */
441         unsigned int valDMR;            /* DMA mode */
442         unsigned int valDCR;            /* DMA command */
443         unsigned int valFCR;            /* FIFO control */
444         unsigned int fifo_offset;       /* FIFO offset within BA1 */
445         unsigned char left_slot;        /* FIFO left slot */
446         unsigned char right_slot;       /* FIFO right slot */
447         int frag;                       /* period number */
448 };
449 
450 #define SUSPEND_REGISTERS       20
451 
452 struct cs4281 {
453         int irq;
454 
455         void __iomem *ba0;              /* virtual (accessible) address */
456         void __iomem *ba1;              /* virtual (accessible) address */
457         unsigned long ba0_addr;
458         unsigned long ba1_addr;
459 
460         int dual_codec;
461 
462         struct snd_ac97_bus *ac97_bus;
463         struct snd_ac97 *ac97;
464         struct snd_ac97 *ac97_secondary;
465 
466         struct pci_dev *pci;
467         struct snd_card *card;
468         struct snd_pcm *pcm;
469         struct snd_rawmidi *rmidi;
470         struct snd_rawmidi_substream *midi_input;
471         struct snd_rawmidi_substream *midi_output;
472 
473         struct cs4281_dma dma[4];
474 
475         unsigned char src_left_play_slot;
476         unsigned char src_right_play_slot;
477         unsigned char src_left_rec_slot;
478         unsigned char src_right_rec_slot;
479 
480         unsigned int spurious_dhtc_irq;
481         unsigned int spurious_dtc_irq;
482 
483         spinlock_t reg_lock;
484         unsigned int midcr;
485         unsigned int uartm;
486 
487         struct gameport *gameport;
488 
489 #ifdef CONFIG_PM_SLEEP
490         u32 suspend_regs[SUSPEND_REGISTERS];
491 #endif
492 
493 };
494 
495 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
496 
497 static const struct pci_device_id snd_cs4281_ids[] = {
498         { PCI_VDEVICE(CIRRUS, 0x6005), 0, },    /* CS4281 */
499         { 0, }
500 };
501 
502 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
503 
504 /*
505  *  constants
506  */
507 
508 #define CS4281_FIFO_SIZE        32
509 
510 /*
511  *  common I/O routines
512  */
513 
514 static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
515                                       unsigned int val)
516 {
517         writel(val, chip->ba0 + offset);
518 }
519 
520 static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
521 {
522         return readl(chip->ba0 + offset);
523 }
524 
525 static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
526                                   unsigned short reg, unsigned short val)
527 {
528         /*
529          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
530          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
531          *  3. Write ACCTL = Control Register = 460h for initiating the write
532          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
533          *  5. if DCV not cleared, break and return error
534          */
535         struct cs4281 *chip = ac97->private_data;
536         int count;
537 
538         /*
539          *  Setup the AC97 control registers on the CS461x to send the
540          *  appropriate command to the AC97 to perform the read.
541          *  ACCAD = Command Address Register = 46Ch
542          *  ACCDA = Command Data Register = 470h
543          *  ACCTL = Control Register = 460h
544          *  set DCV - will clear when process completed
545          *  reset CRW - Write command
546          *  set VFRM - valid frame enabled
547          *  set ESYN - ASYNC generation enabled
548          *  set RSTN - ARST# inactive, AC97 codec not reset
549          */
550         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
551         snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
552         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
553                                             BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
554         for (count = 0; count < 2000; count++) {
555                 /*
556                  *  First, we want to wait for a short time.
557                  */
558                 udelay(10);
559                 /*
560                  *  Now, check to see if the write has completed.
561                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
562                  */
563                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
564                         return;
565                 }
566         }
567         dev_err(chip->card->dev,
568                 "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
569 }
570 
571 static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
572                                            unsigned short reg)
573 {
574         struct cs4281 *chip = ac97->private_data;
575         int count;
576         unsigned short result;
577         // FIXME: volatile is necessary in the following due to a bug of
578         // some gcc versions
579         volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
580 
581         /*
582          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
583          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97 
584          *  3. Write ACCTL = Control Register = 460h for initiating the write
585          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
586          *  5. if DCV not cleared, break and return error
587          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
588          */
589 
590         snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
591 
592         /*
593          *  Setup the AC97 control registers on the CS461x to send the
594          *  appropriate command to the AC97 to perform the read.
595          *  ACCAD = Command Address Register = 46Ch
596          *  ACCDA = Command Data Register = 470h
597          *  ACCTL = Control Register = 460h
598          *  set DCV - will clear when process completed
599          *  set CRW - Read command
600          *  set VFRM - valid frame enabled
601          *  set ESYN - ASYNC generation enabled
602          *  set RSTN - ARST# inactive, AC97 codec not reset
603          */
604 
605         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
606         snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
607         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
608                                             BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
609                            (ac97_num ? BA0_ACCTL_TC : 0));
610 
611 
612         /*
613          *  Wait for the read to occur.
614          */
615         for (count = 0; count < 500; count++) {
616                 /*
617                  *  First, we want to wait for a short time.
618                  */
619                 udelay(10);
620                 /*
621                  *  Now, check to see if the read has completed.
622                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
623                  */
624                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
625                         goto __ok1;
626         }
627 
628         dev_err(chip->card->dev,
629                 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
630         result = 0xffff;
631         goto __end;
632         
633       __ok1:
634         /*
635          *  Wait for the valid status bit to go active.
636          */
637         for (count = 0; count < 100; count++) {
638                 /*
639                  *  Read the AC97 status register.
640                  *  ACSTS = Status Register = 464h
641                  *  VSTS - Valid Status
642                  */
643                 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
644                         goto __ok2;
645                 udelay(10);
646         }
647         
648         dev_err(chip->card->dev,
649                 "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
650         result = 0xffff;
651         goto __end;
652 
653       __ok2:
654         /*
655          *  Read the data returned from the AC97 register.
656          *  ACSDA = Status Data Register = 474h
657          */
658         result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
659 
660       __end:
661         return result;
662 }
663 
664 /*
665  *  PCM part
666  */
667 
668 static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
669 {
670         struct cs4281_dma *dma = substream->runtime->private_data;
671         struct cs4281 *chip = snd_pcm_substream_chip(substream);
672 
673         spin_lock(&chip->reg_lock);
674         switch (cmd) {
675         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
676                 dma->valDCR |= BA0_DCR_MSK;
677                 dma->valFCR |= BA0_FCR_FEN;
678                 break;
679         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
680                 dma->valDCR &= ~BA0_DCR_MSK;
681                 dma->valFCR &= ~BA0_FCR_FEN;
682                 break;
683         case SNDRV_PCM_TRIGGER_START:
684         case SNDRV_PCM_TRIGGER_RESUME:
685                 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
686                 dma->valDMR |= BA0_DMR_DMA;
687                 dma->valDCR &= ~BA0_DCR_MSK;
688                 dma->valFCR |= BA0_FCR_FEN;
689                 break;
690         case SNDRV_PCM_TRIGGER_STOP:
691         case SNDRV_PCM_TRIGGER_SUSPEND:
692                 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
693                 dma->valDCR |= BA0_DCR_MSK;
694                 dma->valFCR &= ~BA0_FCR_FEN;
695                 /* Leave wave playback FIFO enabled for FM */
696                 if (dma->regFCR != BA0_FCR0)
697                         dma->valFCR &= ~BA0_FCR_FEN;
698                 break;
699         default:
700                 spin_unlock(&chip->reg_lock);
701                 return -EINVAL;
702         }
703         snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
704         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
705         snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
706         spin_unlock(&chip->reg_lock);
707         return 0;
708 }
709 
710 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
711 {
712         unsigned int val = ~0;
713         
714         if (real_rate)
715                 *real_rate = rate;
716         /* special "hardcoded" rates */
717         switch (rate) {
718         case 8000:      return 5;
719         case 11025:     return 4;
720         case 16000:     return 3;
721         case 22050:     return 2;
722         case 44100:     return 1;
723         case 48000:     return 0;
724         default:
725                 goto __variable;
726         }
727       __variable:
728         val = 1536000 / rate;
729         if (real_rate)
730                 *real_rate = 1536000 / val;
731         return val;
732 }
733 
734 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
735                             struct snd_pcm_runtime *runtime,
736                             int capture, int src)
737 {
738         int rec_mono;
739 
740         dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
741                       (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
742         if (runtime->channels == 1)
743                 dma->valDMR |= BA0_DMR_MONO;
744         if (snd_pcm_format_unsigned(runtime->format) > 0)
745                 dma->valDMR |= BA0_DMR_USIGN;
746         if (snd_pcm_format_big_endian(runtime->format) > 0)
747                 dma->valDMR |= BA0_DMR_BEND;
748         switch (snd_pcm_format_width(runtime->format)) {
749         case 8: dma->valDMR |= BA0_DMR_SIZE8;
750                 if (runtime->channels == 1)
751                         dma->valDMR |= BA0_DMR_SWAPC;
752                 break;
753         case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
754         }
755         dma->frag = 0;  /* for workaround */
756         dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
757         if (runtime->buffer_size != runtime->period_size)
758                 dma->valDCR |= BA0_DCR_HTCIE;
759         /* Initialize DMA */
760         snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
761         snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
762         rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
763         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
764                                             (chip->src_right_play_slot << 8) |
765                                             (chip->src_left_rec_slot << 16) |
766                                             ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
767         if (!src)
768                 goto __skip_src;
769         if (!capture) {
770                 if (dma->left_slot == chip->src_left_play_slot) {
771                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
772                         snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
773                         snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
774                 }
775         } else {
776                 if (dma->left_slot == chip->src_left_rec_slot) {
777                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
778                         snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
779                         snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
780                 }
781         }
782       __skip_src:
783         /* Deactivate wave playback FIFO before changing slot assignments */
784         if (dma->regFCR == BA0_FCR0)
785                 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
786         /* Initialize FIFO */
787         dma->valFCR = BA0_FCR_LS(dma->left_slot) |
788                       BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
789                       BA0_FCR_SZ(CS4281_FIFO_SIZE) |
790                       BA0_FCR_OF(dma->fifo_offset);
791         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
792         /* Activate FIFO again for FM playback */
793         if (dma->regFCR == BA0_FCR0)
794                 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
795         /* Clear FIFO Status and Interrupt Control Register */
796         snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
797 }
798 
799 static int snd_cs4281_hw_params(struct snd_pcm_substream *substream,
800                                 struct snd_pcm_hw_params *hw_params)
801 {
802         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
803 }
804 
805 static int snd_cs4281_hw_free(struct snd_pcm_substream *substream)
806 {
807         return snd_pcm_lib_free_pages(substream);
808 }
809 
810 static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
811 {
812         struct snd_pcm_runtime *runtime = substream->runtime;
813         struct cs4281_dma *dma = runtime->private_data;
814         struct cs4281 *chip = snd_pcm_substream_chip(substream);
815 
816         spin_lock_irq(&chip->reg_lock);
817         snd_cs4281_mode(chip, dma, runtime, 0, 1);
818         spin_unlock_irq(&chip->reg_lock);
819         return 0;
820 }
821 
822 static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
823 {
824         struct snd_pcm_runtime *runtime = substream->runtime;
825         struct cs4281_dma *dma = runtime->private_data;
826         struct cs4281 *chip = snd_pcm_substream_chip(substream);
827 
828         spin_lock_irq(&chip->reg_lock);
829         snd_cs4281_mode(chip, dma, runtime, 1, 1);
830         spin_unlock_irq(&chip->reg_lock);
831         return 0;
832 }
833 
834 static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
835 {
836         struct snd_pcm_runtime *runtime = substream->runtime;
837         struct cs4281_dma *dma = runtime->private_data;
838         struct cs4281 *chip = snd_pcm_substream_chip(substream);
839 
840         /*
841         dev_dbg(chip->card->dev,
842                 "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",
843                 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
844                jiffies);
845         */
846         return runtime->buffer_size -
847                snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
848 }
849 
850 static struct snd_pcm_hardware snd_cs4281_playback =
851 {
852         .info =                 SNDRV_PCM_INFO_MMAP |
853                                 SNDRV_PCM_INFO_INTERLEAVED |
854                                 SNDRV_PCM_INFO_MMAP_VALID |
855                                 SNDRV_PCM_INFO_PAUSE |
856                                 SNDRV_PCM_INFO_RESUME,
857         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
858                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
859                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
860                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
861                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
862         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
863         .rate_min =             4000,
864         .rate_max =             48000,
865         .channels_min =         1,
866         .channels_max =         2,
867         .buffer_bytes_max =     (512*1024),
868         .period_bytes_min =     64,
869         .period_bytes_max =     (512*1024),
870         .periods_min =          1,
871         .periods_max =          2,
872         .fifo_size =            CS4281_FIFO_SIZE,
873 };
874 
875 static struct snd_pcm_hardware snd_cs4281_capture =
876 {
877         .info =                 SNDRV_PCM_INFO_MMAP |
878                                 SNDRV_PCM_INFO_INTERLEAVED |
879                                 SNDRV_PCM_INFO_MMAP_VALID |
880                                 SNDRV_PCM_INFO_PAUSE |
881                                 SNDRV_PCM_INFO_RESUME,
882         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
883                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
884                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
885                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
886                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
887         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
888         .rate_min =             4000,
889         .rate_max =             48000,
890         .channels_min =         1,
891         .channels_max =         2,
892         .buffer_bytes_max =     (512*1024),
893         .period_bytes_min =     64,
894         .period_bytes_max =     (512*1024),
895         .periods_min =          1,
896         .periods_max =          2,
897         .fifo_size =            CS4281_FIFO_SIZE,
898 };
899 
900 static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
901 {
902         struct cs4281 *chip = snd_pcm_substream_chip(substream);
903         struct snd_pcm_runtime *runtime = substream->runtime;
904         struct cs4281_dma *dma;
905 
906         dma = &chip->dma[0];
907         dma->substream = substream;
908         dma->left_slot = 0;
909         dma->right_slot = 1;
910         runtime->private_data = dma;
911         runtime->hw = snd_cs4281_playback;
912         /* should be detected from the AC'97 layer, but it seems
913            that although CS4297A rev B reports 18-bit ADC resolution,
914            samples are 20-bit */
915         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
916         return 0;
917 }
918 
919 static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
920 {
921         struct cs4281 *chip = snd_pcm_substream_chip(substream);
922         struct snd_pcm_runtime *runtime = substream->runtime;
923         struct cs4281_dma *dma;
924 
925         dma = &chip->dma[1];
926         dma->substream = substream;
927         dma->left_slot = 10;
928         dma->right_slot = 11;
929         runtime->private_data = dma;
930         runtime->hw = snd_cs4281_capture;
931         /* should be detected from the AC'97 layer, but it seems
932            that although CS4297A rev B reports 18-bit ADC resolution,
933            samples are 20-bit */
934         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
935         return 0;
936 }
937 
938 static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
939 {
940         struct cs4281_dma *dma = substream->runtime->private_data;
941 
942         dma->substream = NULL;
943         return 0;
944 }
945 
946 static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
947 {
948         struct cs4281_dma *dma = substream->runtime->private_data;
949 
950         dma->substream = NULL;
951         return 0;
952 }
953 
954 static struct snd_pcm_ops snd_cs4281_playback_ops = {
955         .open =         snd_cs4281_playback_open,
956         .close =        snd_cs4281_playback_close,
957         .ioctl =        snd_pcm_lib_ioctl,
958         .hw_params =    snd_cs4281_hw_params,
959         .hw_free =      snd_cs4281_hw_free,
960         .prepare =      snd_cs4281_playback_prepare,
961         .trigger =      snd_cs4281_trigger,
962         .pointer =      snd_cs4281_pointer,
963 };
964 
965 static struct snd_pcm_ops snd_cs4281_capture_ops = {
966         .open =         snd_cs4281_capture_open,
967         .close =        snd_cs4281_capture_close,
968         .ioctl =        snd_pcm_lib_ioctl,
969         .hw_params =    snd_cs4281_hw_params,
970         .hw_free =      snd_cs4281_hw_free,
971         .prepare =      snd_cs4281_capture_prepare,
972         .trigger =      snd_cs4281_trigger,
973         .pointer =      snd_cs4281_pointer,
974 };
975 
976 static int snd_cs4281_pcm(struct cs4281 *chip, int device)
977 {
978         struct snd_pcm *pcm;
979         int err;
980 
981         err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
982         if (err < 0)
983                 return err;
984 
985         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
986         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
987 
988         pcm->private_data = chip;
989         pcm->info_flags = 0;
990         strcpy(pcm->name, "CS4281");
991         chip->pcm = pcm;
992 
993         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
994                                               snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
995 
996         return 0;
997 }
998 
999 /*
1000  *  Mixer section
1001  */
1002 
1003 #define CS_VOL_MASK     0x1f
1004 
1005 static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
1006                                   struct snd_ctl_elem_info *uinfo)
1007 {
1008         uinfo->type              = SNDRV_CTL_ELEM_TYPE_INTEGER;
1009         uinfo->count             = 2;
1010         uinfo->value.integer.min = 0;
1011         uinfo->value.integer.max = CS_VOL_MASK;
1012         return 0;
1013 }
1014  
1015 static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
1016                                  struct snd_ctl_elem_value *ucontrol)
1017 {
1018         struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1019         int regL = (kcontrol->private_value >> 16) & 0xffff;
1020         int regR = kcontrol->private_value & 0xffff;
1021         int volL, volR;
1022 
1023         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1024         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1025 
1026         ucontrol->value.integer.value[0] = volL;
1027         ucontrol->value.integer.value[1] = volR;
1028         return 0;
1029 }
1030 
1031 static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
1032                                  struct snd_ctl_elem_value *ucontrol)
1033 {
1034         struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1035         int change = 0;
1036         int regL = (kcontrol->private_value >> 16) & 0xffff;
1037         int regR = kcontrol->private_value & 0xffff;
1038         int volL, volR;
1039 
1040         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1041         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1042 
1043         if (ucontrol->value.integer.value[0] != volL) {
1044                 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1045                 snd_cs4281_pokeBA0(chip, regL, volL);
1046                 change = 1;
1047         }
1048         if (ucontrol->value.integer.value[1] != volR) {
1049                 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1050                 snd_cs4281_pokeBA0(chip, regR, volR);
1051                 change = 1;
1052         }
1053         return change;
1054 }
1055 
1056 static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
1057 
1058 static struct snd_kcontrol_new snd_cs4281_fm_vol = 
1059 {
1060         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1061         .name = "Synth Playback Volume",
1062         .info = snd_cs4281_info_volume, 
1063         .get = snd_cs4281_get_volume,
1064         .put = snd_cs4281_put_volume, 
1065         .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1066         .tlv = { .p = db_scale_dsp },
1067 };
1068 
1069 static struct snd_kcontrol_new snd_cs4281_pcm_vol = 
1070 {
1071         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1072         .name = "PCM Stream Playback Volume",
1073         .info = snd_cs4281_info_volume, 
1074         .get = snd_cs4281_get_volume,
1075         .put = snd_cs4281_put_volume, 
1076         .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1077         .tlv = { .p = db_scale_dsp },
1078 };
1079 
1080 static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1081 {
1082         struct cs4281 *chip = bus->private_data;
1083         chip->ac97_bus = NULL;
1084 }
1085 
1086 static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
1087 {
1088         struct cs4281 *chip = ac97->private_data;
1089         if (ac97->num)
1090                 chip->ac97_secondary = NULL;
1091         else
1092                 chip->ac97 = NULL;
1093 }
1094 
1095 static int snd_cs4281_mixer(struct cs4281 *chip)
1096 {
1097         struct snd_card *card = chip->card;
1098         struct snd_ac97_template ac97;
1099         int err;
1100         static struct snd_ac97_bus_ops ops = {
1101                 .write = snd_cs4281_ac97_write,
1102                 .read = snd_cs4281_ac97_read,
1103         };
1104 
1105         if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1106                 return err;
1107         chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1108 
1109         memset(&ac97, 0, sizeof(ac97));
1110         ac97.private_data = chip;
1111         ac97.private_free = snd_cs4281_mixer_free_ac97;
1112         if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1113                 return err;
1114         if (chip->dual_codec) {
1115                 ac97.num = 1;
1116                 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1117                         return err;
1118         }
1119         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1120                 return err;
1121         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1122                 return err;
1123         return 0;
1124 }
1125 
1126 
1127 /*
1128  * proc interface
1129  */
1130 
1131 static void snd_cs4281_proc_read(struct snd_info_entry *entry, 
1132                                   struct snd_info_buffer *buffer)
1133 {
1134         struct cs4281 *chip = entry->private_data;
1135 
1136         snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1137         snd_iprintf(buffer, "Spurious half IRQs   : %u\n", chip->spurious_dhtc_irq);
1138         snd_iprintf(buffer, "Spurious end IRQs    : %u\n", chip->spurious_dtc_irq);
1139 }
1140 
1141 static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,
1142                                    void *file_private_data,
1143                                    struct file *file, char __user *buf,
1144                                    size_t count, loff_t pos)
1145 {
1146         struct cs4281 *chip = entry->private_data;
1147         
1148         if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
1149                 return -EFAULT;
1150         return count;
1151 }
1152 
1153 static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,
1154                                    void *file_private_data,
1155                                    struct file *file, char __user *buf,
1156                                    size_t count, loff_t pos)
1157 {
1158         struct cs4281 *chip = entry->private_data;
1159         
1160         if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
1161                 return -EFAULT;
1162         return count;
1163 }
1164 
1165 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1166         .read = snd_cs4281_BA0_read,
1167 };
1168 
1169 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1170         .read = snd_cs4281_BA1_read,
1171 };
1172 
1173 static void snd_cs4281_proc_init(struct cs4281 *chip)
1174 {
1175         struct snd_info_entry *entry;
1176 
1177         if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1178                 snd_info_set_text_ops(entry, chip, snd_cs4281_proc_read);
1179         if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1180                 entry->content = SNDRV_INFO_CONTENT_DATA;
1181                 entry->private_data = chip;
1182                 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1183                 entry->size = CS4281_BA0_SIZE;
1184         }
1185         if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1186                 entry->content = SNDRV_INFO_CONTENT_DATA;
1187                 entry->private_data = chip;
1188                 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1189                 entry->size = CS4281_BA1_SIZE;
1190         }
1191 }
1192 
1193 /*
1194  * joystick support
1195  */
1196 
1197 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1198 
1199 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1200 {
1201         struct cs4281 *chip = gameport_get_port_data(gameport);
1202 
1203         if (snd_BUG_ON(!chip))
1204                 return;
1205         snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1206 }
1207 
1208 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1209 {
1210         struct cs4281 *chip = gameport_get_port_data(gameport);
1211 
1212         if (snd_BUG_ON(!chip))
1213                 return 0;
1214         return snd_cs4281_peekBA0(chip, BA0_JSPT);
1215 }
1216 
1217 #ifdef COOKED_MODE
1218 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
1219                                            int *axes, int *buttons)
1220 {
1221         struct cs4281 *chip = gameport_get_port_data(gameport);
1222         unsigned js1, js2, jst;
1223         
1224         if (snd_BUG_ON(!chip))
1225                 return 0;
1226 
1227         js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1228         js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1229         jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1230         
1231         *buttons = (~jst >> 4) & 0x0F; 
1232         
1233         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1234         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1235         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1236         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1237 
1238         for (jst = 0; jst < 4; ++jst)
1239                 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1240         return 0;
1241 }
1242 #else
1243 #define snd_cs4281_gameport_cooked_read NULL
1244 #endif
1245 
1246 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1247 {
1248         switch (mode) {
1249 #ifdef COOKED_MODE
1250         case GAMEPORT_MODE_COOKED:
1251                 return 0;
1252 #endif
1253         case GAMEPORT_MODE_RAW:
1254                 return 0;
1255         default:
1256                 return -1;
1257         }
1258         return 0;
1259 }
1260 
1261 static int snd_cs4281_create_gameport(struct cs4281 *chip)
1262 {
1263         struct gameport *gp;
1264 
1265         chip->gameport = gp = gameport_allocate_port();
1266         if (!gp) {
1267                 dev_err(chip->card->dev,
1268                         "cannot allocate memory for gameport\n");
1269                 return -ENOMEM;
1270         }
1271 
1272         gameport_set_name(gp, "CS4281 Gameport");
1273         gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1274         gameport_set_dev_parent(gp, &chip->pci->dev);
1275         gp->open = snd_cs4281_gameport_open;
1276         gp->read = snd_cs4281_gameport_read;
1277         gp->trigger = snd_cs4281_gameport_trigger;
1278         gp->cooked_read = snd_cs4281_gameport_cooked_read;
1279         gameport_set_port_data(gp, chip);
1280 
1281         snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1282         snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1283 
1284         gameport_register_port(gp);
1285 
1286         return 0;
1287 }
1288 
1289 static void snd_cs4281_free_gameport(struct cs4281 *chip)
1290 {
1291         if (chip->gameport) {
1292                 gameport_unregister_port(chip->gameport);
1293                 chip->gameport = NULL;
1294         }
1295 }
1296 #else
1297 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1298 static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1299 #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1300 
1301 static int snd_cs4281_free(struct cs4281 *chip)
1302 {
1303         snd_cs4281_free_gameport(chip);
1304 
1305         if (chip->irq >= 0)
1306                 synchronize_irq(chip->irq);
1307 
1308         /* Mask interrupts */
1309         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1310         /* Stop the DLL Clock logic. */
1311         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1312         /* Sound System Power Management - Turn Everything OFF */
1313         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1314         /* PCI interface - D3 state */
1315         pci_set_power_state(chip->pci, PCI_D3hot);
1316 
1317         if (chip->irq >= 0)
1318                 free_irq(chip->irq, chip);
1319         iounmap(chip->ba0);
1320         iounmap(chip->ba1);
1321         pci_release_regions(chip->pci);
1322         pci_disable_device(chip->pci);
1323 
1324         kfree(chip);
1325         return 0;
1326 }
1327 
1328 static int snd_cs4281_dev_free(struct snd_device *device)
1329 {
1330         struct cs4281 *chip = device->device_data;
1331         return snd_cs4281_free(chip);
1332 }
1333 
1334 static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1335 
1336 static int snd_cs4281_create(struct snd_card *card,
1337                              struct pci_dev *pci,
1338                              struct cs4281 **rchip,
1339                              int dual_codec)
1340 {
1341         struct cs4281 *chip;
1342         unsigned int tmp;
1343         int err;
1344         static struct snd_device_ops ops = {
1345                 .dev_free =     snd_cs4281_dev_free,
1346         };
1347 
1348         *rchip = NULL;
1349         if ((err = pci_enable_device(pci)) < 0)
1350                 return err;
1351         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1352         if (chip == NULL) {
1353                 pci_disable_device(pci);
1354                 return -ENOMEM;
1355         }
1356         spin_lock_init(&chip->reg_lock);
1357         chip->card = card;
1358         chip->pci = pci;
1359         chip->irq = -1;
1360         pci_set_master(pci);
1361         if (dual_codec < 0 || dual_codec > 3) {
1362                 dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec);
1363                 dual_codec = 0;
1364         }
1365         chip->dual_codec = dual_codec;
1366 
1367         if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1368                 kfree(chip);
1369                 pci_disable_device(pci);
1370                 return err;
1371         }
1372         chip->ba0_addr = pci_resource_start(pci, 0);
1373         chip->ba1_addr = pci_resource_start(pci, 1);
1374 
1375         chip->ba0 = pci_ioremap_bar(pci, 0);
1376         chip->ba1 = pci_ioremap_bar(pci, 1);
1377         if (!chip->ba0 || !chip->ba1) {
1378                 snd_cs4281_free(chip);
1379                 return -ENOMEM;
1380         }
1381         
1382         if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
1383                         KBUILD_MODNAME, chip)) {
1384                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1385                 snd_cs4281_free(chip);
1386                 return -ENOMEM;
1387         }
1388         chip->irq = pci->irq;
1389 
1390         tmp = snd_cs4281_chip_init(chip);
1391         if (tmp) {
1392                 snd_cs4281_free(chip);
1393                 return tmp;
1394         }
1395 
1396         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1397                 snd_cs4281_free(chip);
1398                 return err;
1399         }
1400 
1401         snd_cs4281_proc_init(chip);
1402 
1403         *rchip = chip;
1404         return 0;
1405 }
1406 
1407 static int snd_cs4281_chip_init(struct cs4281 *chip)
1408 {
1409         unsigned int tmp;
1410         unsigned long end_time;
1411         int retry_count = 2;
1412 
1413         /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1414         tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1415         if (tmp & BA0_EPPMC_FPDN)
1416                 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1417 
1418       __retry:
1419         tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1420         if (tmp != BA0_CFLR_DEFAULT) {
1421                 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1422                 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1423                 if (tmp != BA0_CFLR_DEFAULT) {
1424                         dev_err(chip->card->dev,
1425                                 "CFLR setup failed (0x%x)\n", tmp);
1426                         return -EIO;
1427                 }
1428         }
1429 
1430         /* Set the 'Configuration Write Protect' register
1431          * to 4281h.  Allows vendor-defined configuration
1432          * space between 0e4h and 0ffh to be written. */        
1433         snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1434         
1435         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1436                 dev_err(chip->card->dev,
1437                         "SERC1 AC'97 check failed (0x%x)\n", tmp);
1438                 return -EIO;
1439         }
1440         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1441                 dev_err(chip->card->dev,
1442                         "SERC2 AC'97 check failed (0x%x)\n", tmp);
1443                 return -EIO;
1444         }
1445 
1446         /* Sound System Power Management */
1447         snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1448                                            BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1449                                            BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1450 
1451         /* Serial Port Power Management */
1452         /* Blast the clock control register to zero so that the
1453          * PLL starts out in a known state, and blast the master serial
1454          * port control register to zero so that the serial ports also
1455          * start out in a known state. */
1456         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1457         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1458 
1459         /* Make ESYN go to zero to turn off
1460          * the Sync pulse on the AC97 link. */
1461         snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1462         udelay(50);
1463                 
1464         /*  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1465          *  spec) and then drive it high.  This is done for non AC97 modes since
1466          *  there might be logic external to the CS4281 that uses the ARST# line
1467          *  for a reset. */
1468         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1469         udelay(50);
1470         snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1471         msleep(50);
1472 
1473         if (chip->dual_codec)
1474                 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1475 
1476         /*
1477          *  Set the serial port timing configuration.
1478          */
1479         snd_cs4281_pokeBA0(chip, BA0_SERMC,
1480                            (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1481                            BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1482 
1483         /*
1484          *  Start the DLL Clock logic.
1485          */
1486         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1487         msleep(50);
1488         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1489 
1490         /*
1491          * Wait for the DLL ready signal from the clock logic.
1492          */
1493         end_time = jiffies + HZ;
1494         do {
1495                 /*
1496                  *  Read the AC97 status register to see if we've seen a CODEC
1497                  *  signal from the AC97 codec.
1498                  */
1499                 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1500                         goto __ok0;
1501                 schedule_timeout_uninterruptible(1);
1502         } while (time_after_eq(end_time, jiffies));
1503 
1504         dev_err(chip->card->dev, "DLLRDY not seen\n");
1505         return -EIO;
1506 
1507       __ok0:
1508 
1509         /*
1510          *  The first thing we do here is to enable sync generation.  As soon
1511          *  as we start receiving bit clock, we'll start producing the SYNC
1512          *  signal.
1513          */
1514         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1515 
1516         /*
1517          * Wait for the codec ready signal from the AC97 codec.
1518          */
1519         end_time = jiffies + HZ;
1520         do {
1521                 /*
1522                  *  Read the AC97 status register to see if we've seen a CODEC
1523                  *  signal from the AC97 codec.
1524                  */
1525                 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1526                         goto __ok1;
1527                 schedule_timeout_uninterruptible(1);
1528         } while (time_after_eq(end_time, jiffies));
1529 
1530         dev_err(chip->card->dev,
1531                 "never read codec ready from AC'97 (0x%x)\n",
1532                 snd_cs4281_peekBA0(chip, BA0_ACSTS));
1533         return -EIO;
1534 
1535       __ok1:
1536         if (chip->dual_codec) {
1537                 end_time = jiffies + HZ;
1538                 do {
1539                         if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1540                                 goto __codec2_ok;
1541                         schedule_timeout_uninterruptible(1);
1542                 } while (time_after_eq(end_time, jiffies));
1543                 dev_info(chip->card->dev,
1544                          "secondary codec doesn't respond. disable it...\n");
1545                 chip->dual_codec = 0;
1546         __codec2_ok: ;
1547         }
1548 
1549         /*
1550          *  Assert the valid frame signal so that we can start sending commands
1551          *  to the AC97 codec.
1552          */
1553 
1554         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1555 
1556         /*
1557          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
1558          *  the codec is pumping ADC data across the AC-link.
1559          */
1560 
1561         end_time = jiffies + HZ;
1562         do {
1563                 /*
1564                  *  Read the input slot valid register and see if input slots 3
1565                  *  4 are valid yet.
1566                  */
1567                 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1568                         goto __ok2;
1569                 schedule_timeout_uninterruptible(1);
1570         } while (time_after_eq(end_time, jiffies));
1571 
1572         if (--retry_count > 0)
1573                 goto __retry;
1574         dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
1575         return -EIO;
1576 
1577       __ok2:
1578 
1579         /*
1580          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
1581          *  commense the transfer of digital audio data to the AC97 codec.
1582          */
1583         snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1584 
1585         /*
1586          *  Initialize DMA structures
1587          */
1588         for (tmp = 0; tmp < 4; tmp++) {
1589                 struct cs4281_dma *dma = &chip->dma[tmp];
1590                 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1591                 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1592                 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1593                 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1594                 dma->regDMR = BA0_DMR0 + (tmp * 8);
1595                 dma->regDCR = BA0_DCR0 + (tmp * 8);
1596                 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1597                 dma->regFCR = BA0_FCR0 + (tmp * 4);
1598                 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1599                 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1600                 snd_cs4281_pokeBA0(chip, dma->regFCR,
1601                                    BA0_FCR_LS(31) |
1602                                    BA0_FCR_RS(31) |
1603                                    BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1604                                    BA0_FCR_OF(dma->fifo_offset));
1605         }
1606 
1607         chip->src_left_play_slot = 0;   /* AC'97 left PCM playback (3) */
1608         chip->src_right_play_slot = 1;  /* AC'97 right PCM playback (4) */
1609         chip->src_left_rec_slot = 10;   /* AC'97 left PCM record (3) */
1610         chip->src_right_rec_slot = 11;  /* AC'97 right PCM record (4) */
1611 
1612         /* Activate wave playback FIFO for FM playback */
1613         chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1614                               BA0_FCR_RS(1) |
1615                               BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1616                               BA0_FCR_OF(chip->dma[0].fifo_offset);
1617         snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1618         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1619                                             (chip->src_right_play_slot << 8) |
1620                                             (chip->src_left_rec_slot << 16) |
1621                                             (chip->src_right_rec_slot << 24));
1622 
1623         /* Initialize digital volume */
1624         snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1625         snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1626 
1627         /* Enable IRQs */
1628         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1629         /* Unmask interrupts */
1630         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1631                                         BA0_HISR_MIDI |
1632                                         BA0_HISR_DMAI |
1633                                         BA0_HISR_DMA(0) |
1634                                         BA0_HISR_DMA(1) |
1635                                         BA0_HISR_DMA(2) |
1636                                         BA0_HISR_DMA(3)));
1637         synchronize_irq(chip->irq);
1638 
1639         return 0;
1640 }
1641 
1642 /*
1643  *  MIDI section
1644  */
1645 
1646 static void snd_cs4281_midi_reset(struct cs4281 *chip)
1647 {
1648         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1649         udelay(100);
1650         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1651 }
1652 
1653 static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
1654 {
1655         struct cs4281 *chip = substream->rmidi->private_data;
1656 
1657         spin_lock_irq(&chip->reg_lock);
1658         chip->midcr |= BA0_MIDCR_RXE;
1659         chip->midi_input = substream;
1660         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1661                 snd_cs4281_midi_reset(chip);
1662         } else {
1663                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1664         }
1665         spin_unlock_irq(&chip->reg_lock);
1666         return 0;
1667 }
1668 
1669 static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
1670 {
1671         struct cs4281 *chip = substream->rmidi->private_data;
1672 
1673         spin_lock_irq(&chip->reg_lock);
1674         chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1675         chip->midi_input = NULL;
1676         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1677                 snd_cs4281_midi_reset(chip);
1678         } else {
1679                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1680         }
1681         chip->uartm &= ~CS4281_MODE_INPUT;
1682         spin_unlock_irq(&chip->reg_lock);
1683         return 0;
1684 }
1685 
1686 static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
1687 {
1688         struct cs4281 *chip = substream->rmidi->private_data;
1689 
1690         spin_lock_irq(&chip->reg_lock);
1691         chip->uartm |= CS4281_MODE_OUTPUT;
1692         chip->midcr |= BA0_MIDCR_TXE;
1693         chip->midi_output = substream;
1694         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1695                 snd_cs4281_midi_reset(chip);
1696         } else {
1697                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1698         }
1699         spin_unlock_irq(&chip->reg_lock);
1700         return 0;
1701 }
1702 
1703 static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
1704 {
1705         struct cs4281 *chip = substream->rmidi->private_data;
1706 
1707         spin_lock_irq(&chip->reg_lock);
1708         chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1709         chip->midi_output = NULL;
1710         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1711                 snd_cs4281_midi_reset(chip);
1712         } else {
1713                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1714         }
1715         chip->uartm &= ~CS4281_MODE_OUTPUT;
1716         spin_unlock_irq(&chip->reg_lock);
1717         return 0;
1718 }
1719 
1720 static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1721 {
1722         unsigned long flags;
1723         struct cs4281 *chip = substream->rmidi->private_data;
1724 
1725         spin_lock_irqsave(&chip->reg_lock, flags);
1726         if (up) {
1727                 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1728                         chip->midcr |= BA0_MIDCR_RIE;
1729                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1730                 }
1731         } else {
1732                 if (chip->midcr & BA0_MIDCR_RIE) {
1733                         chip->midcr &= ~BA0_MIDCR_RIE;
1734                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1735                 }
1736         }
1737         spin_unlock_irqrestore(&chip->reg_lock, flags);
1738 }
1739 
1740 static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1741 {
1742         unsigned long flags;
1743         struct cs4281 *chip = substream->rmidi->private_data;
1744         unsigned char byte;
1745 
1746         spin_lock_irqsave(&chip->reg_lock, flags);
1747         if (up) {
1748                 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1749                         chip->midcr |= BA0_MIDCR_TIE;
1750                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1751                         while ((chip->midcr & BA0_MIDCR_TIE) &&
1752                                (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1753                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1754                                         chip->midcr &= ~BA0_MIDCR_TIE;
1755                                 } else {
1756                                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1757                                 }
1758                         }
1759                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1760                 }
1761         } else {
1762                 if (chip->midcr & BA0_MIDCR_TIE) {
1763                         chip->midcr &= ~BA0_MIDCR_TIE;
1764                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1765                 }
1766         }
1767         spin_unlock_irqrestore(&chip->reg_lock, flags);
1768 }
1769 
1770 static struct snd_rawmidi_ops snd_cs4281_midi_output =
1771 {
1772         .open =         snd_cs4281_midi_output_open,
1773         .close =        snd_cs4281_midi_output_close,
1774         .trigger =      snd_cs4281_midi_output_trigger,
1775 };
1776 
1777 static struct snd_rawmidi_ops snd_cs4281_midi_input =
1778 {
1779         .open =         snd_cs4281_midi_input_open,
1780         .close =        snd_cs4281_midi_input_close,
1781         .trigger =      snd_cs4281_midi_input_trigger,
1782 };
1783 
1784 static int snd_cs4281_midi(struct cs4281 *chip, int device)
1785 {
1786         struct snd_rawmidi *rmidi;
1787         int err;
1788 
1789         if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1790                 return err;
1791         strcpy(rmidi->name, "CS4281");
1792         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1793         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1794         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1795         rmidi->private_data = chip;
1796         chip->rmidi = rmidi;
1797         return 0;
1798 }
1799 
1800 /*
1801  *  Interrupt handler
1802  */
1803 
1804 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
1805 {
1806         struct cs4281 *chip = dev_id;
1807         unsigned int status, dma, val;
1808         struct cs4281_dma *cdma;
1809 
1810         if (chip == NULL)
1811                 return IRQ_NONE;
1812         status = snd_cs4281_peekBA0(chip, BA0_HISR);
1813         if ((status & 0x7fffffff) == 0) {
1814                 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1815                 return IRQ_NONE;
1816         }
1817 
1818         if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1819                 for (dma = 0; dma < 4; dma++)
1820                         if (status & BA0_HISR_DMA(dma)) {
1821                                 cdma = &chip->dma[dma];
1822                                 spin_lock(&chip->reg_lock);
1823                                 /* ack DMA IRQ */
1824                                 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1825                                 /* workaround, sometimes CS4281 acknowledges */
1826                                 /* end or middle transfer position twice */
1827                                 cdma->frag++;
1828                                 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1829                                         cdma->frag--;
1830                                         chip->spurious_dhtc_irq++;
1831                                         spin_unlock(&chip->reg_lock);
1832                                         continue;
1833                                 }
1834                                 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1835                                         cdma->frag--;
1836                                         chip->spurious_dtc_irq++;
1837                                         spin_unlock(&chip->reg_lock);
1838                                         continue;
1839                                 }
1840                                 spin_unlock(&chip->reg_lock);
1841                                 snd_pcm_period_elapsed(cdma->substream);
1842                         }
1843         }
1844 
1845         if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1846                 unsigned char c;
1847                 
1848                 spin_lock(&chip->reg_lock);
1849                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1850                         c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1851                         if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1852                                 continue;
1853                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1854                 }
1855                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1856                         if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1857                                 break;
1858                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1859                                 chip->midcr &= ~BA0_MIDCR_TIE;
1860                                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1861                                 break;
1862                         }
1863                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1864                 }
1865                 spin_unlock(&chip->reg_lock);
1866         }
1867 
1868         /* EOI to the PCI part... reenables interrupts */
1869         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1870 
1871         return IRQ_HANDLED;
1872 }
1873 
1874 
1875 /*
1876  * OPL3 command
1877  */
1878 static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
1879                                     unsigned char val)
1880 {
1881         unsigned long flags;
1882         struct cs4281 *chip = opl3->private_data;
1883         void __iomem *port;
1884 
1885         if (cmd & OPL3_RIGHT)
1886                 port = chip->ba0 + BA0_B1AP; /* right port */
1887         else
1888                 port = chip->ba0 + BA0_B0AP; /* left port */
1889 
1890         spin_lock_irqsave(&opl3->reg_lock, flags);
1891 
1892         writel((unsigned int)cmd, port);
1893         udelay(10);
1894 
1895         writel((unsigned int)val, port + 4);
1896         udelay(30);
1897 
1898         spin_unlock_irqrestore(&opl3->reg_lock, flags);
1899 }
1900 
1901 static int snd_cs4281_probe(struct pci_dev *pci,
1902                             const struct pci_device_id *pci_id)
1903 {
1904         static int dev;
1905         struct snd_card *card;
1906         struct cs4281 *chip;
1907         struct snd_opl3 *opl3;
1908         int err;
1909 
1910         if (dev >= SNDRV_CARDS)
1911                 return -ENODEV;
1912         if (!enable[dev]) {
1913                 dev++;
1914                 return -ENOENT;
1915         }
1916 
1917         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1918                            0, &card);
1919         if (err < 0)
1920                 return err;
1921 
1922         if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1923                 snd_card_free(card);
1924                 return err;
1925         }
1926         card->private_data = chip;
1927 
1928         if ((err = snd_cs4281_mixer(chip)) < 0) {
1929                 snd_card_free(card);
1930                 return err;
1931         }
1932         if ((err = snd_cs4281_pcm(chip, 0)) < 0) {
1933                 snd_card_free(card);
1934                 return err;
1935         }
1936         if ((err = snd_cs4281_midi(chip, 0)) < 0) {
1937                 snd_card_free(card);
1938                 return err;
1939         }
1940         if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1941                 snd_card_free(card);
1942                 return err;
1943         }
1944         opl3->private_data = chip;
1945         opl3->command = snd_cs4281_opl3_command;
1946         snd_opl3_init(opl3);
1947         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1948                 snd_card_free(card);
1949                 return err;
1950         }
1951         snd_cs4281_create_gameport(chip);
1952         strcpy(card->driver, "CS4281");
1953         strcpy(card->shortname, "Cirrus Logic CS4281");
1954         sprintf(card->longname, "%s at 0x%lx, irq %d",
1955                 card->shortname,
1956                 chip->ba0_addr,
1957                 chip->irq);
1958 
1959         if ((err = snd_card_register(card)) < 0) {
1960                 snd_card_free(card);
1961                 return err;
1962         }
1963 
1964         pci_set_drvdata(pci, card);
1965         dev++;
1966         return 0;
1967 }
1968 
1969 static void snd_cs4281_remove(struct pci_dev *pci)
1970 {
1971         snd_card_free(pci_get_drvdata(pci));
1972 }
1973 
1974 /*
1975  * Power Management
1976  */
1977 #ifdef CONFIG_PM_SLEEP
1978 
1979 static int saved_regs[SUSPEND_REGISTERS] = {
1980         BA0_JSCTL,
1981         BA0_GPIOR,
1982         BA0_SSCR,
1983         BA0_MIDCR,
1984         BA0_SRCSA,
1985         BA0_PASR,
1986         BA0_CASR,
1987         BA0_DACSR,
1988         BA0_ADCSR,
1989         BA0_FMLVC,
1990         BA0_FMRVC,
1991         BA0_PPLVC,
1992         BA0_PPRVC,
1993 };
1994 
1995 #define CLKCR1_CKRA                             0x00010000L
1996 
1997 static int cs4281_suspend(struct device *dev)
1998 {
1999         struct snd_card *card = dev_get_drvdata(dev);
2000         struct cs4281 *chip = card->private_data;
2001         u32 ulCLK;
2002         unsigned int i;
2003 
2004         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2005         snd_pcm_suspend_all(chip->pcm);
2006 
2007         snd_ac97_suspend(chip->ac97);
2008         snd_ac97_suspend(chip->ac97_secondary);
2009 
2010         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2011         ulCLK |= CLKCR1_CKRA;
2012         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2013 
2014         /* Disable interrupts. */
2015         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2016 
2017         /* remember the status registers */
2018         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2019                 if (saved_regs[i])
2020                         chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2021 
2022         /* Turn off the serial ports. */
2023         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2024 
2025         /* Power off FM, Joystick, AC link, */
2026         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2027 
2028         /* DLL off. */
2029         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2030 
2031         /* AC link off. */
2032         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2033 
2034         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2035         ulCLK &= ~CLKCR1_CKRA;
2036         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2037         return 0;
2038 }
2039 
2040 static int cs4281_resume(struct device *dev)
2041 {
2042         struct snd_card *card = dev_get_drvdata(dev);
2043         struct cs4281 *chip = card->private_data;
2044         unsigned int i;
2045         u32 ulCLK;
2046 
2047         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2048         ulCLK |= CLKCR1_CKRA;
2049         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2050 
2051         snd_cs4281_chip_init(chip);
2052 
2053         /* restore the status registers */
2054         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2055                 if (saved_regs[i])
2056                         snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2057 
2058         snd_ac97_resume(chip->ac97);
2059         snd_ac97_resume(chip->ac97_secondary);
2060 
2061         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2062         ulCLK &= ~CLKCR1_CKRA;
2063         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2064 
2065         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2066         return 0;
2067 }
2068 
2069 static SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);
2070 #define CS4281_PM_OPS   &cs4281_pm
2071 #else
2072 #define CS4281_PM_OPS   NULL
2073 #endif /* CONFIG_PM_SLEEP */
2074 
2075 static struct pci_driver cs4281_driver = {
2076         .name = KBUILD_MODNAME,
2077         .id_table = snd_cs4281_ids,
2078         .probe = snd_cs4281_probe,
2079         .remove = snd_cs4281_remove,
2080         .driver = {
2081                 .pm = CS4281_PM_OPS,
2082         },
2083 };
2084         
2085 module_pci_driver(cs4281_driver);
2086 

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