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Linux/include/linux/pci.h

  1 /*
  2  *      pci.h
  3  *
  4  *      PCI defines and function prototypes
  5  *      Copyright 1994, Drew Eckhardt
  6  *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
  7  *
  8  *      For more information, please consult the following manuals (look at
  9  *      http://www.pcisig.com/ for how to get them):
 10  *
 11  *      PCI BIOS Specification
 12  *      PCI Local Bus Specification
 13  *      PCI to PCI Bridge Specification
 14  *      PCI System Design Guide
 15  */
 16 #ifndef LINUX_PCI_H
 17 #define LINUX_PCI_H
 18 
 19 
 20 #include <linux/mod_devicetable.h>
 21 
 22 #include <linux/types.h>
 23 #include <linux/init.h>
 24 #include <linux/ioport.h>
 25 #include <linux/list.h>
 26 #include <linux/compiler.h>
 27 #include <linux/errno.h>
 28 #include <linux/kobject.h>
 29 #include <linux/atomic.h>
 30 #include <linux/device.h>
 31 #include <linux/io.h>
 32 #include <uapi/linux/pci.h>
 33 
 34 #include <linux/pci_ids.h>
 35 
 36 /*
 37  * The PCI interface treats multi-function devices as independent
 38  * devices.  The slot/function address of each device is encoded
 39  * in a single byte as follows:
 40  *
 41  *      7:3 = slot
 42  *      2:0 = function
 43  *
 44  * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
 45  * In the interest of not exposing interfaces to user-space unnecessarily,
 46  * the following kernel-only defines are being added here.
 47  */
 48 #define PCI_DEVID(bus, devfn)  ((((u16)bus) << 8) | devfn)
 49 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
 50 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
 51 
 52 /* pci_slot represents a physical slot */
 53 struct pci_slot {
 54         struct pci_bus *bus;            /* The bus this slot is on */
 55         struct list_head list;          /* node in list of slots on this bus */
 56         struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
 57         unsigned char number;           /* PCI_SLOT(pci_dev->devfn) */
 58         struct kobject kobj;
 59 };
 60 
 61 static inline const char *pci_slot_name(const struct pci_slot *slot)
 62 {
 63         return kobject_name(&slot->kobj);
 64 }
 65 
 66 /* File state for mmap()s on /proc/bus/pci/X/Y */
 67 enum pci_mmap_state {
 68         pci_mmap_io,
 69         pci_mmap_mem
 70 };
 71 
 72 /* This defines the direction arg to the DMA mapping routines. */
 73 #define PCI_DMA_BIDIRECTIONAL   0
 74 #define PCI_DMA_TODEVICE        1
 75 #define PCI_DMA_FROMDEVICE      2
 76 #define PCI_DMA_NONE            3
 77 
 78 /*
 79  *  For PCI devices, the region numbers are assigned this way:
 80  */
 81 enum {
 82         /* #0-5: standard PCI resources */
 83         PCI_STD_RESOURCES,
 84         PCI_STD_RESOURCE_END = 5,
 85 
 86         /* #6: expansion ROM resource */
 87         PCI_ROM_RESOURCE,
 88 
 89         /* device specific resources */
 90 #ifdef CONFIG_PCI_IOV
 91         PCI_IOV_RESOURCES,
 92         PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
 93 #endif
 94 
 95         /* resources assigned to buses behind the bridge */
 96 #define PCI_BRIDGE_RESOURCE_NUM 4
 97 
 98         PCI_BRIDGE_RESOURCES,
 99         PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
100                                   PCI_BRIDGE_RESOURCE_NUM - 1,
101 
102         /* total resources associated with a PCI device */
103         PCI_NUM_RESOURCES,
104 
105         /* preserve this for compatibility */
106         DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
107 };
108 
109 typedef int __bitwise pci_power_t;
110 
111 #define PCI_D0          ((pci_power_t __force) 0)
112 #define PCI_D1          ((pci_power_t __force) 1)
113 #define PCI_D2          ((pci_power_t __force) 2)
114 #define PCI_D3hot       ((pci_power_t __force) 3)
115 #define PCI_D3cold      ((pci_power_t __force) 4)
116 #define PCI_UNKNOWN     ((pci_power_t __force) 5)
117 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
118 
119 /* Remember to update this when the list above changes! */
120 extern const char *pci_power_names[];
121 
122 static inline const char *pci_power_name(pci_power_t state)
123 {
124         return pci_power_names[1 + (int) state];
125 }
126 
127 #define PCI_PM_D2_DELAY         200
128 #define PCI_PM_D3_WAIT          10
129 #define PCI_PM_D3COLD_WAIT      100
130 #define PCI_PM_BUS_WAIT         50
131 
132 /** The pci_channel state describes connectivity between the CPU and
133  *  the pci device.  If some PCI bus between here and the pci device
134  *  has crashed or locked up, this info is reflected here.
135  */
136 typedef unsigned int __bitwise pci_channel_state_t;
137 
138 enum pci_channel_state {
139         /* I/O channel is in normal state */
140         pci_channel_io_normal = (__force pci_channel_state_t) 1,
141 
142         /* I/O to channel is blocked */
143         pci_channel_io_frozen = (__force pci_channel_state_t) 2,
144 
145         /* PCI card is dead */
146         pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
147 };
148 
149 typedef unsigned int __bitwise pcie_reset_state_t;
150 
151 enum pcie_reset_state {
152         /* Reset is NOT asserted (Use to deassert reset) */
153         pcie_deassert_reset = (__force pcie_reset_state_t) 1,
154 
155         /* Use #PERST to reset PCIe device */
156         pcie_warm_reset = (__force pcie_reset_state_t) 2,
157 
158         /* Use PCIe Hot Reset to reset device */
159         pcie_hot_reset = (__force pcie_reset_state_t) 3
160 };
161 
162 typedef unsigned short __bitwise pci_dev_flags_t;
163 enum pci_dev_flags {
164         /* INTX_DISABLE in PCI_COMMAND register disables MSI
165          * generation too.
166          */
167         PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
168         /* Device configuration is irrevocably lost if disabled into D3 */
169         PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
170         /* Provide indication device is assigned by a Virtual Machine Manager */
171         PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
172         /* Flag for quirk use to store if quirk-specific ACS is enabled */
173         PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
174         /* Flag to indicate the device uses dma_alias_devfn */
175         PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4),
176         /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
177         PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
178 };
179 
180 enum pci_irq_reroute_variant {
181         INTEL_IRQ_REROUTE_VARIANT = 1,
182         MAX_IRQ_REROUTE_VARIANTS = 3
183 };
184 
185 typedef unsigned short __bitwise pci_bus_flags_t;
186 enum pci_bus_flags {
187         PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
188         PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
189 };
190 
191 /* These values come from the PCI Express Spec */
192 enum pcie_link_width {
193         PCIE_LNK_WIDTH_RESRV    = 0x00,
194         PCIE_LNK_X1             = 0x01,
195         PCIE_LNK_X2             = 0x02,
196         PCIE_LNK_X4             = 0x04,
197         PCIE_LNK_X8             = 0x08,
198         PCIE_LNK_X12            = 0x0C,
199         PCIE_LNK_X16            = 0x10,
200         PCIE_LNK_X32            = 0x20,
201         PCIE_LNK_WIDTH_UNKNOWN  = 0xFF,
202 };
203 
204 /* Based on the PCI Hotplug Spec, but some values are made up by us */
205 enum pci_bus_speed {
206         PCI_SPEED_33MHz                 = 0x00,
207         PCI_SPEED_66MHz                 = 0x01,
208         PCI_SPEED_66MHz_PCIX            = 0x02,
209         PCI_SPEED_100MHz_PCIX           = 0x03,
210         PCI_SPEED_133MHz_PCIX           = 0x04,
211         PCI_SPEED_66MHz_PCIX_ECC        = 0x05,
212         PCI_SPEED_100MHz_PCIX_ECC       = 0x06,
213         PCI_SPEED_133MHz_PCIX_ECC       = 0x07,
214         PCI_SPEED_66MHz_PCIX_266        = 0x09,
215         PCI_SPEED_100MHz_PCIX_266       = 0x0a,
216         PCI_SPEED_133MHz_PCIX_266       = 0x0b,
217         AGP_UNKNOWN                     = 0x0c,
218         AGP_1X                          = 0x0d,
219         AGP_2X                          = 0x0e,
220         AGP_4X                          = 0x0f,
221         AGP_8X                          = 0x10,
222         PCI_SPEED_66MHz_PCIX_533        = 0x11,
223         PCI_SPEED_100MHz_PCIX_533       = 0x12,
224         PCI_SPEED_133MHz_PCIX_533       = 0x13,
225         PCIE_SPEED_2_5GT                = 0x14,
226         PCIE_SPEED_5_0GT                = 0x15,
227         PCIE_SPEED_8_0GT                = 0x16,
228         PCI_SPEED_UNKNOWN               = 0xff,
229 };
230 
231 struct pci_cap_saved_data {
232         u16 cap_nr;
233         bool cap_extended;
234         unsigned int size;
235         u32 data[0];
236 };
237 
238 struct pci_cap_saved_state {
239         struct hlist_node next;
240         struct pci_cap_saved_data cap;
241 };
242 
243 struct pcie_link_state;
244 struct pci_vpd;
245 struct pci_sriov;
246 struct pci_ats;
247 
248 /*
249  * The pci_dev structure is used to describe PCI devices.
250  */
251 struct pci_dev {
252         struct list_head bus_list;      /* node in per-bus list */
253         struct pci_bus  *bus;           /* bus this device is on */
254         struct pci_bus  *subordinate;   /* bus this device bridges to */
255 
256         void            *sysdata;       /* hook for sys-specific extension */
257         struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
258         struct pci_slot *slot;          /* Physical slot this device is in */
259 
260         unsigned int    devfn;          /* encoded device & function index */
261         unsigned short  vendor;
262         unsigned short  device;
263         unsigned short  subsystem_vendor;
264         unsigned short  subsystem_device;
265         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
266         u8              revision;       /* PCI revision, low byte of class word */
267         u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
268         u8              pcie_cap;       /* PCIe capability offset */
269         u8              msi_cap;        /* MSI capability offset */
270         u8              msix_cap;       /* MSI-X capability offset */
271         u8              pcie_mpss:3;    /* PCIe Max Payload Size Supported */
272         u8              rom_base_reg;   /* which config register controls the ROM */
273         u8              pin;            /* which interrupt pin this device uses */
274         u16             pcie_flags_reg; /* cached PCIe Capabilities Register */
275         u8              dma_alias_devfn;/* devfn of DMA alias, if any */
276 
277         struct pci_driver *driver;      /* which driver has allocated this device */
278         u64             dma_mask;       /* Mask of the bits of bus address this
279                                            device implements.  Normally this is
280                                            0xffffffff.  You only need to change
281                                            this if your device has broken DMA
282                                            or supports 64-bit transfers.  */
283 
284         struct device_dma_parameters dma_parms;
285 
286         pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
287                                            this is D0-D3, D0 being fully functional,
288                                            and D3 being off. */
289         u8              pm_cap;         /* PM capability offset */
290         unsigned int    pme_support:5;  /* Bitmask of states from which PME#
291                                            can be generated */
292         unsigned int    pme_interrupt:1;
293         unsigned int    pme_poll:1;     /* Poll device's PME status bit */
294         unsigned int    d1_support:1;   /* Low power state D1 is supported */
295         unsigned int    d2_support:1;   /* Low power state D2 is supported */
296         unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
297         unsigned int    no_d3cold:1;    /* D3cold is forbidden */
298         unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
299         unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
300                                                    decoding during bar sizing */
301         unsigned int    wakeup_prepared:1;
302         unsigned int    runtime_d3cold:1;       /* whether go through runtime
303                                                    D3cold, not set for devices
304                                                    powered on/off by the
305                                                    corresponding bridge */
306         unsigned int    d3_delay;       /* D3->D0 transition time in ms */
307         unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
308 
309 #ifdef CONFIG_PCIEASPM
310         struct pcie_link_state  *link_state;    /* ASPM link state */
311 #endif
312 
313         pci_channel_state_t error_state;        /* current connectivity state */
314         struct  device  dev;            /* Generic device interface */
315 
316         int             cfg_size;       /* Size of configuration space */
317 
318         /*
319          * Instead of touching interrupt line and base address registers
320          * directly, use the values stored here. They might be different!
321          */
322         unsigned int    irq;
323         struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
324 
325         bool match_driver;              /* Skip attaching driver */
326         /* These fields are used by common fixups */
327         unsigned int    transparent:1;  /* Subtractive decode PCI bridge */
328         unsigned int    multifunction:1;/* Part of multi-function device */
329         /* keep track of device state */
330         unsigned int    is_added:1;
331         unsigned int    is_busmaster:1; /* device is busmaster */
332         unsigned int    no_msi:1;       /* device may not use msi */
333         unsigned int    block_cfg_access:1;     /* config space access is blocked */
334         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
335         unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
336         unsigned int    msi_enabled:1;
337         unsigned int    msix_enabled:1;
338         unsigned int    ari_enabled:1;  /* ARI forwarding */
339         unsigned int    is_managed:1;
340         unsigned int    needs_freset:1; /* Dev requires fundamental reset */
341         unsigned int    state_saved:1;
342         unsigned int    is_physfn:1;
343         unsigned int    is_virtfn:1;
344         unsigned int    reset_fn:1;
345         unsigned int    is_hotplug_bridge:1;
346         unsigned int    __aer_firmware_first_valid:1;
347         unsigned int    __aer_firmware_first:1;
348         unsigned int    broken_intx_masking:1;
349         unsigned int    io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
350         pci_dev_flags_t dev_flags;
351         atomic_t        enable_cnt;     /* pci_enable_device has been called */
352 
353         u32             saved_config_space[16]; /* config space saved at suspend time */
354         struct hlist_head saved_cap_space;
355         struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
356         int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
357         struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
358         struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
359 #ifdef CONFIG_PCI_MSI
360         struct list_head msi_list;
361         const struct attribute_group **msi_irq_groups;
362 #endif
363         struct pci_vpd *vpd;
364 #ifdef CONFIG_PCI_ATS
365         union {
366                 struct pci_sriov *sriov;        /* SR-IOV capability related */
367                 struct pci_dev *physfn; /* the PF this VF is associated with */
368         };
369         struct pci_ats  *ats;   /* Address Translation Service */
370 #endif
371         phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
372         size_t romlen; /* Length of ROM if it's not from the BAR */
373         char *driver_override; /* Driver name to force a match */
374 };
375 
376 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
377 {
378 #ifdef CONFIG_PCI_IOV
379         if (dev->is_virtfn)
380                 dev = dev->physfn;
381 #endif
382         return dev;
383 }
384 
385 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
386 
387 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
388 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
389 
390 static inline int pci_channel_offline(struct pci_dev *pdev)
391 {
392         return (pdev->error_state != pci_channel_io_normal);
393 }
394 
395 struct pci_host_bridge_window {
396         struct list_head list;
397         struct resource *res;           /* host bridge aperture (CPU address) */
398         resource_size_t offset;         /* bus address + offset = CPU address */
399 };
400 
401 struct pci_host_bridge {
402         struct device dev;
403         struct pci_bus *bus;            /* root bus */
404         struct list_head windows;       /* pci_host_bridge_windows */
405         void (*release_fn)(struct pci_host_bridge *);
406         void *release_data;
407 };
408 
409 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
410 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
411                      void (*release_fn)(struct pci_host_bridge *),
412                      void *release_data);
413 
414 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
415 
416 /*
417  * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
418  * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
419  * buses below host bridges or subtractive decode bridges) go in the list.
420  * Use pci_bus_for_each_resource() to iterate through all the resources.
421  */
422 
423 /*
424  * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
425  * and there's no way to program the bridge with the details of the window.
426  * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
427  * decode bit set, because they are explicit and can be programmed with _SRS.
428  */
429 #define PCI_SUBTRACTIVE_DECODE  0x1
430 
431 struct pci_bus_resource {
432         struct list_head list;
433         struct resource *res;
434         unsigned int flags;
435 };
436 
437 #define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
438 
439 struct pci_bus {
440         struct list_head node;          /* node in list of buses */
441         struct pci_bus  *parent;        /* parent bus this bridge is on */
442         struct list_head children;      /* list of child buses */
443         struct list_head devices;       /* list of devices on this bus */
444         struct pci_dev  *self;          /* bridge device as seen by parent */
445         struct list_head slots;         /* list of slots on this bus */
446         struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
447         struct list_head resources;     /* address space routed to this bus */
448         struct resource busn_res;       /* bus numbers routed to this bus */
449 
450         struct pci_ops  *ops;           /* configuration access functions */
451         struct msi_chip *msi;           /* MSI controller */
452         void            *sysdata;       /* hook for sys-specific extension */
453         struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
454 
455         unsigned char   number;         /* bus number */
456         unsigned char   primary;        /* number of primary bridge */
457         unsigned char   max_bus_speed;  /* enum pci_bus_speed */
458         unsigned char   cur_bus_speed;  /* enum pci_bus_speed */
459 
460         char            name[48];
461 
462         unsigned short  bridge_ctl;     /* manage NO_ISA/FBB/et al behaviors */
463         pci_bus_flags_t bus_flags;      /* inherited by child buses */
464         struct device           *bridge;
465         struct device           dev;
466         struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
467         struct bin_attribute    *legacy_mem; /* legacy mem */
468         unsigned int            is_added:1;
469 };
470 
471 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
472 
473 /*
474  * Returns true if the PCI bus is root (behind host-PCI bridge),
475  * false otherwise
476  *
477  * Some code assumes that "bus->self == NULL" means that bus is a root bus.
478  * This is incorrect because "virtual" buses added for SR-IOV (via
479  * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
480  */
481 static inline bool pci_is_root_bus(struct pci_bus *pbus)
482 {
483         return !(pbus->parent);
484 }
485 
486 /**
487  * pci_is_bridge - check if the PCI device is a bridge
488  * @dev: PCI device
489  *
490  * Return true if the PCI device is bridge whether it has subordinate
491  * or not.
492  */
493 static inline bool pci_is_bridge(struct pci_dev *dev)
494 {
495         return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
496                 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
497 }
498 
499 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
500 {
501         dev = pci_physfn(dev);
502         if (pci_is_root_bus(dev->bus))
503                 return NULL;
504 
505         return dev->bus->self;
506 }
507 
508 #ifdef CONFIG_PCI_MSI
509 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
510 {
511         return pci_dev->msi_enabled || pci_dev->msix_enabled;
512 }
513 #else
514 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
515 #endif
516 
517 /*
518  * Error values that may be returned by PCI functions.
519  */
520 #define PCIBIOS_SUCCESSFUL              0x00
521 #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
522 #define PCIBIOS_BAD_VENDOR_ID           0x83
523 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
524 #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
525 #define PCIBIOS_SET_FAILED              0x88
526 #define PCIBIOS_BUFFER_TOO_SMALL        0x89
527 
528 /*
529  * Translate above to generic errno for passing back through non-PCI code.
530  */
531 static inline int pcibios_err_to_errno(int err)
532 {
533         if (err <= PCIBIOS_SUCCESSFUL)
534                 return err; /* Assume already errno */
535 
536         switch (err) {
537         case PCIBIOS_FUNC_NOT_SUPPORTED:
538                 return -ENOENT;
539         case PCIBIOS_BAD_VENDOR_ID:
540                 return -ENOTTY;
541         case PCIBIOS_DEVICE_NOT_FOUND:
542                 return -ENODEV;
543         case PCIBIOS_BAD_REGISTER_NUMBER:
544                 return -EFAULT;
545         case PCIBIOS_SET_FAILED:
546                 return -EIO;
547         case PCIBIOS_BUFFER_TOO_SMALL:
548                 return -ENOSPC;
549         }
550 
551         return -ERANGE;
552 }
553 
554 /* Low-level architecture-dependent routines */
555 
556 struct pci_ops {
557         int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
558         int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
559 };
560 
561 /*
562  * ACPI needs to be able to access PCI config space before we've done a
563  * PCI bus scan and created pci_bus structures.
564  */
565 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
566                  int reg, int len, u32 *val);
567 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
568                   int reg, int len, u32 val);
569 
570 struct pci_bus_region {
571         dma_addr_t start;
572         dma_addr_t end;
573 };
574 
575 struct pci_dynids {
576         spinlock_t lock;            /* protects list, index */
577         struct list_head list;      /* for IDs added at runtime */
578 };
579 
580 
581 /*
582  * PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
583  * a set of callbacks in struct pci_error_handlers, that device driver
584  * will be notified of PCI bus errors, and will be driven to recovery
585  * when an error occurs.
586  */
587 
588 typedef unsigned int __bitwise pci_ers_result_t;
589 
590 enum pci_ers_result {
591         /* no result/none/not supported in device driver */
592         PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
593 
594         /* Device driver can recover without slot reset */
595         PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
596 
597         /* Device driver wants slot to be reset. */
598         PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
599 
600         /* Device has completely failed, is unrecoverable */
601         PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
602 
603         /* Device driver is fully recovered and operational */
604         PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
605 
606         /* No AER capabilities registered for the driver */
607         PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
608 };
609 
610 /* PCI bus error event callbacks */
611 struct pci_error_handlers {
612         /* PCI bus error detected on this device */
613         pci_ers_result_t (*error_detected)(struct pci_dev *dev,
614                                            enum pci_channel_state error);
615 
616         /* MMIO has been re-enabled, but not DMA */
617         pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
618 
619         /* PCI Express link has been reset */
620         pci_ers_result_t (*link_reset)(struct pci_dev *dev);
621 
622         /* PCI slot has been reset */
623         pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
624 
625         /* PCI function reset prepare or completed */
626         void (*reset_notify)(struct pci_dev *dev, bool prepare);
627 
628         /* Device driver may resume normal operations */
629         void (*resume)(struct pci_dev *dev);
630 };
631 
632 
633 struct module;
634 struct pci_driver {
635         struct list_head node;
636         const char *name;
637         const struct pci_device_id *id_table;   /* must be non-NULL for probe to be called */
638         int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);   /* New device inserted */
639         void (*remove) (struct pci_dev *dev);   /* Device removed (NULL if not a hot-plug capable driver) */
640         int  (*suspend) (struct pci_dev *dev, pm_message_t state);      /* Device suspended */
641         int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);
642         int  (*resume_early) (struct pci_dev *dev);
643         int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
644         void (*shutdown) (struct pci_dev *dev);
645         int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
646         const struct pci_error_handlers *err_handler;
647         struct device_driver    driver;
648         struct pci_dynids dynids;
649 };
650 
651 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
652 
653 /**
654  * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
655  * @_table: device table name
656  *
657  * This macro is deprecated and should not be used in new code.
658  */
659 #define DEFINE_PCI_DEVICE_TABLE(_table) \
660         const struct pci_device_id _table[]
661 
662 /**
663  * PCI_DEVICE - macro used to describe a specific pci device
664  * @vend: the 16 bit PCI Vendor ID
665  * @dev: the 16 bit PCI Device ID
666  *
667  * This macro is used to create a struct pci_device_id that matches a
668  * specific device.  The subvendor and subdevice fields will be set to
669  * PCI_ANY_ID.
670  */
671 #define PCI_DEVICE(vend,dev) \
672         .vendor = (vend), .device = (dev), \
673         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
674 
675 /**
676  * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
677  * @vend: the 16 bit PCI Vendor ID
678  * @dev: the 16 bit PCI Device ID
679  * @subvend: the 16 bit PCI Subvendor ID
680  * @subdev: the 16 bit PCI Subdevice ID
681  *
682  * This macro is used to create a struct pci_device_id that matches a
683  * specific device with subsystem information.
684  */
685 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
686         .vendor = (vend), .device = (dev), \
687         .subvendor = (subvend), .subdevice = (subdev)
688 
689 /**
690  * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
691  * @dev_class: the class, subclass, prog-if triple for this device
692  * @dev_class_mask: the class mask for this device
693  *
694  * This macro is used to create a struct pci_device_id that matches a
695  * specific PCI class.  The vendor, device, subvendor, and subdevice
696  * fields will be set to PCI_ANY_ID.
697  */
698 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
699         .class = (dev_class), .class_mask = (dev_class_mask), \
700         .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
701         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
702 
703 /**
704  * PCI_VDEVICE - macro used to describe a specific pci device in short form
705  * @vend: the vendor name
706  * @dev: the 16 bit PCI Device ID
707  *
708  * This macro is used to create a struct pci_device_id that matches a
709  * specific PCI device.  The subvendor, and subdevice fields will be set
710  * to PCI_ANY_ID. The macro allows the next field to follow as the device
711  * private data.
712  */
713 
714 #define PCI_VDEVICE(vend, dev) \
715         .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
716         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
717 
718 /* these external functions are only available when PCI support is enabled */
719 #ifdef CONFIG_PCI
720 
721 void pcie_bus_configure_settings(struct pci_bus *bus);
722 
723 enum pcie_bus_config_types {
724         PCIE_BUS_TUNE_OFF,
725         PCIE_BUS_SAFE,
726         PCIE_BUS_PERFORMANCE,
727         PCIE_BUS_PEER2PEER,
728 };
729 
730 extern enum pcie_bus_config_types pcie_bus_config;
731 
732 extern struct bus_type pci_bus_type;
733 
734 /* Do NOT directly access these two variables, unless you are arch-specific PCI
735  * code, or PCI core code. */
736 extern struct list_head pci_root_buses; /* list of all known PCI buses */
737 /* Some device drivers need know if PCI is initiated */
738 int no_pci_devices(void);
739 
740 void pcibios_resource_survey_bus(struct pci_bus *bus);
741 void pcibios_add_bus(struct pci_bus *bus);
742 void pcibios_remove_bus(struct pci_bus *bus);
743 void pcibios_fixup_bus(struct pci_bus *);
744 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
745 /* Architecture-specific versions may override this (weak) */
746 char *pcibios_setup(char *str);
747 
748 /* Used only when drivers/pci/setup.c is used */
749 resource_size_t pcibios_align_resource(void *, const struct resource *,
750                                 resource_size_t,
751                                 resource_size_t);
752 void pcibios_update_irq(struct pci_dev *, int irq);
753 
754 /* Weak but can be overriden by arch */
755 void pci_fixup_cardbus(struct pci_bus *);
756 
757 /* Generic PCI functions used internally */
758 
759 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
760                              struct resource *res);
761 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
762                              struct pci_bus_region *region);
763 void pcibios_scan_specific_bus(int busn);
764 struct pci_bus *pci_find_bus(int domain, int busnr);
765 void pci_bus_add_devices(const struct pci_bus *bus);
766 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
767                                       struct pci_ops *ops, void *sysdata);
768 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
769 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
770                                     struct pci_ops *ops, void *sysdata,
771                                     struct list_head *resources);
772 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
773 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
774 void pci_bus_release_busn_res(struct pci_bus *b);
775 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
776                                              struct pci_ops *ops, void *sysdata,
777                                              struct list_head *resources);
778 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
779                                 int busnr);
780 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
781 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
782                                  const char *name,
783                                  struct hotplug_slot *hotplug);
784 void pci_destroy_slot(struct pci_slot *slot);
785 int pci_scan_slot(struct pci_bus *bus, int devfn);
786 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
787 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
788 unsigned int pci_scan_child_bus(struct pci_bus *bus);
789 void pci_bus_add_device(struct pci_dev *dev);
790 void pci_read_bridge_bases(struct pci_bus *child);
791 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
792                                           struct resource *res);
793 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
794 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
795 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
796 struct pci_dev *pci_dev_get(struct pci_dev *dev);
797 void pci_dev_put(struct pci_dev *dev);
798 void pci_remove_bus(struct pci_bus *b);
799 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
800 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
801 void pci_stop_root_bus(struct pci_bus *bus);
802 void pci_remove_root_bus(struct pci_bus *bus);
803 void pci_setup_cardbus(struct pci_bus *bus);
804 void pci_sort_breadthfirst(void);
805 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
806 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
807 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
808 
809 /* Generic PCI functions exported to card drivers */
810 
811 enum pci_lost_interrupt_reason {
812         PCI_LOST_IRQ_NO_INFORMATION = 0,
813         PCI_LOST_IRQ_DISABLE_MSI,
814         PCI_LOST_IRQ_DISABLE_MSIX,
815         PCI_LOST_IRQ_DISABLE_ACPI,
816 };
817 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
818 int pci_find_capability(struct pci_dev *dev, int cap);
819 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
820 int pci_find_ext_capability(struct pci_dev *dev, int cap);
821 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
822 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
823 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
824 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
825 
826 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
827                                 struct pci_dev *from);
828 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
829                                 unsigned int ss_vendor, unsigned int ss_device,
830                                 struct pci_dev *from);
831 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
832 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
833                                             unsigned int devfn);
834 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
835                                                    unsigned int devfn)
836 {
837         return pci_get_domain_bus_and_slot(0, bus, devfn);
838 }
839 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
840 int pci_dev_present(const struct pci_device_id *ids);
841 
842 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
843                              int where, u8 *val);
844 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
845                              int where, u16 *val);
846 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
847                               int where, u32 *val);
848 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
849                               int where, u8 val);
850 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
851                               int where, u16 val);
852 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
853                                int where, u32 val);
854 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
855 
856 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
857 {
858         return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
859 }
860 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
861 {
862         return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
863 }
864 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
865                                         u32 *val)
866 {
867         return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
868 }
869 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
870 {
871         return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
872 }
873 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
874 {
875         return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
876 }
877 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
878                                          u32 val)
879 {
880         return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
881 }
882 
883 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
884 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
885 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
886 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
887 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
888                                        u16 clear, u16 set);
889 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
890                                         u32 clear, u32 set);
891 
892 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
893                                            u16 set)
894 {
895         return pcie_capability_clear_and_set_word(dev, pos, 0, set);
896 }
897 
898 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
899                                             u32 set)
900 {
901         return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
902 }
903 
904 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
905                                              u16 clear)
906 {
907         return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
908 }
909 
910 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
911                                               u32 clear)
912 {
913         return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
914 }
915 
916 /* user-space driven config access */
917 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
918 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
919 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
920 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
921 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
922 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
923 
924 int __must_check pci_enable_device(struct pci_dev *dev);
925 int __must_check pci_enable_device_io(struct pci_dev *dev);
926 int __must_check pci_enable_device_mem(struct pci_dev *dev);
927 int __must_check pci_reenable_device(struct pci_dev *);
928 int __must_check pcim_enable_device(struct pci_dev *pdev);
929 void pcim_pin_device(struct pci_dev *pdev);
930 
931 static inline int pci_is_enabled(struct pci_dev *pdev)
932 {
933         return (atomic_read(&pdev->enable_cnt) > 0);
934 }
935 
936 static inline int pci_is_managed(struct pci_dev *pdev)
937 {
938         return pdev->is_managed;
939 }
940 
941 void pci_disable_device(struct pci_dev *dev);
942 
943 extern unsigned int pcibios_max_latency;
944 void pci_set_master(struct pci_dev *dev);
945 void pci_clear_master(struct pci_dev *dev);
946 
947 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
948 int pci_set_cacheline_size(struct pci_dev *dev);
949 #define HAVE_PCI_SET_MWI
950 int __must_check pci_set_mwi(struct pci_dev *dev);
951 int pci_try_set_mwi(struct pci_dev *dev);
952 void pci_clear_mwi(struct pci_dev *dev);
953 void pci_intx(struct pci_dev *dev, int enable);
954 bool pci_intx_mask_supported(struct pci_dev *dev);
955 bool pci_check_and_mask_intx(struct pci_dev *dev);
956 bool pci_check_and_unmask_intx(struct pci_dev *dev);
957 void pci_msi_off(struct pci_dev *dev);
958 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
959 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
960 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
961 int pci_wait_for_pending_transaction(struct pci_dev *dev);
962 int pcix_get_max_mmrbc(struct pci_dev *dev);
963 int pcix_get_mmrbc(struct pci_dev *dev);
964 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
965 int pcie_get_readrq(struct pci_dev *dev);
966 int pcie_set_readrq(struct pci_dev *dev, int rq);
967 int pcie_get_mps(struct pci_dev *dev);
968 int pcie_set_mps(struct pci_dev *dev, int mps);
969 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
970                           enum pcie_link_width *width);
971 int __pci_reset_function(struct pci_dev *dev);
972 int __pci_reset_function_locked(struct pci_dev *dev);
973 int pci_reset_function(struct pci_dev *dev);
974 int pci_try_reset_function(struct pci_dev *dev);
975 int pci_probe_reset_slot(struct pci_slot *slot);
976 int pci_reset_slot(struct pci_slot *slot);
977 int pci_try_reset_slot(struct pci_slot *slot);
978 int pci_probe_reset_bus(struct pci_bus *bus);
979 int pci_reset_bus(struct pci_bus *bus);
980 int pci_try_reset_bus(struct pci_bus *bus);
981 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
982 void pci_update_resource(struct pci_dev *dev, int resno);
983 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
984 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
985 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
986 bool pci_device_is_present(struct pci_dev *pdev);
987 
988 /* ROM control related routines */
989 int pci_enable_rom(struct pci_dev *pdev);
990 void pci_disable_rom(struct pci_dev *pdev);
991 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
992 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
993 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
994 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
995 
996 /* Power management related routines */
997 int pci_save_state(struct pci_dev *dev);
998 void pci_restore_state(struct pci_dev *dev);
999 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1000 int pci_load_and_free_saved_state(struct pci_dev *dev,
1001                                   struct pci_saved_state **state);
1002 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1003 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1004                                                    u16 cap);
1005 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1006 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1007                                 u16 cap, unsigned int size);
1008 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1009 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1010 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1011 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1012 void pci_pme_active(struct pci_dev *dev, bool enable);
1013 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1014                       bool runtime, bool enable);
1015 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1016 int pci_prepare_to_sleep(struct pci_dev *dev);
1017 int pci_back_from_sleep(struct pci_dev *dev);
1018 bool pci_dev_run_wake(struct pci_dev *dev);
1019 bool pci_check_pme_status(struct pci_dev *dev);
1020 void pci_pme_wakeup_bus(struct pci_bus *bus);
1021 
1022 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1023                                   bool enable)
1024 {
1025         return __pci_enable_wake(dev, state, false, enable);
1026 }
1027 
1028 /* PCI Virtual Channel */
1029 int pci_save_vc_state(struct pci_dev *dev);
1030 void pci_restore_vc_state(struct pci_dev *dev);
1031 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1032 
1033 /* For use by arch with custom probe code */
1034 void set_pcie_port_type(struct pci_dev *pdev);
1035 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1036 
1037 /* Functions for PCI Hotplug drivers to use */
1038 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1039 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1040 unsigned int pci_rescan_bus(struct pci_bus *bus);
1041 void pci_lock_rescan_remove(void);
1042 void pci_unlock_rescan_remove(void);
1043 
1044 /* Vital product data routines */
1045 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1046 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1047 
1048 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1049 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1050 void pci_bus_assign_resources(const struct pci_bus *bus);
1051 void pci_bus_size_bridges(struct pci_bus *bus);
1052 int pci_claim_resource(struct pci_dev *, int);
1053 void pci_assign_unassigned_resources(void);
1054 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1055 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1056 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1057 void pdev_enable_device(struct pci_dev *);
1058 int pci_enable_resources(struct pci_dev *, int mask);
1059 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1060                     int (*)(const struct pci_dev *, u8, u8));
1061 #define HAVE_PCI_REQ_REGIONS    2
1062 int __must_check pci_request_regions(struct pci_dev *, const char *);
1063 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1064 void pci_release_regions(struct pci_dev *);
1065 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1066 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1067 void pci_release_region(struct pci_dev *, int);
1068 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1069 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1070 void pci_release_selected_regions(struct pci_dev *, int);
1071 
1072 /* drivers/pci/bus.c */
1073 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1074 void pci_bus_put(struct pci_bus *bus);
1075 void pci_add_resource(struct list_head *resources, struct resource *res);
1076 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1077                              resource_size_t offset);
1078 void pci_free_resource_list(struct list_head *resources);
1079 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1080 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1081 void pci_bus_remove_resources(struct pci_bus *bus);
1082 
1083 #define pci_bus_for_each_resource(bus, res, i)                          \
1084         for (i = 0;                                                     \
1085             (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1086              i++)
1087 
1088 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1089                         struct resource *res, resource_size_t size,
1090                         resource_size_t align, resource_size_t min,
1091                         unsigned long type_mask,
1092                         resource_size_t (*alignf)(void *,
1093                                                   const struct resource *,
1094                                                   resource_size_t,
1095                                                   resource_size_t),
1096                         void *alignf_data);
1097 
1098 static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1099 {
1100         struct pci_bus_region region;
1101 
1102         pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1103         return region.start;
1104 }
1105 
1106 /* Proper probing supporting hot-pluggable devices */
1107 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1108                                        const char *mod_name);
1109 
1110 /*
1111  * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1112  */
1113 #define pci_register_driver(driver)             \
1114         __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1115 
1116 void pci_unregister_driver(struct pci_driver *dev);
1117 
1118 /**
1119  * module_pci_driver() - Helper macro for registering a PCI driver
1120  * @__pci_driver: pci_driver struct
1121  *
1122  * Helper macro for PCI drivers which do not do anything special in module
1123  * init/exit. This eliminates a lot of boilerplate. Each module may only
1124  * use this macro once, and calling it replaces module_init() and module_exit()
1125  */
1126 #define module_pci_driver(__pci_driver) \
1127         module_driver(__pci_driver, pci_register_driver, \
1128                        pci_unregister_driver)
1129 
1130 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1131 int pci_add_dynid(struct pci_driver *drv,
1132                   unsigned int vendor, unsigned int device,
1133                   unsigned int subvendor, unsigned int subdevice,
1134                   unsigned int class, unsigned int class_mask,
1135                   unsigned long driver_data);
1136 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1137                                          struct pci_dev *dev);
1138 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1139                     int pass);
1140 
1141 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1142                   void *userdata);
1143 int pci_cfg_space_size(struct pci_dev *dev);
1144 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1145 void pci_setup_bridge(struct pci_bus *bus);
1146 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1147                                          unsigned long type);
1148 
1149 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1150 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1151 
1152 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1153                       unsigned int command_bits, u32 flags);
1154 /* kmem_cache style wrapper around pci_alloc_consistent() */
1155 
1156 #include <linux/pci-dma.h>
1157 #include <linux/dmapool.h>
1158 
1159 #define pci_pool dma_pool
1160 #define pci_pool_create(name, pdev, size, align, allocation) \
1161                 dma_pool_create(name, &pdev->dev, size, align, allocation)
1162 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1163 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1164 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1165 
1166 enum pci_dma_burst_strategy {
1167         PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1168                                    strategy_parameter is N/A */
1169         PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1170                                    byte boundaries */
1171         PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1172                                    strategy_parameter byte boundaries */
1173 };
1174 
1175 struct msix_entry {
1176         u32     vector; /* kernel uses to write allocated vector */
1177         u16     entry;  /* driver uses to specify entry, OS writes */
1178 };
1179 
1180 
1181 #ifdef CONFIG_PCI_MSI
1182 int pci_msi_vec_count(struct pci_dev *dev);
1183 void pci_msi_shutdown(struct pci_dev *dev);
1184 void pci_disable_msi(struct pci_dev *dev);
1185 int pci_msix_vec_count(struct pci_dev *dev);
1186 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1187 void pci_msix_shutdown(struct pci_dev *dev);
1188 void pci_disable_msix(struct pci_dev *dev);
1189 void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1190 void pci_restore_msi_state(struct pci_dev *dev);
1191 int pci_msi_enabled(void);
1192 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1193 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1194 {
1195         int rc = pci_enable_msi_range(dev, nvec, nvec);
1196         if (rc < 0)
1197                 return rc;
1198         return 0;
1199 }
1200 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1201                           int minvec, int maxvec);
1202 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1203                                         struct msix_entry *entries, int nvec)
1204 {
1205         int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1206         if (rc < 0)
1207                 return rc;
1208         return 0;
1209 }
1210 #else
1211 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1212 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1213 static inline void pci_disable_msi(struct pci_dev *dev) { }
1214 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1215 static inline int pci_enable_msix(struct pci_dev *dev,
1216                                   struct msix_entry *entries, int nvec)
1217 { return -ENOSYS; }
1218 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1219 static inline void pci_disable_msix(struct pci_dev *dev) { }
1220 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) { }
1221 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1222 static inline int pci_msi_enabled(void) { return 0; }
1223 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1224                                        int maxvec)
1225 { return -ENOSYS; }
1226 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1227 { return -ENOSYS; }
1228 static inline int pci_enable_msix_range(struct pci_dev *dev,
1229                       struct msix_entry *entries, int minvec, int maxvec)
1230 { return -ENOSYS; }
1231 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1232                       struct msix_entry *entries, int nvec)
1233 { return -ENOSYS; }
1234 #endif
1235 
1236 #ifdef CONFIG_PCIEPORTBUS
1237 extern bool pcie_ports_disabled;
1238 extern bool pcie_ports_auto;
1239 #else
1240 #define pcie_ports_disabled     true
1241 #define pcie_ports_auto         false
1242 #endif
1243 
1244 #ifdef CONFIG_PCIEASPM
1245 bool pcie_aspm_support_enabled(void);
1246 #else
1247 static inline bool pcie_aspm_support_enabled(void) { return false; }
1248 #endif
1249 
1250 #ifdef CONFIG_PCIEAER
1251 void pci_no_aer(void);
1252 bool pci_aer_available(void);
1253 #else
1254 static inline void pci_no_aer(void) { }
1255 static inline bool pci_aer_available(void) { return false; }
1256 #endif
1257 
1258 #ifdef CONFIG_PCIE_ECRC
1259 void pcie_set_ecrc_checking(struct pci_dev *dev);
1260 void pcie_ecrc_get_policy(char *str);
1261 #else
1262 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1263 static inline void pcie_ecrc_get_policy(char *str) { }
1264 #endif
1265 
1266 #define pci_enable_msi(pdev)    pci_enable_msi_exact(pdev, 1)
1267 
1268 #ifdef CONFIG_HT_IRQ
1269 /* The functions a driver should call */
1270 int  ht_create_irq(struct pci_dev *dev, int idx);
1271 void ht_destroy_irq(unsigned int irq);
1272 #endif /* CONFIG_HT_IRQ */
1273 
1274 void pci_cfg_access_lock(struct pci_dev *dev);
1275 bool pci_cfg_access_trylock(struct pci_dev *dev);
1276 void pci_cfg_access_unlock(struct pci_dev *dev);
1277 
1278 /*
1279  * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
1280  * a PCI domain is defined to be a set of PCI buses which share
1281  * configuration space.
1282  */
1283 #ifdef CONFIG_PCI_DOMAINS
1284 extern int pci_domains_supported;
1285 #else
1286 enum { pci_domains_supported = 0 };
1287 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1288 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1289 #endif /* CONFIG_PCI_DOMAINS */
1290 
1291 /* some architectures require additional setup to direct VGA traffic */
1292 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1293                       unsigned int command_bits, u32 flags);
1294 void pci_register_set_vga_state(arch_set_vga_state_t func);
1295 
1296 #else /* CONFIG_PCI is not enabled */
1297 
1298 /*
1299  *  If the system does not have PCI, clearly these return errors.  Define
1300  *  these as simple inline functions to avoid hair in drivers.
1301  */
1302 
1303 #define _PCI_NOP(o, s, t) \
1304         static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1305                                                 int where, t val) \
1306                 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1307 
1308 #define _PCI_NOP_ALL(o, x)      _PCI_NOP(o, byte, u8 x) \
1309                                 _PCI_NOP(o, word, u16 x) \
1310                                 _PCI_NOP(o, dword, u32 x)
1311 _PCI_NOP_ALL(read, *)
1312 _PCI_NOP_ALL(write,)
1313 
1314 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1315                                              unsigned int device,
1316                                              struct pci_dev *from)
1317 { return NULL; }
1318 
1319 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1320                                              unsigned int device,
1321                                              unsigned int ss_vendor,
1322                                              unsigned int ss_device,
1323                                              struct pci_dev *from)
1324 { return NULL; }
1325 
1326 static inline struct pci_dev *pci_get_class(unsigned int class,
1327                                             struct pci_dev *from)
1328 { return NULL; }
1329 
1330 #define pci_dev_present(ids)    (0)
1331 #define no_pci_devices()        (1)
1332 #define pci_dev_put(dev)        do { } while (0)
1333 
1334 static inline void pci_set_master(struct pci_dev *dev) { }
1335 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1336 static inline void pci_disable_device(struct pci_dev *dev) { }
1337 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1338 { return -EIO; }
1339 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1340 { return -EIO; }
1341 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1342                                         unsigned int size)
1343 { return -EIO; }
1344 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1345                                         unsigned long mask)
1346 { return -EIO; }
1347 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1348 { return -EBUSY; }
1349 static inline int __pci_register_driver(struct pci_driver *drv,
1350                                         struct module *owner)
1351 { return 0; }
1352 static inline int pci_register_driver(struct pci_driver *drv)
1353 { return 0; }
1354 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1355 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1356 { return 0; }
1357 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1358                                            int cap)
1359 { return 0; }
1360 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1361 { return 0; }
1362 
1363 /* Power management related routines */
1364 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1365 static inline void pci_restore_state(struct pci_dev *dev) { }
1366 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1367 { return 0; }
1368 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1369 { return 0; }
1370 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1371                                            pm_message_t state)
1372 { return PCI_D0; }
1373 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1374                                   int enable)
1375 { return 0; }
1376 
1377 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1378 { return -EIO; }
1379 static inline void pci_release_regions(struct pci_dev *dev) { }
1380 
1381 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1382 
1383 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1384 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1385 { return 0; }
1386 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1387 
1388 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1389 { return NULL; }
1390 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1391                                                 unsigned int devfn)
1392 { return NULL; }
1393 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1394                                                 unsigned int devfn)
1395 { return NULL; }
1396 
1397 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1398 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1399 
1400 #define dev_is_pci(d) (false)
1401 #define dev_is_pf(d) (false)
1402 #define dev_num_vf(d) (0)
1403 #endif /* CONFIG_PCI */
1404 
1405 /* Include architecture-dependent settings and functions */
1406 
1407 #include <asm/pci.h>
1408 
1409 /* these helpers provide future and backwards compatibility
1410  * for accessing popular PCI BAR info */
1411 #define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
1412 #define pci_resource_end(dev, bar)      ((dev)->resource[(bar)].end)
1413 #define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)
1414 #define pci_resource_len(dev,bar) \
1415         ((pci_resource_start((dev), (bar)) == 0 &&      \
1416           pci_resource_end((dev), (bar)) ==             \
1417           pci_resource_start((dev), (bar))) ? 0 :       \
1418                                                         \
1419          (pci_resource_end((dev), (bar)) -              \
1420           pci_resource_start((dev), (bar)) + 1))
1421 
1422 /* Similar to the helpers above, these manipulate per-pci_dev
1423  * driver-specific data.  They are really just a wrapper around
1424  * the generic device structure functions of these calls.
1425  */
1426 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1427 {
1428         return dev_get_drvdata(&pdev->dev);
1429 }
1430 
1431 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1432 {
1433         dev_set_drvdata(&pdev->dev, data);
1434 }
1435 
1436 /* If you want to know what to call your pci_dev, ask this function.
1437  * Again, it's a wrapper around the generic device.
1438  */
1439 static inline const char *pci_name(const struct pci_dev *pdev)
1440 {
1441         return dev_name(&pdev->dev);
1442 }
1443 
1444 
1445 /* Some archs don't want to expose struct resource to userland as-is
1446  * in sysfs and /proc
1447  */
1448 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1449 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1450                 const struct resource *rsrc, resource_size_t *start,
1451                 resource_size_t *end)
1452 {
1453         *start = rsrc->start;
1454         *end = rsrc->end;
1455 }
1456 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1457 
1458 
1459 /*
1460  *  The world is not perfect and supplies us with broken PCI devices.
1461  *  For at least a part of these bugs we need a work-around, so both
1462  *  generic (drivers/pci/quirks.c) and per-architecture code can define
1463  *  fixup hooks to be called for particular buggy devices.
1464  */
1465 
1466 struct pci_fixup {
1467         u16 vendor;             /* You can use PCI_ANY_ID here of course */
1468         u16 device;             /* You can use PCI_ANY_ID here of course */
1469         u32 class;              /* You can use PCI_ANY_ID here too */
1470         unsigned int class_shift;       /* should be 0, 8, 16 */
1471         void (*hook)(struct pci_dev *dev);
1472 };
1473 
1474 enum pci_fixup_pass {
1475         pci_fixup_early,        /* Before probing BARs */
1476         pci_fixup_header,       /* After reading configuration header */
1477         pci_fixup_final,        /* Final phase of device fixups */
1478         pci_fixup_enable,       /* pci_enable_device() time */
1479         pci_fixup_resume,       /* pci_device_resume() */
1480         pci_fixup_suspend,      /* pci_device_suspend */
1481         pci_fixup_resume_early, /* pci_device_resume_early() */
1482 };
1483 
1484 /* Anonymous variables would be nice... */
1485 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1486                                   class_shift, hook)                    \
1487         static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used       \
1488         __attribute__((__section__(#section), aligned((sizeof(void *)))))    \
1489                 = { vendor, device, class, class_shift, hook };
1490 
1491 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,            \
1492                                          class_shift, hook)             \
1493         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1494                 hook, vendor, device, class, class_shift, hook)
1495 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,           \
1496                                          class_shift, hook)             \
1497         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1498                 hook, vendor, device, class, class_shift, hook)
1499 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,            \
1500                                          class_shift, hook)             \
1501         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1502                 hook, vendor, device, class, class_shift, hook)
1503 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,           \
1504                                          class_shift, hook)             \
1505         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1506                 hook, vendor, device, class, class_shift, hook)
1507 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,           \
1508                                          class_shift, hook)             \
1509         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1510                 resume##hook, vendor, device, class,    \
1511                 class_shift, hook)
1512 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,     \
1513                                          class_shift, hook)             \
1514         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1515                 resume_early##hook, vendor, device,     \
1516                 class, class_shift, hook)
1517 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,          \
1518                                          class_shift, hook)             \
1519         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1520                 suspend##hook, vendor, device, class,   \
1521                 class_shift, hook)
1522 
1523 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
1524         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1525                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1526 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)                  \
1527         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1528                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1529 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)                   \
1530         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1531                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1532 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)                  \
1533         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1534                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1535 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
1536         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1537                 resume##hook, vendor, device,           \
1538                 PCI_ANY_ID, 0, hook)
1539 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
1540         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1541                 resume_early##hook, vendor, device,     \
1542                 PCI_ANY_ID, 0, hook)
1543 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
1544         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1545                 suspend##hook, vendor, device,          \
1546                 PCI_ANY_ID, 0, hook)
1547 
1548 #ifdef CONFIG_PCI_QUIRKS
1549 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1550 struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1551 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1552 void pci_dev_specific_enable_acs(struct pci_dev *dev);
1553 #else
1554 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1555                                     struct pci_dev *dev) { }
1556 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1557 {
1558         return pci_dev_get(dev);
1559 }
1560 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1561                                                u16 acs_flags)
1562 {
1563         return -ENOTTY;
1564 }
1565 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { }
1566 #endif
1567 
1568 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1569 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1570 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1571 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1572 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1573                                    const char *name);
1574 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1575 
1576 extern int pci_pci_problems;
1577 #define PCIPCI_FAIL             1       /* No PCI PCI DMA */
1578 #define PCIPCI_TRITON           2
1579 #define PCIPCI_NATOMA           4
1580 #define PCIPCI_VIAETBF          8
1581 #define PCIPCI_VSFX             16
1582 #define PCIPCI_ALIMAGIK         32      /* Need low latency setting */
1583 #define PCIAGP_FAIL             64      /* No PCI to AGP DMA */
1584 
1585 extern unsigned long pci_cardbus_io_size;
1586 extern unsigned long pci_cardbus_mem_size;
1587 extern u8 pci_dfl_cache_line_size;
1588 extern u8 pci_cache_line_size;
1589 
1590 extern unsigned long pci_hotplug_io_size;
1591 extern unsigned long pci_hotplug_mem_size;
1592 
1593 /* Architecture-specific versions may override these (weak) */
1594 void pcibios_disable_device(struct pci_dev *dev);
1595 void pcibios_set_master(struct pci_dev *dev);
1596 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1597                                  enum pcie_reset_state state);
1598 int pcibios_add_device(struct pci_dev *dev);
1599 void pcibios_release_device(struct pci_dev *dev);
1600 void pcibios_penalize_isa_irq(int irq, int active);
1601 
1602 #ifdef CONFIG_HIBERNATE_CALLBACKS
1603 extern struct dev_pm_ops pcibios_pm_ops;
1604 #endif
1605 
1606 #ifdef CONFIG_PCI_MMCONFIG
1607 void __init pci_mmcfg_early_init(void);
1608 void __init pci_mmcfg_late_init(void);
1609 #else
1610 static inline void pci_mmcfg_early_init(void) { }
1611 static inline void pci_mmcfg_late_init(void) { }
1612 #endif
1613 
1614 int pci_ext_cfg_avail(void);
1615 
1616 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1617 
1618 #ifdef CONFIG_PCI_IOV
1619 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1620 void pci_disable_sriov(struct pci_dev *dev);
1621 int pci_num_vf(struct pci_dev *dev);
1622 int pci_vfs_assigned(struct pci_dev *dev);
1623 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1624 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1625 #else
1626 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1627 { return -ENODEV; }
1628 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1629 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1630 static inline int pci_vfs_assigned(struct pci_dev *dev)
1631 { return 0; }
1632 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1633 { return 0; }
1634 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1635 { return 0; }
1636 #endif
1637 
1638 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1639 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1640 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1641 #endif
1642 
1643 /**
1644  * pci_pcie_cap - get the saved PCIe capability offset
1645  * @dev: PCI device
1646  *
1647  * PCIe capability offset is calculated at PCI device initialization
1648  * time and saved in the data structure. This function returns saved
1649  * PCIe capability offset. Using this instead of pci_find_capability()
1650  * reduces unnecessary search in the PCI configuration space. If you
1651  * need to calculate PCIe capability offset from raw device for some
1652  * reasons, please use pci_find_capability() instead.
1653  */
1654 static inline int pci_pcie_cap(struct pci_dev *dev)
1655 {
1656         return dev->pcie_cap;
1657 }
1658 
1659 /**
1660  * pci_is_pcie - check if the PCI device is PCI Express capable
1661  * @dev: PCI device
1662  *
1663  * Returns: true if the PCI device is PCI Express capable, false otherwise.
1664  */
1665 static inline bool pci_is_pcie(struct pci_dev *dev)
1666 {
1667         return pci_pcie_cap(dev);
1668 }
1669 
1670 /**
1671  * pcie_caps_reg - get the PCIe Capabilities Register
1672  * @dev: PCI device
1673  */
1674 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1675 {
1676         return dev->pcie_flags_reg;
1677 }
1678 
1679 /**
1680  * pci_pcie_type - get the PCIe device/port type
1681  * @dev: PCI device
1682  */
1683 static inline int pci_pcie_type(const struct pci_dev *dev)
1684 {
1685         return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1686 }
1687 
1688 void pci_request_acs(void);
1689 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1690 bool pci_acs_path_enabled(struct pci_dev *start,
1691                           struct pci_dev *end, u16 acs_flags);
1692 
1693 #define PCI_VPD_LRDT                    0x80    /* Large Resource Data Type */
1694 #define PCI_VPD_LRDT_ID(x)              (x | PCI_VPD_LRDT)
1695 
1696 /* Large Resource Data Type Tag Item Names */
1697 #define PCI_VPD_LTIN_ID_STRING          0x02    /* Identifier String */
1698 #define PCI_VPD_LTIN_RO_DATA            0x10    /* Read-Only Data */
1699 #define PCI_VPD_LTIN_RW_DATA            0x11    /* Read-Write Data */
1700 
1701 #define PCI_VPD_LRDT_ID_STRING          PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1702 #define PCI_VPD_LRDT_RO_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1703 #define PCI_VPD_LRDT_RW_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1704 
1705 /* Small Resource Data Type Tag Item Names */
1706 #define PCI_VPD_STIN_END                0x78    /* End */
1707 
1708 #define PCI_VPD_SRDT_END                PCI_VPD_STIN_END
1709 
1710 #define PCI_VPD_SRDT_TIN_MASK           0x78
1711 #define PCI_VPD_SRDT_LEN_MASK           0x07
1712 
1713 #define PCI_VPD_LRDT_TAG_SIZE           3
1714 #define PCI_VPD_SRDT_TAG_SIZE           1
1715 
1716 #define PCI_VPD_INFO_FLD_HDR_SIZE       3
1717 
1718 #define PCI_VPD_RO_KEYWORD_PARTNO       "PN"
1719 #define PCI_VPD_RO_KEYWORD_MFR_ID       "MN"
1720 #define PCI_VPD_RO_KEYWORD_VENDOR0      "V0"
1721 #define PCI_VPD_RO_KEYWORD_CHKSUM       "RV"
1722 
1723 /**
1724  * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1725  * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1726  *
1727  * Returns the extracted Large Resource Data Type length.
1728  */
1729 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1730 {
1731         return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1732 }
1733 
1734 /**
1735  * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1736  * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1737  *
1738  * Returns the extracted Small Resource Data Type length.
1739  */
1740 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1741 {
1742         return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1743 }
1744 
1745 /**
1746  * pci_vpd_info_field_size - Extracts the information field length
1747  * @lrdt: Pointer to the beginning of an information field header
1748  *
1749  * Returns the extracted information field length.
1750  */
1751 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1752 {
1753         return info_field[2];
1754 }
1755 
1756 /**
1757  * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1758  * @buf: Pointer to buffered vpd data
1759  * @off: The offset into the buffer at which to begin the search
1760  * @len: The length of the vpd buffer
1761  * @rdt: The Resource Data Type to search for
1762  *
1763  * Returns the index where the Resource Data Type was found or
1764  * -ENOENT otherwise.
1765  */
1766 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1767 
1768 /**
1769  * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1770  * @buf: Pointer to buffered vpd data
1771  * @off: The offset into the buffer at which to begin the search
1772  * @len: The length of the buffer area, relative to off, in which to search
1773  * @kw: The keyword to search for
1774  *
1775  * Returns the index where the information field keyword was found or
1776  * -ENOENT otherwise.
1777  */
1778 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1779                               unsigned int len, const char *kw);
1780 
1781 /* PCI <-> OF binding helpers */
1782 #ifdef CONFIG_OF
1783 struct device_node;
1784 void pci_set_of_node(struct pci_dev *dev);
1785 void pci_release_of_node(struct pci_dev *dev);
1786 void pci_set_bus_of_node(struct pci_bus *bus);
1787 void pci_release_bus_of_node(struct pci_bus *bus);
1788 
1789 /* Arch may override this (weak) */
1790 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1791 
1792 static inline struct device_node *
1793 pci_device_to_OF_node(const struct pci_dev *pdev)
1794 {
1795         return pdev ? pdev->dev.of_node : NULL;
1796 }
1797 
1798 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1799 {
1800         return bus ? bus->dev.of_node : NULL;
1801 }
1802 
1803 #else /* CONFIG_OF */
1804 static inline void pci_set_of_node(struct pci_dev *dev) { }
1805 static inline void pci_release_of_node(struct pci_dev *dev) { }
1806 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1807 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1808 #endif  /* CONFIG_OF */
1809 
1810 #ifdef CONFIG_EEH
1811 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1812 {
1813         return pdev->dev.archdata.edev;
1814 }
1815 #endif
1816 
1817 int pci_for_each_dma_alias(struct pci_dev *pdev,
1818                            int (*fn)(struct pci_dev *pdev,
1819                                      u16 alias, void *data), void *data);
1820 
1821 /**
1822  * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1823  * @pdev: the PCI device
1824  *
1825  * if the device is PCIE, return NULL
1826  * if the device isn't connected to a PCIe bridge (that is its parent is a
1827  * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1828  * parent
1829  */
1830 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1831 
1832 #endif /* LINUX_PCI_H */
1833 

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