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Linux/include/linux/pci.h

  1 /*
  2  *      pci.h
  3  *
  4  *      PCI defines and function prototypes
  5  *      Copyright 1994, Drew Eckhardt
  6  *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
  7  *
  8  *      For more information, please consult the following manuals (look at
  9  *      http://www.pcisig.com/ for how to get them):
 10  *
 11  *      PCI BIOS Specification
 12  *      PCI Local Bus Specification
 13  *      PCI to PCI Bridge Specification
 14  *      PCI System Design Guide
 15  */
 16 #ifndef LINUX_PCI_H
 17 #define LINUX_PCI_H
 18 
 19 
 20 #include <linux/mod_devicetable.h>
 21 
 22 #include <linux/types.h>
 23 #include <linux/init.h>
 24 #include <linux/ioport.h>
 25 #include <linux/list.h>
 26 #include <linux/compiler.h>
 27 #include <linux/errno.h>
 28 #include <linux/kobject.h>
 29 #include <linux/atomic.h>
 30 #include <linux/device.h>
 31 #include <linux/io.h>
 32 #include <linux/resource_ext.h>
 33 #include <uapi/linux/pci.h>
 34 
 35 #include <linux/pci_ids.h>
 36 
 37 /*
 38  * The PCI interface treats multi-function devices as independent
 39  * devices.  The slot/function address of each device is encoded
 40  * in a single byte as follows:
 41  *
 42  *      7:3 = slot
 43  *      2:0 = function
 44  *
 45  * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
 46  * In the interest of not exposing interfaces to user-space unnecessarily,
 47  * the following kernel-only defines are being added here.
 48  */
 49 #define PCI_DEVID(bus, devfn)  ((((u16)(bus)) << 8) | (devfn))
 50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
 51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
 52 
 53 /* pci_slot represents a physical slot */
 54 struct pci_slot {
 55         struct pci_bus *bus;            /* The bus this slot is on */
 56         struct list_head list;          /* node in list of slots on this bus */
 57         struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
 58         unsigned char number;           /* PCI_SLOT(pci_dev->devfn) */
 59         struct kobject kobj;
 60 };
 61 
 62 static inline const char *pci_slot_name(const struct pci_slot *slot)
 63 {
 64         return kobject_name(&slot->kobj);
 65 }
 66 
 67 /* File state for mmap()s on /proc/bus/pci/X/Y */
 68 enum pci_mmap_state {
 69         pci_mmap_io,
 70         pci_mmap_mem
 71 };
 72 
 73 /*
 74  *  For PCI devices, the region numbers are assigned this way:
 75  */
 76 enum {
 77         /* #0-5: standard PCI resources */
 78         PCI_STD_RESOURCES,
 79         PCI_STD_RESOURCE_END = 5,
 80 
 81         /* #6: expansion ROM resource */
 82         PCI_ROM_RESOURCE,
 83 
 84         /* device specific resources */
 85 #ifdef CONFIG_PCI_IOV
 86         PCI_IOV_RESOURCES,
 87         PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
 88 #endif
 89 
 90         /* resources assigned to buses behind the bridge */
 91 #define PCI_BRIDGE_RESOURCE_NUM 4
 92 
 93         PCI_BRIDGE_RESOURCES,
 94         PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
 95                                   PCI_BRIDGE_RESOURCE_NUM - 1,
 96 
 97         /* total resources associated with a PCI device */
 98         PCI_NUM_RESOURCES,
 99 
100         /* preserve this for compatibility */
101         DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
102 };
103 
104 /*
105  * pci_power_t values must match the bits in the Capabilities PME_Support
106  * and Control/Status PowerState fields in the Power Management capability.
107  */
108 typedef int __bitwise pci_power_t;
109 
110 #define PCI_D0          ((pci_power_t __force) 0)
111 #define PCI_D1          ((pci_power_t __force) 1)
112 #define PCI_D2          ((pci_power_t __force) 2)
113 #define PCI_D3hot       ((pci_power_t __force) 3)
114 #define PCI_D3cold      ((pci_power_t __force) 4)
115 #define PCI_UNKNOWN     ((pci_power_t __force) 5)
116 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
117 
118 /* Remember to update this when the list above changes! */
119 extern const char *pci_power_names[];
120 
121 static inline const char *pci_power_name(pci_power_t state)
122 {
123         return pci_power_names[1 + (__force int) state];
124 }
125 
126 #define PCI_PM_D2_DELAY         200
127 #define PCI_PM_D3_WAIT          10
128 #define PCI_PM_D3COLD_WAIT      100
129 #define PCI_PM_BUS_WAIT         50
130 
131 /** The pci_channel state describes connectivity between the CPU and
132  *  the pci device.  If some PCI bus between here and the pci device
133  *  has crashed or locked up, this info is reflected here.
134  */
135 typedef unsigned int __bitwise pci_channel_state_t;
136 
137 enum pci_channel_state {
138         /* I/O channel is in normal state */
139         pci_channel_io_normal = (__force pci_channel_state_t) 1,
140 
141         /* I/O to channel is blocked */
142         pci_channel_io_frozen = (__force pci_channel_state_t) 2,
143 
144         /* PCI card is dead */
145         pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
146 };
147 
148 typedef unsigned int __bitwise pcie_reset_state_t;
149 
150 enum pcie_reset_state {
151         /* Reset is NOT asserted (Use to deassert reset) */
152         pcie_deassert_reset = (__force pcie_reset_state_t) 1,
153 
154         /* Use #PERST to reset PCIe device */
155         pcie_warm_reset = (__force pcie_reset_state_t) 2,
156 
157         /* Use PCIe Hot Reset to reset device */
158         pcie_hot_reset = (__force pcie_reset_state_t) 3
159 };
160 
161 typedef unsigned short __bitwise pci_dev_flags_t;
162 enum pci_dev_flags {
163         /* INTX_DISABLE in PCI_COMMAND register disables MSI
164          * generation too.
165          */
166         PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
167         /* Device configuration is irrevocably lost if disabled into D3 */
168         PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
169         /* Provide indication device is assigned by a Virtual Machine Manager */
170         PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
171         /* Flag for quirk use to store if quirk-specific ACS is enabled */
172         PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
173         /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
174         PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
175         /* Do not use bus resets for device */
176         PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
177         /* Do not use PM reset even if device advertises NoSoftRst- */
178         PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
179         /* Get VPD from function 0 VPD */
180         PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
181 };
182 
183 enum pci_irq_reroute_variant {
184         INTEL_IRQ_REROUTE_VARIANT = 1,
185         MAX_IRQ_REROUTE_VARIANTS = 3
186 };
187 
188 typedef unsigned short __bitwise pci_bus_flags_t;
189 enum pci_bus_flags {
190         PCI_BUS_FLAGS_NO_MSI    = (__force pci_bus_flags_t) 1,
191         PCI_BUS_FLAGS_NO_MMRBC  = (__force pci_bus_flags_t) 2,
192         PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
193 };
194 
195 /* These values come from the PCI Express Spec */
196 enum pcie_link_width {
197         PCIE_LNK_WIDTH_RESRV    = 0x00,
198         PCIE_LNK_X1             = 0x01,
199         PCIE_LNK_X2             = 0x02,
200         PCIE_LNK_X4             = 0x04,
201         PCIE_LNK_X8             = 0x08,
202         PCIE_LNK_X12            = 0x0C,
203         PCIE_LNK_X16            = 0x10,
204         PCIE_LNK_X32            = 0x20,
205         PCIE_LNK_WIDTH_UNKNOWN  = 0xFF,
206 };
207 
208 /* Based on the PCI Hotplug Spec, but some values are made up by us */
209 enum pci_bus_speed {
210         PCI_SPEED_33MHz                 = 0x00,
211         PCI_SPEED_66MHz                 = 0x01,
212         PCI_SPEED_66MHz_PCIX            = 0x02,
213         PCI_SPEED_100MHz_PCIX           = 0x03,
214         PCI_SPEED_133MHz_PCIX           = 0x04,
215         PCI_SPEED_66MHz_PCIX_ECC        = 0x05,
216         PCI_SPEED_100MHz_PCIX_ECC       = 0x06,
217         PCI_SPEED_133MHz_PCIX_ECC       = 0x07,
218         PCI_SPEED_66MHz_PCIX_266        = 0x09,
219         PCI_SPEED_100MHz_PCIX_266       = 0x0a,
220         PCI_SPEED_133MHz_PCIX_266       = 0x0b,
221         AGP_UNKNOWN                     = 0x0c,
222         AGP_1X                          = 0x0d,
223         AGP_2X                          = 0x0e,
224         AGP_4X                          = 0x0f,
225         AGP_8X                          = 0x10,
226         PCI_SPEED_66MHz_PCIX_533        = 0x11,
227         PCI_SPEED_100MHz_PCIX_533       = 0x12,
228         PCI_SPEED_133MHz_PCIX_533       = 0x13,
229         PCIE_SPEED_2_5GT                = 0x14,
230         PCIE_SPEED_5_0GT                = 0x15,
231         PCIE_SPEED_8_0GT                = 0x16,
232         PCI_SPEED_UNKNOWN               = 0xff,
233 };
234 
235 struct pci_cap_saved_data {
236         u16 cap_nr;
237         bool cap_extended;
238         unsigned int size;
239         u32 data[0];
240 };
241 
242 struct pci_cap_saved_state {
243         struct hlist_node next;
244         struct pci_cap_saved_data cap;
245 };
246 
247 struct pcie_link_state;
248 struct pci_vpd;
249 struct pci_sriov;
250 struct pci_ats;
251 
252 /*
253  * The pci_dev structure is used to describe PCI devices.
254  */
255 struct pci_dev {
256         struct list_head bus_list;      /* node in per-bus list */
257         struct pci_bus  *bus;           /* bus this device is on */
258         struct pci_bus  *subordinate;   /* bus this device bridges to */
259 
260         void            *sysdata;       /* hook for sys-specific extension */
261         struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
262         struct pci_slot *slot;          /* Physical slot this device is in */
263 
264         unsigned int    devfn;          /* encoded device & function index */
265         unsigned short  vendor;
266         unsigned short  device;
267         unsigned short  subsystem_vendor;
268         unsigned short  subsystem_device;
269         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
270         u8              revision;       /* PCI revision, low byte of class word */
271         u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
272 #ifdef CONFIG_PCIEAER
273         u16             aer_cap;        /* AER capability offset */
274 #endif
275         u8              pcie_cap;       /* PCIe capability offset */
276         u8              msi_cap;        /* MSI capability offset */
277         u8              msix_cap;       /* MSI-X capability offset */
278         u8              pcie_mpss:3;    /* PCIe Max Payload Size Supported */
279         u8              rom_base_reg;   /* which config register controls the ROM */
280         u8              pin;            /* which interrupt pin this device uses */
281         u16             pcie_flags_reg; /* cached PCIe Capabilities Register */
282         unsigned long   *dma_alias_mask;/* mask of enabled devfn aliases */
283 
284         struct pci_driver *driver;      /* which driver has allocated this device */
285         u64             dma_mask;       /* Mask of the bits of bus address this
286                                            device implements.  Normally this is
287                                            0xffffffff.  You only need to change
288                                            this if your device has broken DMA
289                                            or supports 64-bit transfers.  */
290 
291         struct device_dma_parameters dma_parms;
292 
293         pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
294                                            this is D0-D3, D0 being fully functional,
295                                            and D3 being off. */
296         u8              pm_cap;         /* PM capability offset */
297         unsigned int    pme_support:5;  /* Bitmask of states from which PME#
298                                            can be generated */
299         unsigned int    pme_interrupt:1;
300         unsigned int    pme_poll:1;     /* Poll device's PME status bit */
301         unsigned int    d1_support:1;   /* Low power state D1 is supported */
302         unsigned int    d2_support:1;   /* Low power state D2 is supported */
303         unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
304         unsigned int    no_d3cold:1;    /* D3cold is forbidden */
305         unsigned int    bridge_d3:1;    /* Allow D3 for bridge */
306         unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
307         unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
308                                                    decoding during bar sizing */
309         unsigned int    wakeup_prepared:1;
310         unsigned int    runtime_d3cold:1;       /* whether go through runtime
311                                                    D3cold, not set for devices
312                                                    powered on/off by the
313                                                    corresponding bridge */
314         unsigned int    ignore_hotplug:1;       /* Ignore hotplug events */
315         unsigned int    hotplug_user_indicators:1; /* SlotCtl indicators
316                                                       controlled exclusively by
317                                                       user sysfs */
318         unsigned int    d3_delay;       /* D3->D0 transition time in ms */
319         unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
320 
321 #ifdef CONFIG_PCIEASPM
322         struct pcie_link_state  *link_state;    /* ASPM link state */
323 #endif
324 
325         pci_channel_state_t error_state;        /* current connectivity state */
326         struct  device  dev;            /* Generic device interface */
327 
328         int             cfg_size;       /* Size of configuration space */
329 
330         /*
331          * Instead of touching interrupt line and base address registers
332          * directly, use the values stored here. They might be different!
333          */
334         unsigned int    irq;
335         struct cpumask  *irq_affinity;
336         struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
337 
338         bool match_driver;              /* Skip attaching driver */
339         /* These fields are used by common fixups */
340         unsigned int    transparent:1;  /* Subtractive decode PCI bridge */
341         unsigned int    multifunction:1;/* Part of multi-function device */
342         /* keep track of device state */
343         unsigned int    is_added:1;
344         unsigned int    is_busmaster:1; /* device is busmaster */
345         unsigned int    no_msi:1;       /* device may not use msi */
346         unsigned int    no_64bit_msi:1; /* device may only use 32-bit MSIs */
347         unsigned int    block_cfg_access:1;     /* config space access is blocked */
348         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
349         unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
350         unsigned int    msi_enabled:1;
351         unsigned int    msix_enabled:1;
352         unsigned int    ari_enabled:1;  /* ARI forwarding */
353         unsigned int    ats_enabled:1;  /* Address Translation Service */
354         unsigned int    is_managed:1;
355         unsigned int    needs_freset:1; /* Dev requires fundamental reset */
356         unsigned int    state_saved:1;
357         unsigned int    is_physfn:1;
358         unsigned int    is_virtfn:1;
359         unsigned int    reset_fn:1;
360         unsigned int    is_hotplug_bridge:1;
361         unsigned int    __aer_firmware_first_valid:1;
362         unsigned int    __aer_firmware_first:1;
363         unsigned int    broken_intx_masking:1;
364         unsigned int    io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
365         unsigned int    irq_managed:1;
366         unsigned int    has_secondary_link:1;
367         unsigned int    non_compliant_bars:1;   /* broken BARs; ignore them */
368         pci_dev_flags_t dev_flags;
369         atomic_t        enable_cnt;     /* pci_enable_device has been called */
370 
371         u32             saved_config_space[16]; /* config space saved at suspend time */
372         struct hlist_head saved_cap_space;
373         struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
374         int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
375         struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
376         struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
377 
378 #ifdef CONFIG_PCIE_PTM
379         unsigned int    ptm_root:1;
380         unsigned int    ptm_enabled:1;
381         u8              ptm_granularity;
382 #endif
383 #ifdef CONFIG_PCI_MSI
384         const struct attribute_group **msi_irq_groups;
385 #endif
386         struct pci_vpd *vpd;
387 #ifdef CONFIG_PCI_ATS
388         union {
389                 struct pci_sriov *sriov;        /* SR-IOV capability related */
390                 struct pci_dev *physfn; /* the PF this VF is associated with */
391         };
392         u16             ats_cap;        /* ATS Capability offset */
393         u8              ats_stu;        /* ATS Smallest Translation Unit */
394         atomic_t        ats_ref_cnt;    /* number of VFs with ATS enabled */
395 #endif
396         phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
397         size_t romlen; /* Length of ROM if it's not from the BAR */
398         char *driver_override; /* Driver name to force a match */
399 };
400 
401 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
402 {
403 #ifdef CONFIG_PCI_IOV
404         if (dev->is_virtfn)
405                 dev = dev->physfn;
406 #endif
407         return dev;
408 }
409 
410 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
411 
412 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
413 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
414 
415 static inline int pci_channel_offline(struct pci_dev *pdev)
416 {
417         return (pdev->error_state != pci_channel_io_normal);
418 }
419 
420 struct pci_host_bridge {
421         struct device dev;
422         struct pci_bus *bus;            /* root bus */
423         struct list_head windows;       /* resource_entry */
424         void (*release_fn)(struct pci_host_bridge *);
425         void *release_data;
426         unsigned int ignore_reset_delay:1;      /* for entire hierarchy */
427         /* Resource alignment requirements */
428         resource_size_t (*align_resource)(struct pci_dev *dev,
429                         const struct resource *res,
430                         resource_size_t start,
431                         resource_size_t size,
432                         resource_size_t align);
433 };
434 
435 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
436 
437 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
438 
439 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
440                      void (*release_fn)(struct pci_host_bridge *),
441                      void *release_data);
442 
443 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
444 
445 /*
446  * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
447  * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
448  * buses below host bridges or subtractive decode bridges) go in the list.
449  * Use pci_bus_for_each_resource() to iterate through all the resources.
450  */
451 
452 /*
453  * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
454  * and there's no way to program the bridge with the details of the window.
455  * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
456  * decode bit set, because they are explicit and can be programmed with _SRS.
457  */
458 #define PCI_SUBTRACTIVE_DECODE  0x1
459 
460 struct pci_bus_resource {
461         struct list_head list;
462         struct resource *res;
463         unsigned int flags;
464 };
465 
466 #define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
467 
468 struct pci_bus {
469         struct list_head node;          /* node in list of buses */
470         struct pci_bus  *parent;        /* parent bus this bridge is on */
471         struct list_head children;      /* list of child buses */
472         struct list_head devices;       /* list of devices on this bus */
473         struct pci_dev  *self;          /* bridge device as seen by parent */
474         struct list_head slots;         /* list of slots on this bus;
475                                            protected by pci_slot_mutex */
476         struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
477         struct list_head resources;     /* address space routed to this bus */
478         struct resource busn_res;       /* bus numbers routed to this bus */
479 
480         struct pci_ops  *ops;           /* configuration access functions */
481         struct msi_controller *msi;     /* MSI controller */
482         void            *sysdata;       /* hook for sys-specific extension */
483         struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
484 
485         unsigned char   number;         /* bus number */
486         unsigned char   primary;        /* number of primary bridge */
487         unsigned char   max_bus_speed;  /* enum pci_bus_speed */
488         unsigned char   cur_bus_speed;  /* enum pci_bus_speed */
489 #ifdef CONFIG_PCI_DOMAINS_GENERIC
490         int             domain_nr;
491 #endif
492 
493         char            name[48];
494 
495         unsigned short  bridge_ctl;     /* manage NO_ISA/FBB/et al behaviors */
496         pci_bus_flags_t bus_flags;      /* inherited by child buses */
497         struct device           *bridge;
498         struct device           dev;
499         struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
500         struct bin_attribute    *legacy_mem; /* legacy mem */
501         unsigned int            is_added:1;
502 };
503 
504 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
505 
506 /*
507  * Returns true if the PCI bus is root (behind host-PCI bridge),
508  * false otherwise
509  *
510  * Some code assumes that "bus->self == NULL" means that bus is a root bus.
511  * This is incorrect because "virtual" buses added for SR-IOV (via
512  * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
513  */
514 static inline bool pci_is_root_bus(struct pci_bus *pbus)
515 {
516         return !(pbus->parent);
517 }
518 
519 /**
520  * pci_is_bridge - check if the PCI device is a bridge
521  * @dev: PCI device
522  *
523  * Return true if the PCI device is bridge whether it has subordinate
524  * or not.
525  */
526 static inline bool pci_is_bridge(struct pci_dev *dev)
527 {
528         return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
529                 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
530 }
531 
532 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
533 {
534         dev = pci_physfn(dev);
535         if (pci_is_root_bus(dev->bus))
536                 return NULL;
537 
538         return dev->bus->self;
539 }
540 
541 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
542 void pci_put_host_bridge_device(struct device *dev);
543 
544 #ifdef CONFIG_PCI_MSI
545 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
546 {
547         return pci_dev->msi_enabled || pci_dev->msix_enabled;
548 }
549 #else
550 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
551 #endif
552 
553 /*
554  * Error values that may be returned by PCI functions.
555  */
556 #define PCIBIOS_SUCCESSFUL              0x00
557 #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
558 #define PCIBIOS_BAD_VENDOR_ID           0x83
559 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
560 #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
561 #define PCIBIOS_SET_FAILED              0x88
562 #define PCIBIOS_BUFFER_TOO_SMALL        0x89
563 
564 /*
565  * Translate above to generic errno for passing back through non-PCI code.
566  */
567 static inline int pcibios_err_to_errno(int err)
568 {
569         if (err <= PCIBIOS_SUCCESSFUL)
570                 return err; /* Assume already errno */
571 
572         switch (err) {
573         case PCIBIOS_FUNC_NOT_SUPPORTED:
574                 return -ENOENT;
575         case PCIBIOS_BAD_VENDOR_ID:
576                 return -ENOTTY;
577         case PCIBIOS_DEVICE_NOT_FOUND:
578                 return -ENODEV;
579         case PCIBIOS_BAD_REGISTER_NUMBER:
580                 return -EFAULT;
581         case PCIBIOS_SET_FAILED:
582                 return -EIO;
583         case PCIBIOS_BUFFER_TOO_SMALL:
584                 return -ENOSPC;
585         }
586 
587         return -ERANGE;
588 }
589 
590 /* Low-level architecture-dependent routines */
591 
592 struct pci_ops {
593         int (*add_bus)(struct pci_bus *bus);
594         void (*remove_bus)(struct pci_bus *bus);
595         void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
596         int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
597         int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
598 };
599 
600 /*
601  * ACPI needs to be able to access PCI config space before we've done a
602  * PCI bus scan and created pci_bus structures.
603  */
604 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
605                  int reg, int len, u32 *val);
606 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
607                   int reg, int len, u32 val);
608 
609 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
610 typedef u64 pci_bus_addr_t;
611 #else
612 typedef u32 pci_bus_addr_t;
613 #endif
614 
615 struct pci_bus_region {
616         pci_bus_addr_t start;
617         pci_bus_addr_t end;
618 };
619 
620 struct pci_dynids {
621         spinlock_t lock;            /* protects list, index */
622         struct list_head list;      /* for IDs added at runtime */
623 };
624 
625 
626 /*
627  * PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
628  * a set of callbacks in struct pci_error_handlers, that device driver
629  * will be notified of PCI bus errors, and will be driven to recovery
630  * when an error occurs.
631  */
632 
633 typedef unsigned int __bitwise pci_ers_result_t;
634 
635 enum pci_ers_result {
636         /* no result/none/not supported in device driver */
637         PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
638 
639         /* Device driver can recover without slot reset */
640         PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
641 
642         /* Device driver wants slot to be reset. */
643         PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
644 
645         /* Device has completely failed, is unrecoverable */
646         PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
647 
648         /* Device driver is fully recovered and operational */
649         PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
650 
651         /* No AER capabilities registered for the driver */
652         PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
653 };
654 
655 /* PCI bus error event callbacks */
656 struct pci_error_handlers {
657         /* PCI bus error detected on this device */
658         pci_ers_result_t (*error_detected)(struct pci_dev *dev,
659                                            enum pci_channel_state error);
660 
661         /* MMIO has been re-enabled, but not DMA */
662         pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
663 
664         /* PCI Express link has been reset */
665         pci_ers_result_t (*link_reset)(struct pci_dev *dev);
666 
667         /* PCI slot has been reset */
668         pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
669 
670         /* PCI function reset prepare or completed */
671         void (*reset_notify)(struct pci_dev *dev, bool prepare);
672 
673         /* Device driver may resume normal operations */
674         void (*resume)(struct pci_dev *dev);
675 };
676 
677 
678 struct module;
679 struct pci_driver {
680         struct list_head node;
681         const char *name;
682         const struct pci_device_id *id_table;   /* must be non-NULL for probe to be called */
683         int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);   /* New device inserted */
684         void (*remove) (struct pci_dev *dev);   /* Device removed (NULL if not a hot-plug capable driver) */
685         int  (*suspend) (struct pci_dev *dev, pm_message_t state);      /* Device suspended */
686         int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);
687         int  (*resume_early) (struct pci_dev *dev);
688         int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
689         void (*shutdown) (struct pci_dev *dev);
690         int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
691         const struct pci_error_handlers *err_handler;
692         struct device_driver    driver;
693         struct pci_dynids dynids;
694 };
695 
696 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
697 
698 /**
699  * PCI_DEVICE - macro used to describe a specific pci device
700  * @vend: the 16 bit PCI Vendor ID
701  * @dev: the 16 bit PCI Device ID
702  *
703  * This macro is used to create a struct pci_device_id that matches a
704  * specific device.  The subvendor and subdevice fields will be set to
705  * PCI_ANY_ID.
706  */
707 #define PCI_DEVICE(vend,dev) \
708         .vendor = (vend), .device = (dev), \
709         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
710 
711 /**
712  * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
713  * @vend: the 16 bit PCI Vendor ID
714  * @dev: the 16 bit PCI Device ID
715  * @subvend: the 16 bit PCI Subvendor ID
716  * @subdev: the 16 bit PCI Subdevice ID
717  *
718  * This macro is used to create a struct pci_device_id that matches a
719  * specific device with subsystem information.
720  */
721 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
722         .vendor = (vend), .device = (dev), \
723         .subvendor = (subvend), .subdevice = (subdev)
724 
725 /**
726  * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
727  * @dev_class: the class, subclass, prog-if triple for this device
728  * @dev_class_mask: the class mask for this device
729  *
730  * This macro is used to create a struct pci_device_id that matches a
731  * specific PCI class.  The vendor, device, subvendor, and subdevice
732  * fields will be set to PCI_ANY_ID.
733  */
734 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
735         .class = (dev_class), .class_mask = (dev_class_mask), \
736         .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
737         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
738 
739 /**
740  * PCI_VDEVICE - macro used to describe a specific pci device in short form
741  * @vend: the vendor name
742  * @dev: the 16 bit PCI Device ID
743  *
744  * This macro is used to create a struct pci_device_id that matches a
745  * specific PCI device.  The subvendor, and subdevice fields will be set
746  * to PCI_ANY_ID. The macro allows the next field to follow as the device
747  * private data.
748  */
749 
750 #define PCI_VDEVICE(vend, dev) \
751         .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
752         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
753 
754 enum {
755         PCI_REASSIGN_ALL_RSRC   = 0x00000001,   /* ignore firmware setup */
756         PCI_REASSIGN_ALL_BUS    = 0x00000002,   /* reassign all bus numbers */
757         PCI_PROBE_ONLY          = 0x00000004,   /* use existing setup */
758         PCI_CAN_SKIP_ISA_ALIGN  = 0x00000008,   /* don't do ISA alignment */
759         PCI_ENABLE_PROC_DOMAINS = 0x00000010,   /* enable domains in /proc */
760         PCI_COMPAT_DOMAIN_0     = 0x00000020,   /* ... except domain 0 */
761         PCI_SCAN_ALL_PCIE_DEVS  = 0x00000040,   /* scan all, not just dev 0 */
762 };
763 
764 /* these external functions are only available when PCI support is enabled */
765 #ifdef CONFIG_PCI
766 
767 extern unsigned int pci_flags;
768 
769 static inline void pci_set_flags(int flags) { pci_flags = flags; }
770 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
771 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
772 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
773 
774 void pcie_bus_configure_settings(struct pci_bus *bus);
775 
776 enum pcie_bus_config_types {
777         PCIE_BUS_TUNE_OFF,      /* don't touch MPS at all */
778         PCIE_BUS_DEFAULT,       /* ensure MPS matches upstream bridge */
779         PCIE_BUS_SAFE,          /* use largest MPS boot-time devices support */
780         PCIE_BUS_PERFORMANCE,   /* use MPS and MRRS for best performance */
781         PCIE_BUS_PEER2PEER,     /* set MPS = 128 for all devices */
782 };
783 
784 extern enum pcie_bus_config_types pcie_bus_config;
785 
786 extern struct bus_type pci_bus_type;
787 
788 /* Do NOT directly access these two variables, unless you are arch-specific PCI
789  * code, or PCI core code. */
790 extern struct list_head pci_root_buses; /* list of all known PCI buses */
791 /* Some device drivers need know if PCI is initiated */
792 int no_pci_devices(void);
793 
794 void pcibios_resource_survey_bus(struct pci_bus *bus);
795 void pcibios_bus_add_device(struct pci_dev *pdev);
796 void pcibios_add_bus(struct pci_bus *bus);
797 void pcibios_remove_bus(struct pci_bus *bus);
798 void pcibios_fixup_bus(struct pci_bus *);
799 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
800 /* Architecture-specific versions may override this (weak) */
801 char *pcibios_setup(char *str);
802 
803 /* Used only when drivers/pci/setup.c is used */
804 resource_size_t pcibios_align_resource(void *, const struct resource *,
805                                 resource_size_t,
806                                 resource_size_t);
807 void pcibios_update_irq(struct pci_dev *, int irq);
808 
809 /* Weak but can be overriden by arch */
810 void pci_fixup_cardbus(struct pci_bus *);
811 
812 /* Generic PCI functions used internally */
813 
814 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
815                              struct resource *res);
816 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
817                              struct pci_bus_region *region);
818 void pcibios_scan_specific_bus(int busn);
819 struct pci_bus *pci_find_bus(int domain, int busnr);
820 void pci_bus_add_devices(const struct pci_bus *bus);
821 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
822 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
823                                     struct pci_ops *ops, void *sysdata,
824                                     struct list_head *resources);
825 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
826 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
827 void pci_bus_release_busn_res(struct pci_bus *b);
828 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
829                                       struct pci_ops *ops, void *sysdata,
830                                       struct list_head *resources,
831                                       struct msi_controller *msi);
832 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
833                                              struct pci_ops *ops, void *sysdata,
834                                              struct list_head *resources);
835 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
836                                 int busnr);
837 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
838 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
839                                  const char *name,
840                                  struct hotplug_slot *hotplug);
841 void pci_destroy_slot(struct pci_slot *slot);
842 #ifdef CONFIG_SYSFS
843 void pci_dev_assign_slot(struct pci_dev *dev);
844 #else
845 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
846 #endif
847 int pci_scan_slot(struct pci_bus *bus, int devfn);
848 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
849 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
850 unsigned int pci_scan_child_bus(struct pci_bus *bus);
851 void pci_bus_add_device(struct pci_dev *dev);
852 void pci_read_bridge_bases(struct pci_bus *child);
853 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
854                                           struct resource *res);
855 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
856 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
857 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
858 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
859 struct pci_dev *pci_dev_get(struct pci_dev *dev);
860 void pci_dev_put(struct pci_dev *dev);
861 void pci_remove_bus(struct pci_bus *b);
862 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
863 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
864 void pci_stop_root_bus(struct pci_bus *bus);
865 void pci_remove_root_bus(struct pci_bus *bus);
866 void pci_setup_cardbus(struct pci_bus *bus);
867 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
868 void pci_sort_breadthfirst(void);
869 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
870 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
871 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
872 
873 /* Generic PCI functions exported to card drivers */
874 
875 enum pci_lost_interrupt_reason {
876         PCI_LOST_IRQ_NO_INFORMATION = 0,
877         PCI_LOST_IRQ_DISABLE_MSI,
878         PCI_LOST_IRQ_DISABLE_MSIX,
879         PCI_LOST_IRQ_DISABLE_ACPI,
880 };
881 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
882 int pci_find_capability(struct pci_dev *dev, int cap);
883 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
884 int pci_find_ext_capability(struct pci_dev *dev, int cap);
885 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
886 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
887 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
888 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
889 
890 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
891                                 struct pci_dev *from);
892 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
893                                 unsigned int ss_vendor, unsigned int ss_device,
894                                 struct pci_dev *from);
895 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
896 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
897                                             unsigned int devfn);
898 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
899                                                    unsigned int devfn)
900 {
901         return pci_get_domain_bus_and_slot(0, bus, devfn);
902 }
903 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
904 int pci_dev_present(const struct pci_device_id *ids);
905 
906 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
907                              int where, u8 *val);
908 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
909                              int where, u16 *val);
910 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
911                               int where, u32 *val);
912 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
913                               int where, u8 val);
914 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
915                               int where, u16 val);
916 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
917                                int where, u32 val);
918 
919 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
920                             int where, int size, u32 *val);
921 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
922                             int where, int size, u32 val);
923 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
924                               int where, int size, u32 *val);
925 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
926                                int where, int size, u32 val);
927 
928 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
929 
930 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
931 {
932         return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
933 }
934 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
935 {
936         return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
937 }
938 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
939                                         u32 *val)
940 {
941         return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
942 }
943 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
944 {
945         return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
946 }
947 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
948 {
949         return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
950 }
951 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
952                                          u32 val)
953 {
954         return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
955 }
956 
957 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
958 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
959 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
960 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
961 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
962                                        u16 clear, u16 set);
963 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
964                                         u32 clear, u32 set);
965 
966 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
967                                            u16 set)
968 {
969         return pcie_capability_clear_and_set_word(dev, pos, 0, set);
970 }
971 
972 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
973                                             u32 set)
974 {
975         return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
976 }
977 
978 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
979                                              u16 clear)
980 {
981         return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
982 }
983 
984 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
985                                               u32 clear)
986 {
987         return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
988 }
989 
990 /* user-space driven config access */
991 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
992 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
993 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
994 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
995 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
996 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
997 
998 int __must_check pci_enable_device(struct pci_dev *dev);
999 int __must_check pci_enable_device_io(struct pci_dev *dev);
1000 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1001 int __must_check pci_reenable_device(struct pci_dev *);
1002 int __must_check pcim_enable_device(struct pci_dev *pdev);
1003 void pcim_pin_device(struct pci_dev *pdev);
1004 
1005 static inline int pci_is_enabled(struct pci_dev *pdev)
1006 {
1007         return (atomic_read(&pdev->enable_cnt) > 0);
1008 }
1009 
1010 static inline int pci_is_managed(struct pci_dev *pdev)
1011 {
1012         return pdev->is_managed;
1013 }
1014 
1015 void pci_disable_device(struct pci_dev *dev);
1016 
1017 extern unsigned int pcibios_max_latency;
1018 void pci_set_master(struct pci_dev *dev);
1019 void pci_clear_master(struct pci_dev *dev);
1020 
1021 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1022 int pci_set_cacheline_size(struct pci_dev *dev);
1023 #define HAVE_PCI_SET_MWI
1024 int __must_check pci_set_mwi(struct pci_dev *dev);
1025 int pci_try_set_mwi(struct pci_dev *dev);
1026 void pci_clear_mwi(struct pci_dev *dev);
1027 void pci_intx(struct pci_dev *dev, int enable);
1028 bool pci_intx_mask_supported(struct pci_dev *dev);
1029 bool pci_check_and_mask_intx(struct pci_dev *dev);
1030 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1031 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1032 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1033 int pcix_get_max_mmrbc(struct pci_dev *dev);
1034 int pcix_get_mmrbc(struct pci_dev *dev);
1035 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1036 int pcie_get_readrq(struct pci_dev *dev);
1037 int pcie_set_readrq(struct pci_dev *dev, int rq);
1038 int pcie_get_mps(struct pci_dev *dev);
1039 int pcie_set_mps(struct pci_dev *dev, int mps);
1040 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1041                           enum pcie_link_width *width);
1042 int __pci_reset_function(struct pci_dev *dev);
1043 int __pci_reset_function_locked(struct pci_dev *dev);
1044 int pci_reset_function(struct pci_dev *dev);
1045 int pci_try_reset_function(struct pci_dev *dev);
1046 int pci_probe_reset_slot(struct pci_slot *slot);
1047 int pci_reset_slot(struct pci_slot *slot);
1048 int pci_try_reset_slot(struct pci_slot *slot);
1049 int pci_probe_reset_bus(struct pci_bus *bus);
1050 int pci_reset_bus(struct pci_bus *bus);
1051 int pci_try_reset_bus(struct pci_bus *bus);
1052 void pci_reset_secondary_bus(struct pci_dev *dev);
1053 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1054 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1055 void pci_update_resource(struct pci_dev *dev, int resno);
1056 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1057 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1058 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1059 bool pci_device_is_present(struct pci_dev *pdev);
1060 void pci_ignore_hotplug(struct pci_dev *dev);
1061 
1062 /* ROM control related routines */
1063 int pci_enable_rom(struct pci_dev *pdev);
1064 void pci_disable_rom(struct pci_dev *pdev);
1065 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1066 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1067 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1068 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1069 
1070 /* Power management related routines */
1071 int pci_save_state(struct pci_dev *dev);
1072 void pci_restore_state(struct pci_dev *dev);
1073 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1074 int pci_load_saved_state(struct pci_dev *dev,
1075                          struct pci_saved_state *state);
1076 int pci_load_and_free_saved_state(struct pci_dev *dev,
1077                                   struct pci_saved_state **state);
1078 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1079 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1080                                                    u16 cap);
1081 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1082 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1083                                 u16 cap, unsigned int size);
1084 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1085 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1086 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1087 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1088 void pci_pme_active(struct pci_dev *dev, bool enable);
1089 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1090                       bool runtime, bool enable);
1091 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1092 int pci_prepare_to_sleep(struct pci_dev *dev);
1093 int pci_back_from_sleep(struct pci_dev *dev);
1094 bool pci_dev_run_wake(struct pci_dev *dev);
1095 bool pci_check_pme_status(struct pci_dev *dev);
1096 void pci_pme_wakeup_bus(struct pci_bus *bus);
1097 void pci_d3cold_enable(struct pci_dev *dev);
1098 void pci_d3cold_disable(struct pci_dev *dev);
1099 
1100 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1101                                   bool enable)
1102 {
1103         return __pci_enable_wake(dev, state, false, enable);
1104 }
1105 
1106 /* PCI Virtual Channel */
1107 int pci_save_vc_state(struct pci_dev *dev);
1108 void pci_restore_vc_state(struct pci_dev *dev);
1109 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1110 
1111 /* For use by arch with custom probe code */
1112 void set_pcie_port_type(struct pci_dev *pdev);
1113 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1114 
1115 /* Functions for PCI Hotplug drivers to use */
1116 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1117 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1118 unsigned int pci_rescan_bus(struct pci_bus *bus);
1119 void pci_lock_rescan_remove(void);
1120 void pci_unlock_rescan_remove(void);
1121 
1122 /* Vital product data routines */
1123 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1124 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1125 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1126 
1127 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1128 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1129 void pci_bus_assign_resources(const struct pci_bus *bus);
1130 void pci_bus_claim_resources(struct pci_bus *bus);
1131 void pci_bus_size_bridges(struct pci_bus *bus);
1132 int pci_claim_resource(struct pci_dev *, int);
1133 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1134 void pci_assign_unassigned_resources(void);
1135 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1136 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1137 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1138 void pdev_enable_device(struct pci_dev *);
1139 int pci_enable_resources(struct pci_dev *, int mask);
1140 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1141                     int (*)(const struct pci_dev *, u8, u8));
1142 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1143 #define HAVE_PCI_REQ_REGIONS    2
1144 int __must_check pci_request_regions(struct pci_dev *, const char *);
1145 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1146 void pci_release_regions(struct pci_dev *);
1147 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1148 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1149 void pci_release_region(struct pci_dev *, int);
1150 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1151 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1152 void pci_release_selected_regions(struct pci_dev *, int);
1153 
1154 /* drivers/pci/bus.c */
1155 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1156 void pci_bus_put(struct pci_bus *bus);
1157 void pci_add_resource(struct list_head *resources, struct resource *res);
1158 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1159                              resource_size_t offset);
1160 void pci_free_resource_list(struct list_head *resources);
1161 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1162                           unsigned int flags);
1163 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1164 void pci_bus_remove_resources(struct pci_bus *bus);
1165 int devm_request_pci_bus_resources(struct device *dev,
1166                                    struct list_head *resources);
1167 
1168 #define pci_bus_for_each_resource(bus, res, i)                          \
1169         for (i = 0;                                                     \
1170             (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1171              i++)
1172 
1173 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1174                         struct resource *res, resource_size_t size,
1175                         resource_size_t align, resource_size_t min,
1176                         unsigned long type_mask,
1177                         resource_size_t (*alignf)(void *,
1178                                                   const struct resource *,
1179                                                   resource_size_t,
1180                                                   resource_size_t),
1181                         void *alignf_data);
1182 
1183 
1184 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1185 unsigned long pci_address_to_pio(phys_addr_t addr);
1186 phys_addr_t pci_pio_to_address(unsigned long pio);
1187 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1188 void pci_unmap_iospace(struct resource *res);
1189 
1190 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1191 {
1192         struct pci_bus_region region;
1193 
1194         pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1195         return region.start;
1196 }
1197 
1198 /* Proper probing supporting hot-pluggable devices */
1199 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1200                                        const char *mod_name);
1201 
1202 /*
1203  * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1204  */
1205 #define pci_register_driver(driver)             \
1206         __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1207 
1208 void pci_unregister_driver(struct pci_driver *dev);
1209 
1210 /**
1211  * module_pci_driver() - Helper macro for registering a PCI driver
1212  * @__pci_driver: pci_driver struct
1213  *
1214  * Helper macro for PCI drivers which do not do anything special in module
1215  * init/exit. This eliminates a lot of boilerplate. Each module may only
1216  * use this macro once, and calling it replaces module_init() and module_exit()
1217  */
1218 #define module_pci_driver(__pci_driver) \
1219         module_driver(__pci_driver, pci_register_driver, \
1220                        pci_unregister_driver)
1221 
1222 /**
1223  * builtin_pci_driver() - Helper macro for registering a PCI driver
1224  * @__pci_driver: pci_driver struct
1225  *
1226  * Helper macro for PCI drivers which do not do anything special in their
1227  * init code. This eliminates a lot of boilerplate. Each driver may only
1228  * use this macro once, and calling it replaces device_initcall(...)
1229  */
1230 #define builtin_pci_driver(__pci_driver) \
1231         builtin_driver(__pci_driver, pci_register_driver)
1232 
1233 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1234 int pci_add_dynid(struct pci_driver *drv,
1235                   unsigned int vendor, unsigned int device,
1236                   unsigned int subvendor, unsigned int subdevice,
1237                   unsigned int class, unsigned int class_mask,
1238                   unsigned long driver_data);
1239 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1240                                          struct pci_dev *dev);
1241 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1242                     int pass);
1243 
1244 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1245                   void *userdata);
1246 int pci_cfg_space_size(struct pci_dev *dev);
1247 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1248 void pci_setup_bridge(struct pci_bus *bus);
1249 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1250                                          unsigned long type);
1251 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1252 
1253 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1254 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1255 
1256 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1257                       unsigned int command_bits, u32 flags);
1258 
1259 #define PCI_IRQ_LEGACY          (1 << 0) /* allow legacy interrupts */
1260 #define PCI_IRQ_MSI             (1 << 1) /* allow MSI interrupts */
1261 #define PCI_IRQ_MSIX            (1 << 2) /* allow MSI-X interrupts */
1262 #define PCI_IRQ_AFFINITY        (1 << 3) /* auto-assign affinity */
1263 #define PCI_IRQ_ALL_TYPES \
1264         (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1265 
1266 /* kmem_cache style wrapper around pci_alloc_consistent() */
1267 
1268 #include <linux/pci-dma.h>
1269 #include <linux/dmapool.h>
1270 
1271 #define pci_pool dma_pool
1272 #define pci_pool_create(name, pdev, size, align, allocation) \
1273                 dma_pool_create(name, &pdev->dev, size, align, allocation)
1274 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1275 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1276 #define pci_pool_zalloc(pool, flags, handle) \
1277                 dma_pool_zalloc(pool, flags, handle)
1278 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1279 
1280 struct msix_entry {
1281         u32     vector; /* kernel uses to write allocated vector */
1282         u16     entry;  /* driver uses to specify entry, OS writes */
1283 };
1284 
1285 #ifdef CONFIG_PCI_MSI
1286 int pci_msi_vec_count(struct pci_dev *dev);
1287 void pci_msi_shutdown(struct pci_dev *dev);
1288 void pci_disable_msi(struct pci_dev *dev);
1289 int pci_msix_vec_count(struct pci_dev *dev);
1290 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1291 void pci_msix_shutdown(struct pci_dev *dev);
1292 void pci_disable_msix(struct pci_dev *dev);
1293 void pci_restore_msi_state(struct pci_dev *dev);
1294 int pci_msi_enabled(void);
1295 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1296 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1297 {
1298         int rc = pci_enable_msi_range(dev, nvec, nvec);
1299         if (rc < 0)
1300                 return rc;
1301         return 0;
1302 }
1303 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1304                           int minvec, int maxvec);
1305 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1306                                         struct msix_entry *entries, int nvec)
1307 {
1308         int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1309         if (rc < 0)
1310                 return rc;
1311         return 0;
1312 }
1313 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1314                 unsigned int max_vecs, unsigned int flags);
1315 void pci_free_irq_vectors(struct pci_dev *dev);
1316 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1317 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1318 
1319 #else
1320 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1321 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1322 static inline void pci_disable_msi(struct pci_dev *dev) { }
1323 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1324 static inline int pci_enable_msix(struct pci_dev *dev,
1325                                   struct msix_entry *entries, int nvec)
1326 { return -ENOSYS; }
1327 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1328 static inline void pci_disable_msix(struct pci_dev *dev) { }
1329 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1330 static inline int pci_msi_enabled(void) { return 0; }
1331 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1332                                        int maxvec)
1333 { return -ENOSYS; }
1334 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1335 { return -ENOSYS; }
1336 static inline int pci_enable_msix_range(struct pci_dev *dev,
1337                       struct msix_entry *entries, int minvec, int maxvec)
1338 { return -ENOSYS; }
1339 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1340                       struct msix_entry *entries, int nvec)
1341 { return -ENOSYS; }
1342 static inline int pci_alloc_irq_vectors(struct pci_dev *dev,
1343                 unsigned int min_vecs, unsigned int max_vecs,
1344                 unsigned int flags)
1345 {
1346         if (min_vecs > 1)
1347                 return -EINVAL;
1348         return 1;
1349 }
1350 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1351 {
1352 }
1353 
1354 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1355 {
1356         if (WARN_ON_ONCE(nr > 0))
1357                 return -EINVAL;
1358         return dev->irq;
1359 }
1360 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1361                 int vec)
1362 {
1363         return cpu_possible_mask;
1364 }
1365 #endif
1366 
1367 #ifdef CONFIG_PCIEPORTBUS
1368 extern bool pcie_ports_disabled;
1369 extern bool pcie_ports_auto;
1370 #else
1371 #define pcie_ports_disabled     true
1372 #define pcie_ports_auto         false
1373 #endif
1374 
1375 #ifdef CONFIG_PCIEASPM
1376 bool pcie_aspm_support_enabled(void);
1377 #else
1378 static inline bool pcie_aspm_support_enabled(void) { return false; }
1379 #endif
1380 
1381 #ifdef CONFIG_PCIEAER
1382 void pci_no_aer(void);
1383 bool pci_aer_available(void);
1384 int pci_aer_init(struct pci_dev *dev);
1385 #else
1386 static inline void pci_no_aer(void) { }
1387 static inline bool pci_aer_available(void) { return false; }
1388 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1389 #endif
1390 
1391 #ifdef CONFIG_PCIE_ECRC
1392 void pcie_set_ecrc_checking(struct pci_dev *dev);
1393 void pcie_ecrc_get_policy(char *str);
1394 #else
1395 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1396 static inline void pcie_ecrc_get_policy(char *str) { }
1397 #endif
1398 
1399 #define pci_enable_msi(pdev)    pci_enable_msi_exact(pdev, 1)
1400 
1401 #ifdef CONFIG_HT_IRQ
1402 /* The functions a driver should call */
1403 int  ht_create_irq(struct pci_dev *dev, int idx);
1404 void ht_destroy_irq(unsigned int irq);
1405 #endif /* CONFIG_HT_IRQ */
1406 
1407 #ifdef CONFIG_PCI_ATS
1408 /* Address Translation Service */
1409 void pci_ats_init(struct pci_dev *dev);
1410 int pci_enable_ats(struct pci_dev *dev, int ps);
1411 void pci_disable_ats(struct pci_dev *dev);
1412 int pci_ats_queue_depth(struct pci_dev *dev);
1413 #else
1414 static inline void pci_ats_init(struct pci_dev *d) { }
1415 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1416 static inline void pci_disable_ats(struct pci_dev *d) { }
1417 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1418 #endif
1419 
1420 #ifdef CONFIG_PCIE_PTM
1421 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1422 #else
1423 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1424 { return -EINVAL; }
1425 #endif
1426 
1427 void pci_cfg_access_lock(struct pci_dev *dev);
1428 bool pci_cfg_access_trylock(struct pci_dev *dev);
1429 void pci_cfg_access_unlock(struct pci_dev *dev);
1430 
1431 /*
1432  * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
1433  * a PCI domain is defined to be a set of PCI buses which share
1434  * configuration space.
1435  */
1436 #ifdef CONFIG_PCI_DOMAINS
1437 extern int pci_domains_supported;
1438 int pci_get_new_domain_nr(void);
1439 #else
1440 enum { pci_domains_supported = 0 };
1441 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1442 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1443 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1444 #endif /* CONFIG_PCI_DOMAINS */
1445 
1446 /*
1447  * Generic implementation for PCI domain support. If your
1448  * architecture does not need custom management of PCI
1449  * domains then this implementation will be used
1450  */
1451 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1452 static inline int pci_domain_nr(struct pci_bus *bus)
1453 {
1454         return bus->domain_nr;
1455 }
1456 #ifdef CONFIG_ACPI
1457 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1458 #else
1459 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1460 { return 0; }
1461 #endif
1462 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1463 #endif
1464 
1465 /* some architectures require additional setup to direct VGA traffic */
1466 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1467                       unsigned int command_bits, u32 flags);
1468 void pci_register_set_vga_state(arch_set_vga_state_t func);
1469 
1470 static inline int
1471 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1472 {
1473         return pci_request_selected_regions(pdev,
1474                             pci_select_bars(pdev, IORESOURCE_IO), name);
1475 }
1476 
1477 static inline void
1478 pci_release_io_regions(struct pci_dev *pdev)
1479 {
1480         return pci_release_selected_regions(pdev,
1481                             pci_select_bars(pdev, IORESOURCE_IO));
1482 }
1483 
1484 static inline int
1485 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1486 {
1487         return pci_request_selected_regions(pdev,
1488                             pci_select_bars(pdev, IORESOURCE_MEM), name);
1489 }
1490 
1491 static inline void
1492 pci_release_mem_regions(struct pci_dev *pdev)
1493 {
1494         return pci_release_selected_regions(pdev,
1495                             pci_select_bars(pdev, IORESOURCE_MEM));
1496 }
1497 
1498 #else /* CONFIG_PCI is not enabled */
1499 
1500 static inline void pci_set_flags(int flags) { }
1501 static inline void pci_add_flags(int flags) { }
1502 static inline void pci_clear_flags(int flags) { }
1503 static inline int pci_has_flag(int flag) { return 0; }
1504 
1505 /*
1506  *  If the system does not have PCI, clearly these return errors.  Define
1507  *  these as simple inline functions to avoid hair in drivers.
1508  */
1509 
1510 #define _PCI_NOP(o, s, t) \
1511         static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1512                                                 int where, t val) \
1513                 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1514 
1515 #define _PCI_NOP_ALL(o, x)      _PCI_NOP(o, byte, u8 x) \
1516                                 _PCI_NOP(o, word, u16 x) \
1517                                 _PCI_NOP(o, dword, u32 x)
1518 _PCI_NOP_ALL(read, *)
1519 _PCI_NOP_ALL(write,)
1520 
1521 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1522                                              unsigned int device,
1523                                              struct pci_dev *from)
1524 { return NULL; }
1525 
1526 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1527                                              unsigned int device,
1528                                              unsigned int ss_vendor,
1529                                              unsigned int ss_device,
1530                                              struct pci_dev *from)
1531 { return NULL; }
1532 
1533 static inline struct pci_dev *pci_get_class(unsigned int class,
1534                                             struct pci_dev *from)
1535 { return NULL; }
1536 
1537 #define pci_dev_present(ids)    (0)
1538 #define no_pci_devices()        (1)
1539 #define pci_dev_put(dev)        do { } while (0)
1540 
1541 static inline void pci_set_master(struct pci_dev *dev) { }
1542 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1543 static inline void pci_disable_device(struct pci_dev *dev) { }
1544 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1545 { return -EBUSY; }
1546 static inline int __pci_register_driver(struct pci_driver *drv,
1547                                         struct module *owner)
1548 { return 0; }
1549 static inline int pci_register_driver(struct pci_driver *drv)
1550 { return 0; }
1551 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1552 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1553 { return 0; }
1554 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1555                                            int cap)
1556 { return 0; }
1557 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1558 { return 0; }
1559 
1560 /* Power management related routines */
1561 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1562 static inline void pci_restore_state(struct pci_dev *dev) { }
1563 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1564 { return 0; }
1565 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1566 { return 0; }
1567 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1568                                            pm_message_t state)
1569 { return PCI_D0; }
1570 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1571                                   int enable)
1572 { return 0; }
1573 
1574 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1575                                                  struct resource *res)
1576 { return NULL; }
1577 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1578 { return -EIO; }
1579 static inline void pci_release_regions(struct pci_dev *dev) { }
1580 
1581 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1582 
1583 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1584 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1585 { return 0; }
1586 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1587 
1588 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1589 { return NULL; }
1590 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1591                                                 unsigned int devfn)
1592 { return NULL; }
1593 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1594                                                 unsigned int devfn)
1595 { return NULL; }
1596 
1597 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1598 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1599 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1600 
1601 #define dev_is_pci(d) (false)
1602 #define dev_is_pf(d) (false)
1603 #define dev_num_vf(d) (0)
1604 #endif /* CONFIG_PCI */
1605 
1606 /* Include architecture-dependent settings and functions */
1607 
1608 #include <asm/pci.h>
1609 
1610 #ifndef pci_root_bus_fwnode
1611 #define pci_root_bus_fwnode(bus)        NULL
1612 #endif
1613 
1614 /* these helpers provide future and backwards compatibility
1615  * for accessing popular PCI BAR info */
1616 #define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
1617 #define pci_resource_end(dev, bar)      ((dev)->resource[(bar)].end)
1618 #define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)
1619 #define pci_resource_len(dev,bar) \
1620         ((pci_resource_start((dev), (bar)) == 0 &&      \
1621           pci_resource_end((dev), (bar)) ==             \
1622           pci_resource_start((dev), (bar))) ? 0 :       \
1623                                                         \
1624          (pci_resource_end((dev), (bar)) -              \
1625           pci_resource_start((dev), (bar)) + 1))
1626 
1627 /* Similar to the helpers above, these manipulate per-pci_dev
1628  * driver-specific data.  They are really just a wrapper around
1629  * the generic device structure functions of these calls.
1630  */
1631 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1632 {
1633         return dev_get_drvdata(&pdev->dev);
1634 }
1635 
1636 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1637 {
1638         dev_set_drvdata(&pdev->dev, data);
1639 }
1640 
1641 /* If you want to know what to call your pci_dev, ask this function.
1642  * Again, it's a wrapper around the generic device.
1643  */
1644 static inline const char *pci_name(const struct pci_dev *pdev)
1645 {
1646         return dev_name(&pdev->dev);
1647 }
1648 
1649 
1650 /* Some archs don't want to expose struct resource to userland as-is
1651  * in sysfs and /proc
1652  */
1653 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1654 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1655                           const struct resource *rsrc,
1656                           resource_size_t *start, resource_size_t *end);
1657 #else
1658 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1659                 const struct resource *rsrc, resource_size_t *start,
1660                 resource_size_t *end)
1661 {
1662         *start = rsrc->start;
1663         *end = rsrc->end;
1664 }
1665 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1666 
1667 
1668 /*
1669  *  The world is not perfect and supplies us with broken PCI devices.
1670  *  For at least a part of these bugs we need a work-around, so both
1671  *  generic (drivers/pci/quirks.c) and per-architecture code can define
1672  *  fixup hooks to be called for particular buggy devices.
1673  */
1674 
1675 struct pci_fixup {
1676         u16 vendor;             /* You can use PCI_ANY_ID here of course */
1677         u16 device;             /* You can use PCI_ANY_ID here of course */
1678         u32 class;              /* You can use PCI_ANY_ID here too */
1679         unsigned int class_shift;       /* should be 0, 8, 16 */
1680         void (*hook)(struct pci_dev *dev);
1681 };
1682 
1683 enum pci_fixup_pass {
1684         pci_fixup_early,        /* Before probing BARs */
1685         pci_fixup_header,       /* After reading configuration header */
1686         pci_fixup_final,        /* Final phase of device fixups */
1687         pci_fixup_enable,       /* pci_enable_device() time */
1688         pci_fixup_resume,       /* pci_device_resume() */
1689         pci_fixup_suspend,      /* pci_device_suspend() */
1690         pci_fixup_resume_early, /* pci_device_resume_early() */
1691         pci_fixup_suspend_late, /* pci_device_suspend_late() */
1692 };
1693 
1694 /* Anonymous variables would be nice... */
1695 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1696                                   class_shift, hook)                    \
1697         static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used       \
1698         __attribute__((__section__(#section), aligned((sizeof(void *)))))    \
1699                 = { vendor, device, class, class_shift, hook };
1700 
1701 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,            \
1702                                          class_shift, hook)             \
1703         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1704                 hook, vendor, device, class, class_shift, hook)
1705 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,           \
1706                                          class_shift, hook)             \
1707         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1708                 hook, vendor, device, class, class_shift, hook)
1709 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,            \
1710                                          class_shift, hook)             \
1711         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1712                 hook, vendor, device, class, class_shift, hook)
1713 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,           \
1714                                          class_shift, hook)             \
1715         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1716                 hook, vendor, device, class, class_shift, hook)
1717 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,           \
1718                                          class_shift, hook)             \
1719         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1720                 resume##hook, vendor, device, class,    \
1721                 class_shift, hook)
1722 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,     \
1723                                          class_shift, hook)             \
1724         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1725                 resume_early##hook, vendor, device,     \
1726                 class, class_shift, hook)
1727 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,          \
1728                                          class_shift, hook)             \
1729         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1730                 suspend##hook, vendor, device, class,   \
1731                 class_shift, hook)
1732 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class,     \
1733                                          class_shift, hook)             \
1734         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,              \
1735                 suspend_late##hook, vendor, device,     \
1736                 class, class_shift, hook)
1737 
1738 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
1739         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1740                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1741 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)                  \
1742         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1743                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1744 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)                   \
1745         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1746                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1747 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)                  \
1748         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1749                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1750 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
1751         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1752                 resume##hook, vendor, device,           \
1753                 PCI_ANY_ID, 0, hook)
1754 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
1755         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1756                 resume_early##hook, vendor, device,     \
1757                 PCI_ANY_ID, 0, hook)
1758 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
1759         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1760                 suspend##hook, vendor, device,          \
1761                 PCI_ANY_ID, 0, hook)
1762 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook)            \
1763         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,              \
1764                 suspend_late##hook, vendor, device,     \
1765                 PCI_ANY_ID, 0, hook)
1766 
1767 #ifdef CONFIG_PCI_QUIRKS
1768 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1769 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1770 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1771 #else
1772 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1773                                     struct pci_dev *dev) { }
1774 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1775                                                u16 acs_flags)
1776 {
1777         return -ENOTTY;
1778 }
1779 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1780 {
1781         return -ENOTTY;
1782 }
1783 #endif
1784 
1785 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1786 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1787 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1788 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1789 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1790                                    const char *name);
1791 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1792 
1793 extern int pci_pci_problems;
1794 #define PCIPCI_FAIL             1       /* No PCI PCI DMA */
1795 #define PCIPCI_TRITON           2
1796 #define PCIPCI_NATOMA           4
1797 #define PCIPCI_VIAETBF          8
1798 #define PCIPCI_VSFX             16
1799 #define PCIPCI_ALIMAGIK         32      /* Need low latency setting */
1800 #define PCIAGP_FAIL             64      /* No PCI to AGP DMA */
1801 
1802 extern unsigned long pci_cardbus_io_size;
1803 extern unsigned long pci_cardbus_mem_size;
1804 extern u8 pci_dfl_cache_line_size;
1805 extern u8 pci_cache_line_size;
1806 
1807 extern unsigned long pci_hotplug_io_size;
1808 extern unsigned long pci_hotplug_mem_size;
1809 extern unsigned long pci_hotplug_bus_size;
1810 
1811 /* Architecture-specific versions may override these (weak) */
1812 void pcibios_disable_device(struct pci_dev *dev);
1813 void pcibios_set_master(struct pci_dev *dev);
1814 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1815                                  enum pcie_reset_state state);
1816 int pcibios_add_device(struct pci_dev *dev);
1817 void pcibios_release_device(struct pci_dev *dev);
1818 void pcibios_penalize_isa_irq(int irq, int active);
1819 int pcibios_alloc_irq(struct pci_dev *dev);
1820 void pcibios_free_irq(struct pci_dev *dev);
1821 
1822 #ifdef CONFIG_HIBERNATE_CALLBACKS
1823 extern struct dev_pm_ops pcibios_pm_ops;
1824 #endif
1825 
1826 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1827 void __init pci_mmcfg_early_init(void);
1828 void __init pci_mmcfg_late_init(void);
1829 #else
1830 static inline void pci_mmcfg_early_init(void) { }
1831 static inline void pci_mmcfg_late_init(void) { }
1832 #endif
1833 
1834 int pci_ext_cfg_avail(void);
1835 
1836 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1837 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1838 
1839 #ifdef CONFIG_PCI_IOV
1840 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1841 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1842 
1843 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1844 void pci_disable_sriov(struct pci_dev *dev);
1845 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1846 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1847 int pci_num_vf(struct pci_dev *dev);
1848 int pci_vfs_assigned(struct pci_dev *dev);
1849 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1850 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1851 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1852 #else
1853 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1854 {
1855         return -ENOSYS;
1856 }
1857 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1858 {
1859         return -ENOSYS;
1860 }
1861 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1862 { return -ENODEV; }
1863 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1864 {
1865         return -ENOSYS;
1866 }
1867 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1868                                          int id, int reset) { }
1869 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1870 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1871 static inline int pci_vfs_assigned(struct pci_dev *dev)
1872 { return 0; }
1873 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1874 { return 0; }
1875 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1876 { return 0; }
1877 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1878 { return 0; }
1879 #endif
1880 
1881 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1882 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1883 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1884 #endif
1885 
1886 /**
1887  * pci_pcie_cap - get the saved PCIe capability offset
1888  * @dev: PCI device
1889  *
1890  * PCIe capability offset is calculated at PCI device initialization
1891  * time and saved in the data structure. This function returns saved
1892  * PCIe capability offset. Using this instead of pci_find_capability()
1893  * reduces unnecessary search in the PCI configuration space. If you
1894  * need to calculate PCIe capability offset from raw device for some
1895  * reasons, please use pci_find_capability() instead.
1896  */
1897 static inline int pci_pcie_cap(struct pci_dev *dev)
1898 {
1899         return dev->pcie_cap;
1900 }
1901 
1902 /**
1903  * pci_is_pcie - check if the PCI device is PCI Express capable
1904  * @dev: PCI device
1905  *
1906  * Returns: true if the PCI device is PCI Express capable, false otherwise.
1907  */
1908 static inline bool pci_is_pcie(struct pci_dev *dev)
1909 {
1910         return pci_pcie_cap(dev);
1911 }
1912 
1913 /**
1914  * pcie_caps_reg - get the PCIe Capabilities Register
1915  * @dev: PCI device
1916  */
1917 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1918 {
1919         return dev->pcie_flags_reg;
1920 }
1921 
1922 /**
1923  * pci_pcie_type - get the PCIe device/port type
1924  * @dev: PCI device
1925  */
1926 static inline int pci_pcie_type(const struct pci_dev *dev)
1927 {
1928         return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1929 }
1930 
1931 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
1932 {
1933         while (1) {
1934                 if (!pci_is_pcie(dev))
1935                         break;
1936                 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
1937                         return dev;
1938                 if (!dev->bus->self)
1939                         break;
1940                 dev = dev->bus->self;
1941         }
1942         return NULL;
1943 }
1944 
1945 void pci_request_acs(void);
1946 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1947 bool pci_acs_path_enabled(struct pci_dev *start,
1948                           struct pci_dev *end, u16 acs_flags);
1949 
1950 #define PCI_VPD_LRDT                    0x80    /* Large Resource Data Type */
1951 #define PCI_VPD_LRDT_ID(x)              ((x) | PCI_VPD_LRDT)
1952 
1953 /* Large Resource Data Type Tag Item Names */
1954 #define PCI_VPD_LTIN_ID_STRING          0x02    /* Identifier String */
1955 #define PCI_VPD_LTIN_RO_DATA            0x10    /* Read-Only Data */
1956 #define PCI_VPD_LTIN_RW_DATA            0x11    /* Read-Write Data */
1957 
1958 #define PCI_VPD_LRDT_ID_STRING          PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1959 #define PCI_VPD_LRDT_RO_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1960 #define PCI_VPD_LRDT_RW_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1961 
1962 /* Small Resource Data Type Tag Item Names */
1963 #define PCI_VPD_STIN_END                0x0f    /* End */
1964 
1965 #define PCI_VPD_SRDT_END                (PCI_VPD_STIN_END << 3)
1966 
1967 #define PCI_VPD_SRDT_TIN_MASK           0x78
1968 #define PCI_VPD_SRDT_LEN_MASK           0x07
1969 #define PCI_VPD_LRDT_TIN_MASK           0x7f
1970 
1971 #define PCI_VPD_LRDT_TAG_SIZE           3
1972 #define PCI_VPD_SRDT_TAG_SIZE           1
1973 
1974 #define PCI_VPD_INFO_FLD_HDR_SIZE       3
1975 
1976 #define PCI_VPD_RO_KEYWORD_PARTNO       "PN"
1977 #define PCI_VPD_RO_KEYWORD_MFR_ID       "MN"
1978 #define PCI_VPD_RO_KEYWORD_VENDOR0      "V0"
1979 #define PCI_VPD_RO_KEYWORD_CHKSUM       "RV"
1980 
1981 /**
1982  * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1983  * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1984  *
1985  * Returns the extracted Large Resource Data Type length.
1986  */
1987 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1988 {
1989         return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1990 }
1991 
1992 /**
1993  * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
1994  * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1995  *
1996  * Returns the extracted Large Resource Data Type Tag item.
1997  */
1998 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
1999 {
2000     return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2001 }
2002 
2003 /**
2004  * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2005  * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2006  *
2007  * Returns the extracted Small Resource Data Type length.
2008  */
2009 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2010 {
2011         return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2012 }
2013 
2014 /**
2015  * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2016  * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2017  *
2018  * Returns the extracted Small Resource Data Type Tag Item.
2019  */
2020 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2021 {
2022         return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2023 }
2024 
2025 /**
2026  * pci_vpd_info_field_size - Extracts the information field length
2027  * @lrdt: Pointer to the beginning of an information field header
2028  *
2029  * Returns the extracted information field length.
2030  */
2031 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2032 {
2033         return info_field[2];
2034 }
2035 
2036 /**
2037  * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2038  * @buf: Pointer to buffered vpd data
2039  * @off: The offset into the buffer at which to begin the search
2040  * @len: The length of the vpd buffer
2041  * @rdt: The Resource Data Type to search for
2042  *
2043  * Returns the index where the Resource Data Type was found or
2044  * -ENOENT otherwise.
2045  */
2046 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2047 
2048 /**
2049  * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2050  * @buf: Pointer to buffered vpd data
2051  * @off: The offset into the buffer at which to begin the search
2052  * @len: The length of the buffer area, relative to off, in which to search
2053  * @kw: The keyword to search for
2054  *
2055  * Returns the index where the information field keyword was found or
2056  * -ENOENT otherwise.
2057  */
2058 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2059                               unsigned int len, const char *kw);
2060 
2061 /* PCI <-> OF binding helpers */
2062 #ifdef CONFIG_OF
2063 struct device_node;
2064 struct irq_domain;
2065 void pci_set_of_node(struct pci_dev *dev);
2066 void pci_release_of_node(struct pci_dev *dev);
2067 void pci_set_bus_of_node(struct pci_bus *bus);
2068 void pci_release_bus_of_node(struct pci_bus *bus);
2069 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2070 
2071 /* Arch may override this (weak) */
2072 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2073 
2074 static inline struct device_node *
2075 pci_device_to_OF_node(const struct pci_dev *pdev)
2076 {
2077         return pdev ? pdev->dev.of_node : NULL;
2078 }
2079 
2080 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2081 {
2082         return bus ? bus->dev.of_node : NULL;
2083 }
2084 
2085 #else /* CONFIG_OF */
2086 static inline void pci_set_of_node(struct pci_dev *dev) { }
2087 static inline void pci_release_of_node(struct pci_dev *dev) { }
2088 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2089 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2090 static inline struct device_node *
2091 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2092 static inline struct irq_domain *
2093 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2094 #endif  /* CONFIG_OF */
2095 
2096 #ifdef CONFIG_ACPI
2097 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2098 
2099 void
2100 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2101 #else
2102 static inline struct irq_domain *
2103 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2104 #endif
2105 
2106 #ifdef CONFIG_EEH
2107 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2108 {
2109         return pdev->dev.archdata.edev;
2110 }
2111 #endif
2112 
2113 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2114 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2115 int pci_for_each_dma_alias(struct pci_dev *pdev,
2116                            int (*fn)(struct pci_dev *pdev,
2117                                      u16 alias, void *data), void *data);
2118 
2119 /* helper functions for operation of device flag */
2120 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2121 {
2122         pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2123 }
2124 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2125 {
2126         pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2127 }
2128 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2129 {
2130         return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2131 }
2132 
2133 /**
2134  * pci_ari_enabled - query ARI forwarding status
2135  * @bus: the PCI bus
2136  *
2137  * Returns true if ARI forwarding is enabled.
2138  */
2139 static inline bool pci_ari_enabled(struct pci_bus *bus)
2140 {
2141         return bus->self && bus->self->ari_enabled;
2142 }
2143 
2144 /* provide the legacy pci_dma_* API */
2145 #include <linux/pci-dma-compat.h>
2146 
2147 #endif /* LINUX_PCI_H */
2148 

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