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Linux/include/linux/pci.h

  1 /*
  2  *      pci.h
  3  *
  4  *      PCI defines and function prototypes
  5  *      Copyright 1994, Drew Eckhardt
  6  *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
  7  *
  8  *      For more information, please consult the following manuals (look at
  9  *      http://www.pcisig.com/ for how to get them):
 10  *
 11  *      PCI BIOS Specification
 12  *      PCI Local Bus Specification
 13  *      PCI to PCI Bridge Specification
 14  *      PCI System Design Guide
 15  */
 16 #ifndef LINUX_PCI_H
 17 #define LINUX_PCI_H
 18 
 19 
 20 #include <linux/mod_devicetable.h>
 21 
 22 #include <linux/types.h>
 23 #include <linux/init.h>
 24 #include <linux/ioport.h>
 25 #include <linux/list.h>
 26 #include <linux/compiler.h>
 27 #include <linux/errno.h>
 28 #include <linux/kobject.h>
 29 #include <linux/atomic.h>
 30 #include <linux/device.h>
 31 #include <linux/io.h>
 32 #include <linux/resource_ext.h>
 33 #include <uapi/linux/pci.h>
 34 
 35 #include <linux/pci_ids.h>
 36 
 37 /*
 38  * The PCI interface treats multi-function devices as independent
 39  * devices.  The slot/function address of each device is encoded
 40  * in a single byte as follows:
 41  *
 42  *      7:3 = slot
 43  *      2:0 = function
 44  *
 45  * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
 46  * In the interest of not exposing interfaces to user-space unnecessarily,
 47  * the following kernel-only defines are being added here.
 48  */
 49 #define PCI_DEVID(bus, devfn)  ((((u16)(bus)) << 8) | (devfn))
 50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
 51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
 52 
 53 /* pci_slot represents a physical slot */
 54 struct pci_slot {
 55         struct pci_bus *bus;            /* The bus this slot is on */
 56         struct list_head list;          /* node in list of slots on this bus */
 57         struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
 58         unsigned char number;           /* PCI_SLOT(pci_dev->devfn) */
 59         struct kobject kobj;
 60 };
 61 
 62 static inline const char *pci_slot_name(const struct pci_slot *slot)
 63 {
 64         return kobject_name(&slot->kobj);
 65 }
 66 
 67 /* File state for mmap()s on /proc/bus/pci/X/Y */
 68 enum pci_mmap_state {
 69         pci_mmap_io,
 70         pci_mmap_mem
 71 };
 72 
 73 /* This defines the direction arg to the DMA mapping routines. */
 74 #define PCI_DMA_BIDIRECTIONAL   0
 75 #define PCI_DMA_TODEVICE        1
 76 #define PCI_DMA_FROMDEVICE      2
 77 #define PCI_DMA_NONE            3
 78 
 79 /*
 80  *  For PCI devices, the region numbers are assigned this way:
 81  */
 82 enum {
 83         /* #0-5: standard PCI resources */
 84         PCI_STD_RESOURCES,
 85         PCI_STD_RESOURCE_END = 5,
 86 
 87         /* #6: expansion ROM resource */
 88         PCI_ROM_RESOURCE,
 89 
 90         /* device specific resources */
 91 #ifdef CONFIG_PCI_IOV
 92         PCI_IOV_RESOURCES,
 93         PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
 94 #endif
 95 
 96         /* resources assigned to buses behind the bridge */
 97 #define PCI_BRIDGE_RESOURCE_NUM 4
 98 
 99         PCI_BRIDGE_RESOURCES,
100         PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101                                   PCI_BRIDGE_RESOURCE_NUM - 1,
102 
103         /* total resources associated with a PCI device */
104         PCI_NUM_RESOURCES,
105 
106         /* preserve this for compatibility */
107         DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
108 };
109 
110 typedef int __bitwise pci_power_t;
111 
112 #define PCI_D0          ((pci_power_t __force) 0)
113 #define PCI_D1          ((pci_power_t __force) 1)
114 #define PCI_D2          ((pci_power_t __force) 2)
115 #define PCI_D3hot       ((pci_power_t __force) 3)
116 #define PCI_D3cold      ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN     ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
119 
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names[];
122 
123 static inline const char *pci_power_name(pci_power_t state)
124 {
125         return pci_power_names[1 + (int) state];
126 }
127 
128 #define PCI_PM_D2_DELAY         200
129 #define PCI_PM_D3_WAIT          10
130 #define PCI_PM_D3COLD_WAIT      100
131 #define PCI_PM_BUS_WAIT         50
132 
133 /** The pci_channel state describes connectivity between the CPU and
134  *  the pci device.  If some PCI bus between here and the pci device
135  *  has crashed or locked up, this info is reflected here.
136  */
137 typedef unsigned int __bitwise pci_channel_state_t;
138 
139 enum pci_channel_state {
140         /* I/O channel is in normal state */
141         pci_channel_io_normal = (__force pci_channel_state_t) 1,
142 
143         /* I/O to channel is blocked */
144         pci_channel_io_frozen = (__force pci_channel_state_t) 2,
145 
146         /* PCI card is dead */
147         pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
148 };
149 
150 typedef unsigned int __bitwise pcie_reset_state_t;
151 
152 enum pcie_reset_state {
153         /* Reset is NOT asserted (Use to deassert reset) */
154         pcie_deassert_reset = (__force pcie_reset_state_t) 1,
155 
156         /* Use #PERST to reset PCIe device */
157         pcie_warm_reset = (__force pcie_reset_state_t) 2,
158 
159         /* Use PCIe Hot Reset to reset device */
160         pcie_hot_reset = (__force pcie_reset_state_t) 3
161 };
162 
163 typedef unsigned short __bitwise pci_dev_flags_t;
164 enum pci_dev_flags {
165         /* INTX_DISABLE in PCI_COMMAND register disables MSI
166          * generation too.
167          */
168         PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
169         /* Device configuration is irrevocably lost if disabled into D3 */
170         PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
171         /* Provide indication device is assigned by a Virtual Machine Manager */
172         PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
173         /* Flag for quirk use to store if quirk-specific ACS is enabled */
174         PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
175         /* Flag to indicate the device uses dma_alias_devfn */
176         PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4),
177         /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
178         PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
179         /* Do not use bus resets for device */
180         PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
181         /* Do not use PM reset even if device advertises NoSoftRst- */
182         PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
183 };
184 
185 enum pci_irq_reroute_variant {
186         INTEL_IRQ_REROUTE_VARIANT = 1,
187         MAX_IRQ_REROUTE_VARIANTS = 3
188 };
189 
190 typedef unsigned short __bitwise pci_bus_flags_t;
191 enum pci_bus_flags {
192         PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
193         PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
194 };
195 
196 /* These values come from the PCI Express Spec */
197 enum pcie_link_width {
198         PCIE_LNK_WIDTH_RESRV    = 0x00,
199         PCIE_LNK_X1             = 0x01,
200         PCIE_LNK_X2             = 0x02,
201         PCIE_LNK_X4             = 0x04,
202         PCIE_LNK_X8             = 0x08,
203         PCIE_LNK_X12            = 0x0C,
204         PCIE_LNK_X16            = 0x10,
205         PCIE_LNK_X32            = 0x20,
206         PCIE_LNK_WIDTH_UNKNOWN  = 0xFF,
207 };
208 
209 /* Based on the PCI Hotplug Spec, but some values are made up by us */
210 enum pci_bus_speed {
211         PCI_SPEED_33MHz                 = 0x00,
212         PCI_SPEED_66MHz                 = 0x01,
213         PCI_SPEED_66MHz_PCIX            = 0x02,
214         PCI_SPEED_100MHz_PCIX           = 0x03,
215         PCI_SPEED_133MHz_PCIX           = 0x04,
216         PCI_SPEED_66MHz_PCIX_ECC        = 0x05,
217         PCI_SPEED_100MHz_PCIX_ECC       = 0x06,
218         PCI_SPEED_133MHz_PCIX_ECC       = 0x07,
219         PCI_SPEED_66MHz_PCIX_266        = 0x09,
220         PCI_SPEED_100MHz_PCIX_266       = 0x0a,
221         PCI_SPEED_133MHz_PCIX_266       = 0x0b,
222         AGP_UNKNOWN                     = 0x0c,
223         AGP_1X                          = 0x0d,
224         AGP_2X                          = 0x0e,
225         AGP_4X                          = 0x0f,
226         AGP_8X                          = 0x10,
227         PCI_SPEED_66MHz_PCIX_533        = 0x11,
228         PCI_SPEED_100MHz_PCIX_533       = 0x12,
229         PCI_SPEED_133MHz_PCIX_533       = 0x13,
230         PCIE_SPEED_2_5GT                = 0x14,
231         PCIE_SPEED_5_0GT                = 0x15,
232         PCIE_SPEED_8_0GT                = 0x16,
233         PCI_SPEED_UNKNOWN               = 0xff,
234 };
235 
236 struct pci_cap_saved_data {
237         u16 cap_nr;
238         bool cap_extended;
239         unsigned int size;
240         u32 data[0];
241 };
242 
243 struct pci_cap_saved_state {
244         struct hlist_node next;
245         struct pci_cap_saved_data cap;
246 };
247 
248 struct pcie_link_state;
249 struct pci_vpd;
250 struct pci_sriov;
251 struct pci_ats;
252 
253 /*
254  * The pci_dev structure is used to describe PCI devices.
255  */
256 struct pci_dev {
257         struct list_head bus_list;      /* node in per-bus list */
258         struct pci_bus  *bus;           /* bus this device is on */
259         struct pci_bus  *subordinate;   /* bus this device bridges to */
260 
261         void            *sysdata;       /* hook for sys-specific extension */
262         struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
263         struct pci_slot *slot;          /* Physical slot this device is in */
264 
265         unsigned int    devfn;          /* encoded device & function index */
266         unsigned short  vendor;
267         unsigned short  device;
268         unsigned short  subsystem_vendor;
269         unsigned short  subsystem_device;
270         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
271         u8              revision;       /* PCI revision, low byte of class word */
272         u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
273         u8              pcie_cap;       /* PCIe capability offset */
274         u8              msi_cap;        /* MSI capability offset */
275         u8              msix_cap;       /* MSI-X capability offset */
276         u8              pcie_mpss:3;    /* PCIe Max Payload Size Supported */
277         u8              rom_base_reg;   /* which config register controls the ROM */
278         u8              pin;            /* which interrupt pin this device uses */
279         u16             pcie_flags_reg; /* cached PCIe Capabilities Register */
280         u8              dma_alias_devfn;/* devfn of DMA alias, if any */
281 
282         struct pci_driver *driver;      /* which driver has allocated this device */
283         u64             dma_mask;       /* Mask of the bits of bus address this
284                                            device implements.  Normally this is
285                                            0xffffffff.  You only need to change
286                                            this if your device has broken DMA
287                                            or supports 64-bit transfers.  */
288 
289         struct device_dma_parameters dma_parms;
290 
291         pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
292                                            this is D0-D3, D0 being fully functional,
293                                            and D3 being off. */
294         u8              pm_cap;         /* PM capability offset */
295         unsigned int    pme_support:5;  /* Bitmask of states from which PME#
296                                            can be generated */
297         unsigned int    pme_interrupt:1;
298         unsigned int    pme_poll:1;     /* Poll device's PME status bit */
299         unsigned int    d1_support:1;   /* Low power state D1 is supported */
300         unsigned int    d2_support:1;   /* Low power state D2 is supported */
301         unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
302         unsigned int    no_d3cold:1;    /* D3cold is forbidden */
303         unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
304         unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
305                                                    decoding during bar sizing */
306         unsigned int    wakeup_prepared:1;
307         unsigned int    runtime_d3cold:1;       /* whether go through runtime
308                                                    D3cold, not set for devices
309                                                    powered on/off by the
310                                                    corresponding bridge */
311         unsigned int    ignore_hotplug:1;       /* Ignore hotplug events */
312         unsigned int    d3_delay;       /* D3->D0 transition time in ms */
313         unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
314 
315 #ifdef CONFIG_PCIEASPM
316         struct pcie_link_state  *link_state;    /* ASPM link state */
317 #endif
318 
319         pci_channel_state_t error_state;        /* current connectivity state */
320         struct  device  dev;            /* Generic device interface */
321 
322         int             cfg_size;       /* Size of configuration space */
323 
324         /*
325          * Instead of touching interrupt line and base address registers
326          * directly, use the values stored here. They might be different!
327          */
328         unsigned int    irq;
329         struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
330 
331         bool match_driver;              /* Skip attaching driver */
332         /* These fields are used by common fixups */
333         unsigned int    transparent:1;  /* Subtractive decode PCI bridge */
334         unsigned int    multifunction:1;/* Part of multi-function device */
335         /* keep track of device state */
336         unsigned int    is_added:1;
337         unsigned int    is_busmaster:1; /* device is busmaster */
338         unsigned int    no_msi:1;       /* device may not use msi */
339         unsigned int    no_64bit_msi:1; /* device may only use 32-bit MSIs */
340         unsigned int    block_cfg_access:1;     /* config space access is blocked */
341         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
342         unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
343         unsigned int    msi_enabled:1;
344         unsigned int    msix_enabled:1;
345         unsigned int    ari_enabled:1;  /* ARI forwarding */
346         unsigned int    is_managed:1;
347         unsigned int    needs_freset:1; /* Dev requires fundamental reset */
348         unsigned int    state_saved:1;
349         unsigned int    is_physfn:1;
350         unsigned int    is_virtfn:1;
351         unsigned int    reset_fn:1;
352         unsigned int    is_hotplug_bridge:1;
353         unsigned int    __aer_firmware_first_valid:1;
354         unsigned int    __aer_firmware_first:1;
355         unsigned int    broken_intx_masking:1;
356         unsigned int    io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
357         unsigned int    irq_managed:1;
358         pci_dev_flags_t dev_flags;
359         atomic_t        enable_cnt;     /* pci_enable_device has been called */
360 
361         u32             saved_config_space[16]; /* config space saved at suspend time */
362         struct hlist_head saved_cap_space;
363         struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
364         int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
365         struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
366         struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
367 #ifdef CONFIG_PCI_MSI
368         struct list_head msi_list;
369         const struct attribute_group **msi_irq_groups;
370 #endif
371         struct pci_vpd *vpd;
372 #ifdef CONFIG_PCI_ATS
373         union {
374                 struct pci_sriov *sriov;        /* SR-IOV capability related */
375                 struct pci_dev *physfn; /* the PF this VF is associated with */
376         };
377         struct pci_ats  *ats;   /* Address Translation Service */
378 #endif
379         phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
380         size_t romlen; /* Length of ROM if it's not from the BAR */
381         char *driver_override; /* Driver name to force a match */
382 };
383 
384 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
385 {
386 #ifdef CONFIG_PCI_IOV
387         if (dev->is_virtfn)
388                 dev = dev->physfn;
389 #endif
390         return dev;
391 }
392 
393 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
394 
395 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
396 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
397 
398 static inline int pci_channel_offline(struct pci_dev *pdev)
399 {
400         return (pdev->error_state != pci_channel_io_normal);
401 }
402 
403 struct pci_host_bridge {
404         struct device dev;
405         struct pci_bus *bus;            /* root bus */
406         struct list_head windows;       /* resource_entry */
407         void (*release_fn)(struct pci_host_bridge *);
408         void *release_data;
409         unsigned int ignore_reset_delay:1;      /* for entire hierarchy */
410 };
411 
412 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
413 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
414                      void (*release_fn)(struct pci_host_bridge *),
415                      void *release_data);
416 
417 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
418 
419 /*
420  * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
421  * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
422  * buses below host bridges or subtractive decode bridges) go in the list.
423  * Use pci_bus_for_each_resource() to iterate through all the resources.
424  */
425 
426 /*
427  * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
428  * and there's no way to program the bridge with the details of the window.
429  * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
430  * decode bit set, because they are explicit and can be programmed with _SRS.
431  */
432 #define PCI_SUBTRACTIVE_DECODE  0x1
433 
434 struct pci_bus_resource {
435         struct list_head list;
436         struct resource *res;
437         unsigned int flags;
438 };
439 
440 #define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
441 
442 struct pci_bus {
443         struct list_head node;          /* node in list of buses */
444         struct pci_bus  *parent;        /* parent bus this bridge is on */
445         struct list_head children;      /* list of child buses */
446         struct list_head devices;       /* list of devices on this bus */
447         struct pci_dev  *self;          /* bridge device as seen by parent */
448         struct list_head slots;         /* list of slots on this bus */
449         struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
450         struct list_head resources;     /* address space routed to this bus */
451         struct resource busn_res;       /* bus numbers routed to this bus */
452 
453         struct pci_ops  *ops;           /* configuration access functions */
454         struct msi_controller *msi;     /* MSI controller */
455         void            *sysdata;       /* hook for sys-specific extension */
456         struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
457 
458         unsigned char   number;         /* bus number */
459         unsigned char   primary;        /* number of primary bridge */
460         unsigned char   max_bus_speed;  /* enum pci_bus_speed */
461         unsigned char   cur_bus_speed;  /* enum pci_bus_speed */
462 #ifdef CONFIG_PCI_DOMAINS_GENERIC
463         int             domain_nr;
464 #endif
465 
466         char            name[48];
467 
468         unsigned short  bridge_ctl;     /* manage NO_ISA/FBB/et al behaviors */
469         pci_bus_flags_t bus_flags;      /* inherited by child buses */
470         struct device           *bridge;
471         struct device           dev;
472         struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
473         struct bin_attribute    *legacy_mem; /* legacy mem */
474         unsigned int            is_added:1;
475 };
476 
477 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
478 
479 /*
480  * Returns true if the PCI bus is root (behind host-PCI bridge),
481  * false otherwise
482  *
483  * Some code assumes that "bus->self == NULL" means that bus is a root bus.
484  * This is incorrect because "virtual" buses added for SR-IOV (via
485  * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
486  */
487 static inline bool pci_is_root_bus(struct pci_bus *pbus)
488 {
489         return !(pbus->parent);
490 }
491 
492 /**
493  * pci_is_bridge - check if the PCI device is a bridge
494  * @dev: PCI device
495  *
496  * Return true if the PCI device is bridge whether it has subordinate
497  * or not.
498  */
499 static inline bool pci_is_bridge(struct pci_dev *dev)
500 {
501         return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
502                 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
503 }
504 
505 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
506 {
507         dev = pci_physfn(dev);
508         if (pci_is_root_bus(dev->bus))
509                 return NULL;
510 
511         return dev->bus->self;
512 }
513 
514 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
515 void pci_put_host_bridge_device(struct device *dev);
516 
517 #ifdef CONFIG_PCI_MSI
518 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
519 {
520         return pci_dev->msi_enabled || pci_dev->msix_enabled;
521 }
522 #else
523 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
524 #endif
525 
526 /*
527  * Error values that may be returned by PCI functions.
528  */
529 #define PCIBIOS_SUCCESSFUL              0x00
530 #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
531 #define PCIBIOS_BAD_VENDOR_ID           0x83
532 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
533 #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
534 #define PCIBIOS_SET_FAILED              0x88
535 #define PCIBIOS_BUFFER_TOO_SMALL        0x89
536 
537 /*
538  * Translate above to generic errno for passing back through non-PCI code.
539  */
540 static inline int pcibios_err_to_errno(int err)
541 {
542         if (err <= PCIBIOS_SUCCESSFUL)
543                 return err; /* Assume already errno */
544 
545         switch (err) {
546         case PCIBIOS_FUNC_NOT_SUPPORTED:
547                 return -ENOENT;
548         case PCIBIOS_BAD_VENDOR_ID:
549                 return -ENOTTY;
550         case PCIBIOS_DEVICE_NOT_FOUND:
551                 return -ENODEV;
552         case PCIBIOS_BAD_REGISTER_NUMBER:
553                 return -EFAULT;
554         case PCIBIOS_SET_FAILED:
555                 return -EIO;
556         case PCIBIOS_BUFFER_TOO_SMALL:
557                 return -ENOSPC;
558         }
559 
560         return -ERANGE;
561 }
562 
563 /* Low-level architecture-dependent routines */
564 
565 struct pci_ops {
566         void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
567         int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
568         int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
569 };
570 
571 /*
572  * ACPI needs to be able to access PCI config space before we've done a
573  * PCI bus scan and created pci_bus structures.
574  */
575 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
576                  int reg, int len, u32 *val);
577 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
578                   int reg, int len, u32 val);
579 
580 struct pci_bus_region {
581         dma_addr_t start;
582         dma_addr_t end;
583 };
584 
585 struct pci_dynids {
586         spinlock_t lock;            /* protects list, index */
587         struct list_head list;      /* for IDs added at runtime */
588 };
589 
590 
591 /*
592  * PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
593  * a set of callbacks in struct pci_error_handlers, that device driver
594  * will be notified of PCI bus errors, and will be driven to recovery
595  * when an error occurs.
596  */
597 
598 typedef unsigned int __bitwise pci_ers_result_t;
599 
600 enum pci_ers_result {
601         /* no result/none/not supported in device driver */
602         PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
603 
604         /* Device driver can recover without slot reset */
605         PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
606 
607         /* Device driver wants slot to be reset. */
608         PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
609 
610         /* Device has completely failed, is unrecoverable */
611         PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
612 
613         /* Device driver is fully recovered and operational */
614         PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
615 
616         /* No AER capabilities registered for the driver */
617         PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
618 };
619 
620 /* PCI bus error event callbacks */
621 struct pci_error_handlers {
622         /* PCI bus error detected on this device */
623         pci_ers_result_t (*error_detected)(struct pci_dev *dev,
624                                            enum pci_channel_state error);
625 
626         /* MMIO has been re-enabled, but not DMA */
627         pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
628 
629         /* PCI Express link has been reset */
630         pci_ers_result_t (*link_reset)(struct pci_dev *dev);
631 
632         /* PCI slot has been reset */
633         pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
634 
635         /* PCI function reset prepare or completed */
636         void (*reset_notify)(struct pci_dev *dev, bool prepare);
637 
638         /* Device driver may resume normal operations */
639         void (*resume)(struct pci_dev *dev);
640 };
641 
642 
643 struct module;
644 struct pci_driver {
645         struct list_head node;
646         const char *name;
647         const struct pci_device_id *id_table;   /* must be non-NULL for probe to be called */
648         int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);   /* New device inserted */
649         void (*remove) (struct pci_dev *dev);   /* Device removed (NULL if not a hot-plug capable driver) */
650         int  (*suspend) (struct pci_dev *dev, pm_message_t state);      /* Device suspended */
651         int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);
652         int  (*resume_early) (struct pci_dev *dev);
653         int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
654         void (*shutdown) (struct pci_dev *dev);
655         int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
656         const struct pci_error_handlers *err_handler;
657         struct device_driver    driver;
658         struct pci_dynids dynids;
659 };
660 
661 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
662 
663 /**
664  * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
665  * @_table: device table name
666  *
667  * This macro is deprecated and should not be used in new code.
668  */
669 #define DEFINE_PCI_DEVICE_TABLE(_table) \
670         const struct pci_device_id _table[]
671 
672 /**
673  * PCI_DEVICE - macro used to describe a specific pci device
674  * @vend: the 16 bit PCI Vendor ID
675  * @dev: the 16 bit PCI Device ID
676  *
677  * This macro is used to create a struct pci_device_id that matches a
678  * specific device.  The subvendor and subdevice fields will be set to
679  * PCI_ANY_ID.
680  */
681 #define PCI_DEVICE(vend,dev) \
682         .vendor = (vend), .device = (dev), \
683         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
684 
685 /**
686  * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
687  * @vend: the 16 bit PCI Vendor ID
688  * @dev: the 16 bit PCI Device ID
689  * @subvend: the 16 bit PCI Subvendor ID
690  * @subdev: the 16 bit PCI Subdevice ID
691  *
692  * This macro is used to create a struct pci_device_id that matches a
693  * specific device with subsystem information.
694  */
695 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
696         .vendor = (vend), .device = (dev), \
697         .subvendor = (subvend), .subdevice = (subdev)
698 
699 /**
700  * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
701  * @dev_class: the class, subclass, prog-if triple for this device
702  * @dev_class_mask: the class mask for this device
703  *
704  * This macro is used to create a struct pci_device_id that matches a
705  * specific PCI class.  The vendor, device, subvendor, and subdevice
706  * fields will be set to PCI_ANY_ID.
707  */
708 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
709         .class = (dev_class), .class_mask = (dev_class_mask), \
710         .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
711         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
712 
713 /**
714  * PCI_VDEVICE - macro used to describe a specific pci device in short form
715  * @vend: the vendor name
716  * @dev: the 16 bit PCI Device ID
717  *
718  * This macro is used to create a struct pci_device_id that matches a
719  * specific PCI device.  The subvendor, and subdevice fields will be set
720  * to PCI_ANY_ID. The macro allows the next field to follow as the device
721  * private data.
722  */
723 
724 #define PCI_VDEVICE(vend, dev) \
725         .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
726         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
727 
728 /* these external functions are only available when PCI support is enabled */
729 #ifdef CONFIG_PCI
730 
731 void pcie_bus_configure_settings(struct pci_bus *bus);
732 
733 enum pcie_bus_config_types {
734         PCIE_BUS_TUNE_OFF,
735         PCIE_BUS_SAFE,
736         PCIE_BUS_PERFORMANCE,
737         PCIE_BUS_PEER2PEER,
738 };
739 
740 extern enum pcie_bus_config_types pcie_bus_config;
741 
742 extern struct bus_type pci_bus_type;
743 
744 /* Do NOT directly access these two variables, unless you are arch-specific PCI
745  * code, or PCI core code. */
746 extern struct list_head pci_root_buses; /* list of all known PCI buses */
747 /* Some device drivers need know if PCI is initiated */
748 int no_pci_devices(void);
749 
750 void pcibios_resource_survey_bus(struct pci_bus *bus);
751 void pcibios_add_bus(struct pci_bus *bus);
752 void pcibios_remove_bus(struct pci_bus *bus);
753 void pcibios_fixup_bus(struct pci_bus *);
754 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
755 /* Architecture-specific versions may override this (weak) */
756 char *pcibios_setup(char *str);
757 
758 /* Used only when drivers/pci/setup.c is used */
759 resource_size_t pcibios_align_resource(void *, const struct resource *,
760                                 resource_size_t,
761                                 resource_size_t);
762 void pcibios_update_irq(struct pci_dev *, int irq);
763 
764 /* Weak but can be overriden by arch */
765 void pci_fixup_cardbus(struct pci_bus *);
766 
767 /* Generic PCI functions used internally */
768 
769 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
770                              struct resource *res);
771 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
772                              struct pci_bus_region *region);
773 void pcibios_scan_specific_bus(int busn);
774 struct pci_bus *pci_find_bus(int domain, int busnr);
775 void pci_bus_add_devices(const struct pci_bus *bus);
776 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
777                                       struct pci_ops *ops, void *sysdata);
778 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
779 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
780                                     struct pci_ops *ops, void *sysdata,
781                                     struct list_head *resources);
782 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
783 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
784 void pci_bus_release_busn_res(struct pci_bus *b);
785 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
786                                              struct pci_ops *ops, void *sysdata,
787                                              struct list_head *resources);
788 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
789                                 int busnr);
790 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
791 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
792                                  const char *name,
793                                  struct hotplug_slot *hotplug);
794 void pci_destroy_slot(struct pci_slot *slot);
795 int pci_scan_slot(struct pci_bus *bus, int devfn);
796 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
797 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
798 unsigned int pci_scan_child_bus(struct pci_bus *bus);
799 void pci_bus_add_device(struct pci_dev *dev);
800 void pci_read_bridge_bases(struct pci_bus *child);
801 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
802                                           struct resource *res);
803 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
804 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
805 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
806 struct pci_dev *pci_dev_get(struct pci_dev *dev);
807 void pci_dev_put(struct pci_dev *dev);
808 void pci_remove_bus(struct pci_bus *b);
809 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
810 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
811 void pci_stop_root_bus(struct pci_bus *bus);
812 void pci_remove_root_bus(struct pci_bus *bus);
813 void pci_setup_cardbus(struct pci_bus *bus);
814 void pci_sort_breadthfirst(void);
815 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
816 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
817 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
818 
819 /* Generic PCI functions exported to card drivers */
820 
821 enum pci_lost_interrupt_reason {
822         PCI_LOST_IRQ_NO_INFORMATION = 0,
823         PCI_LOST_IRQ_DISABLE_MSI,
824         PCI_LOST_IRQ_DISABLE_MSIX,
825         PCI_LOST_IRQ_DISABLE_ACPI,
826 };
827 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
828 int pci_find_capability(struct pci_dev *dev, int cap);
829 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
830 int pci_find_ext_capability(struct pci_dev *dev, int cap);
831 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
832 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
833 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
834 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
835 
836 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
837                                 struct pci_dev *from);
838 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
839                                 unsigned int ss_vendor, unsigned int ss_device,
840                                 struct pci_dev *from);
841 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
842 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
843                                             unsigned int devfn);
844 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
845                                                    unsigned int devfn)
846 {
847         return pci_get_domain_bus_and_slot(0, bus, devfn);
848 }
849 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
850 int pci_dev_present(const struct pci_device_id *ids);
851 
852 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
853                              int where, u8 *val);
854 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
855                              int where, u16 *val);
856 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
857                               int where, u32 *val);
858 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
859                               int where, u8 val);
860 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
861                               int where, u16 val);
862 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
863                                int where, u32 val);
864 
865 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
866                             int where, int size, u32 *val);
867 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
868                             int where, int size, u32 val);
869 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
870                               int where, int size, u32 *val);
871 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
872                                int where, int size, u32 val);
873 
874 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
875 
876 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
877 {
878         return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
879 }
880 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
881 {
882         return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
883 }
884 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
885                                         u32 *val)
886 {
887         return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
888 }
889 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
890 {
891         return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
892 }
893 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
894 {
895         return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
896 }
897 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
898                                          u32 val)
899 {
900         return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
901 }
902 
903 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
904 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
905 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
906 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
907 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
908                                        u16 clear, u16 set);
909 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
910                                         u32 clear, u32 set);
911 
912 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
913                                            u16 set)
914 {
915         return pcie_capability_clear_and_set_word(dev, pos, 0, set);
916 }
917 
918 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
919                                             u32 set)
920 {
921         return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
922 }
923 
924 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
925                                              u16 clear)
926 {
927         return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
928 }
929 
930 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
931                                               u32 clear)
932 {
933         return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
934 }
935 
936 /* user-space driven config access */
937 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
938 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
939 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
940 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
941 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
942 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
943 
944 int __must_check pci_enable_device(struct pci_dev *dev);
945 int __must_check pci_enable_device_io(struct pci_dev *dev);
946 int __must_check pci_enable_device_mem(struct pci_dev *dev);
947 int __must_check pci_reenable_device(struct pci_dev *);
948 int __must_check pcim_enable_device(struct pci_dev *pdev);
949 void pcim_pin_device(struct pci_dev *pdev);
950 
951 static inline int pci_is_enabled(struct pci_dev *pdev)
952 {
953         return (atomic_read(&pdev->enable_cnt) > 0);
954 }
955 
956 static inline int pci_is_managed(struct pci_dev *pdev)
957 {
958         return pdev->is_managed;
959 }
960 
961 void pci_disable_device(struct pci_dev *dev);
962 
963 extern unsigned int pcibios_max_latency;
964 void pci_set_master(struct pci_dev *dev);
965 void pci_clear_master(struct pci_dev *dev);
966 
967 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
968 int pci_set_cacheline_size(struct pci_dev *dev);
969 #define HAVE_PCI_SET_MWI
970 int __must_check pci_set_mwi(struct pci_dev *dev);
971 int pci_try_set_mwi(struct pci_dev *dev);
972 void pci_clear_mwi(struct pci_dev *dev);
973 void pci_intx(struct pci_dev *dev, int enable);
974 bool pci_intx_mask_supported(struct pci_dev *dev);
975 bool pci_check_and_mask_intx(struct pci_dev *dev);
976 bool pci_check_and_unmask_intx(struct pci_dev *dev);
977 void pci_msi_off(struct pci_dev *dev);
978 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
979 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
980 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
981 int pci_wait_for_pending_transaction(struct pci_dev *dev);
982 int pcix_get_max_mmrbc(struct pci_dev *dev);
983 int pcix_get_mmrbc(struct pci_dev *dev);
984 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
985 int pcie_get_readrq(struct pci_dev *dev);
986 int pcie_set_readrq(struct pci_dev *dev, int rq);
987 int pcie_get_mps(struct pci_dev *dev);
988 int pcie_set_mps(struct pci_dev *dev, int mps);
989 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
990                           enum pcie_link_width *width);
991 int __pci_reset_function(struct pci_dev *dev);
992 int __pci_reset_function_locked(struct pci_dev *dev);
993 int pci_reset_function(struct pci_dev *dev);
994 int pci_try_reset_function(struct pci_dev *dev);
995 int pci_probe_reset_slot(struct pci_slot *slot);
996 int pci_reset_slot(struct pci_slot *slot);
997 int pci_try_reset_slot(struct pci_slot *slot);
998 int pci_probe_reset_bus(struct pci_bus *bus);
999 int pci_reset_bus(struct pci_bus *bus);
1000 int pci_try_reset_bus(struct pci_bus *bus);
1001 void pci_reset_secondary_bus(struct pci_dev *dev);
1002 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1003 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1004 void pci_update_resource(struct pci_dev *dev, int resno);
1005 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1006 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1007 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1008 bool pci_device_is_present(struct pci_dev *pdev);
1009 
1010 /* ROM control related routines */
1011 int pci_enable_rom(struct pci_dev *pdev);
1012 void pci_disable_rom(struct pci_dev *pdev);
1013 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1014 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1015 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1016 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1017 
1018 /* Power management related routines */
1019 int pci_save_state(struct pci_dev *dev);
1020 void pci_restore_state(struct pci_dev *dev);
1021 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1022 int pci_load_saved_state(struct pci_dev *dev,
1023                          struct pci_saved_state *state);
1024 int pci_load_and_free_saved_state(struct pci_dev *dev,
1025                                   struct pci_saved_state **state);
1026 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1027 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1028                                                    u16 cap);
1029 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1030 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1031                                 u16 cap, unsigned int size);
1032 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1033 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1034 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1035 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1036 void pci_pme_active(struct pci_dev *dev, bool enable);
1037 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1038                       bool runtime, bool enable);
1039 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1040 int pci_prepare_to_sleep(struct pci_dev *dev);
1041 int pci_back_from_sleep(struct pci_dev *dev);
1042 bool pci_dev_run_wake(struct pci_dev *dev);
1043 bool pci_check_pme_status(struct pci_dev *dev);
1044 void pci_pme_wakeup_bus(struct pci_bus *bus);
1045 
1046 static inline void pci_ignore_hotplug(struct pci_dev *dev)
1047 {
1048         dev->ignore_hotplug = 1;
1049 }
1050 
1051 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1052                                   bool enable)
1053 {
1054         return __pci_enable_wake(dev, state, false, enable);
1055 }
1056 
1057 /* PCI Virtual Channel */
1058 int pci_save_vc_state(struct pci_dev *dev);
1059 void pci_restore_vc_state(struct pci_dev *dev);
1060 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1061 
1062 /* For use by arch with custom probe code */
1063 void set_pcie_port_type(struct pci_dev *pdev);
1064 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1065 
1066 /* Functions for PCI Hotplug drivers to use */
1067 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1068 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1069 unsigned int pci_rescan_bus(struct pci_bus *bus);
1070 void pci_lock_rescan_remove(void);
1071 void pci_unlock_rescan_remove(void);
1072 
1073 /* Vital product data routines */
1074 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1075 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1076 
1077 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1078 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1079 void pci_bus_assign_resources(const struct pci_bus *bus);
1080 void pci_bus_size_bridges(struct pci_bus *bus);
1081 int pci_claim_resource(struct pci_dev *, int);
1082 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1083 void pci_assign_unassigned_resources(void);
1084 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1085 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1086 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1087 void pdev_enable_device(struct pci_dev *);
1088 int pci_enable_resources(struct pci_dev *, int mask);
1089 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1090                     int (*)(const struct pci_dev *, u8, u8));
1091 #define HAVE_PCI_REQ_REGIONS    2
1092 int __must_check pci_request_regions(struct pci_dev *, const char *);
1093 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1094 void pci_release_regions(struct pci_dev *);
1095 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1096 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1097 void pci_release_region(struct pci_dev *, int);
1098 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1099 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1100 void pci_release_selected_regions(struct pci_dev *, int);
1101 
1102 /* drivers/pci/bus.c */
1103 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1104 void pci_bus_put(struct pci_bus *bus);
1105 void pci_add_resource(struct list_head *resources, struct resource *res);
1106 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1107                              resource_size_t offset);
1108 void pci_free_resource_list(struct list_head *resources);
1109 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1110 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1111 void pci_bus_remove_resources(struct pci_bus *bus);
1112 
1113 #define pci_bus_for_each_resource(bus, res, i)                          \
1114         for (i = 0;                                                     \
1115             (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1116              i++)
1117 
1118 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1119                         struct resource *res, resource_size_t size,
1120                         resource_size_t align, resource_size_t min,
1121                         unsigned long type_mask,
1122                         resource_size_t (*alignf)(void *,
1123                                                   const struct resource *,
1124                                                   resource_size_t,
1125                                                   resource_size_t),
1126                         void *alignf_data);
1127 
1128 
1129 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1130 
1131 static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1132 {
1133         struct pci_bus_region region;
1134 
1135         pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1136         return region.start;
1137 }
1138 
1139 /* Proper probing supporting hot-pluggable devices */
1140 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1141                                        const char *mod_name);
1142 
1143 /*
1144  * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1145  */
1146 #define pci_register_driver(driver)             \
1147         __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1148 
1149 void pci_unregister_driver(struct pci_driver *dev);
1150 
1151 /**
1152  * module_pci_driver() - Helper macro for registering a PCI driver
1153  * @__pci_driver: pci_driver struct
1154  *
1155  * Helper macro for PCI drivers which do not do anything special in module
1156  * init/exit. This eliminates a lot of boilerplate. Each module may only
1157  * use this macro once, and calling it replaces module_init() and module_exit()
1158  */
1159 #define module_pci_driver(__pci_driver) \
1160         module_driver(__pci_driver, pci_register_driver, \
1161                        pci_unregister_driver)
1162 
1163 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1164 int pci_add_dynid(struct pci_driver *drv,
1165                   unsigned int vendor, unsigned int device,
1166                   unsigned int subvendor, unsigned int subdevice,
1167                   unsigned int class, unsigned int class_mask,
1168                   unsigned long driver_data);
1169 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1170                                          struct pci_dev *dev);
1171 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1172                     int pass);
1173 
1174 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1175                   void *userdata);
1176 int pci_cfg_space_size(struct pci_dev *dev);
1177 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1178 void pci_setup_bridge(struct pci_bus *bus);
1179 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1180                                          unsigned long type);
1181 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1182 
1183 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1184 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1185 
1186 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1187                       unsigned int command_bits, u32 flags);
1188 /* kmem_cache style wrapper around pci_alloc_consistent() */
1189 
1190 #include <linux/pci-dma.h>
1191 #include <linux/dmapool.h>
1192 
1193 #define pci_pool dma_pool
1194 #define pci_pool_create(name, pdev, size, align, allocation) \
1195                 dma_pool_create(name, &pdev->dev, size, align, allocation)
1196 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1197 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1198 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1199 
1200 enum pci_dma_burst_strategy {
1201         PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1202                                    strategy_parameter is N/A */
1203         PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1204                                    byte boundaries */
1205         PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1206                                    strategy_parameter byte boundaries */
1207 };
1208 
1209 struct msix_entry {
1210         u32     vector; /* kernel uses to write allocated vector */
1211         u16     entry;  /* driver uses to specify entry, OS writes */
1212 };
1213 
1214 
1215 #ifdef CONFIG_PCI_MSI
1216 int pci_msi_vec_count(struct pci_dev *dev);
1217 void pci_msi_shutdown(struct pci_dev *dev);
1218 void pci_disable_msi(struct pci_dev *dev);
1219 int pci_msix_vec_count(struct pci_dev *dev);
1220 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1221 void pci_msix_shutdown(struct pci_dev *dev);
1222 void pci_disable_msix(struct pci_dev *dev);
1223 void pci_restore_msi_state(struct pci_dev *dev);
1224 int pci_msi_enabled(void);
1225 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1226 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1227 {
1228         int rc = pci_enable_msi_range(dev, nvec, nvec);
1229         if (rc < 0)
1230                 return rc;
1231         return 0;
1232 }
1233 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1234                           int minvec, int maxvec);
1235 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1236                                         struct msix_entry *entries, int nvec)
1237 {
1238         int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1239         if (rc < 0)
1240                 return rc;
1241         return 0;
1242 }
1243 #else
1244 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1245 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1246 static inline void pci_disable_msi(struct pci_dev *dev) { }
1247 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1248 static inline int pci_enable_msix(struct pci_dev *dev,
1249                                   struct msix_entry *entries, int nvec)
1250 { return -ENOSYS; }
1251 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1252 static inline void pci_disable_msix(struct pci_dev *dev) { }
1253 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1254 static inline int pci_msi_enabled(void) { return 0; }
1255 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1256                                        int maxvec)
1257 { return -ENOSYS; }
1258 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1259 { return -ENOSYS; }
1260 static inline int pci_enable_msix_range(struct pci_dev *dev,
1261                       struct msix_entry *entries, int minvec, int maxvec)
1262 { return -ENOSYS; }
1263 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1264                       struct msix_entry *entries, int nvec)
1265 { return -ENOSYS; }
1266 #endif
1267 
1268 #ifdef CONFIG_PCIEPORTBUS
1269 extern bool pcie_ports_disabled;
1270 extern bool pcie_ports_auto;
1271 #else
1272 #define pcie_ports_disabled     true
1273 #define pcie_ports_auto         false
1274 #endif
1275 
1276 #ifdef CONFIG_PCIEASPM
1277 bool pcie_aspm_support_enabled(void);
1278 #else
1279 static inline bool pcie_aspm_support_enabled(void) { return false; }
1280 #endif
1281 
1282 #ifdef CONFIG_PCIEAER
1283 void pci_no_aer(void);
1284 bool pci_aer_available(void);
1285 #else
1286 static inline void pci_no_aer(void) { }
1287 static inline bool pci_aer_available(void) { return false; }
1288 #endif
1289 
1290 #ifdef CONFIG_PCIE_ECRC
1291 void pcie_set_ecrc_checking(struct pci_dev *dev);
1292 void pcie_ecrc_get_policy(char *str);
1293 #else
1294 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1295 static inline void pcie_ecrc_get_policy(char *str) { }
1296 #endif
1297 
1298 #define pci_enable_msi(pdev)    pci_enable_msi_exact(pdev, 1)
1299 
1300 #ifdef CONFIG_HT_IRQ
1301 /* The functions a driver should call */
1302 int  ht_create_irq(struct pci_dev *dev, int idx);
1303 void ht_destroy_irq(unsigned int irq);
1304 #endif /* CONFIG_HT_IRQ */
1305 
1306 void pci_cfg_access_lock(struct pci_dev *dev);
1307 bool pci_cfg_access_trylock(struct pci_dev *dev);
1308 void pci_cfg_access_unlock(struct pci_dev *dev);
1309 
1310 /*
1311  * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
1312  * a PCI domain is defined to be a set of PCI buses which share
1313  * configuration space.
1314  */
1315 #ifdef CONFIG_PCI_DOMAINS
1316 extern int pci_domains_supported;
1317 int pci_get_new_domain_nr(void);
1318 #else
1319 enum { pci_domains_supported = 0 };
1320 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1321 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1322 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1323 #endif /* CONFIG_PCI_DOMAINS */
1324 
1325 /*
1326  * Generic implementation for PCI domain support. If your
1327  * architecture does not need custom management of PCI
1328  * domains then this implementation will be used
1329  */
1330 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1331 static inline int pci_domain_nr(struct pci_bus *bus)
1332 {
1333         return bus->domain_nr;
1334 }
1335 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent);
1336 #else
1337 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus,
1338                                         struct device *parent)
1339 {
1340 }
1341 #endif
1342 
1343 /* some architectures require additional setup to direct VGA traffic */
1344 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1345                       unsigned int command_bits, u32 flags);
1346 void pci_register_set_vga_state(arch_set_vga_state_t func);
1347 
1348 #else /* CONFIG_PCI is not enabled */
1349 
1350 /*
1351  *  If the system does not have PCI, clearly these return errors.  Define
1352  *  these as simple inline functions to avoid hair in drivers.
1353  */
1354 
1355 #define _PCI_NOP(o, s, t) \
1356         static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1357                                                 int where, t val) \
1358                 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1359 
1360 #define _PCI_NOP_ALL(o, x)      _PCI_NOP(o, byte, u8 x) \
1361                                 _PCI_NOP(o, word, u16 x) \
1362                                 _PCI_NOP(o, dword, u32 x)
1363 _PCI_NOP_ALL(read, *)
1364 _PCI_NOP_ALL(write,)
1365 
1366 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1367                                              unsigned int device,
1368                                              struct pci_dev *from)
1369 { return NULL; }
1370 
1371 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1372                                              unsigned int device,
1373                                              unsigned int ss_vendor,
1374                                              unsigned int ss_device,
1375                                              struct pci_dev *from)
1376 { return NULL; }
1377 
1378 static inline struct pci_dev *pci_get_class(unsigned int class,
1379                                             struct pci_dev *from)
1380 { return NULL; }
1381 
1382 #define pci_dev_present(ids)    (0)
1383 #define no_pci_devices()        (1)
1384 #define pci_dev_put(dev)        do { } while (0)
1385 
1386 static inline void pci_set_master(struct pci_dev *dev) { }
1387 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1388 static inline void pci_disable_device(struct pci_dev *dev) { }
1389 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1390 { return -EIO; }
1391 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1392 { return -EIO; }
1393 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1394                                         unsigned int size)
1395 { return -EIO; }
1396 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1397                                         unsigned long mask)
1398 { return -EIO; }
1399 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1400 { return -EBUSY; }
1401 static inline int __pci_register_driver(struct pci_driver *drv,
1402                                         struct module *owner)
1403 { return 0; }
1404 static inline int pci_register_driver(struct pci_driver *drv)
1405 { return 0; }
1406 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1407 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1408 { return 0; }
1409 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1410                                            int cap)
1411 { return 0; }
1412 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1413 { return 0; }
1414 
1415 /* Power management related routines */
1416 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1417 static inline void pci_restore_state(struct pci_dev *dev) { }
1418 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1419 { return 0; }
1420 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1421 { return 0; }
1422 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1423                                            pm_message_t state)
1424 { return PCI_D0; }
1425 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1426                                   int enable)
1427 { return 0; }
1428 
1429 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1430 { return -EIO; }
1431 static inline void pci_release_regions(struct pci_dev *dev) { }
1432 
1433 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1434 
1435 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1436 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1437 { return 0; }
1438 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1439 
1440 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1441 { return NULL; }
1442 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1443                                                 unsigned int devfn)
1444 { return NULL; }
1445 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1446                                                 unsigned int devfn)
1447 { return NULL; }
1448 
1449 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1450 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1451 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1452 
1453 #define dev_is_pci(d) (false)
1454 #define dev_is_pf(d) (false)
1455 #define dev_num_vf(d) (0)
1456 #endif /* CONFIG_PCI */
1457 
1458 /* Include architecture-dependent settings and functions */
1459 
1460 #include <asm/pci.h>
1461 
1462 /* these helpers provide future and backwards compatibility
1463  * for accessing popular PCI BAR info */
1464 #define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
1465 #define pci_resource_end(dev, bar)      ((dev)->resource[(bar)].end)
1466 #define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)
1467 #define pci_resource_len(dev,bar) \
1468         ((pci_resource_start((dev), (bar)) == 0 &&      \
1469           pci_resource_end((dev), (bar)) ==             \
1470           pci_resource_start((dev), (bar))) ? 0 :       \
1471                                                         \
1472          (pci_resource_end((dev), (bar)) -              \
1473           pci_resource_start((dev), (bar)) + 1))
1474 
1475 /* Similar to the helpers above, these manipulate per-pci_dev
1476  * driver-specific data.  They are really just a wrapper around
1477  * the generic device structure functions of these calls.
1478  */
1479 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1480 {
1481         return dev_get_drvdata(&pdev->dev);
1482 }
1483 
1484 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1485 {
1486         dev_set_drvdata(&pdev->dev, data);
1487 }
1488 
1489 /* If you want to know what to call your pci_dev, ask this function.
1490  * Again, it's a wrapper around the generic device.
1491  */
1492 static inline const char *pci_name(const struct pci_dev *pdev)
1493 {
1494         return dev_name(&pdev->dev);
1495 }
1496 
1497 
1498 /* Some archs don't want to expose struct resource to userland as-is
1499  * in sysfs and /proc
1500  */
1501 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1502 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1503                 const struct resource *rsrc, resource_size_t *start,
1504                 resource_size_t *end)
1505 {
1506         *start = rsrc->start;
1507         *end = rsrc->end;
1508 }
1509 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1510 
1511 
1512 /*
1513  *  The world is not perfect and supplies us with broken PCI devices.
1514  *  For at least a part of these bugs we need a work-around, so both
1515  *  generic (drivers/pci/quirks.c) and per-architecture code can define
1516  *  fixup hooks to be called for particular buggy devices.
1517  */
1518 
1519 struct pci_fixup {
1520         u16 vendor;             /* You can use PCI_ANY_ID here of course */
1521         u16 device;             /* You can use PCI_ANY_ID here of course */
1522         u32 class;              /* You can use PCI_ANY_ID here too */
1523         unsigned int class_shift;       /* should be 0, 8, 16 */
1524         void (*hook)(struct pci_dev *dev);
1525 };
1526 
1527 enum pci_fixup_pass {
1528         pci_fixup_early,        /* Before probing BARs */
1529         pci_fixup_header,       /* After reading configuration header */
1530         pci_fixup_final,        /* Final phase of device fixups */
1531         pci_fixup_enable,       /* pci_enable_device() time */
1532         pci_fixup_resume,       /* pci_device_resume() */
1533         pci_fixup_suspend,      /* pci_device_suspend() */
1534         pci_fixup_resume_early, /* pci_device_resume_early() */
1535         pci_fixup_suspend_late, /* pci_device_suspend_late() */
1536 };
1537 
1538 /* Anonymous variables would be nice... */
1539 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1540                                   class_shift, hook)                    \
1541         static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used       \
1542         __attribute__((__section__(#section), aligned((sizeof(void *)))))    \
1543                 = { vendor, device, class, class_shift, hook };
1544 
1545 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,            \
1546                                          class_shift, hook)             \
1547         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1548                 hook, vendor, device, class, class_shift, hook)
1549 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,           \
1550                                          class_shift, hook)             \
1551         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1552                 hook, vendor, device, class, class_shift, hook)
1553 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,            \
1554                                          class_shift, hook)             \
1555         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1556                 hook, vendor, device, class, class_shift, hook)
1557 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,           \
1558                                          class_shift, hook)             \
1559         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1560                 hook, vendor, device, class, class_shift, hook)
1561 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,           \
1562                                          class_shift, hook)             \
1563         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1564                 resume##hook, vendor, device, class,    \
1565                 class_shift, hook)
1566 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,     \
1567                                          class_shift, hook)             \
1568         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1569                 resume_early##hook, vendor, device,     \
1570                 class, class_shift, hook)
1571 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,          \
1572                                          class_shift, hook)             \
1573         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1574                 suspend##hook, vendor, device, class,   \
1575                 class_shift, hook)
1576 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class,     \
1577                                          class_shift, hook)             \
1578         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,              \
1579                 suspend_late##hook, vendor, device,     \
1580                 class, class_shift, hook)
1581 
1582 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
1583         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1584                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1585 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)                  \
1586         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1587                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1588 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)                   \
1589         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1590                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1591 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)                  \
1592         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1593                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1594 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
1595         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1596                 resume##hook, vendor, device,           \
1597                 PCI_ANY_ID, 0, hook)
1598 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
1599         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1600                 resume_early##hook, vendor, device,     \
1601                 PCI_ANY_ID, 0, hook)
1602 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
1603         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1604                 suspend##hook, vendor, device,          \
1605                 PCI_ANY_ID, 0, hook)
1606 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook)            \
1607         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,              \
1608                 suspend_late##hook, vendor, device,     \
1609                 PCI_ANY_ID, 0, hook)
1610 
1611 #ifdef CONFIG_PCI_QUIRKS
1612 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1613 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1614 void pci_dev_specific_enable_acs(struct pci_dev *dev);
1615 #else
1616 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1617                                     struct pci_dev *dev) { }
1618 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1619                                                u16 acs_flags)
1620 {
1621         return -ENOTTY;
1622 }
1623 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { }
1624 #endif
1625 
1626 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1627 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1628 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1629 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1630 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1631                                    const char *name);
1632 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1633 
1634 extern int pci_pci_problems;
1635 #define PCIPCI_FAIL             1       /* No PCI PCI DMA */
1636 #define PCIPCI_TRITON           2
1637 #define PCIPCI_NATOMA           4
1638 #define PCIPCI_VIAETBF          8
1639 #define PCIPCI_VSFX             16
1640 #define PCIPCI_ALIMAGIK         32      /* Need low latency setting */
1641 #define PCIAGP_FAIL             64      /* No PCI to AGP DMA */
1642 
1643 extern unsigned long pci_cardbus_io_size;
1644 extern unsigned long pci_cardbus_mem_size;
1645 extern u8 pci_dfl_cache_line_size;
1646 extern u8 pci_cache_line_size;
1647 
1648 extern unsigned long pci_hotplug_io_size;
1649 extern unsigned long pci_hotplug_mem_size;
1650 
1651 /* Architecture-specific versions may override these (weak) */
1652 void pcibios_disable_device(struct pci_dev *dev);
1653 void pcibios_set_master(struct pci_dev *dev);
1654 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1655                                  enum pcie_reset_state state);
1656 int pcibios_add_device(struct pci_dev *dev);
1657 void pcibios_release_device(struct pci_dev *dev);
1658 void pcibios_penalize_isa_irq(int irq, int active);
1659 
1660 #ifdef CONFIG_HIBERNATE_CALLBACKS
1661 extern struct dev_pm_ops pcibios_pm_ops;
1662 #endif
1663 
1664 #ifdef CONFIG_PCI_MMCONFIG
1665 void __init pci_mmcfg_early_init(void);
1666 void __init pci_mmcfg_late_init(void);
1667 #else
1668 static inline void pci_mmcfg_early_init(void) { }
1669 static inline void pci_mmcfg_late_init(void) { }
1670 #endif
1671 
1672 int pci_ext_cfg_avail(void);
1673 
1674 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1675 
1676 #ifdef CONFIG_PCI_IOV
1677 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1678 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1679 
1680 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1681 void pci_disable_sriov(struct pci_dev *dev);
1682 int pci_num_vf(struct pci_dev *dev);
1683 int pci_vfs_assigned(struct pci_dev *dev);
1684 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1685 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1686 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1687 #else
1688 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1689 {
1690         return -ENOSYS;
1691 }
1692 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1693 {
1694         return -ENOSYS;
1695 }
1696 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1697 { return -ENODEV; }
1698 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1699 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1700 static inline int pci_vfs_assigned(struct pci_dev *dev)
1701 { return 0; }
1702 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1703 { return 0; }
1704 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1705 { return 0; }
1706 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1707 { return 0; }
1708 #endif
1709 
1710 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1711 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1712 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1713 #endif
1714 
1715 /**
1716  * pci_pcie_cap - get the saved PCIe capability offset
1717  * @dev: PCI device
1718  *
1719  * PCIe capability offset is calculated at PCI device initialization
1720  * time and saved in the data structure. This function returns saved
1721  * PCIe capability offset. Using this instead of pci_find_capability()
1722  * reduces unnecessary search in the PCI configuration space. If you
1723  * need to calculate PCIe capability offset from raw device for some
1724  * reasons, please use pci_find_capability() instead.
1725  */
1726 static inline int pci_pcie_cap(struct pci_dev *dev)
1727 {
1728         return dev->pcie_cap;
1729 }
1730 
1731 /**
1732  * pci_is_pcie - check if the PCI device is PCI Express capable
1733  * @dev: PCI device
1734  *
1735  * Returns: true if the PCI device is PCI Express capable, false otherwise.
1736  */
1737 static inline bool pci_is_pcie(struct pci_dev *dev)
1738 {
1739         return pci_pcie_cap(dev);
1740 }
1741 
1742 /**
1743  * pcie_caps_reg - get the PCIe Capabilities Register
1744  * @dev: PCI device
1745  */
1746 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1747 {
1748         return dev->pcie_flags_reg;
1749 }
1750 
1751 /**
1752  * pci_pcie_type - get the PCIe device/port type
1753  * @dev: PCI device
1754  */
1755 static inline int pci_pcie_type(const struct pci_dev *dev)
1756 {
1757         return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1758 }
1759 
1760 void pci_request_acs(void);
1761 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1762 bool pci_acs_path_enabled(struct pci_dev *start,
1763                           struct pci_dev *end, u16 acs_flags);
1764 
1765 #define PCI_VPD_LRDT                    0x80    /* Large Resource Data Type */
1766 #define PCI_VPD_LRDT_ID(x)              ((x) | PCI_VPD_LRDT)
1767 
1768 /* Large Resource Data Type Tag Item Names */
1769 #define PCI_VPD_LTIN_ID_STRING          0x02    /* Identifier String */
1770 #define PCI_VPD_LTIN_RO_DATA            0x10    /* Read-Only Data */
1771 #define PCI_VPD_LTIN_RW_DATA            0x11    /* Read-Write Data */
1772 
1773 #define PCI_VPD_LRDT_ID_STRING          PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1774 #define PCI_VPD_LRDT_RO_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1775 #define PCI_VPD_LRDT_RW_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1776 
1777 /* Small Resource Data Type Tag Item Names */
1778 #define PCI_VPD_STIN_END                0x78    /* End */
1779 
1780 #define PCI_VPD_SRDT_END                PCI_VPD_STIN_END
1781 
1782 #define PCI_VPD_SRDT_TIN_MASK           0x78
1783 #define PCI_VPD_SRDT_LEN_MASK           0x07
1784 
1785 #define PCI_VPD_LRDT_TAG_SIZE           3
1786 #define PCI_VPD_SRDT_TAG_SIZE           1
1787 
1788 #define PCI_VPD_INFO_FLD_HDR_SIZE       3
1789 
1790 #define PCI_VPD_RO_KEYWORD_PARTNO       "PN"
1791 #define PCI_VPD_RO_KEYWORD_MFR_ID       "MN"
1792 #define PCI_VPD_RO_KEYWORD_VENDOR0      "V0"
1793 #define PCI_VPD_RO_KEYWORD_CHKSUM       "RV"
1794 
1795 /**
1796  * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1797  * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1798  *
1799  * Returns the extracted Large Resource Data Type length.
1800  */
1801 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1802 {
1803         return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1804 }
1805 
1806 /**
1807  * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1808  * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1809  *
1810  * Returns the extracted Small Resource Data Type length.
1811  */
1812 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1813 {
1814         return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1815 }
1816 
1817 /**
1818  * pci_vpd_info_field_size - Extracts the information field length
1819  * @lrdt: Pointer to the beginning of an information field header
1820  *
1821  * Returns the extracted information field length.
1822  */
1823 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1824 {
1825         return info_field[2];
1826 }
1827 
1828 /**
1829  * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1830  * @buf: Pointer to buffered vpd data
1831  * @off: The offset into the buffer at which to begin the search
1832  * @len: The length of the vpd buffer
1833  * @rdt: The Resource Data Type to search for
1834  *
1835  * Returns the index where the Resource Data Type was found or
1836  * -ENOENT otherwise.
1837  */
1838 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1839 
1840 /**
1841  * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1842  * @buf: Pointer to buffered vpd data
1843  * @off: The offset into the buffer at which to begin the search
1844  * @len: The length of the buffer area, relative to off, in which to search
1845  * @kw: The keyword to search for
1846  *
1847  * Returns the index where the information field keyword was found or
1848  * -ENOENT otherwise.
1849  */
1850 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1851                               unsigned int len, const char *kw);
1852 
1853 /* PCI <-> OF binding helpers */
1854 #ifdef CONFIG_OF
1855 struct device_node;
1856 void pci_set_of_node(struct pci_dev *dev);
1857 void pci_release_of_node(struct pci_dev *dev);
1858 void pci_set_bus_of_node(struct pci_bus *bus);
1859 void pci_release_bus_of_node(struct pci_bus *bus);
1860 
1861 /* Arch may override this (weak) */
1862 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1863 
1864 static inline struct device_node *
1865 pci_device_to_OF_node(const struct pci_dev *pdev)
1866 {
1867         return pdev ? pdev->dev.of_node : NULL;
1868 }
1869 
1870 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1871 {
1872         return bus ? bus->dev.of_node : NULL;
1873 }
1874 
1875 #else /* CONFIG_OF */
1876 static inline void pci_set_of_node(struct pci_dev *dev) { }
1877 static inline void pci_release_of_node(struct pci_dev *dev) { }
1878 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1879 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1880 static inline struct device_node *
1881 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
1882 #endif  /* CONFIG_OF */
1883 
1884 #ifdef CONFIG_EEH
1885 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1886 {
1887         return pdev->dev.archdata.edev;
1888 }
1889 #endif
1890 
1891 int pci_for_each_dma_alias(struct pci_dev *pdev,
1892                            int (*fn)(struct pci_dev *pdev,
1893                                      u16 alias, void *data), void *data);
1894 
1895 /* helper functions for operation of device flag */
1896 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
1897 {
1898         pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
1899 }
1900 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
1901 {
1902         pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
1903 }
1904 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
1905 {
1906         return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
1907 }
1908 #endif /* LINUX_PCI_H */
1909 

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