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Linux/include/linux/pci.h

  1 /*
  2  *      pci.h
  3  *
  4  *      PCI defines and function prototypes
  5  *      Copyright 1994, Drew Eckhardt
  6  *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
  7  *
  8  *      For more information, please consult the following manuals (look at
  9  *      http://www.pcisig.com/ for how to get them):
 10  *
 11  *      PCI BIOS Specification
 12  *      PCI Local Bus Specification
 13  *      PCI to PCI Bridge Specification
 14  *      PCI System Design Guide
 15  */
 16 #ifndef LINUX_PCI_H
 17 #define LINUX_PCI_H
 18 
 19 
 20 #include <linux/mod_devicetable.h>
 21 
 22 #include <linux/types.h>
 23 #include <linux/init.h>
 24 #include <linux/ioport.h>
 25 #include <linux/list.h>
 26 #include <linux/compiler.h>
 27 #include <linux/errno.h>
 28 #include <linux/kobject.h>
 29 #include <linux/atomic.h>
 30 #include <linux/device.h>
 31 #include <linux/io.h>
 32 #include <linux/resource_ext.h>
 33 #include <uapi/linux/pci.h>
 34 
 35 #include <linux/pci_ids.h>
 36 
 37 /*
 38  * The PCI interface treats multi-function devices as independent
 39  * devices.  The slot/function address of each device is encoded
 40  * in a single byte as follows:
 41  *
 42  *      7:3 = slot
 43  *      2:0 = function
 44  *
 45  * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
 46  * In the interest of not exposing interfaces to user-space unnecessarily,
 47  * the following kernel-only defines are being added here.
 48  */
 49 #define PCI_DEVID(bus, devfn)  ((((u16)(bus)) << 8) | (devfn))
 50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
 51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
 52 
 53 /* pci_slot represents a physical slot */
 54 struct pci_slot {
 55         struct pci_bus *bus;            /* The bus this slot is on */
 56         struct list_head list;          /* node in list of slots on this bus */
 57         struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
 58         unsigned char number;           /* PCI_SLOT(pci_dev->devfn) */
 59         struct kobject kobj;
 60 };
 61 
 62 static inline const char *pci_slot_name(const struct pci_slot *slot)
 63 {
 64         return kobject_name(&slot->kobj);
 65 }
 66 
 67 /* File state for mmap()s on /proc/bus/pci/X/Y */
 68 enum pci_mmap_state {
 69         pci_mmap_io,
 70         pci_mmap_mem
 71 };
 72 
 73 /*
 74  *  For PCI devices, the region numbers are assigned this way:
 75  */
 76 enum {
 77         /* #0-5: standard PCI resources */
 78         PCI_STD_RESOURCES,
 79         PCI_STD_RESOURCE_END = 5,
 80 
 81         /* #6: expansion ROM resource */
 82         PCI_ROM_RESOURCE,
 83 
 84         /* device specific resources */
 85 #ifdef CONFIG_PCI_IOV
 86         PCI_IOV_RESOURCES,
 87         PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
 88 #endif
 89 
 90         /* resources assigned to buses behind the bridge */
 91 #define PCI_BRIDGE_RESOURCE_NUM 4
 92 
 93         PCI_BRIDGE_RESOURCES,
 94         PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
 95                                   PCI_BRIDGE_RESOURCE_NUM - 1,
 96 
 97         /* total resources associated with a PCI device */
 98         PCI_NUM_RESOURCES,
 99 
100         /* preserve this for compatibility */
101         DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
102 };
103 
104 /*
105  * pci_power_t values must match the bits in the Capabilities PME_Support
106  * and Control/Status PowerState fields in the Power Management capability.
107  */
108 typedef int __bitwise pci_power_t;
109 
110 #define PCI_D0          ((pci_power_t __force) 0)
111 #define PCI_D1          ((pci_power_t __force) 1)
112 #define PCI_D2          ((pci_power_t __force) 2)
113 #define PCI_D3hot       ((pci_power_t __force) 3)
114 #define PCI_D3cold      ((pci_power_t __force) 4)
115 #define PCI_UNKNOWN     ((pci_power_t __force) 5)
116 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
117 
118 /* Remember to update this when the list above changes! */
119 extern const char *pci_power_names[];
120 
121 static inline const char *pci_power_name(pci_power_t state)
122 {
123         return pci_power_names[1 + (__force int) state];
124 }
125 
126 #define PCI_PM_D2_DELAY         200
127 #define PCI_PM_D3_WAIT          10
128 #define PCI_PM_D3COLD_WAIT      100
129 #define PCI_PM_BUS_WAIT         50
130 
131 /** The pci_channel state describes connectivity between the CPU and
132  *  the pci device.  If some PCI bus between here and the pci device
133  *  has crashed or locked up, this info is reflected here.
134  */
135 typedef unsigned int __bitwise pci_channel_state_t;
136 
137 enum pci_channel_state {
138         /* I/O channel is in normal state */
139         pci_channel_io_normal = (__force pci_channel_state_t) 1,
140 
141         /* I/O to channel is blocked */
142         pci_channel_io_frozen = (__force pci_channel_state_t) 2,
143 
144         /* PCI card is dead */
145         pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
146 };
147 
148 typedef unsigned int __bitwise pcie_reset_state_t;
149 
150 enum pcie_reset_state {
151         /* Reset is NOT asserted (Use to deassert reset) */
152         pcie_deassert_reset = (__force pcie_reset_state_t) 1,
153 
154         /* Use #PERST to reset PCIe device */
155         pcie_warm_reset = (__force pcie_reset_state_t) 2,
156 
157         /* Use PCIe Hot Reset to reset device */
158         pcie_hot_reset = (__force pcie_reset_state_t) 3
159 };
160 
161 typedef unsigned short __bitwise pci_dev_flags_t;
162 enum pci_dev_flags {
163         /* INTX_DISABLE in PCI_COMMAND register disables MSI
164          * generation too.
165          */
166         PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
167         /* Device configuration is irrevocably lost if disabled into D3 */
168         PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
169         /* Provide indication device is assigned by a Virtual Machine Manager */
170         PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
171         /* Flag for quirk use to store if quirk-specific ACS is enabled */
172         PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
173         /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
174         PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
175         /* Do not use bus resets for device */
176         PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
177         /* Do not use PM reset even if device advertises NoSoftRst- */
178         PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
179         /* Get VPD from function 0 VPD */
180         PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
181 };
182 
183 enum pci_irq_reroute_variant {
184         INTEL_IRQ_REROUTE_VARIANT = 1,
185         MAX_IRQ_REROUTE_VARIANTS = 3
186 };
187 
188 typedef unsigned short __bitwise pci_bus_flags_t;
189 enum pci_bus_flags {
190         PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
191         PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
192 };
193 
194 /* These values come from the PCI Express Spec */
195 enum pcie_link_width {
196         PCIE_LNK_WIDTH_RESRV    = 0x00,
197         PCIE_LNK_X1             = 0x01,
198         PCIE_LNK_X2             = 0x02,
199         PCIE_LNK_X4             = 0x04,
200         PCIE_LNK_X8             = 0x08,
201         PCIE_LNK_X12            = 0x0C,
202         PCIE_LNK_X16            = 0x10,
203         PCIE_LNK_X32            = 0x20,
204         PCIE_LNK_WIDTH_UNKNOWN  = 0xFF,
205 };
206 
207 /* Based on the PCI Hotplug Spec, but some values are made up by us */
208 enum pci_bus_speed {
209         PCI_SPEED_33MHz                 = 0x00,
210         PCI_SPEED_66MHz                 = 0x01,
211         PCI_SPEED_66MHz_PCIX            = 0x02,
212         PCI_SPEED_100MHz_PCIX           = 0x03,
213         PCI_SPEED_133MHz_PCIX           = 0x04,
214         PCI_SPEED_66MHz_PCIX_ECC        = 0x05,
215         PCI_SPEED_100MHz_PCIX_ECC       = 0x06,
216         PCI_SPEED_133MHz_PCIX_ECC       = 0x07,
217         PCI_SPEED_66MHz_PCIX_266        = 0x09,
218         PCI_SPEED_100MHz_PCIX_266       = 0x0a,
219         PCI_SPEED_133MHz_PCIX_266       = 0x0b,
220         AGP_UNKNOWN                     = 0x0c,
221         AGP_1X                          = 0x0d,
222         AGP_2X                          = 0x0e,
223         AGP_4X                          = 0x0f,
224         AGP_8X                          = 0x10,
225         PCI_SPEED_66MHz_PCIX_533        = 0x11,
226         PCI_SPEED_100MHz_PCIX_533       = 0x12,
227         PCI_SPEED_133MHz_PCIX_533       = 0x13,
228         PCIE_SPEED_2_5GT                = 0x14,
229         PCIE_SPEED_5_0GT                = 0x15,
230         PCIE_SPEED_8_0GT                = 0x16,
231         PCI_SPEED_UNKNOWN               = 0xff,
232 };
233 
234 struct pci_cap_saved_data {
235         u16 cap_nr;
236         bool cap_extended;
237         unsigned int size;
238         u32 data[0];
239 };
240 
241 struct pci_cap_saved_state {
242         struct hlist_node next;
243         struct pci_cap_saved_data cap;
244 };
245 
246 struct pcie_link_state;
247 struct pci_vpd;
248 struct pci_sriov;
249 struct pci_ats;
250 
251 /*
252  * The pci_dev structure is used to describe PCI devices.
253  */
254 struct pci_dev {
255         struct list_head bus_list;      /* node in per-bus list */
256         struct pci_bus  *bus;           /* bus this device is on */
257         struct pci_bus  *subordinate;   /* bus this device bridges to */
258 
259         void            *sysdata;       /* hook for sys-specific extension */
260         struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
261         struct pci_slot *slot;          /* Physical slot this device is in */
262 
263         unsigned int    devfn;          /* encoded device & function index */
264         unsigned short  vendor;
265         unsigned short  device;
266         unsigned short  subsystem_vendor;
267         unsigned short  subsystem_device;
268         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
269         u8              revision;       /* PCI revision, low byte of class word */
270         u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
271         u8              pcie_cap;       /* PCIe capability offset */
272         u8              msi_cap;        /* MSI capability offset */
273         u8              msix_cap;       /* MSI-X capability offset */
274         u8              pcie_mpss:3;    /* PCIe Max Payload Size Supported */
275         u8              rom_base_reg;   /* which config register controls the ROM */
276         u8              pin;            /* which interrupt pin this device uses */
277         u16             pcie_flags_reg; /* cached PCIe Capabilities Register */
278         unsigned long   *dma_alias_mask;/* mask of enabled devfn aliases */
279 
280         struct pci_driver *driver;      /* which driver has allocated this device */
281         u64             dma_mask;       /* Mask of the bits of bus address this
282                                            device implements.  Normally this is
283                                            0xffffffff.  You only need to change
284                                            this if your device has broken DMA
285                                            or supports 64-bit transfers.  */
286 
287         struct device_dma_parameters dma_parms;
288 
289         pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
290                                            this is D0-D3, D0 being fully functional,
291                                            and D3 being off. */
292         u8              pm_cap;         /* PM capability offset */
293         unsigned int    pme_support:5;  /* Bitmask of states from which PME#
294                                            can be generated */
295         unsigned int    pme_interrupt:1;
296         unsigned int    pme_poll:1;     /* Poll device's PME status bit */
297         unsigned int    d1_support:1;   /* Low power state D1 is supported */
298         unsigned int    d2_support:1;   /* Low power state D2 is supported */
299         unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
300         unsigned int    no_d3cold:1;    /* D3cold is forbidden */
301         unsigned int    bridge_d3:1;    /* Allow D3 for bridge */
302         unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
303         unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
304                                                    decoding during bar sizing */
305         unsigned int    wakeup_prepared:1;
306         unsigned int    runtime_d3cold:1;       /* whether go through runtime
307                                                    D3cold, not set for devices
308                                                    powered on/off by the
309                                                    corresponding bridge */
310         unsigned int    ignore_hotplug:1;       /* Ignore hotplug events */
311         unsigned int    d3_delay;       /* D3->D0 transition time in ms */
312         unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
313 
314 #ifdef CONFIG_PCIEASPM
315         struct pcie_link_state  *link_state;    /* ASPM link state */
316 #endif
317 
318         pci_channel_state_t error_state;        /* current connectivity state */
319         struct  device  dev;            /* Generic device interface */
320 
321         int             cfg_size;       /* Size of configuration space */
322 
323         /*
324          * Instead of touching interrupt line and base address registers
325          * directly, use the values stored here. They might be different!
326          */
327         unsigned int    irq;
328         struct cpumask  *irq_affinity;
329         struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
330 
331         bool match_driver;              /* Skip attaching driver */
332         /* These fields are used by common fixups */
333         unsigned int    transparent:1;  /* Subtractive decode PCI bridge */
334         unsigned int    multifunction:1;/* Part of multi-function device */
335         /* keep track of device state */
336         unsigned int    is_added:1;
337         unsigned int    is_busmaster:1; /* device is busmaster */
338         unsigned int    no_msi:1;       /* device may not use msi */
339         unsigned int    no_64bit_msi:1; /* device may only use 32-bit MSIs */
340         unsigned int    block_cfg_access:1;     /* config space access is blocked */
341         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
342         unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
343         unsigned int    msi_enabled:1;
344         unsigned int    msix_enabled:1;
345         unsigned int    ari_enabled:1;  /* ARI forwarding */
346         unsigned int    ats_enabled:1;  /* Address Translation Service */
347         unsigned int    is_managed:1;
348         unsigned int    needs_freset:1; /* Dev requires fundamental reset */
349         unsigned int    state_saved:1;
350         unsigned int    is_physfn:1;
351         unsigned int    is_virtfn:1;
352         unsigned int    reset_fn:1;
353         unsigned int    is_hotplug_bridge:1;
354         unsigned int    __aer_firmware_first_valid:1;
355         unsigned int    __aer_firmware_first:1;
356         unsigned int    broken_intx_masking:1;
357         unsigned int    io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
358         unsigned int    irq_managed:1;
359         unsigned int    has_secondary_link:1;
360         unsigned int    non_compliant_bars:1;   /* broken BARs; ignore them */
361         pci_dev_flags_t dev_flags;
362         atomic_t        enable_cnt;     /* pci_enable_device has been called */
363 
364         u32             saved_config_space[16]; /* config space saved at suspend time */
365         struct hlist_head saved_cap_space;
366         struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
367         int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
368         struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
369         struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
370 #ifdef CONFIG_PCI_MSI
371         const struct attribute_group **msi_irq_groups;
372 #endif
373         struct pci_vpd *vpd;
374 #ifdef CONFIG_PCI_ATS
375         union {
376                 struct pci_sriov *sriov;        /* SR-IOV capability related */
377                 struct pci_dev *physfn; /* the PF this VF is associated with */
378         };
379         u16             ats_cap;        /* ATS Capability offset */
380         u8              ats_stu;        /* ATS Smallest Translation Unit */
381         atomic_t        ats_ref_cnt;    /* number of VFs with ATS enabled */
382 #endif
383         phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
384         size_t romlen; /* Length of ROM if it's not from the BAR */
385         char *driver_override; /* Driver name to force a match */
386 };
387 
388 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
389 {
390 #ifdef CONFIG_PCI_IOV
391         if (dev->is_virtfn)
392                 dev = dev->physfn;
393 #endif
394         return dev;
395 }
396 
397 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
398 
399 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
400 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
401 
402 static inline int pci_channel_offline(struct pci_dev *pdev)
403 {
404         return (pdev->error_state != pci_channel_io_normal);
405 }
406 
407 struct pci_host_bridge {
408         struct device dev;
409         struct pci_bus *bus;            /* root bus */
410         struct list_head windows;       /* resource_entry */
411         void (*release_fn)(struct pci_host_bridge *);
412         void *release_data;
413         unsigned int ignore_reset_delay:1;      /* for entire hierarchy */
414         /* Resource alignment requirements */
415         resource_size_t (*align_resource)(struct pci_dev *dev,
416                         const struct resource *res,
417                         resource_size_t start,
418                         resource_size_t size,
419                         resource_size_t align);
420 };
421 
422 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
423 
424 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
425 
426 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
427                      void (*release_fn)(struct pci_host_bridge *),
428                      void *release_data);
429 
430 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
431 
432 /*
433  * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
434  * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
435  * buses below host bridges or subtractive decode bridges) go in the list.
436  * Use pci_bus_for_each_resource() to iterate through all the resources.
437  */
438 
439 /*
440  * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
441  * and there's no way to program the bridge with the details of the window.
442  * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
443  * decode bit set, because they are explicit and can be programmed with _SRS.
444  */
445 #define PCI_SUBTRACTIVE_DECODE  0x1
446 
447 struct pci_bus_resource {
448         struct list_head list;
449         struct resource *res;
450         unsigned int flags;
451 };
452 
453 #define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
454 
455 struct pci_bus {
456         struct list_head node;          /* node in list of buses */
457         struct pci_bus  *parent;        /* parent bus this bridge is on */
458         struct list_head children;      /* list of child buses */
459         struct list_head devices;       /* list of devices on this bus */
460         struct pci_dev  *self;          /* bridge device as seen by parent */
461         struct list_head slots;         /* list of slots on this bus;
462                                            protected by pci_slot_mutex */
463         struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
464         struct list_head resources;     /* address space routed to this bus */
465         struct resource busn_res;       /* bus numbers routed to this bus */
466 
467         struct pci_ops  *ops;           /* configuration access functions */
468         struct msi_controller *msi;     /* MSI controller */
469         void            *sysdata;       /* hook for sys-specific extension */
470         struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
471 
472         unsigned char   number;         /* bus number */
473         unsigned char   primary;        /* number of primary bridge */
474         unsigned char   max_bus_speed;  /* enum pci_bus_speed */
475         unsigned char   cur_bus_speed;  /* enum pci_bus_speed */
476 #ifdef CONFIG_PCI_DOMAINS_GENERIC
477         int             domain_nr;
478 #endif
479 
480         char            name[48];
481 
482         unsigned short  bridge_ctl;     /* manage NO_ISA/FBB/et al behaviors */
483         pci_bus_flags_t bus_flags;      /* inherited by child buses */
484         struct device           *bridge;
485         struct device           dev;
486         struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
487         struct bin_attribute    *legacy_mem; /* legacy mem */
488         unsigned int            is_added:1;
489 };
490 
491 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
492 
493 /*
494  * Returns true if the PCI bus is root (behind host-PCI bridge),
495  * false otherwise
496  *
497  * Some code assumes that "bus->self == NULL" means that bus is a root bus.
498  * This is incorrect because "virtual" buses added for SR-IOV (via
499  * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
500  */
501 static inline bool pci_is_root_bus(struct pci_bus *pbus)
502 {
503         return !(pbus->parent);
504 }
505 
506 /**
507  * pci_is_bridge - check if the PCI device is a bridge
508  * @dev: PCI device
509  *
510  * Return true if the PCI device is bridge whether it has subordinate
511  * or not.
512  */
513 static inline bool pci_is_bridge(struct pci_dev *dev)
514 {
515         return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
516                 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
517 }
518 
519 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
520 {
521         dev = pci_physfn(dev);
522         if (pci_is_root_bus(dev->bus))
523                 return NULL;
524 
525         return dev->bus->self;
526 }
527 
528 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
529 void pci_put_host_bridge_device(struct device *dev);
530 
531 #ifdef CONFIG_PCI_MSI
532 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
533 {
534         return pci_dev->msi_enabled || pci_dev->msix_enabled;
535 }
536 #else
537 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
538 #endif
539 
540 /*
541  * Error values that may be returned by PCI functions.
542  */
543 #define PCIBIOS_SUCCESSFUL              0x00
544 #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
545 #define PCIBIOS_BAD_VENDOR_ID           0x83
546 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
547 #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
548 #define PCIBIOS_SET_FAILED              0x88
549 #define PCIBIOS_BUFFER_TOO_SMALL        0x89
550 
551 /*
552  * Translate above to generic errno for passing back through non-PCI code.
553  */
554 static inline int pcibios_err_to_errno(int err)
555 {
556         if (err <= PCIBIOS_SUCCESSFUL)
557                 return err; /* Assume already errno */
558 
559         switch (err) {
560         case PCIBIOS_FUNC_NOT_SUPPORTED:
561                 return -ENOENT;
562         case PCIBIOS_BAD_VENDOR_ID:
563                 return -ENOTTY;
564         case PCIBIOS_DEVICE_NOT_FOUND:
565                 return -ENODEV;
566         case PCIBIOS_BAD_REGISTER_NUMBER:
567                 return -EFAULT;
568         case PCIBIOS_SET_FAILED:
569                 return -EIO;
570         case PCIBIOS_BUFFER_TOO_SMALL:
571                 return -ENOSPC;
572         }
573 
574         return -ERANGE;
575 }
576 
577 /* Low-level architecture-dependent routines */
578 
579 struct pci_ops {
580         int (*add_bus)(struct pci_bus *bus);
581         void (*remove_bus)(struct pci_bus *bus);
582         void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
583         int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
584         int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
585 };
586 
587 /*
588  * ACPI needs to be able to access PCI config space before we've done a
589  * PCI bus scan and created pci_bus structures.
590  */
591 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
592                  int reg, int len, u32 *val);
593 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
594                   int reg, int len, u32 val);
595 
596 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
597 typedef u64 pci_bus_addr_t;
598 #else
599 typedef u32 pci_bus_addr_t;
600 #endif
601 
602 struct pci_bus_region {
603         pci_bus_addr_t start;
604         pci_bus_addr_t end;
605 };
606 
607 struct pci_dynids {
608         spinlock_t lock;            /* protects list, index */
609         struct list_head list;      /* for IDs added at runtime */
610 };
611 
612 
613 /*
614  * PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
615  * a set of callbacks in struct pci_error_handlers, that device driver
616  * will be notified of PCI bus errors, and will be driven to recovery
617  * when an error occurs.
618  */
619 
620 typedef unsigned int __bitwise pci_ers_result_t;
621 
622 enum pci_ers_result {
623         /* no result/none/not supported in device driver */
624         PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
625 
626         /* Device driver can recover without slot reset */
627         PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
628 
629         /* Device driver wants slot to be reset. */
630         PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
631 
632         /* Device has completely failed, is unrecoverable */
633         PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
634 
635         /* Device driver is fully recovered and operational */
636         PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
637 
638         /* No AER capabilities registered for the driver */
639         PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
640 };
641 
642 /* PCI bus error event callbacks */
643 struct pci_error_handlers {
644         /* PCI bus error detected on this device */
645         pci_ers_result_t (*error_detected)(struct pci_dev *dev,
646                                            enum pci_channel_state error);
647 
648         /* MMIO has been re-enabled, but not DMA */
649         pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
650 
651         /* PCI Express link has been reset */
652         pci_ers_result_t (*link_reset)(struct pci_dev *dev);
653 
654         /* PCI slot has been reset */
655         pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
656 
657         /* PCI function reset prepare or completed */
658         void (*reset_notify)(struct pci_dev *dev, bool prepare);
659 
660         /* Device driver may resume normal operations */
661         void (*resume)(struct pci_dev *dev);
662 };
663 
664 
665 struct module;
666 struct pci_driver {
667         struct list_head node;
668         const char *name;
669         const struct pci_device_id *id_table;   /* must be non-NULL for probe to be called */
670         int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);   /* New device inserted */
671         void (*remove) (struct pci_dev *dev);   /* Device removed (NULL if not a hot-plug capable driver) */
672         int  (*suspend) (struct pci_dev *dev, pm_message_t state);      /* Device suspended */
673         int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);
674         int  (*resume_early) (struct pci_dev *dev);
675         int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
676         void (*shutdown) (struct pci_dev *dev);
677         int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
678         const struct pci_error_handlers *err_handler;
679         struct device_driver    driver;
680         struct pci_dynids dynids;
681 };
682 
683 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
684 
685 /**
686  * PCI_DEVICE - macro used to describe a specific pci device
687  * @vend: the 16 bit PCI Vendor ID
688  * @dev: the 16 bit PCI Device ID
689  *
690  * This macro is used to create a struct pci_device_id that matches a
691  * specific device.  The subvendor and subdevice fields will be set to
692  * PCI_ANY_ID.
693  */
694 #define PCI_DEVICE(vend,dev) \
695         .vendor = (vend), .device = (dev), \
696         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
697 
698 /**
699  * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
700  * @vend: the 16 bit PCI Vendor ID
701  * @dev: the 16 bit PCI Device ID
702  * @subvend: the 16 bit PCI Subvendor ID
703  * @subdev: the 16 bit PCI Subdevice ID
704  *
705  * This macro is used to create a struct pci_device_id that matches a
706  * specific device with subsystem information.
707  */
708 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
709         .vendor = (vend), .device = (dev), \
710         .subvendor = (subvend), .subdevice = (subdev)
711 
712 /**
713  * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
714  * @dev_class: the class, subclass, prog-if triple for this device
715  * @dev_class_mask: the class mask for this device
716  *
717  * This macro is used to create a struct pci_device_id that matches a
718  * specific PCI class.  The vendor, device, subvendor, and subdevice
719  * fields will be set to PCI_ANY_ID.
720  */
721 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
722         .class = (dev_class), .class_mask = (dev_class_mask), \
723         .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
724         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
725 
726 /**
727  * PCI_VDEVICE - macro used to describe a specific pci device in short form
728  * @vend: the vendor name
729  * @dev: the 16 bit PCI Device ID
730  *
731  * This macro is used to create a struct pci_device_id that matches a
732  * specific PCI device.  The subvendor, and subdevice fields will be set
733  * to PCI_ANY_ID. The macro allows the next field to follow as the device
734  * private data.
735  */
736 
737 #define PCI_VDEVICE(vend, dev) \
738         .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
739         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
740 
741 enum {
742         PCI_REASSIGN_ALL_RSRC   = 0x00000001,   /* ignore firmware setup */
743         PCI_REASSIGN_ALL_BUS    = 0x00000002,   /* reassign all bus numbers */
744         PCI_PROBE_ONLY          = 0x00000004,   /* use existing setup */
745         PCI_CAN_SKIP_ISA_ALIGN  = 0x00000008,   /* don't do ISA alignment */
746         PCI_ENABLE_PROC_DOMAINS = 0x00000010,   /* enable domains in /proc */
747         PCI_COMPAT_DOMAIN_0     = 0x00000020,   /* ... except domain 0 */
748         PCI_SCAN_ALL_PCIE_DEVS  = 0x00000040,   /* scan all, not just dev 0 */
749 };
750 
751 /* these external functions are only available when PCI support is enabled */
752 #ifdef CONFIG_PCI
753 
754 extern unsigned int pci_flags;
755 
756 static inline void pci_set_flags(int flags) { pci_flags = flags; }
757 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
758 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
759 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
760 
761 void pcie_bus_configure_settings(struct pci_bus *bus);
762 
763 enum pcie_bus_config_types {
764         PCIE_BUS_TUNE_OFF,      /* don't touch MPS at all */
765         PCIE_BUS_DEFAULT,       /* ensure MPS matches upstream bridge */
766         PCIE_BUS_SAFE,          /* use largest MPS boot-time devices support */
767         PCIE_BUS_PERFORMANCE,   /* use MPS and MRRS for best performance */
768         PCIE_BUS_PEER2PEER,     /* set MPS = 128 for all devices */
769 };
770 
771 extern enum pcie_bus_config_types pcie_bus_config;
772 
773 extern struct bus_type pci_bus_type;
774 
775 /* Do NOT directly access these two variables, unless you are arch-specific PCI
776  * code, or PCI core code. */
777 extern struct list_head pci_root_buses; /* list of all known PCI buses */
778 /* Some device drivers need know if PCI is initiated */
779 int no_pci_devices(void);
780 
781 void pcibios_resource_survey_bus(struct pci_bus *bus);
782 void pcibios_bus_add_device(struct pci_dev *pdev);
783 void pcibios_add_bus(struct pci_bus *bus);
784 void pcibios_remove_bus(struct pci_bus *bus);
785 void pcibios_fixup_bus(struct pci_bus *);
786 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
787 /* Architecture-specific versions may override this (weak) */
788 char *pcibios_setup(char *str);
789 
790 /* Used only when drivers/pci/setup.c is used */
791 resource_size_t pcibios_align_resource(void *, const struct resource *,
792                                 resource_size_t,
793                                 resource_size_t);
794 void pcibios_update_irq(struct pci_dev *, int irq);
795 
796 /* Weak but can be overriden by arch */
797 void pci_fixup_cardbus(struct pci_bus *);
798 
799 /* Generic PCI functions used internally */
800 
801 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
802                              struct resource *res);
803 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
804                              struct pci_bus_region *region);
805 void pcibios_scan_specific_bus(int busn);
806 struct pci_bus *pci_find_bus(int domain, int busnr);
807 void pci_bus_add_devices(const struct pci_bus *bus);
808 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
809 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
810                                     struct pci_ops *ops, void *sysdata,
811                                     struct list_head *resources);
812 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
813 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
814 void pci_bus_release_busn_res(struct pci_bus *b);
815 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
816                                       struct pci_ops *ops, void *sysdata,
817                                       struct list_head *resources,
818                                       struct msi_controller *msi);
819 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
820                                              struct pci_ops *ops, void *sysdata,
821                                              struct list_head *resources);
822 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
823                                 int busnr);
824 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
825 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
826                                  const char *name,
827                                  struct hotplug_slot *hotplug);
828 void pci_destroy_slot(struct pci_slot *slot);
829 #ifdef CONFIG_SYSFS
830 void pci_dev_assign_slot(struct pci_dev *dev);
831 #else
832 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
833 #endif
834 int pci_scan_slot(struct pci_bus *bus, int devfn);
835 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
836 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
837 unsigned int pci_scan_child_bus(struct pci_bus *bus);
838 void pci_bus_add_device(struct pci_dev *dev);
839 void pci_read_bridge_bases(struct pci_bus *child);
840 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
841                                           struct resource *res);
842 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
843 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
844 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
845 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
846 struct pci_dev *pci_dev_get(struct pci_dev *dev);
847 void pci_dev_put(struct pci_dev *dev);
848 void pci_remove_bus(struct pci_bus *b);
849 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
850 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
851 void pci_stop_root_bus(struct pci_bus *bus);
852 void pci_remove_root_bus(struct pci_bus *bus);
853 void pci_setup_cardbus(struct pci_bus *bus);
854 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
855 void pci_sort_breadthfirst(void);
856 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
857 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
858 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
859 
860 /* Generic PCI functions exported to card drivers */
861 
862 enum pci_lost_interrupt_reason {
863         PCI_LOST_IRQ_NO_INFORMATION = 0,
864         PCI_LOST_IRQ_DISABLE_MSI,
865         PCI_LOST_IRQ_DISABLE_MSIX,
866         PCI_LOST_IRQ_DISABLE_ACPI,
867 };
868 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
869 int pci_find_capability(struct pci_dev *dev, int cap);
870 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
871 int pci_find_ext_capability(struct pci_dev *dev, int cap);
872 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
873 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
874 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
875 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
876 
877 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
878                                 struct pci_dev *from);
879 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
880                                 unsigned int ss_vendor, unsigned int ss_device,
881                                 struct pci_dev *from);
882 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
883 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
884                                             unsigned int devfn);
885 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
886                                                    unsigned int devfn)
887 {
888         return pci_get_domain_bus_and_slot(0, bus, devfn);
889 }
890 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
891 int pci_dev_present(const struct pci_device_id *ids);
892 
893 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
894                              int where, u8 *val);
895 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
896                              int where, u16 *val);
897 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
898                               int where, u32 *val);
899 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
900                               int where, u8 val);
901 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
902                               int where, u16 val);
903 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
904                                int where, u32 val);
905 
906 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
907                             int where, int size, u32 *val);
908 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
909                             int where, int size, u32 val);
910 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
911                               int where, int size, u32 *val);
912 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
913                                int where, int size, u32 val);
914 
915 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
916 
917 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
918 {
919         return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
920 }
921 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
922 {
923         return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
924 }
925 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
926                                         u32 *val)
927 {
928         return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
929 }
930 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
931 {
932         return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
933 }
934 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
935 {
936         return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
937 }
938 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
939                                          u32 val)
940 {
941         return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
942 }
943 
944 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
945 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
946 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
947 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
948 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
949                                        u16 clear, u16 set);
950 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
951                                         u32 clear, u32 set);
952 
953 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
954                                            u16 set)
955 {
956         return pcie_capability_clear_and_set_word(dev, pos, 0, set);
957 }
958 
959 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
960                                             u32 set)
961 {
962         return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
963 }
964 
965 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
966                                              u16 clear)
967 {
968         return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
969 }
970 
971 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
972                                               u32 clear)
973 {
974         return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
975 }
976 
977 /* user-space driven config access */
978 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
979 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
980 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
981 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
982 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
983 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
984 
985 int __must_check pci_enable_device(struct pci_dev *dev);
986 int __must_check pci_enable_device_io(struct pci_dev *dev);
987 int __must_check pci_enable_device_mem(struct pci_dev *dev);
988 int __must_check pci_reenable_device(struct pci_dev *);
989 int __must_check pcim_enable_device(struct pci_dev *pdev);
990 void pcim_pin_device(struct pci_dev *pdev);
991 
992 static inline int pci_is_enabled(struct pci_dev *pdev)
993 {
994         return (atomic_read(&pdev->enable_cnt) > 0);
995 }
996 
997 static inline int pci_is_managed(struct pci_dev *pdev)
998 {
999         return pdev->is_managed;
1000 }
1001 
1002 void pci_disable_device(struct pci_dev *dev);
1003 
1004 extern unsigned int pcibios_max_latency;
1005 void pci_set_master(struct pci_dev *dev);
1006 void pci_clear_master(struct pci_dev *dev);
1007 
1008 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1009 int pci_set_cacheline_size(struct pci_dev *dev);
1010 #define HAVE_PCI_SET_MWI
1011 int __must_check pci_set_mwi(struct pci_dev *dev);
1012 int pci_try_set_mwi(struct pci_dev *dev);
1013 void pci_clear_mwi(struct pci_dev *dev);
1014 void pci_intx(struct pci_dev *dev, int enable);
1015 bool pci_intx_mask_supported(struct pci_dev *dev);
1016 bool pci_check_and_mask_intx(struct pci_dev *dev);
1017 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1018 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1019 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1020 int pcix_get_max_mmrbc(struct pci_dev *dev);
1021 int pcix_get_mmrbc(struct pci_dev *dev);
1022 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1023 int pcie_get_readrq(struct pci_dev *dev);
1024 int pcie_set_readrq(struct pci_dev *dev, int rq);
1025 int pcie_get_mps(struct pci_dev *dev);
1026 int pcie_set_mps(struct pci_dev *dev, int mps);
1027 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1028                           enum pcie_link_width *width);
1029 int __pci_reset_function(struct pci_dev *dev);
1030 int __pci_reset_function_locked(struct pci_dev *dev);
1031 int pci_reset_function(struct pci_dev *dev);
1032 int pci_try_reset_function(struct pci_dev *dev);
1033 int pci_probe_reset_slot(struct pci_slot *slot);
1034 int pci_reset_slot(struct pci_slot *slot);
1035 int pci_try_reset_slot(struct pci_slot *slot);
1036 int pci_probe_reset_bus(struct pci_bus *bus);
1037 int pci_reset_bus(struct pci_bus *bus);
1038 int pci_try_reset_bus(struct pci_bus *bus);
1039 void pci_reset_secondary_bus(struct pci_dev *dev);
1040 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1041 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1042 void pci_update_resource(struct pci_dev *dev, int resno);
1043 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1044 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1045 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1046 bool pci_device_is_present(struct pci_dev *pdev);
1047 void pci_ignore_hotplug(struct pci_dev *dev);
1048 
1049 /* ROM control related routines */
1050 int pci_enable_rom(struct pci_dev *pdev);
1051 void pci_disable_rom(struct pci_dev *pdev);
1052 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1053 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1054 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1055 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1056 
1057 /* Power management related routines */
1058 int pci_save_state(struct pci_dev *dev);
1059 void pci_restore_state(struct pci_dev *dev);
1060 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1061 int pci_load_saved_state(struct pci_dev *dev,
1062                          struct pci_saved_state *state);
1063 int pci_load_and_free_saved_state(struct pci_dev *dev,
1064                                   struct pci_saved_state **state);
1065 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1066 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1067                                                    u16 cap);
1068 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1069 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1070                                 u16 cap, unsigned int size);
1071 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1072 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1073 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1074 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1075 void pci_pme_active(struct pci_dev *dev, bool enable);
1076 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1077                       bool runtime, bool enable);
1078 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1079 int pci_prepare_to_sleep(struct pci_dev *dev);
1080 int pci_back_from_sleep(struct pci_dev *dev);
1081 bool pci_dev_run_wake(struct pci_dev *dev);
1082 bool pci_check_pme_status(struct pci_dev *dev);
1083 void pci_pme_wakeup_bus(struct pci_bus *bus);
1084 void pci_d3cold_enable(struct pci_dev *dev);
1085 void pci_d3cold_disable(struct pci_dev *dev);
1086 
1087 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1088                                   bool enable)
1089 {
1090         return __pci_enable_wake(dev, state, false, enable);
1091 }
1092 
1093 /* PCI Virtual Channel */
1094 int pci_save_vc_state(struct pci_dev *dev);
1095 void pci_restore_vc_state(struct pci_dev *dev);
1096 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1097 
1098 /* For use by arch with custom probe code */
1099 void set_pcie_port_type(struct pci_dev *pdev);
1100 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1101 
1102 /* Functions for PCI Hotplug drivers to use */
1103 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1104 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1105 unsigned int pci_rescan_bus(struct pci_bus *bus);
1106 void pci_lock_rescan_remove(void);
1107 void pci_unlock_rescan_remove(void);
1108 
1109 /* Vital product data routines */
1110 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1111 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1112 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1113 
1114 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1115 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1116 void pci_bus_assign_resources(const struct pci_bus *bus);
1117 void pci_bus_claim_resources(struct pci_bus *bus);
1118 void pci_bus_size_bridges(struct pci_bus *bus);
1119 int pci_claim_resource(struct pci_dev *, int);
1120 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1121 void pci_assign_unassigned_resources(void);
1122 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1123 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1124 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1125 void pdev_enable_device(struct pci_dev *);
1126 int pci_enable_resources(struct pci_dev *, int mask);
1127 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1128                     int (*)(const struct pci_dev *, u8, u8));
1129 #define HAVE_PCI_REQ_REGIONS    2
1130 int __must_check pci_request_regions(struct pci_dev *, const char *);
1131 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1132 void pci_release_regions(struct pci_dev *);
1133 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1134 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1135 void pci_release_region(struct pci_dev *, int);
1136 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1137 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1138 void pci_release_selected_regions(struct pci_dev *, int);
1139 
1140 /* drivers/pci/bus.c */
1141 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1142 void pci_bus_put(struct pci_bus *bus);
1143 void pci_add_resource(struct list_head *resources, struct resource *res);
1144 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1145                              resource_size_t offset);
1146 void pci_free_resource_list(struct list_head *resources);
1147 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1148                           unsigned int flags);
1149 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1150 void pci_bus_remove_resources(struct pci_bus *bus);
1151 int devm_request_pci_bus_resources(struct device *dev,
1152                                    struct list_head *resources);
1153 
1154 #define pci_bus_for_each_resource(bus, res, i)                          \
1155         for (i = 0;                                                     \
1156             (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1157              i++)
1158 
1159 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1160                         struct resource *res, resource_size_t size,
1161                         resource_size_t align, resource_size_t min,
1162                         unsigned long type_mask,
1163                         resource_size_t (*alignf)(void *,
1164                                                   const struct resource *,
1165                                                   resource_size_t,
1166                                                   resource_size_t),
1167                         void *alignf_data);
1168 
1169 
1170 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1171 unsigned long pci_address_to_pio(phys_addr_t addr);
1172 phys_addr_t pci_pio_to_address(unsigned long pio);
1173 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1174 void pci_unmap_iospace(struct resource *res);
1175 
1176 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1177 {
1178         struct pci_bus_region region;
1179 
1180         pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1181         return region.start;
1182 }
1183 
1184 /* Proper probing supporting hot-pluggable devices */
1185 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1186                                        const char *mod_name);
1187 
1188 /*
1189  * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1190  */
1191 #define pci_register_driver(driver)             \
1192         __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1193 
1194 void pci_unregister_driver(struct pci_driver *dev);
1195 
1196 /**
1197  * module_pci_driver() - Helper macro for registering a PCI driver
1198  * @__pci_driver: pci_driver struct
1199  *
1200  * Helper macro for PCI drivers which do not do anything special in module
1201  * init/exit. This eliminates a lot of boilerplate. Each module may only
1202  * use this macro once, and calling it replaces module_init() and module_exit()
1203  */
1204 #define module_pci_driver(__pci_driver) \
1205         module_driver(__pci_driver, pci_register_driver, \
1206                        pci_unregister_driver)
1207 
1208 /**
1209  * builtin_pci_driver() - Helper macro for registering a PCI driver
1210  * @__pci_driver: pci_driver struct
1211  *
1212  * Helper macro for PCI drivers which do not do anything special in their
1213  * init code. This eliminates a lot of boilerplate. Each driver may only
1214  * use this macro once, and calling it replaces device_initcall(...)
1215  */
1216 #define builtin_pci_driver(__pci_driver) \
1217         builtin_driver(__pci_driver, pci_register_driver)
1218 
1219 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1220 int pci_add_dynid(struct pci_driver *drv,
1221                   unsigned int vendor, unsigned int device,
1222                   unsigned int subvendor, unsigned int subdevice,
1223                   unsigned int class, unsigned int class_mask,
1224                   unsigned long driver_data);
1225 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1226                                          struct pci_dev *dev);
1227 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1228                     int pass);
1229 
1230 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1231                   void *userdata);
1232 int pci_cfg_space_size(struct pci_dev *dev);
1233 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1234 void pci_setup_bridge(struct pci_bus *bus);
1235 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1236                                          unsigned long type);
1237 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1238 
1239 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1240 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1241 
1242 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1243                       unsigned int command_bits, u32 flags);
1244 
1245 #define PCI_IRQ_LEGACY          (1 << 0) /* allow legacy interrupts */
1246 #define PCI_IRQ_MSI             (1 << 1) /* allow MSI interrupts */
1247 #define PCI_IRQ_MSIX            (1 << 2) /* allow MSI-X interrupts */
1248 #define PCI_IRQ_AFFINITY        (1 << 3) /* auto-assign affinity */
1249 #define PCI_IRQ_ALL_TYPES \
1250         (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1251 
1252 /* kmem_cache style wrapper around pci_alloc_consistent() */
1253 
1254 #include <linux/pci-dma.h>
1255 #include <linux/dmapool.h>
1256 
1257 #define pci_pool dma_pool
1258 #define pci_pool_create(name, pdev, size, align, allocation) \
1259                 dma_pool_create(name, &pdev->dev, size, align, allocation)
1260 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1261 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1262 #define pci_pool_zalloc(pool, flags, handle) \
1263                 dma_pool_zalloc(pool, flags, handle)
1264 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1265 
1266 struct msix_entry {
1267         u32     vector; /* kernel uses to write allocated vector */
1268         u16     entry;  /* driver uses to specify entry, OS writes */
1269 };
1270 
1271 #ifdef CONFIG_PCI_MSI
1272 int pci_msi_vec_count(struct pci_dev *dev);
1273 void pci_msi_shutdown(struct pci_dev *dev);
1274 void pci_disable_msi(struct pci_dev *dev);
1275 int pci_msix_vec_count(struct pci_dev *dev);
1276 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1277 void pci_msix_shutdown(struct pci_dev *dev);
1278 void pci_disable_msix(struct pci_dev *dev);
1279 void pci_restore_msi_state(struct pci_dev *dev);
1280 int pci_msi_enabled(void);
1281 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1282 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1283 {
1284         int rc = pci_enable_msi_range(dev, nvec, nvec);
1285         if (rc < 0)
1286                 return rc;
1287         return 0;
1288 }
1289 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1290                           int minvec, int maxvec);
1291 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1292                                         struct msix_entry *entries, int nvec)
1293 {
1294         int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1295         if (rc < 0)
1296                 return rc;
1297         return 0;
1298 }
1299 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1300                 unsigned int max_vecs, unsigned int flags);
1301 void pci_free_irq_vectors(struct pci_dev *dev);
1302 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1303 
1304 #else
1305 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1306 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1307 static inline void pci_disable_msi(struct pci_dev *dev) { }
1308 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1309 static inline int pci_enable_msix(struct pci_dev *dev,
1310                                   struct msix_entry *entries, int nvec)
1311 { return -ENOSYS; }
1312 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1313 static inline void pci_disable_msix(struct pci_dev *dev) { }
1314 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1315 static inline int pci_msi_enabled(void) { return 0; }
1316 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1317                                        int maxvec)
1318 { return -ENOSYS; }
1319 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1320 { return -ENOSYS; }
1321 static inline int pci_enable_msix_range(struct pci_dev *dev,
1322                       struct msix_entry *entries, int minvec, int maxvec)
1323 { return -ENOSYS; }
1324 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1325                       struct msix_entry *entries, int nvec)
1326 { return -ENOSYS; }
1327 static inline int pci_alloc_irq_vectors(struct pci_dev *dev,
1328                 unsigned int min_vecs, unsigned int max_vecs,
1329                 unsigned int flags)
1330 {
1331         if (min_vecs > 1)
1332                 return -EINVAL;
1333         return 1;
1334 }
1335 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1336 {
1337 }
1338 
1339 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1340 {
1341         if (WARN_ON_ONCE(nr > 0))
1342                 return -EINVAL;
1343         return dev->irq;
1344 }
1345 #endif
1346 
1347 #ifdef CONFIG_PCIEPORTBUS
1348 extern bool pcie_ports_disabled;
1349 extern bool pcie_ports_auto;
1350 #else
1351 #define pcie_ports_disabled     true
1352 #define pcie_ports_auto         false
1353 #endif
1354 
1355 #ifdef CONFIG_PCIEASPM
1356 bool pcie_aspm_support_enabled(void);
1357 #else
1358 static inline bool pcie_aspm_support_enabled(void) { return false; }
1359 #endif
1360 
1361 #ifdef CONFIG_PCIEAER
1362 void pci_no_aer(void);
1363 bool pci_aer_available(void);
1364 #else
1365 static inline void pci_no_aer(void) { }
1366 static inline bool pci_aer_available(void) { return false; }
1367 #endif
1368 
1369 #ifdef CONFIG_PCIE_ECRC
1370 void pcie_set_ecrc_checking(struct pci_dev *dev);
1371 void pcie_ecrc_get_policy(char *str);
1372 #else
1373 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1374 static inline void pcie_ecrc_get_policy(char *str) { }
1375 #endif
1376 
1377 #define pci_enable_msi(pdev)    pci_enable_msi_exact(pdev, 1)
1378 
1379 #ifdef CONFIG_HT_IRQ
1380 /* The functions a driver should call */
1381 int  ht_create_irq(struct pci_dev *dev, int idx);
1382 void ht_destroy_irq(unsigned int irq);
1383 #endif /* CONFIG_HT_IRQ */
1384 
1385 #ifdef CONFIG_PCI_ATS
1386 /* Address Translation Service */
1387 void pci_ats_init(struct pci_dev *dev);
1388 int pci_enable_ats(struct pci_dev *dev, int ps);
1389 void pci_disable_ats(struct pci_dev *dev);
1390 int pci_ats_queue_depth(struct pci_dev *dev);
1391 #else
1392 static inline void pci_ats_init(struct pci_dev *d) { }
1393 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1394 static inline void pci_disable_ats(struct pci_dev *d) { }
1395 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1396 #endif
1397 
1398 void pci_cfg_access_lock(struct pci_dev *dev);
1399 bool pci_cfg_access_trylock(struct pci_dev *dev);
1400 void pci_cfg_access_unlock(struct pci_dev *dev);
1401 
1402 /*
1403  * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
1404  * a PCI domain is defined to be a set of PCI buses which share
1405  * configuration space.
1406  */
1407 #ifdef CONFIG_PCI_DOMAINS
1408 extern int pci_domains_supported;
1409 int pci_get_new_domain_nr(void);
1410 #else
1411 enum { pci_domains_supported = 0 };
1412 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1413 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1414 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1415 #endif /* CONFIG_PCI_DOMAINS */
1416 
1417 /*
1418  * Generic implementation for PCI domain support. If your
1419  * architecture does not need custom management of PCI
1420  * domains then this implementation will be used
1421  */
1422 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1423 static inline int pci_domain_nr(struct pci_bus *bus)
1424 {
1425         return bus->domain_nr;
1426 }
1427 #ifdef CONFIG_ACPI
1428 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1429 #else
1430 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1431 { return 0; }
1432 #endif
1433 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1434 #endif
1435 
1436 /* some architectures require additional setup to direct VGA traffic */
1437 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1438                       unsigned int command_bits, u32 flags);
1439 void pci_register_set_vga_state(arch_set_vga_state_t func);
1440 
1441 static inline int
1442 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1443 {
1444         return pci_request_selected_regions(pdev,
1445                             pci_select_bars(pdev, IORESOURCE_IO), name);
1446 }
1447 
1448 static inline void
1449 pci_release_io_regions(struct pci_dev *pdev)
1450 {
1451         return pci_release_selected_regions(pdev,
1452                             pci_select_bars(pdev, IORESOURCE_IO));
1453 }
1454 
1455 static inline int
1456 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1457 {
1458         return pci_request_selected_regions(pdev,
1459                             pci_select_bars(pdev, IORESOURCE_MEM), name);
1460 }
1461 
1462 static inline void
1463 pci_release_mem_regions(struct pci_dev *pdev)
1464 {
1465         return pci_release_selected_regions(pdev,
1466                             pci_select_bars(pdev, IORESOURCE_MEM));
1467 }
1468 
1469 #else /* CONFIG_PCI is not enabled */
1470 
1471 static inline void pci_set_flags(int flags) { }
1472 static inline void pci_add_flags(int flags) { }
1473 static inline void pci_clear_flags(int flags) { }
1474 static inline int pci_has_flag(int flag) { return 0; }
1475 
1476 /*
1477  *  If the system does not have PCI, clearly these return errors.  Define
1478  *  these as simple inline functions to avoid hair in drivers.
1479  */
1480 
1481 #define _PCI_NOP(o, s, t) \
1482         static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1483                                                 int where, t val) \
1484                 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1485 
1486 #define _PCI_NOP_ALL(o, x)      _PCI_NOP(o, byte, u8 x) \
1487                                 _PCI_NOP(o, word, u16 x) \
1488                                 _PCI_NOP(o, dword, u32 x)
1489 _PCI_NOP_ALL(read, *)
1490 _PCI_NOP_ALL(write,)
1491 
1492 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1493                                              unsigned int device,
1494                                              struct pci_dev *from)
1495 { return NULL; }
1496 
1497 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1498                                              unsigned int device,
1499                                              unsigned int ss_vendor,
1500                                              unsigned int ss_device,
1501                                              struct pci_dev *from)
1502 { return NULL; }
1503 
1504 static inline struct pci_dev *pci_get_class(unsigned int class,
1505                                             struct pci_dev *from)
1506 { return NULL; }
1507 
1508 #define pci_dev_present(ids)    (0)
1509 #define no_pci_devices()        (1)
1510 #define pci_dev_put(dev)        do { } while (0)
1511 
1512 static inline void pci_set_master(struct pci_dev *dev) { }
1513 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1514 static inline void pci_disable_device(struct pci_dev *dev) { }
1515 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1516 { return -EBUSY; }
1517 static inline int __pci_register_driver(struct pci_driver *drv,
1518                                         struct module *owner)
1519 { return 0; }
1520 static inline int pci_register_driver(struct pci_driver *drv)
1521 { return 0; }
1522 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1523 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1524 { return 0; }
1525 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1526                                            int cap)
1527 { return 0; }
1528 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1529 { return 0; }
1530 
1531 /* Power management related routines */
1532 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1533 static inline void pci_restore_state(struct pci_dev *dev) { }
1534 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1535 { return 0; }
1536 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1537 { return 0; }
1538 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1539                                            pm_message_t state)
1540 { return PCI_D0; }
1541 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1542                                   int enable)
1543 { return 0; }
1544 
1545 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1546 { return -EIO; }
1547 static inline void pci_release_regions(struct pci_dev *dev) { }
1548 
1549 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1550 
1551 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1552 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1553 { return 0; }
1554 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1555 
1556 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1557 { return NULL; }
1558 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1559                                                 unsigned int devfn)
1560 { return NULL; }
1561 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1562                                                 unsigned int devfn)
1563 { return NULL; }
1564 
1565 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1566 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1567 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1568 
1569 #define dev_is_pci(d) (false)
1570 #define dev_is_pf(d) (false)
1571 #define dev_num_vf(d) (0)
1572 #endif /* CONFIG_PCI */
1573 
1574 /* Include architecture-dependent settings and functions */
1575 
1576 #include <asm/pci.h>
1577 
1578 #ifndef pci_root_bus_fwnode
1579 #define pci_root_bus_fwnode(bus)        NULL
1580 #endif
1581 
1582 /* these helpers provide future and backwards compatibility
1583  * for accessing popular PCI BAR info */
1584 #define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
1585 #define pci_resource_end(dev, bar)      ((dev)->resource[(bar)].end)
1586 #define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)
1587 #define pci_resource_len(dev,bar) \
1588         ((pci_resource_start((dev), (bar)) == 0 &&      \
1589           pci_resource_end((dev), (bar)) ==             \
1590           pci_resource_start((dev), (bar))) ? 0 :       \
1591                                                         \
1592          (pci_resource_end((dev), (bar)) -              \
1593           pci_resource_start((dev), (bar)) + 1))
1594 
1595 /* Similar to the helpers above, these manipulate per-pci_dev
1596  * driver-specific data.  They are really just a wrapper around
1597  * the generic device structure functions of these calls.
1598  */
1599 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1600 {
1601         return dev_get_drvdata(&pdev->dev);
1602 }
1603 
1604 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1605 {
1606         dev_set_drvdata(&pdev->dev, data);
1607 }
1608 
1609 /* If you want to know what to call your pci_dev, ask this function.
1610  * Again, it's a wrapper around the generic device.
1611  */
1612 static inline const char *pci_name(const struct pci_dev *pdev)
1613 {
1614         return dev_name(&pdev->dev);
1615 }
1616 
1617 
1618 /* Some archs don't want to expose struct resource to userland as-is
1619  * in sysfs and /proc
1620  */
1621 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1622 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1623                           const struct resource *rsrc,
1624                           resource_size_t *start, resource_size_t *end);
1625 #else
1626 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1627                 const struct resource *rsrc, resource_size_t *start,
1628                 resource_size_t *end)
1629 {
1630         *start = rsrc->start;
1631         *end = rsrc->end;
1632 }
1633 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1634 
1635 
1636 /*
1637  *  The world is not perfect and supplies us with broken PCI devices.
1638  *  For at least a part of these bugs we need a work-around, so both
1639  *  generic (drivers/pci/quirks.c) and per-architecture code can define
1640  *  fixup hooks to be called for particular buggy devices.
1641  */
1642 
1643 struct pci_fixup {
1644         u16 vendor;             /* You can use PCI_ANY_ID here of course */
1645         u16 device;             /* You can use PCI_ANY_ID here of course */
1646         u32 class;              /* You can use PCI_ANY_ID here too */
1647         unsigned int class_shift;       /* should be 0, 8, 16 */
1648         void (*hook)(struct pci_dev *dev);
1649 };
1650 
1651 enum pci_fixup_pass {
1652         pci_fixup_early,        /* Before probing BARs */
1653         pci_fixup_header,       /* After reading configuration header */
1654         pci_fixup_final,        /* Final phase of device fixups */
1655         pci_fixup_enable,       /* pci_enable_device() time */
1656         pci_fixup_resume,       /* pci_device_resume() */
1657         pci_fixup_suspend,      /* pci_device_suspend() */
1658         pci_fixup_resume_early, /* pci_device_resume_early() */
1659         pci_fixup_suspend_late, /* pci_device_suspend_late() */
1660 };
1661 
1662 /* Anonymous variables would be nice... */
1663 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1664                                   class_shift, hook)                    \
1665         static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used       \
1666         __attribute__((__section__(#section), aligned((sizeof(void *)))))    \
1667                 = { vendor, device, class, class_shift, hook };
1668 
1669 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,            \
1670                                          class_shift, hook)             \
1671         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1672                 hook, vendor, device, class, class_shift, hook)
1673 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,           \
1674                                          class_shift, hook)             \
1675         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1676                 hook, vendor, device, class, class_shift, hook)
1677 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,            \
1678                                          class_shift, hook)             \
1679         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1680                 hook, vendor, device, class, class_shift, hook)
1681 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,           \
1682                                          class_shift, hook)             \
1683         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1684                 hook, vendor, device, class, class_shift, hook)
1685 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,           \
1686                                          class_shift, hook)             \
1687         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1688                 resume##hook, vendor, device, class,    \
1689                 class_shift, hook)
1690 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,     \
1691                                          class_shift, hook)             \
1692         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1693                 resume_early##hook, vendor, device,     \
1694                 class, class_shift, hook)
1695 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,          \
1696                                          class_shift, hook)             \
1697         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1698                 suspend##hook, vendor, device, class,   \
1699                 class_shift, hook)
1700 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class,     \
1701                                          class_shift, hook)             \
1702         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,              \
1703                 suspend_late##hook, vendor, device,     \
1704                 class, class_shift, hook)
1705 
1706 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
1707         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
1708                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1709 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)                  \
1710         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,                    \
1711                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1712 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)                   \
1713         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,                     \
1714                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1715 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)                  \
1716         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,                    \
1717                 hook, vendor, device, PCI_ANY_ID, 0, hook)
1718 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
1719         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
1720                 resume##hook, vendor, device,           \
1721                 PCI_ANY_ID, 0, hook)
1722 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
1723         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
1724                 resume_early##hook, vendor, device,     \
1725                 PCI_ANY_ID, 0, hook)
1726 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
1727         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
1728                 suspend##hook, vendor, device,          \
1729                 PCI_ANY_ID, 0, hook)
1730 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook)            \
1731         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,              \
1732                 suspend_late##hook, vendor, device,     \
1733                 PCI_ANY_ID, 0, hook)
1734 
1735 #ifdef CONFIG_PCI_QUIRKS
1736 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1737 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1738 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1739 #else
1740 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1741                                     struct pci_dev *dev) { }
1742 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1743                                                u16 acs_flags)
1744 {
1745         return -ENOTTY;
1746 }
1747 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1748 {
1749         return -ENOTTY;
1750 }
1751 #endif
1752 
1753 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1754 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1755 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1756 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1757 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1758                                    const char *name);
1759 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1760 
1761 extern int pci_pci_problems;
1762 #define PCIPCI_FAIL             1       /* No PCI PCI DMA */
1763 #define PCIPCI_TRITON           2
1764 #define PCIPCI_NATOMA           4
1765 #define PCIPCI_VIAETBF          8
1766 #define PCIPCI_VSFX             16
1767 #define PCIPCI_ALIMAGIK         32      /* Need low latency setting */
1768 #define PCIAGP_FAIL             64      /* No PCI to AGP DMA */
1769 
1770 extern unsigned long pci_cardbus_io_size;
1771 extern unsigned long pci_cardbus_mem_size;
1772 extern u8 pci_dfl_cache_line_size;
1773 extern u8 pci_cache_line_size;
1774 
1775 extern unsigned long pci_hotplug_io_size;
1776 extern unsigned long pci_hotplug_mem_size;
1777 extern unsigned long pci_hotplug_bus_size;
1778 
1779 /* Architecture-specific versions may override these (weak) */
1780 void pcibios_disable_device(struct pci_dev *dev);
1781 void pcibios_set_master(struct pci_dev *dev);
1782 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1783                                  enum pcie_reset_state state);
1784 int pcibios_add_device(struct pci_dev *dev);
1785 void pcibios_release_device(struct pci_dev *dev);
1786 void pcibios_penalize_isa_irq(int irq, int active);
1787 int pcibios_alloc_irq(struct pci_dev *dev);
1788 void pcibios_free_irq(struct pci_dev *dev);
1789 
1790 #ifdef CONFIG_HIBERNATE_CALLBACKS
1791 extern struct dev_pm_ops pcibios_pm_ops;
1792 #endif
1793 
1794 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1795 void __init pci_mmcfg_early_init(void);
1796 void __init pci_mmcfg_late_init(void);
1797 #else
1798 static inline void pci_mmcfg_early_init(void) { }
1799 static inline void pci_mmcfg_late_init(void) { }
1800 #endif
1801 
1802 int pci_ext_cfg_avail(void);
1803 
1804 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1805 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1806 
1807 #ifdef CONFIG_PCI_IOV
1808 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1809 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1810 
1811 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1812 void pci_disable_sriov(struct pci_dev *dev);
1813 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1814 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1815 int pci_num_vf(struct pci_dev *dev);
1816 int pci_vfs_assigned(struct pci_dev *dev);
1817 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1818 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1819 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1820 #else
1821 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1822 {
1823         return -ENOSYS;
1824 }
1825 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1826 {
1827         return -ENOSYS;
1828 }
1829 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1830 { return -ENODEV; }
1831 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1832 {
1833         return -ENOSYS;
1834 }
1835 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1836                                          int id, int reset) { }
1837 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1838 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1839 static inline int pci_vfs_assigned(struct pci_dev *dev)
1840 { return 0; }
1841 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1842 { return 0; }
1843 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1844 { return 0; }
1845 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1846 { return 0; }
1847 #endif
1848 
1849 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1850 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1851 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1852 #endif
1853 
1854 /**
1855  * pci_pcie_cap - get the saved PCIe capability offset
1856  * @dev: PCI device
1857  *
1858  * PCIe capability offset is calculated at PCI device initialization
1859  * time and saved in the data structure. This function returns saved
1860  * PCIe capability offset. Using this instead of pci_find_capability()
1861  * reduces unnecessary search in the PCI configuration space. If you
1862  * need to calculate PCIe capability offset from raw device for some
1863  * reasons, please use pci_find_capability() instead.
1864  */
1865 static inline int pci_pcie_cap(struct pci_dev *dev)
1866 {
1867         return dev->pcie_cap;
1868 }
1869 
1870 /**
1871  * pci_is_pcie - check if the PCI device is PCI Express capable
1872  * @dev: PCI device
1873  *
1874  * Returns: true if the PCI device is PCI Express capable, false otherwise.
1875  */
1876 static inline bool pci_is_pcie(struct pci_dev *dev)
1877 {
1878         return pci_pcie_cap(dev);
1879 }
1880 
1881 /**
1882  * pcie_caps_reg - get the PCIe Capabilities Register
1883  * @dev: PCI device
1884  */
1885 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1886 {
1887         return dev->pcie_flags_reg;
1888 }
1889 
1890 /**
1891  * pci_pcie_type - get the PCIe device/port type
1892  * @dev: PCI device
1893  */
1894 static inline int pci_pcie_type(const struct pci_dev *dev)
1895 {
1896         return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1897 }
1898 
1899 void pci_request_acs(void);
1900 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1901 bool pci_acs_path_enabled(struct pci_dev *start,
1902                           struct pci_dev *end, u16 acs_flags);
1903 
1904 #define PCI_VPD_LRDT                    0x80    /* Large Resource Data Type */
1905 #define PCI_VPD_LRDT_ID(x)              ((x) | PCI_VPD_LRDT)
1906 
1907 /* Large Resource Data Type Tag Item Names */
1908 #define PCI_VPD_LTIN_ID_STRING          0x02    /* Identifier String */
1909 #define PCI_VPD_LTIN_RO_DATA            0x10    /* Read-Only Data */
1910 #define PCI_VPD_LTIN_RW_DATA            0x11    /* Read-Write Data */
1911 
1912 #define PCI_VPD_LRDT_ID_STRING          PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1913 #define PCI_VPD_LRDT_RO_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1914 #define PCI_VPD_LRDT_RW_DATA            PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1915 
1916 /* Small Resource Data Type Tag Item Names */
1917 #define PCI_VPD_STIN_END                0x0f    /* End */
1918 
1919 #define PCI_VPD_SRDT_END                (PCI_VPD_STIN_END << 3)
1920 
1921 #define PCI_VPD_SRDT_TIN_MASK           0x78
1922 #define PCI_VPD_SRDT_LEN_MASK           0x07
1923 #define PCI_VPD_LRDT_TIN_MASK           0x7f
1924 
1925 #define PCI_VPD_LRDT_TAG_SIZE           3
1926 #define PCI_VPD_SRDT_TAG_SIZE           1
1927 
1928 #define PCI_VPD_INFO_FLD_HDR_SIZE       3
1929 
1930 #define PCI_VPD_RO_KEYWORD_PARTNO       "PN"
1931 #define PCI_VPD_RO_KEYWORD_MFR_ID       "MN"
1932 #define PCI_VPD_RO_KEYWORD_VENDOR0      "V0"
1933 #define PCI_VPD_RO_KEYWORD_CHKSUM       "RV"
1934 
1935 /**
1936  * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1937  * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1938  *
1939  * Returns the extracted Large Resource Data Type length.
1940  */
1941 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1942 {
1943         return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1944 }
1945 
1946 /**
1947  * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
1948  * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1949  *
1950  * Returns the extracted Large Resource Data Type Tag item.
1951  */
1952 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
1953 {
1954     return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
1955 }
1956 
1957 /**
1958  * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1959  * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1960  *
1961  * Returns the extracted Small Resource Data Type length.
1962  */
1963 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1964 {
1965         return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1966 }
1967 
1968 /**
1969  * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
1970  * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1971  *
1972  * Returns the extracted Small Resource Data Type Tag Item.
1973  */
1974 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
1975 {
1976         return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
1977 }
1978 
1979 /**
1980  * pci_vpd_info_field_size - Extracts the information field length
1981  * @lrdt: Pointer to the beginning of an information field header
1982  *
1983  * Returns the extracted information field length.
1984  */
1985 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1986 {
1987         return info_field[2];
1988 }
1989 
1990 /**
1991  * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1992  * @buf: Pointer to buffered vpd data
1993  * @off: The offset into the buffer at which to begin the search
1994  * @len: The length of the vpd buffer
1995  * @rdt: The Resource Data Type to search for
1996  *
1997  * Returns the index where the Resource Data Type was found or
1998  * -ENOENT otherwise.
1999  */
2000 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2001 
2002 /**
2003  * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2004  * @buf: Pointer to buffered vpd data
2005  * @off: The offset into the buffer at which to begin the search
2006  * @len: The length of the buffer area, relative to off, in which to search
2007  * @kw: The keyword to search for
2008  *
2009  * Returns the index where the information field keyword was found or
2010  * -ENOENT otherwise.
2011  */
2012 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2013                               unsigned int len, const char *kw);
2014 
2015 /* PCI <-> OF binding helpers */
2016 #ifdef CONFIG_OF
2017 struct device_node;
2018 struct irq_domain;
2019 void pci_set_of_node(struct pci_dev *dev);
2020 void pci_release_of_node(struct pci_dev *dev);
2021 void pci_set_bus_of_node(struct pci_bus *bus);
2022 void pci_release_bus_of_node(struct pci_bus *bus);
2023 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2024 
2025 /* Arch may override this (weak) */
2026 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2027 
2028 static inline struct device_node *
2029 pci_device_to_OF_node(const struct pci_dev *pdev)
2030 {
2031         return pdev ? pdev->dev.of_node : NULL;
2032 }
2033 
2034 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2035 {
2036         return bus ? bus->dev.of_node : NULL;
2037 }
2038 
2039 #else /* CONFIG_OF */
2040 static inline void pci_set_of_node(struct pci_dev *dev) { }
2041 static inline void pci_release_of_node(struct pci_dev *dev) { }
2042 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2043 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2044 static inline struct device_node *
2045 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2046 static inline struct irq_domain *
2047 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2048 #endif  /* CONFIG_OF */
2049 
2050 #ifdef CONFIG_ACPI
2051 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2052 
2053 void
2054 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2055 #else
2056 static inline struct irq_domain *
2057 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2058 #endif
2059 
2060 #ifdef CONFIG_EEH
2061 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2062 {
2063         return pdev->dev.archdata.edev;
2064 }
2065 #endif
2066 
2067 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2068 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2069 int pci_for_each_dma_alias(struct pci_dev *pdev,
2070                            int (*fn)(struct pci_dev *pdev,
2071                                      u16 alias, void *data), void *data);
2072 
2073 /* helper functions for operation of device flag */
2074 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2075 {
2076         pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2077 }
2078 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2079 {
2080         pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2081 }
2082 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2083 {
2084         return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2085 }
2086 
2087 /**
2088  * pci_ari_enabled - query ARI forwarding status
2089  * @bus: the PCI bus
2090  *
2091  * Returns true if ARI forwarding is enabled.
2092  */
2093 static inline bool pci_ari_enabled(struct pci_bus *bus)
2094 {
2095         return bus->self && bus->self->ari_enabled;
2096 }
2097 
2098 /* provide the legacy pci_dma_* API */
2099 #include <linux/pci-dma-compat.h>
2100 
2101 #endif /* LINUX_PCI_H */
2102 

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