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Linux/drivers/watchdog/pnx4008_wdt.c

  1 /*
  2  * drivers/char/watchdog/pnx4008_wdt.c
  3  *
  4  * Watchdog driver for PNX4008 board
  5  *
  6  * Authors: Dmitry Chigirev <source@mvista.com>,
  7  *          Vitaly Wool <vitalywool@gmail.com>
  8  * Based on sa1100 driver,
  9  * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
 10  *
 11  * 2005-2006 (c) MontaVista Software, Inc.
 12  *
 13  * (C) 2012 Wolfram Sang, Pengutronix
 14  *
 15  * This file is licensed under the terms of the GNU General Public License
 16  * version 2. This program is licensed "as is" without any warranty of any
 17  * kind, whether express or implied.
 18  */
 19 
 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 21 
 22 #include <linux/module.h>
 23 #include <linux/moduleparam.h>
 24 #include <linux/types.h>
 25 #include <linux/kernel.h>
 26 #include <linux/watchdog.h>
 27 #include <linux/init.h>
 28 #include <linux/platform_device.h>
 29 #include <linux/clk.h>
 30 #include <linux/spinlock.h>
 31 #include <linux/io.h>
 32 #include <linux/slab.h>
 33 #include <linux/err.h>
 34 #include <linux/of.h>
 35 #include <mach/hardware.h>
 36 
 37 /* WatchDog Timer - Chapter 23 Page 207 */
 38 
 39 #define DEFAULT_HEARTBEAT 19
 40 #define MAX_HEARTBEAT     60
 41 
 42 /* Watchdog timer register set definition */
 43 #define WDTIM_INT(p)     ((p) + 0x0)
 44 #define WDTIM_CTRL(p)    ((p) + 0x4)
 45 #define WDTIM_COUNTER(p) ((p) + 0x8)
 46 #define WDTIM_MCTRL(p)   ((p) + 0xC)
 47 #define WDTIM_MATCH0(p)  ((p) + 0x10)
 48 #define WDTIM_EMR(p)     ((p) + 0x14)
 49 #define WDTIM_PULSE(p)   ((p) + 0x18)
 50 #define WDTIM_RES(p)     ((p) + 0x1C)
 51 
 52 /* WDTIM_INT bit definitions */
 53 #define MATCH_INT      1
 54 
 55 /* WDTIM_CTRL bit definitions */
 56 #define COUNT_ENAB     1
 57 #define RESET_COUNT    (1 << 1)
 58 #define DEBUG_EN       (1 << 2)
 59 
 60 /* WDTIM_MCTRL bit definitions */
 61 #define MR0_INT        1
 62 #undef  RESET_COUNT0
 63 #define RESET_COUNT0   (1 << 2)
 64 #define STOP_COUNT0    (1 << 2)
 65 #define M_RES1         (1 << 3)
 66 #define M_RES2         (1 << 4)
 67 #define RESFRC1        (1 << 5)
 68 #define RESFRC2        (1 << 6)
 69 
 70 /* WDTIM_EMR bit definitions */
 71 #define EXT_MATCH0      1
 72 #define MATCH_OUTPUT_HIGH (2 << 4)      /*a MATCH_CTRL setting */
 73 
 74 /* WDTIM_RES bit definitions */
 75 #define WDOG_RESET      1       /* read only */
 76 
 77 #define WDOG_COUNTER_RATE 13000000      /*the counter clock is 13 MHz fixed */
 78 
 79 static bool nowayout = WATCHDOG_NOWAYOUT;
 80 static unsigned int heartbeat = DEFAULT_HEARTBEAT;
 81 
 82 static DEFINE_SPINLOCK(io_lock);
 83 static void __iomem     *wdt_base;
 84 struct clk              *wdt_clk;
 85 
 86 static int pnx4008_wdt_start(struct watchdog_device *wdd)
 87 {
 88         spin_lock(&io_lock);
 89 
 90         /* stop counter, initiate counter reset */
 91         writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
 92         /*wait for reset to complete. 100% guarantee event */
 93         while (readl(WDTIM_COUNTER(wdt_base)))
 94                 cpu_relax();
 95         /* internal and external reset, stop after that */
 96         writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base));
 97         /* configure match output */
 98         writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
 99         /* clear interrupt, just in case */
100         writel(MATCH_INT, WDTIM_INT(wdt_base));
101         /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
102         writel(0xFFFF, WDTIM_PULSE(wdt_base));
103         writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
104         /*enable counter, stop when debugger active */
105         writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
106 
107         spin_unlock(&io_lock);
108         return 0;
109 }
110 
111 static int pnx4008_wdt_stop(struct watchdog_device *wdd)
112 {
113         spin_lock(&io_lock);
114 
115         writel(0, WDTIM_CTRL(wdt_base));        /*stop counter */
116 
117         spin_unlock(&io_lock);
118         return 0;
119 }
120 
121 static int pnx4008_wdt_set_timeout(struct watchdog_device *wdd,
122                                     unsigned int new_timeout)
123 {
124         wdd->timeout = new_timeout;
125         return 0;
126 }
127 
128 static const struct watchdog_info pnx4008_wdt_ident = {
129         .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
130             WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
131         .identity = "PNX4008 Watchdog",
132 };
133 
134 static const struct watchdog_ops pnx4008_wdt_ops = {
135         .owner = THIS_MODULE,
136         .start = pnx4008_wdt_start,
137         .stop = pnx4008_wdt_stop,
138         .set_timeout = pnx4008_wdt_set_timeout,
139 };
140 
141 static struct watchdog_device pnx4008_wdd = {
142         .info = &pnx4008_wdt_ident,
143         .ops = &pnx4008_wdt_ops,
144         .timeout = DEFAULT_HEARTBEAT,
145         .min_timeout = 1,
146         .max_timeout = MAX_HEARTBEAT,
147 };
148 
149 static int pnx4008_wdt_probe(struct platform_device *pdev)
150 {
151         struct resource *r;
152         int ret = 0;
153 
154         watchdog_init_timeout(&pnx4008_wdd, heartbeat, &pdev->dev);
155 
156         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
157         wdt_base = devm_ioremap_resource(&pdev->dev, r);
158         if (IS_ERR(wdt_base))
159                 return PTR_ERR(wdt_base);
160 
161         wdt_clk = devm_clk_get(&pdev->dev, NULL);
162         if (IS_ERR(wdt_clk))
163                 return PTR_ERR(wdt_clk);
164 
165         ret = clk_enable(wdt_clk);
166         if (ret)
167                 return ret;
168 
169         pnx4008_wdd.bootstatus = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
170                         WDIOF_CARDRESET : 0;
171         watchdog_set_nowayout(&pnx4008_wdd, nowayout);
172 
173         pnx4008_wdt_stop(&pnx4008_wdd); /* disable for now */
174 
175         ret = watchdog_register_device(&pnx4008_wdd);
176         if (ret < 0) {
177                 dev_err(&pdev->dev, "cannot register watchdog device\n");
178                 goto disable_clk;
179         }
180 
181         dev_info(&pdev->dev, "PNX4008 Watchdog Timer: heartbeat %d sec\n",
182                  pnx4008_wdd.timeout);
183 
184         return 0;
185 
186 disable_clk:
187         clk_disable(wdt_clk);
188         return ret;
189 }
190 
191 static int pnx4008_wdt_remove(struct platform_device *pdev)
192 {
193         watchdog_unregister_device(&pnx4008_wdd);
194 
195         clk_disable(wdt_clk);
196 
197         return 0;
198 }
199 
200 #ifdef CONFIG_OF
201 static const struct of_device_id pnx4008_wdt_match[] = {
202         { .compatible = "nxp,pnx4008-wdt" },
203         { }
204 };
205 MODULE_DEVICE_TABLE(of, pnx4008_wdt_match);
206 #endif
207 
208 static struct platform_driver platform_wdt_driver = {
209         .driver = {
210                 .name = "pnx4008-watchdog",
211                 .owner  = THIS_MODULE,
212                 .of_match_table = of_match_ptr(pnx4008_wdt_match),
213         },
214         .probe = pnx4008_wdt_probe,
215         .remove = pnx4008_wdt_remove,
216 };
217 
218 module_platform_driver(platform_wdt_driver);
219 
220 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
221 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
222 MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
223 
224 module_param(heartbeat, uint, 0);
225 MODULE_PARM_DESC(heartbeat,
226                  "Watchdog heartbeat period in seconds from 1 to "
227                  __MODULE_STRING(MAX_HEARTBEAT) ", default "
228                  __MODULE_STRING(DEFAULT_HEARTBEAT));
229 
230 module_param(nowayout, bool, 0);
231 MODULE_PARM_DESC(nowayout,
232                  "Set to 1 to keep watchdog running after device release");
233 
234 MODULE_LICENSE("GPL");
235 MODULE_ALIAS("platform:pnx4008-watchdog");
236 

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