Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/watchdog/jz4740_wdt.c

  1 /*
  2  *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
  3  *  JZ4740 Watchdog driver
  4  *
  5  *  This program is free software; you can redistribute it and/or modify it
  6  *  under  the terms of the GNU General  Public License as published by the
  7  *  Free Software Foundation;  either version 2 of the License, or (at your
  8  *  option) any later version.
  9  *
 10  *  You should have received a copy of the GNU General Public License along
 11  *  with this program; if not, write to the Free Software Foundation, Inc.,
 12  *  675 Mass Ave, Cambridge, MA 02139, USA.
 13  *
 14  */
 15 
 16 #include <linux/module.h>
 17 #include <linux/moduleparam.h>
 18 #include <linux/types.h>
 19 #include <linux/kernel.h>
 20 #include <linux/watchdog.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/io.h>
 23 #include <linux/device.h>
 24 #include <linux/clk.h>
 25 #include <linux/slab.h>
 26 #include <linux/err.h>
 27 
 28 #include <asm/mach-jz4740/timer.h>
 29 
 30 #define JZ_REG_WDT_TIMER_DATA     0x0
 31 #define JZ_REG_WDT_COUNTER_ENABLE 0x4
 32 #define JZ_REG_WDT_TIMER_COUNTER  0x8
 33 #define JZ_REG_WDT_TIMER_CONTROL  0xC
 34 
 35 #define JZ_WDT_CLOCK_PCLK 0x1
 36 #define JZ_WDT_CLOCK_RTC  0x2
 37 #define JZ_WDT_CLOCK_EXT  0x4
 38 
 39 #define JZ_WDT_CLOCK_DIV_SHIFT   3
 40 
 41 #define JZ_WDT_CLOCK_DIV_1    (0 << JZ_WDT_CLOCK_DIV_SHIFT)
 42 #define JZ_WDT_CLOCK_DIV_4    (1 << JZ_WDT_CLOCK_DIV_SHIFT)
 43 #define JZ_WDT_CLOCK_DIV_16   (2 << JZ_WDT_CLOCK_DIV_SHIFT)
 44 #define JZ_WDT_CLOCK_DIV_64   (3 << JZ_WDT_CLOCK_DIV_SHIFT)
 45 #define JZ_WDT_CLOCK_DIV_256  (4 << JZ_WDT_CLOCK_DIV_SHIFT)
 46 #define JZ_WDT_CLOCK_DIV_1024 (5 << JZ_WDT_CLOCK_DIV_SHIFT)
 47 
 48 #define DEFAULT_HEARTBEAT 5
 49 #define MAX_HEARTBEAT     2048
 50 
 51 static bool nowayout = WATCHDOG_NOWAYOUT;
 52 module_param(nowayout, bool, 0);
 53 MODULE_PARM_DESC(nowayout,
 54                  "Watchdog cannot be stopped once started (default="
 55                  __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 56 
 57 static unsigned int heartbeat = DEFAULT_HEARTBEAT;
 58 module_param(heartbeat, uint, 0);
 59 MODULE_PARM_DESC(heartbeat,
 60                 "Watchdog heartbeat period in seconds from 1 to "
 61                 __MODULE_STRING(MAX_HEARTBEAT) ", default "
 62                 __MODULE_STRING(DEFAULT_HEARTBEAT));
 63 
 64 struct jz4740_wdt_drvdata {
 65         struct watchdog_device wdt;
 66         void __iomem *base;
 67         struct clk *rtc_clk;
 68 };
 69 
 70 static int jz4740_wdt_ping(struct watchdog_device *wdt_dev)
 71 {
 72         struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
 73 
 74         writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
 75         return 0;
 76 }
 77 
 78 static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev,
 79                                     unsigned int new_timeout)
 80 {
 81         struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
 82         unsigned int rtc_clk_rate;
 83         unsigned int timeout_value;
 84         unsigned short clock_div = JZ_WDT_CLOCK_DIV_1;
 85 
 86         rtc_clk_rate = clk_get_rate(drvdata->rtc_clk);
 87 
 88         timeout_value = rtc_clk_rate * new_timeout;
 89         while (timeout_value > 0xffff) {
 90                 if (clock_div == JZ_WDT_CLOCK_DIV_1024) {
 91                         /* Requested timeout too high;
 92                         * use highest possible value. */
 93                         timeout_value = 0xffff;
 94                         break;
 95                 }
 96                 timeout_value >>= 2;
 97                 clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT);
 98         }
 99 
100         writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
101         writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
102 
103         writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA);
104         writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
105         writew(clock_div | JZ_WDT_CLOCK_RTC,
106                 drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
107 
108         writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
109 
110         wdt_dev->timeout = new_timeout;
111         return 0;
112 }
113 
114 static int jz4740_wdt_start(struct watchdog_device *wdt_dev)
115 {
116         jz4740_timer_enable_watchdog();
117         jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
118 
119         return 0;
120 }
121 
122 static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
123 {
124         struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
125 
126         jz4740_timer_disable_watchdog();
127         writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
128 
129         return 0;
130 }
131 
132 static const struct watchdog_info jz4740_wdt_info = {
133         .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
134         .identity = "jz4740 Watchdog",
135 };
136 
137 static const struct watchdog_ops jz4740_wdt_ops = {
138         .owner = THIS_MODULE,
139         .start = jz4740_wdt_start,
140         .stop = jz4740_wdt_stop,
141         .ping = jz4740_wdt_ping,
142         .set_timeout = jz4740_wdt_set_timeout,
143 };
144 
145 static int jz4740_wdt_probe(struct platform_device *pdev)
146 {
147         struct jz4740_wdt_drvdata *drvdata;
148         struct watchdog_device *jz4740_wdt;
149         struct resource *res;
150         int ret;
151 
152         drvdata = devm_kzalloc(&pdev->dev, sizeof(struct jz4740_wdt_drvdata),
153                                GFP_KERNEL);
154         if (!drvdata) {
155                 dev_err(&pdev->dev, "Unable to alloacate watchdog device\n");
156                 return -ENOMEM;
157         }
158 
159         if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
160                 heartbeat = DEFAULT_HEARTBEAT;
161 
162         jz4740_wdt = &drvdata->wdt;
163         jz4740_wdt->info = &jz4740_wdt_info;
164         jz4740_wdt->ops = &jz4740_wdt_ops;
165         jz4740_wdt->timeout = heartbeat;
166         jz4740_wdt->min_timeout = 1;
167         jz4740_wdt->max_timeout = MAX_HEARTBEAT;
168         watchdog_set_nowayout(jz4740_wdt, nowayout);
169         watchdog_set_drvdata(jz4740_wdt, drvdata);
170 
171         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
172         drvdata->base = devm_ioremap_resource(&pdev->dev, res);
173         if (IS_ERR(drvdata->base)) {
174                 ret = PTR_ERR(drvdata->base);
175                 goto err_out;
176         }
177 
178         drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
179         if (IS_ERR(drvdata->rtc_clk)) {
180                 dev_err(&pdev->dev, "cannot find RTC clock\n");
181                 ret = PTR_ERR(drvdata->rtc_clk);
182                 goto err_out;
183         }
184 
185         ret = watchdog_register_device(&drvdata->wdt);
186         if (ret < 0)
187                 goto err_disable_clk;
188 
189         platform_set_drvdata(pdev, drvdata);
190         return 0;
191 
192 err_disable_clk:
193         clk_put(drvdata->rtc_clk);
194 err_out:
195         return ret;
196 }
197 
198 static int jz4740_wdt_remove(struct platform_device *pdev)
199 {
200         struct jz4740_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
201 
202         jz4740_wdt_stop(&drvdata->wdt);
203         watchdog_unregister_device(&drvdata->wdt);
204         clk_put(drvdata->rtc_clk);
205 
206         return 0;
207 }
208 
209 static struct platform_driver jz4740_wdt_driver = {
210         .probe = jz4740_wdt_probe,
211         .remove = jz4740_wdt_remove,
212         .driver = {
213                 .name = "jz4740-wdt",
214                 .owner  = THIS_MODULE,
215         },
216 };
217 
218 module_platform_driver(jz4740_wdt_driver);
219 
220 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
221 MODULE_DESCRIPTION("jz4740 Watchdog Driver");
222 MODULE_LICENSE("GPL");
223 MODULE_ALIAS("platform:jz4740-wdt");
224 

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