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Linux/drivers/watchdog/imx2_wdt.c

  1 /*
  2  * Watchdog driver for IMX2 and later processors
  3  *
  4  *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
  5  *  Copyright (C) 2014 Freescale Semiconductor, Inc.
  6  *
  7  * some parts adapted by similar drivers from Darius Augulis and Vladimir
  8  * Zapolskiy, additional improvements by Wim Van Sebroeck.
  9  *
 10  * This program is free software; you can redistribute it and/or modify it
 11  * under the terms of the GNU General Public License version 2 as published by
 12  * the Free Software Foundation.
 13  *
 14  * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
 15  *
 16  *                      MX1:            MX2+:
 17  *                      ----            -----
 18  * Registers:           32-bit          16-bit
 19  * Stopable timer:      Yes             No
 20  * Need to enable clk:  No              Yes
 21  * Halt on suspend:     Manual          Can be automatic
 22  */
 23 
 24 #include <linux/clk.h>
 25 #include <linux/delay.h>
 26 #include <linux/init.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/io.h>
 29 #include <linux/kernel.h>
 30 #include <linux/module.h>
 31 #include <linux/moduleparam.h>
 32 #include <linux/of_address.h>
 33 #include <linux/platform_device.h>
 34 #include <linux/regmap.h>
 35 #include <linux/watchdog.h>
 36 
 37 #define DRIVER_NAME "imx2-wdt"
 38 
 39 #define IMX2_WDT_WCR            0x00            /* Control Register */
 40 #define IMX2_WDT_WCR_WT         (0xFF << 8)     /* -> Watchdog Timeout Field */
 41 #define IMX2_WDT_WCR_WDA        BIT(5)          /* -> External Reset WDOG_B */
 42 #define IMX2_WDT_WCR_SRS        BIT(4)          /* -> Software Reset Signal */
 43 #define IMX2_WDT_WCR_WRE        BIT(3)          /* -> WDOG Reset Enable */
 44 #define IMX2_WDT_WCR_WDE        BIT(2)          /* -> Watchdog Enable */
 45 #define IMX2_WDT_WCR_WDZST      BIT(0)          /* -> Watchdog timer Suspend */
 46 
 47 #define IMX2_WDT_WSR            0x02            /* Service Register */
 48 #define IMX2_WDT_SEQ1           0x5555          /* -> service sequence 1 */
 49 #define IMX2_WDT_SEQ2           0xAAAA          /* -> service sequence 2 */
 50 
 51 #define IMX2_WDT_WRSR           0x04            /* Reset Status Register */
 52 #define IMX2_WDT_WRSR_TOUT      BIT(1)          /* -> Reset due to Timeout */
 53 
 54 #define IMX2_WDT_WICR           0x06            /* Interrupt Control Register */
 55 #define IMX2_WDT_WICR_WIE       BIT(15)         /* -> Interrupt Enable */
 56 #define IMX2_WDT_WICR_WTIS      BIT(14)         /* -> Interrupt Status */
 57 #define IMX2_WDT_WICR_WICT      0xFF            /* -> Interrupt Count Timeout */
 58 
 59 #define IMX2_WDT_WMCR           0x08            /* Misc Register */
 60 
 61 #define IMX2_WDT_MAX_TIME       128
 62 #define IMX2_WDT_DEFAULT_TIME   60              /* in seconds */
 63 
 64 #define WDOG_SEC_TO_COUNT(s)    ((s * 2 - 1) << 8)
 65 
 66 struct imx2_wdt_device {
 67         struct clk *clk;
 68         struct regmap *regmap;
 69         struct watchdog_device wdog;
 70         bool ext_reset;
 71 };
 72 
 73 static bool nowayout = WATCHDOG_NOWAYOUT;
 74 module_param(nowayout, bool, 0);
 75 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
 76                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 77 
 78 
 79 static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
 80 module_param(timeout, uint, 0);
 81 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
 82                                 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
 83 
 84 static const struct watchdog_info imx2_wdt_info = {
 85         .identity = "imx2+ watchdog",
 86         .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
 87 };
 88 
 89 static const struct watchdog_info imx2_wdt_pretimeout_info = {
 90         .identity = "imx2+ watchdog",
 91         .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
 92                    WDIOF_PRETIMEOUT,
 93 };
 94 
 95 static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
 96                             void *data)
 97 {
 98         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 99         unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
100 
101         /* Use internal reset or external - not both */
102         if (wdev->ext_reset)
103                 wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
104         else
105                 wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
106 
107         /* Assert SRS signal */
108         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
109         /*
110          * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
111          * written twice), we add another two writes to ensure there must be at
112          * least two writes happen in the same one 32kHz clock period.  We save
113          * the target check here, since the writes shouldn't be a huge burden
114          * for other platforms.
115          */
116         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
117         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
118 
119         /* wait for reset to assert... */
120         mdelay(500);
121 
122         return 0;
123 }
124 
125 static inline void imx2_wdt_setup(struct watchdog_device *wdog)
126 {
127         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
128         u32 val;
129 
130         regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
131 
132         /* Suspend timer in low power mode, write once-only */
133         val |= IMX2_WDT_WCR_WDZST;
134         /* Strip the old watchdog Time-Out value */
135         val &= ~IMX2_WDT_WCR_WT;
136         /* Generate internal chip-level reset if WDOG times out */
137         if (!wdev->ext_reset)
138                 val &= ~IMX2_WDT_WCR_WRE;
139         /* Or if external-reset assert WDOG_B reset only on time-out */
140         else
141                 val |= IMX2_WDT_WCR_WRE;
142         /* Keep Watchdog Disabled */
143         val &= ~IMX2_WDT_WCR_WDE;
144         /* Set the watchdog's Time-Out value */
145         val |= WDOG_SEC_TO_COUNT(wdog->timeout);
146 
147         regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
148 
149         /* enable the watchdog */
150         val |= IMX2_WDT_WCR_WDE;
151         regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
152 }
153 
154 static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
155 {
156         u32 val;
157 
158         regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
159 
160         return val & IMX2_WDT_WCR_WDE;
161 }
162 
163 static int imx2_wdt_ping(struct watchdog_device *wdog)
164 {
165         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
166 
167         regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
168         regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
169         return 0;
170 }
171 
172 static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
173                                 unsigned int new_timeout)
174 {
175         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
176 
177         wdog->timeout = new_timeout;
178 
179         regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
180                            WDOG_SEC_TO_COUNT(new_timeout));
181         return 0;
182 }
183 
184 static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
185                                    unsigned int new_pretimeout)
186 {
187         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
188 
189         if (new_pretimeout >= IMX2_WDT_MAX_TIME)
190                 return -EINVAL;
191 
192         wdog->pretimeout = new_pretimeout;
193 
194         regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
195                            IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
196                            IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
197         return 0;
198 }
199 
200 static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
201 {
202         struct watchdog_device *wdog = wdog_arg;
203         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
204 
205         regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
206                           IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
207 
208         watchdog_notify_pretimeout(wdog);
209 
210         return IRQ_HANDLED;
211 }
212 
213 static int imx2_wdt_start(struct watchdog_device *wdog)
214 {
215         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
216 
217         if (imx2_wdt_is_running(wdev))
218                 imx2_wdt_set_timeout(wdog, wdog->timeout);
219         else
220                 imx2_wdt_setup(wdog);
221 
222         set_bit(WDOG_HW_RUNNING, &wdog->status);
223 
224         return imx2_wdt_ping(wdog);
225 }
226 
227 static const struct watchdog_ops imx2_wdt_ops = {
228         .owner = THIS_MODULE,
229         .start = imx2_wdt_start,
230         .ping = imx2_wdt_ping,
231         .set_timeout = imx2_wdt_set_timeout,
232         .set_pretimeout = imx2_wdt_set_pretimeout,
233         .restart = imx2_wdt_restart,
234 };
235 
236 static const struct regmap_config imx2_wdt_regmap_config = {
237         .reg_bits = 16,
238         .reg_stride = 2,
239         .val_bits = 16,
240         .max_register = 0x8,
241 };
242 
243 static int __init imx2_wdt_probe(struct platform_device *pdev)
244 {
245         struct imx2_wdt_device *wdev;
246         struct watchdog_device *wdog;
247         struct resource *res;
248         void __iomem *base;
249         int ret;
250         u32 val;
251 
252         wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
253         if (!wdev)
254                 return -ENOMEM;
255 
256         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
257         base = devm_ioremap_resource(&pdev->dev, res);
258         if (IS_ERR(base))
259                 return PTR_ERR(base);
260 
261         wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
262                                                  &imx2_wdt_regmap_config);
263         if (IS_ERR(wdev->regmap)) {
264                 dev_err(&pdev->dev, "regmap init failed\n");
265                 return PTR_ERR(wdev->regmap);
266         }
267 
268         wdev->clk = devm_clk_get(&pdev->dev, NULL);
269         if (IS_ERR(wdev->clk)) {
270                 dev_err(&pdev->dev, "can't get Watchdog clock\n");
271                 return PTR_ERR(wdev->clk);
272         }
273 
274         wdog                    = &wdev->wdog;
275         wdog->info              = &imx2_wdt_info;
276         wdog->ops               = &imx2_wdt_ops;
277         wdog->min_timeout       = 1;
278         wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
279         wdog->parent            = &pdev->dev;
280 
281         ret = platform_get_irq(pdev, 0);
282         if (ret > 0)
283                 if (!devm_request_irq(&pdev->dev, ret, imx2_wdt_isr, 0,
284                                       dev_name(&pdev->dev), wdog))
285                         wdog->info = &imx2_wdt_pretimeout_info;
286 
287         ret = clk_prepare_enable(wdev->clk);
288         if (ret)
289                 return ret;
290 
291         regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
292         wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
293 
294         wdev->ext_reset = of_property_read_bool(pdev->dev.of_node,
295                                                 "fsl,ext-reset-output");
296         wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
297         if (wdog->timeout != timeout)
298                 dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
299                          timeout, wdog->timeout);
300 
301         platform_set_drvdata(pdev, wdog);
302         watchdog_set_drvdata(wdog, wdev);
303         watchdog_set_nowayout(wdog, nowayout);
304         watchdog_set_restart_priority(wdog, 128);
305         watchdog_init_timeout(wdog, timeout, &pdev->dev);
306 
307         if (imx2_wdt_is_running(wdev)) {
308                 imx2_wdt_set_timeout(wdog, wdog->timeout);
309                 set_bit(WDOG_HW_RUNNING, &wdog->status);
310         }
311 
312         /*
313          * Disable the watchdog power down counter at boot. Otherwise the power
314          * down counter will pull down the #WDOG interrupt line for one clock
315          * cycle.
316          */
317         regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
318 
319         ret = watchdog_register_device(wdog);
320         if (ret) {
321                 dev_err(&pdev->dev, "cannot register watchdog device\n");
322                 goto disable_clk;
323         }
324 
325         dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
326                  wdog->timeout, nowayout);
327 
328         return 0;
329 
330 disable_clk:
331         clk_disable_unprepare(wdev->clk);
332         return ret;
333 }
334 
335 static int __exit imx2_wdt_remove(struct platform_device *pdev)
336 {
337         struct watchdog_device *wdog = platform_get_drvdata(pdev);
338         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
339 
340         watchdog_unregister_device(wdog);
341 
342         if (imx2_wdt_is_running(wdev)) {
343                 imx2_wdt_ping(wdog);
344                 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
345         }
346         return 0;
347 }
348 
349 static void imx2_wdt_shutdown(struct platform_device *pdev)
350 {
351         struct watchdog_device *wdog = platform_get_drvdata(pdev);
352         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
353 
354         if (imx2_wdt_is_running(wdev)) {
355                 /*
356                  * We are running, configure max timeout before reboot
357                  * will take place.
358                  */
359                 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
360                 imx2_wdt_ping(wdog);
361                 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
362         }
363 }
364 
365 #ifdef CONFIG_PM_SLEEP
366 /* Disable watchdog if it is active or non-active but still running */
367 static int imx2_wdt_suspend(struct device *dev)
368 {
369         struct watchdog_device *wdog = dev_get_drvdata(dev);
370         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
371 
372         /* The watchdog IP block is running */
373         if (imx2_wdt_is_running(wdev)) {
374                 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
375                 imx2_wdt_ping(wdog);
376         }
377 
378         clk_disable_unprepare(wdev->clk);
379 
380         return 0;
381 }
382 
383 /* Enable watchdog and configure it if necessary */
384 static int imx2_wdt_resume(struct device *dev)
385 {
386         struct watchdog_device *wdog = dev_get_drvdata(dev);
387         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
388         int ret;
389 
390         ret = clk_prepare_enable(wdev->clk);
391         if (ret)
392                 return ret;
393 
394         if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
395                 /*
396                  * If the watchdog is still active and resumes
397                  * from deep sleep state, need to restart the
398                  * watchdog again.
399                  */
400                 imx2_wdt_setup(wdog);
401         }
402         if (imx2_wdt_is_running(wdev)) {
403                 imx2_wdt_set_timeout(wdog, wdog->timeout);
404                 imx2_wdt_ping(wdog);
405         }
406 
407         return 0;
408 }
409 #endif
410 
411 static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
412                          imx2_wdt_resume);
413 
414 static const struct of_device_id imx2_wdt_dt_ids[] = {
415         { .compatible = "fsl,imx21-wdt", },
416         { /* sentinel */ }
417 };
418 MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
419 
420 static struct platform_driver imx2_wdt_driver = {
421         .remove         = __exit_p(imx2_wdt_remove),
422         .shutdown       = imx2_wdt_shutdown,
423         .driver         = {
424                 .name   = DRIVER_NAME,
425                 .pm     = &imx2_wdt_pm_ops,
426                 .of_match_table = imx2_wdt_dt_ids,
427         },
428 };
429 
430 module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
431 
432 MODULE_AUTHOR("Wolfram Sang");
433 MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
434 MODULE_LICENSE("GPL v2");
435 MODULE_ALIAS("platform:" DRIVER_NAME);
436 

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