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Linux/drivers/watchdog/iTCO_wdt.c

  1 /*
  2  *      intel TCO Watchdog Driver
  3  *
  4  *      (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
  5  *
  6  *      This program is free software; you can redistribute it and/or
  7  *      modify it under the terms of the GNU General Public License
  8  *      as published by the Free Software Foundation; either version
  9  *      2 of the License, or (at your option) any later version.
 10  *
 11  *      Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
 12  *      provide warranty for any of this software. This material is
 13  *      provided "AS-IS" and at no charge.
 14  *
 15  *      The TCO watchdog is implemented in the following I/O controller hubs:
 16  *      (See the intel documentation on http://developer.intel.com.)
 17  *      document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
 18  *      document number 290687-002, 298242-027: 82801BA (ICH2)
 19  *      document number 290733-003, 290739-013: 82801CA (ICH3-S)
 20  *      document number 290716-001, 290718-007: 82801CAM (ICH3-M)
 21  *      document number 290744-001, 290745-025: 82801DB (ICH4)
 22  *      document number 252337-001, 252663-008: 82801DBM (ICH4-M)
 23  *      document number 273599-001, 273645-002: 82801E (C-ICH)
 24  *      document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
 25  *      document number 300641-004, 300884-013: 6300ESB
 26  *      document number 301473-002, 301474-026: 82801F (ICH6)
 27  *      document number 313082-001, 313075-006: 631xESB, 632xESB
 28  *      document number 307013-003, 307014-024: 82801G (ICH7)
 29  *      document number 322896-001, 322897-001: NM10
 30  *      document number 313056-003, 313057-017: 82801H (ICH8)
 31  *      document number 316972-004, 316973-012: 82801I (ICH9)
 32  *      document number 319973-002, 319974-002: 82801J (ICH10)
 33  *      document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
 34  *      document number 320066-003, 320257-008: EP80597 (IICH)
 35  *      document number 324645-001, 324646-001: Cougar Point (CPT)
 36  *      document number TBD                   : Patsburg (PBG)
 37  *      document number TBD                   : DH89xxCC
 38  *      document number TBD                   : Panther Point
 39  *      document number TBD                   : Lynx Point
 40  *      document number TBD                   : Lynx Point-LP
 41  */
 42 
 43 /*
 44  *      Includes, defines, variables, module parameters, ...
 45  */
 46 
 47 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 48 
 49 /* Module and version information */
 50 #define DRV_NAME        "iTCO_wdt"
 51 #define DRV_VERSION     "1.11"
 52 
 53 /* Includes */
 54 #include <linux/module.h>               /* For module specific items */
 55 #include <linux/moduleparam.h>          /* For new moduleparam's */
 56 #include <linux/types.h>                /* For standard types (like size_t) */
 57 #include <linux/errno.h>                /* For the -ENODEV/... values */
 58 #include <linux/kernel.h>               /* For printk/panic/... */
 59 #include <linux/watchdog.h>             /* For the watchdog specific items */
 60 #include <linux/init.h>                 /* For __init/__exit/... */
 61 #include <linux/fs.h>                   /* For file operations */
 62 #include <linux/platform_device.h>      /* For platform_driver framework */
 63 #include <linux/pci.h>                  /* For pci functions */
 64 #include <linux/ioport.h>               /* For io-port access */
 65 #include <linux/spinlock.h>             /* For spin_lock/spin_unlock/... */
 66 #include <linux/uaccess.h>              /* For copy_to_user/put_user/... */
 67 #include <linux/io.h>                   /* For inb/outb/... */
 68 #include <linux/mfd/core.h>
 69 #include <linux/mfd/lpc_ich.h>
 70 
 71 #include "iTCO_vendor.h"
 72 
 73 /* Address definitions for the TCO */
 74 /* TCO base address */
 75 #define TCOBASE         (iTCO_wdt_private.tco_res->start)
 76 /* SMI Control and Enable Register */
 77 #define SMI_EN          (iTCO_wdt_private.smi_res->start)
 78 
 79 #define TCO_RLD         (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
 80 #define TCOv1_TMR       (TCOBASE + 0x01) /* TCOv1 Timer Initial Value   */
 81 #define TCO_DAT_IN      (TCOBASE + 0x02) /* TCO Data In Register        */
 82 #define TCO_DAT_OUT     (TCOBASE + 0x03) /* TCO Data Out Register       */
 83 #define TCO1_STS        (TCOBASE + 0x04) /* TCO1 Status Register        */
 84 #define TCO2_STS        (TCOBASE + 0x06) /* TCO2 Status Register        */
 85 #define TCO1_CNT        (TCOBASE + 0x08) /* TCO1 Control Register       */
 86 #define TCO2_CNT        (TCOBASE + 0x0a) /* TCO2 Control Register       */
 87 #define TCOv2_TMR       (TCOBASE + 0x12) /* TCOv2 Timer Initial Value   */
 88 
 89 /* internal variables */
 90 static struct {         /* this is private data for the iTCO_wdt device */
 91         /* TCO version/generation */
 92         unsigned int iTCO_version;
 93         struct resource *tco_res;
 94         struct resource *smi_res;
 95         /*
 96          * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
 97          * or memory-mapped PMC register bit 4 (TCO version 3).
 98          */
 99         struct resource *gcs_pmc_res;
100         unsigned long __iomem *gcs_pmc;
101         /* the lock for io operations */
102         spinlock_t io_lock;
103         struct platform_device *dev;
104         /* the PCI-device */
105         struct pci_dev *pdev;
106 } iTCO_wdt_private;
107 
108 /* module parameters */
109 #define WATCHDOG_TIMEOUT 30     /* 30 sec default heartbeat */
110 static int heartbeat = WATCHDOG_TIMEOUT;  /* in seconds */
111 module_param(heartbeat, int, 0);
112 MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
113         "5..76 (TCO v1) or 3..614 (TCO v2), default="
114                                 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
115 
116 static bool nowayout = WATCHDOG_NOWAYOUT;
117 module_param(nowayout, bool, 0);
118 MODULE_PARM_DESC(nowayout,
119         "Watchdog cannot be stopped once started (default="
120                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
121 
122 static int turn_SMI_watchdog_clear_off = 1;
123 module_param(turn_SMI_watchdog_clear_off, int, 0);
124 MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
125         "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
126 
127 /*
128  * Some TCO specific functions
129  */
130 
131 /*
132  * The iTCO v1 and v2's internal timer is stored as ticks which decrement
133  * every 0.6 seconds.  v3's internal timer is stored as seconds (some
134  * datasheets incorrectly state 0.6 seconds).
135  */
136 static inline unsigned int seconds_to_ticks(int secs)
137 {
138         return iTCO_wdt_private.iTCO_version == 3 ? secs : (secs * 10) / 6;
139 }
140 
141 static inline unsigned int ticks_to_seconds(int ticks)
142 {
143         return iTCO_wdt_private.iTCO_version == 3 ? ticks : (ticks * 6) / 10;
144 }
145 
146 static void iTCO_wdt_set_NO_REBOOT_bit(void)
147 {
148         u32 val32;
149 
150         /* Set the NO_REBOOT bit: this disables reboots */
151         if (iTCO_wdt_private.iTCO_version == 3) {
152                 val32 = readl(iTCO_wdt_private.gcs_pmc);
153                 val32 |= 0x00000010;
154                 writel(val32, iTCO_wdt_private.gcs_pmc);
155         } else if (iTCO_wdt_private.iTCO_version == 2) {
156                 val32 = readl(iTCO_wdt_private.gcs_pmc);
157                 val32 |= 0x00000020;
158                 writel(val32, iTCO_wdt_private.gcs_pmc);
159         } else if (iTCO_wdt_private.iTCO_version == 1) {
160                 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
161                 val32 |= 0x00000002;
162                 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
163         }
164 }
165 
166 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
167 {
168         int ret = 0;
169         u32 val32;
170 
171         /* Unset the NO_REBOOT bit: this enables reboots */
172         if (iTCO_wdt_private.iTCO_version == 3) {
173                 val32 = readl(iTCO_wdt_private.gcs_pmc);
174                 val32 &= 0xffffffef;
175                 writel(val32, iTCO_wdt_private.gcs_pmc);
176 
177                 val32 = readl(iTCO_wdt_private.gcs_pmc);
178                 if (val32 & 0x00000010)
179                         ret = -EIO;
180         } else if (iTCO_wdt_private.iTCO_version == 2) {
181                 val32 = readl(iTCO_wdt_private.gcs_pmc);
182                 val32 &= 0xffffffdf;
183                 writel(val32, iTCO_wdt_private.gcs_pmc);
184 
185                 val32 = readl(iTCO_wdt_private.gcs_pmc);
186                 if (val32 & 0x00000020)
187                         ret = -EIO;
188         } else if (iTCO_wdt_private.iTCO_version == 1) {
189                 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
190                 val32 &= 0xfffffffd;
191                 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
192 
193                 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
194                 if (val32 & 0x00000002)
195                         ret = -EIO;
196         }
197 
198         return ret; /* returns: 0 = OK, -EIO = Error */
199 }
200 
201 static int iTCO_wdt_start(struct watchdog_device *wd_dev)
202 {
203         unsigned int val;
204 
205         spin_lock(&iTCO_wdt_private.io_lock);
206 
207         iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout);
208 
209         /* disable chipset's NO_REBOOT bit */
210         if (iTCO_wdt_unset_NO_REBOOT_bit()) {
211                 spin_unlock(&iTCO_wdt_private.io_lock);
212                 pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
213                 return -EIO;
214         }
215 
216         /* Force the timer to its reload value by writing to the TCO_RLD
217            register */
218         if (iTCO_wdt_private.iTCO_version >= 2)
219                 outw(0x01, TCO_RLD);
220         else if (iTCO_wdt_private.iTCO_version == 1)
221                 outb(0x01, TCO_RLD);
222 
223         /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
224         val = inw(TCO1_CNT);
225         val &= 0xf7ff;
226         outw(val, TCO1_CNT);
227         val = inw(TCO1_CNT);
228         spin_unlock(&iTCO_wdt_private.io_lock);
229 
230         if (val & 0x0800)
231                 return -1;
232         return 0;
233 }
234 
235 static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
236 {
237         unsigned int val;
238 
239         spin_lock(&iTCO_wdt_private.io_lock);
240 
241         iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res);
242 
243         /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
244         val = inw(TCO1_CNT);
245         val |= 0x0800;
246         outw(val, TCO1_CNT);
247         val = inw(TCO1_CNT);
248 
249         /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
250         iTCO_wdt_set_NO_REBOOT_bit();
251 
252         spin_unlock(&iTCO_wdt_private.io_lock);
253 
254         if ((val & 0x0800) == 0)
255                 return -1;
256         return 0;
257 }
258 
259 static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
260 {
261         spin_lock(&iTCO_wdt_private.io_lock);
262 
263         iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout);
264 
265         /* Reload the timer by writing to the TCO Timer Counter register */
266         if (iTCO_wdt_private.iTCO_version >= 2) {
267                 outw(0x01, TCO_RLD);
268         } else if (iTCO_wdt_private.iTCO_version == 1) {
269                 /* Reset the timeout status bit so that the timer
270                  * needs to count down twice again before rebooting */
271                 outw(0x0008, TCO1_STS); /* write 1 to clear bit */
272 
273                 outb(0x01, TCO_RLD);
274         }
275 
276         spin_unlock(&iTCO_wdt_private.io_lock);
277         return 0;
278 }
279 
280 static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
281 {
282         unsigned int val16;
283         unsigned char val8;
284         unsigned int tmrval;
285 
286         tmrval = seconds_to_ticks(t);
287 
288         /* For TCO v1 the timer counts down twice before rebooting */
289         if (iTCO_wdt_private.iTCO_version == 1)
290                 tmrval /= 2;
291 
292         /* from the specs: */
293         /* "Values of 0h-3h are ignored and should not be attempted" */
294         if (tmrval < 0x04)
295                 return -EINVAL;
296         if (((iTCO_wdt_private.iTCO_version >= 2) && (tmrval > 0x3ff)) ||
297             ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
298                 return -EINVAL;
299 
300         iTCO_vendor_pre_set_heartbeat(tmrval);
301 
302         /* Write new heartbeat to watchdog */
303         if (iTCO_wdt_private.iTCO_version >= 2) {
304                 spin_lock(&iTCO_wdt_private.io_lock);
305                 val16 = inw(TCOv2_TMR);
306                 val16 &= 0xfc00;
307                 val16 |= tmrval;
308                 outw(val16, TCOv2_TMR);
309                 val16 = inw(TCOv2_TMR);
310                 spin_unlock(&iTCO_wdt_private.io_lock);
311 
312                 if ((val16 & 0x3ff) != tmrval)
313                         return -EINVAL;
314         } else if (iTCO_wdt_private.iTCO_version == 1) {
315                 spin_lock(&iTCO_wdt_private.io_lock);
316                 val8 = inb(TCOv1_TMR);
317                 val8 &= 0xc0;
318                 val8 |= (tmrval & 0xff);
319                 outb(val8, TCOv1_TMR);
320                 val8 = inb(TCOv1_TMR);
321                 spin_unlock(&iTCO_wdt_private.io_lock);
322 
323                 if ((val8 & 0x3f) != tmrval)
324                         return -EINVAL;
325         }
326 
327         wd_dev->timeout = t;
328         return 0;
329 }
330 
331 static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
332 {
333         unsigned int val16;
334         unsigned char val8;
335         unsigned int time_left = 0;
336 
337         /* read the TCO Timer */
338         if (iTCO_wdt_private.iTCO_version >= 2) {
339                 spin_lock(&iTCO_wdt_private.io_lock);
340                 val16 = inw(TCO_RLD);
341                 val16 &= 0x3ff;
342                 spin_unlock(&iTCO_wdt_private.io_lock);
343 
344                 time_left = ticks_to_seconds(val16);
345         } else if (iTCO_wdt_private.iTCO_version == 1) {
346                 spin_lock(&iTCO_wdt_private.io_lock);
347                 val8 = inb(TCO_RLD);
348                 val8 &= 0x3f;
349                 if (!(inw(TCO1_STS) & 0x0008))
350                         val8 += (inb(TCOv1_TMR) & 0x3f);
351                 spin_unlock(&iTCO_wdt_private.io_lock);
352 
353                 time_left = ticks_to_seconds(val8);
354         }
355         return time_left;
356 }
357 
358 /*
359  *      Kernel Interfaces
360  */
361 
362 static const struct watchdog_info ident = {
363         .options =              WDIOF_SETTIMEOUT |
364                                 WDIOF_KEEPALIVEPING |
365                                 WDIOF_MAGICCLOSE,
366         .firmware_version =     0,
367         .identity =             DRV_NAME,
368 };
369 
370 static const struct watchdog_ops iTCO_wdt_ops = {
371         .owner =                THIS_MODULE,
372         .start =                iTCO_wdt_start,
373         .stop =                 iTCO_wdt_stop,
374         .ping =                 iTCO_wdt_ping,
375         .set_timeout =          iTCO_wdt_set_timeout,
376         .get_timeleft =         iTCO_wdt_get_timeleft,
377 };
378 
379 static struct watchdog_device iTCO_wdt_watchdog_dev = {
380         .info =         &ident,
381         .ops =          &iTCO_wdt_ops,
382 };
383 
384 /*
385  *      Init & exit routines
386  */
387 
388 static void iTCO_wdt_cleanup(void)
389 {
390         /* Stop the timer before we leave */
391         if (!nowayout)
392                 iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
393 
394         /* Deregister */
395         watchdog_unregister_device(&iTCO_wdt_watchdog_dev);
396 
397         /* release resources */
398         release_region(iTCO_wdt_private.tco_res->start,
399                         resource_size(iTCO_wdt_private.tco_res));
400         release_region(iTCO_wdt_private.smi_res->start,
401                         resource_size(iTCO_wdt_private.smi_res));
402         if (iTCO_wdt_private.iTCO_version >= 2) {
403                 iounmap(iTCO_wdt_private.gcs_pmc);
404                 release_mem_region(iTCO_wdt_private.gcs_pmc_res->start,
405                                 resource_size(iTCO_wdt_private.gcs_pmc_res));
406         }
407 
408         iTCO_wdt_private.tco_res = NULL;
409         iTCO_wdt_private.smi_res = NULL;
410         iTCO_wdt_private.gcs_pmc_res = NULL;
411         iTCO_wdt_private.gcs_pmc = NULL;
412 }
413 
414 static int iTCO_wdt_probe(struct platform_device *dev)
415 {
416         int ret = -ENODEV;
417         unsigned long val32;
418         struct lpc_ich_info *ich_info = dev_get_platdata(&dev->dev);
419 
420         if (!ich_info)
421                 goto out;
422 
423         spin_lock_init(&iTCO_wdt_private.io_lock);
424 
425         iTCO_wdt_private.tco_res =
426                 platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO);
427         if (!iTCO_wdt_private.tco_res)
428                 goto out;
429 
430         iTCO_wdt_private.smi_res =
431                 platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI);
432         if (!iTCO_wdt_private.smi_res)
433                 goto out;
434 
435         iTCO_wdt_private.iTCO_version = ich_info->iTCO_version;
436         iTCO_wdt_private.dev = dev;
437         iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent);
438 
439         /*
440          * Get the Memory-Mapped GCS or PMC register, we need it for the
441          * NO_REBOOT flag (TCO v2 and v3).
442          */
443         if (iTCO_wdt_private.iTCO_version >= 2) {
444                 iTCO_wdt_private.gcs_pmc_res = platform_get_resource(dev,
445                                                         IORESOURCE_MEM,
446                                                         ICH_RES_MEM_GCS_PMC);
447 
448                 if (!iTCO_wdt_private.gcs_pmc_res)
449                         goto out;
450 
451                 if (!request_mem_region(iTCO_wdt_private.gcs_pmc_res->start,
452                         resource_size(iTCO_wdt_private.gcs_pmc_res), dev->name)) {
453                         ret = -EBUSY;
454                         goto out;
455                 }
456                 iTCO_wdt_private.gcs_pmc = ioremap(iTCO_wdt_private.gcs_pmc_res->start,
457                         resource_size(iTCO_wdt_private.gcs_pmc_res));
458                 if (!iTCO_wdt_private.gcs_pmc) {
459                         ret = -EIO;
460                         goto unreg_gcs_pmc;
461                 }
462         }
463 
464         /* Check chipset's NO_REBOOT bit */
465         if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
466                 pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
467                 ret = -ENODEV;  /* Cannot reset NO_REBOOT bit */
468                 goto unmap_gcs_pmc;
469         }
470 
471         /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
472         iTCO_wdt_set_NO_REBOOT_bit();
473 
474         /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
475         if (!request_region(iTCO_wdt_private.smi_res->start,
476                         resource_size(iTCO_wdt_private.smi_res), dev->name)) {
477                 pr_err("I/O address 0x%04llx already in use, device disabled\n",
478                        (u64)SMI_EN);
479                 ret = -EBUSY;
480                 goto unmap_gcs_pmc;
481         }
482         if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) {
483                 /*
484                  * Bit 13: TCO_EN -> 0
485                  * Disables TCO logic generating an SMI#
486                  */
487                 val32 = inl(SMI_EN);
488                 val32 &= 0xffffdfff;    /* Turn off SMI clearing watchdog */
489                 outl(val32, SMI_EN);
490         }
491 
492         if (!request_region(iTCO_wdt_private.tco_res->start,
493                         resource_size(iTCO_wdt_private.tco_res), dev->name)) {
494                 pr_err("I/O address 0x%04llx already in use, device disabled\n",
495                        (u64)TCOBASE);
496                 ret = -EBUSY;
497                 goto unreg_smi;
498         }
499 
500         pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
501                 ich_info->name, ich_info->iTCO_version, (u64)TCOBASE);
502 
503         /* Clear out the (probably old) status */
504         if (iTCO_wdt_private.iTCO_version == 3) {
505                 outl(0x20008, TCO1_STS);
506         } else {
507                 outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
508                 outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
509                 outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
510         }
511 
512         iTCO_wdt_watchdog_dev.bootstatus = 0;
513         iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT;
514         watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout);
515         iTCO_wdt_watchdog_dev.parent = &dev->dev;
516 
517         /* Make sure the watchdog is not running */
518         iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
519 
520         /* Check that the heartbeat value is within it's range;
521            if not reset to the default */
522         if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) {
523                 iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT);
524                 pr_info("timeout value out of range, using %d\n",
525                         WATCHDOG_TIMEOUT);
526         }
527 
528         ret = watchdog_register_device(&iTCO_wdt_watchdog_dev);
529         if (ret != 0) {
530                 pr_err("cannot register watchdog device (err=%d)\n", ret);
531                 goto unreg_tco;
532         }
533 
534         pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
535                 heartbeat, nowayout);
536 
537         return 0;
538 
539 unreg_tco:
540         release_region(iTCO_wdt_private.tco_res->start,
541                         resource_size(iTCO_wdt_private.tco_res));
542 unreg_smi:
543         release_region(iTCO_wdt_private.smi_res->start,
544                         resource_size(iTCO_wdt_private.smi_res));
545 unmap_gcs_pmc:
546         if (iTCO_wdt_private.iTCO_version >= 2)
547                 iounmap(iTCO_wdt_private.gcs_pmc);
548 unreg_gcs_pmc:
549         if (iTCO_wdt_private.iTCO_version >= 2)
550                 release_mem_region(iTCO_wdt_private.gcs_pmc_res->start,
551                                 resource_size(iTCO_wdt_private.gcs_pmc_res));
552 out:
553         iTCO_wdt_private.tco_res = NULL;
554         iTCO_wdt_private.smi_res = NULL;
555         iTCO_wdt_private.gcs_pmc_res = NULL;
556         iTCO_wdt_private.gcs_pmc = NULL;
557 
558         return ret;
559 }
560 
561 static int iTCO_wdt_remove(struct platform_device *dev)
562 {
563         if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res)
564                 iTCO_wdt_cleanup();
565 
566         return 0;
567 }
568 
569 static void iTCO_wdt_shutdown(struct platform_device *dev)
570 {
571         iTCO_wdt_stop(NULL);
572 }
573 
574 static struct platform_driver iTCO_wdt_driver = {
575         .probe          = iTCO_wdt_probe,
576         .remove         = iTCO_wdt_remove,
577         .shutdown       = iTCO_wdt_shutdown,
578         .driver         = {
579                 .owner  = THIS_MODULE,
580                 .name   = DRV_NAME,
581         },
582 };
583 
584 static int __init iTCO_wdt_init_module(void)
585 {
586         int err;
587 
588         pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
589 
590         err = platform_driver_register(&iTCO_wdt_driver);
591         if (err)
592                 return err;
593 
594         return 0;
595 }
596 
597 static void __exit iTCO_wdt_cleanup_module(void)
598 {
599         platform_driver_unregister(&iTCO_wdt_driver);
600         pr_info("Watchdog Module Unloaded\n");
601 }
602 
603 module_init(iTCO_wdt_init_module);
604 module_exit(iTCO_wdt_cleanup_module);
605 
606 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
607 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
608 MODULE_VERSION(DRV_VERSION);
609 MODULE_LICENSE("GPL");
610 MODULE_ALIAS("platform:" DRV_NAME);
611 

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