Version:  2.6.34 2.6.35 2.6.36 2.6.37 2.6.38 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14

Linux/drivers/video/omap2/dss/venc.c

  1 /*
  2  * linux/drivers/video/omap2/dss/venc.c
  3  *
  4  * Copyright (C) 2009 Nokia Corporation
  5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6  *
  7  * VENC settings from TI's DSS driver
  8  *
  9  * This program is free software; you can redistribute it and/or modify it
 10  * under the terms of the GNU General Public License version 2 as published by
 11  * the Free Software Foundation.
 12  *
 13  * This program is distributed in the hope that it will be useful, but WITHOUT
 14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 16  * more details.
 17  *
 18  * You should have received a copy of the GNU General Public License along with
 19  * this program.  If not, see <http://www.gnu.org/licenses/>.
 20  */
 21 
 22 #define DSS_SUBSYS_NAME "VENC"
 23 
 24 #include <linux/kernel.h>
 25 #include <linux/module.h>
 26 #include <linux/clk.h>
 27 #include <linux/err.h>
 28 #include <linux/io.h>
 29 #include <linux/mutex.h>
 30 #include <linux/completion.h>
 31 #include <linux/delay.h>
 32 #include <linux/string.h>
 33 #include <linux/seq_file.h>
 34 #include <linux/platform_device.h>
 35 #include <linux/regulator/consumer.h>
 36 #include <linux/pm_runtime.h>
 37 
 38 #include <video/omapdss.h>
 39 
 40 #include "dss.h"
 41 #include "dss_features.h"
 42 
 43 /* Venc registers */
 44 #define VENC_REV_ID                             0x00
 45 #define VENC_STATUS                             0x04
 46 #define VENC_F_CONTROL                          0x08
 47 #define VENC_VIDOUT_CTRL                        0x10
 48 #define VENC_SYNC_CTRL                          0x14
 49 #define VENC_LLEN                               0x1C
 50 #define VENC_FLENS                              0x20
 51 #define VENC_HFLTR_CTRL                         0x24
 52 #define VENC_CC_CARR_WSS_CARR                   0x28
 53 #define VENC_C_PHASE                            0x2C
 54 #define VENC_GAIN_U                             0x30
 55 #define VENC_GAIN_V                             0x34
 56 #define VENC_GAIN_Y                             0x38
 57 #define VENC_BLACK_LEVEL                        0x3C
 58 #define VENC_BLANK_LEVEL                        0x40
 59 #define VENC_X_COLOR                            0x44
 60 #define VENC_M_CONTROL                          0x48
 61 #define VENC_BSTAMP_WSS_DATA                    0x4C
 62 #define VENC_S_CARR                             0x50
 63 #define VENC_LINE21                             0x54
 64 #define VENC_LN_SEL                             0x58
 65 #define VENC_L21__WC_CTL                        0x5C
 66 #define VENC_HTRIGGER_VTRIGGER                  0x60
 67 #define VENC_SAVID__EAVID                       0x64
 68 #define VENC_FLEN__FAL                          0x68
 69 #define VENC_LAL__PHASE_RESET                   0x6C
 70 #define VENC_HS_INT_START_STOP_X                0x70
 71 #define VENC_HS_EXT_START_STOP_X                0x74
 72 #define VENC_VS_INT_START_X                     0x78
 73 #define VENC_VS_INT_STOP_X__VS_INT_START_Y      0x7C
 74 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X      0x80
 75 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y      0x84
 76 #define VENC_VS_EXT_STOP_Y                      0x88
 77 #define VENC_AVID_START_STOP_X                  0x90
 78 #define VENC_AVID_START_STOP_Y                  0x94
 79 #define VENC_FID_INT_START_X__FID_INT_START_Y   0xA0
 80 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X  0xA4
 81 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y  0xA8
 82 #define VENC_TVDETGP_INT_START_STOP_X           0xB0
 83 #define VENC_TVDETGP_INT_START_STOP_Y           0xB4
 84 #define VENC_GEN_CTRL                           0xB8
 85 #define VENC_OUTPUT_CONTROL                     0xC4
 86 #define VENC_OUTPUT_TEST                        0xC8
 87 #define VENC_DAC_B__DAC_C                       0xC8
 88 
 89 struct venc_config {
 90         u32 f_control;
 91         u32 vidout_ctrl;
 92         u32 sync_ctrl;
 93         u32 llen;
 94         u32 flens;
 95         u32 hfltr_ctrl;
 96         u32 cc_carr_wss_carr;
 97         u32 c_phase;
 98         u32 gain_u;
 99         u32 gain_v;
100         u32 gain_y;
101         u32 black_level;
102         u32 blank_level;
103         u32 x_color;
104         u32 m_control;
105         u32 bstamp_wss_data;
106         u32 s_carr;
107         u32 line21;
108         u32 ln_sel;
109         u32 l21__wc_ctl;
110         u32 htrigger_vtrigger;
111         u32 savid__eavid;
112         u32 flen__fal;
113         u32 lal__phase_reset;
114         u32 hs_int_start_stop_x;
115         u32 hs_ext_start_stop_x;
116         u32 vs_int_start_x;
117         u32 vs_int_stop_x__vs_int_start_y;
118         u32 vs_int_stop_y__vs_ext_start_x;
119         u32 vs_ext_stop_x__vs_ext_start_y;
120         u32 vs_ext_stop_y;
121         u32 avid_start_stop_x;
122         u32 avid_start_stop_y;
123         u32 fid_int_start_x__fid_int_start_y;
124         u32 fid_int_offset_y__fid_ext_start_x;
125         u32 fid_ext_start_y__fid_ext_offset_y;
126         u32 tvdetgp_int_start_stop_x;
127         u32 tvdetgp_int_start_stop_y;
128         u32 gen_ctrl;
129 };
130 
131 /* from TRM */
132 static const struct venc_config venc_config_pal_trm = {
133         .f_control                              = 0,
134         .vidout_ctrl                            = 1,
135         .sync_ctrl                              = 0x40,
136         .llen                                   = 0x35F, /* 863 */
137         .flens                                  = 0x270, /* 624 */
138         .hfltr_ctrl                             = 0,
139         .cc_carr_wss_carr                       = 0x2F7225ED,
140         .c_phase                                = 0,
141         .gain_u                                 = 0x111,
142         .gain_v                                 = 0x181,
143         .gain_y                                 = 0x140,
144         .black_level                            = 0x3B,
145         .blank_level                            = 0x3B,
146         .x_color                                = 0x7,
147         .m_control                              = 0x2,
148         .bstamp_wss_data                        = 0x3F,
149         .s_carr                                 = 0x2A098ACB,
150         .line21                                 = 0,
151         .ln_sel                                 = 0x01290015,
152         .l21__wc_ctl                            = 0x0000F603,
153         .htrigger_vtrigger                      = 0,
154 
155         .savid__eavid                           = 0x06A70108,
156         .flen__fal                              = 0x00180270,
157         .lal__phase_reset                       = 0x00040135,
158         .hs_int_start_stop_x                    = 0x00880358,
159         .hs_ext_start_stop_x                    = 0x000F035F,
160         .vs_int_start_x                         = 0x01A70000,
161         .vs_int_stop_x__vs_int_start_y          = 0x000001A7,
162         .vs_int_stop_y__vs_ext_start_x          = 0x01AF0000,
163         .vs_ext_stop_x__vs_ext_start_y          = 0x000101AF,
164         .vs_ext_stop_y                          = 0x00000025,
165         .avid_start_stop_x                      = 0x03530083,
166         .avid_start_stop_y                      = 0x026C002E,
167         .fid_int_start_x__fid_int_start_y       = 0x0001008A,
168         .fid_int_offset_y__fid_ext_start_x      = 0x002E0138,
169         .fid_ext_start_y__fid_ext_offset_y      = 0x01380001,
170 
171         .tvdetgp_int_start_stop_x               = 0x00140001,
172         .tvdetgp_int_start_stop_y               = 0x00010001,
173         .gen_ctrl                               = 0x00FF0000,
174 };
175 
176 /* from TRM */
177 static const struct venc_config venc_config_ntsc_trm = {
178         .f_control                              = 0,
179         .vidout_ctrl                            = 1,
180         .sync_ctrl                              = 0x8040,
181         .llen                                   = 0x359,
182         .flens                                  = 0x20C,
183         .hfltr_ctrl                             = 0,
184         .cc_carr_wss_carr                       = 0x043F2631,
185         .c_phase                                = 0,
186         .gain_u                                 = 0x102,
187         .gain_v                                 = 0x16C,
188         .gain_y                                 = 0x12F,
189         .black_level                            = 0x43,
190         .blank_level                            = 0x38,
191         .x_color                                = 0x7,
192         .m_control                              = 0x1,
193         .bstamp_wss_data                        = 0x38,
194         .s_carr                                 = 0x21F07C1F,
195         .line21                                 = 0,
196         .ln_sel                                 = 0x01310011,
197         .l21__wc_ctl                            = 0x0000F003,
198         .htrigger_vtrigger                      = 0,
199 
200         .savid__eavid                           = 0x069300F4,
201         .flen__fal                              = 0x0016020C,
202         .lal__phase_reset                       = 0x00060107,
203         .hs_int_start_stop_x                    = 0x008E0350,
204         .hs_ext_start_stop_x                    = 0x000F0359,
205         .vs_int_start_x                         = 0x01A00000,
206         .vs_int_stop_x__vs_int_start_y          = 0x020701A0,
207         .vs_int_stop_y__vs_ext_start_x          = 0x01AC0024,
208         .vs_ext_stop_x__vs_ext_start_y          = 0x020D01AC,
209         .vs_ext_stop_y                          = 0x00000006,
210         .avid_start_stop_x                      = 0x03480078,
211         .avid_start_stop_y                      = 0x02060024,
212         .fid_int_start_x__fid_int_start_y       = 0x0001008A,
213         .fid_int_offset_y__fid_ext_start_x      = 0x01AC0106,
214         .fid_ext_start_y__fid_ext_offset_y      = 0x01060006,
215 
216         .tvdetgp_int_start_stop_x               = 0x00140001,
217         .tvdetgp_int_start_stop_y               = 0x00010001,
218         .gen_ctrl                               = 0x00F90000,
219 };
220 
221 static const struct venc_config venc_config_pal_bdghi = {
222         .f_control                              = 0,
223         .vidout_ctrl                            = 0,
224         .sync_ctrl                              = 0,
225         .hfltr_ctrl                             = 0,
226         .x_color                                = 0,
227         .line21                                 = 0,
228         .ln_sel                                 = 21,
229         .htrigger_vtrigger                      = 0,
230         .tvdetgp_int_start_stop_x               = 0x00140001,
231         .tvdetgp_int_start_stop_y               = 0x00010001,
232         .gen_ctrl                               = 0x00FB0000,
233 
234         .llen                                   = 864-1,
235         .flens                                  = 625-1,
236         .cc_carr_wss_carr                       = 0x2F7625ED,
237         .c_phase                                = 0xDF,
238         .gain_u                                 = 0x111,
239         .gain_v                                 = 0x181,
240         .gain_y                                 = 0x140,
241         .black_level                            = 0x3e,
242         .blank_level                            = 0x3e,
243         .m_control                              = 0<<2 | 1<<1,
244         .bstamp_wss_data                        = 0x42,
245         .s_carr                                 = 0x2a098acb,
246         .l21__wc_ctl                            = 0<<13 | 0x16<<8 | 0<<0,
247         .savid__eavid                           = 0x06A70108,
248         .flen__fal                              = 23<<16 | 624<<0,
249         .lal__phase_reset                       = 2<<17 | 310<<0,
250         .hs_int_start_stop_x                    = 0x00920358,
251         .hs_ext_start_stop_x                    = 0x000F035F,
252         .vs_int_start_x                         = 0x1a7<<16,
253         .vs_int_stop_x__vs_int_start_y          = 0x000601A7,
254         .vs_int_stop_y__vs_ext_start_x          = 0x01AF0036,
255         .vs_ext_stop_x__vs_ext_start_y          = 0x27101af,
256         .vs_ext_stop_y                          = 0x05,
257         .avid_start_stop_x                      = 0x03530082,
258         .avid_start_stop_y                      = 0x0270002E,
259         .fid_int_start_x__fid_int_start_y       = 0x0005008A,
260         .fid_int_offset_y__fid_ext_start_x      = 0x002E0138,
261         .fid_ext_start_y__fid_ext_offset_y      = 0x01380005,
262 };
263 
264 const struct omap_video_timings omap_dss_pal_timings = {
265         .x_res          = 720,
266         .y_res          = 574,
267         .pixel_clock    = 13500,
268         .hsw            = 64,
269         .hfp            = 12,
270         .hbp            = 68,
271         .vsw            = 5,
272         .vfp            = 5,
273         .vbp            = 41,
274 
275         .interlace      = true,
276 };
277 EXPORT_SYMBOL(omap_dss_pal_timings);
278 
279 const struct omap_video_timings omap_dss_ntsc_timings = {
280         .x_res          = 720,
281         .y_res          = 482,
282         .pixel_clock    = 13500,
283         .hsw            = 64,
284         .hfp            = 16,
285         .hbp            = 58,
286         .vsw            = 6,
287         .vfp            = 6,
288         .vbp            = 31,
289 
290         .interlace      = true,
291 };
292 EXPORT_SYMBOL(omap_dss_ntsc_timings);
293 
294 static struct {
295         struct platform_device *pdev;
296         void __iomem *base;
297         struct mutex venc_lock;
298         u32 wss_data;
299         struct regulator *vdda_dac_reg;
300 
301         struct clk      *tv_dac_clk;
302 
303         struct omap_video_timings timings;
304         enum omap_dss_venc_type type;
305         bool invert_polarity;
306 
307         struct omap_dss_device output;
308 } venc;
309 
310 static inline void venc_write_reg(int idx, u32 val)
311 {
312         __raw_writel(val, venc.base + idx);
313 }
314 
315 static inline u32 venc_read_reg(int idx)
316 {
317         u32 l = __raw_readl(venc.base + idx);
318         return l;
319 }
320 
321 static void venc_write_config(const struct venc_config *config)
322 {
323         DSSDBG("write venc conf\n");
324 
325         venc_write_reg(VENC_LLEN, config->llen);
326         venc_write_reg(VENC_FLENS, config->flens);
327         venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
328         venc_write_reg(VENC_C_PHASE, config->c_phase);
329         venc_write_reg(VENC_GAIN_U, config->gain_u);
330         venc_write_reg(VENC_GAIN_V, config->gain_v);
331         venc_write_reg(VENC_GAIN_Y, config->gain_y);
332         venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
333         venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
334         venc_write_reg(VENC_M_CONTROL, config->m_control);
335         venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
336                         venc.wss_data);
337         venc_write_reg(VENC_S_CARR, config->s_carr);
338         venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
339         venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
340         venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
341         venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
342         venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
343         venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
344         venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
345         venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
346                        config->vs_int_stop_x__vs_int_start_y);
347         venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
348                        config->vs_int_stop_y__vs_ext_start_x);
349         venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
350                        config->vs_ext_stop_x__vs_ext_start_y);
351         venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
352         venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
353         venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
354         venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
355                        config->fid_int_start_x__fid_int_start_y);
356         venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
357                        config->fid_int_offset_y__fid_ext_start_x);
358         venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
359                        config->fid_ext_start_y__fid_ext_offset_y);
360 
361         venc_write_reg(VENC_DAC_B__DAC_C,  venc_read_reg(VENC_DAC_B__DAC_C));
362         venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
363         venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
364         venc_write_reg(VENC_X_COLOR, config->x_color);
365         venc_write_reg(VENC_LINE21, config->line21);
366         venc_write_reg(VENC_LN_SEL, config->ln_sel);
367         venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
368         venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
369                        config->tvdetgp_int_start_stop_x);
370         venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
371                        config->tvdetgp_int_start_stop_y);
372         venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
373         venc_write_reg(VENC_F_CONTROL, config->f_control);
374         venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
375 }
376 
377 static void venc_reset(void)
378 {
379         int t = 1000;
380 
381         venc_write_reg(VENC_F_CONTROL, 1<<8);
382         while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
383                 if (--t == 0) {
384                         DSSERR("Failed to reset venc\n");
385                         return;
386                 }
387         }
388 
389 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
390         /* the magical sleep that makes things work */
391         /* XXX more info? What bug this circumvents? */
392         msleep(20);
393 #endif
394 }
395 
396 static int venc_runtime_get(void)
397 {
398         int r;
399 
400         DSSDBG("venc_runtime_get\n");
401 
402         r = pm_runtime_get_sync(&venc.pdev->dev);
403         WARN_ON(r < 0);
404         return r < 0 ? r : 0;
405 }
406 
407 static void venc_runtime_put(void)
408 {
409         int r;
410 
411         DSSDBG("venc_runtime_put\n");
412 
413         r = pm_runtime_put_sync(&venc.pdev->dev);
414         WARN_ON(r < 0 && r != -ENOSYS);
415 }
416 
417 static const struct venc_config *venc_timings_to_config(
418                 struct omap_video_timings *timings)
419 {
420         if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
421                 return &venc_config_pal_trm;
422 
423         if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
424                 return &venc_config_ntsc_trm;
425 
426         BUG();
427         return NULL;
428 }
429 
430 static int venc_power_on(struct omap_dss_device *dssdev)
431 {
432         struct omap_overlay_manager *mgr = venc.output.manager;
433         u32 l;
434         int r;
435 
436         r = venc_runtime_get();
437         if (r)
438                 goto err0;
439 
440         venc_reset();
441         venc_write_config(venc_timings_to_config(&venc.timings));
442 
443         dss_set_venc_output(venc.type);
444         dss_set_dac_pwrdn_bgz(1);
445 
446         l = 0;
447 
448         if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
449                 l |= 1 << 1;
450         else /* S-Video */
451                 l |= (1 << 0) | (1 << 2);
452 
453         if (venc.invert_polarity == false)
454                 l |= 1 << 3;
455 
456         venc_write_reg(VENC_OUTPUT_CONTROL, l);
457 
458         dss_mgr_set_timings(mgr, &venc.timings);
459 
460         r = regulator_enable(venc.vdda_dac_reg);
461         if (r)
462                 goto err1;
463 
464         r = dss_mgr_enable(mgr);
465         if (r)
466                 goto err2;
467 
468         return 0;
469 
470 err2:
471         regulator_disable(venc.vdda_dac_reg);
472 err1:
473         venc_write_reg(VENC_OUTPUT_CONTROL, 0);
474         dss_set_dac_pwrdn_bgz(0);
475 
476         venc_runtime_put();
477 err0:
478         return r;
479 }
480 
481 static void venc_power_off(struct omap_dss_device *dssdev)
482 {
483         struct omap_overlay_manager *mgr = venc.output.manager;
484 
485         venc_write_reg(VENC_OUTPUT_CONTROL, 0);
486         dss_set_dac_pwrdn_bgz(0);
487 
488         dss_mgr_disable(mgr);
489 
490         regulator_disable(venc.vdda_dac_reg);
491 
492         venc_runtime_put();
493 }
494 
495 static int venc_display_enable(struct omap_dss_device *dssdev)
496 {
497         struct omap_dss_device *out = &venc.output;
498         int r;
499 
500         DSSDBG("venc_display_enable\n");
501 
502         mutex_lock(&venc.venc_lock);
503 
504         if (out == NULL || out->manager == NULL) {
505                 DSSERR("Failed to enable display: no output/manager\n");
506                 r = -ENODEV;
507                 goto err0;
508         }
509 
510         r = venc_power_on(dssdev);
511         if (r)
512                 goto err0;
513 
514         venc.wss_data = 0;
515 
516         mutex_unlock(&venc.venc_lock);
517 
518         return 0;
519 err0:
520         mutex_unlock(&venc.venc_lock);
521         return r;
522 }
523 
524 static void venc_display_disable(struct omap_dss_device *dssdev)
525 {
526         DSSDBG("venc_display_disable\n");
527 
528         mutex_lock(&venc.venc_lock);
529 
530         venc_power_off(dssdev);
531 
532         mutex_unlock(&venc.venc_lock);
533 }
534 
535 static void venc_set_timings(struct omap_dss_device *dssdev,
536                 struct omap_video_timings *timings)
537 {
538         DSSDBG("venc_set_timings\n");
539 
540         mutex_lock(&venc.venc_lock);
541 
542         /* Reset WSS data when the TV standard changes. */
543         if (memcmp(&venc.timings, timings, sizeof(*timings)))
544                 venc.wss_data = 0;
545 
546         venc.timings = *timings;
547 
548         dispc_set_tv_pclk(13500000);
549 
550         mutex_unlock(&venc.venc_lock);
551 }
552 
553 static int venc_check_timings(struct omap_dss_device *dssdev,
554                 struct omap_video_timings *timings)
555 {
556         DSSDBG("venc_check_timings\n");
557 
558         if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
559                 return 0;
560 
561         if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
562                 return 0;
563 
564         return -EINVAL;
565 }
566 
567 static void venc_get_timings(struct omap_dss_device *dssdev,
568                 struct omap_video_timings *timings)
569 {
570         mutex_lock(&venc.venc_lock);
571 
572         *timings = venc.timings;
573 
574         mutex_unlock(&venc.venc_lock);
575 }
576 
577 static u32 venc_get_wss(struct omap_dss_device *dssdev)
578 {
579         /* Invert due to VENC_L21_WC_CTL:INV=1 */
580         return (venc.wss_data >> 8) ^ 0xfffff;
581 }
582 
583 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
584 {
585         const struct venc_config *config;
586         int r;
587 
588         DSSDBG("venc_set_wss\n");
589 
590         mutex_lock(&venc.venc_lock);
591 
592         config = venc_timings_to_config(&venc.timings);
593 
594         /* Invert due to VENC_L21_WC_CTL:INV=1 */
595         venc.wss_data = (wss ^ 0xfffff) << 8;
596 
597         r = venc_runtime_get();
598         if (r)
599                 goto err;
600 
601         venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
602                         venc.wss_data);
603 
604         venc_runtime_put();
605 
606 err:
607         mutex_unlock(&venc.venc_lock);
608 
609         return r;
610 }
611 
612 static void venc_set_type(struct omap_dss_device *dssdev,
613                 enum omap_dss_venc_type type)
614 {
615         mutex_lock(&venc.venc_lock);
616 
617         venc.type = type;
618 
619         mutex_unlock(&venc.venc_lock);
620 }
621 
622 static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
623                 bool invert_polarity)
624 {
625         mutex_lock(&venc.venc_lock);
626 
627         venc.invert_polarity = invert_polarity;
628 
629         mutex_unlock(&venc.venc_lock);
630 }
631 
632 static int venc_init_regulator(void)
633 {
634         struct regulator *vdda_dac;
635 
636         if (venc.vdda_dac_reg != NULL)
637                 return 0;
638 
639         vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac");
640 
641         if (IS_ERR(vdda_dac)) {
642                 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
643                         DSSERR("can't get VDDA_DAC regulator\n");
644                 return PTR_ERR(vdda_dac);
645         }
646 
647         venc.vdda_dac_reg = vdda_dac;
648 
649         return 0;
650 }
651 
652 static void venc_dump_regs(struct seq_file *s)
653 {
654 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
655 
656         if (venc_runtime_get())
657                 return;
658 
659         DUMPREG(VENC_F_CONTROL);
660         DUMPREG(VENC_VIDOUT_CTRL);
661         DUMPREG(VENC_SYNC_CTRL);
662         DUMPREG(VENC_LLEN);
663         DUMPREG(VENC_FLENS);
664         DUMPREG(VENC_HFLTR_CTRL);
665         DUMPREG(VENC_CC_CARR_WSS_CARR);
666         DUMPREG(VENC_C_PHASE);
667         DUMPREG(VENC_GAIN_U);
668         DUMPREG(VENC_GAIN_V);
669         DUMPREG(VENC_GAIN_Y);
670         DUMPREG(VENC_BLACK_LEVEL);
671         DUMPREG(VENC_BLANK_LEVEL);
672         DUMPREG(VENC_X_COLOR);
673         DUMPREG(VENC_M_CONTROL);
674         DUMPREG(VENC_BSTAMP_WSS_DATA);
675         DUMPREG(VENC_S_CARR);
676         DUMPREG(VENC_LINE21);
677         DUMPREG(VENC_LN_SEL);
678         DUMPREG(VENC_L21__WC_CTL);
679         DUMPREG(VENC_HTRIGGER_VTRIGGER);
680         DUMPREG(VENC_SAVID__EAVID);
681         DUMPREG(VENC_FLEN__FAL);
682         DUMPREG(VENC_LAL__PHASE_RESET);
683         DUMPREG(VENC_HS_INT_START_STOP_X);
684         DUMPREG(VENC_HS_EXT_START_STOP_X);
685         DUMPREG(VENC_VS_INT_START_X);
686         DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
687         DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
688         DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
689         DUMPREG(VENC_VS_EXT_STOP_Y);
690         DUMPREG(VENC_AVID_START_STOP_X);
691         DUMPREG(VENC_AVID_START_STOP_Y);
692         DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
693         DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
694         DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
695         DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
696         DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
697         DUMPREG(VENC_GEN_CTRL);
698         DUMPREG(VENC_OUTPUT_CONTROL);
699         DUMPREG(VENC_OUTPUT_TEST);
700 
701         venc_runtime_put();
702 
703 #undef DUMPREG
704 }
705 
706 static int venc_get_clocks(struct platform_device *pdev)
707 {
708         struct clk *clk;
709 
710         if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
711                 clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
712                 if (IS_ERR(clk)) {
713                         DSSERR("can't get tv_dac_clk\n");
714                         return PTR_ERR(clk);
715                 }
716         } else {
717                 clk = NULL;
718         }
719 
720         venc.tv_dac_clk = clk;
721 
722         return 0;
723 }
724 
725 static int venc_connect(struct omap_dss_device *dssdev,
726                 struct omap_dss_device *dst)
727 {
728         struct omap_overlay_manager *mgr;
729         int r;
730 
731         r = venc_init_regulator();
732         if (r)
733                 return r;
734 
735         mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
736         if (!mgr)
737                 return -ENODEV;
738 
739         r = dss_mgr_connect(mgr, dssdev);
740         if (r)
741                 return r;
742 
743         r = omapdss_output_set_device(dssdev, dst);
744         if (r) {
745                 DSSERR("failed to connect output to new device: %s\n",
746                                 dst->name);
747                 dss_mgr_disconnect(mgr, dssdev);
748                 return r;
749         }
750 
751         return 0;
752 }
753 
754 static void venc_disconnect(struct omap_dss_device *dssdev,
755                 struct omap_dss_device *dst)
756 {
757         WARN_ON(dst != dssdev->dst);
758 
759         if (dst != dssdev->dst)
760                 return;
761 
762         omapdss_output_unset_device(dssdev);
763 
764         if (dssdev->manager)
765                 dss_mgr_disconnect(dssdev->manager, dssdev);
766 }
767 
768 static const struct omapdss_atv_ops venc_ops = {
769         .connect = venc_connect,
770         .disconnect = venc_disconnect,
771 
772         .enable = venc_display_enable,
773         .disable = venc_display_disable,
774 
775         .check_timings = venc_check_timings,
776         .set_timings = venc_set_timings,
777         .get_timings = venc_get_timings,
778 
779         .set_type = venc_set_type,
780         .invert_vid_out_polarity = venc_invert_vid_out_polarity,
781 
782         .set_wss = venc_set_wss,
783         .get_wss = venc_get_wss,
784 };
785 
786 static void venc_init_output(struct platform_device *pdev)
787 {
788         struct omap_dss_device *out = &venc.output;
789 
790         out->dev = &pdev->dev;
791         out->id = OMAP_DSS_OUTPUT_VENC;
792         out->output_type = OMAP_DISPLAY_TYPE_VENC;
793         out->name = "venc.0";
794         out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
795         out->ops.atv = &venc_ops;
796         out->owner = THIS_MODULE;
797 
798         omapdss_register_output(out);
799 }
800 
801 static void __exit venc_uninit_output(struct platform_device *pdev)
802 {
803         struct omap_dss_device *out = &venc.output;
804 
805         omapdss_unregister_output(out);
806 }
807 
808 /* VENC HW IP initialisation */
809 static int omap_venchw_probe(struct platform_device *pdev)
810 {
811         u8 rev_id;
812         struct resource *venc_mem;
813         int r;
814 
815         venc.pdev = pdev;
816 
817         mutex_init(&venc.venc_lock);
818 
819         venc.wss_data = 0;
820 
821         venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
822         if (!venc_mem) {
823                 DSSERR("can't get IORESOURCE_MEM VENC\n");
824                 return -EINVAL;
825         }
826 
827         venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
828                                  resource_size(venc_mem));
829         if (!venc.base) {
830                 DSSERR("can't ioremap VENC\n");
831                 return -ENOMEM;
832         }
833 
834         r = venc_get_clocks(pdev);
835         if (r)
836                 return r;
837 
838         pm_runtime_enable(&pdev->dev);
839 
840         r = venc_runtime_get();
841         if (r)
842                 goto err_runtime_get;
843 
844         rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
845         dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
846 
847         venc_runtime_put();
848 
849         dss_debugfs_create_file("venc", venc_dump_regs);
850 
851         venc_init_output(pdev);
852 
853         return 0;
854 
855 err_runtime_get:
856         pm_runtime_disable(&pdev->dev);
857         return r;
858 }
859 
860 static int __exit omap_venchw_remove(struct platform_device *pdev)
861 {
862         venc_uninit_output(pdev);
863 
864         pm_runtime_disable(&pdev->dev);
865 
866         return 0;
867 }
868 
869 static int venc_runtime_suspend(struct device *dev)
870 {
871         if (venc.tv_dac_clk)
872                 clk_disable_unprepare(venc.tv_dac_clk);
873 
874         dispc_runtime_put();
875 
876         return 0;
877 }
878 
879 static int venc_runtime_resume(struct device *dev)
880 {
881         int r;
882 
883         r = dispc_runtime_get();
884         if (r < 0)
885                 return r;
886 
887         if (venc.tv_dac_clk)
888                 clk_prepare_enable(venc.tv_dac_clk);
889 
890         return 0;
891 }
892 
893 static const struct dev_pm_ops venc_pm_ops = {
894         .runtime_suspend = venc_runtime_suspend,
895         .runtime_resume = venc_runtime_resume,
896 };
897 
898 static struct platform_driver omap_venchw_driver = {
899         .probe          = omap_venchw_probe,
900         .remove         = __exit_p(omap_venchw_remove),
901         .driver         = {
902                 .name   = "omapdss_venc",
903                 .owner  = THIS_MODULE,
904                 .pm     = &venc_pm_ops,
905         },
906 };
907 
908 int __init venc_init_platform_driver(void)
909 {
910         return platform_driver_register(&omap_venchw_driver);
911 }
912 
913 void __exit venc_uninit_platform_driver(void)
914 {
915         platform_driver_unregister(&omap_venchw_driver);
916 }
917 

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