Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/usb/phy/phy-tegra-usb.c

  1 /*
  2  * Copyright (C) 2010 Google, Inc.
  3  * Copyright (C) 2013 NVIDIA Corporation
  4  *
  5  * Author:
  6  *      Erik Gilling <konkers@google.com>
  7  *      Benoit Goby <benoit@android.com>
  8  *      Venu Byravarasu <vbyravarasu@nvidia.com>
  9  *
 10  * This software is licensed under the terms of the GNU General Public
 11  * License version 2, as published by the Free Software Foundation, and
 12  * may be copied, distributed, and modified under those terms.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  * GNU General Public License for more details.
 18  *
 19  */
 20 
 21 #include <linux/resource.h>
 22 #include <linux/delay.h>
 23 #include <linux/slab.h>
 24 #include <linux/err.h>
 25 #include <linux/export.h>
 26 #include <linux/module.h>
 27 #include <linux/platform_device.h>
 28 #include <linux/io.h>
 29 #include <linux/gpio.h>
 30 #include <linux/of.h>
 31 #include <linux/of_device.h>
 32 #include <linux/of_gpio.h>
 33 #include <linux/usb/otg.h>
 34 #include <linux/usb/ulpi.h>
 35 #include <linux/usb/of.h>
 36 #include <asm/mach-types.h>
 37 #include <linux/usb/ehci_def.h>
 38 #include <linux/usb/tegra_usb_phy.h>
 39 #include <linux/regulator/consumer.h>
 40 
 41 #define ULPI_VIEWPORT           0x170
 42 
 43 /* PORTSC PTS/PHCD bits, Tegra20 only */
 44 #define TEGRA_USB_PORTSC1                               0x184
 45 #define TEGRA_USB_PORTSC1_PTS(x)                        (((x) & 0x3) << 30)
 46 #define TEGRA_USB_PORTSC1_PHCD                          (1 << 23)
 47 
 48 /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
 49 #define TEGRA_USB_HOSTPC1_DEVLC         0x1b4
 50 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x)  (((x) & 0x7) << 29)
 51 #define TEGRA_USB_HOSTPC1_DEVLC_PHCD    (1 << 22)
 52 
 53 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
 54 #define TEGRA_PORTSC1_RWC_BITS  (PORT_CSC | PORT_PEC | PORT_OCC)
 55 
 56 #define USB_SUSP_CTRL           0x400
 57 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
 58 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
 59 #define   USB_SUSP_CLR          (1 << 5)
 60 #define   USB_PHY_CLK_VALID     (1 << 7)
 61 #define   UTMIP_RESET                   (1 << 11)
 62 #define   UHSIC_RESET                   (1 << 11)
 63 #define   UTMIP_PHY_ENABLE              (1 << 12)
 64 #define   ULPI_PHY_ENABLE       (1 << 13)
 65 #define   USB_SUSP_SET          (1 << 14)
 66 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
 67 
 68 #define USB1_LEGACY_CTRL        0x410
 69 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
 70 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
 71 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
 72 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
 73                                                 (1 << 1)
 74 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
 75 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
 76 
 77 #define ULPI_TIMING_CTRL_0      0x424
 78 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
 79 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
 80 
 81 #define ULPI_TIMING_CTRL_1      0x428
 82 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
 83 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
 84 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
 85 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
 86 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
 87 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
 88 
 89 #define UTMIP_PLL_CFG1          0x804
 90 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
 91 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
 92 
 93 #define UTMIP_XCVR_CFG0         0x808
 94 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
 95 #define   UTMIP_XCVR_SETUP_MSB(x)               ((((x) & 0x70) >> 4) << 22)
 96 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
 97 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
 98 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
 99 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
100 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
101 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
102 #define   UTMIP_XCVR_HSSLEW(x)                  (((x) & 0x3) << 4)
103 #define   UTMIP_XCVR_HSSLEW_MSB(x)              ((((x) & 0x1fc) >> 2) << 25)
104 
105 #define UTMIP_BIAS_CFG0         0x80c
106 #define   UTMIP_OTGPD                   (1 << 11)
107 #define   UTMIP_BIASPD                  (1 << 10)
108 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
109 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
110 #define   UTMIP_HSDISCON_LEVEL_MSB(x)   ((((x) & 0x4) >> 2) << 24)
111 
112 #define UTMIP_HSRX_CFG0         0x810
113 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
114 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
115 
116 #define UTMIP_HSRX_CFG1         0x814
117 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
118 
119 #define UTMIP_TX_CFG0           0x820
120 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
121 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
122 
123 #define UTMIP_MISC_CFG0         0x824
124 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
125 #define   UTMIP_DPDM_OBSERVE_SEL(x)     (((x) & 0xf) << 27)
126 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
127 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
128 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
129 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
130 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
131 
132 #define UTMIP_MISC_CFG1         0x828
133 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
134 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
135 
136 #define UTMIP_DEBOUNCE_CFG0     0x82c
137 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
138 
139 #define UTMIP_BAT_CHRG_CFG0     0x830
140 #define   UTMIP_PD_CHRG                 (1 << 0)
141 
142 #define UTMIP_SPARE_CFG0        0x834
143 #define   FUSE_SETUP_SEL                (1 << 3)
144 
145 #define UTMIP_XCVR_CFG1         0x838
146 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
147 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
148 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
149 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
150 
151 #define UTMIP_BIAS_CFG1         0x83c
152 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
153 
154 /* For Tegra30 and above only, the address is different in Tegra20 */
155 #define USB_USBMODE             0x1f8
156 #define   USB_USBMODE_MASK              (3 << 0)
157 #define   USB_USBMODE_HOST              (3 << 0)
158 #define   USB_USBMODE_DEVICE            (2 << 0)
159 
160 static DEFINE_SPINLOCK(utmip_pad_lock);
161 static int utmip_pad_count;
162 
163 struct tegra_xtal_freq {
164         int freq;
165         u8 enable_delay;
166         u8 stable_count;
167         u8 active_delay;
168         u8 xtal_freq_count;
169         u16 debounce;
170 };
171 
172 static const struct tegra_xtal_freq tegra_freq_table[] = {
173         {
174                 .freq = 12000000,
175                 .enable_delay = 0x02,
176                 .stable_count = 0x2F,
177                 .active_delay = 0x04,
178                 .xtal_freq_count = 0x76,
179                 .debounce = 0x7530,
180         },
181         {
182                 .freq = 13000000,
183                 .enable_delay = 0x02,
184                 .stable_count = 0x33,
185                 .active_delay = 0x05,
186                 .xtal_freq_count = 0x7F,
187                 .debounce = 0x7EF4,
188         },
189         {
190                 .freq = 19200000,
191                 .enable_delay = 0x03,
192                 .stable_count = 0x4B,
193                 .active_delay = 0x06,
194                 .xtal_freq_count = 0xBB,
195                 .debounce = 0xBB80,
196         },
197         {
198                 .freq = 26000000,
199                 .enable_delay = 0x04,
200                 .stable_count = 0x66,
201                 .active_delay = 0x09,
202                 .xtal_freq_count = 0xFE,
203                 .debounce = 0xFDE8,
204         },
205 };
206 
207 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
208 {
209         void __iomem *base = phy->regs;
210         unsigned long val;
211 
212         if (phy->soc_config->has_hostpc) {
213                 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
214                 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
215                 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
216                 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
217         } else {
218                 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
219                 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
220                 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
221                 writel(val, base + TEGRA_USB_PORTSC1);
222         }
223 }
224 
225 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
226 {
227         void __iomem *base = phy->regs;
228         unsigned long val;
229 
230         if (phy->soc_config->has_hostpc) {
231                 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
232                 if (enable)
233                         val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
234                 else
235                         val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
236                 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
237         } else {
238                 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
239                 if (enable)
240                         val |= TEGRA_USB_PORTSC1_PHCD;
241                 else
242                         val &= ~TEGRA_USB_PORTSC1_PHCD;
243                 writel(val, base + TEGRA_USB_PORTSC1);
244         }
245 }
246 
247 static int utmip_pad_open(struct tegra_usb_phy *phy)
248 {
249         phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
250         if (IS_ERR(phy->pad_clk)) {
251                 pr_err("%s: can't get utmip pad clock\n", __func__);
252                 return PTR_ERR(phy->pad_clk);
253         }
254 
255         return 0;
256 }
257 
258 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
259 {
260         unsigned long val, flags;
261         void __iomem *base = phy->pad_regs;
262         struct tegra_utmip_config *config = phy->config;
263 
264         clk_prepare_enable(phy->pad_clk);
265 
266         spin_lock_irqsave(&utmip_pad_lock, flags);
267 
268         if (utmip_pad_count++ == 0) {
269                 val = readl(base + UTMIP_BIAS_CFG0);
270                 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
271 
272                 if (phy->soc_config->requires_extra_tuning_parameters) {
273                         val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
274                                 UTMIP_HSDISCON_LEVEL(~0) |
275                                 UTMIP_HSDISCON_LEVEL_MSB(~0));
276 
277                         val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
278                         val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
279                         val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
280                 }
281                 writel(val, base + UTMIP_BIAS_CFG0);
282         }
283 
284         spin_unlock_irqrestore(&utmip_pad_lock, flags);
285 
286         clk_disable_unprepare(phy->pad_clk);
287 }
288 
289 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
290 {
291         unsigned long val, flags;
292         void __iomem *base = phy->pad_regs;
293 
294         if (!utmip_pad_count) {
295                 pr_err("%s: utmip pad already powered off\n", __func__);
296                 return -EINVAL;
297         }
298 
299         clk_prepare_enable(phy->pad_clk);
300 
301         spin_lock_irqsave(&utmip_pad_lock, flags);
302 
303         if (--utmip_pad_count == 0) {
304                 val = readl(base + UTMIP_BIAS_CFG0);
305                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
306                 writel(val, base + UTMIP_BIAS_CFG0);
307         }
308 
309         spin_unlock_irqrestore(&utmip_pad_lock, flags);
310 
311         clk_disable_unprepare(phy->pad_clk);
312 
313         return 0;
314 }
315 
316 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
317 {
318         unsigned long timeout = 2000;
319         do {
320                 if ((readl(reg) & mask) == result)
321                         return 0;
322                 udelay(1);
323                 timeout--;
324         } while (timeout);
325         return -1;
326 }
327 
328 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
329 {
330         unsigned long val;
331         void __iomem *base = phy->regs;
332 
333         if (phy->is_legacy_phy) {
334                 val = readl(base + USB_SUSP_CTRL);
335                 val |= USB_SUSP_SET;
336                 writel(val, base + USB_SUSP_CTRL);
337 
338                 udelay(10);
339 
340                 val = readl(base + USB_SUSP_CTRL);
341                 val &= ~USB_SUSP_SET;
342                 writel(val, base + USB_SUSP_CTRL);
343         } else
344                 set_phcd(phy, true);
345 
346         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
347                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
348 }
349 
350 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
351 {
352         unsigned long val;
353         void __iomem *base = phy->regs;
354 
355         if (phy->is_legacy_phy) {
356                 val = readl(base + USB_SUSP_CTRL);
357                 val |= USB_SUSP_CLR;
358                 writel(val, base + USB_SUSP_CTRL);
359 
360                 udelay(10);
361 
362                 val = readl(base + USB_SUSP_CTRL);
363                 val &= ~USB_SUSP_CLR;
364                 writel(val, base + USB_SUSP_CTRL);
365         } else
366                 set_phcd(phy, false);
367 
368         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
369                                                      USB_PHY_CLK_VALID))
370                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
371 }
372 
373 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
374 {
375         unsigned long val;
376         void __iomem *base = phy->regs;
377         struct tegra_utmip_config *config = phy->config;
378 
379         val = readl(base + USB_SUSP_CTRL);
380         val |= UTMIP_RESET;
381         writel(val, base + USB_SUSP_CTRL);
382 
383         if (phy->is_legacy_phy) {
384                 val = readl(base + USB1_LEGACY_CTRL);
385                 val |= USB1_NO_LEGACY_MODE;
386                 writel(val, base + USB1_LEGACY_CTRL);
387         }
388 
389         val = readl(base + UTMIP_TX_CFG0);
390         val |= UTMIP_FS_PREABMLE_J;
391         writel(val, base + UTMIP_TX_CFG0);
392 
393         val = readl(base + UTMIP_HSRX_CFG0);
394         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
395         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
396         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
397         writel(val, base + UTMIP_HSRX_CFG0);
398 
399         val = readl(base + UTMIP_HSRX_CFG1);
400         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
401         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
402         writel(val, base + UTMIP_HSRX_CFG1);
403 
404         val = readl(base + UTMIP_DEBOUNCE_CFG0);
405         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
406         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
407         writel(val, base + UTMIP_DEBOUNCE_CFG0);
408 
409         val = readl(base + UTMIP_MISC_CFG0);
410         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
411         writel(val, base + UTMIP_MISC_CFG0);
412 
413         if (!phy->soc_config->utmi_pll_config_in_car_module) {
414                 val = readl(base + UTMIP_MISC_CFG1);
415                 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
416                         UTMIP_PLLU_STABLE_COUNT(~0));
417                 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
418                         UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
419                 writel(val, base + UTMIP_MISC_CFG1);
420 
421                 val = readl(base + UTMIP_PLL_CFG1);
422                 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
423                         UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
424                 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
425                         UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
426                 writel(val, base + UTMIP_PLL_CFG1);
427         }
428 
429         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
430                 val = readl(base + USB_SUSP_CTRL);
431                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
432                 writel(val, base + USB_SUSP_CTRL);
433 
434                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
435                 val &= ~UTMIP_PD_CHRG;
436                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
437         } else {
438                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
439                 val |= UTMIP_PD_CHRG;
440                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
441         }
442 
443         utmip_pad_power_on(phy);
444 
445         val = readl(base + UTMIP_XCVR_CFG0);
446         val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
447                  UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
448                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
449                  UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
450 
451         if (!config->xcvr_setup_use_fuses) {
452                 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
453                 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
454         }
455         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
456         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
457 
458         if (phy->soc_config->requires_extra_tuning_parameters) {
459                 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
460                 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
461                 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
462         }
463         writel(val, base + UTMIP_XCVR_CFG0);
464 
465         val = readl(base + UTMIP_XCVR_CFG1);
466         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
467                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
468         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
469         writel(val, base + UTMIP_XCVR_CFG1);
470 
471         val = readl(base + UTMIP_BIAS_CFG1);
472         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
473         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
474         writel(val, base + UTMIP_BIAS_CFG1);
475 
476         val = readl(base + UTMIP_SPARE_CFG0);
477         if (config->xcvr_setup_use_fuses)
478                 val |= FUSE_SETUP_SEL;
479         else
480                 val &= ~FUSE_SETUP_SEL;
481         writel(val, base + UTMIP_SPARE_CFG0);
482 
483         if (!phy->is_legacy_phy) {
484                 val = readl(base + USB_SUSP_CTRL);
485                 val |= UTMIP_PHY_ENABLE;
486                 writel(val, base + USB_SUSP_CTRL);
487         }
488 
489         val = readl(base + USB_SUSP_CTRL);
490         val &= ~UTMIP_RESET;
491         writel(val, base + USB_SUSP_CTRL);
492 
493         if (phy->is_legacy_phy) {
494                 val = readl(base + USB1_LEGACY_CTRL);
495                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
496                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
497                 writel(val, base + USB1_LEGACY_CTRL);
498 
499                 val = readl(base + USB_SUSP_CTRL);
500                 val &= ~USB_SUSP_SET;
501                 writel(val, base + USB_SUSP_CTRL);
502         }
503 
504         utmi_phy_clk_enable(phy);
505 
506         if (phy->soc_config->requires_usbmode_setup) {
507                 val = readl(base + USB_USBMODE);
508                 val &= ~USB_USBMODE_MASK;
509                 if (phy->mode == USB_DR_MODE_HOST)
510                         val |= USB_USBMODE_HOST;
511                 else
512                         val |= USB_USBMODE_DEVICE;
513                 writel(val, base + USB_USBMODE);
514         }
515 
516         if (!phy->is_legacy_phy)
517                 set_pts(phy, 0);
518 
519         return 0;
520 }
521 
522 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
523 {
524         unsigned long val;
525         void __iomem *base = phy->regs;
526 
527         utmi_phy_clk_disable(phy);
528 
529         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
530                 val = readl(base + USB_SUSP_CTRL);
531                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
532                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
533                 writel(val, base + USB_SUSP_CTRL);
534         }
535 
536         val = readl(base + USB_SUSP_CTRL);
537         val |= UTMIP_RESET;
538         writel(val, base + USB_SUSP_CTRL);
539 
540         val = readl(base + UTMIP_BAT_CHRG_CFG0);
541         val |= UTMIP_PD_CHRG;
542         writel(val, base + UTMIP_BAT_CHRG_CFG0);
543 
544         val = readl(base + UTMIP_XCVR_CFG0);
545         val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
546                UTMIP_FORCE_PDZI_POWERDOWN;
547         writel(val, base + UTMIP_XCVR_CFG0);
548 
549         val = readl(base + UTMIP_XCVR_CFG1);
550         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
551                UTMIP_FORCE_PDDR_POWERDOWN;
552         writel(val, base + UTMIP_XCVR_CFG1);
553 
554         return utmip_pad_power_off(phy);
555 }
556 
557 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
558 {
559         unsigned long val;
560         void __iomem *base = phy->regs;
561 
562         val = readl(base + UTMIP_TX_CFG0);
563         val |= UTMIP_HS_DISCON_DISABLE;
564         writel(val, base + UTMIP_TX_CFG0);
565 }
566 
567 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
568 {
569         unsigned long val;
570         void __iomem *base = phy->regs;
571 
572         val = readl(base + UTMIP_TX_CFG0);
573         val &= ~UTMIP_HS_DISCON_DISABLE;
574         writel(val, base + UTMIP_TX_CFG0);
575 }
576 
577 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
578                                    enum tegra_usb_phy_port_speed port_speed)
579 {
580         unsigned long val;
581         void __iomem *base = phy->regs;
582 
583         val = readl(base + UTMIP_MISC_CFG0);
584         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
585         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
586                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
587         else
588                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
589         writel(val, base + UTMIP_MISC_CFG0);
590         udelay(1);
591 
592         val = readl(base + UTMIP_MISC_CFG0);
593         val |= UTMIP_DPDM_OBSERVE;
594         writel(val, base + UTMIP_MISC_CFG0);
595         udelay(10);
596 }
597 
598 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
599 {
600         unsigned long val;
601         void __iomem *base = phy->regs;
602 
603         val = readl(base + UTMIP_MISC_CFG0);
604         val &= ~UTMIP_DPDM_OBSERVE;
605         writel(val, base + UTMIP_MISC_CFG0);
606         udelay(10);
607 }
608 
609 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
610 {
611         int ret;
612         unsigned long val;
613         void __iomem *base = phy->regs;
614 
615         ret = gpio_direction_output(phy->reset_gpio, 0);
616         if (ret < 0) {
617                 dev_err(phy->u_phy.dev, "gpio %d not set to 0\n",
618                         phy->reset_gpio);
619                 return ret;
620         }
621         msleep(5);
622         ret = gpio_direction_output(phy->reset_gpio, 1);
623         if (ret < 0) {
624                 dev_err(phy->u_phy.dev, "gpio %d not set to 1\n",
625                         phy->reset_gpio);
626                 return ret;
627         }
628 
629         clk_prepare_enable(phy->clk);
630         msleep(1);
631 
632         val = readl(base + USB_SUSP_CTRL);
633         val |= UHSIC_RESET;
634         writel(val, base + USB_SUSP_CTRL);
635 
636         val = readl(base + ULPI_TIMING_CTRL_0);
637         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
638         writel(val, base + ULPI_TIMING_CTRL_0);
639 
640         val = readl(base + USB_SUSP_CTRL);
641         val |= ULPI_PHY_ENABLE;
642         writel(val, base + USB_SUSP_CTRL);
643 
644         val = 0;
645         writel(val, base + ULPI_TIMING_CTRL_1);
646 
647         val |= ULPI_DATA_TRIMMER_SEL(4);
648         val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
649         val |= ULPI_DIR_TRIMMER_SEL(4);
650         writel(val, base + ULPI_TIMING_CTRL_1);
651         udelay(10);
652 
653         val |= ULPI_DATA_TRIMMER_LOAD;
654         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
655         val |= ULPI_DIR_TRIMMER_LOAD;
656         writel(val, base + ULPI_TIMING_CTRL_1);
657 
658         /* Fix VbusInvalid due to floating VBUS */
659         ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
660         if (ret) {
661                 pr_err("%s: ulpi write failed\n", __func__);
662                 return ret;
663         }
664 
665         ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
666         if (ret) {
667                 pr_err("%s: ulpi write failed\n", __func__);
668                 return ret;
669         }
670 
671         val = readl(base + USB_SUSP_CTRL);
672         val |= USB_SUSP_CLR;
673         writel(val, base + USB_SUSP_CTRL);
674         udelay(100);
675 
676         val = readl(base + USB_SUSP_CTRL);
677         val &= ~USB_SUSP_CLR;
678         writel(val, base + USB_SUSP_CTRL);
679 
680         return 0;
681 }
682 
683 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
684 {
685         clk_disable(phy->clk);
686         return gpio_direction_output(phy->reset_gpio, 0);
687 }
688 
689 static void tegra_usb_phy_close(struct usb_phy *x)
690 {
691         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
692 
693         if (!IS_ERR(phy->vbus))
694                 regulator_disable(phy->vbus);
695 
696         clk_disable_unprepare(phy->pll_u);
697 }
698 
699 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
700 {
701         if (phy->is_ulpi_phy)
702                 return ulpi_phy_power_on(phy);
703         else
704                 return utmi_phy_power_on(phy);
705 }
706 
707 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
708 {
709         if (phy->is_ulpi_phy)
710                 return ulpi_phy_power_off(phy);
711         else
712                 return utmi_phy_power_off(phy);
713 }
714 
715 static int      tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
716 {
717         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
718         if (suspend)
719                 return tegra_usb_phy_power_off(phy);
720         else
721                 return tegra_usb_phy_power_on(phy);
722 }
723 
724 static int ulpi_open(struct tegra_usb_phy *phy)
725 {
726         int err;
727 
728         phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
729         if (IS_ERR(phy->clk)) {
730                 pr_err("%s: can't get ulpi clock\n", __func__);
731                 return PTR_ERR(phy->clk);
732         }
733 
734         err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
735                 "ulpi_phy_reset_b");
736         if (err < 0) {
737                 dev_err(phy->u_phy.dev, "request failed for gpio: %d\n",
738                        phy->reset_gpio);
739                 return err;
740         }
741 
742         err = gpio_direction_output(phy->reset_gpio, 0);
743         if (err < 0) {
744                 dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n",
745                        phy->reset_gpio);
746                 return err;
747         }
748 
749         phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
750         if (!phy->ulpi) {
751                 dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n");
752                 err = -ENOMEM;
753                 return err;
754         }
755 
756         phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
757         return 0;
758 }
759 
760 static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
761 {
762         unsigned long parent_rate;
763         int i;
764         int err;
765 
766         phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
767         if (IS_ERR(phy->pll_u)) {
768                 pr_err("Can't get pll_u clock\n");
769                 return PTR_ERR(phy->pll_u);
770         }
771 
772         err = clk_prepare_enable(phy->pll_u);
773         if (err)
774                 return err;
775 
776         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
777         for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
778                 if (tegra_freq_table[i].freq == parent_rate) {
779                         phy->freq = &tegra_freq_table[i];
780                         break;
781                 }
782         }
783         if (!phy->freq) {
784                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
785                 err = -EINVAL;
786                 goto fail;
787         }
788 
789         if (!IS_ERR(phy->vbus)) {
790                 err = regulator_enable(phy->vbus);
791                 if (err) {
792                         dev_err(phy->u_phy.dev,
793                                 "failed to enable usb vbus regulator: %d\n",
794                                 err);
795                         goto fail;
796                 }
797         }
798 
799         if (phy->is_ulpi_phy)
800                 err = ulpi_open(phy);
801         else
802                 err = utmip_pad_open(phy);
803         if (err < 0)
804                 goto fail;
805 
806         return 0;
807 
808 fail:
809         clk_disable_unprepare(phy->pll_u);
810         return err;
811 }
812 
813 void tegra_usb_phy_preresume(struct usb_phy *x)
814 {
815         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
816 
817         if (!phy->is_ulpi_phy)
818                 utmi_phy_preresume(phy);
819 }
820 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
821 
822 void tegra_usb_phy_postresume(struct usb_phy *x)
823 {
824         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
825 
826         if (!phy->is_ulpi_phy)
827                 utmi_phy_postresume(phy);
828 }
829 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
830 
831 void tegra_ehci_phy_restore_start(struct usb_phy *x,
832                                  enum tegra_usb_phy_port_speed port_speed)
833 {
834         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
835 
836         if (!phy->is_ulpi_phy)
837                 utmi_phy_restore_start(phy, port_speed);
838 }
839 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
840 
841 void tegra_ehci_phy_restore_end(struct usb_phy *x)
842 {
843         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
844 
845         if (!phy->is_ulpi_phy)
846                 utmi_phy_restore_end(phy);
847 }
848 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
849 
850 static int read_utmi_param(struct platform_device *pdev, const char *param,
851                            u8 *dest)
852 {
853         u32 value;
854         int err = of_property_read_u32(pdev->dev.of_node, param, &value);
855         *dest = (u8)value;
856         if (err < 0)
857                 dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n",
858                         param, err);
859         return err;
860 }
861 
862 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
863                           struct platform_device *pdev)
864 {
865         struct resource *res;
866         int err;
867         struct tegra_utmip_config *config;
868 
869         tegra_phy->is_ulpi_phy = false;
870 
871         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
872         if (!res) {
873                 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n");
874                 return  -ENXIO;
875         }
876 
877         tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
878                 resource_size(res));
879         if (!tegra_phy->pad_regs) {
880                 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n");
881                 return -ENOMEM;
882         }
883 
884         tegra_phy->config = devm_kzalloc(&pdev->dev,
885                 sizeof(*tegra_phy->config), GFP_KERNEL);
886         if (!tegra_phy->config) {
887                 dev_err(&pdev->dev,
888                         "unable to allocate memory for USB UTMIP config\n");
889                 return -ENOMEM;
890         }
891 
892         config = tegra_phy->config;
893 
894         err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
895                 &config->hssync_start_delay);
896         if (err < 0)
897                 return err;
898 
899         err = read_utmi_param(pdev, "nvidia,elastic-limit",
900                 &config->elastic_limit);
901         if (err < 0)
902                 return err;
903 
904         err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
905                 &config->idle_wait_delay);
906         if (err < 0)
907                 return err;
908 
909         err = read_utmi_param(pdev, "nvidia,term-range-adj",
910                 &config->term_range_adj);
911         if (err < 0)
912                 return err;
913 
914         err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
915                 &config->xcvr_lsfslew);
916         if (err < 0)
917                 return err;
918 
919         err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
920                 &config->xcvr_lsrslew);
921         if (err < 0)
922                 return err;
923 
924         if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
925                 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
926                         &config->xcvr_hsslew);
927                 if (err < 0)
928                         return err;
929 
930                 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
931                         &config->hssquelch_level);
932                 if (err < 0)
933                         return err;
934 
935                 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
936                         &config->hsdiscon_level);
937                 if (err < 0)
938                         return err;
939         }
940 
941         config->xcvr_setup_use_fuses = of_property_read_bool(
942                 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
943 
944         if (!config->xcvr_setup_use_fuses) {
945                 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
946                         &config->xcvr_setup);
947                 if (err < 0)
948                         return err;
949         }
950 
951         return 0;
952 }
953 
954 static const struct tegra_phy_soc_config tegra20_soc_config = {
955         .utmi_pll_config_in_car_module = false,
956         .has_hostpc = false,
957         .requires_usbmode_setup = false,
958         .requires_extra_tuning_parameters = false,
959 };
960 
961 static const struct tegra_phy_soc_config tegra30_soc_config = {
962         .utmi_pll_config_in_car_module = true,
963         .has_hostpc = true,
964         .requires_usbmode_setup = true,
965         .requires_extra_tuning_parameters = true,
966 };
967 
968 static struct of_device_id tegra_usb_phy_id_table[] = {
969         { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
970         { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
971         { },
972 };
973 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
974 
975 static int tegra_usb_phy_probe(struct platform_device *pdev)
976 {
977         const struct of_device_id *match;
978         struct resource *res;
979         struct tegra_usb_phy *tegra_phy = NULL;
980         struct device_node *np = pdev->dev.of_node;
981         enum usb_phy_interface phy_type;
982         int err;
983 
984         tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
985         if (!tegra_phy) {
986                 dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n");
987                 return -ENOMEM;
988         }
989 
990         match = of_match_device(tegra_usb_phy_id_table, &pdev->dev);
991         if (!match) {
992                 dev_err(&pdev->dev, "Error: No device match found\n");
993                 return -ENODEV;
994         }
995         tegra_phy->soc_config = match->data;
996 
997         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
998         if (!res) {
999                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1000                 return  -ENXIO;
1001         }
1002 
1003         tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1004                 resource_size(res));
1005         if (!tegra_phy->regs) {
1006                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1007                 return -ENOMEM;
1008         }
1009 
1010         tegra_phy->is_legacy_phy =
1011                 of_property_read_bool(np, "nvidia,has-legacy-mode");
1012 
1013         phy_type = of_usb_get_phy_mode(np);
1014         switch (phy_type) {
1015         case USBPHY_INTERFACE_MODE_UTMI:
1016                 err = utmi_phy_probe(tegra_phy, pdev);
1017                 if (err < 0)
1018                         return err;
1019                 break;
1020 
1021         case USBPHY_INTERFACE_MODE_ULPI:
1022                 tegra_phy->is_ulpi_phy = true;
1023 
1024                 tegra_phy->reset_gpio =
1025                         of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
1026                 if (!gpio_is_valid(tegra_phy->reset_gpio)) {
1027                         dev_err(&pdev->dev, "invalid gpio: %d\n",
1028                                 tegra_phy->reset_gpio);
1029                         return tegra_phy->reset_gpio;
1030                 }
1031                 tegra_phy->config = NULL;
1032                 break;
1033 
1034         default:
1035                 dev_err(&pdev->dev, "phy_type is invalid or unsupported\n");
1036                 return -EINVAL;
1037         }
1038 
1039         if (of_find_property(np, "dr_mode", NULL))
1040                 tegra_phy->mode = of_usb_get_dr_mode(np);
1041         else
1042                 tegra_phy->mode = USB_DR_MODE_HOST;
1043 
1044         if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1045                 dev_err(&pdev->dev, "dr_mode is invalid\n");
1046                 return -EINVAL;
1047         }
1048 
1049         /* On some boards, the VBUS regulator doesn't need to be controlled */
1050         if (of_find_property(np, "vbus-supply", NULL)) {
1051                 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1052                 if (IS_ERR(tegra_phy->vbus))
1053                         return PTR_ERR(tegra_phy->vbus);
1054         } else {
1055                 dev_notice(&pdev->dev, "no vbus regulator");
1056                 tegra_phy->vbus = ERR_PTR(-ENODEV);
1057         }
1058 
1059         tegra_phy->u_phy.dev = &pdev->dev;
1060         err = tegra_usb_phy_init(tegra_phy);
1061         if (err < 0)
1062                 return err;
1063 
1064         tegra_phy->u_phy.shutdown = tegra_usb_phy_close;
1065         tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
1066 
1067         platform_set_drvdata(pdev, tegra_phy);
1068 
1069         err = usb_add_phy_dev(&tegra_phy->u_phy);
1070         if (err < 0) {
1071                 tegra_usb_phy_close(&tegra_phy->u_phy);
1072                 return err;
1073         }
1074 
1075         return 0;
1076 }
1077 
1078 static int tegra_usb_phy_remove(struct platform_device *pdev)
1079 {
1080         struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1081 
1082         usb_remove_phy(&tegra_phy->u_phy);
1083 
1084         return 0;
1085 }
1086 
1087 static struct platform_driver tegra_usb_phy_driver = {
1088         .probe          = tegra_usb_phy_probe,
1089         .remove         = tegra_usb_phy_remove,
1090         .driver         = {
1091                 .name   = "tegra-phy",
1092                 .owner  = THIS_MODULE,
1093                 .of_match_table = tegra_usb_phy_id_table,
1094         },
1095 };
1096 module_platform_driver(tegra_usb_phy_driver);
1097 
1098 MODULE_DESCRIPTION("Tegra USB PHY driver");
1099 MODULE_LICENSE("GPL v2");
1100 

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