Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/usb/phy/phy-mxs-usb.c

  1 /*
  2  * Copyright 2012-2014 Freescale Semiconductor, Inc.
  3  * Copyright (C) 2012 Marek Vasut <marex@denx.de>
  4  * on behalf of DENX Software Engineering GmbH
  5  *
  6  * The code contained herein is licensed under the GNU General Public
  7  * License. You may obtain a copy of the GNU General Public License
  8  * Version 2 or later at the following locations:
  9  *
 10  * http://www.opensource.org/licenses/gpl-license.html
 11  * http://www.gnu.org/copyleft/gpl.html
 12  */
 13 
 14 #include <linux/module.h>
 15 #include <linux/kernel.h>
 16 #include <linux/platform_device.h>
 17 #include <linux/clk.h>
 18 #include <linux/usb/otg.h>
 19 #include <linux/stmp_device.h>
 20 #include <linux/delay.h>
 21 #include <linux/err.h>
 22 #include <linux/io.h>
 23 #include <linux/of_device.h>
 24 #include <linux/regmap.h>
 25 #include <linux/mfd/syscon.h>
 26 
 27 #define DRIVER_NAME "mxs_phy"
 28 
 29 #define HW_USBPHY_PWD                           0x00
 30 #define HW_USBPHY_CTRL                          0x30
 31 #define HW_USBPHY_CTRL_SET                      0x34
 32 #define HW_USBPHY_CTRL_CLR                      0x38
 33 
 34 #define HW_USBPHY_DEBUG_SET                     0x54
 35 #define HW_USBPHY_DEBUG_CLR                     0x58
 36 
 37 #define HW_USBPHY_IP                            0x90
 38 #define HW_USBPHY_IP_SET                        0x94
 39 #define HW_USBPHY_IP_CLR                        0x98
 40 
 41 #define BM_USBPHY_CTRL_SFTRST                   BIT(31)
 42 #define BM_USBPHY_CTRL_CLKGATE                  BIT(30)
 43 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS        BIT(26)
 44 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE     BIT(25)
 45 #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP           BIT(23)
 46 #define BM_USBPHY_CTRL_ENIDCHG_WKUP             BIT(22)
 47 #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP           BIT(21)
 48 #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD        BIT(20)
 49 #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE        BIT(19)
 50 #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL         BIT(18)
 51 #define BM_USBPHY_CTRL_ENUTMILEVEL3             BIT(15)
 52 #define BM_USBPHY_CTRL_ENUTMILEVEL2             BIT(14)
 53 #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT       BIT(1)
 54 
 55 #define BM_USBPHY_IP_FIX                       (BIT(17) | BIT(18))
 56 
 57 #define BM_USBPHY_DEBUG_CLKGATE                 BIT(30)
 58 
 59 /* Anatop Registers */
 60 #define ANADIG_ANA_MISC0                        0x150
 61 #define ANADIG_ANA_MISC0_SET                    0x154
 62 #define ANADIG_ANA_MISC0_CLR                    0x158
 63 
 64 #define ANADIG_USB1_VBUS_DET_STAT               0x1c0
 65 #define ANADIG_USB2_VBUS_DET_STAT               0x220
 66 
 67 #define ANADIG_USB1_LOOPBACK_SET                0x1e4
 68 #define ANADIG_USB1_LOOPBACK_CLR                0x1e8
 69 #define ANADIG_USB2_LOOPBACK_SET                0x244
 70 #define ANADIG_USB2_LOOPBACK_CLR                0x248
 71 
 72 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG    BIT(12)
 73 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11)
 74 
 75 #define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3)
 76 #define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3)
 77 
 78 #define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1   BIT(2)
 79 #define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN      BIT(5)
 80 #define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1   BIT(2)
 81 #define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN      BIT(5)
 82 
 83 #define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
 84 
 85 /* Do disconnection between PHY and controller without vbus */
 86 #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS    BIT(0)
 87 
 88 /*
 89  * The PHY will be in messy if there is a wakeup after putting
 90  * bus to suspend (set portsc.suspendM) but before setting PHY to low
 91  * power mode (set portsc.phcd).
 92  */
 93 #define MXS_PHY_ABNORMAL_IN_SUSPEND             BIT(1)
 94 
 95 /*
 96  * The SOF sends too fast after resuming, it will cause disconnection
 97  * between host and high speed device.
 98  */
 99 #define MXS_PHY_SENDING_SOF_TOO_FAST            BIT(2)
100 
101 /*
102  * IC has bug fixes logic, they include
103  * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST
104  * which are described at above flags, the RTL will handle it
105  * according to different versions.
106  */
107 #define MXS_PHY_NEED_IP_FIX                     BIT(3)
108 
109 struct mxs_phy_data {
110         unsigned int flags;
111 };
112 
113 static const struct mxs_phy_data imx23_phy_data = {
114         .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST,
115 };
116 
117 static const struct mxs_phy_data imx6q_phy_data = {
118         .flags = MXS_PHY_SENDING_SOF_TOO_FAST |
119                 MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
120                 MXS_PHY_NEED_IP_FIX,
121 };
122 
123 static const struct mxs_phy_data imx6sl_phy_data = {
124         .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
125                 MXS_PHY_NEED_IP_FIX,
126 };
127 
128 static const struct mxs_phy_data imx6sx_phy_data = {
129         .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
130                 MXS_PHY_NEED_IP_FIX,
131 };
132 
133 static const struct of_device_id mxs_phy_dt_ids[] = {
134         { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, },
135         { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
136         { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
137         { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
138         { /* sentinel */ }
139 };
140 MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
141 
142 struct mxs_phy {
143         struct usb_phy phy;
144         struct clk *clk;
145         const struct mxs_phy_data *data;
146         struct regmap *regmap_anatop;
147         int port_id;
148 };
149 
150 static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy)
151 {
152         return mxs_phy->data == &imx6q_phy_data;
153 }
154 
155 static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy)
156 {
157         return mxs_phy->data == &imx6sl_phy_data;
158 }
159 
160 /*
161  * PHY needs some 32K cycles to switch from 32K clock to
162  * bus (such as AHB/AXI, etc) clock.
163  */
164 static void mxs_phy_clock_switch_delay(void)
165 {
166         usleep_range(300, 400);
167 }
168 
169 static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
170 {
171         int ret;
172         void __iomem *base = mxs_phy->phy.io_priv;
173 
174         ret = stmp_reset_block(base + HW_USBPHY_CTRL);
175         if (ret)
176                 return ret;
177 
178         /* Power up the PHY */
179         writel(0, base + HW_USBPHY_PWD);
180 
181         /*
182          * USB PHY Ctrl Setting
183          * - Auto clock/power on
184          * - Enable full/low speed support
185          */
186         writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
187                 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
188                 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
189                 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
190                 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL |
191                 BM_USBPHY_CTRL_ENUTMILEVEL2 |
192                 BM_USBPHY_CTRL_ENUTMILEVEL3,
193                base + HW_USBPHY_CTRL_SET);
194 
195         if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX)
196                 writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);
197 
198         return 0;
199 }
200 
201 /* Return true if the vbus is there */
202 static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy)
203 {
204         unsigned int vbus_value;
205 
206         if (mxs_phy->port_id == 0)
207                 regmap_read(mxs_phy->regmap_anatop,
208                         ANADIG_USB1_VBUS_DET_STAT,
209                         &vbus_value);
210         else if (mxs_phy->port_id == 1)
211                 regmap_read(mxs_phy->regmap_anatop,
212                         ANADIG_USB2_VBUS_DET_STAT,
213                         &vbus_value);
214 
215         if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)
216                 return true;
217         else
218                 return false;
219 }
220 
221 static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect)
222 {
223         void __iomem *base = mxs_phy->phy.io_priv;
224         u32 reg;
225 
226         if (disconnect)
227                 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
228                         base + HW_USBPHY_DEBUG_CLR);
229 
230         if (mxs_phy->port_id == 0) {
231                 reg = disconnect ? ANADIG_USB1_LOOPBACK_SET
232                         : ANADIG_USB1_LOOPBACK_CLR;
233                 regmap_write(mxs_phy->regmap_anatop, reg,
234                         BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 |
235                         BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN);
236         } else if (mxs_phy->port_id == 1) {
237                 reg = disconnect ? ANADIG_USB2_LOOPBACK_SET
238                         : ANADIG_USB2_LOOPBACK_CLR;
239                 regmap_write(mxs_phy->regmap_anatop, reg,
240                         BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 |
241                         BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN);
242         }
243 
244         if (!disconnect)
245                 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
246                         base + HW_USBPHY_DEBUG_SET);
247 
248         /* Delay some time, and let Linestate be SE0 for controller */
249         if (disconnect)
250                 usleep_range(500, 1000);
251 }
252 
253 static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on)
254 {
255         bool vbus_is_on = false;
256 
257         /* If the SoCs don't need to disconnect line without vbus, quit */
258         if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS))
259                 return;
260 
261         /* If the SoCs don't have anatop, quit */
262         if (!mxs_phy->regmap_anatop)
263                 return;
264 
265         vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
266 
267         if (on && !vbus_is_on)
268                 __mxs_phy_disconnect_line(mxs_phy, true);
269         else
270                 __mxs_phy_disconnect_line(mxs_phy, false);
271 
272 }
273 
274 static int mxs_phy_init(struct usb_phy *phy)
275 {
276         int ret;
277         struct mxs_phy *mxs_phy = to_mxs_phy(phy);
278 
279         mxs_phy_clock_switch_delay();
280         ret = clk_prepare_enable(mxs_phy->clk);
281         if (ret)
282                 return ret;
283 
284         return mxs_phy_hw_init(mxs_phy);
285 }
286 
287 static void mxs_phy_shutdown(struct usb_phy *phy)
288 {
289         struct mxs_phy *mxs_phy = to_mxs_phy(phy);
290 
291         writel(BM_USBPHY_CTRL_CLKGATE,
292                phy->io_priv + HW_USBPHY_CTRL_SET);
293 
294         clk_disable_unprepare(mxs_phy->clk);
295 }
296 
297 static int mxs_phy_suspend(struct usb_phy *x, int suspend)
298 {
299         int ret;
300         struct mxs_phy *mxs_phy = to_mxs_phy(x);
301 
302         if (suspend) {
303                 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
304                 writel(BM_USBPHY_CTRL_CLKGATE,
305                        x->io_priv + HW_USBPHY_CTRL_SET);
306                 clk_disable_unprepare(mxs_phy->clk);
307         } else {
308                 mxs_phy_clock_switch_delay();
309                 ret = clk_prepare_enable(mxs_phy->clk);
310                 if (ret)
311                         return ret;
312                 writel(BM_USBPHY_CTRL_CLKGATE,
313                        x->io_priv + HW_USBPHY_CTRL_CLR);
314                 writel(0, x->io_priv + HW_USBPHY_PWD);
315         }
316 
317         return 0;
318 }
319 
320 static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled)
321 {
322         struct mxs_phy *mxs_phy = to_mxs_phy(x);
323         u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP |
324                         BM_USBPHY_CTRL_ENDPDMCHG_WKUP |
325                                 BM_USBPHY_CTRL_ENIDCHG_WKUP;
326         if (enabled) {
327                 mxs_phy_disconnect_line(mxs_phy, true);
328                 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET);
329         } else {
330                 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR);
331                 mxs_phy_disconnect_line(mxs_phy, false);
332         }
333 
334         return 0;
335 }
336 
337 static int mxs_phy_on_connect(struct usb_phy *phy,
338                 enum usb_device_speed speed)
339 {
340         dev_dbg(phy->dev, "%s device has connected\n",
341                 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
342 
343         if (speed == USB_SPEED_HIGH)
344                 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
345                        phy->io_priv + HW_USBPHY_CTRL_SET);
346 
347         return 0;
348 }
349 
350 static int mxs_phy_on_disconnect(struct usb_phy *phy,
351                 enum usb_device_speed speed)
352 {
353         dev_dbg(phy->dev, "%s device has disconnected\n",
354                 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
355 
356         if (speed == USB_SPEED_HIGH)
357                 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
358                        phy->io_priv + HW_USBPHY_CTRL_CLR);
359 
360         return 0;
361 }
362 
363 static int mxs_phy_probe(struct platform_device *pdev)
364 {
365         struct resource *res;
366         void __iomem *base;
367         struct clk *clk;
368         struct mxs_phy *mxs_phy;
369         int ret;
370         const struct of_device_id *of_id =
371                         of_match_device(mxs_phy_dt_ids, &pdev->dev);
372         struct device_node *np = pdev->dev.of_node;
373 
374         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
375         base = devm_ioremap_resource(&pdev->dev, res);
376         if (IS_ERR(base))
377                 return PTR_ERR(base);
378 
379         clk = devm_clk_get(&pdev->dev, NULL);
380         if (IS_ERR(clk)) {
381                 dev_err(&pdev->dev,
382                         "can't get the clock, err=%ld", PTR_ERR(clk));
383                 return PTR_ERR(clk);
384         }
385 
386         mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL);
387         if (!mxs_phy) {
388                 dev_err(&pdev->dev, "Failed to allocate USB PHY structure!\n");
389                 return -ENOMEM;
390         }
391 
392         /* Some SoCs don't have anatop registers */
393         if (of_get_property(np, "fsl,anatop", NULL)) {
394                 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle
395                         (np, "fsl,anatop");
396                 if (IS_ERR(mxs_phy->regmap_anatop)) {
397                         dev_dbg(&pdev->dev,
398                                 "failed to find regmap for anatop\n");
399                         return PTR_ERR(mxs_phy->regmap_anatop);
400                 }
401         }
402 
403         ret = of_alias_get_id(np, "usbphy");
404         if (ret < 0)
405                 dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret);
406         mxs_phy->port_id = ret;
407 
408         mxs_phy->phy.io_priv            = base;
409         mxs_phy->phy.dev                = &pdev->dev;
410         mxs_phy->phy.label              = DRIVER_NAME;
411         mxs_phy->phy.init               = mxs_phy_init;
412         mxs_phy->phy.shutdown           = mxs_phy_shutdown;
413         mxs_phy->phy.set_suspend        = mxs_phy_suspend;
414         mxs_phy->phy.notify_connect     = mxs_phy_on_connect;
415         mxs_phy->phy.notify_disconnect  = mxs_phy_on_disconnect;
416         mxs_phy->phy.type               = USB_PHY_TYPE_USB2;
417         mxs_phy->phy.set_wakeup         = mxs_phy_set_wakeup;
418 
419         mxs_phy->clk = clk;
420         mxs_phy->data = of_id->data;
421 
422         platform_set_drvdata(pdev, mxs_phy);
423 
424         device_set_wakeup_capable(&pdev->dev, true);
425 
426         ret = usb_add_phy_dev(&mxs_phy->phy);
427         if (ret)
428                 return ret;
429 
430         return 0;
431 }
432 
433 static int mxs_phy_remove(struct platform_device *pdev)
434 {
435         struct mxs_phy *mxs_phy = platform_get_drvdata(pdev);
436 
437         usb_remove_phy(&mxs_phy->phy);
438 
439         return 0;
440 }
441 
442 #ifdef CONFIG_PM_SLEEP
443 static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on)
444 {
445         unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR;
446 
447         /* If the SoCs don't have anatop, quit */
448         if (!mxs_phy->regmap_anatop)
449                 return;
450 
451         if (is_imx6q_phy(mxs_phy))
452                 regmap_write(mxs_phy->regmap_anatop, reg,
453                         BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG);
454         else if (is_imx6sl_phy(mxs_phy))
455                 regmap_write(mxs_phy->regmap_anatop,
456                         reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL);
457 }
458 
459 static int mxs_phy_system_suspend(struct device *dev)
460 {
461         struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
462 
463         if (device_may_wakeup(dev))
464                 mxs_phy_enable_ldo_in_suspend(mxs_phy, true);
465 
466         return 0;
467 }
468 
469 static int mxs_phy_system_resume(struct device *dev)
470 {
471         struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
472 
473         if (device_may_wakeup(dev))
474                 mxs_phy_enable_ldo_in_suspend(mxs_phy, false);
475 
476         return 0;
477 }
478 #endif /* CONFIG_PM_SLEEP */
479 
480 static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend,
481                 mxs_phy_system_resume);
482 
483 static struct platform_driver mxs_phy_driver = {
484         .probe = mxs_phy_probe,
485         .remove = mxs_phy_remove,
486         .driver = {
487                 .name = DRIVER_NAME,
488                 .owner  = THIS_MODULE,
489                 .of_match_table = mxs_phy_dt_ids,
490                 .pm = &mxs_phy_pm,
491          },
492 };
493 
494 static int __init mxs_phy_module_init(void)
495 {
496         return platform_driver_register(&mxs_phy_driver);
497 }
498 postcore_initcall(mxs_phy_module_init);
499 
500 static void __exit mxs_phy_module_exit(void)
501 {
502         platform_driver_unregister(&mxs_phy_driver);
503 }
504 module_exit(mxs_phy_module_exit);
505 
506 MODULE_ALIAS("platform:mxs-usb-phy");
507 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
508 MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
509 MODULE_DESCRIPTION("Freescale MXS USB PHY driver");
510 MODULE_LICENSE("GPL");
511 

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