Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/usb/phy/phy-msm-usb.c

  1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
  2  *
  3  * This program is free software; you can redistribute it and/or modify
  4  * it under the terms of the GNU General Public License version 2 and
  5  * only version 2 as published by the Free Software Foundation.
  6  *
  7  * This program is distributed in the hope that it will be useful,
  8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 10  * GNU General Public License for more details.
 11  *
 12  * You should have received a copy of the GNU General Public License
 13  * along with this program; if not, write to the Free Software
 14  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 15  * 02110-1301, USA.
 16  *
 17  */
 18 
 19 #include <linux/module.h>
 20 #include <linux/device.h>
 21 #include <linux/gpio/consumer.h>
 22 #include <linux/platform_device.h>
 23 #include <linux/clk.h>
 24 #include <linux/slab.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/err.h>
 27 #include <linux/delay.h>
 28 #include <linux/io.h>
 29 #include <linux/ioport.h>
 30 #include <linux/uaccess.h>
 31 #include <linux/debugfs.h>
 32 #include <linux/seq_file.h>
 33 #include <linux/pm_runtime.h>
 34 #include <linux/of.h>
 35 #include <linux/of_device.h>
 36 #include <linux/reboot.h>
 37 #include <linux/reset.h>
 38 
 39 #include <linux/usb.h>
 40 #include <linux/usb/otg.h>
 41 #include <linux/usb/of.h>
 42 #include <linux/usb/ulpi.h>
 43 #include <linux/usb/gadget.h>
 44 #include <linux/usb/hcd.h>
 45 #include <linux/usb/msm_hsusb.h>
 46 #include <linux/usb/msm_hsusb_hw.h>
 47 #include <linux/regulator/consumer.h>
 48 
 49 #define MSM_USB_BASE    (motg->regs)
 50 #define DRIVER_NAME     "msm_otg"
 51 
 52 #define ULPI_IO_TIMEOUT_USEC    (10 * 1000)
 53 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
 54 
 55 #define USB_PHY_3P3_VOL_MIN     3050000 /* uV */
 56 #define USB_PHY_3P3_VOL_MAX     3300000 /* uV */
 57 #define USB_PHY_3P3_HPM_LOAD    50000   /* uA */
 58 #define USB_PHY_3P3_LPM_LOAD    4000    /* uA */
 59 
 60 #define USB_PHY_1P8_VOL_MIN     1800000 /* uV */
 61 #define USB_PHY_1P8_VOL_MAX     1800000 /* uV */
 62 #define USB_PHY_1P8_HPM_LOAD    50000   /* uA */
 63 #define USB_PHY_1P8_LPM_LOAD    4000    /* uA */
 64 
 65 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
 66 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
 67 #define USB_PHY_SUSP_DIG_VOL    500000  /* uV */
 68 
 69 enum vdd_levels {
 70         VDD_LEVEL_NONE = 0,
 71         VDD_LEVEL_MIN,
 72         VDD_LEVEL_MAX,
 73 };
 74 
 75 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
 76 {
 77         int ret = 0;
 78 
 79         if (init) {
 80                 ret = regulator_set_voltage(motg->vddcx,
 81                                 motg->vdd_levels[VDD_LEVEL_MIN],
 82                                 motg->vdd_levels[VDD_LEVEL_MAX]);
 83                 if (ret) {
 84                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
 85                         return ret;
 86                 }
 87 
 88                 ret = regulator_enable(motg->vddcx);
 89                 if (ret)
 90                         dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
 91         } else {
 92                 ret = regulator_set_voltage(motg->vddcx, 0,
 93                                 motg->vdd_levels[VDD_LEVEL_MAX]);
 94                 if (ret)
 95                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
 96                 ret = regulator_disable(motg->vddcx);
 97                 if (ret)
 98                         dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
 99         }
100 
101         return ret;
102 }
103 
104 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
105 {
106         int rc = 0;
107 
108         if (init) {
109                 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
110                                 USB_PHY_3P3_VOL_MAX);
111                 if (rc) {
112                         dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
113                         goto exit;
114                 }
115                 rc = regulator_enable(motg->v3p3);
116                 if (rc) {
117                         dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
118                         goto exit;
119                 }
120                 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
121                                 USB_PHY_1P8_VOL_MAX);
122                 if (rc) {
123                         dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
124                         goto disable_3p3;
125                 }
126                 rc = regulator_enable(motg->v1p8);
127                 if (rc) {
128                         dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
129                         goto disable_3p3;
130                 }
131 
132                 return 0;
133         }
134 
135         regulator_disable(motg->v1p8);
136 disable_3p3:
137         regulator_disable(motg->v3p3);
138 exit:
139         return rc;
140 }
141 
142 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
143 {
144         int ret = 0;
145 
146         if (on) {
147                 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_HPM_LOAD);
148                 if (ret < 0) {
149                         pr_err("Could not set HPM for v1p8\n");
150                         return ret;
151                 }
152                 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_HPM_LOAD);
153                 if (ret < 0) {
154                         pr_err("Could not set HPM for v3p3\n");
155                         regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
156                         return ret;
157                 }
158         } else {
159                 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
160                 if (ret < 0)
161                         pr_err("Could not set LPM for v1p8\n");
162                 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_LPM_LOAD);
163                 if (ret < 0)
164                         pr_err("Could not set LPM for v3p3\n");
165         }
166 
167         pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
168         return ret < 0 ? ret : 0;
169 }
170 
171 static int ulpi_read(struct usb_phy *phy, u32 reg)
172 {
173         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
174         int cnt = 0;
175 
176         /* initiate read operation */
177         writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
178                USB_ULPI_VIEWPORT);
179 
180         /* wait for completion */
181         while (cnt < ULPI_IO_TIMEOUT_USEC) {
182                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
183                         break;
184                 udelay(1);
185                 cnt++;
186         }
187 
188         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
189                 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
190                         readl(USB_ULPI_VIEWPORT));
191                 return -ETIMEDOUT;
192         }
193         return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
194 }
195 
196 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
197 {
198         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
199         int cnt = 0;
200 
201         /* initiate write operation */
202         writel(ULPI_RUN | ULPI_WRITE |
203                ULPI_ADDR(reg) | ULPI_DATA(val),
204                USB_ULPI_VIEWPORT);
205 
206         /* wait for completion */
207         while (cnt < ULPI_IO_TIMEOUT_USEC) {
208                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
209                         break;
210                 udelay(1);
211                 cnt++;
212         }
213 
214         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
215                 dev_err(phy->dev, "ulpi_write: timeout\n");
216                 return -ETIMEDOUT;
217         }
218         return 0;
219 }
220 
221 static struct usb_phy_io_ops msm_otg_io_ops = {
222         .read = ulpi_read,
223         .write = ulpi_write,
224 };
225 
226 static void ulpi_init(struct msm_otg *motg)
227 {
228         struct msm_otg_platform_data *pdata = motg->pdata;
229         int *seq = pdata->phy_init_seq, idx;
230         u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
231 
232         for (idx = 0; idx < pdata->phy_init_sz; idx++) {
233                 if (seq[idx] == -1)
234                         continue;
235 
236                 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
237                                 seq[idx], addr + idx);
238                 ulpi_write(&motg->phy, seq[idx], addr + idx);
239         }
240 }
241 
242 static int msm_phy_notify_disconnect(struct usb_phy *phy,
243                                    enum usb_device_speed speed)
244 {
245         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
246         int val;
247 
248         if (motg->manual_pullup) {
249                 val = ULPI_MISC_A_VBUSVLDEXT | ULPI_MISC_A_VBUSVLDEXTSEL;
250                 usb_phy_io_write(phy, val, ULPI_CLR(ULPI_MISC_A));
251         }
252 
253         /*
254          * Put the transceiver in non-driving mode. Otherwise host
255          * may not detect soft-disconnection.
256          */
257         val = ulpi_read(phy, ULPI_FUNC_CTRL);
258         val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
259         val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
260         ulpi_write(phy, val, ULPI_FUNC_CTRL);
261 
262         return 0;
263 }
264 
265 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
266 {
267         int ret;
268 
269         if (assert)
270                 ret = reset_control_assert(motg->link_rst);
271         else
272                 ret = reset_control_deassert(motg->link_rst);
273 
274         if (ret)
275                 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
276                         assert ? "assert" : "deassert");
277 
278         return ret;
279 }
280 
281 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
282 {
283         int ret = 0;
284 
285         if (motg->phy_rst)
286                 ret = reset_control_reset(motg->phy_rst);
287 
288         if (ret)
289                 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
290 
291         return ret;
292 }
293 
294 static int msm_link_reset(struct msm_otg *motg)
295 {
296         u32 val;
297         int ret;
298 
299         ret = msm_otg_link_clk_reset(motg, 1);
300         if (ret)
301                 return ret;
302 
303         /* wait for 1ms delay as suggested in HPG. */
304         usleep_range(1000, 1200);
305 
306         ret = msm_otg_link_clk_reset(motg, 0);
307         if (ret)
308                 return ret;
309 
310         if (motg->phy_number)
311                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
312 
313         /* put transceiver in serial mode as part of reset */
314         val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
315         writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
316 
317         return 0;
318 }
319 
320 static int msm_otg_reset(struct usb_phy *phy)
321 {
322         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
323         int cnt = 0;
324 
325         writel(USBCMD_RESET, USB_USBCMD);
326         while (cnt < LINK_RESET_TIMEOUT_USEC) {
327                 if (!(readl(USB_USBCMD) & USBCMD_RESET))
328                         break;
329                 udelay(1);
330                 cnt++;
331         }
332         if (cnt >= LINK_RESET_TIMEOUT_USEC)
333                 return -ETIMEDOUT;
334 
335         /* select ULPI phy and clear other status/control bits in PORTSC */
336         writel(PORTSC_PTS_ULPI, USB_PORTSC);
337 
338         writel(0x0, USB_AHBBURST);
339         writel(0x08, USB_AHBMODE);
340 
341         if (motg->phy_number)
342                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
343         return 0;
344 }
345 
346 static void msm_phy_reset(struct msm_otg *motg)
347 {
348         void __iomem *addr;
349 
350         if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
351                 msm_otg_phy_clk_reset(motg);
352                 return;
353         }
354 
355         addr = USB_PHY_CTRL;
356         if (motg->phy_number)
357                 addr = USB_PHY_CTRL2;
358 
359         /* Assert USB PHY_POR */
360         writel(readl(addr) | PHY_POR_ASSERT, addr);
361 
362         /*
363          * wait for minimum 10 microseconds as suggested in HPG.
364          * Use a slightly larger value since the exact value didn't
365          * work 100% of the time.
366          */
367         udelay(12);
368 
369         /* Deassert USB PHY_POR */
370         writel(readl(addr) & ~PHY_POR_ASSERT, addr);
371 }
372 
373 static int msm_usb_reset(struct usb_phy *phy)
374 {
375         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
376         int ret;
377 
378         if (!IS_ERR(motg->core_clk))
379                 clk_prepare_enable(motg->core_clk);
380 
381         ret = msm_link_reset(motg);
382         if (ret) {
383                 dev_err(phy->dev, "phy_reset failed\n");
384                 return ret;
385         }
386 
387         ret = msm_otg_reset(&motg->phy);
388         if (ret) {
389                 dev_err(phy->dev, "link reset failed\n");
390                 return ret;
391         }
392 
393         msleep(100);
394 
395         /* Reset USB PHY after performing USB Link RESET */
396         msm_phy_reset(motg);
397 
398         if (!IS_ERR(motg->core_clk))
399                 clk_disable_unprepare(motg->core_clk);
400 
401         return 0;
402 }
403 
404 static int msm_phy_init(struct usb_phy *phy)
405 {
406         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
407         struct msm_otg_platform_data *pdata = motg->pdata;
408         u32 val, ulpi_val = 0;
409 
410         /* Program USB PHY Override registers. */
411         ulpi_init(motg);
412 
413         /*
414          * It is recommended in HPG to reset USB PHY after programming
415          * USB PHY Override registers.
416          */
417         msm_phy_reset(motg);
418 
419         if (pdata->otg_control == OTG_PHY_CONTROL) {
420                 val = readl(USB_OTGSC);
421                 if (pdata->mode == USB_DR_MODE_OTG) {
422                         ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
423                         val |= OTGSC_IDIE | OTGSC_BSVIE;
424                 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
425                         ulpi_val = ULPI_INT_SESS_VALID;
426                         val |= OTGSC_BSVIE;
427                 }
428                 writel(val, USB_OTGSC);
429                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
430                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
431         }
432 
433         if (motg->manual_pullup) {
434                 val = ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT;
435                 ulpi_write(phy, val, ULPI_SET(ULPI_MISC_A));
436 
437                 val = readl(USB_GENCONFIG_2);
438                 val |= GENCONFIG_2_SESS_VLD_CTRL_EN;
439                 writel(val, USB_GENCONFIG_2);
440 
441                 val = readl(USB_USBCMD);
442                 val |= USBCMD_SESS_VLD_CTRL;
443                 writel(val, USB_USBCMD);
444 
445                 val = ulpi_read(phy, ULPI_FUNC_CTRL);
446                 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
447                 val |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
448                 ulpi_write(phy, val, ULPI_FUNC_CTRL);
449         }
450 
451         if (motg->phy_number)
452                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
453 
454         return 0;
455 }
456 
457 #define PHY_SUSPEND_TIMEOUT_USEC        (500 * 1000)
458 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
459 
460 #ifdef CONFIG_PM
461 
462 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
463 {
464         int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
465         int min_vol;
466         int ret;
467 
468         if (high)
469                 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
470         else
471                 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
472 
473         ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
474         if (ret) {
475                 pr_err("Cannot set vddcx voltage\n");
476                 return ret;
477         }
478 
479         pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
480 
481         return ret;
482 }
483 
484 static int msm_otg_suspend(struct msm_otg *motg)
485 {
486         struct usb_phy *phy = &motg->phy;
487         struct usb_bus *bus = phy->otg->host;
488         struct msm_otg_platform_data *pdata = motg->pdata;
489         void __iomem *addr;
490         int cnt = 0;
491 
492         if (atomic_read(&motg->in_lpm))
493                 return 0;
494 
495         disable_irq(motg->irq);
496         /*
497          * Chipidea 45-nm PHY suspend sequence:
498          *
499          * Interrupt Latch Register auto-clear feature is not present
500          * in all PHY versions. Latch register is clear on read type.
501          * Clear latch register to avoid spurious wakeup from
502          * low power mode (LPM).
503          *
504          * PHY comparators are disabled when PHY enters into low power
505          * mode (LPM). Keep PHY comparators ON in LPM only when we expect
506          * VBUS/Id notifications from USB PHY. Otherwise turn off USB
507          * PHY comparators. This save significant amount of power.
508          *
509          * PLL is not turned off when PHY enters into low power mode (LPM).
510          * Disable PLL for maximum power savings.
511          */
512 
513         if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
514                 ulpi_read(phy, 0x14);
515                 if (pdata->otg_control == OTG_PHY_CONTROL)
516                         ulpi_write(phy, 0x01, 0x30);
517                 ulpi_write(phy, 0x08, 0x09);
518         }
519 
520         /*
521          * PHY may take some time or even fail to enter into low power
522          * mode (LPM). Hence poll for 500 msec and reset the PHY and link
523          * in failure case.
524          */
525         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
526         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
527                 if (readl(USB_PORTSC) & PORTSC_PHCD)
528                         break;
529                 udelay(1);
530                 cnt++;
531         }
532 
533         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
534                 dev_err(phy->dev, "Unable to suspend PHY\n");
535                 msm_otg_reset(phy);
536                 enable_irq(motg->irq);
537                 return -ETIMEDOUT;
538         }
539 
540         /*
541          * PHY has capability to generate interrupt asynchronously in low
542          * power mode (LPM). This interrupt is level triggered. So USB IRQ
543          * line must be disabled till async interrupt enable bit is cleared
544          * in USBCMD register. Assert STP (ULPI interface STOP signal) to
545          * block data communication from PHY.
546          */
547         writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
548 
549         addr = USB_PHY_CTRL;
550         if (motg->phy_number)
551                 addr = USB_PHY_CTRL2;
552 
553         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
554                         motg->pdata->otg_control == OTG_PMIC_CONTROL)
555                 writel(readl(addr) | PHY_RETEN, addr);
556 
557         clk_disable_unprepare(motg->pclk);
558         clk_disable_unprepare(motg->clk);
559         if (!IS_ERR(motg->core_clk))
560                 clk_disable_unprepare(motg->core_clk);
561 
562         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
563                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
564                 msm_hsusb_ldo_set_mode(motg, 0);
565                 msm_hsusb_config_vddcx(motg, 0);
566         }
567 
568         if (device_may_wakeup(phy->dev))
569                 enable_irq_wake(motg->irq);
570         if (bus)
571                 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
572 
573         atomic_set(&motg->in_lpm, 1);
574         enable_irq(motg->irq);
575 
576         dev_info(phy->dev, "USB in low power mode\n");
577 
578         return 0;
579 }
580 
581 static int msm_otg_resume(struct msm_otg *motg)
582 {
583         struct usb_phy *phy = &motg->phy;
584         struct usb_bus *bus = phy->otg->host;
585         void __iomem *addr;
586         int cnt = 0;
587         unsigned temp;
588 
589         if (!atomic_read(&motg->in_lpm))
590                 return 0;
591 
592         clk_prepare_enable(motg->pclk);
593         clk_prepare_enable(motg->clk);
594         if (!IS_ERR(motg->core_clk))
595                 clk_prepare_enable(motg->core_clk);
596 
597         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
598                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
599 
600                 addr = USB_PHY_CTRL;
601                 if (motg->phy_number)
602                         addr = USB_PHY_CTRL2;
603 
604                 msm_hsusb_ldo_set_mode(motg, 1);
605                 msm_hsusb_config_vddcx(motg, 1);
606                 writel(readl(addr) & ~PHY_RETEN, addr);
607         }
608 
609         temp = readl(USB_USBCMD);
610         temp &= ~ASYNC_INTR_CTRL;
611         temp &= ~ULPI_STP_CTRL;
612         writel(temp, USB_USBCMD);
613 
614         /*
615          * PHY comes out of low power mode (LPM) in case of wakeup
616          * from asynchronous interrupt.
617          */
618         if (!(readl(USB_PORTSC) & PORTSC_PHCD))
619                 goto skip_phy_resume;
620 
621         writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
622         while (cnt < PHY_RESUME_TIMEOUT_USEC) {
623                 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
624                         break;
625                 udelay(1);
626                 cnt++;
627         }
628 
629         if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
630                 /*
631                  * This is a fatal error. Reset the link and
632                  * PHY. USB state can not be restored. Re-insertion
633                  * of USB cable is the only way to get USB working.
634                  */
635                 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
636                 msm_otg_reset(phy);
637         }
638 
639 skip_phy_resume:
640         if (device_may_wakeup(phy->dev))
641                 disable_irq_wake(motg->irq);
642         if (bus)
643                 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
644 
645         atomic_set(&motg->in_lpm, 0);
646 
647         if (motg->async_int) {
648                 motg->async_int = 0;
649                 pm_runtime_put(phy->dev);
650                 enable_irq(motg->irq);
651         }
652 
653         dev_info(phy->dev, "USB exited from low power mode\n");
654 
655         return 0;
656 }
657 #endif
658 
659 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
660 {
661         if (motg->cur_power == mA)
662                 return;
663 
664         /* TODO: Notify PMIC about available current */
665         dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
666         motg->cur_power = mA;
667 }
668 
669 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
670 {
671         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
672 
673         /*
674          * Gadget driver uses set_power method to notify about the
675          * available current based on suspend/configured states.
676          *
677          * IDEV_CHG can be drawn irrespective of suspend/un-configured
678          * states when CDP/ACA is connected.
679          */
680         if (motg->chg_type == USB_SDP_CHARGER)
681                 msm_otg_notify_charger(motg, mA);
682 
683         return 0;
684 }
685 
686 static void msm_otg_start_host(struct usb_phy *phy, int on)
687 {
688         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
689         struct msm_otg_platform_data *pdata = motg->pdata;
690         struct usb_hcd *hcd;
691 
692         if (!phy->otg->host)
693                 return;
694 
695         hcd = bus_to_hcd(phy->otg->host);
696 
697         if (on) {
698                 dev_dbg(phy->dev, "host on\n");
699 
700                 if (pdata->vbus_power)
701                         pdata->vbus_power(1);
702                 /*
703                  * Some boards have a switch cotrolled by gpio
704                  * to enable/disable internal HUB. Enable internal
705                  * HUB before kicking the host.
706                  */
707                 if (pdata->setup_gpio)
708                         pdata->setup_gpio(OTG_STATE_A_HOST);
709 #ifdef CONFIG_USB
710                 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
711                 device_wakeup_enable(hcd->self.controller);
712 #endif
713         } else {
714                 dev_dbg(phy->dev, "host off\n");
715 
716 #ifdef CONFIG_USB
717                 usb_remove_hcd(hcd);
718 #endif
719                 if (pdata->setup_gpio)
720                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
721                 if (pdata->vbus_power)
722                         pdata->vbus_power(0);
723         }
724 }
725 
726 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
727 {
728         struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
729         struct usb_hcd *hcd;
730 
731         /*
732          * Fail host registration if this board can support
733          * only peripheral configuration.
734          */
735         if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
736                 dev_info(otg->usb_phy->dev, "Host mode is not supported\n");
737                 return -ENODEV;
738         }
739 
740         if (!host) {
741                 if (otg->state == OTG_STATE_A_HOST) {
742                         pm_runtime_get_sync(otg->usb_phy->dev);
743                         msm_otg_start_host(otg->usb_phy, 0);
744                         otg->host = NULL;
745                         otg->state = OTG_STATE_UNDEFINED;
746                         schedule_work(&motg->sm_work);
747                 } else {
748                         otg->host = NULL;
749                 }
750 
751                 return 0;
752         }
753 
754         hcd = bus_to_hcd(host);
755         hcd->power_budget = motg->pdata->power_budget;
756 
757         otg->host = host;
758         dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n");
759 
760         pm_runtime_get_sync(otg->usb_phy->dev);
761         schedule_work(&motg->sm_work);
762 
763         return 0;
764 }
765 
766 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
767 {
768         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
769         struct msm_otg_platform_data *pdata = motg->pdata;
770 
771         if (!phy->otg->gadget)
772                 return;
773 
774         if (on) {
775                 dev_dbg(phy->dev, "gadget on\n");
776                 /*
777                  * Some boards have a switch cotrolled by gpio
778                  * to enable/disable internal HUB. Disable internal
779                  * HUB before kicking the gadget.
780                  */
781                 if (pdata->setup_gpio)
782                         pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
783                 usb_gadget_vbus_connect(phy->otg->gadget);
784         } else {
785                 dev_dbg(phy->dev, "gadget off\n");
786                 usb_gadget_vbus_disconnect(phy->otg->gadget);
787                 if (pdata->setup_gpio)
788                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
789         }
790 
791 }
792 
793 static int msm_otg_set_peripheral(struct usb_otg *otg,
794                                         struct usb_gadget *gadget)
795 {
796         struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
797 
798         /*
799          * Fail peripheral registration if this board can support
800          * only host configuration.
801          */
802         if (motg->pdata->mode == USB_DR_MODE_HOST) {
803                 dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n");
804                 return -ENODEV;
805         }
806 
807         if (!gadget) {
808                 if (otg->state == OTG_STATE_B_PERIPHERAL) {
809                         pm_runtime_get_sync(otg->usb_phy->dev);
810                         msm_otg_start_peripheral(otg->usb_phy, 0);
811                         otg->gadget = NULL;
812                         otg->state = OTG_STATE_UNDEFINED;
813                         schedule_work(&motg->sm_work);
814                 } else {
815                         otg->gadget = NULL;
816                 }
817 
818                 return 0;
819         }
820         otg->gadget = gadget;
821         dev_dbg(otg->usb_phy->dev,
822                 "peripheral driver registered w/ tranceiver\n");
823 
824         pm_runtime_get_sync(otg->usb_phy->dev);
825         schedule_work(&motg->sm_work);
826 
827         return 0;
828 }
829 
830 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
831 {
832         struct usb_phy *phy = &motg->phy;
833         u32 chg_det;
834         bool ret = false;
835 
836         switch (motg->pdata->phy_type) {
837         case CI_45NM_INTEGRATED_PHY:
838                 chg_det = ulpi_read(phy, 0x34);
839                 ret = chg_det & (1 << 4);
840                 break;
841         case SNPS_28NM_INTEGRATED_PHY:
842                 chg_det = ulpi_read(phy, 0x87);
843                 ret = chg_det & 1;
844                 break;
845         default:
846                 break;
847         }
848         return ret;
849 }
850 
851 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
852 {
853         struct usb_phy *phy = &motg->phy;
854         u32 chg_det;
855 
856         switch (motg->pdata->phy_type) {
857         case CI_45NM_INTEGRATED_PHY:
858                 chg_det = ulpi_read(phy, 0x34);
859                 /* Turn off charger block */
860                 chg_det |= ~(1 << 1);
861                 ulpi_write(phy, chg_det, 0x34);
862                 udelay(20);
863                 /* control chg block via ULPI */
864                 chg_det &= ~(1 << 3);
865                 ulpi_write(phy, chg_det, 0x34);
866                 /* put it in host mode for enabling D- source */
867                 chg_det &= ~(1 << 2);
868                 ulpi_write(phy, chg_det, 0x34);
869                 /* Turn on chg detect block */
870                 chg_det &= ~(1 << 1);
871                 ulpi_write(phy, chg_det, 0x34);
872                 udelay(20);
873                 /* enable chg detection */
874                 chg_det &= ~(1 << 0);
875                 ulpi_write(phy, chg_det, 0x34);
876                 break;
877         case SNPS_28NM_INTEGRATED_PHY:
878                 /*
879                  * Configure DM as current source, DP as current sink
880                  * and enable battery charging comparators.
881                  */
882                 ulpi_write(phy, 0x8, 0x85);
883                 ulpi_write(phy, 0x2, 0x85);
884                 ulpi_write(phy, 0x1, 0x85);
885                 break;
886         default:
887                 break;
888         }
889 }
890 
891 static bool msm_chg_check_primary_det(struct msm_otg *motg)
892 {
893         struct usb_phy *phy = &motg->phy;
894         u32 chg_det;
895         bool ret = false;
896 
897         switch (motg->pdata->phy_type) {
898         case CI_45NM_INTEGRATED_PHY:
899                 chg_det = ulpi_read(phy, 0x34);
900                 ret = chg_det & (1 << 4);
901                 break;
902         case SNPS_28NM_INTEGRATED_PHY:
903                 chg_det = ulpi_read(phy, 0x87);
904                 ret = chg_det & 1;
905                 break;
906         default:
907                 break;
908         }
909         return ret;
910 }
911 
912 static void msm_chg_enable_primary_det(struct msm_otg *motg)
913 {
914         struct usb_phy *phy = &motg->phy;
915         u32 chg_det;
916 
917         switch (motg->pdata->phy_type) {
918         case CI_45NM_INTEGRATED_PHY:
919                 chg_det = ulpi_read(phy, 0x34);
920                 /* enable chg detection */
921                 chg_det &= ~(1 << 0);
922                 ulpi_write(phy, chg_det, 0x34);
923                 break;
924         case SNPS_28NM_INTEGRATED_PHY:
925                 /*
926                  * Configure DP as current source, DM as current sink
927                  * and enable battery charging comparators.
928                  */
929                 ulpi_write(phy, 0x2, 0x85);
930                 ulpi_write(phy, 0x1, 0x85);
931                 break;
932         default:
933                 break;
934         }
935 }
936 
937 static bool msm_chg_check_dcd(struct msm_otg *motg)
938 {
939         struct usb_phy *phy = &motg->phy;
940         u32 line_state;
941         bool ret = false;
942 
943         switch (motg->pdata->phy_type) {
944         case CI_45NM_INTEGRATED_PHY:
945                 line_state = ulpi_read(phy, 0x15);
946                 ret = !(line_state & 1);
947                 break;
948         case SNPS_28NM_INTEGRATED_PHY:
949                 line_state = ulpi_read(phy, 0x87);
950                 ret = line_state & 2;
951                 break;
952         default:
953                 break;
954         }
955         return ret;
956 }
957 
958 static void msm_chg_disable_dcd(struct msm_otg *motg)
959 {
960         struct usb_phy *phy = &motg->phy;
961         u32 chg_det;
962 
963         switch (motg->pdata->phy_type) {
964         case CI_45NM_INTEGRATED_PHY:
965                 chg_det = ulpi_read(phy, 0x34);
966                 chg_det &= ~(1 << 5);
967                 ulpi_write(phy, chg_det, 0x34);
968                 break;
969         case SNPS_28NM_INTEGRATED_PHY:
970                 ulpi_write(phy, 0x10, 0x86);
971                 break;
972         default:
973                 break;
974         }
975 }
976 
977 static void msm_chg_enable_dcd(struct msm_otg *motg)
978 {
979         struct usb_phy *phy = &motg->phy;
980         u32 chg_det;
981 
982         switch (motg->pdata->phy_type) {
983         case CI_45NM_INTEGRATED_PHY:
984                 chg_det = ulpi_read(phy, 0x34);
985                 /* Turn on D+ current source */
986                 chg_det |= (1 << 5);
987                 ulpi_write(phy, chg_det, 0x34);
988                 break;
989         case SNPS_28NM_INTEGRATED_PHY:
990                 /* Data contact detection enable */
991                 ulpi_write(phy, 0x10, 0x85);
992                 break;
993         default:
994                 break;
995         }
996 }
997 
998 static void msm_chg_block_on(struct msm_otg *motg)
999 {
1000         struct usb_phy *phy = &motg->phy;
1001         u32 func_ctrl, chg_det;
1002 
1003         /* put the controller in non-driving mode */
1004         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1005         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1006         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
1007         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1008 
1009         switch (motg->pdata->phy_type) {
1010         case CI_45NM_INTEGRATED_PHY:
1011                 chg_det = ulpi_read(phy, 0x34);
1012                 /* control chg block via ULPI */
1013                 chg_det &= ~(1 << 3);
1014                 ulpi_write(phy, chg_det, 0x34);
1015                 /* Turn on chg detect block */
1016                 chg_det &= ~(1 << 1);
1017                 ulpi_write(phy, chg_det, 0x34);
1018                 udelay(20);
1019                 break;
1020         case SNPS_28NM_INTEGRATED_PHY:
1021                 /* Clear charger detecting control bits */
1022                 ulpi_write(phy, 0x3F, 0x86);
1023                 /* Clear alt interrupt latch and enable bits */
1024                 ulpi_write(phy, 0x1F, 0x92);
1025                 ulpi_write(phy, 0x1F, 0x95);
1026                 udelay(100);
1027                 break;
1028         default:
1029                 break;
1030         }
1031 }
1032 
1033 static void msm_chg_block_off(struct msm_otg *motg)
1034 {
1035         struct usb_phy *phy = &motg->phy;
1036         u32 func_ctrl, chg_det;
1037 
1038         switch (motg->pdata->phy_type) {
1039         case CI_45NM_INTEGRATED_PHY:
1040                 chg_det = ulpi_read(phy, 0x34);
1041                 /* Turn off charger block */
1042                 chg_det |= ~(1 << 1);
1043                 ulpi_write(phy, chg_det, 0x34);
1044                 break;
1045         case SNPS_28NM_INTEGRATED_PHY:
1046                 /* Clear charger detecting control bits */
1047                 ulpi_write(phy, 0x3F, 0x86);
1048                 /* Clear alt interrupt latch and enable bits */
1049                 ulpi_write(phy, 0x1F, 0x92);
1050                 ulpi_write(phy, 0x1F, 0x95);
1051                 break;
1052         default:
1053                 break;
1054         }
1055 
1056         /* put the controller in normal mode */
1057         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1058         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1059         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1060         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1061 }
1062 
1063 #define MSM_CHG_DCD_POLL_TIME           (100 * HZ/1000) /* 100 msec */
1064 #define MSM_CHG_DCD_MAX_RETRIES         6 /* Tdcd_tmout = 6 * 100 msec */
1065 #define MSM_CHG_PRIMARY_DET_TIME        (40 * HZ/1000) /* TVDPSRC_ON */
1066 #define MSM_CHG_SECONDARY_DET_TIME      (40 * HZ/1000) /* TVDMSRC_ON */
1067 static void msm_chg_detect_work(struct work_struct *w)
1068 {
1069         struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1070         struct usb_phy *phy = &motg->phy;
1071         bool is_dcd, tmout, vout;
1072         unsigned long delay;
1073 
1074         dev_dbg(phy->dev, "chg detection work\n");
1075         switch (motg->chg_state) {
1076         case USB_CHG_STATE_UNDEFINED:
1077                 pm_runtime_get_sync(phy->dev);
1078                 msm_chg_block_on(motg);
1079                 msm_chg_enable_dcd(motg);
1080                 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1081                 motg->dcd_retries = 0;
1082                 delay = MSM_CHG_DCD_POLL_TIME;
1083                 break;
1084         case USB_CHG_STATE_WAIT_FOR_DCD:
1085                 is_dcd = msm_chg_check_dcd(motg);
1086                 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1087                 if (is_dcd || tmout) {
1088                         msm_chg_disable_dcd(motg);
1089                         msm_chg_enable_primary_det(motg);
1090                         delay = MSM_CHG_PRIMARY_DET_TIME;
1091                         motg->chg_state = USB_CHG_STATE_DCD_DONE;
1092                 } else {
1093                         delay = MSM_CHG_DCD_POLL_TIME;
1094                 }
1095                 break;
1096         case USB_CHG_STATE_DCD_DONE:
1097                 vout = msm_chg_check_primary_det(motg);
1098                 if (vout) {
1099                         msm_chg_enable_secondary_det(motg);
1100                         delay = MSM_CHG_SECONDARY_DET_TIME;
1101                         motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1102                 } else {
1103                         motg->chg_type = USB_SDP_CHARGER;
1104                         motg->chg_state = USB_CHG_STATE_DETECTED;
1105                         delay = 0;
1106                 }
1107                 break;
1108         case USB_CHG_STATE_PRIMARY_DONE:
1109                 vout = msm_chg_check_secondary_det(motg);
1110                 if (vout)
1111                         motg->chg_type = USB_DCP_CHARGER;
1112                 else
1113                         motg->chg_type = USB_CDP_CHARGER;
1114                 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1115                 /* fall through */
1116         case USB_CHG_STATE_SECONDARY_DONE:
1117                 motg->chg_state = USB_CHG_STATE_DETECTED;
1118         case USB_CHG_STATE_DETECTED:
1119                 msm_chg_block_off(motg);
1120                 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1121                 schedule_work(&motg->sm_work);
1122                 return;
1123         default:
1124                 return;
1125         }
1126 
1127         schedule_delayed_work(&motg->chg_work, delay);
1128 }
1129 
1130 /*
1131  * We support OTG, Peripheral only and Host only configurations. In case
1132  * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1133  * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1134  * enabled when switch is controlled by user and default mode is supplied
1135  * by board file, which can be changed by userspace later.
1136  */
1137 static void msm_otg_init_sm(struct msm_otg *motg)
1138 {
1139         struct msm_otg_platform_data *pdata = motg->pdata;
1140         u32 otgsc = readl(USB_OTGSC);
1141 
1142         switch (pdata->mode) {
1143         case USB_DR_MODE_OTG:
1144                 if (pdata->otg_control == OTG_PHY_CONTROL) {
1145                         if (otgsc & OTGSC_ID)
1146                                 set_bit(ID, &motg->inputs);
1147                         else
1148                                 clear_bit(ID, &motg->inputs);
1149 
1150                         if (otgsc & OTGSC_BSV)
1151                                 set_bit(B_SESS_VLD, &motg->inputs);
1152                         else
1153                                 clear_bit(B_SESS_VLD, &motg->inputs);
1154                 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1155                                 set_bit(ID, &motg->inputs);
1156                                 clear_bit(B_SESS_VLD, &motg->inputs);
1157                 }
1158                 break;
1159         case USB_DR_MODE_HOST:
1160                 clear_bit(ID, &motg->inputs);
1161                 break;
1162         case USB_DR_MODE_PERIPHERAL:
1163                 set_bit(ID, &motg->inputs);
1164                 if (otgsc & OTGSC_BSV)
1165                         set_bit(B_SESS_VLD, &motg->inputs);
1166                 else
1167                         clear_bit(B_SESS_VLD, &motg->inputs);
1168                 break;
1169         default:
1170                 break;
1171         }
1172 }
1173 
1174 static void msm_otg_sm_work(struct work_struct *w)
1175 {
1176         struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1177         struct usb_otg *otg = motg->phy.otg;
1178 
1179         switch (otg->state) {
1180         case OTG_STATE_UNDEFINED:
1181                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n");
1182                 msm_otg_reset(otg->usb_phy);
1183                 msm_otg_init_sm(motg);
1184                 otg->state = OTG_STATE_B_IDLE;
1185                 /* FALL THROUGH */
1186         case OTG_STATE_B_IDLE:
1187                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n");
1188                 if (!test_bit(ID, &motg->inputs) && otg->host) {
1189                         /* disable BSV bit */
1190                         writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1191                         msm_otg_start_host(otg->usb_phy, 1);
1192                         otg->state = OTG_STATE_A_HOST;
1193                 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1194                         switch (motg->chg_state) {
1195                         case USB_CHG_STATE_UNDEFINED:
1196                                 msm_chg_detect_work(&motg->chg_work.work);
1197                                 break;
1198                         case USB_CHG_STATE_DETECTED:
1199                                 switch (motg->chg_type) {
1200                                 case USB_DCP_CHARGER:
1201                                         msm_otg_notify_charger(motg,
1202                                                         IDEV_CHG_MAX);
1203                                         break;
1204                                 case USB_CDP_CHARGER:
1205                                         msm_otg_notify_charger(motg,
1206                                                         IDEV_CHG_MAX);
1207                                         msm_otg_start_peripheral(otg->usb_phy,
1208                                                                  1);
1209                                         otg->state
1210                                                 = OTG_STATE_B_PERIPHERAL;
1211                                         break;
1212                                 case USB_SDP_CHARGER:
1213                                         msm_otg_notify_charger(motg, IUNIT);
1214                                         msm_otg_start_peripheral(otg->usb_phy,
1215                                                                  1);
1216                                         otg->state
1217                                                 = OTG_STATE_B_PERIPHERAL;
1218                                         break;
1219                                 default:
1220                                         break;
1221                                 }
1222                                 break;
1223                         default:
1224                                 break;
1225                         }
1226                 } else {
1227                         /*
1228                          * If charger detection work is pending, decrement
1229                          * the pm usage counter to balance with the one that
1230                          * is incremented in charger detection work.
1231                          */
1232                         if (cancel_delayed_work_sync(&motg->chg_work)) {
1233                                 pm_runtime_put_sync(otg->usb_phy->dev);
1234                                 msm_otg_reset(otg->usb_phy);
1235                         }
1236                         msm_otg_notify_charger(motg, 0);
1237                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1238                         motg->chg_type = USB_INVALID_CHARGER;
1239                 }
1240 
1241                 if (otg->state == OTG_STATE_B_IDLE)
1242                         pm_runtime_put_sync(otg->usb_phy->dev);
1243                 break;
1244         case OTG_STATE_B_PERIPHERAL:
1245                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1246                 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1247                                 !test_bit(ID, &motg->inputs)) {
1248                         msm_otg_notify_charger(motg, 0);
1249                         msm_otg_start_peripheral(otg->usb_phy, 0);
1250                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1251                         motg->chg_type = USB_INVALID_CHARGER;
1252                         otg->state = OTG_STATE_B_IDLE;
1253                         msm_otg_reset(otg->usb_phy);
1254                         schedule_work(w);
1255                 }
1256                 break;
1257         case OTG_STATE_A_HOST:
1258                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n");
1259                 if (test_bit(ID, &motg->inputs)) {
1260                         msm_otg_start_host(otg->usb_phy, 0);
1261                         otg->state = OTG_STATE_B_IDLE;
1262                         msm_otg_reset(otg->usb_phy);
1263                         schedule_work(w);
1264                 }
1265                 break;
1266         default:
1267                 break;
1268         }
1269 }
1270 
1271 static irqreturn_t msm_otg_irq(int irq, void *data)
1272 {
1273         struct msm_otg *motg = data;
1274         struct usb_phy *phy = &motg->phy;
1275         u32 otgsc = 0;
1276 
1277         if (atomic_read(&motg->in_lpm)) {
1278                 disable_irq_nosync(irq);
1279                 motg->async_int = 1;
1280                 pm_runtime_get(phy->dev);
1281                 return IRQ_HANDLED;
1282         }
1283 
1284         otgsc = readl(USB_OTGSC);
1285         if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1286                 return IRQ_NONE;
1287 
1288         if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1289                 if (otgsc & OTGSC_ID)
1290                         set_bit(ID, &motg->inputs);
1291                 else
1292                         clear_bit(ID, &motg->inputs);
1293                 dev_dbg(phy->dev, "ID set/clear\n");
1294                 pm_runtime_get_noresume(phy->dev);
1295         } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1296                 if (otgsc & OTGSC_BSV)
1297                         set_bit(B_SESS_VLD, &motg->inputs);
1298                 else
1299                         clear_bit(B_SESS_VLD, &motg->inputs);
1300                 dev_dbg(phy->dev, "BSV set/clear\n");
1301                 pm_runtime_get_noresume(phy->dev);
1302         }
1303 
1304         writel(otgsc, USB_OTGSC);
1305         schedule_work(&motg->sm_work);
1306         return IRQ_HANDLED;
1307 }
1308 
1309 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1310 {
1311         struct msm_otg *motg = s->private;
1312         struct usb_otg *otg = motg->phy.otg;
1313 
1314         switch (otg->state) {
1315         case OTG_STATE_A_HOST:
1316                 seq_puts(s, "host\n");
1317                 break;
1318         case OTG_STATE_B_PERIPHERAL:
1319                 seq_puts(s, "peripheral\n");
1320                 break;
1321         default:
1322                 seq_puts(s, "none\n");
1323                 break;
1324         }
1325 
1326         return 0;
1327 }
1328 
1329 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1330 {
1331         return single_open(file, msm_otg_mode_show, inode->i_private);
1332 }
1333 
1334 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1335                                 size_t count, loff_t *ppos)
1336 {
1337         struct seq_file *s = file->private_data;
1338         struct msm_otg *motg = s->private;
1339         char buf[16];
1340         struct usb_otg *otg = motg->phy.otg;
1341         int status = count;
1342         enum usb_dr_mode req_mode;
1343 
1344         memset(buf, 0x00, sizeof(buf));
1345 
1346         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1347                 status = -EFAULT;
1348                 goto out;
1349         }
1350 
1351         if (!strncmp(buf, "host", 4)) {
1352                 req_mode = USB_DR_MODE_HOST;
1353         } else if (!strncmp(buf, "peripheral", 10)) {
1354                 req_mode = USB_DR_MODE_PERIPHERAL;
1355         } else if (!strncmp(buf, "none", 4)) {
1356                 req_mode = USB_DR_MODE_UNKNOWN;
1357         } else {
1358                 status = -EINVAL;
1359                 goto out;
1360         }
1361 
1362         switch (req_mode) {
1363         case USB_DR_MODE_UNKNOWN:
1364                 switch (otg->state) {
1365                 case OTG_STATE_A_HOST:
1366                 case OTG_STATE_B_PERIPHERAL:
1367                         set_bit(ID, &motg->inputs);
1368                         clear_bit(B_SESS_VLD, &motg->inputs);
1369                         break;
1370                 default:
1371                         goto out;
1372                 }
1373                 break;
1374         case USB_DR_MODE_PERIPHERAL:
1375                 switch (otg->state) {
1376                 case OTG_STATE_B_IDLE:
1377                 case OTG_STATE_A_HOST:
1378                         set_bit(ID, &motg->inputs);
1379                         set_bit(B_SESS_VLD, &motg->inputs);
1380                         break;
1381                 default:
1382                         goto out;
1383                 }
1384                 break;
1385         case USB_DR_MODE_HOST:
1386                 switch (otg->state) {
1387                 case OTG_STATE_B_IDLE:
1388                 case OTG_STATE_B_PERIPHERAL:
1389                         clear_bit(ID, &motg->inputs);
1390                         break;
1391                 default:
1392                         goto out;
1393                 }
1394                 break;
1395         default:
1396                 goto out;
1397         }
1398 
1399         pm_runtime_get_sync(otg->usb_phy->dev);
1400         schedule_work(&motg->sm_work);
1401 out:
1402         return status;
1403 }
1404 
1405 static const struct file_operations msm_otg_mode_fops = {
1406         .open = msm_otg_mode_open,
1407         .read = seq_read,
1408         .write = msm_otg_mode_write,
1409         .llseek = seq_lseek,
1410         .release = single_release,
1411 };
1412 
1413 static struct dentry *msm_otg_dbg_root;
1414 static struct dentry *msm_otg_dbg_mode;
1415 
1416 static int msm_otg_debugfs_init(struct msm_otg *motg)
1417 {
1418         msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1419 
1420         if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1421                 return -ENODEV;
1422 
1423         msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1424                                 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1425         if (!msm_otg_dbg_mode) {
1426                 debugfs_remove(msm_otg_dbg_root);
1427                 msm_otg_dbg_root = NULL;
1428                 return -ENODEV;
1429         }
1430 
1431         return 0;
1432 }
1433 
1434 static void msm_otg_debugfs_cleanup(void)
1435 {
1436         debugfs_remove(msm_otg_dbg_mode);
1437         debugfs_remove(msm_otg_dbg_root);
1438 }
1439 
1440 static const struct of_device_id msm_otg_dt_match[] = {
1441         {
1442                 .compatible = "qcom,usb-otg-ci",
1443                 .data = (void *) CI_45NM_INTEGRATED_PHY
1444         },
1445         {
1446                 .compatible = "qcom,usb-otg-snps",
1447                 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1448         },
1449         { }
1450 };
1451 MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1452 
1453 static int msm_otg_vbus_notifier(struct notifier_block *nb, unsigned long event,
1454                                 void *ptr)
1455 {
1456         struct msm_usb_cable *vbus = container_of(nb, struct msm_usb_cable, nb);
1457         struct msm_otg *motg = container_of(vbus, struct msm_otg, vbus);
1458 
1459         if (event)
1460                 set_bit(B_SESS_VLD, &motg->inputs);
1461         else
1462                 clear_bit(B_SESS_VLD, &motg->inputs);
1463 
1464         if (test_bit(B_SESS_VLD, &motg->inputs)) {
1465                 /* Switch D+/D- lines to Device connector */
1466                 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1467         } else {
1468                 /* Switch D+/D- lines to Hub */
1469                 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1470         }
1471 
1472         schedule_work(&motg->sm_work);
1473 
1474         return NOTIFY_DONE;
1475 }
1476 
1477 static int msm_otg_id_notifier(struct notifier_block *nb, unsigned long event,
1478                                 void *ptr)
1479 {
1480         struct msm_usb_cable *id = container_of(nb, struct msm_usb_cable, nb);
1481         struct msm_otg *motg = container_of(id, struct msm_otg, id);
1482 
1483         if (event)
1484                 clear_bit(ID, &motg->inputs);
1485         else
1486                 set_bit(ID, &motg->inputs);
1487 
1488         schedule_work(&motg->sm_work);
1489 
1490         return NOTIFY_DONE;
1491 }
1492 
1493 static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1494 {
1495         struct msm_otg_platform_data *pdata;
1496         struct extcon_dev *ext_id, *ext_vbus;
1497         struct device_node *node = pdev->dev.of_node;
1498         struct property *prop;
1499         int len, ret, words;
1500         u32 val, tmp[3];
1501 
1502         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1503         if (!pdata)
1504                 return -ENOMEM;
1505 
1506         motg->pdata = pdata;
1507 
1508         pdata->phy_type = (enum msm_usb_phy_type)of_device_get_match_data(&pdev->dev);
1509         if (!pdata->phy_type)
1510                 return 1;
1511 
1512         motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1513         if (IS_ERR(motg->link_rst))
1514                 return PTR_ERR(motg->link_rst);
1515 
1516         motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1517         if (IS_ERR(motg->phy_rst))
1518                 motg->phy_rst = NULL;
1519 
1520         pdata->mode = usb_get_dr_mode(&pdev->dev);
1521         if (pdata->mode == USB_DR_MODE_UNKNOWN)
1522                 pdata->mode = USB_DR_MODE_OTG;
1523 
1524         pdata->otg_control = OTG_PHY_CONTROL;
1525         if (!of_property_read_u32(node, "qcom,otg-control", &val))
1526                 if (val == OTG_PMIC_CONTROL)
1527                         pdata->otg_control = val;
1528 
1529         if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1530                 motg->phy_number = val;
1531 
1532         motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1533         motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1534         motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1535 
1536         if (of_get_property(node, "qcom,vdd-levels", &len) &&
1537             len == sizeof(tmp)) {
1538                 of_property_read_u32_array(node, "qcom,vdd-levels",
1539                                            tmp, len / sizeof(*tmp));
1540                 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1541                 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1542                 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1543         }
1544 
1545         motg->manual_pullup = of_property_read_bool(node, "qcom,manual-pullup");
1546 
1547         motg->switch_gpio = devm_gpiod_get_optional(&pdev->dev, "switch",
1548                                                     GPIOD_OUT_LOW);
1549         if (IS_ERR(motg->switch_gpio))
1550                 return PTR_ERR(motg->switch_gpio);
1551 
1552         ext_id = ERR_PTR(-ENODEV);
1553         ext_vbus = ERR_PTR(-ENODEV);
1554         if (of_property_read_bool(node, "extcon")) {
1555 
1556                 /* Each one of them is not mandatory */
1557                 ext_vbus = extcon_get_edev_by_phandle(&pdev->dev, 0);
1558                 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
1559                         return PTR_ERR(ext_vbus);
1560 
1561                 ext_id = extcon_get_edev_by_phandle(&pdev->dev, 1);
1562                 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
1563                         return PTR_ERR(ext_id);
1564         }
1565 
1566         if (!IS_ERR(ext_vbus)) {
1567                 motg->vbus.extcon = ext_vbus;
1568                 motg->vbus.nb.notifier_call = msm_otg_vbus_notifier;
1569                 ret = extcon_register_notifier(ext_vbus, EXTCON_USB,
1570                                                 &motg->vbus.nb);
1571                 if (ret < 0) {
1572                         dev_err(&pdev->dev, "register VBUS notifier failed\n");
1573                         return ret;
1574                 }
1575 
1576                 ret = extcon_get_cable_state_(ext_vbus, EXTCON_USB);
1577                 if (ret)
1578                         set_bit(B_SESS_VLD, &motg->inputs);
1579                 else
1580                         clear_bit(B_SESS_VLD, &motg->inputs);
1581         }
1582 
1583         if (!IS_ERR(ext_id)) {
1584                 motg->id.extcon = ext_id;
1585                 motg->id.nb.notifier_call = msm_otg_id_notifier;
1586                 ret = extcon_register_notifier(ext_id, EXTCON_USB_HOST,
1587                                                 &motg->id.nb);
1588                 if (ret < 0) {
1589                         dev_err(&pdev->dev, "register ID notifier failed\n");
1590                         extcon_unregister_notifier(motg->vbus.extcon,
1591                                                    EXTCON_USB, &motg->vbus.nb);
1592                         return ret;
1593                 }
1594 
1595                 ret = extcon_get_cable_state_(ext_id, EXTCON_USB_HOST);
1596                 if (ret)
1597                         clear_bit(ID, &motg->inputs);
1598                 else
1599                         set_bit(ID, &motg->inputs);
1600         }
1601 
1602         prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1603         if (!prop || !len)
1604                 return 0;
1605 
1606         words = len / sizeof(u32);
1607 
1608         if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1609                 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1610                 return 0;
1611         }
1612 
1613         pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1614         if (!pdata->phy_init_seq)
1615                 return 0;
1616 
1617         ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1618                                          pdata->phy_init_seq, words);
1619         if (!ret)
1620                 pdata->phy_init_sz = words;
1621 
1622         return 0;
1623 }
1624 
1625 static int msm_otg_reboot_notify(struct notifier_block *this,
1626                                  unsigned long code, void *unused)
1627 {
1628         struct msm_otg *motg = container_of(this, struct msm_otg, reboot);
1629 
1630         /*
1631          * Ensure that D+/D- lines are routed to uB connector, so
1632          * we could load bootloader/kernel at next reboot
1633          */
1634         gpiod_set_value_cansleep(motg->switch_gpio, 0);
1635         return NOTIFY_DONE;
1636 }
1637 
1638 static int msm_otg_probe(struct platform_device *pdev)
1639 {
1640         struct regulator_bulk_data regs[3];
1641         int ret = 0;
1642         struct device_node *np = pdev->dev.of_node;
1643         struct msm_otg_platform_data *pdata;
1644         struct resource *res;
1645         struct msm_otg *motg;
1646         struct usb_phy *phy;
1647         void __iomem *phy_select;
1648 
1649         motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1650         if (!motg)
1651                 return -ENOMEM;
1652 
1653         motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1654                                      GFP_KERNEL);
1655         if (!motg->phy.otg)
1656                 return -ENOMEM;
1657 
1658         phy = &motg->phy;
1659         phy->dev = &pdev->dev;
1660 
1661         motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
1662         if (IS_ERR(motg->clk)) {
1663                 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1664                 return PTR_ERR(motg->clk);
1665         }
1666 
1667         /*
1668          * If USB Core is running its protocol engine based on CORE CLK,
1669          * CORE CLK  must be running at >55Mhz for correct HSUSB
1670          * operation and USB core cannot tolerate frequency changes on
1671          * CORE CLK.
1672          */
1673         motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
1674         if (IS_ERR(motg->pclk)) {
1675                 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1676                 return PTR_ERR(motg->pclk);
1677         }
1678 
1679         /*
1680          * USB core clock is not present on all MSM chips. This
1681          * clock is introduced to remove the dependency on AXI
1682          * bus frequency.
1683          */
1684         motg->core_clk = devm_clk_get(&pdev->dev,
1685                                       np ? "alt_core" : "usb_hs_core_clk");
1686 
1687         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1688         if (!res)
1689                 return -EINVAL;
1690         motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1691         if (!motg->regs)
1692                 return -ENOMEM;
1693 
1694         pdata = dev_get_platdata(&pdev->dev);
1695         if (!pdata) {
1696                 if (!np)
1697                         return -ENXIO;
1698                 ret = msm_otg_read_dt(pdev, motg);
1699                 if (ret)
1700                         return ret;
1701         }
1702 
1703         /*
1704          * NOTE: The PHYs can be multiplexed between the chipidea controller
1705          * and the dwc3 controller, using a single bit. It is important that
1706          * the dwc3 driver does not set this bit in an incompatible way.
1707          */
1708         if (motg->phy_number) {
1709                 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1710                 if (!phy_select) {
1711                         ret = -ENOMEM;
1712                         goto unregister_extcon;
1713                 }
1714                 /* Enable second PHY with the OTG port */
1715                 writel(0x1, phy_select);
1716         }
1717 
1718         dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1719 
1720         motg->irq = platform_get_irq(pdev, 0);
1721         if (motg->irq < 0) {
1722                 dev_err(&pdev->dev, "platform_get_irq failed\n");
1723                 ret = motg->irq;
1724                 goto unregister_extcon;
1725         }
1726 
1727         regs[0].supply = "vddcx";
1728         regs[1].supply = "v3p3";
1729         regs[2].supply = "v1p8";
1730 
1731         ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1732         if (ret)
1733                 goto unregister_extcon;
1734 
1735         motg->vddcx = regs[0].consumer;
1736         motg->v3p3  = regs[1].consumer;
1737         motg->v1p8  = regs[2].consumer;
1738 
1739         clk_set_rate(motg->clk, 60000000);
1740 
1741         clk_prepare_enable(motg->clk);
1742         clk_prepare_enable(motg->pclk);
1743 
1744         if (!IS_ERR(motg->core_clk))
1745                 clk_prepare_enable(motg->core_clk);
1746 
1747         ret = msm_hsusb_init_vddcx(motg, 1);
1748         if (ret) {
1749                 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1750                 goto disable_clks;
1751         }
1752 
1753         ret = msm_hsusb_ldo_init(motg, 1);
1754         if (ret) {
1755                 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1756                 goto disable_vddcx;
1757         }
1758         ret = msm_hsusb_ldo_set_mode(motg, 1);
1759         if (ret) {
1760                 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1761                 goto disable_ldo;
1762         }
1763 
1764         writel(0, USB_USBINTR);
1765         writel(0, USB_OTGSC);
1766 
1767         INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1768         INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1769         ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1770                                         "msm_otg", motg);
1771         if (ret) {
1772                 dev_err(&pdev->dev, "request irq failed\n");
1773                 goto disable_ldo;
1774         }
1775 
1776         phy->init = msm_phy_init;
1777         phy->set_power = msm_otg_set_power;
1778         phy->notify_disconnect = msm_phy_notify_disconnect;
1779         phy->type = USB_PHY_TYPE_USB2;
1780 
1781         phy->io_ops = &msm_otg_io_ops;
1782 
1783         phy->otg->usb_phy = &motg->phy;
1784         phy->otg->set_host = msm_otg_set_host;
1785         phy->otg->set_peripheral = msm_otg_set_peripheral;
1786 
1787         msm_usb_reset(phy);
1788 
1789         ret = usb_add_phy_dev(&motg->phy);
1790         if (ret) {
1791                 dev_err(&pdev->dev, "usb_add_phy failed\n");
1792                 goto disable_ldo;
1793         }
1794 
1795         platform_set_drvdata(pdev, motg);
1796         device_init_wakeup(&pdev->dev, 1);
1797 
1798         if (motg->pdata->mode == USB_DR_MODE_OTG &&
1799                 motg->pdata->otg_control == OTG_USER_CONTROL) {
1800                 ret = msm_otg_debugfs_init(motg);
1801                 if (ret)
1802                         dev_dbg(&pdev->dev, "Can not create mode change file\n");
1803         }
1804 
1805         if (test_bit(B_SESS_VLD, &motg->inputs)) {
1806                 /* Switch D+/D- lines to Device connector */
1807                 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1808         } else {
1809                 /* Switch D+/D- lines to Hub */
1810                 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1811         }
1812 
1813         motg->reboot.notifier_call = msm_otg_reboot_notify;
1814         register_reboot_notifier(&motg->reboot);
1815 
1816         pm_runtime_set_active(&pdev->dev);
1817         pm_runtime_enable(&pdev->dev);
1818 
1819         return 0;
1820 
1821 disable_ldo:
1822         msm_hsusb_ldo_init(motg, 0);
1823 disable_vddcx:
1824         msm_hsusb_init_vddcx(motg, 0);
1825 disable_clks:
1826         clk_disable_unprepare(motg->pclk);
1827         clk_disable_unprepare(motg->clk);
1828         if (!IS_ERR(motg->core_clk))
1829                 clk_disable_unprepare(motg->core_clk);
1830 unregister_extcon:
1831         extcon_unregister_notifier(motg->id.extcon,
1832                                    EXTCON_USB_HOST, &motg->id.nb);
1833         extcon_unregister_notifier(motg->vbus.extcon,
1834                                    EXTCON_USB, &motg->vbus.nb);
1835 
1836         return ret;
1837 }
1838 
1839 static int msm_otg_remove(struct platform_device *pdev)
1840 {
1841         struct msm_otg *motg = platform_get_drvdata(pdev);
1842         struct usb_phy *phy = &motg->phy;
1843         int cnt = 0;
1844 
1845         if (phy->otg->host || phy->otg->gadget)
1846                 return -EBUSY;
1847 
1848         unregister_reboot_notifier(&motg->reboot);
1849 
1850         /*
1851          * Ensure that D+/D- lines are routed to uB connector, so
1852          * we could load bootloader/kernel at next reboot
1853          */
1854         gpiod_set_value_cansleep(motg->switch_gpio, 0);
1855 
1856         extcon_unregister_notifier(motg->id.extcon, EXTCON_USB_HOST, &motg->id.nb);
1857         extcon_unregister_notifier(motg->vbus.extcon, EXTCON_USB, &motg->vbus.nb);
1858 
1859         msm_otg_debugfs_cleanup();
1860         cancel_delayed_work_sync(&motg->chg_work);
1861         cancel_work_sync(&motg->sm_work);
1862 
1863         pm_runtime_resume(&pdev->dev);
1864 
1865         device_init_wakeup(&pdev->dev, 0);
1866         pm_runtime_disable(&pdev->dev);
1867 
1868         usb_remove_phy(phy);
1869         disable_irq(motg->irq);
1870 
1871         /*
1872          * Put PHY in low power mode.
1873          */
1874         ulpi_read(phy, 0x14);
1875         ulpi_write(phy, 0x08, 0x09);
1876 
1877         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1878         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1879                 if (readl(USB_PORTSC) & PORTSC_PHCD)
1880                         break;
1881                 udelay(1);
1882                 cnt++;
1883         }
1884         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1885                 dev_err(phy->dev, "Unable to suspend PHY\n");
1886 
1887         clk_disable_unprepare(motg->pclk);
1888         clk_disable_unprepare(motg->clk);
1889         if (!IS_ERR(motg->core_clk))
1890                 clk_disable_unprepare(motg->core_clk);
1891         msm_hsusb_ldo_init(motg, 0);
1892 
1893         pm_runtime_set_suspended(&pdev->dev);
1894 
1895         return 0;
1896 }
1897 
1898 #ifdef CONFIG_PM
1899 static int msm_otg_runtime_idle(struct device *dev)
1900 {
1901         struct msm_otg *motg = dev_get_drvdata(dev);
1902         struct usb_otg *otg = motg->phy.otg;
1903 
1904         dev_dbg(dev, "OTG runtime idle\n");
1905 
1906         /*
1907          * It is observed some times that a spurious interrupt
1908          * comes when PHY is put into LPM immediately after PHY reset.
1909          * This 1 sec delay also prevents entering into LPM immediately
1910          * after asynchronous interrupt.
1911          */
1912         if (otg->state != OTG_STATE_UNDEFINED)
1913                 pm_schedule_suspend(dev, 1000);
1914 
1915         return -EAGAIN;
1916 }
1917 
1918 static int msm_otg_runtime_suspend(struct device *dev)
1919 {
1920         struct msm_otg *motg = dev_get_drvdata(dev);
1921 
1922         dev_dbg(dev, "OTG runtime suspend\n");
1923         return msm_otg_suspend(motg);
1924 }
1925 
1926 static int msm_otg_runtime_resume(struct device *dev)
1927 {
1928         struct msm_otg *motg = dev_get_drvdata(dev);
1929 
1930         dev_dbg(dev, "OTG runtime resume\n");
1931         return msm_otg_resume(motg);
1932 }
1933 #endif
1934 
1935 #ifdef CONFIG_PM_SLEEP
1936 static int msm_otg_pm_suspend(struct device *dev)
1937 {
1938         struct msm_otg *motg = dev_get_drvdata(dev);
1939 
1940         dev_dbg(dev, "OTG PM suspend\n");
1941         return msm_otg_suspend(motg);
1942 }
1943 
1944 static int msm_otg_pm_resume(struct device *dev)
1945 {
1946         struct msm_otg *motg = dev_get_drvdata(dev);
1947         int ret;
1948 
1949         dev_dbg(dev, "OTG PM resume\n");
1950 
1951         ret = msm_otg_resume(motg);
1952         if (ret)
1953                 return ret;
1954 
1955         /*
1956          * Runtime PM Documentation recommends bringing the
1957          * device to full powered state upon resume.
1958          */
1959         pm_runtime_disable(dev);
1960         pm_runtime_set_active(dev);
1961         pm_runtime_enable(dev);
1962 
1963         return 0;
1964 }
1965 #endif
1966 
1967 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1968         SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1969         SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1970                                 msm_otg_runtime_idle)
1971 };
1972 
1973 static struct platform_driver msm_otg_driver = {
1974         .probe = msm_otg_probe,
1975         .remove = msm_otg_remove,
1976         .driver = {
1977                 .name = DRIVER_NAME,
1978                 .pm = &msm_otg_dev_pm_ops,
1979                 .of_match_table = msm_otg_dt_match,
1980         },
1981 };
1982 
1983 module_platform_driver(msm_otg_driver);
1984 
1985 MODULE_LICENSE("GPL v2");
1986 MODULE_DESCRIPTION("MSM USB transceiver driver");
1987 

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