Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/usb/musb/tusb6010.c

  1 /*
  2  * TUSB6010 USB 2.0 OTG Dual Role controller
  3  *
  4  * Copyright (C) 2006 Nokia Corporation
  5  * Tony Lindgren <tony@atomide.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10  *
 11  * Notes:
 12  * - Driver assumes that interface to external host (main CPU) is
 13  *   configured for NOR FLASH interface instead of VLYNQ serial
 14  *   interface.
 15  */
 16 
 17 #include <linux/module.h>
 18 #include <linux/kernel.h>
 19 #include <linux/errno.h>
 20 #include <linux/err.h>
 21 #include <linux/prefetch.h>
 22 #include <linux/usb.h>
 23 #include <linux/irq.h>
 24 #include <linux/io.h>
 25 #include <linux/platform_device.h>
 26 #include <linux/dma-mapping.h>
 27 #include <linux/usb/usb_phy_generic.h>
 28 
 29 #include "musb_core.h"
 30 
 31 struct tusb6010_glue {
 32         struct device           *dev;
 33         struct platform_device  *musb;
 34         struct platform_device  *phy;
 35 };
 36 
 37 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
 38 
 39 #define TUSB_REV_MAJOR(reg_val)         ((reg_val >> 4) & 0xf)
 40 #define TUSB_REV_MINOR(reg_val)         (reg_val & 0xf)
 41 
 42 /*
 43  * Checks the revision. We need to use the DMA register as 3.0 does not
 44  * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
 45  */
 46 static u8 tusb_get_revision(struct musb *musb)
 47 {
 48         void __iomem    *tbase = musb->ctrl_base;
 49         u32             die_id;
 50         u8              rev;
 51 
 52         rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
 53         if (TUSB_REV_MAJOR(rev) == 3) {
 54                 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
 55                                 TUSB_DIDR1_HI));
 56                 if (die_id >= TUSB_DIDR1_HI_REV_31)
 57                         rev |= 1;
 58         }
 59 
 60         return rev;
 61 }
 62 
 63 static void tusb_print_revision(struct musb *musb)
 64 {
 65         void __iomem    *tbase = musb->ctrl_base;
 66         u8              rev;
 67 
 68         rev = musb->tusb_revision;
 69 
 70         pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
 71                 "prcm",
 72                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
 73                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
 74                 "int",
 75                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
 76                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
 77                 "gpio",
 78                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
 79                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
 80                 "dma",
 81                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
 82                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
 83                 "dieid",
 84                 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
 85                 "rev",
 86                 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
 87 }
 88 
 89 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
 90                                 | TUSB_PHY_OTG_CTRL_TESTM0)
 91 
 92 /*
 93  * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
 94  * Disables power detection in PHY for the duration of idle.
 95  */
 96 static void tusb_wbus_quirk(struct musb *musb, int enabled)
 97 {
 98         void __iomem    *tbase = musb->ctrl_base;
 99         static u32      phy_otg_ctrl, phy_otg_ena;
100         u32             tmp;
101 
102         if (enabled) {
103                 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
104                 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
105                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
106                                 | phy_otg_ena | WBUS_QUIRK_MASK;
107                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
108                 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
109                 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
110                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
111                 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
112                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
113                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
114         } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
115                                         & TUSB_PHY_OTG_CTRL_TESTM2) {
116                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
117                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
118                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
119                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
120                 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
121                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
122                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
123                 phy_otg_ctrl = 0;
124                 phy_otg_ena = 0;
125         }
126 }
127 
128 /*
129  * TUSB 6010 may use a parallel bus that doesn't support byte ops;
130  * so both loading and unloading FIFOs need explicit byte counts.
131  */
132 
133 static inline void
134 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
135 {
136         u32             val;
137         int             i;
138 
139         if (len > 4) {
140                 for (i = 0; i < (len >> 2); i++) {
141                         memcpy(&val, buf, 4);
142                         musb_writel(fifo, 0, val);
143                         buf += 4;
144                 }
145                 len %= 4;
146         }
147         if (len > 0) {
148                 /* Write the rest 1 - 3 bytes to FIFO */
149                 memcpy(&val, buf, len);
150                 musb_writel(fifo, 0, val);
151         }
152 }
153 
154 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
155                                                 void *buf, u16 len)
156 {
157         u32             val;
158         int             i;
159 
160         if (len > 4) {
161                 for (i = 0; i < (len >> 2); i++) {
162                         val = musb_readl(fifo, 0);
163                         memcpy(buf, &val, 4);
164                         buf += 4;
165                 }
166                 len %= 4;
167         }
168         if (len > 0) {
169                 /* Read the rest 1 - 3 bytes from FIFO */
170                 val = musb_readl(fifo, 0);
171                 memcpy(buf, &val, len);
172         }
173 }
174 
175 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
176 {
177         struct musb *musb = hw_ep->musb;
178         void __iomem    *ep_conf = hw_ep->conf;
179         void __iomem    *fifo = hw_ep->fifo;
180         u8              epnum = hw_ep->epnum;
181 
182         prefetch(buf);
183 
184         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
185                         'T', epnum, fifo, len, buf);
186 
187         if (epnum)
188                 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
189                         TUSB_EP_CONFIG_XFR_SIZE(len));
190         else
191                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
192                         TUSB_EP0_CONFIG_XFR_SIZE(len));
193 
194         if (likely((0x01 & (unsigned long) buf) == 0)) {
195 
196                 /* Best case is 32bit-aligned destination address */
197                 if ((0x02 & (unsigned long) buf) == 0) {
198                         if (len >= 4) {
199                                 iowrite32_rep(fifo, buf, len >> 2);
200                                 buf += (len & ~0x03);
201                                 len &= 0x03;
202                         }
203                 } else {
204                         if (len >= 2) {
205                                 u32 val;
206                                 int i;
207 
208                                 /* Cannot use writesw, fifo is 32-bit */
209                                 for (i = 0; i < (len >> 2); i++) {
210                                         val = (u32)(*(u16 *)buf);
211                                         buf += 2;
212                                         val |= (*(u16 *)buf) << 16;
213                                         buf += 2;
214                                         musb_writel(fifo, 0, val);
215                                 }
216                                 len &= 0x03;
217                         }
218                 }
219         }
220 
221         if (len > 0)
222                 tusb_fifo_write_unaligned(fifo, buf, len);
223 }
224 
225 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
226 {
227         struct musb *musb = hw_ep->musb;
228         void __iomem    *ep_conf = hw_ep->conf;
229         void __iomem    *fifo = hw_ep->fifo;
230         u8              epnum = hw_ep->epnum;
231 
232         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
233                         'R', epnum, fifo, len, buf);
234 
235         if (epnum)
236                 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
237                         TUSB_EP_CONFIG_XFR_SIZE(len));
238         else
239                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
240 
241         if (likely((0x01 & (unsigned long) buf) == 0)) {
242 
243                 /* Best case is 32bit-aligned destination address */
244                 if ((0x02 & (unsigned long) buf) == 0) {
245                         if (len >= 4) {
246                                 ioread32_rep(fifo, buf, len >> 2);
247                                 buf += (len & ~0x03);
248                                 len &= 0x03;
249                         }
250                 } else {
251                         if (len >= 2) {
252                                 u32 val;
253                                 int i;
254 
255                                 /* Cannot use readsw, fifo is 32-bit */
256                                 for (i = 0; i < (len >> 2); i++) {
257                                         val = musb_readl(fifo, 0);
258                                         *(u16 *)buf = (u16)(val & 0xffff);
259                                         buf += 2;
260                                         *(u16 *)buf = (u16)(val >> 16);
261                                         buf += 2;
262                                 }
263                                 len &= 0x03;
264                         }
265                 }
266         }
267 
268         if (len > 0)
269                 tusb_fifo_read_unaligned(fifo, buf, len);
270 }
271 
272 static struct musb *the_musb;
273 
274 /* This is used by gadget drivers, and OTG transceiver logic, allowing
275  * at most mA current to be drawn from VBUS during a Default-B session
276  * (that is, while VBUS exceeds 4.4V).  In Default-A (including pure host
277  * mode), or low power Default-B sessions, something else supplies power.
278  * Caller must take care of locking.
279  */
280 static int tusb_draw_power(struct usb_phy *x, unsigned mA)
281 {
282         struct musb     *musb = the_musb;
283         void __iomem    *tbase = musb->ctrl_base;
284         u32             reg;
285 
286         /* tps65030 seems to consume max 100mA, with maybe 60mA available
287          * (measured on one board) for things other than tps and tusb.
288          *
289          * Boards sharing the CPU clock with CLKIN will need to prevent
290          * certain idle sleep states while the USB link is active.
291          *
292          * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
293          * The actual current usage would be very board-specific.  For now,
294          * it's simpler to just use an aggregate (also board-specific).
295          */
296         if (x->otg->default_a || mA < (musb->min_power << 1))
297                 mA = 0;
298 
299         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
300         if (mA) {
301                 musb->is_bus_powered = 1;
302                 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
303         } else {
304                 musb->is_bus_powered = 0;
305                 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
306         }
307         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
308 
309         dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
310         return 0;
311 }
312 
313 /* workaround for issue 13:  change clock during chip idle
314  * (to be fixed in rev3 silicon) ... symptoms include disconnect
315  * or looping suspend/resume cycles
316  */
317 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
318 {
319         void __iomem    *tbase = musb->ctrl_base;
320         u32             reg;
321 
322         reg = musb_readl(tbase, TUSB_PRCM_CONF);
323         reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
324 
325         /* 0 = refclk (clkin, XI)
326          * 1 = PHY 60 MHz (internal PLL)
327          * 2 = not supported
328          * 3 = what?
329          */
330         if (mode > 0)
331                 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
332 
333         musb_writel(tbase, TUSB_PRCM_CONF, reg);
334 
335         /* FIXME tusb6010_platform_retime(mode == 0); */
336 }
337 
338 /*
339  * Idle TUSB6010 until next wake-up event; NOR access always wakes.
340  * Other code ensures that we idle unless we're connected _and_ the
341  * USB link is not suspended ... and tells us the relevant wakeup
342  * events.  SW_EN for voltage is handled separately.
343  */
344 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
345 {
346         void __iomem    *tbase = musb->ctrl_base;
347         u32             reg;
348 
349         if ((wakeup_enables & TUSB_PRCM_WBUS)
350                         && (musb->tusb_revision == TUSB_REV_30))
351                 tusb_wbus_quirk(musb, 1);
352 
353         tusb_set_clock_source(musb, 0);
354 
355         wakeup_enables |= TUSB_PRCM_WNORCS;
356         musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
357 
358         /* REVISIT writeup of WID implies that if WID set and ID is grounded,
359          * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
360          * Presumably that's mostly to save power, hence WID is immaterial ...
361          */
362 
363         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
364         /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
365         if (is_host_active(musb)) {
366                 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
367                 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
368         } else {
369                 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
370                 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
371         }
372         reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
373         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
374 
375         dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
376 }
377 
378 /*
379  * Updates cable VBUS status. Caller must take care of locking.
380  */
381 static int tusb_musb_vbus_status(struct musb *musb)
382 {
383         void __iomem    *tbase = musb->ctrl_base;
384         u32             otg_stat, prcm_mngmt;
385         int             ret = 0;
386 
387         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
388         prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
389 
390         /* Temporarily enable VBUS detection if it was disabled for
391          * suspend mode. Unless it's enabled otg_stat and devctl will
392          * not show correct VBUS state.
393          */
394         if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
395                 u32 tmp = prcm_mngmt;
396                 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
397                 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
398                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
399                 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
400         }
401 
402         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
403                 ret = 1;
404 
405         return ret;
406 }
407 
408 static struct timer_list musb_idle_timer;
409 
410 static void musb_do_idle(unsigned long _musb)
411 {
412         struct musb     *musb = (void *)_musb;
413         unsigned long   flags;
414 
415         spin_lock_irqsave(&musb->lock, flags);
416 
417         switch (musb->xceiv->state) {
418         case OTG_STATE_A_WAIT_BCON:
419                 if ((musb->a_wait_bcon != 0)
420                         && (musb->idle_timeout == 0
421                                 || time_after(jiffies, musb->idle_timeout))) {
422                         dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
423                                         usb_otg_state_string(musb->xceiv->state));
424                 }
425                 /* FALLTHROUGH */
426         case OTG_STATE_A_IDLE:
427                 tusb_musb_set_vbus(musb, 0);
428         default:
429                 break;
430         }
431 
432         if (!musb->is_active) {
433                 u32     wakeups;
434 
435                 /* wait until khubd handles port change status */
436                 if (is_host_active(musb) && (musb->port1_status >> 16))
437                         goto done;
438 
439                 if (!musb->gadget_driver) {
440                         wakeups = 0;
441                 } else {
442                         wakeups = TUSB_PRCM_WHOSTDISCON
443                                 | TUSB_PRCM_WBUS
444                                         | TUSB_PRCM_WVBUS;
445                         wakeups |= TUSB_PRCM_WID;
446                 }
447                 tusb_allow_idle(musb, wakeups);
448         }
449 done:
450         spin_unlock_irqrestore(&musb->lock, flags);
451 }
452 
453 /*
454  * Maybe put TUSB6010 into idle mode mode depending on USB link status,
455  * like "disconnected" or "suspended".  We'll be woken out of it by
456  * connect, resume, or disconnect.
457  *
458  * Needs to be called as the last function everywhere where there is
459  * register access to TUSB6010 because of NOR flash wake-up.
460  * Caller should own controller spinlock.
461  *
462  * Delay because peripheral enables D+ pullup 3msec after SE0, and
463  * we don't want to treat that full speed J as a wakeup event.
464  * ... peripherals must draw only suspend current after 10 msec.
465  */
466 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
467 {
468         unsigned long           default_timeout = jiffies + msecs_to_jiffies(3);
469         static unsigned long    last_timer;
470 
471         if (timeout == 0)
472                 timeout = default_timeout;
473 
474         /* Never idle if active, or when VBUS timeout is not set as host */
475         if (musb->is_active || ((musb->a_wait_bcon == 0)
476                         && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
477                 dev_dbg(musb->controller, "%s active, deleting timer\n",
478                         usb_otg_state_string(musb->xceiv->state));
479                 del_timer(&musb_idle_timer);
480                 last_timer = jiffies;
481                 return;
482         }
483 
484         if (time_after(last_timer, timeout)) {
485                 if (!timer_pending(&musb_idle_timer))
486                         last_timer = timeout;
487                 else {
488                         dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
489                         return;
490                 }
491         }
492         last_timer = timeout;
493 
494         dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
495                 usb_otg_state_string(musb->xceiv->state),
496                 (unsigned long)jiffies_to_msecs(timeout - jiffies));
497         mod_timer(&musb_idle_timer, timeout);
498 }
499 
500 /* ticks of 60 MHz clock */
501 #define DEVCLOCK                60000000
502 #define OTG_TIMER_MS(msecs)     ((msecs) \
503                 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
504                                 | TUSB_DEV_OTG_TIMER_ENABLE) \
505                 : 0)
506 
507 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
508 {
509         void __iomem    *tbase = musb->ctrl_base;
510         u32             conf, prcm, timer;
511         u8              devctl;
512         struct usb_otg  *otg = musb->xceiv->otg;
513 
514         /* HDRC controls CPEN, but beware current surges during device
515          * connect.  They can trigger transient overcurrent conditions
516          * that must be ignored.
517          */
518 
519         prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
520         conf = musb_readl(tbase, TUSB_DEV_CONF);
521         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
522 
523         if (is_on) {
524                 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
525                 otg->default_a = 1;
526                 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
527                 devctl |= MUSB_DEVCTL_SESSION;
528 
529                 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
530                 MUSB_HST_MODE(musb);
531         } else {
532                 u32     otg_stat;
533 
534                 timer = 0;
535 
536                 /* If ID pin is grounded, we want to be a_idle */
537                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
538                 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
539                         switch (musb->xceiv->state) {
540                         case OTG_STATE_A_WAIT_VRISE:
541                         case OTG_STATE_A_WAIT_BCON:
542                                 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
543                                 break;
544                         case OTG_STATE_A_WAIT_VFALL:
545                                 musb->xceiv->state = OTG_STATE_A_IDLE;
546                                 break;
547                         default:
548                                 musb->xceiv->state = OTG_STATE_A_IDLE;
549                         }
550                         musb->is_active = 0;
551                         otg->default_a = 1;
552                         MUSB_HST_MODE(musb);
553                 } else {
554                         musb->is_active = 0;
555                         otg->default_a = 0;
556                         musb->xceiv->state = OTG_STATE_B_IDLE;
557                         MUSB_DEV_MODE(musb);
558                 }
559 
560                 devctl &= ~MUSB_DEVCTL_SESSION;
561                 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
562         }
563         prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
564 
565         musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
566         musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
567         musb_writel(tbase, TUSB_DEV_CONF, conf);
568         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
569 
570         dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
571                 usb_otg_state_string(musb->xceiv->state),
572                 musb_readb(musb->mregs, MUSB_DEVCTL),
573                 musb_readl(tbase, TUSB_DEV_OTG_STAT),
574                 conf, prcm);
575 }
576 
577 /*
578  * Sets the mode to OTG, peripheral or host by changing the ID detection.
579  * Caller must take care of locking.
580  *
581  * Note that if a mini-A cable is plugged in the ID line will stay down as
582  * the weak ID pull-up is not able to pull the ID up.
583  */
584 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
585 {
586         void __iomem    *tbase = musb->ctrl_base;
587         u32             otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
588 
589         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
590         phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
591         phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
592         dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
593 
594         switch (musb_mode) {
595 
596         case MUSB_HOST:         /* Disable PHY ID detect, ground ID */
597                 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
598                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
599                 dev_conf |= TUSB_DEV_CONF_ID_SEL;
600                 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
601                 break;
602         case MUSB_PERIPHERAL:   /* Disable PHY ID detect, keep ID pull-up on */
603                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
604                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
605                 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
606                 break;
607         case MUSB_OTG:          /* Use PHY ID detection */
608                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
609                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
610                 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
611                 break;
612 
613         default:
614                 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
615                 return -EINVAL;
616         }
617 
618         musb_writel(tbase, TUSB_PHY_OTG_CTRL,
619                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
620         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
621                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
622         musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
623 
624         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
625         if ((musb_mode == MUSB_PERIPHERAL) &&
626                 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
627                         INFO("Cannot be peripheral with mini-A cable "
628                         "otg_stat: %08x\n", otg_stat);
629 
630         return 0;
631 }
632 
633 static inline unsigned long
634 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
635 {
636         u32             otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
637         unsigned long   idle_timeout = 0;
638         struct usb_otg  *otg = musb->xceiv->otg;
639 
640         /* ID pin */
641         if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
642                 int     default_a;
643 
644                 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
645                 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
646                 otg->default_a = default_a;
647                 tusb_musb_set_vbus(musb, default_a);
648 
649                 /* Don't allow idling immediately */
650                 if (default_a)
651                         idle_timeout = jiffies + (HZ * 3);
652         }
653 
654         /* VBUS state change */
655         if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
656 
657                 /* B-dev state machine:  no vbus ~= disconnect */
658                 if (!otg->default_a) {
659                         /* ? musb_root_disconnect(musb); */
660                         musb->port1_status &=
661                                 ~(USB_PORT_STAT_CONNECTION
662                                 | USB_PORT_STAT_ENABLE
663                                 | USB_PORT_STAT_LOW_SPEED
664                                 | USB_PORT_STAT_HIGH_SPEED
665                                 | USB_PORT_STAT_TEST
666                                 );
667 
668                         if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
669                                 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
670                                 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
671                                         /* INTR_DISCONNECT can hide... */
672                                         musb->xceiv->state = OTG_STATE_B_IDLE;
673                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
674                                 }
675                                 musb->is_active = 0;
676                         }
677                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
678                                 usb_otg_state_string(musb->xceiv->state), otg_stat);
679                         idle_timeout = jiffies + (1 * HZ);
680                         schedule_work(&musb->irq_work);
681 
682                 } else /* A-dev state machine */ {
683                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
684                                 usb_otg_state_string(musb->xceiv->state), otg_stat);
685 
686                         switch (musb->xceiv->state) {
687                         case OTG_STATE_A_IDLE:
688                                 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
689                                 musb_platform_set_vbus(musb, 1);
690 
691                                 /* CONNECT can wake if a_wait_bcon is set */
692                                 if (musb->a_wait_bcon != 0)
693                                         musb->is_active = 0;
694                                 else
695                                         musb->is_active = 1;
696 
697                                 /*
698                                  * OPT FS A TD.4.6 needs few seconds for
699                                  * A_WAIT_VRISE
700                                  */
701                                 idle_timeout = jiffies + (2 * HZ);
702 
703                                 break;
704                         case OTG_STATE_A_WAIT_VRISE:
705                                 /* ignore; A-session-valid < VBUS_VALID/2,
706                                  * we monitor this with the timer
707                                  */
708                                 break;
709                         case OTG_STATE_A_WAIT_VFALL:
710                                 /* REVISIT this irq triggers during short
711                                  * spikes caused by enumeration ...
712                                  */
713                                 if (musb->vbuserr_retry) {
714                                         musb->vbuserr_retry--;
715                                         tusb_musb_set_vbus(musb, 1);
716                                 } else {
717                                         musb->vbuserr_retry
718                                                 = VBUSERR_RETRY_COUNT;
719                                         tusb_musb_set_vbus(musb, 0);
720                                 }
721                                 break;
722                         default:
723                                 break;
724                         }
725                 }
726         }
727 
728         /* OTG timer expiration */
729         if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
730                 u8      devctl;
731 
732                 dev_dbg(musb->controller, "%s timer, %03x\n",
733                         usb_otg_state_string(musb->xceiv->state), otg_stat);
734 
735                 switch (musb->xceiv->state) {
736                 case OTG_STATE_A_WAIT_VRISE:
737                         /* VBUS has probably been valid for a while now,
738                          * but may well have bounced out of range a bit
739                          */
740                         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
741                         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
742                                 if ((devctl & MUSB_DEVCTL_VBUS)
743                                                 != MUSB_DEVCTL_VBUS) {
744                                         dev_dbg(musb->controller, "devctl %02x\n", devctl);
745                                         break;
746                                 }
747                                 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
748                                 musb->is_active = 0;
749                                 idle_timeout = jiffies
750                                         + msecs_to_jiffies(musb->a_wait_bcon);
751                         } else {
752                                 /* REVISIT report overcurrent to hub? */
753                                 ERR("vbus too slow, devctl %02x\n", devctl);
754                                 tusb_musb_set_vbus(musb, 0);
755                         }
756                         break;
757                 case OTG_STATE_A_WAIT_BCON:
758                         if (musb->a_wait_bcon != 0)
759                                 idle_timeout = jiffies
760                                         + msecs_to_jiffies(musb->a_wait_bcon);
761                         break;
762                 case OTG_STATE_A_SUSPEND:
763                         break;
764                 case OTG_STATE_B_WAIT_ACON:
765                         break;
766                 default:
767                         break;
768                 }
769         }
770         schedule_work(&musb->irq_work);
771 
772         return idle_timeout;
773 }
774 
775 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
776 {
777         struct musb     *musb = __hci;
778         void __iomem    *tbase = musb->ctrl_base;
779         unsigned long   flags, idle_timeout = 0;
780         u32             int_mask, int_src;
781 
782         spin_lock_irqsave(&musb->lock, flags);
783 
784         /* Mask all interrupts to allow using both edge and level GPIO irq */
785         int_mask = musb_readl(tbase, TUSB_INT_MASK);
786         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
787 
788         int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
789         dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
790 
791         musb->int_usb = (u8) int_src;
792 
793         /* Acknowledge wake-up source interrupts */
794         if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
795                 u32     reg;
796                 u32     i;
797 
798                 if (musb->tusb_revision == TUSB_REV_30)
799                         tusb_wbus_quirk(musb, 0);
800 
801                 /* there are issues re-locking the PLL on wakeup ... */
802 
803                 /* work around issue 8 */
804                 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
805                         musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
806                         musb_writel(tbase, TUSB_SCRATCH_PAD, i);
807                         reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
808                         if (reg == i)
809                                 break;
810                         dev_dbg(musb->controller, "TUSB NOR not ready\n");
811                 }
812 
813                 /* work around issue 13 (2nd half) */
814                 tusb_set_clock_source(musb, 1);
815 
816                 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
817                 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
818                 if (reg & ~TUSB_PRCM_WNORCS) {
819                         musb->is_active = 1;
820                         schedule_work(&musb->irq_work);
821                 }
822                 dev_dbg(musb->controller, "wake %sactive %02x\n",
823                                 musb->is_active ? "" : "in", reg);
824 
825                 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
826         }
827 
828         if (int_src & TUSB_INT_SRC_USB_IP_CONN)
829                 del_timer(&musb_idle_timer);
830 
831         /* OTG state change reports (annoyingly) not issued by Mentor core */
832         if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
833                                 | TUSB_INT_SRC_OTG_TIMEOUT
834                                 | TUSB_INT_SRC_ID_STATUS_CHNG))
835                 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
836 
837         /* TX dma callback must be handled here, RX dma callback is
838          * handled in tusb_omap_dma_cb.
839          */
840         if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
841                 u32     dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
842                 u32     real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
843 
844                 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
845                 real_dma_src = ~real_dma_src & dma_src;
846                 if (tusb_dma_omap() && real_dma_src) {
847                         int     tx_source = (real_dma_src & 0xffff);
848                         int     i;
849 
850                         for (i = 1; i <= 15; i++) {
851                                 if (tx_source & (1 << i)) {
852                                         dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
853                                         musb_dma_completion(musb, i, 1);
854                                 }
855                         }
856                 }
857                 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
858         }
859 
860         /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
861         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
862                 u32     musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
863 
864                 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
865                 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
866                 musb->int_tx = (musb_src & 0xffff);
867         } else {
868                 musb->int_rx = 0;
869                 musb->int_tx = 0;
870         }
871 
872         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
873                 musb_interrupt(musb);
874 
875         /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
876         musb_writel(tbase, TUSB_INT_SRC_CLEAR,
877                 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
878 
879         tusb_musb_try_idle(musb, idle_timeout);
880 
881         musb_writel(tbase, TUSB_INT_MASK, int_mask);
882         spin_unlock_irqrestore(&musb->lock, flags);
883 
884         return IRQ_HANDLED;
885 }
886 
887 static int dma_off;
888 
889 /*
890  * Enables TUSB6010. Caller must take care of locking.
891  * REVISIT:
892  * - Check what is unnecessary in MGC_HdrcStart()
893  */
894 static void tusb_musb_enable(struct musb *musb)
895 {
896         void __iomem    *tbase = musb->ctrl_base;
897 
898         /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
899          * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
900         musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
901 
902         /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
903         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
904         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
905         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
906 
907         /* Clear all subsystem interrups */
908         musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
909         musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
910         musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
911 
912         /* Acknowledge pending interrupt(s) */
913         musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
914 
915         /* Only 0 clock cycles for minimum interrupt de-assertion time and
916          * interrupt polarity active low seems to work reliably here */
917         musb_writel(tbase, TUSB_INT_CTRL_CONF,
918                         TUSB_INT_CTRL_CONF_INT_RELCYC(0));
919 
920         irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
921 
922         /* maybe force into the Default-A OTG state machine */
923         if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
924                         & TUSB_DEV_OTG_STAT_ID_STATUS))
925                 musb_writel(tbase, TUSB_INT_SRC_SET,
926                                 TUSB_INT_SRC_ID_STATUS_CHNG);
927 
928         if (is_dma_capable() && dma_off)
929                 printk(KERN_WARNING "%s %s: dma not reactivated\n",
930                                 __FILE__, __func__);
931         else
932                 dma_off = 1;
933 }
934 
935 /*
936  * Disables TUSB6010. Caller must take care of locking.
937  */
938 static void tusb_musb_disable(struct musb *musb)
939 {
940         void __iomem    *tbase = musb->ctrl_base;
941 
942         /* FIXME stop DMA, IRQs, timers, ... */
943 
944         /* disable all IRQs */
945         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
946         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
947         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
948         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
949 
950         del_timer(&musb_idle_timer);
951 
952         if (is_dma_capable() && !dma_off) {
953                 printk(KERN_WARNING "%s %s: dma still active\n",
954                                 __FILE__, __func__);
955                 dma_off = 1;
956         }
957 }
958 
959 /*
960  * Sets up TUSB6010 CPU interface specific signals and registers
961  * Note: Settings optimized for OMAP24xx
962  */
963 static void tusb_setup_cpu_interface(struct musb *musb)
964 {
965         void __iomem    *tbase = musb->ctrl_base;
966 
967         /*
968          * Disable GPIO[5:0] pullups (used as output DMA requests)
969          * Don't disable GPIO[7:6] as they are needed for wake-up.
970          */
971         musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
972 
973         /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
974         musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
975 
976         /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
977         musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
978 
979         /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
980          * de-assertion time 2 system clocks p 62 */
981         musb_writel(tbase, TUSB_DMA_REQ_CONF,
982                 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
983                 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
984                 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
985 
986         /* Set 0 wait count for synchronous burst access */
987         musb_writel(tbase, TUSB_WAIT_COUNT, 1);
988 }
989 
990 static int tusb_musb_start(struct musb *musb)
991 {
992         void __iomem    *tbase = musb->ctrl_base;
993         int             ret = 0;
994         unsigned long   flags;
995         u32             reg;
996 
997         if (musb->board_set_power)
998                 ret = musb->board_set_power(1);
999         if (ret != 0) {
1000                 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1001                 return ret;
1002         }
1003 
1004         spin_lock_irqsave(&musb->lock, flags);
1005 
1006         if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1007                 TUSB_PROD_TEST_RESET_VAL) {
1008                 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1009                 goto err;
1010         }
1011 
1012         musb->tusb_revision = tusb_get_revision(musb);
1013         tusb_print_revision(musb);
1014         if (musb->tusb_revision < 2) {
1015                 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1016                                 musb->tusb_revision);
1017                 goto err;
1018         }
1019 
1020         /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1021          * NOR FLASH interface is used */
1022         musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1023 
1024         /* Select PHY free running 60MHz as a system clock */
1025         tusb_set_clock_source(musb, 1);
1026 
1027         /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1028          * power saving, enable VBus detect and session end comparators,
1029          * enable IDpullup, enable VBus charging */
1030         musb_writel(tbase, TUSB_PRCM_MNGMT,
1031                 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1032                 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1033                 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1034                 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1035                 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1036         tusb_setup_cpu_interface(musb);
1037 
1038         /* simplify:  always sense/pullup ID pins, as if in OTG mode */
1039         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1040         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1041         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1042 
1043         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1044         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1045         musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1046 
1047         spin_unlock_irqrestore(&musb->lock, flags);
1048 
1049         return 0;
1050 
1051 err:
1052         spin_unlock_irqrestore(&musb->lock, flags);
1053 
1054         if (musb->board_set_power)
1055                 musb->board_set_power(0);
1056 
1057         return -ENODEV;
1058 }
1059 
1060 static int tusb_musb_init(struct musb *musb)
1061 {
1062         struct platform_device  *pdev;
1063         struct resource         *mem;
1064         void __iomem            *sync = NULL;
1065         int                     ret;
1066 
1067         musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
1068         if (IS_ERR_OR_NULL(musb->xceiv))
1069                 return -EPROBE_DEFER;
1070 
1071         pdev = to_platform_device(musb->controller);
1072 
1073         /* dma address for async dma */
1074         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1075         musb->async = mem->start;
1076 
1077         /* dma address for sync dma */
1078         mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1079         if (!mem) {
1080                 pr_debug("no sync dma resource?\n");
1081                 ret = -ENODEV;
1082                 goto done;
1083         }
1084         musb->sync = mem->start;
1085 
1086         sync = ioremap(mem->start, resource_size(mem));
1087         if (!sync) {
1088                 pr_debug("ioremap for sync failed\n");
1089                 ret = -ENOMEM;
1090                 goto done;
1091         }
1092         musb->sync_va = sync;
1093 
1094         /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1095          * FIFOs at 0x600, TUSB at 0x800
1096          */
1097         musb->mregs += TUSB_BASE_OFFSET;
1098 
1099         ret = tusb_musb_start(musb);
1100         if (ret) {
1101                 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1102                                 ret);
1103                 goto done;
1104         }
1105         musb->isr = tusb_musb_interrupt;
1106 
1107         musb->xceiv->set_power = tusb_draw_power;
1108         the_musb = musb;
1109 
1110         setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1111 
1112 done:
1113         if (ret < 0) {
1114                 if (sync)
1115                         iounmap(sync);
1116 
1117                 usb_put_phy(musb->xceiv);
1118         }
1119         return ret;
1120 }
1121 
1122 static int tusb_musb_exit(struct musb *musb)
1123 {
1124         del_timer_sync(&musb_idle_timer);
1125         the_musb = NULL;
1126 
1127         if (musb->board_set_power)
1128                 musb->board_set_power(0);
1129 
1130         iounmap(musb->sync_va);
1131 
1132         usb_put_phy(musb->xceiv);
1133         return 0;
1134 }
1135 
1136 static const struct musb_platform_ops tusb_ops = {
1137         .init           = tusb_musb_init,
1138         .exit           = tusb_musb_exit,
1139 
1140         .enable         = tusb_musb_enable,
1141         .disable        = tusb_musb_disable,
1142 
1143         .set_mode       = tusb_musb_set_mode,
1144         .try_idle       = tusb_musb_try_idle,
1145 
1146         .vbus_status    = tusb_musb_vbus_status,
1147         .set_vbus       = tusb_musb_set_vbus,
1148 };
1149 
1150 static const struct platform_device_info tusb_dev_info = {
1151         .name           = "musb-hdrc",
1152         .id             = PLATFORM_DEVID_AUTO,
1153         .dma_mask       = DMA_BIT_MASK(32),
1154 };
1155 
1156 static int tusb_probe(struct platform_device *pdev)
1157 {
1158         struct resource musb_resources[3];
1159         struct musb_hdrc_platform_data  *pdata = dev_get_platdata(&pdev->dev);
1160         struct platform_device          *musb;
1161         struct tusb6010_glue            *glue;
1162         struct platform_device_info     pinfo;
1163         int                             ret = -ENOMEM;
1164 
1165         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1166         if (!glue) {
1167                 dev_err(&pdev->dev, "failed to allocate glue context\n");
1168                 goto err0;
1169         }
1170 
1171         glue->dev                       = &pdev->dev;
1172 
1173         pdata->platform_ops             = &tusb_ops;
1174 
1175         usb_phy_generic_register();
1176         platform_set_drvdata(pdev, glue);
1177 
1178         memset(musb_resources, 0x00, sizeof(*musb_resources) *
1179                         ARRAY_SIZE(musb_resources));
1180 
1181         musb_resources[0].name = pdev->resource[0].name;
1182         musb_resources[0].start = pdev->resource[0].start;
1183         musb_resources[0].end = pdev->resource[0].end;
1184         musb_resources[0].flags = pdev->resource[0].flags;
1185 
1186         musb_resources[1].name = pdev->resource[1].name;
1187         musb_resources[1].start = pdev->resource[1].start;
1188         musb_resources[1].end = pdev->resource[1].end;
1189         musb_resources[1].flags = pdev->resource[1].flags;
1190 
1191         musb_resources[2].name = pdev->resource[2].name;
1192         musb_resources[2].start = pdev->resource[2].start;
1193         musb_resources[2].end = pdev->resource[2].end;
1194         musb_resources[2].flags = pdev->resource[2].flags;
1195 
1196         pinfo = tusb_dev_info;
1197         pinfo.parent = &pdev->dev;
1198         pinfo.res = musb_resources;
1199         pinfo.num_res = ARRAY_SIZE(musb_resources);
1200         pinfo.data = pdata;
1201         pinfo.size_data = sizeof(*pdata);
1202 
1203         glue->musb = musb = platform_device_register_full(&pinfo);
1204         if (IS_ERR(musb)) {
1205                 ret = PTR_ERR(musb);
1206                 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
1207                 goto err3;
1208         }
1209 
1210         return 0;
1211 
1212 err3:
1213         kfree(glue);
1214 
1215 err0:
1216         return ret;
1217 }
1218 
1219 static int tusb_remove(struct platform_device *pdev)
1220 {
1221         struct tusb6010_glue            *glue = platform_get_drvdata(pdev);
1222 
1223         platform_device_unregister(glue->musb);
1224         usb_phy_generic_unregister(glue->phy);
1225         kfree(glue);
1226 
1227         return 0;
1228 }
1229 
1230 static struct platform_driver tusb_driver = {
1231         .probe          = tusb_probe,
1232         .remove         = tusb_remove,
1233         .driver         = {
1234                 .name   = "musb-tusb",
1235         },
1236 };
1237 
1238 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1239 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1240 MODULE_LICENSE("GPL v2");
1241 module_platform_driver(tusb_driver);
1242 

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