Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/usb/musb/tusb6010.c

  1 /*
  2  * TUSB6010 USB 2.0 OTG Dual Role controller
  3  *
  4  * Copyright (C) 2006 Nokia Corporation
  5  * Tony Lindgren <tony@atomide.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10  *
 11  * Notes:
 12  * - Driver assumes that interface to external host (main CPU) is
 13  *   configured for NOR FLASH interface instead of VLYNQ serial
 14  *   interface.
 15  */
 16 
 17 #include <linux/module.h>
 18 #include <linux/kernel.h>
 19 #include <linux/errno.h>
 20 #include <linux/err.h>
 21 #include <linux/prefetch.h>
 22 #include <linux/usb.h>
 23 #include <linux/irq.h>
 24 #include <linux/io.h>
 25 #include <linux/platform_device.h>
 26 #include <linux/dma-mapping.h>
 27 #include <linux/usb/usb_phy_gen_xceiv.h>
 28 
 29 #include "musb_core.h"
 30 
 31 struct tusb6010_glue {
 32         struct device           *dev;
 33         struct platform_device  *musb;
 34 };
 35 
 36 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
 37 
 38 #define TUSB_REV_MAJOR(reg_val)         ((reg_val >> 4) & 0xf)
 39 #define TUSB_REV_MINOR(reg_val)         (reg_val & 0xf)
 40 
 41 /*
 42  * Checks the revision. We need to use the DMA register as 3.0 does not
 43  * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
 44  */
 45 u8 tusb_get_revision(struct musb *musb)
 46 {
 47         void __iomem    *tbase = musb->ctrl_base;
 48         u32             die_id;
 49         u8              rev;
 50 
 51         rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
 52         if (TUSB_REV_MAJOR(rev) == 3) {
 53                 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
 54                                 TUSB_DIDR1_HI));
 55                 if (die_id >= TUSB_DIDR1_HI_REV_31)
 56                         rev |= 1;
 57         }
 58 
 59         return rev;
 60 }
 61 EXPORT_SYMBOL_GPL(tusb_get_revision);
 62 
 63 static int tusb_print_revision(struct musb *musb)
 64 {
 65         void __iomem    *tbase = musb->ctrl_base;
 66         u8              rev;
 67 
 68         rev = tusb_get_revision(musb);
 69 
 70         pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
 71                 "prcm",
 72                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
 73                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
 74                 "int",
 75                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
 76                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
 77                 "gpio",
 78                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
 79                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
 80                 "dma",
 81                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
 82                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
 83                 "dieid",
 84                 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
 85                 "rev",
 86                 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
 87 
 88         return tusb_get_revision(musb);
 89 }
 90 
 91 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
 92                                 | TUSB_PHY_OTG_CTRL_TESTM0)
 93 
 94 /*
 95  * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
 96  * Disables power detection in PHY for the duration of idle.
 97  */
 98 static void tusb_wbus_quirk(struct musb *musb, int enabled)
 99 {
100         void __iomem    *tbase = musb->ctrl_base;
101         static u32      phy_otg_ctrl, phy_otg_ena;
102         u32             tmp;
103 
104         if (enabled) {
105                 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
106                 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
107                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
108                                 | phy_otg_ena | WBUS_QUIRK_MASK;
109                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
110                 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
111                 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
112                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
113                 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
114                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
115                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
116         } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
117                                         & TUSB_PHY_OTG_CTRL_TESTM2) {
118                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
119                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
120                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
121                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
122                 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
123                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
124                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
125                 phy_otg_ctrl = 0;
126                 phy_otg_ena = 0;
127         }
128 }
129 
130 /*
131  * TUSB 6010 may use a parallel bus that doesn't support byte ops;
132  * so both loading and unloading FIFOs need explicit byte counts.
133  */
134 
135 static inline void
136 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
137 {
138         u32             val;
139         int             i;
140 
141         if (len > 4) {
142                 for (i = 0; i < (len >> 2); i++) {
143                         memcpy(&val, buf, 4);
144                         musb_writel(fifo, 0, val);
145                         buf += 4;
146                 }
147                 len %= 4;
148         }
149         if (len > 0) {
150                 /* Write the rest 1 - 3 bytes to FIFO */
151                 memcpy(&val, buf, len);
152                 musb_writel(fifo, 0, val);
153         }
154 }
155 
156 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
157                                                 void *buf, u16 len)
158 {
159         u32             val;
160         int             i;
161 
162         if (len > 4) {
163                 for (i = 0; i < (len >> 2); i++) {
164                         val = musb_readl(fifo, 0);
165                         memcpy(buf, &val, 4);
166                         buf += 4;
167                 }
168                 len %= 4;
169         }
170         if (len > 0) {
171                 /* Read the rest 1 - 3 bytes from FIFO */
172                 val = musb_readl(fifo, 0);
173                 memcpy(buf, &val, len);
174         }
175 }
176 
177 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
178 {
179         struct musb *musb = hw_ep->musb;
180         void __iomem    *ep_conf = hw_ep->conf;
181         void __iomem    *fifo = hw_ep->fifo;
182         u8              epnum = hw_ep->epnum;
183 
184         prefetch(buf);
185 
186         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
187                         'T', epnum, fifo, len, buf);
188 
189         if (epnum)
190                 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
191                         TUSB_EP_CONFIG_XFR_SIZE(len));
192         else
193                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
194                         TUSB_EP0_CONFIG_XFR_SIZE(len));
195 
196         if (likely((0x01 & (unsigned long) buf) == 0)) {
197 
198                 /* Best case is 32bit-aligned destination address */
199                 if ((0x02 & (unsigned long) buf) == 0) {
200                         if (len >= 4) {
201                                 iowrite32_rep(fifo, buf, len >> 2);
202                                 buf += (len & ~0x03);
203                                 len &= 0x03;
204                         }
205                 } else {
206                         if (len >= 2) {
207                                 u32 val;
208                                 int i;
209 
210                                 /* Cannot use writesw, fifo is 32-bit */
211                                 for (i = 0; i < (len >> 2); i++) {
212                                         val = (u32)(*(u16 *)buf);
213                                         buf += 2;
214                                         val |= (*(u16 *)buf) << 16;
215                                         buf += 2;
216                                         musb_writel(fifo, 0, val);
217                                 }
218                                 len &= 0x03;
219                         }
220                 }
221         }
222 
223         if (len > 0)
224                 tusb_fifo_write_unaligned(fifo, buf, len);
225 }
226 
227 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
228 {
229         struct musb *musb = hw_ep->musb;
230         void __iomem    *ep_conf = hw_ep->conf;
231         void __iomem    *fifo = hw_ep->fifo;
232         u8              epnum = hw_ep->epnum;
233 
234         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
235                         'R', epnum, fifo, len, buf);
236 
237         if (epnum)
238                 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
239                         TUSB_EP_CONFIG_XFR_SIZE(len));
240         else
241                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
242 
243         if (likely((0x01 & (unsigned long) buf) == 0)) {
244 
245                 /* Best case is 32bit-aligned destination address */
246                 if ((0x02 & (unsigned long) buf) == 0) {
247                         if (len >= 4) {
248                                 ioread32_rep(fifo, buf, len >> 2);
249                                 buf += (len & ~0x03);
250                                 len &= 0x03;
251                         }
252                 } else {
253                         if (len >= 2) {
254                                 u32 val;
255                                 int i;
256 
257                                 /* Cannot use readsw, fifo is 32-bit */
258                                 for (i = 0; i < (len >> 2); i++) {
259                                         val = musb_readl(fifo, 0);
260                                         *(u16 *)buf = (u16)(val & 0xffff);
261                                         buf += 2;
262                                         *(u16 *)buf = (u16)(val >> 16);
263                                         buf += 2;
264                                 }
265                                 len &= 0x03;
266                         }
267                 }
268         }
269 
270         if (len > 0)
271                 tusb_fifo_read_unaligned(fifo, buf, len);
272 }
273 
274 static struct musb *the_musb;
275 
276 /* This is used by gadget drivers, and OTG transceiver logic, allowing
277  * at most mA current to be drawn from VBUS during a Default-B session
278  * (that is, while VBUS exceeds 4.4V).  In Default-A (including pure host
279  * mode), or low power Default-B sessions, something else supplies power.
280  * Caller must take care of locking.
281  */
282 static int tusb_draw_power(struct usb_phy *x, unsigned mA)
283 {
284         struct musb     *musb = the_musb;
285         void __iomem    *tbase = musb->ctrl_base;
286         u32             reg;
287 
288         /* tps65030 seems to consume max 100mA, with maybe 60mA available
289          * (measured on one board) for things other than tps and tusb.
290          *
291          * Boards sharing the CPU clock with CLKIN will need to prevent
292          * certain idle sleep states while the USB link is active.
293          *
294          * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
295          * The actual current usage would be very board-specific.  For now,
296          * it's simpler to just use an aggregate (also board-specific).
297          */
298         if (x->otg->default_a || mA < (musb->min_power << 1))
299                 mA = 0;
300 
301         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
302         if (mA) {
303                 musb->is_bus_powered = 1;
304                 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
305         } else {
306                 musb->is_bus_powered = 0;
307                 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
308         }
309         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
310 
311         dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
312         return 0;
313 }
314 
315 /* workaround for issue 13:  change clock during chip idle
316  * (to be fixed in rev3 silicon) ... symptoms include disconnect
317  * or looping suspend/resume cycles
318  */
319 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
320 {
321         void __iomem    *tbase = musb->ctrl_base;
322         u32             reg;
323 
324         reg = musb_readl(tbase, TUSB_PRCM_CONF);
325         reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
326 
327         /* 0 = refclk (clkin, XI)
328          * 1 = PHY 60 MHz (internal PLL)
329          * 2 = not supported
330          * 3 = what?
331          */
332         if (mode > 0)
333                 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
334 
335         musb_writel(tbase, TUSB_PRCM_CONF, reg);
336 
337         /* FIXME tusb6010_platform_retime(mode == 0); */
338 }
339 
340 /*
341  * Idle TUSB6010 until next wake-up event; NOR access always wakes.
342  * Other code ensures that we idle unless we're connected _and_ the
343  * USB link is not suspended ... and tells us the relevant wakeup
344  * events.  SW_EN for voltage is handled separately.
345  */
346 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
347 {
348         void __iomem    *tbase = musb->ctrl_base;
349         u32             reg;
350 
351         if ((wakeup_enables & TUSB_PRCM_WBUS)
352                         && (tusb_get_revision(musb) == TUSB_REV_30))
353                 tusb_wbus_quirk(musb, 1);
354 
355         tusb_set_clock_source(musb, 0);
356 
357         wakeup_enables |= TUSB_PRCM_WNORCS;
358         musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
359 
360         /* REVISIT writeup of WID implies that if WID set and ID is grounded,
361          * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
362          * Presumably that's mostly to save power, hence WID is immaterial ...
363          */
364 
365         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
366         /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
367         if (is_host_active(musb)) {
368                 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
369                 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
370         } else {
371                 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
372                 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
373         }
374         reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
375         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
376 
377         dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
378 }
379 
380 /*
381  * Updates cable VBUS status. Caller must take care of locking.
382  */
383 static int tusb_musb_vbus_status(struct musb *musb)
384 {
385         void __iomem    *tbase = musb->ctrl_base;
386         u32             otg_stat, prcm_mngmt;
387         int             ret = 0;
388 
389         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
390         prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
391 
392         /* Temporarily enable VBUS detection if it was disabled for
393          * suspend mode. Unless it's enabled otg_stat and devctl will
394          * not show correct VBUS state.
395          */
396         if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
397                 u32 tmp = prcm_mngmt;
398                 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
399                 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
400                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
401                 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
402         }
403 
404         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
405                 ret = 1;
406 
407         return ret;
408 }
409 
410 static struct timer_list musb_idle_timer;
411 
412 static void musb_do_idle(unsigned long _musb)
413 {
414         struct musb     *musb = (void *)_musb;
415         unsigned long   flags;
416 
417         spin_lock_irqsave(&musb->lock, flags);
418 
419         switch (musb->xceiv->state) {
420         case OTG_STATE_A_WAIT_BCON:
421                 if ((musb->a_wait_bcon != 0)
422                         && (musb->idle_timeout == 0
423                                 || time_after(jiffies, musb->idle_timeout))) {
424                         dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
425                                         usb_otg_state_string(musb->xceiv->state));
426                 }
427                 /* FALLTHROUGH */
428         case OTG_STATE_A_IDLE:
429                 tusb_musb_set_vbus(musb, 0);
430         default:
431                 break;
432         }
433 
434         if (!musb->is_active) {
435                 u32     wakeups;
436 
437                 /* wait until khubd handles port change status */
438                 if (is_host_active(musb) && (musb->port1_status >> 16))
439                         goto done;
440 
441                 if (!musb->gadget_driver) {
442                         wakeups = 0;
443                 } else {
444                         wakeups = TUSB_PRCM_WHOSTDISCON
445                                 | TUSB_PRCM_WBUS
446                                         | TUSB_PRCM_WVBUS;
447                         wakeups |= TUSB_PRCM_WID;
448                 }
449                 tusb_allow_idle(musb, wakeups);
450         }
451 done:
452         spin_unlock_irqrestore(&musb->lock, flags);
453 }
454 
455 /*
456  * Maybe put TUSB6010 into idle mode mode depending on USB link status,
457  * like "disconnected" or "suspended".  We'll be woken out of it by
458  * connect, resume, or disconnect.
459  *
460  * Needs to be called as the last function everywhere where there is
461  * register access to TUSB6010 because of NOR flash wake-up.
462  * Caller should own controller spinlock.
463  *
464  * Delay because peripheral enables D+ pullup 3msec after SE0, and
465  * we don't want to treat that full speed J as a wakeup event.
466  * ... peripherals must draw only suspend current after 10 msec.
467  */
468 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
469 {
470         unsigned long           default_timeout = jiffies + msecs_to_jiffies(3);
471         static unsigned long    last_timer;
472 
473         if (timeout == 0)
474                 timeout = default_timeout;
475 
476         /* Never idle if active, or when VBUS timeout is not set as host */
477         if (musb->is_active || ((musb->a_wait_bcon == 0)
478                         && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
479                 dev_dbg(musb->controller, "%s active, deleting timer\n",
480                         usb_otg_state_string(musb->xceiv->state));
481                 del_timer(&musb_idle_timer);
482                 last_timer = jiffies;
483                 return;
484         }
485 
486         if (time_after(last_timer, timeout)) {
487                 if (!timer_pending(&musb_idle_timer))
488                         last_timer = timeout;
489                 else {
490                         dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
491                         return;
492                 }
493         }
494         last_timer = timeout;
495 
496         dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
497                 usb_otg_state_string(musb->xceiv->state),
498                 (unsigned long)jiffies_to_msecs(timeout - jiffies));
499         mod_timer(&musb_idle_timer, timeout);
500 }
501 
502 /* ticks of 60 MHz clock */
503 #define DEVCLOCK                60000000
504 #define OTG_TIMER_MS(msecs)     ((msecs) \
505                 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
506                                 | TUSB_DEV_OTG_TIMER_ENABLE) \
507                 : 0)
508 
509 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
510 {
511         void __iomem    *tbase = musb->ctrl_base;
512         u32             conf, prcm, timer;
513         u8              devctl;
514         struct usb_otg  *otg = musb->xceiv->otg;
515 
516         /* HDRC controls CPEN, but beware current surges during device
517          * connect.  They can trigger transient overcurrent conditions
518          * that must be ignored.
519          */
520 
521         prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
522         conf = musb_readl(tbase, TUSB_DEV_CONF);
523         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
524 
525         if (is_on) {
526                 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
527                 otg->default_a = 1;
528                 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
529                 devctl |= MUSB_DEVCTL_SESSION;
530 
531                 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
532                 MUSB_HST_MODE(musb);
533         } else {
534                 u32     otg_stat;
535 
536                 timer = 0;
537 
538                 /* If ID pin is grounded, we want to be a_idle */
539                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
540                 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
541                         switch (musb->xceiv->state) {
542                         case OTG_STATE_A_WAIT_VRISE:
543                         case OTG_STATE_A_WAIT_BCON:
544                                 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
545                                 break;
546                         case OTG_STATE_A_WAIT_VFALL:
547                                 musb->xceiv->state = OTG_STATE_A_IDLE;
548                                 break;
549                         default:
550                                 musb->xceiv->state = OTG_STATE_A_IDLE;
551                         }
552                         musb->is_active = 0;
553                         otg->default_a = 1;
554                         MUSB_HST_MODE(musb);
555                 } else {
556                         musb->is_active = 0;
557                         otg->default_a = 0;
558                         musb->xceiv->state = OTG_STATE_B_IDLE;
559                         MUSB_DEV_MODE(musb);
560                 }
561 
562                 devctl &= ~MUSB_DEVCTL_SESSION;
563                 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
564         }
565         prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
566 
567         musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
568         musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
569         musb_writel(tbase, TUSB_DEV_CONF, conf);
570         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
571 
572         dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
573                 usb_otg_state_string(musb->xceiv->state),
574                 musb_readb(musb->mregs, MUSB_DEVCTL),
575                 musb_readl(tbase, TUSB_DEV_OTG_STAT),
576                 conf, prcm);
577 }
578 
579 /*
580  * Sets the mode to OTG, peripheral or host by changing the ID detection.
581  * Caller must take care of locking.
582  *
583  * Note that if a mini-A cable is plugged in the ID line will stay down as
584  * the weak ID pull-up is not able to pull the ID up.
585  */
586 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
587 {
588         void __iomem    *tbase = musb->ctrl_base;
589         u32             otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
590 
591         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
592         phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
593         phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
594         dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
595 
596         switch (musb_mode) {
597 
598         case MUSB_HOST:         /* Disable PHY ID detect, ground ID */
599                 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
600                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
601                 dev_conf |= TUSB_DEV_CONF_ID_SEL;
602                 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
603                 break;
604         case MUSB_PERIPHERAL:   /* Disable PHY ID detect, keep ID pull-up on */
605                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
606                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
607                 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
608                 break;
609         case MUSB_OTG:          /* Use PHY ID detection */
610                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
611                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
612                 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
613                 break;
614 
615         default:
616                 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
617                 return -EINVAL;
618         }
619 
620         musb_writel(tbase, TUSB_PHY_OTG_CTRL,
621                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
622         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
623                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
624         musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
625 
626         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
627         if ((musb_mode == MUSB_PERIPHERAL) &&
628                 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
629                         INFO("Cannot be peripheral with mini-A cable "
630                         "otg_stat: %08x\n", otg_stat);
631 
632         return 0;
633 }
634 
635 static inline unsigned long
636 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
637 {
638         u32             otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
639         unsigned long   idle_timeout = 0;
640         struct usb_otg  *otg = musb->xceiv->otg;
641 
642         /* ID pin */
643         if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
644                 int     default_a;
645 
646                 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
647                 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
648                 otg->default_a = default_a;
649                 tusb_musb_set_vbus(musb, default_a);
650 
651                 /* Don't allow idling immediately */
652                 if (default_a)
653                         idle_timeout = jiffies + (HZ * 3);
654         }
655 
656         /* VBUS state change */
657         if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
658 
659                 /* B-dev state machine:  no vbus ~= disconnect */
660                 if (!otg->default_a) {
661                         /* ? musb_root_disconnect(musb); */
662                         musb->port1_status &=
663                                 ~(USB_PORT_STAT_CONNECTION
664                                 | USB_PORT_STAT_ENABLE
665                                 | USB_PORT_STAT_LOW_SPEED
666                                 | USB_PORT_STAT_HIGH_SPEED
667                                 | USB_PORT_STAT_TEST
668                                 );
669 
670                         if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
671                                 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
672                                 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
673                                         /* INTR_DISCONNECT can hide... */
674                                         musb->xceiv->state = OTG_STATE_B_IDLE;
675                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
676                                 }
677                                 musb->is_active = 0;
678                         }
679                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
680                                 usb_otg_state_string(musb->xceiv->state), otg_stat);
681                         idle_timeout = jiffies + (1 * HZ);
682                         schedule_work(&musb->irq_work);
683 
684                 } else /* A-dev state machine */ {
685                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
686                                 usb_otg_state_string(musb->xceiv->state), otg_stat);
687 
688                         switch (musb->xceiv->state) {
689                         case OTG_STATE_A_IDLE:
690                                 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
691                                 musb_platform_set_vbus(musb, 1);
692 
693                                 /* CONNECT can wake if a_wait_bcon is set */
694                                 if (musb->a_wait_bcon != 0)
695                                         musb->is_active = 0;
696                                 else
697                                         musb->is_active = 1;
698 
699                                 /*
700                                  * OPT FS A TD.4.6 needs few seconds for
701                                  * A_WAIT_VRISE
702                                  */
703                                 idle_timeout = jiffies + (2 * HZ);
704 
705                                 break;
706                         case OTG_STATE_A_WAIT_VRISE:
707                                 /* ignore; A-session-valid < VBUS_VALID/2,
708                                  * we monitor this with the timer
709                                  */
710                                 break;
711                         case OTG_STATE_A_WAIT_VFALL:
712                                 /* REVISIT this irq triggers during short
713                                  * spikes caused by enumeration ...
714                                  */
715                                 if (musb->vbuserr_retry) {
716                                         musb->vbuserr_retry--;
717                                         tusb_musb_set_vbus(musb, 1);
718                                 } else {
719                                         musb->vbuserr_retry
720                                                 = VBUSERR_RETRY_COUNT;
721                                         tusb_musb_set_vbus(musb, 0);
722                                 }
723                                 break;
724                         default:
725                                 break;
726                         }
727                 }
728         }
729 
730         /* OTG timer expiration */
731         if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
732                 u8      devctl;
733 
734                 dev_dbg(musb->controller, "%s timer, %03x\n",
735                         usb_otg_state_string(musb->xceiv->state), otg_stat);
736 
737                 switch (musb->xceiv->state) {
738                 case OTG_STATE_A_WAIT_VRISE:
739                         /* VBUS has probably been valid for a while now,
740                          * but may well have bounced out of range a bit
741                          */
742                         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
743                         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
744                                 if ((devctl & MUSB_DEVCTL_VBUS)
745                                                 != MUSB_DEVCTL_VBUS) {
746                                         dev_dbg(musb->controller, "devctl %02x\n", devctl);
747                                         break;
748                                 }
749                                 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
750                                 musb->is_active = 0;
751                                 idle_timeout = jiffies
752                                         + msecs_to_jiffies(musb->a_wait_bcon);
753                         } else {
754                                 /* REVISIT report overcurrent to hub? */
755                                 ERR("vbus too slow, devctl %02x\n", devctl);
756                                 tusb_musb_set_vbus(musb, 0);
757                         }
758                         break;
759                 case OTG_STATE_A_WAIT_BCON:
760                         if (musb->a_wait_bcon != 0)
761                                 idle_timeout = jiffies
762                                         + msecs_to_jiffies(musb->a_wait_bcon);
763                         break;
764                 case OTG_STATE_A_SUSPEND:
765                         break;
766                 case OTG_STATE_B_WAIT_ACON:
767                         break;
768                 default:
769                         break;
770                 }
771         }
772         schedule_work(&musb->irq_work);
773 
774         return idle_timeout;
775 }
776 
777 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
778 {
779         struct musb     *musb = __hci;
780         void __iomem    *tbase = musb->ctrl_base;
781         unsigned long   flags, idle_timeout = 0;
782         u32             int_mask, int_src;
783 
784         spin_lock_irqsave(&musb->lock, flags);
785 
786         /* Mask all interrupts to allow using both edge and level GPIO irq */
787         int_mask = musb_readl(tbase, TUSB_INT_MASK);
788         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
789 
790         int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
791         dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
792 
793         musb->int_usb = (u8) int_src;
794 
795         /* Acknowledge wake-up source interrupts */
796         if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
797                 u32     reg;
798                 u32     i;
799 
800                 if (tusb_get_revision(musb) == TUSB_REV_30)
801                         tusb_wbus_quirk(musb, 0);
802 
803                 /* there are issues re-locking the PLL on wakeup ... */
804 
805                 /* work around issue 8 */
806                 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
807                         musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
808                         musb_writel(tbase, TUSB_SCRATCH_PAD, i);
809                         reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
810                         if (reg == i)
811                                 break;
812                         dev_dbg(musb->controller, "TUSB NOR not ready\n");
813                 }
814 
815                 /* work around issue 13 (2nd half) */
816                 tusb_set_clock_source(musb, 1);
817 
818                 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
819                 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
820                 if (reg & ~TUSB_PRCM_WNORCS) {
821                         musb->is_active = 1;
822                         schedule_work(&musb->irq_work);
823                 }
824                 dev_dbg(musb->controller, "wake %sactive %02x\n",
825                                 musb->is_active ? "" : "in", reg);
826 
827                 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
828         }
829 
830         if (int_src & TUSB_INT_SRC_USB_IP_CONN)
831                 del_timer(&musb_idle_timer);
832 
833         /* OTG state change reports (annoyingly) not issued by Mentor core */
834         if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
835                                 | TUSB_INT_SRC_OTG_TIMEOUT
836                                 | TUSB_INT_SRC_ID_STATUS_CHNG))
837                 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
838 
839         /* TX dma callback must be handled here, RX dma callback is
840          * handled in tusb_omap_dma_cb.
841          */
842         if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
843                 u32     dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
844                 u32     real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
845 
846                 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
847                 real_dma_src = ~real_dma_src & dma_src;
848                 if (tusb_dma_omap() && real_dma_src) {
849                         int     tx_source = (real_dma_src & 0xffff);
850                         int     i;
851 
852                         for (i = 1; i <= 15; i++) {
853                                 if (tx_source & (1 << i)) {
854                                         dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
855                                         musb_dma_completion(musb, i, 1);
856                                 }
857                         }
858                 }
859                 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
860         }
861 
862         /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
863         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
864                 u32     musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
865 
866                 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
867                 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
868                 musb->int_tx = (musb_src & 0xffff);
869         } else {
870                 musb->int_rx = 0;
871                 musb->int_tx = 0;
872         }
873 
874         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
875                 musb_interrupt(musb);
876 
877         /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
878         musb_writel(tbase, TUSB_INT_SRC_CLEAR,
879                 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
880 
881         tusb_musb_try_idle(musb, idle_timeout);
882 
883         musb_writel(tbase, TUSB_INT_MASK, int_mask);
884         spin_unlock_irqrestore(&musb->lock, flags);
885 
886         return IRQ_HANDLED;
887 }
888 
889 static int dma_off;
890 
891 /*
892  * Enables TUSB6010. Caller must take care of locking.
893  * REVISIT:
894  * - Check what is unnecessary in MGC_HdrcStart()
895  */
896 static void tusb_musb_enable(struct musb *musb)
897 {
898         void __iomem    *tbase = musb->ctrl_base;
899 
900         /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
901          * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
902         musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
903 
904         /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
905         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
906         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
907         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
908 
909         /* Clear all subsystem interrups */
910         musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
911         musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
912         musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
913 
914         /* Acknowledge pending interrupt(s) */
915         musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
916 
917         /* Only 0 clock cycles for minimum interrupt de-assertion time and
918          * interrupt polarity active low seems to work reliably here */
919         musb_writel(tbase, TUSB_INT_CTRL_CONF,
920                         TUSB_INT_CTRL_CONF_INT_RELCYC(0));
921 
922         irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
923 
924         /* maybe force into the Default-A OTG state machine */
925         if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
926                         & TUSB_DEV_OTG_STAT_ID_STATUS))
927                 musb_writel(tbase, TUSB_INT_SRC_SET,
928                                 TUSB_INT_SRC_ID_STATUS_CHNG);
929 
930         if (is_dma_capable() && dma_off)
931                 printk(KERN_WARNING "%s %s: dma not reactivated\n",
932                                 __FILE__, __func__);
933         else
934                 dma_off = 1;
935 }
936 
937 /*
938  * Disables TUSB6010. Caller must take care of locking.
939  */
940 static void tusb_musb_disable(struct musb *musb)
941 {
942         void __iomem    *tbase = musb->ctrl_base;
943 
944         /* FIXME stop DMA, IRQs, timers, ... */
945 
946         /* disable all IRQs */
947         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
948         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
949         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
950         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
951 
952         del_timer(&musb_idle_timer);
953 
954         if (is_dma_capable() && !dma_off) {
955                 printk(KERN_WARNING "%s %s: dma still active\n",
956                                 __FILE__, __func__);
957                 dma_off = 1;
958         }
959 }
960 
961 /*
962  * Sets up TUSB6010 CPU interface specific signals and registers
963  * Note: Settings optimized for OMAP24xx
964  */
965 static void tusb_setup_cpu_interface(struct musb *musb)
966 {
967         void __iomem    *tbase = musb->ctrl_base;
968 
969         /*
970          * Disable GPIO[5:0] pullups (used as output DMA requests)
971          * Don't disable GPIO[7:6] as they are needed for wake-up.
972          */
973         musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
974 
975         /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
976         musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
977 
978         /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
979         musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
980 
981         /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
982          * de-assertion time 2 system clocks p 62 */
983         musb_writel(tbase, TUSB_DMA_REQ_CONF,
984                 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
985                 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
986                 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
987 
988         /* Set 0 wait count for synchronous burst access */
989         musb_writel(tbase, TUSB_WAIT_COUNT, 1);
990 }
991 
992 static int tusb_musb_start(struct musb *musb)
993 {
994         void __iomem    *tbase = musb->ctrl_base;
995         int             ret = 0;
996         unsigned long   flags;
997         u32             reg;
998 
999         if (musb->board_set_power)
1000                 ret = musb->board_set_power(1);
1001         if (ret != 0) {
1002                 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1003                 return ret;
1004         }
1005 
1006         spin_lock_irqsave(&musb->lock, flags);
1007 
1008         if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1009                 TUSB_PROD_TEST_RESET_VAL) {
1010                 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1011                 goto err;
1012         }
1013 
1014         ret = tusb_print_revision(musb);
1015         if (ret < 2) {
1016                 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1017                                 ret);
1018                 goto err;
1019         }
1020 
1021         /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1022          * NOR FLASH interface is used */
1023         musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1024 
1025         /* Select PHY free running 60MHz as a system clock */
1026         tusb_set_clock_source(musb, 1);
1027 
1028         /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1029          * power saving, enable VBus detect and session end comparators,
1030          * enable IDpullup, enable VBus charging */
1031         musb_writel(tbase, TUSB_PRCM_MNGMT,
1032                 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1033                 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1034                 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1035                 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1036                 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1037         tusb_setup_cpu_interface(musb);
1038 
1039         /* simplify:  always sense/pullup ID pins, as if in OTG mode */
1040         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1041         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1042         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1043 
1044         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1045         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1046         musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1047 
1048         spin_unlock_irqrestore(&musb->lock, flags);
1049 
1050         return 0;
1051 
1052 err:
1053         spin_unlock_irqrestore(&musb->lock, flags);
1054 
1055         if (musb->board_set_power)
1056                 musb->board_set_power(0);
1057 
1058         return -ENODEV;
1059 }
1060 
1061 static int tusb_musb_init(struct musb *musb)
1062 {
1063         struct platform_device  *pdev;
1064         struct resource         *mem;
1065         void __iomem            *sync = NULL;
1066         int                     ret;
1067 
1068         usb_nop_xceiv_register();
1069         musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
1070         if (IS_ERR_OR_NULL(musb->xceiv))
1071                 return -EPROBE_DEFER;
1072 
1073         pdev = to_platform_device(musb->controller);
1074 
1075         /* dma address for async dma */
1076         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1077         musb->async = mem->start;
1078 
1079         /* dma address for sync dma */
1080         mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1081         if (!mem) {
1082                 pr_debug("no sync dma resource?\n");
1083                 ret = -ENODEV;
1084                 goto done;
1085         }
1086         musb->sync = mem->start;
1087 
1088         sync = ioremap(mem->start, resource_size(mem));
1089         if (!sync) {
1090                 pr_debug("ioremap for sync failed\n");
1091                 ret = -ENOMEM;
1092                 goto done;
1093         }
1094         musb->sync_va = sync;
1095 
1096         /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1097          * FIFOs at 0x600, TUSB at 0x800
1098          */
1099         musb->mregs += TUSB_BASE_OFFSET;
1100 
1101         ret = tusb_musb_start(musb);
1102         if (ret) {
1103                 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1104                                 ret);
1105                 goto done;
1106         }
1107         musb->isr = tusb_musb_interrupt;
1108 
1109         musb->xceiv->set_power = tusb_draw_power;
1110         the_musb = musb;
1111 
1112         setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1113 
1114 done:
1115         if (ret < 0) {
1116                 if (sync)
1117                         iounmap(sync);
1118 
1119                 usb_put_phy(musb->xceiv);
1120                 usb_nop_xceiv_unregister();
1121         }
1122         return ret;
1123 }
1124 
1125 static int tusb_musb_exit(struct musb *musb)
1126 {
1127         del_timer_sync(&musb_idle_timer);
1128         the_musb = NULL;
1129 
1130         if (musb->board_set_power)
1131                 musb->board_set_power(0);
1132 
1133         iounmap(musb->sync_va);
1134 
1135         usb_put_phy(musb->xceiv);
1136         usb_nop_xceiv_unregister();
1137         return 0;
1138 }
1139 
1140 static const struct musb_platform_ops tusb_ops = {
1141         .init           = tusb_musb_init,
1142         .exit           = tusb_musb_exit,
1143 
1144         .enable         = tusb_musb_enable,
1145         .disable        = tusb_musb_disable,
1146 
1147         .set_mode       = tusb_musb_set_mode,
1148         .try_idle       = tusb_musb_try_idle,
1149 
1150         .vbus_status    = tusb_musb_vbus_status,
1151         .set_vbus       = tusb_musb_set_vbus,
1152 };
1153 
1154 static const struct platform_device_info tusb_dev_info = {
1155         .name           = "musb-hdrc",
1156         .id             = PLATFORM_DEVID_AUTO,
1157         .dma_mask       = DMA_BIT_MASK(32),
1158 };
1159 
1160 static int tusb_probe(struct platform_device *pdev)
1161 {
1162         struct resource musb_resources[3];
1163         struct musb_hdrc_platform_data  *pdata = dev_get_platdata(&pdev->dev);
1164         struct platform_device          *musb;
1165         struct tusb6010_glue            *glue;
1166         struct platform_device_info     pinfo;
1167         int                             ret = -ENOMEM;
1168 
1169         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1170         if (!glue) {
1171                 dev_err(&pdev->dev, "failed to allocate glue context\n");
1172                 goto err0;
1173         }
1174 
1175         glue->dev                       = &pdev->dev;
1176 
1177         pdata->platform_ops             = &tusb_ops;
1178 
1179         platform_set_drvdata(pdev, glue);
1180 
1181         memset(musb_resources, 0x00, sizeof(*musb_resources) *
1182                         ARRAY_SIZE(musb_resources));
1183 
1184         musb_resources[0].name = pdev->resource[0].name;
1185         musb_resources[0].start = pdev->resource[0].start;
1186         musb_resources[0].end = pdev->resource[0].end;
1187         musb_resources[0].flags = pdev->resource[0].flags;
1188 
1189         musb_resources[1].name = pdev->resource[1].name;
1190         musb_resources[1].start = pdev->resource[1].start;
1191         musb_resources[1].end = pdev->resource[1].end;
1192         musb_resources[1].flags = pdev->resource[1].flags;
1193 
1194         musb_resources[2].name = pdev->resource[2].name;
1195         musb_resources[2].start = pdev->resource[2].start;
1196         musb_resources[2].end = pdev->resource[2].end;
1197         musb_resources[2].flags = pdev->resource[2].flags;
1198 
1199         pinfo = tusb_dev_info;
1200         pinfo.parent = &pdev->dev;
1201         pinfo.res = musb_resources;
1202         pinfo.num_res = ARRAY_SIZE(musb_resources);
1203         pinfo.data = pdata;
1204         pinfo.size_data = sizeof(*pdata);
1205 
1206         glue->musb = musb = platform_device_register_full(&pinfo);
1207         if (IS_ERR(musb)) {
1208                 ret = PTR_ERR(musb);
1209                 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
1210                 goto err3;
1211         }
1212 
1213         return 0;
1214 
1215 err3:
1216         kfree(glue);
1217 
1218 err0:
1219         return ret;
1220 }
1221 
1222 static int tusb_remove(struct platform_device *pdev)
1223 {
1224         struct tusb6010_glue            *glue = platform_get_drvdata(pdev);
1225 
1226         platform_device_unregister(glue->musb);
1227         kfree(glue);
1228 
1229         return 0;
1230 }
1231 
1232 static struct platform_driver tusb_driver = {
1233         .probe          = tusb_probe,
1234         .remove         = tusb_remove,
1235         .driver         = {
1236                 .name   = "musb-tusb",
1237         },
1238 };
1239 
1240 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1241 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1242 MODULE_LICENSE("GPL v2");
1243 module_platform_driver(tusb_driver);
1244 

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