Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/usb/musb/tusb6010.c

  1 /*
  2  * TUSB6010 USB 2.0 OTG Dual Role controller
  3  *
  4  * Copyright (C) 2006 Nokia Corporation
  5  * Tony Lindgren <tony@atomide.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10  *
 11  * Notes:
 12  * - Driver assumes that interface to external host (main CPU) is
 13  *   configured for NOR FLASH interface instead of VLYNQ serial
 14  *   interface.
 15  */
 16 
 17 #include <linux/module.h>
 18 #include <linux/kernel.h>
 19 #include <linux/errno.h>
 20 #include <linux/err.h>
 21 #include <linux/prefetch.h>
 22 #include <linux/usb.h>
 23 #include <linux/irq.h>
 24 #include <linux/io.h>
 25 #include <linux/device.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/dma-mapping.h>
 28 #include <linux/usb/usb_phy_generic.h>
 29 
 30 #include "musb_core.h"
 31 
 32 struct tusb6010_glue {
 33         struct device           *dev;
 34         struct platform_device  *musb;
 35         struct platform_device  *phy;
 36 };
 37 
 38 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
 39 
 40 #define TUSB_REV_MAJOR(reg_val)         ((reg_val >> 4) & 0xf)
 41 #define TUSB_REV_MINOR(reg_val)         (reg_val & 0xf)
 42 
 43 /*
 44  * Checks the revision. We need to use the DMA register as 3.0 does not
 45  * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
 46  */
 47 static u8 tusb_get_revision(struct musb *musb)
 48 {
 49         void __iomem    *tbase = musb->ctrl_base;
 50         u32             die_id;
 51         u8              rev;
 52 
 53         rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
 54         if (TUSB_REV_MAJOR(rev) == 3) {
 55                 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
 56                                 TUSB_DIDR1_HI));
 57                 if (die_id >= TUSB_DIDR1_HI_REV_31)
 58                         rev |= 1;
 59         }
 60 
 61         return rev;
 62 }
 63 
 64 static void tusb_print_revision(struct musb *musb)
 65 {
 66         void __iomem    *tbase = musb->ctrl_base;
 67         u8              rev;
 68 
 69         rev = musb->tusb_revision;
 70 
 71         pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
 72                 "prcm",
 73                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
 74                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
 75                 "int",
 76                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
 77                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
 78                 "gpio",
 79                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
 80                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
 81                 "dma",
 82                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
 83                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
 84                 "dieid",
 85                 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
 86                 "rev",
 87                 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
 88 }
 89 
 90 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
 91                                 | TUSB_PHY_OTG_CTRL_TESTM0)
 92 
 93 /*
 94  * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
 95  * Disables power detection in PHY for the duration of idle.
 96  */
 97 static void tusb_wbus_quirk(struct musb *musb, int enabled)
 98 {
 99         void __iomem    *tbase = musb->ctrl_base;
100         static u32      phy_otg_ctrl, phy_otg_ena;
101         u32             tmp;
102 
103         if (enabled) {
104                 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
105                 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
106                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
107                                 | phy_otg_ena | WBUS_QUIRK_MASK;
108                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
109                 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
110                 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
111                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
112                 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
113                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
114                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
115         } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
116                                         & TUSB_PHY_OTG_CTRL_TESTM2) {
117                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
118                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
119                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
120                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
121                 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
122                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
123                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
124                 phy_otg_ctrl = 0;
125                 phy_otg_ena = 0;
126         }
127 }
128 
129 /*
130  * TUSB 6010 may use a parallel bus that doesn't support byte ops;
131  * so both loading and unloading FIFOs need explicit byte counts.
132  */
133 
134 static inline void
135 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
136 {
137         u32             val;
138         int             i;
139 
140         if (len > 4) {
141                 for (i = 0; i < (len >> 2); i++) {
142                         memcpy(&val, buf, 4);
143                         musb_writel(fifo, 0, val);
144                         buf += 4;
145                 }
146                 len %= 4;
147         }
148         if (len > 0) {
149                 /* Write the rest 1 - 3 bytes to FIFO */
150                 memcpy(&val, buf, len);
151                 musb_writel(fifo, 0, val);
152         }
153 }
154 
155 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
156                                                 void *buf, u16 len)
157 {
158         u32             val;
159         int             i;
160 
161         if (len > 4) {
162                 for (i = 0; i < (len >> 2); i++) {
163                         val = musb_readl(fifo, 0);
164                         memcpy(buf, &val, 4);
165                         buf += 4;
166                 }
167                 len %= 4;
168         }
169         if (len > 0) {
170                 /* Read the rest 1 - 3 bytes from FIFO */
171                 val = musb_readl(fifo, 0);
172                 memcpy(buf, &val, len);
173         }
174 }
175 
176 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
177 {
178         struct musb *musb = hw_ep->musb;
179         void __iomem    *ep_conf = hw_ep->conf;
180         void __iomem    *fifo = hw_ep->fifo;
181         u8              epnum = hw_ep->epnum;
182 
183         prefetch(buf);
184 
185         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
186                         'T', epnum, fifo, len, buf);
187 
188         if (epnum)
189                 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
190                         TUSB_EP_CONFIG_XFR_SIZE(len));
191         else
192                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
193                         TUSB_EP0_CONFIG_XFR_SIZE(len));
194 
195         if (likely((0x01 & (unsigned long) buf) == 0)) {
196 
197                 /* Best case is 32bit-aligned destination address */
198                 if ((0x02 & (unsigned long) buf) == 0) {
199                         if (len >= 4) {
200                                 iowrite32_rep(fifo, buf, len >> 2);
201                                 buf += (len & ~0x03);
202                                 len &= 0x03;
203                         }
204                 } else {
205                         if (len >= 2) {
206                                 u32 val;
207                                 int i;
208 
209                                 /* Cannot use writesw, fifo is 32-bit */
210                                 for (i = 0; i < (len >> 2); i++) {
211                                         val = (u32)(*(u16 *)buf);
212                                         buf += 2;
213                                         val |= (*(u16 *)buf) << 16;
214                                         buf += 2;
215                                         musb_writel(fifo, 0, val);
216                                 }
217                                 len &= 0x03;
218                         }
219                 }
220         }
221 
222         if (len > 0)
223                 tusb_fifo_write_unaligned(fifo, buf, len);
224 }
225 
226 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
227 {
228         struct musb *musb = hw_ep->musb;
229         void __iomem    *ep_conf = hw_ep->conf;
230         void __iomem    *fifo = hw_ep->fifo;
231         u8              epnum = hw_ep->epnum;
232 
233         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
234                         'R', epnum, fifo, len, buf);
235 
236         if (epnum)
237                 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
238                         TUSB_EP_CONFIG_XFR_SIZE(len));
239         else
240                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
241 
242         if (likely((0x01 & (unsigned long) buf) == 0)) {
243 
244                 /* Best case is 32bit-aligned destination address */
245                 if ((0x02 & (unsigned long) buf) == 0) {
246                         if (len >= 4) {
247                                 ioread32_rep(fifo, buf, len >> 2);
248                                 buf += (len & ~0x03);
249                                 len &= 0x03;
250                         }
251                 } else {
252                         if (len >= 2) {
253                                 u32 val;
254                                 int i;
255 
256                                 /* Cannot use readsw, fifo is 32-bit */
257                                 for (i = 0; i < (len >> 2); i++) {
258                                         val = musb_readl(fifo, 0);
259                                         *(u16 *)buf = (u16)(val & 0xffff);
260                                         buf += 2;
261                                         *(u16 *)buf = (u16)(val >> 16);
262                                         buf += 2;
263                                 }
264                                 len &= 0x03;
265                         }
266                 }
267         }
268 
269         if (len > 0)
270                 tusb_fifo_read_unaligned(fifo, buf, len);
271 }
272 
273 static struct musb *the_musb;
274 
275 /* This is used by gadget drivers, and OTG transceiver logic, allowing
276  * at most mA current to be drawn from VBUS during a Default-B session
277  * (that is, while VBUS exceeds 4.4V).  In Default-A (including pure host
278  * mode), or low power Default-B sessions, something else supplies power.
279  * Caller must take care of locking.
280  */
281 static int tusb_draw_power(struct usb_phy *x, unsigned mA)
282 {
283         struct musb     *musb = the_musb;
284         void __iomem    *tbase = musb->ctrl_base;
285         u32             reg;
286 
287         /* tps65030 seems to consume max 100mA, with maybe 60mA available
288          * (measured on one board) for things other than tps and tusb.
289          *
290          * Boards sharing the CPU clock with CLKIN will need to prevent
291          * certain idle sleep states while the USB link is active.
292          *
293          * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
294          * The actual current usage would be very board-specific.  For now,
295          * it's simpler to just use an aggregate (also board-specific).
296          */
297         if (x->otg->default_a || mA < (musb->min_power << 1))
298                 mA = 0;
299 
300         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
301         if (mA) {
302                 musb->is_bus_powered = 1;
303                 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
304         } else {
305                 musb->is_bus_powered = 0;
306                 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
307         }
308         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
309 
310         dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
311         return 0;
312 }
313 
314 /* workaround for issue 13:  change clock during chip idle
315  * (to be fixed in rev3 silicon) ... symptoms include disconnect
316  * or looping suspend/resume cycles
317  */
318 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
319 {
320         void __iomem    *tbase = musb->ctrl_base;
321         u32             reg;
322 
323         reg = musb_readl(tbase, TUSB_PRCM_CONF);
324         reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
325 
326         /* 0 = refclk (clkin, XI)
327          * 1 = PHY 60 MHz (internal PLL)
328          * 2 = not supported
329          * 3 = what?
330          */
331         if (mode > 0)
332                 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
333 
334         musb_writel(tbase, TUSB_PRCM_CONF, reg);
335 
336         /* FIXME tusb6010_platform_retime(mode == 0); */
337 }
338 
339 /*
340  * Idle TUSB6010 until next wake-up event; NOR access always wakes.
341  * Other code ensures that we idle unless we're connected _and_ the
342  * USB link is not suspended ... and tells us the relevant wakeup
343  * events.  SW_EN for voltage is handled separately.
344  */
345 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
346 {
347         void __iomem    *tbase = musb->ctrl_base;
348         u32             reg;
349 
350         if ((wakeup_enables & TUSB_PRCM_WBUS)
351                         && (musb->tusb_revision == TUSB_REV_30))
352                 tusb_wbus_quirk(musb, 1);
353 
354         tusb_set_clock_source(musb, 0);
355 
356         wakeup_enables |= TUSB_PRCM_WNORCS;
357         musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
358 
359         /* REVISIT writeup of WID implies that if WID set and ID is grounded,
360          * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
361          * Presumably that's mostly to save power, hence WID is immaterial ...
362          */
363 
364         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
365         /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
366         if (is_host_active(musb)) {
367                 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
368                 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
369         } else {
370                 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
371                 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
372         }
373         reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
374         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
375 
376         dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
377 }
378 
379 /*
380  * Updates cable VBUS status. Caller must take care of locking.
381  */
382 static int tusb_musb_vbus_status(struct musb *musb)
383 {
384         void __iomem    *tbase = musb->ctrl_base;
385         u32             otg_stat, prcm_mngmt;
386         int             ret = 0;
387 
388         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
389         prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
390 
391         /* Temporarily enable VBUS detection if it was disabled for
392          * suspend mode. Unless it's enabled otg_stat and devctl will
393          * not show correct VBUS state.
394          */
395         if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
396                 u32 tmp = prcm_mngmt;
397                 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
398                 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
399                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
400                 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
401         }
402 
403         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
404                 ret = 1;
405 
406         return ret;
407 }
408 
409 static struct timer_list musb_idle_timer;
410 
411 static void musb_do_idle(unsigned long _musb)
412 {
413         struct musb     *musb = (void *)_musb;
414         unsigned long   flags;
415 
416         spin_lock_irqsave(&musb->lock, flags);
417 
418         switch (musb->xceiv->state) {
419         case OTG_STATE_A_WAIT_BCON:
420                 if ((musb->a_wait_bcon != 0)
421                         && (musb->idle_timeout == 0
422                                 || time_after(jiffies, musb->idle_timeout))) {
423                         dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
424                                         usb_otg_state_string(musb->xceiv->state));
425                 }
426                 /* FALLTHROUGH */
427         case OTG_STATE_A_IDLE:
428                 tusb_musb_set_vbus(musb, 0);
429         default:
430                 break;
431         }
432 
433         if (!musb->is_active) {
434                 u32     wakeups;
435 
436                 /* wait until khubd handles port change status */
437                 if (is_host_active(musb) && (musb->port1_status >> 16))
438                         goto done;
439 
440                 if (!musb->gadget_driver) {
441                         wakeups = 0;
442                 } else {
443                         wakeups = TUSB_PRCM_WHOSTDISCON
444                                 | TUSB_PRCM_WBUS
445                                         | TUSB_PRCM_WVBUS;
446                         wakeups |= TUSB_PRCM_WID;
447                 }
448                 tusb_allow_idle(musb, wakeups);
449         }
450 done:
451         spin_unlock_irqrestore(&musb->lock, flags);
452 }
453 
454 /*
455  * Maybe put TUSB6010 into idle mode mode depending on USB link status,
456  * like "disconnected" or "suspended".  We'll be woken out of it by
457  * connect, resume, or disconnect.
458  *
459  * Needs to be called as the last function everywhere where there is
460  * register access to TUSB6010 because of NOR flash wake-up.
461  * Caller should own controller spinlock.
462  *
463  * Delay because peripheral enables D+ pullup 3msec after SE0, and
464  * we don't want to treat that full speed J as a wakeup event.
465  * ... peripherals must draw only suspend current after 10 msec.
466  */
467 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
468 {
469         unsigned long           default_timeout = jiffies + msecs_to_jiffies(3);
470         static unsigned long    last_timer;
471 
472         if (timeout == 0)
473                 timeout = default_timeout;
474 
475         /* Never idle if active, or when VBUS timeout is not set as host */
476         if (musb->is_active || ((musb->a_wait_bcon == 0)
477                         && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
478                 dev_dbg(musb->controller, "%s active, deleting timer\n",
479                         usb_otg_state_string(musb->xceiv->state));
480                 del_timer(&musb_idle_timer);
481                 last_timer = jiffies;
482                 return;
483         }
484 
485         if (time_after(last_timer, timeout)) {
486                 if (!timer_pending(&musb_idle_timer))
487                         last_timer = timeout;
488                 else {
489                         dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
490                         return;
491                 }
492         }
493         last_timer = timeout;
494 
495         dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
496                 usb_otg_state_string(musb->xceiv->state),
497                 (unsigned long)jiffies_to_msecs(timeout - jiffies));
498         mod_timer(&musb_idle_timer, timeout);
499 }
500 
501 /* ticks of 60 MHz clock */
502 #define DEVCLOCK                60000000
503 #define OTG_TIMER_MS(msecs)     ((msecs) \
504                 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
505                                 | TUSB_DEV_OTG_TIMER_ENABLE) \
506                 : 0)
507 
508 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
509 {
510         void __iomem    *tbase = musb->ctrl_base;
511         u32             conf, prcm, timer;
512         u8              devctl;
513         struct usb_otg  *otg = musb->xceiv->otg;
514 
515         /* HDRC controls CPEN, but beware current surges during device
516          * connect.  They can trigger transient overcurrent conditions
517          * that must be ignored.
518          */
519 
520         prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
521         conf = musb_readl(tbase, TUSB_DEV_CONF);
522         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
523 
524         if (is_on) {
525                 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
526                 otg->default_a = 1;
527                 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
528                 devctl |= MUSB_DEVCTL_SESSION;
529 
530                 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
531                 MUSB_HST_MODE(musb);
532         } else {
533                 u32     otg_stat;
534 
535                 timer = 0;
536 
537                 /* If ID pin is grounded, we want to be a_idle */
538                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
539                 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
540                         switch (musb->xceiv->state) {
541                         case OTG_STATE_A_WAIT_VRISE:
542                         case OTG_STATE_A_WAIT_BCON:
543                                 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
544                                 break;
545                         case OTG_STATE_A_WAIT_VFALL:
546                                 musb->xceiv->state = OTG_STATE_A_IDLE;
547                                 break;
548                         default:
549                                 musb->xceiv->state = OTG_STATE_A_IDLE;
550                         }
551                         musb->is_active = 0;
552                         otg->default_a = 1;
553                         MUSB_HST_MODE(musb);
554                 } else {
555                         musb->is_active = 0;
556                         otg->default_a = 0;
557                         musb->xceiv->state = OTG_STATE_B_IDLE;
558                         MUSB_DEV_MODE(musb);
559                 }
560 
561                 devctl &= ~MUSB_DEVCTL_SESSION;
562                 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
563         }
564         prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
565 
566         musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
567         musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
568         musb_writel(tbase, TUSB_DEV_CONF, conf);
569         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
570 
571         dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
572                 usb_otg_state_string(musb->xceiv->state),
573                 musb_readb(musb->mregs, MUSB_DEVCTL),
574                 musb_readl(tbase, TUSB_DEV_OTG_STAT),
575                 conf, prcm);
576 }
577 
578 /*
579  * Sets the mode to OTG, peripheral or host by changing the ID detection.
580  * Caller must take care of locking.
581  *
582  * Note that if a mini-A cable is plugged in the ID line will stay down as
583  * the weak ID pull-up is not able to pull the ID up.
584  */
585 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
586 {
587         void __iomem    *tbase = musb->ctrl_base;
588         u32             otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
589 
590         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
591         phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
592         phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
593         dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
594 
595         switch (musb_mode) {
596 
597         case MUSB_HOST:         /* Disable PHY ID detect, ground ID */
598                 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
599                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
600                 dev_conf |= TUSB_DEV_CONF_ID_SEL;
601                 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
602                 break;
603         case MUSB_PERIPHERAL:   /* Disable PHY ID detect, keep ID pull-up on */
604                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
605                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
606                 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
607                 break;
608         case MUSB_OTG:          /* Use PHY ID detection */
609                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
610                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
611                 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
612                 break;
613 
614         default:
615                 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
616                 return -EINVAL;
617         }
618 
619         musb_writel(tbase, TUSB_PHY_OTG_CTRL,
620                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
621         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
622                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
623         musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
624 
625         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
626         if ((musb_mode == MUSB_PERIPHERAL) &&
627                 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
628                         INFO("Cannot be peripheral with mini-A cable "
629                         "otg_stat: %08x\n", otg_stat);
630 
631         return 0;
632 }
633 
634 static inline unsigned long
635 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
636 {
637         u32             otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
638         unsigned long   idle_timeout = 0;
639         struct usb_otg  *otg = musb->xceiv->otg;
640 
641         /* ID pin */
642         if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
643                 int     default_a;
644 
645                 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
646                 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
647                 otg->default_a = default_a;
648                 tusb_musb_set_vbus(musb, default_a);
649 
650                 /* Don't allow idling immediately */
651                 if (default_a)
652                         idle_timeout = jiffies + (HZ * 3);
653         }
654 
655         /* VBUS state change */
656         if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
657 
658                 /* B-dev state machine:  no vbus ~= disconnect */
659                 if (!otg->default_a) {
660                         /* ? musb_root_disconnect(musb); */
661                         musb->port1_status &=
662                                 ~(USB_PORT_STAT_CONNECTION
663                                 | USB_PORT_STAT_ENABLE
664                                 | USB_PORT_STAT_LOW_SPEED
665                                 | USB_PORT_STAT_HIGH_SPEED
666                                 | USB_PORT_STAT_TEST
667                                 );
668 
669                         if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
670                                 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
671                                 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
672                                         /* INTR_DISCONNECT can hide... */
673                                         musb->xceiv->state = OTG_STATE_B_IDLE;
674                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
675                                 }
676                                 musb->is_active = 0;
677                         }
678                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
679                                 usb_otg_state_string(musb->xceiv->state), otg_stat);
680                         idle_timeout = jiffies + (1 * HZ);
681                         schedule_work(&musb->irq_work);
682 
683                 } else /* A-dev state machine */ {
684                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
685                                 usb_otg_state_string(musb->xceiv->state), otg_stat);
686 
687                         switch (musb->xceiv->state) {
688                         case OTG_STATE_A_IDLE:
689                                 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
690                                 musb_platform_set_vbus(musb, 1);
691 
692                                 /* CONNECT can wake if a_wait_bcon is set */
693                                 if (musb->a_wait_bcon != 0)
694                                         musb->is_active = 0;
695                                 else
696                                         musb->is_active = 1;
697 
698                                 /*
699                                  * OPT FS A TD.4.6 needs few seconds for
700                                  * A_WAIT_VRISE
701                                  */
702                                 idle_timeout = jiffies + (2 * HZ);
703 
704                                 break;
705                         case OTG_STATE_A_WAIT_VRISE:
706                                 /* ignore; A-session-valid < VBUS_VALID/2,
707                                  * we monitor this with the timer
708                                  */
709                                 break;
710                         case OTG_STATE_A_WAIT_VFALL:
711                                 /* REVISIT this irq triggers during short
712                                  * spikes caused by enumeration ...
713                                  */
714                                 if (musb->vbuserr_retry) {
715                                         musb->vbuserr_retry--;
716                                         tusb_musb_set_vbus(musb, 1);
717                                 } else {
718                                         musb->vbuserr_retry
719                                                 = VBUSERR_RETRY_COUNT;
720                                         tusb_musb_set_vbus(musb, 0);
721                                 }
722                                 break;
723                         default:
724                                 break;
725                         }
726                 }
727         }
728 
729         /* OTG timer expiration */
730         if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
731                 u8      devctl;
732 
733                 dev_dbg(musb->controller, "%s timer, %03x\n",
734                         usb_otg_state_string(musb->xceiv->state), otg_stat);
735 
736                 switch (musb->xceiv->state) {
737                 case OTG_STATE_A_WAIT_VRISE:
738                         /* VBUS has probably been valid for a while now,
739                          * but may well have bounced out of range a bit
740                          */
741                         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
742                         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
743                                 if ((devctl & MUSB_DEVCTL_VBUS)
744                                                 != MUSB_DEVCTL_VBUS) {
745                                         dev_dbg(musb->controller, "devctl %02x\n", devctl);
746                                         break;
747                                 }
748                                 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
749                                 musb->is_active = 0;
750                                 idle_timeout = jiffies
751                                         + msecs_to_jiffies(musb->a_wait_bcon);
752                         } else {
753                                 /* REVISIT report overcurrent to hub? */
754                                 ERR("vbus too slow, devctl %02x\n", devctl);
755                                 tusb_musb_set_vbus(musb, 0);
756                         }
757                         break;
758                 case OTG_STATE_A_WAIT_BCON:
759                         if (musb->a_wait_bcon != 0)
760                                 idle_timeout = jiffies
761                                         + msecs_to_jiffies(musb->a_wait_bcon);
762                         break;
763                 case OTG_STATE_A_SUSPEND:
764                         break;
765                 case OTG_STATE_B_WAIT_ACON:
766                         break;
767                 default:
768                         break;
769                 }
770         }
771         schedule_work(&musb->irq_work);
772 
773         return idle_timeout;
774 }
775 
776 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
777 {
778         struct musb     *musb = __hci;
779         void __iomem    *tbase = musb->ctrl_base;
780         unsigned long   flags, idle_timeout = 0;
781         u32             int_mask, int_src;
782 
783         spin_lock_irqsave(&musb->lock, flags);
784 
785         /* Mask all interrupts to allow using both edge and level GPIO irq */
786         int_mask = musb_readl(tbase, TUSB_INT_MASK);
787         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
788 
789         int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
790         dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
791 
792         musb->int_usb = (u8) int_src;
793 
794         /* Acknowledge wake-up source interrupts */
795         if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
796                 u32     reg;
797                 u32     i;
798 
799                 if (musb->tusb_revision == TUSB_REV_30)
800                         tusb_wbus_quirk(musb, 0);
801 
802                 /* there are issues re-locking the PLL on wakeup ... */
803 
804                 /* work around issue 8 */
805                 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
806                         musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
807                         musb_writel(tbase, TUSB_SCRATCH_PAD, i);
808                         reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
809                         if (reg == i)
810                                 break;
811                         dev_dbg(musb->controller, "TUSB NOR not ready\n");
812                 }
813 
814                 /* work around issue 13 (2nd half) */
815                 tusb_set_clock_source(musb, 1);
816 
817                 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
818                 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
819                 if (reg & ~TUSB_PRCM_WNORCS) {
820                         musb->is_active = 1;
821                         schedule_work(&musb->irq_work);
822                 }
823                 dev_dbg(musb->controller, "wake %sactive %02x\n",
824                                 musb->is_active ? "" : "in", reg);
825 
826                 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
827         }
828 
829         if (int_src & TUSB_INT_SRC_USB_IP_CONN)
830                 del_timer(&musb_idle_timer);
831 
832         /* OTG state change reports (annoyingly) not issued by Mentor core */
833         if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
834                                 | TUSB_INT_SRC_OTG_TIMEOUT
835                                 | TUSB_INT_SRC_ID_STATUS_CHNG))
836                 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
837 
838         /* TX dma callback must be handled here, RX dma callback is
839          * handled in tusb_omap_dma_cb.
840          */
841         if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
842                 u32     dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
843                 u32     real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
844 
845                 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
846                 real_dma_src = ~real_dma_src & dma_src;
847                 if (tusb_dma_omap() && real_dma_src) {
848                         int     tx_source = (real_dma_src & 0xffff);
849                         int     i;
850 
851                         for (i = 1; i <= 15; i++) {
852                                 if (tx_source & (1 << i)) {
853                                         dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
854                                         musb_dma_completion(musb, i, 1);
855                                 }
856                         }
857                 }
858                 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
859         }
860 
861         /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
862         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
863                 u32     musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
864 
865                 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
866                 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
867                 musb->int_tx = (musb_src & 0xffff);
868         } else {
869                 musb->int_rx = 0;
870                 musb->int_tx = 0;
871         }
872 
873         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
874                 musb_interrupt(musb);
875 
876         /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
877         musb_writel(tbase, TUSB_INT_SRC_CLEAR,
878                 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
879 
880         tusb_musb_try_idle(musb, idle_timeout);
881 
882         musb_writel(tbase, TUSB_INT_MASK, int_mask);
883         spin_unlock_irqrestore(&musb->lock, flags);
884 
885         return IRQ_HANDLED;
886 }
887 
888 static int dma_off;
889 
890 /*
891  * Enables TUSB6010. Caller must take care of locking.
892  * REVISIT:
893  * - Check what is unnecessary in MGC_HdrcStart()
894  */
895 static void tusb_musb_enable(struct musb *musb)
896 {
897         void __iomem    *tbase = musb->ctrl_base;
898 
899         /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
900          * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
901         musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
902 
903         /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
904         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
905         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
906         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
907 
908         /* Clear all subsystem interrups */
909         musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
910         musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
911         musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
912 
913         /* Acknowledge pending interrupt(s) */
914         musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
915 
916         /* Only 0 clock cycles for minimum interrupt de-assertion time and
917          * interrupt polarity active low seems to work reliably here */
918         musb_writel(tbase, TUSB_INT_CTRL_CONF,
919                         TUSB_INT_CTRL_CONF_INT_RELCYC(0));
920 
921         irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
922 
923         /* maybe force into the Default-A OTG state machine */
924         if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
925                         & TUSB_DEV_OTG_STAT_ID_STATUS))
926                 musb_writel(tbase, TUSB_INT_SRC_SET,
927                                 TUSB_INT_SRC_ID_STATUS_CHNG);
928 
929         if (is_dma_capable() && dma_off)
930                 printk(KERN_WARNING "%s %s: dma not reactivated\n",
931                                 __FILE__, __func__);
932         else
933                 dma_off = 1;
934 }
935 
936 /*
937  * Disables TUSB6010. Caller must take care of locking.
938  */
939 static void tusb_musb_disable(struct musb *musb)
940 {
941         void __iomem    *tbase = musb->ctrl_base;
942 
943         /* FIXME stop DMA, IRQs, timers, ... */
944 
945         /* disable all IRQs */
946         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
947         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
948         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
949         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
950 
951         del_timer(&musb_idle_timer);
952 
953         if (is_dma_capable() && !dma_off) {
954                 printk(KERN_WARNING "%s %s: dma still active\n",
955                                 __FILE__, __func__);
956                 dma_off = 1;
957         }
958 }
959 
960 /*
961  * Sets up TUSB6010 CPU interface specific signals and registers
962  * Note: Settings optimized for OMAP24xx
963  */
964 static void tusb_setup_cpu_interface(struct musb *musb)
965 {
966         void __iomem    *tbase = musb->ctrl_base;
967 
968         /*
969          * Disable GPIO[5:0] pullups (used as output DMA requests)
970          * Don't disable GPIO[7:6] as they are needed for wake-up.
971          */
972         musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
973 
974         /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
975         musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
976 
977         /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
978         musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
979 
980         /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
981          * de-assertion time 2 system clocks p 62 */
982         musb_writel(tbase, TUSB_DMA_REQ_CONF,
983                 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
984                 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
985                 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
986 
987         /* Set 0 wait count for synchronous burst access */
988         musb_writel(tbase, TUSB_WAIT_COUNT, 1);
989 }
990 
991 static int tusb_musb_start(struct musb *musb)
992 {
993         void __iomem    *tbase = musb->ctrl_base;
994         int             ret = 0;
995         unsigned long   flags;
996         u32             reg;
997 
998         if (musb->board_set_power)
999                 ret = musb->board_set_power(1);
1000         if (ret != 0) {
1001                 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1002                 return ret;
1003         }
1004 
1005         spin_lock_irqsave(&musb->lock, flags);
1006 
1007         if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1008                 TUSB_PROD_TEST_RESET_VAL) {
1009                 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1010                 goto err;
1011         }
1012 
1013         musb->tusb_revision = tusb_get_revision(musb);
1014         tusb_print_revision(musb);
1015         if (musb->tusb_revision < 2) {
1016                 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1017                                 musb->tusb_revision);
1018                 goto err;
1019         }
1020 
1021         /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1022          * NOR FLASH interface is used */
1023         musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1024 
1025         /* Select PHY free running 60MHz as a system clock */
1026         tusb_set_clock_source(musb, 1);
1027 
1028         /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1029          * power saving, enable VBus detect and session end comparators,
1030          * enable IDpullup, enable VBus charging */
1031         musb_writel(tbase, TUSB_PRCM_MNGMT,
1032                 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1033                 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1034                 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1035                 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1036                 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1037         tusb_setup_cpu_interface(musb);
1038 
1039         /* simplify:  always sense/pullup ID pins, as if in OTG mode */
1040         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1041         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1042         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1043 
1044         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1045         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1046         musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1047 
1048         spin_unlock_irqrestore(&musb->lock, flags);
1049 
1050         return 0;
1051 
1052 err:
1053         spin_unlock_irqrestore(&musb->lock, flags);
1054 
1055         if (musb->board_set_power)
1056                 musb->board_set_power(0);
1057 
1058         return -ENODEV;
1059 }
1060 
1061 static int tusb_musb_init(struct musb *musb)
1062 {
1063         struct platform_device  *pdev;
1064         struct resource         *mem;
1065         void __iomem            *sync = NULL;
1066         int                     ret;
1067 
1068         musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
1069         if (IS_ERR_OR_NULL(musb->xceiv))
1070                 return -EPROBE_DEFER;
1071 
1072         pdev = to_platform_device(musb->controller);
1073 
1074         /* dma address for async dma */
1075         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1076         musb->async = mem->start;
1077 
1078         /* dma address for sync dma */
1079         mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1080         if (!mem) {
1081                 pr_debug("no sync dma resource?\n");
1082                 ret = -ENODEV;
1083                 goto done;
1084         }
1085         musb->sync = mem->start;
1086 
1087         sync = ioremap(mem->start, resource_size(mem));
1088         if (!sync) {
1089                 pr_debug("ioremap for sync failed\n");
1090                 ret = -ENOMEM;
1091                 goto done;
1092         }
1093         musb->sync_va = sync;
1094 
1095         /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1096          * FIFOs at 0x600, TUSB at 0x800
1097          */
1098         musb->mregs += TUSB_BASE_OFFSET;
1099 
1100         ret = tusb_musb_start(musb);
1101         if (ret) {
1102                 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1103                                 ret);
1104                 goto done;
1105         }
1106         musb->isr = tusb_musb_interrupt;
1107 
1108         musb->xceiv->set_power = tusb_draw_power;
1109         the_musb = musb;
1110 
1111         setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1112 
1113 done:
1114         if (ret < 0) {
1115                 if (sync)
1116                         iounmap(sync);
1117 
1118                 usb_put_phy(musb->xceiv);
1119         }
1120         return ret;
1121 }
1122 
1123 static int tusb_musb_exit(struct musb *musb)
1124 {
1125         del_timer_sync(&musb_idle_timer);
1126         the_musb = NULL;
1127 
1128         if (musb->board_set_power)
1129                 musb->board_set_power(0);
1130 
1131         iounmap(musb->sync_va);
1132 
1133         usb_put_phy(musb->xceiv);
1134         return 0;
1135 }
1136 
1137 static const struct musb_platform_ops tusb_ops = {
1138         .init           = tusb_musb_init,
1139         .exit           = tusb_musb_exit,
1140 
1141         .enable         = tusb_musb_enable,
1142         .disable        = tusb_musb_disable,
1143 
1144         .set_mode       = tusb_musb_set_mode,
1145         .try_idle       = tusb_musb_try_idle,
1146 
1147         .vbus_status    = tusb_musb_vbus_status,
1148         .set_vbus       = tusb_musb_set_vbus,
1149 };
1150 
1151 static const struct platform_device_info tusb_dev_info = {
1152         .name           = "musb-hdrc",
1153         .id             = PLATFORM_DEVID_AUTO,
1154         .dma_mask       = DMA_BIT_MASK(32),
1155 };
1156 
1157 static int tusb_probe(struct platform_device *pdev)
1158 {
1159         struct resource musb_resources[3];
1160         struct musb_hdrc_platform_data  *pdata = dev_get_platdata(&pdev->dev);
1161         struct platform_device          *musb;
1162         struct tusb6010_glue            *glue;
1163         struct platform_device_info     pinfo;
1164         int                             ret;
1165 
1166         glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
1167         if (!glue) {
1168                 dev_err(&pdev->dev, "failed to allocate glue context\n");
1169                 return -ENOMEM;
1170         }
1171 
1172         glue->dev                       = &pdev->dev;
1173 
1174         pdata->platform_ops             = &tusb_ops;
1175 
1176         usb_phy_generic_register();
1177         platform_set_drvdata(pdev, glue);
1178 
1179         memset(musb_resources, 0x00, sizeof(*musb_resources) *
1180                         ARRAY_SIZE(musb_resources));
1181 
1182         musb_resources[0].name = pdev->resource[0].name;
1183         musb_resources[0].start = pdev->resource[0].start;
1184         musb_resources[0].end = pdev->resource[0].end;
1185         musb_resources[0].flags = pdev->resource[0].flags;
1186 
1187         musb_resources[1].name = pdev->resource[1].name;
1188         musb_resources[1].start = pdev->resource[1].start;
1189         musb_resources[1].end = pdev->resource[1].end;
1190         musb_resources[1].flags = pdev->resource[1].flags;
1191 
1192         musb_resources[2].name = pdev->resource[2].name;
1193         musb_resources[2].start = pdev->resource[2].start;
1194         musb_resources[2].end = pdev->resource[2].end;
1195         musb_resources[2].flags = pdev->resource[2].flags;
1196 
1197         pinfo = tusb_dev_info;
1198         pinfo.parent = &pdev->dev;
1199         pinfo.res = musb_resources;
1200         pinfo.num_res = ARRAY_SIZE(musb_resources);
1201         pinfo.data = pdata;
1202         pinfo.size_data = sizeof(*pdata);
1203 
1204         glue->musb = musb = platform_device_register_full(&pinfo);
1205         if (IS_ERR(musb)) {
1206                 ret = PTR_ERR(musb);
1207                 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
1208                 return ret;
1209         }
1210 
1211         return 0;
1212 }
1213 
1214 static int tusb_remove(struct platform_device *pdev)
1215 {
1216         struct tusb6010_glue            *glue = platform_get_drvdata(pdev);
1217 
1218         platform_device_unregister(glue->musb);
1219         usb_phy_generic_unregister(glue->phy);
1220 
1221         return 0;
1222 }
1223 
1224 static struct platform_driver tusb_driver = {
1225         .probe          = tusb_probe,
1226         .remove         = tusb_remove,
1227         .driver         = {
1228                 .name   = "musb-tusb",
1229         },
1230 };
1231 
1232 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1233 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1234 MODULE_LICENSE("GPL v2");
1235 module_platform_driver(tusb_driver);
1236 

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