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Linux/drivers/usb/musb/musb_core.c

  1 /*
  2  * MUSB OTG driver core code
  3  *
  4  * Copyright 2005 Mentor Graphics Corporation
  5  * Copyright (C) 2005-2006 by Texas Instruments
  6  * Copyright (C) 2006-2007 Nokia Corporation
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License
 10  * version 2 as published by the Free Software Foundation.
 11  *
 12  * This program is distributed in the hope that it will be useful, but
 13  * WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 15  * General Public License for more details.
 16  *
 17  * You should have received a copy of the GNU General Public License
 18  * along with this program; if not, write to the Free Software
 19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 20  * 02110-1301 USA
 21  *
 22  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 25  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 32  *
 33  */
 34 
 35 /*
 36  * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
 37  *
 38  * This consists of a Host Controller Driver (HCD) and a peripheral
 39  * controller driver implementing the "Gadget" API; OTG support is
 40  * in the works.  These are normal Linux-USB controller drivers which
 41  * use IRQs and have no dedicated thread.
 42  *
 43  * This version of the driver has only been used with products from
 44  * Texas Instruments.  Those products integrate the Inventra logic
 45  * with other DMA, IRQ, and bus modules, as well as other logic that
 46  * needs to be reflected in this driver.
 47  *
 48  *
 49  * NOTE:  the original Mentor code here was pretty much a collection
 50  * of mechanisms that don't seem to have been fully integrated/working
 51  * for *any* Linux kernel version.  This version aims at Linux 2.6.now,
 52  * Key open issues include:
 53  *
 54  *  - Lack of host-side transaction scheduling, for all transfer types.
 55  *    The hardware doesn't do it; instead, software must.
 56  *
 57  *    This is not an issue for OTG devices that don't support external
 58  *    hubs, but for more "normal" USB hosts it's a user issue that the
 59  *    "multipoint" support doesn't scale in the expected ways.  That
 60  *    includes DaVinci EVM in a common non-OTG mode.
 61  *
 62  *      * Control and bulk use dedicated endpoints, and there's as
 63  *        yet no mechanism to either (a) reclaim the hardware when
 64  *        peripherals are NAKing, which gets complicated with bulk
 65  *        endpoints, or (b) use more than a single bulk endpoint in
 66  *        each direction.
 67  *
 68  *        RESULT:  one device may be perceived as blocking another one.
 69  *
 70  *      * Interrupt and isochronous will dynamically allocate endpoint
 71  *        hardware, but (a) there's no record keeping for bandwidth;
 72  *        (b) in the common case that few endpoints are available, there
 73  *        is no mechanism to reuse endpoints to talk to multiple devices.
 74  *
 75  *        RESULT:  At one extreme, bandwidth can be overcommitted in
 76  *        some hardware configurations, no faults will be reported.
 77  *        At the other extreme, the bandwidth capabilities which do
 78  *        exist tend to be severely undercommitted.  You can't yet hook
 79  *        up both a keyboard and a mouse to an external USB hub.
 80  */
 81 
 82 /*
 83  * This gets many kinds of configuration information:
 84  *      - Kconfig for everything user-configurable
 85  *      - platform_device for addressing, irq, and platform_data
 86  *      - platform_data is mostly for board-specific information
 87  *        (plus recentrly, SOC or family details)
 88  *
 89  * Most of the conditional compilation will (someday) vanish.
 90  */
 91 
 92 #include <linux/module.h>
 93 #include <linux/kernel.h>
 94 #include <linux/sched.h>
 95 #include <linux/slab.h>
 96 #include <linux/list.h>
 97 #include <linux/kobject.h>
 98 #include <linux/prefetch.h>
 99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102 
103 #include "musb_core.h"
104 
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106 
107 
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110 
111 #define MUSB_VERSION "6.0"
112 
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114 
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117 
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122 
123 
124 /*-------------------------------------------------------------------------*/
125 
126 static inline struct musb *dev_to_musb(struct device *dev)
127 {
128         return dev_get_drvdata(dev);
129 }
130 
131 /*-------------------------------------------------------------------------*/
132 
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
135 {
136         void __iomem *addr = phy->io_priv;
137         int     i = 0;
138         u8      r;
139         u8      power;
140         int     ret;
141 
142         pm_runtime_get_sync(phy->io_dev);
143 
144         /* Make sure the transceiver is not in low power mode */
145         power = musb_readb(addr, MUSB_POWER);
146         power &= ~MUSB_POWER_SUSPENDM;
147         musb_writeb(addr, MUSB_POWER, power);
148 
149         /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150          * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151          */
152 
153         musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154         musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155                         MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156 
157         while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158                                 & MUSB_ULPI_REG_CMPLT)) {
159                 i++;
160                 if (i == 10000) {
161                         ret = -ETIMEDOUT;
162                         goto out;
163                 }
164 
165         }
166         r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167         r &= ~MUSB_ULPI_REG_CMPLT;
168         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169 
170         ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171 
172 out:
173         pm_runtime_put(phy->io_dev);
174 
175         return ret;
176 }
177 
178 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
179 {
180         void __iomem *addr = phy->io_priv;
181         int     i = 0;
182         u8      r = 0;
183         u8      power;
184         int     ret = 0;
185 
186         pm_runtime_get_sync(phy->io_dev);
187 
188         /* Make sure the transceiver is not in low power mode */
189         power = musb_readb(addr, MUSB_POWER);
190         power &= ~MUSB_POWER_SUSPENDM;
191         musb_writeb(addr, MUSB_POWER, power);
192 
193         musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194         musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196 
197         while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198                                 & MUSB_ULPI_REG_CMPLT)) {
199                 i++;
200                 if (i == 10000) {
201                         ret = -ETIMEDOUT;
202                         goto out;
203                 }
204         }
205 
206         r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207         r &= ~MUSB_ULPI_REG_CMPLT;
208         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209 
210 out:
211         pm_runtime_put(phy->io_dev);
212 
213         return ret;
214 }
215 #else
216 #define musb_ulpi_read          NULL
217 #define musb_ulpi_write         NULL
218 #endif
219 
220 static struct usb_phy_io_ops musb_ulpi_access = {
221         .read = musb_ulpi_read,
222         .write = musb_ulpi_write,
223 };
224 
225 /*-------------------------------------------------------------------------*/
226 
227 static u32 musb_default_fifo_offset(u8 epnum)
228 {
229         return 0x20 + (epnum * 4);
230 }
231 
232 /* "flat" mapping: each endpoint has its own i/o address */
233 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
234 {
235 }
236 
237 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
238 {
239         return 0x100 + (0x10 * epnum) + offset;
240 }
241 
242 /* "indexed" mapping: INDEX register controls register bank select */
243 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
244 {
245         musb_writeb(mbase, MUSB_INDEX, epnum);
246 }
247 
248 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
249 {
250         return 0x10 + offset;
251 }
252 
253 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
254 {
255         return __raw_readb(addr + offset);
256 }
257 
258 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
259 {
260         __raw_writeb(data, addr + offset);
261 }
262 
263 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
264 {
265         return __raw_readw(addr + offset);
266 }
267 
268 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
269 {
270         __raw_writew(data, addr + offset);
271 }
272 
273 static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
274 {
275         return __raw_readl(addr + offset);
276 }
277 
278 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
279 {
280         __raw_writel(data, addr + offset);
281 }
282 
283 /*
284  * Load an endpoint's FIFO
285  */
286 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
287                                     const u8 *src)
288 {
289         struct musb *musb = hw_ep->musb;
290         void __iomem *fifo = hw_ep->fifo;
291 
292         if (unlikely(len == 0))
293                 return;
294 
295         prefetch((u8 *)src);
296 
297         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
298                         'T', hw_ep->epnum, fifo, len, src);
299 
300         /* we can't assume unaligned reads work */
301         if (likely((0x01 & (unsigned long) src) == 0)) {
302                 u16     index = 0;
303 
304                 /* best case is 32bit-aligned source address */
305                 if ((0x02 & (unsigned long) src) == 0) {
306                         if (len >= 4) {
307                                 iowrite32_rep(fifo, src + index, len >> 2);
308                                 index += len & ~0x03;
309                         }
310                         if (len & 0x02) {
311                                 musb_writew(fifo, 0, *(u16 *)&src[index]);
312                                 index += 2;
313                         }
314                 } else {
315                         if (len >= 2) {
316                                 iowrite16_rep(fifo, src + index, len >> 1);
317                                 index += len & ~0x01;
318                         }
319                 }
320                 if (len & 0x01)
321                         musb_writeb(fifo, 0, src[index]);
322         } else  {
323                 /* byte aligned */
324                 iowrite8_rep(fifo, src, len);
325         }
326 }
327 
328 /*
329  * Unload an endpoint's FIFO
330  */
331 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
332 {
333         struct musb *musb = hw_ep->musb;
334         void __iomem *fifo = hw_ep->fifo;
335 
336         if (unlikely(len == 0))
337                 return;
338 
339         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
340                         'R', hw_ep->epnum, fifo, len, dst);
341 
342         /* we can't assume unaligned writes work */
343         if (likely((0x01 & (unsigned long) dst) == 0)) {
344                 u16     index = 0;
345 
346                 /* best case is 32bit-aligned destination address */
347                 if ((0x02 & (unsigned long) dst) == 0) {
348                         if (len >= 4) {
349                                 ioread32_rep(fifo, dst, len >> 2);
350                                 index = len & ~0x03;
351                         }
352                         if (len & 0x02) {
353                                 *(u16 *)&dst[index] = musb_readw(fifo, 0);
354                                 index += 2;
355                         }
356                 } else {
357                         if (len >= 2) {
358                                 ioread16_rep(fifo, dst, len >> 1);
359                                 index = len & ~0x01;
360                         }
361                 }
362                 if (len & 0x01)
363                         dst[index] = musb_readb(fifo, 0);
364         } else  {
365                 /* byte aligned */
366                 ioread8_rep(fifo, dst, len);
367         }
368 }
369 
370 /*
371  * Old style IO functions
372  */
373 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
374 EXPORT_SYMBOL_GPL(musb_readb);
375 
376 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
377 EXPORT_SYMBOL_GPL(musb_writeb);
378 
379 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
380 EXPORT_SYMBOL_GPL(musb_readw);
381 
382 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
383 EXPORT_SYMBOL_GPL(musb_writew);
384 
385 u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
386 EXPORT_SYMBOL_GPL(musb_readl);
387 
388 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
389 EXPORT_SYMBOL_GPL(musb_writel);
390 
391 /*
392  * New style IO functions
393  */
394 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
395 {
396         return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
397 }
398 
399 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
400 {
401         return hw_ep->musb->io.write_fifo(hw_ep, len, src);
402 }
403 
404 /*-------------------------------------------------------------------------*/
405 
406 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
407 static const u8 musb_test_packet[53] = {
408         /* implicit SYNC then DATA0 to start */
409 
410         /* JKJKJKJK x9 */
411         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
412         /* JJKKJJKK x8 */
413         0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
414         /* JJJJKKKK x8 */
415         0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
416         /* JJJJJJJKKKKKKK x8 */
417         0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
418         /* JJJJJJJK x8 */
419         0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
420         /* JKKKKKKK x10, JK */
421         0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
422 
423         /* implicit CRC16 then EOP to end */
424 };
425 
426 void musb_load_testpacket(struct musb *musb)
427 {
428         void __iomem    *regs = musb->endpoints[0].regs;
429 
430         musb_ep_select(musb->mregs, 0);
431         musb_write_fifo(musb->control_ep,
432                         sizeof(musb_test_packet), musb_test_packet);
433         musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
434 }
435 
436 /*-------------------------------------------------------------------------*/
437 
438 /*
439  * Handles OTG hnp timeouts, such as b_ase0_brst
440  */
441 static void musb_otg_timer_func(unsigned long data)
442 {
443         struct musb     *musb = (struct musb *)data;
444         unsigned long   flags;
445 
446         spin_lock_irqsave(&musb->lock, flags);
447         switch (musb->xceiv->otg->state) {
448         case OTG_STATE_B_WAIT_ACON:
449                 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
450                 musb_g_disconnect(musb);
451                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
452                 musb->is_active = 0;
453                 break;
454         case OTG_STATE_A_SUSPEND:
455         case OTG_STATE_A_WAIT_BCON:
456                 dev_dbg(musb->controller, "HNP: %s timeout\n",
457                         usb_otg_state_string(musb->xceiv->otg->state));
458                 musb_platform_set_vbus(musb, 0);
459                 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
460                 break;
461         default:
462                 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
463                         usb_otg_state_string(musb->xceiv->otg->state));
464         }
465         spin_unlock_irqrestore(&musb->lock, flags);
466 }
467 
468 /*
469  * Stops the HNP transition. Caller must take care of locking.
470  */
471 void musb_hnp_stop(struct musb *musb)
472 {
473         struct usb_hcd  *hcd = musb->hcd;
474         void __iomem    *mbase = musb->mregs;
475         u8      reg;
476 
477         dev_dbg(musb->controller, "HNP: stop from %s\n",
478                         usb_otg_state_string(musb->xceiv->otg->state));
479 
480         switch (musb->xceiv->otg->state) {
481         case OTG_STATE_A_PERIPHERAL:
482                 musb_g_disconnect(musb);
483                 dev_dbg(musb->controller, "HNP: back to %s\n",
484                         usb_otg_state_string(musb->xceiv->otg->state));
485                 break;
486         case OTG_STATE_B_HOST:
487                 dev_dbg(musb->controller, "HNP: Disabling HR\n");
488                 if (hcd)
489                         hcd->self.is_b_host = 0;
490                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
491                 MUSB_DEV_MODE(musb);
492                 reg = musb_readb(mbase, MUSB_POWER);
493                 reg |= MUSB_POWER_SUSPENDM;
494                 musb_writeb(mbase, MUSB_POWER, reg);
495                 /* REVISIT: Start SESSION_REQUEST here? */
496                 break;
497         default:
498                 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
499                         usb_otg_state_string(musb->xceiv->otg->state));
500         }
501 
502         /*
503          * When returning to A state after HNP, avoid hub_port_rebounce(),
504          * which cause occasional OPT A "Did not receive reset after connect"
505          * errors.
506          */
507         musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
508 }
509 
510 static void musb_generic_disable(struct musb *musb);
511 /*
512  * Interrupt Service Routine to record USB "global" interrupts.
513  * Since these do not happen often and signify things of
514  * paramount importance, it seems OK to check them individually;
515  * the order of the tests is specified in the manual
516  *
517  * @param musb instance pointer
518  * @param int_usb register contents
519  * @param devctl
520  * @param power
521  */
522 
523 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
524                                 u8 devctl)
525 {
526         irqreturn_t handled = IRQ_NONE;
527 
528         dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
529                 int_usb);
530 
531         /* in host mode, the peripheral may issue remote wakeup.
532          * in peripheral mode, the host may resume the link.
533          * spurious RESUME irqs happen too, paired with SUSPEND.
534          */
535         if (int_usb & MUSB_INTR_RESUME) {
536                 handled = IRQ_HANDLED;
537                 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->otg->state));
538 
539                 if (devctl & MUSB_DEVCTL_HM) {
540                         void __iomem *mbase = musb->mregs;
541                         u8 power;
542 
543                         switch (musb->xceiv->otg->state) {
544                         case OTG_STATE_A_SUSPEND:
545                                 /* remote wakeup?  later, GetPortStatus
546                                  * will stop RESUME signaling
547                                  */
548 
549                                 power = musb_readb(musb->mregs, MUSB_POWER);
550                                 if (power & MUSB_POWER_SUSPENDM) {
551                                         /* spurious */
552                                         musb->int_usb &= ~MUSB_INTR_SUSPEND;
553                                         dev_dbg(musb->controller, "Spurious SUSPENDM\n");
554                                         break;
555                                 }
556 
557                                 power &= ~MUSB_POWER_SUSPENDM;
558                                 musb_writeb(mbase, MUSB_POWER,
559                                                 power | MUSB_POWER_RESUME);
560 
561                                 musb->port1_status |=
562                                                 (USB_PORT_STAT_C_SUSPEND << 16)
563                                                 | MUSB_PORT_STAT_RESUME;
564                                 musb->rh_timer = jiffies
565                                                  + msecs_to_jiffies(20);
566                                 musb->need_finish_resume = 1;
567 
568                                 musb->xceiv->otg->state = OTG_STATE_A_HOST;
569                                 musb->is_active = 1;
570                                 break;
571                         case OTG_STATE_B_WAIT_ACON:
572                                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
573                                 musb->is_active = 1;
574                                 MUSB_DEV_MODE(musb);
575                                 break;
576                         default:
577                                 WARNING("bogus %s RESUME (%s)\n",
578                                         "host",
579                                         usb_otg_state_string(musb->xceiv->otg->state));
580                         }
581                 } else {
582                         switch (musb->xceiv->otg->state) {
583                         case OTG_STATE_A_SUSPEND:
584                                 /* possibly DISCONNECT is upcoming */
585                                 musb->xceiv->otg->state = OTG_STATE_A_HOST;
586                                 musb_host_resume_root_hub(musb);
587                                 break;
588                         case OTG_STATE_B_WAIT_ACON:
589                         case OTG_STATE_B_PERIPHERAL:
590                                 /* disconnect while suspended?  we may
591                                  * not get a disconnect irq...
592                                  */
593                                 if ((devctl & MUSB_DEVCTL_VBUS)
594                                                 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
595                                                 ) {
596                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
597                                         musb->int_usb &= ~MUSB_INTR_SUSPEND;
598                                         break;
599                                 }
600                                 musb_g_resume(musb);
601                                 break;
602                         case OTG_STATE_B_IDLE:
603                                 musb->int_usb &= ~MUSB_INTR_SUSPEND;
604                                 break;
605                         default:
606                                 WARNING("bogus %s RESUME (%s)\n",
607                                         "peripheral",
608                                         usb_otg_state_string(musb->xceiv->otg->state));
609                         }
610                 }
611         }
612 
613         /* see manual for the order of the tests */
614         if (int_usb & MUSB_INTR_SESSREQ) {
615                 void __iomem *mbase = musb->mregs;
616 
617                 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
618                                 && (devctl & MUSB_DEVCTL_BDEVICE)) {
619                         dev_dbg(musb->controller, "SessReq while on B state\n");
620                         return IRQ_HANDLED;
621                 }
622 
623                 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
624                         usb_otg_state_string(musb->xceiv->otg->state));
625 
626                 /* IRQ arrives from ID pin sense or (later, if VBUS power
627                  * is removed) SRP.  responses are time critical:
628                  *  - turn on VBUS (with silicon-specific mechanism)
629                  *  - go through A_WAIT_VRISE
630                  *  - ... to A_WAIT_BCON.
631                  * a_wait_vrise_tmout triggers VBUS_ERROR transitions
632                  */
633                 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
634                 musb->ep0_stage = MUSB_EP0_START;
635                 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
636                 MUSB_HST_MODE(musb);
637                 musb_platform_set_vbus(musb, 1);
638 
639                 handled = IRQ_HANDLED;
640         }
641 
642         if (int_usb & MUSB_INTR_VBUSERROR) {
643                 int     ignore = 0;
644 
645                 /* During connection as an A-Device, we may see a short
646                  * current spikes causing voltage drop, because of cable
647                  * and peripheral capacitance combined with vbus draw.
648                  * (So: less common with truly self-powered devices, where
649                  * vbus doesn't act like a power supply.)
650                  *
651                  * Such spikes are short; usually less than ~500 usec, max
652                  * of ~2 msec.  That is, they're not sustained overcurrent
653                  * errors, though they're reported using VBUSERROR irqs.
654                  *
655                  * Workarounds:  (a) hardware: use self powered devices.
656                  * (b) software:  ignore non-repeated VBUS errors.
657                  *
658                  * REVISIT:  do delays from lots of DEBUG_KERNEL checks
659                  * make trouble here, keeping VBUS < 4.4V ?
660                  */
661                 switch (musb->xceiv->otg->state) {
662                 case OTG_STATE_A_HOST:
663                         /* recovery is dicey once we've gotten past the
664                          * initial stages of enumeration, but if VBUS
665                          * stayed ok at the other end of the link, and
666                          * another reset is due (at least for high speed,
667                          * to redo the chirp etc), it might work OK...
668                          */
669                 case OTG_STATE_A_WAIT_BCON:
670                 case OTG_STATE_A_WAIT_VRISE:
671                         if (musb->vbuserr_retry) {
672                                 void __iomem *mbase = musb->mregs;
673 
674                                 musb->vbuserr_retry--;
675                                 ignore = 1;
676                                 devctl |= MUSB_DEVCTL_SESSION;
677                                 musb_writeb(mbase, MUSB_DEVCTL, devctl);
678                         } else {
679                                 musb->port1_status |=
680                                           USB_PORT_STAT_OVERCURRENT
681                                         | (USB_PORT_STAT_C_OVERCURRENT << 16);
682                         }
683                         break;
684                 default:
685                         break;
686                 }
687 
688                 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
689                                 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
690                                 usb_otg_state_string(musb->xceiv->otg->state),
691                                 devctl,
692                                 ({ char *s;
693                                 switch (devctl & MUSB_DEVCTL_VBUS) {
694                                 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
695                                         s = "<SessEnd"; break;
696                                 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
697                                         s = "<AValid"; break;
698                                 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
699                                         s = "<VBusValid"; break;
700                                 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
701                                 default:
702                                         s = "VALID"; break;
703                                 } s; }),
704                                 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
705                                 musb->port1_status);
706 
707                 /* go through A_WAIT_VFALL then start a new session */
708                 if (!ignore)
709                         musb_platform_set_vbus(musb, 0);
710                 handled = IRQ_HANDLED;
711         }
712 
713         if (int_usb & MUSB_INTR_SUSPEND) {
714                 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
715                         usb_otg_state_string(musb->xceiv->otg->state), devctl);
716                 handled = IRQ_HANDLED;
717 
718                 switch (musb->xceiv->otg->state) {
719                 case OTG_STATE_A_PERIPHERAL:
720                         /* We also come here if the cable is removed, since
721                          * this silicon doesn't report ID-no-longer-grounded.
722                          *
723                          * We depend on T(a_wait_bcon) to shut us down, and
724                          * hope users don't do anything dicey during this
725                          * undesired detour through A_WAIT_BCON.
726                          */
727                         musb_hnp_stop(musb);
728                         musb_host_resume_root_hub(musb);
729                         musb_root_disconnect(musb);
730                         musb_platform_try_idle(musb, jiffies
731                                         + msecs_to_jiffies(musb->a_wait_bcon
732                                                 ? : OTG_TIME_A_WAIT_BCON));
733 
734                         break;
735                 case OTG_STATE_B_IDLE:
736                         if (!musb->is_active)
737                                 break;
738                 case OTG_STATE_B_PERIPHERAL:
739                         musb_g_suspend(musb);
740                         musb->is_active = musb->g.b_hnp_enable;
741                         if (musb->is_active) {
742                                 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
743                                 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
744                                 mod_timer(&musb->otg_timer, jiffies
745                                         + msecs_to_jiffies(
746                                                         OTG_TIME_B_ASE0_BRST));
747                         }
748                         break;
749                 case OTG_STATE_A_WAIT_BCON:
750                         if (musb->a_wait_bcon != 0)
751                                 musb_platform_try_idle(musb, jiffies
752                                         + msecs_to_jiffies(musb->a_wait_bcon));
753                         break;
754                 case OTG_STATE_A_HOST:
755                         musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
756                         musb->is_active = musb->hcd->self.b_hnp_enable;
757                         break;
758                 case OTG_STATE_B_HOST:
759                         /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
760                         dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
761                         break;
762                 default:
763                         /* "should not happen" */
764                         musb->is_active = 0;
765                         break;
766                 }
767         }
768 
769         if (int_usb & MUSB_INTR_CONNECT) {
770                 struct usb_hcd *hcd = musb->hcd;
771 
772                 handled = IRQ_HANDLED;
773                 musb->is_active = 1;
774 
775                 musb->ep0_stage = MUSB_EP0_START;
776 
777                 /* flush endpoints when transitioning from Device Mode */
778                 if (is_peripheral_active(musb)) {
779                         /* REVISIT HNP; just force disconnect */
780                 }
781                 musb->intrtxe = musb->epmask;
782                 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
783                 musb->intrrxe = musb->epmask & 0xfffe;
784                 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
785                 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
786                 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
787                                         |USB_PORT_STAT_HIGH_SPEED
788                                         |USB_PORT_STAT_ENABLE
789                                         );
790                 musb->port1_status |= USB_PORT_STAT_CONNECTION
791                                         |(USB_PORT_STAT_C_CONNECTION << 16);
792 
793                 /* high vs full speed is just a guess until after reset */
794                 if (devctl & MUSB_DEVCTL_LSDEV)
795                         musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
796 
797                 /* indicate new connection to OTG machine */
798                 switch (musb->xceiv->otg->state) {
799                 case OTG_STATE_B_PERIPHERAL:
800                         if (int_usb & MUSB_INTR_SUSPEND) {
801                                 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
802                                 int_usb &= ~MUSB_INTR_SUSPEND;
803                                 goto b_host;
804                         } else
805                                 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
806                         break;
807                 case OTG_STATE_B_WAIT_ACON:
808                         dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
809 b_host:
810                         musb->xceiv->otg->state = OTG_STATE_B_HOST;
811                         if (musb->hcd)
812                                 musb->hcd->self.is_b_host = 1;
813                         del_timer(&musb->otg_timer);
814                         break;
815                 default:
816                         if ((devctl & MUSB_DEVCTL_VBUS)
817                                         == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
818                                 musb->xceiv->otg->state = OTG_STATE_A_HOST;
819                                 if (hcd)
820                                         hcd->self.is_b_host = 0;
821                         }
822                         break;
823                 }
824 
825                 musb_host_poke_root_hub(musb);
826 
827                 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
828                                 usb_otg_state_string(musb->xceiv->otg->state), devctl);
829         }
830 
831         if (int_usb & MUSB_INTR_DISCONNECT) {
832                 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
833                                 usb_otg_state_string(musb->xceiv->otg->state),
834                                 MUSB_MODE(musb), devctl);
835                 handled = IRQ_HANDLED;
836 
837                 switch (musb->xceiv->otg->state) {
838                 case OTG_STATE_A_HOST:
839                 case OTG_STATE_A_SUSPEND:
840                         musb_host_resume_root_hub(musb);
841                         musb_root_disconnect(musb);
842                         if (musb->a_wait_bcon != 0)
843                                 musb_platform_try_idle(musb, jiffies
844                                         + msecs_to_jiffies(musb->a_wait_bcon));
845                         break;
846                 case OTG_STATE_B_HOST:
847                         /* REVISIT this behaves for "real disconnect"
848                          * cases; make sure the other transitions from
849                          * from B_HOST act right too.  The B_HOST code
850                          * in hnp_stop() is currently not used...
851                          */
852                         musb_root_disconnect(musb);
853                         if (musb->hcd)
854                                 musb->hcd->self.is_b_host = 0;
855                         musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
856                         MUSB_DEV_MODE(musb);
857                         musb_g_disconnect(musb);
858                         break;
859                 case OTG_STATE_A_PERIPHERAL:
860                         musb_hnp_stop(musb);
861                         musb_root_disconnect(musb);
862                         /* FALLTHROUGH */
863                 case OTG_STATE_B_WAIT_ACON:
864                         /* FALLTHROUGH */
865                 case OTG_STATE_B_PERIPHERAL:
866                 case OTG_STATE_B_IDLE:
867                         musb_g_disconnect(musb);
868                         break;
869                 default:
870                         WARNING("unhandled DISCONNECT transition (%s)\n",
871                                 usb_otg_state_string(musb->xceiv->otg->state));
872                         break;
873                 }
874         }
875 
876         /* mentor saves a bit: bus reset and babble share the same irq.
877          * only host sees babble; only peripheral sees bus reset.
878          */
879         if (int_usb & MUSB_INTR_RESET) {
880                 handled = IRQ_HANDLED;
881                 if ((devctl & MUSB_DEVCTL_HM) != 0) {
882                         /*
883                          * Looks like non-HS BABBLE can be ignored, but
884                          * HS BABBLE is an error condition. For HS the solution
885                          * is to avoid babble in the first place and fix what
886                          * caused BABBLE. When HS BABBLE happens we can only
887                          * stop the session.
888                          */
889                         if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
890                                 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
891                         else {
892                                 ERR("Stopping host session -- babble\n");
893                                 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
894                         }
895                 } else {
896                         dev_dbg(musb->controller, "BUS RESET as %s\n",
897                                 usb_otg_state_string(musb->xceiv->otg->state));
898                         switch (musb->xceiv->otg->state) {
899                         case OTG_STATE_A_SUSPEND:
900                                 musb_g_reset(musb);
901                                 /* FALLTHROUGH */
902                         case OTG_STATE_A_WAIT_BCON:     /* OPT TD.4.7-900ms */
903                                 /* never use invalid T(a_wait_bcon) */
904                                 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
905                                         usb_otg_state_string(musb->xceiv->otg->state),
906                                         TA_WAIT_BCON(musb));
907                                 mod_timer(&musb->otg_timer, jiffies
908                                         + msecs_to_jiffies(TA_WAIT_BCON(musb)));
909                                 break;
910                         case OTG_STATE_A_PERIPHERAL:
911                                 del_timer(&musb->otg_timer);
912                                 musb_g_reset(musb);
913                                 break;
914                         case OTG_STATE_B_WAIT_ACON:
915                                 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
916                                         usb_otg_state_string(musb->xceiv->otg->state));
917                                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
918                                 musb_g_reset(musb);
919                                 break;
920                         case OTG_STATE_B_IDLE:
921                                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
922                                 /* FALLTHROUGH */
923                         case OTG_STATE_B_PERIPHERAL:
924                                 musb_g_reset(musb);
925                                 break;
926                         default:
927                                 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
928                                         usb_otg_state_string(musb->xceiv->otg->state));
929                         }
930                 }
931         }
932 
933         /* handle babble condition */
934         if (int_usb & MUSB_INTR_BABBLE && is_host_active(musb)) {
935                 musb_generic_disable(musb);
936                 schedule_delayed_work(&musb->recover_work,
937                                       msecs_to_jiffies(100));
938         }
939 
940 #if 0
941 /* REVISIT ... this would be for multiplexing periodic endpoints, or
942  * supporting transfer phasing to prevent exceeding ISO bandwidth
943  * limits of a given frame or microframe.
944  *
945  * It's not needed for peripheral side, which dedicates endpoints;
946  * though it _might_ use SOF irqs for other purposes.
947  *
948  * And it's not currently needed for host side, which also dedicates
949  * endpoints, relies on TX/RX interval registers, and isn't claimed
950  * to support ISO transfers yet.
951  */
952         if (int_usb & MUSB_INTR_SOF) {
953                 void __iomem *mbase = musb->mregs;
954                 struct musb_hw_ep       *ep;
955                 u8 epnum;
956                 u16 frame;
957 
958                 dev_dbg(musb->controller, "START_OF_FRAME\n");
959                 handled = IRQ_HANDLED;
960 
961                 /* start any periodic Tx transfers waiting for current frame */
962                 frame = musb_readw(mbase, MUSB_FRAME);
963                 ep = musb->endpoints;
964                 for (epnum = 1; (epnum < musb->nr_endpoints)
965                                         && (musb->epmask >= (1 << epnum));
966                                 epnum++, ep++) {
967                         /*
968                          * FIXME handle framecounter wraps (12 bits)
969                          * eliminate duplicated StartUrb logic
970                          */
971                         if (ep->dwWaitFrame >= frame) {
972                                 ep->dwWaitFrame = 0;
973                                 pr_debug("SOF --> periodic TX%s on %d\n",
974                                         ep->tx_channel ? " DMA" : "",
975                                         epnum);
976                                 if (!ep->tx_channel)
977                                         musb_h_tx_start(musb, epnum);
978                                 else
979                                         cppi_hostdma_start(musb, epnum);
980                         }
981                 }               /* end of for loop */
982         }
983 #endif
984 
985         schedule_work(&musb->irq_work);
986 
987         return handled;
988 }
989 
990 /*-------------------------------------------------------------------------*/
991 
992 static void musb_generic_disable(struct musb *musb)
993 {
994         void __iomem    *mbase = musb->mregs;
995         u16     temp;
996 
997         /* disable interrupts */
998         musb_writeb(mbase, MUSB_INTRUSBE, 0);
999         musb->intrtxe = 0;
1000         musb_writew(mbase, MUSB_INTRTXE, 0);
1001         musb->intrrxe = 0;
1002         musb_writew(mbase, MUSB_INTRRXE, 0);
1003 
1004         /* off */
1005         musb_writeb(mbase, MUSB_DEVCTL, 0);
1006 
1007         /*  flush pending interrupts */
1008         temp = musb_readb(mbase, MUSB_INTRUSB);
1009         temp = musb_readw(mbase, MUSB_INTRTX);
1010         temp = musb_readw(mbase, MUSB_INTRRX);
1011 
1012 }
1013 
1014 /*
1015  * Program the HDRC to start (enable interrupts, dma, etc.).
1016  */
1017 void musb_start(struct musb *musb)
1018 {
1019         void __iomem    *regs = musb->mregs;
1020         u8              devctl = musb_readb(regs, MUSB_DEVCTL);
1021 
1022         dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1023 
1024         /*  Set INT enable registers, enable interrupts */
1025         musb->intrtxe = musb->epmask;
1026         musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1027         musb->intrrxe = musb->epmask & 0xfffe;
1028         musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1029         musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1030 
1031         musb_writeb(regs, MUSB_TESTMODE, 0);
1032 
1033         /* put into basic highspeed mode and start session */
1034         musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
1035                         | MUSB_POWER_HSENAB
1036                         /* ENSUSPEND wedges tusb */
1037                         /* | MUSB_POWER_ENSUSPEND */
1038                    );
1039 
1040         musb->is_active = 0;
1041         devctl = musb_readb(regs, MUSB_DEVCTL);
1042         devctl &= ~MUSB_DEVCTL_SESSION;
1043 
1044         /* session started after:
1045          * (a) ID-grounded irq, host mode;
1046          * (b) vbus present/connect IRQ, peripheral mode;
1047          * (c) peripheral initiates, using SRP
1048          */
1049         if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1050                         (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1051                 musb->is_active = 1;
1052         } else {
1053                 devctl |= MUSB_DEVCTL_SESSION;
1054         }
1055 
1056         musb_platform_enable(musb);
1057         musb_writeb(regs, MUSB_DEVCTL, devctl);
1058 }
1059 
1060 /*
1061  * Make the HDRC stop (disable interrupts, etc.);
1062  * reversible by musb_start
1063  * called on gadget driver unregister
1064  * with controller locked, irqs blocked
1065  * acts as a NOP unless some role activated the hardware
1066  */
1067 void musb_stop(struct musb *musb)
1068 {
1069         /* stop IRQs, timers, ... */
1070         musb_platform_disable(musb);
1071         musb_generic_disable(musb);
1072         dev_dbg(musb->controller, "HDRC disabled\n");
1073 
1074         /* FIXME
1075          *  - mark host and/or peripheral drivers unusable/inactive
1076          *  - disable DMA (and enable it in HdrcStart)
1077          *  - make sure we can musb_start() after musb_stop(); with
1078          *    OTG mode, gadget driver module rmmod/modprobe cycles that
1079          *  - ...
1080          */
1081         musb_platform_try_idle(musb, 0);
1082 }
1083 
1084 static void musb_shutdown(struct platform_device *pdev)
1085 {
1086         struct musb     *musb = dev_to_musb(&pdev->dev);
1087         unsigned long   flags;
1088 
1089         pm_runtime_get_sync(musb->controller);
1090 
1091         musb_host_cleanup(musb);
1092         musb_gadget_cleanup(musb);
1093 
1094         spin_lock_irqsave(&musb->lock, flags);
1095         musb_platform_disable(musb);
1096         musb_generic_disable(musb);
1097         spin_unlock_irqrestore(&musb->lock, flags);
1098 
1099         musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1100         musb_platform_exit(musb);
1101 
1102         pm_runtime_put(musb->controller);
1103         /* FIXME power down */
1104 }
1105 
1106 
1107 /*-------------------------------------------------------------------------*/
1108 
1109 /*
1110  * The silicon either has hard-wired endpoint configurations, or else
1111  * "dynamic fifo" sizing.  The driver has support for both, though at this
1112  * writing only the dynamic sizing is very well tested.   Since we switched
1113  * away from compile-time hardware parameters, we can no longer rely on
1114  * dead code elimination to leave only the relevant one in the object file.
1115  *
1116  * We don't currently use dynamic fifo setup capability to do anything
1117  * more than selecting one of a bunch of predefined configurations.
1118  */
1119 static ushort fifo_mode;
1120 
1121 /* "modprobe ... fifo_mode=1" etc */
1122 module_param(fifo_mode, ushort, 0);
1123 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1124 
1125 /*
1126  * tables defining fifo_mode values.  define more if you like.
1127  * for host side, make sure both halves of ep1 are set up.
1128  */
1129 
1130 /* mode 0 - fits in 2KB */
1131 static struct musb_fifo_cfg mode_0_cfg[] = {
1132 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1133 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1134 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1135 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1136 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1137 };
1138 
1139 /* mode 1 - fits in 4KB */
1140 static struct musb_fifo_cfg mode_1_cfg[] = {
1141 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1142 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1143 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1144 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1145 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1146 };
1147 
1148 /* mode 2 - fits in 4KB */
1149 static struct musb_fifo_cfg mode_2_cfg[] = {
1150 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1151 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1152 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1153 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1154 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1155 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1156 };
1157 
1158 /* mode 3 - fits in 4KB */
1159 static struct musb_fifo_cfg mode_3_cfg[] = {
1160 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1161 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1162 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1163 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1164 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1165 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1166 };
1167 
1168 /* mode 4 - fits in 16KB */
1169 static struct musb_fifo_cfg mode_4_cfg[] = {
1170 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1171 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1172 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1173 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1174 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1175 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1176 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1177 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1178 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1179 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1180 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 512, },
1181 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 512, },
1182 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 512, },
1183 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 512, },
1184 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 512, },
1185 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
1186 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
1187 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
1188 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
1189 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
1190 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
1191 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
1192 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
1193 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
1194 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1195 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1196 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1197 };
1198 
1199 /* mode 5 - fits in 8KB */
1200 static struct musb_fifo_cfg mode_5_cfg[] = {
1201 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1202 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1203 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1204 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1205 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1206 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1207 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1208 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1209 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1210 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1211 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 32, },
1212 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 32, },
1213 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 32, },
1214 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 32, },
1215 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 32, },
1216 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 32, },
1217 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 32, },
1218 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 32, },
1219 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 32, },
1220 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 32, },
1221 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 32, },
1222 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 32, },
1223 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 32, },
1224 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 32, },
1225 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1226 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1227 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1228 };
1229 
1230 /*
1231  * configure a fifo; for non-shared endpoints, this may be called
1232  * once for a tx fifo and once for an rx fifo.
1233  *
1234  * returns negative errno or offset for next fifo.
1235  */
1236 static int
1237 fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
1238                 const struct musb_fifo_cfg *cfg, u16 offset)
1239 {
1240         void __iomem    *mbase = musb->mregs;
1241         int     size = 0;
1242         u16     maxpacket = cfg->maxpacket;
1243         u16     c_off = offset >> 3;
1244         u8      c_size;
1245 
1246         /* expect hw_ep has already been zero-initialized */
1247 
1248         size = ffs(max(maxpacket, (u16) 8)) - 1;
1249         maxpacket = 1 << size;
1250 
1251         c_size = size - 3;
1252         if (cfg->mode == BUF_DOUBLE) {
1253                 if ((offset + (maxpacket << 1)) >
1254                                 (1 << (musb->config->ram_bits + 2)))
1255                         return -EMSGSIZE;
1256                 c_size |= MUSB_FIFOSZ_DPB;
1257         } else {
1258                 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1259                         return -EMSGSIZE;
1260         }
1261 
1262         /* configure the FIFO */
1263         musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1264 
1265         /* EP0 reserved endpoint for control, bidirectional;
1266          * EP1 reserved for bulk, two unidirectional halves.
1267          */
1268         if (hw_ep->epnum == 1)
1269                 musb->bulk_ep = hw_ep;
1270         /* REVISIT error check:  be sure ep0 can both rx and tx ... */
1271         switch (cfg->style) {
1272         case FIFO_TX:
1273                 musb_write_txfifosz(mbase, c_size);
1274                 musb_write_txfifoadd(mbase, c_off);
1275                 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1276                 hw_ep->max_packet_sz_tx = maxpacket;
1277                 break;
1278         case FIFO_RX:
1279                 musb_write_rxfifosz(mbase, c_size);
1280                 musb_write_rxfifoadd(mbase, c_off);
1281                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1282                 hw_ep->max_packet_sz_rx = maxpacket;
1283                 break;
1284         case FIFO_RXTX:
1285                 musb_write_txfifosz(mbase, c_size);
1286                 musb_write_txfifoadd(mbase, c_off);
1287                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1288                 hw_ep->max_packet_sz_rx = maxpacket;
1289 
1290                 musb_write_rxfifosz(mbase, c_size);
1291                 musb_write_rxfifoadd(mbase, c_off);
1292                 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1293                 hw_ep->max_packet_sz_tx = maxpacket;
1294 
1295                 hw_ep->is_shared_fifo = true;
1296                 break;
1297         }
1298 
1299         /* NOTE rx and tx endpoint irqs aren't managed separately,
1300          * which happens to be ok
1301          */
1302         musb->epmask |= (1 << hw_ep->epnum);
1303 
1304         return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1305 }
1306 
1307 static struct musb_fifo_cfg ep0_cfg = {
1308         .style = FIFO_RXTX, .maxpacket = 64,
1309 };
1310 
1311 static int ep_config_from_table(struct musb *musb)
1312 {
1313         const struct musb_fifo_cfg      *cfg;
1314         unsigned                i, n;
1315         int                     offset;
1316         struct musb_hw_ep       *hw_ep = musb->endpoints;
1317 
1318         if (musb->config->fifo_cfg) {
1319                 cfg = musb->config->fifo_cfg;
1320                 n = musb->config->fifo_cfg_size;
1321                 goto done;
1322         }
1323 
1324         switch (fifo_mode) {
1325         default:
1326                 fifo_mode = 0;
1327                 /* FALLTHROUGH */
1328         case 0:
1329                 cfg = mode_0_cfg;
1330                 n = ARRAY_SIZE(mode_0_cfg);
1331                 break;
1332         case 1:
1333                 cfg = mode_1_cfg;
1334                 n = ARRAY_SIZE(mode_1_cfg);
1335                 break;
1336         case 2:
1337                 cfg = mode_2_cfg;
1338                 n = ARRAY_SIZE(mode_2_cfg);
1339                 break;
1340         case 3:
1341                 cfg = mode_3_cfg;
1342                 n = ARRAY_SIZE(mode_3_cfg);
1343                 break;
1344         case 4:
1345                 cfg = mode_4_cfg;
1346                 n = ARRAY_SIZE(mode_4_cfg);
1347                 break;
1348         case 5:
1349                 cfg = mode_5_cfg;
1350                 n = ARRAY_SIZE(mode_5_cfg);
1351                 break;
1352         }
1353 
1354         printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1355                         musb_driver_name, fifo_mode);
1356 
1357 
1358 done:
1359         offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1360         /* assert(offset > 0) */
1361 
1362         /* NOTE:  for RTL versions >= 1.400 EPINFO and RAMINFO would
1363          * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1364          */
1365 
1366         for (i = 0; i < n; i++) {
1367                 u8      epn = cfg->hw_ep_num;
1368 
1369                 if (epn >= musb->config->num_eps) {
1370                         pr_debug("%s: invalid ep %d\n",
1371                                         musb_driver_name, epn);
1372                         return -EINVAL;
1373                 }
1374                 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1375                 if (offset < 0) {
1376                         pr_debug("%s: mem overrun, ep %d\n",
1377                                         musb_driver_name, epn);
1378                         return offset;
1379                 }
1380                 epn++;
1381                 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1382         }
1383 
1384         printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1385                         musb_driver_name,
1386                         n + 1, musb->config->num_eps * 2 - 1,
1387                         offset, (1 << (musb->config->ram_bits + 2)));
1388 
1389         if (!musb->bulk_ep) {
1390                 pr_debug("%s: missing bulk\n", musb_driver_name);
1391                 return -EINVAL;
1392         }
1393 
1394         return 0;
1395 }
1396 
1397 
1398 /*
1399  * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1400  * @param musb the controller
1401  */
1402 static int ep_config_from_hw(struct musb *musb)
1403 {
1404         u8 epnum = 0;
1405         struct musb_hw_ep *hw_ep;
1406         void __iomem *mbase = musb->mregs;
1407         int ret = 0;
1408 
1409         dev_dbg(musb->controller, "<== static silicon ep config\n");
1410 
1411         /* FIXME pick up ep0 maxpacket size */
1412 
1413         for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1414                 musb_ep_select(mbase, epnum);
1415                 hw_ep = musb->endpoints + epnum;
1416 
1417                 ret = musb_read_fifosize(musb, hw_ep, epnum);
1418                 if (ret < 0)
1419                         break;
1420 
1421                 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1422 
1423                 /* pick an RX/TX endpoint for bulk */
1424                 if (hw_ep->max_packet_sz_tx < 512
1425                                 || hw_ep->max_packet_sz_rx < 512)
1426                         continue;
1427 
1428                 /* REVISIT:  this algorithm is lazy, we should at least
1429                  * try to pick a double buffered endpoint.
1430                  */
1431                 if (musb->bulk_ep)
1432                         continue;
1433                 musb->bulk_ep = hw_ep;
1434         }
1435 
1436         if (!musb->bulk_ep) {
1437                 pr_debug("%s: missing bulk\n", musb_driver_name);
1438                 return -EINVAL;
1439         }
1440 
1441         return 0;
1442 }
1443 
1444 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1445 
1446 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1447  * configure endpoints, or take their config from silicon
1448  */
1449 static int musb_core_init(u16 musb_type, struct musb *musb)
1450 {
1451         u8 reg;
1452         char *type;
1453         char aInfo[90], aRevision[32], aDate[12];
1454         void __iomem    *mbase = musb->mregs;
1455         int             status = 0;
1456         int             i;
1457 
1458         /* log core options (read using indexed model) */
1459         reg = musb_read_configdata(mbase);
1460 
1461         strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1462         if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1463                 strcat(aInfo, ", dyn FIFOs");
1464                 musb->dyn_fifo = true;
1465         }
1466         if (reg & MUSB_CONFIGDATA_MPRXE) {
1467                 strcat(aInfo, ", bulk combine");
1468                 musb->bulk_combine = true;
1469         }
1470         if (reg & MUSB_CONFIGDATA_MPTXE) {
1471                 strcat(aInfo, ", bulk split");
1472                 musb->bulk_split = true;
1473         }
1474         if (reg & MUSB_CONFIGDATA_HBRXE) {
1475                 strcat(aInfo, ", HB-ISO Rx");
1476                 musb->hb_iso_rx = true;
1477         }
1478         if (reg & MUSB_CONFIGDATA_HBTXE) {
1479                 strcat(aInfo, ", HB-ISO Tx");
1480                 musb->hb_iso_tx = true;
1481         }
1482         if (reg & MUSB_CONFIGDATA_SOFTCONE)
1483                 strcat(aInfo, ", SoftConn");
1484 
1485         printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1486                         musb_driver_name, reg, aInfo);
1487 
1488         aDate[0] = 0;
1489         if (MUSB_CONTROLLER_MHDRC == musb_type) {
1490                 musb->is_multipoint = 1;
1491                 type = "M";
1492         } else {
1493                 musb->is_multipoint = 0;
1494                 type = "";
1495 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1496                 printk(KERN_ERR
1497                         "%s: kernel must blacklist external hubs\n",
1498                         musb_driver_name);
1499 #endif
1500         }
1501 
1502         /* log release info */
1503         musb->hwvers = musb_read_hwvers(mbase);
1504         snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1505                 MUSB_HWVERS_MINOR(musb->hwvers),
1506                 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1507         printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1508                         musb_driver_name, type, aRevision, aDate);
1509 
1510         /* configure ep0 */
1511         musb_configure_ep0(musb);
1512 
1513         /* discover endpoint configuration */
1514         musb->nr_endpoints = 1;
1515         musb->epmask = 1;
1516 
1517         if (musb->dyn_fifo)
1518                 status = ep_config_from_table(musb);
1519         else
1520                 status = ep_config_from_hw(musb);
1521 
1522         if (status < 0)
1523                 return status;
1524 
1525         /* finish init, and print endpoint config */
1526         for (i = 0; i < musb->nr_endpoints; i++) {
1527                 struct musb_hw_ep       *hw_ep = musb->endpoints + i;
1528 
1529                 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1530 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1531                 if (musb->io.quirks & MUSB_IN_TUSB) {
1532                         hw_ep->fifo_async = musb->async + 0x400 +
1533                                 musb->io.fifo_offset(i);
1534                         hw_ep->fifo_sync = musb->sync + 0x400 +
1535                                 musb->io.fifo_offset(i);
1536                         hw_ep->fifo_sync_va =
1537                                 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1538 
1539                         if (i == 0)
1540                                 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1541                         else
1542                                 hw_ep->conf = mbase + 0x400 +
1543                                         (((i - 1) & 0xf) << 2);
1544                 }
1545 #endif
1546 
1547                 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1548                 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1549                 hw_ep->rx_reinit = 1;
1550                 hw_ep->tx_reinit = 1;
1551 
1552                 if (hw_ep->max_packet_sz_tx) {
1553                         dev_dbg(musb->controller,
1554                                 "%s: hw_ep %d%s, %smax %d\n",
1555                                 musb_driver_name, i,
1556                                 hw_ep->is_shared_fifo ? "shared" : "tx",
1557                                 hw_ep->tx_double_buffered
1558                                         ? "doublebuffer, " : "",
1559                                 hw_ep->max_packet_sz_tx);
1560                 }
1561                 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1562                         dev_dbg(musb->controller,
1563                                 "%s: hw_ep %d%s, %smax %d\n",
1564                                 musb_driver_name, i,
1565                                 "rx",
1566                                 hw_ep->rx_double_buffered
1567                                         ? "doublebuffer, " : "",
1568                                 hw_ep->max_packet_sz_rx);
1569                 }
1570                 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1571                         dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1572         }
1573 
1574         return 0;
1575 }
1576 
1577 /*-------------------------------------------------------------------------*/
1578 
1579 /*
1580  * handle all the irqs defined by the HDRC core. for now we expect:  other
1581  * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1582  * will be assigned, and the irq will already have been acked.
1583  *
1584  * called in irq context with spinlock held, irqs blocked
1585  */
1586 irqreturn_t musb_interrupt(struct musb *musb)
1587 {
1588         irqreturn_t     retval = IRQ_NONE;
1589         u8              devctl;
1590         int             ep_num;
1591         u32             reg;
1592 
1593         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1594 
1595         dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1596                 is_host_active(musb) ? "host" : "peripheral",
1597                 musb->int_usb, musb->int_tx, musb->int_rx);
1598 
1599         /* the core can interrupt us for multiple reasons; docs have
1600          * a generic interrupt flowchart to follow
1601          */
1602         if (musb->int_usb)
1603                 retval |= musb_stage0_irq(musb, musb->int_usb,
1604                                 devctl);
1605 
1606         /* "stage 1" is handling endpoint irqs */
1607 
1608         /* handle endpoint 0 first */
1609         if (musb->int_tx & 1) {
1610                 if (is_host_active(musb))
1611                         retval |= musb_h_ep0_irq(musb);
1612                 else
1613                         retval |= musb_g_ep0_irq(musb);
1614         }
1615 
1616         /* RX on endpoints 1-15 */
1617         reg = musb->int_rx >> 1;
1618         ep_num = 1;
1619         while (reg) {
1620                 if (reg & 1) {
1621                         /* musb_ep_select(musb->mregs, ep_num); */
1622                         /* REVISIT just retval = ep->rx_irq(...) */
1623                         retval = IRQ_HANDLED;
1624                         if (is_host_active(musb))
1625                                 musb_host_rx(musb, ep_num);
1626                         else
1627                                 musb_g_rx(musb, ep_num);
1628                 }
1629 
1630                 reg >>= 1;
1631                 ep_num++;
1632         }
1633 
1634         /* TX on endpoints 1-15 */
1635         reg = musb->int_tx >> 1;
1636         ep_num = 1;
1637         while (reg) {
1638                 if (reg & 1) {
1639                         /* musb_ep_select(musb->mregs, ep_num); */
1640                         /* REVISIT just retval |= ep->tx_irq(...) */
1641                         retval = IRQ_HANDLED;
1642                         if (is_host_active(musb))
1643                                 musb_host_tx(musb, ep_num);
1644                         else
1645                                 musb_g_tx(musb, ep_num);
1646                 }
1647                 reg >>= 1;
1648                 ep_num++;
1649         }
1650 
1651         return retval;
1652 }
1653 EXPORT_SYMBOL_GPL(musb_interrupt);
1654 
1655 #ifndef CONFIG_MUSB_PIO_ONLY
1656 static bool use_dma = 1;
1657 
1658 /* "modprobe ... use_dma=0" etc */
1659 module_param(use_dma, bool, 0);
1660 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1661 
1662 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1663 {
1664         /* called with controller lock already held */
1665 
1666         if (!epnum) {
1667 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1668                 if (!is_cppi_enabled()) {
1669                         /* endpoint 0 */
1670                         if (is_host_active(musb))
1671                                 musb_h_ep0_irq(musb);
1672                         else
1673                                 musb_g_ep0_irq(musb);
1674                 }
1675 #endif
1676         } else {
1677                 /* endpoints 1..15 */
1678                 if (transmit) {
1679                         if (is_host_active(musb))
1680                                 musb_host_tx(musb, epnum);
1681                         else
1682                                 musb_g_tx(musb, epnum);
1683                 } else {
1684                         /* receive */
1685                         if (is_host_active(musb))
1686                                 musb_host_rx(musb, epnum);
1687                         else
1688                                 musb_g_rx(musb, epnum);
1689                 }
1690         }
1691 }
1692 EXPORT_SYMBOL_GPL(musb_dma_completion);
1693 
1694 #else
1695 #define use_dma                 0
1696 #endif
1697 
1698 /*-------------------------------------------------------------------------*/
1699 
1700 static ssize_t
1701 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1702 {
1703         struct musb *musb = dev_to_musb(dev);
1704         unsigned long flags;
1705         int ret = -EINVAL;
1706 
1707         spin_lock_irqsave(&musb->lock, flags);
1708         ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1709         spin_unlock_irqrestore(&musb->lock, flags);
1710 
1711         return ret;
1712 }
1713 
1714 static ssize_t
1715 musb_mode_store(struct device *dev, struct device_attribute *attr,
1716                 const char *buf, size_t n)
1717 {
1718         struct musb     *musb = dev_to_musb(dev);
1719         unsigned long   flags;
1720         int             status;
1721 
1722         spin_lock_irqsave(&musb->lock, flags);
1723         if (sysfs_streq(buf, "host"))
1724                 status = musb_platform_set_mode(musb, MUSB_HOST);
1725         else if (sysfs_streq(buf, "peripheral"))
1726                 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1727         else if (sysfs_streq(buf, "otg"))
1728                 status = musb_platform_set_mode(musb, MUSB_OTG);
1729         else
1730                 status = -EINVAL;
1731         spin_unlock_irqrestore(&musb->lock, flags);
1732 
1733         return (status == 0) ? n : status;
1734 }
1735 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1736 
1737 static ssize_t
1738 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1739                 const char *buf, size_t n)
1740 {
1741         struct musb     *musb = dev_to_musb(dev);
1742         unsigned long   flags;
1743         unsigned long   val;
1744 
1745         if (sscanf(buf, "%lu", &val) < 1) {
1746                 dev_err(dev, "Invalid VBUS timeout ms value\n");
1747                 return -EINVAL;
1748         }
1749 
1750         spin_lock_irqsave(&musb->lock, flags);
1751         /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1752         musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1753         if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1754                 musb->is_active = 0;
1755         musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1756         spin_unlock_irqrestore(&musb->lock, flags);
1757 
1758         return n;
1759 }
1760 
1761 static ssize_t
1762 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1763 {
1764         struct musb     *musb = dev_to_musb(dev);
1765         unsigned long   flags;
1766         unsigned long   val;
1767         int             vbus;
1768 
1769         spin_lock_irqsave(&musb->lock, flags);
1770         val = musb->a_wait_bcon;
1771         /* FIXME get_vbus_status() is normally #defined as false...
1772          * and is effectively TUSB-specific.
1773          */
1774         vbus = musb_platform_get_vbus_status(musb);
1775         spin_unlock_irqrestore(&musb->lock, flags);
1776 
1777         return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1778                         vbus ? "on" : "off", val);
1779 }
1780 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1781 
1782 /* Gadget drivers can't know that a host is connected so they might want
1783  * to start SRP, but users can.  This allows userspace to trigger SRP.
1784  */
1785 static ssize_t
1786 musb_srp_store(struct device *dev, struct device_attribute *attr,
1787                 const char *buf, size_t n)
1788 {
1789         struct musb     *musb = dev_to_musb(dev);
1790         unsigned short  srp;
1791 
1792         if (sscanf(buf, "%hu", &srp) != 1
1793                         || (srp != 1)) {
1794                 dev_err(dev, "SRP: Value must be 1\n");
1795                 return -EINVAL;
1796         }
1797 
1798         if (srp == 1)
1799                 musb_g_wakeup(musb);
1800 
1801         return n;
1802 }
1803 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1804 
1805 static struct attribute *musb_attributes[] = {
1806         &dev_attr_mode.attr,
1807         &dev_attr_vbus.attr,
1808         &dev_attr_srp.attr,
1809         NULL
1810 };
1811 
1812 static const struct attribute_group musb_attr_group = {
1813         .attrs = musb_attributes,
1814 };
1815 
1816 /* Only used to provide driver mode change events */
1817 static void musb_irq_work(struct work_struct *data)
1818 {
1819         struct musb *musb = container_of(data, struct musb, irq_work);
1820 
1821         if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1822                 musb->xceiv_old_state = musb->xceiv->otg->state;
1823                 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1824         }
1825 }
1826 
1827 /* Recover from babble interrupt conditions */
1828 static void musb_recover_work(struct work_struct *data)
1829 {
1830         struct musb *musb = container_of(data, struct musb, recover_work.work);
1831         int status, ret;
1832 
1833         ret  = musb_platform_reset(musb);
1834         if (ret)
1835                 return;
1836 
1837         usb_phy_vbus_off(musb->xceiv);
1838         usleep_range(100, 200);
1839 
1840         usb_phy_vbus_on(musb->xceiv);
1841         usleep_range(100, 200);
1842 
1843         /*
1844          * When a babble condition occurs, the musb controller
1845          * removes the session bit and the endpoint config is lost.
1846          */
1847         if (musb->dyn_fifo)
1848                 status = ep_config_from_table(musb);
1849         else
1850                 status = ep_config_from_hw(musb);
1851 
1852         /* start the session again */
1853         if (status == 0)
1854                 musb_start(musb);
1855 }
1856 
1857 /* --------------------------------------------------------------------------
1858  * Init support
1859  */
1860 
1861 static struct musb *allocate_instance(struct device *dev,
1862                 struct musb_hdrc_config *config, void __iomem *mbase)
1863 {
1864         struct musb             *musb;
1865         struct musb_hw_ep       *ep;
1866         int                     epnum;
1867         int                     ret;
1868 
1869         musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1870         if (!musb)
1871                 return NULL;
1872 
1873         INIT_LIST_HEAD(&musb->control);
1874         INIT_LIST_HEAD(&musb->in_bulk);
1875         INIT_LIST_HEAD(&musb->out_bulk);
1876 
1877         musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1878         musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1879         musb->mregs = mbase;
1880         musb->ctrl_base = mbase;
1881         musb->nIrq = -ENODEV;
1882         musb->config = config;
1883         BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1884         for (epnum = 0, ep = musb->endpoints;
1885                         epnum < musb->config->num_eps;
1886                         epnum++, ep++) {
1887                 ep->musb = musb;
1888                 ep->epnum = epnum;
1889         }
1890 
1891         musb->controller = dev;
1892 
1893         ret = musb_host_alloc(musb);
1894         if (ret < 0)
1895                 goto err_free;
1896 
1897         dev_set_drvdata(dev, musb);
1898 
1899         return musb;
1900 
1901 err_free:
1902         return NULL;
1903 }
1904 
1905 static void musb_free(struct musb *musb)
1906 {
1907         /* this has multiple entry modes. it handles fault cleanup after
1908          * probe(), where things may be partially set up, as well as rmmod
1909          * cleanup after everything's been de-activated.
1910          */
1911 
1912 #ifdef CONFIG_SYSFS
1913         sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1914 #endif
1915 
1916         if (musb->nIrq >= 0) {
1917                 if (musb->irq_wake)
1918                         disable_irq_wake(musb->nIrq);
1919                 free_irq(musb->nIrq, musb);
1920         }
1921 
1922         musb_host_free(musb);
1923 }
1924 
1925 static void musb_deassert_reset(struct work_struct *work)
1926 {
1927         struct musb *musb;
1928         unsigned long flags;
1929 
1930         musb = container_of(work, struct musb, deassert_reset_work.work);
1931 
1932         spin_lock_irqsave(&musb->lock, flags);
1933 
1934         if (musb->port1_status & USB_PORT_STAT_RESET)
1935                 musb_port_reset(musb, false);
1936 
1937         spin_unlock_irqrestore(&musb->lock, flags);
1938 }
1939 
1940 /*
1941  * Perform generic per-controller initialization.
1942  *
1943  * @dev: the controller (already clocked, etc)
1944  * @nIrq: IRQ number
1945  * @ctrl: virtual address of controller registers,
1946  *      not yet corrected for platform-specific offsets
1947  */
1948 static int
1949 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1950 {
1951         int                     status;
1952         struct musb             *musb;
1953         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1954 
1955         /* The driver might handle more features than the board; OK.
1956          * Fail when the board needs a feature that's not enabled.
1957          */
1958         if (!plat) {
1959                 dev_dbg(dev, "no platform_data?\n");
1960                 status = -ENODEV;
1961                 goto fail0;
1962         }
1963 
1964         /* allocate */
1965         musb = allocate_instance(dev, plat->config, ctrl);
1966         if (!musb) {
1967                 status = -ENOMEM;
1968                 goto fail0;
1969         }
1970 
1971         pm_runtime_use_autosuspend(musb->controller);
1972         pm_runtime_set_autosuspend_delay(musb->controller, 200);
1973         pm_runtime_enable(musb->controller);
1974 
1975         spin_lock_init(&musb->lock);
1976         musb->board_set_power = plat->set_power;
1977         musb->min_power = plat->min_power;
1978         musb->ops = plat->platform_ops;
1979         musb->port_mode = plat->mode;
1980 
1981         /*
1982          * Initialize the default IO functions. At least omap2430 needs
1983          * these early. We initialize the platform specific IO functions
1984          * later on.
1985          */
1986         musb_readb = musb_default_readb;
1987         musb_writeb = musb_default_writeb;
1988         musb_readw = musb_default_readw;
1989         musb_writew = musb_default_writew;
1990         musb_readl = musb_default_readl;
1991         musb_writel = musb_default_writel;
1992 
1993         /* The musb_platform_init() call:
1994          *   - adjusts musb->mregs
1995          *   - sets the musb->isr
1996          *   - may initialize an integrated transceiver
1997          *   - initializes musb->xceiv, usually by otg_get_phy()
1998          *   - stops powering VBUS
1999          *
2000          * There are various transceiver configurations.  Blackfin,
2001          * DaVinci, TUSB60x0, and others integrate them.  OMAP3 uses
2002          * external/discrete ones in various flavors (twl4030 family,
2003          * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2004          */
2005         status = musb_platform_init(musb);
2006         if (status < 0)
2007                 goto fail1;
2008 
2009         if (!musb->isr) {
2010                 status = -ENODEV;
2011                 goto fail2;
2012         }
2013 
2014         if (musb->ops->quirks)
2015                 musb->io.quirks = musb->ops->quirks;
2016 
2017         /* At least tusb6010 has it's own offsets.. */
2018         if (musb->ops->ep_offset)
2019                 musb->io.ep_offset = musb->ops->ep_offset;
2020         if (musb->ops->ep_select)
2021                 musb->io.ep_select = musb->ops->ep_select;
2022 
2023         /* ..and some devices use indexed offset or flat offset */
2024         if (musb->io.quirks & MUSB_INDEXED_EP) {
2025                 musb->io.ep_offset = musb_indexed_ep_offset;
2026                 musb->io.ep_select = musb_indexed_ep_select;
2027         } else {
2028                 musb->io.ep_offset = musb_flat_ep_offset;
2029                 musb->io.ep_select = musb_flat_ep_select;
2030         }
2031 
2032         if (musb->ops->fifo_mode)
2033                 fifo_mode = musb->ops->fifo_mode;
2034         else
2035                 fifo_mode = 4;
2036 
2037         if (musb->ops->fifo_offset)
2038                 musb->io.fifo_offset = musb->ops->fifo_offset;
2039         else
2040                 musb->io.fifo_offset = musb_default_fifo_offset;
2041 
2042         if (musb->ops->readb)
2043                 musb_readb = musb->ops->readb;
2044         if (musb->ops->writeb)
2045                 musb_writeb = musb->ops->writeb;
2046         if (musb->ops->readw)
2047                 musb_readw = musb->ops->readw;
2048         if (musb->ops->writew)
2049                 musb_writew = musb->ops->writew;
2050         if (musb->ops->readl)
2051                 musb_readl = musb->ops->readl;
2052         if (musb->ops->writel)
2053                 musb_writel = musb->ops->writel;
2054 
2055         if (musb->ops->read_fifo)
2056                 musb->io.read_fifo = musb->ops->read_fifo;
2057         else
2058                 musb->io.read_fifo = musb_default_read_fifo;
2059 
2060         if (musb->ops->write_fifo)
2061                 musb->io.write_fifo = musb->ops->write_fifo;
2062         else
2063                 musb->io.write_fifo = musb_default_write_fifo;
2064 
2065         if (!musb->xceiv->io_ops) {
2066                 musb->xceiv->io_dev = musb->controller;
2067                 musb->xceiv->io_priv = musb->mregs;
2068                 musb->xceiv->io_ops = &musb_ulpi_access;
2069         }
2070 
2071         pm_runtime_get_sync(musb->controller);
2072 
2073         if (use_dma && dev->dma_mask) {
2074                 musb->dma_controller = dma_controller_create(musb, musb->mregs);
2075                 if (IS_ERR(musb->dma_controller)) {
2076                         status = PTR_ERR(musb->dma_controller);
2077                         goto fail2_5;
2078                 }
2079         }
2080 
2081         /* be sure interrupts are disabled before connecting ISR */
2082         musb_platform_disable(musb);
2083         musb_generic_disable(musb);
2084 
2085         /* Init IRQ workqueue before request_irq */
2086         INIT_WORK(&musb->irq_work, musb_irq_work);
2087         INIT_DELAYED_WORK(&musb->recover_work, musb_recover_work);
2088         INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2089         INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2090 
2091         /* setup musb parts of the core (especially endpoints) */
2092         status = musb_core_init(plat->config->multipoint
2093                         ? MUSB_CONTROLLER_MHDRC
2094                         : MUSB_CONTROLLER_HDRC, musb);
2095         if (status < 0)
2096                 goto fail3;
2097 
2098         setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2099 
2100         /* attach to the IRQ */
2101         if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2102                 dev_err(dev, "request_irq %d failed!\n", nIrq);
2103                 status = -ENODEV;
2104                 goto fail3;
2105         }
2106         musb->nIrq = nIrq;
2107         /* FIXME this handles wakeup irqs wrong */
2108         if (enable_irq_wake(nIrq) == 0) {
2109                 musb->irq_wake = 1;
2110                 device_init_wakeup(dev, 1);
2111         } else {
2112                 musb->irq_wake = 0;
2113         }
2114 
2115         /* program PHY to use external vBus if required */
2116         if (plat->extvbus) {
2117                 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2118                 busctl |= MUSB_ULPI_USE_EXTVBUS;
2119                 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2120         }
2121 
2122         if (musb->xceiv->otg->default_a) {
2123                 MUSB_HST_MODE(musb);
2124                 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2125         } else {
2126                 MUSB_DEV_MODE(musb);
2127                 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2128         }
2129 
2130         switch (musb->port_mode) {
2131         case MUSB_PORT_MODE_HOST:
2132                 status = musb_host_setup(musb, plat->power);
2133                 if (status < 0)
2134                         goto fail3;
2135                 status = musb_platform_set_mode(musb, MUSB_HOST);
2136                 break;
2137         case MUSB_PORT_MODE_GADGET:
2138                 status = musb_gadget_setup(musb);
2139                 if (status < 0)
2140                         goto fail3;
2141                 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2142                 break;
2143         case MUSB_PORT_MODE_DUAL_ROLE:
2144                 status = musb_host_setup(musb, plat->power);
2145                 if (status < 0)
2146                         goto fail3;
2147                 status = musb_gadget_setup(musb);
2148                 if (status) {
2149                         musb_host_cleanup(musb);
2150                         goto fail3;
2151                 }
2152                 status = musb_platform_set_mode(musb, MUSB_OTG);
2153                 break;
2154         default:
2155                 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2156                 break;
2157         }
2158 
2159         if (status < 0)
2160                 goto fail3;
2161 
2162         status = musb_init_debugfs(musb);
2163         if (status < 0)
2164                 goto fail4;
2165 
2166         status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2167         if (status)
2168                 goto fail5;
2169 
2170         pm_runtime_put(musb->controller);
2171 
2172         return 0;
2173 
2174 fail5:
2175         musb_exit_debugfs(musb);
2176 
2177 fail4:
2178         musb_gadget_cleanup(musb);
2179         musb_host_cleanup(musb);
2180 
2181 fail3:
2182         cancel_work_sync(&musb->irq_work);
2183         cancel_delayed_work_sync(&musb->recover_work);
2184         cancel_delayed_work_sync(&musb->finish_resume_work);
2185         cancel_delayed_work_sync(&musb->deassert_reset_work);
2186         if (musb->dma_controller)
2187                 dma_controller_destroy(musb->dma_controller);
2188 fail2_5:
2189         pm_runtime_put_sync(musb->controller);
2190 
2191 fail2:
2192         if (musb->irq_wake)
2193                 device_init_wakeup(dev, 0);
2194         musb_platform_exit(musb);
2195 
2196 fail1:
2197         pm_runtime_disable(musb->controller);
2198         dev_err(musb->controller,
2199                 "musb_init_controller failed with status %d\n", status);
2200 
2201         musb_free(musb);
2202 
2203 fail0:
2204 
2205         return status;
2206 
2207 }
2208 
2209 /*-------------------------------------------------------------------------*/
2210 
2211 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2212  * bridge to a platform device; this driver then suffices.
2213  */
2214 static int musb_probe(struct platform_device *pdev)
2215 {
2216         struct device   *dev = &pdev->dev;
2217         int             irq = platform_get_irq_byname(pdev, "mc");
2218         struct resource *iomem;
2219         void __iomem    *base;
2220 
2221         if (irq <= 0)
2222                 return -ENODEV;
2223 
2224         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2225         base = devm_ioremap_resource(dev, iomem);
2226         if (IS_ERR(base))
2227                 return PTR_ERR(base);
2228 
2229         return musb_init_controller(dev, irq, base);
2230 }
2231 
2232 static int musb_remove(struct platform_device *pdev)
2233 {
2234         struct device   *dev = &pdev->dev;
2235         struct musb     *musb = dev_to_musb(dev);
2236 
2237         /* this gets called on rmmod.
2238          *  - Host mode: host may still be active
2239          *  - Peripheral mode: peripheral is deactivated (or never-activated)
2240          *  - OTG mode: both roles are deactivated (or never-activated)
2241          */
2242         musb_exit_debugfs(musb);
2243         musb_shutdown(pdev);
2244 
2245         if (musb->dma_controller)
2246                 dma_controller_destroy(musb->dma_controller);
2247 
2248         cancel_work_sync(&musb->irq_work);
2249         cancel_delayed_work_sync(&musb->recover_work);
2250         cancel_delayed_work_sync(&musb->finish_resume_work);
2251         cancel_delayed_work_sync(&musb->deassert_reset_work);
2252         musb_free(musb);
2253         device_init_wakeup(dev, 0);
2254         return 0;
2255 }
2256 
2257 #ifdef  CONFIG_PM
2258 
2259 static void musb_save_context(struct musb *musb)
2260 {
2261         int i;
2262         void __iomem *musb_base = musb->mregs;
2263         void __iomem *epio;
2264 
2265         musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2266         musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2267         musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2268         musb->context.power = musb_readb(musb_base, MUSB_POWER);
2269         musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2270         musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2271         musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2272 
2273         for (i = 0; i < musb->config->num_eps; ++i) {
2274                 struct musb_hw_ep       *hw_ep;
2275 
2276                 hw_ep = &musb->endpoints[i];
2277                 if (!hw_ep)
2278                         continue;
2279 
2280                 epio = hw_ep->regs;
2281                 if (!epio)
2282                         continue;
2283 
2284                 musb_writeb(musb_base, MUSB_INDEX, i);
2285                 musb->context.index_regs[i].txmaxp =
2286                         musb_readw(epio, MUSB_TXMAXP);
2287                 musb->context.index_regs[i].txcsr =
2288                         musb_readw(epio, MUSB_TXCSR);
2289                 musb->context.index_regs[i].rxmaxp =
2290                         musb_readw(epio, MUSB_RXMAXP);
2291                 musb->context.index_regs[i].rxcsr =
2292                         musb_readw(epio, MUSB_RXCSR);
2293 
2294                 if (musb->dyn_fifo) {
2295                         musb->context.index_regs[i].txfifoadd =
2296                                         musb_read_txfifoadd(musb_base);
2297                         musb->context.index_regs[i].rxfifoadd =
2298                                         musb_read_rxfifoadd(musb_base);
2299                         musb->context.index_regs[i].txfifosz =
2300                                         musb_read_txfifosz(musb_base);
2301                         musb->context.index_regs[i].rxfifosz =
2302                                         musb_read_rxfifosz(musb_base);
2303                 }
2304 
2305                 musb->context.index_regs[i].txtype =
2306                         musb_readb(epio, MUSB_TXTYPE);
2307                 musb->context.index_regs[i].txinterval =
2308                         musb_readb(epio, MUSB_TXINTERVAL);
2309                 musb->context.index_regs[i].rxtype =
2310                         musb_readb(epio, MUSB_RXTYPE);
2311                 musb->context.index_regs[i].rxinterval =
2312                         musb_readb(epio, MUSB_RXINTERVAL);
2313 
2314                 musb->context.index_regs[i].txfunaddr =
2315                         musb_read_txfunaddr(musb_base, i);
2316                 musb->context.index_regs[i].txhubaddr =
2317                         musb_read_txhubaddr(musb_base, i);
2318                 musb->context.index_regs[i].txhubport =
2319                         musb_read_txhubport(musb_base, i);
2320 
2321                 musb->context.index_regs[i].rxfunaddr =
2322                         musb_read_rxfunaddr(musb_base, i);
2323                 musb->context.index_regs[i].rxhubaddr =
2324                         musb_read_rxhubaddr(musb_base, i);
2325                 musb->context.index_regs[i].rxhubport =
2326                         musb_read_rxhubport(musb_base, i);
2327         }
2328 }
2329 
2330 static void musb_restore_context(struct musb *musb)
2331 {
2332         int i;
2333         void __iomem *musb_base = musb->mregs;
2334         void __iomem *ep_target_regs;
2335         void __iomem *epio;
2336         u8 power;
2337 
2338         musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2339         musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2340         musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2341 
2342         /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2343         power = musb_readb(musb_base, MUSB_POWER);
2344         power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2345         musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2346         power |= musb->context.power;
2347         musb_writeb(musb_base, MUSB_POWER, power);
2348 
2349         musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2350         musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2351         musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2352         musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2353 
2354         for (i = 0; i < musb->config->num_eps; ++i) {
2355                 struct musb_hw_ep       *hw_ep;
2356 
2357                 hw_ep = &musb->endpoints[i];
2358                 if (!hw_ep)
2359                         continue;
2360 
2361                 epio = hw_ep->regs;
2362                 if (!epio)
2363                         continue;
2364 
2365                 musb_writeb(musb_base, MUSB_INDEX, i);
2366                 musb_writew(epio, MUSB_TXMAXP,
2367                         musb->context.index_regs[i].txmaxp);
2368                 musb_writew(epio, MUSB_TXCSR,
2369                         musb->context.index_regs[i].txcsr);
2370                 musb_writew(epio, MUSB_RXMAXP,
2371                         musb->context.index_regs[i].rxmaxp);
2372                 musb_writew(epio, MUSB_RXCSR,
2373                         musb->context.index_regs[i].rxcsr);
2374 
2375                 if (musb->dyn_fifo) {
2376                         musb_write_txfifosz(musb_base,
2377                                 musb->context.index_regs[i].txfifosz);
2378                         musb_write_rxfifosz(musb_base,
2379                                 musb->context.index_regs[i].rxfifosz);
2380                         musb_write_txfifoadd(musb_base,
2381                                 musb->context.index_regs[i].txfifoadd);
2382                         musb_write_rxfifoadd(musb_base,
2383                                 musb->context.index_regs[i].rxfifoadd);
2384                 }
2385 
2386                 musb_writeb(epio, MUSB_TXTYPE,
2387                                 musb->context.index_regs[i].txtype);
2388                 musb_writeb(epio, MUSB_TXINTERVAL,
2389                                 musb->context.index_regs[i].txinterval);
2390                 musb_writeb(epio, MUSB_RXTYPE,
2391                                 musb->context.index_regs[i].rxtype);
2392                 musb_writeb(epio, MUSB_RXINTERVAL,
2393 
2394                                 musb->context.index_regs[i].rxinterval);
2395                 musb_write_txfunaddr(musb_base, i,
2396                                 musb->context.index_regs[i].txfunaddr);
2397                 musb_write_txhubaddr(musb_base, i,
2398                                 musb->context.index_regs[i].txhubaddr);
2399                 musb_write_txhubport(musb_base, i,
2400                                 musb->context.index_regs[i].txhubport);
2401 
2402                 ep_target_regs =
2403                         musb_read_target_reg_base(i, musb_base);
2404 
2405                 musb_write_rxfunaddr(ep_target_regs,
2406                                 musb->context.index_regs[i].rxfunaddr);
2407                 musb_write_rxhubaddr(ep_target_regs,
2408                                 musb->context.index_regs[i].rxhubaddr);
2409                 musb_write_rxhubport(ep_target_regs,
2410                                 musb->context.index_regs[i].rxhubport);
2411         }
2412         musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2413 }
2414 
2415 static int musb_suspend(struct device *dev)
2416 {
2417         struct musb     *musb = dev_to_musb(dev);
2418         unsigned long   flags;
2419 
2420         spin_lock_irqsave(&musb->lock, flags);
2421 
2422         if (is_peripheral_active(musb)) {
2423                 /* FIXME force disconnect unless we know USB will wake
2424                  * the system up quickly enough to respond ...
2425                  */
2426         } else if (is_host_active(musb)) {
2427                 /* we know all the children are suspended; sometimes
2428                  * they will even be wakeup-enabled.
2429                  */
2430         }
2431 
2432         musb_save_context(musb);
2433 
2434         spin_unlock_irqrestore(&musb->lock, flags);
2435         return 0;
2436 }
2437 
2438 static int musb_resume(struct device *dev)
2439 {
2440         struct musb     *musb = dev_to_musb(dev);
2441         u8              devctl;
2442         u8              mask;
2443 
2444         /*
2445          * For static cmos like DaVinci, register values were preserved
2446          * unless for some reason the whole soc powered down or the USB
2447          * module got reset through the PSC (vs just being disabled).
2448          *
2449          * For the DSPS glue layer though, a full register restore has to
2450          * be done. As it shouldn't harm other platforms, we do it
2451          * unconditionally.
2452          */
2453 
2454         musb_restore_context(musb);
2455 
2456         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2457         mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2458         if ((devctl & mask) != (musb->context.devctl & mask))
2459                 musb->port1_status = 0;
2460         if (musb->need_finish_resume) {
2461                 musb->need_finish_resume = 0;
2462                 schedule_delayed_work(&musb->finish_resume_work,
2463                                       msecs_to_jiffies(20));
2464         }
2465 
2466         /*
2467          * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2468          * out of suspend
2469          */
2470         pm_runtime_disable(dev);
2471         pm_runtime_set_active(dev);
2472         pm_runtime_enable(dev);
2473         return 0;
2474 }
2475 
2476 static int musb_runtime_suspend(struct device *dev)
2477 {
2478         struct musb     *musb = dev_to_musb(dev);
2479 
2480         musb_save_context(musb);
2481 
2482         return 0;
2483 }
2484 
2485 static int musb_runtime_resume(struct device *dev)
2486 {
2487         struct musb     *musb = dev_to_musb(dev);
2488         static int      first = 1;
2489 
2490         /*
2491          * When pm_runtime_get_sync called for the first time in driver
2492          * init,  some of the structure is still not initialized which is
2493          * used in restore function. But clock needs to be
2494          * enabled before any register access, so
2495          * pm_runtime_get_sync has to be called.
2496          * Also context restore without save does not make
2497          * any sense
2498          */
2499         if (!first)
2500                 musb_restore_context(musb);
2501         first = 0;
2502 
2503         return 0;
2504 }
2505 
2506 static const struct dev_pm_ops musb_dev_pm_ops = {
2507         .suspend        = musb_suspend,
2508         .resume         = musb_resume,
2509         .runtime_suspend = musb_runtime_suspend,
2510         .runtime_resume = musb_runtime_resume,
2511 };
2512 
2513 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2514 #else
2515 #define MUSB_DEV_PM_OPS NULL
2516 #endif
2517 
2518 static struct platform_driver musb_driver = {
2519         .driver = {
2520                 .name           = (char *)musb_driver_name,
2521                 .bus            = &platform_bus_type,
2522                 .pm             = MUSB_DEV_PM_OPS,
2523         },
2524         .probe          = musb_probe,
2525         .remove         = musb_remove,
2526         .shutdown       = musb_shutdown,
2527 };
2528 
2529 module_platform_driver(musb_driver);
2530 

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