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Linux/drivers/usb/musb/musb_core.c

  1 /*
  2  * MUSB OTG driver core code
  3  *
  4  * Copyright 2005 Mentor Graphics Corporation
  5  * Copyright (C) 2005-2006 by Texas Instruments
  6  * Copyright (C) 2006-2007 Nokia Corporation
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License
 10  * version 2 as published by the Free Software Foundation.
 11  *
 12  * This program is distributed in the hope that it will be useful, but
 13  * WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 15  * General Public License for more details.
 16  *
 17  * You should have received a copy of the GNU General Public License
 18  * along with this program; if not, write to the Free Software
 19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 20  * 02110-1301 USA
 21  *
 22  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 25  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 32  *
 33  */
 34 
 35 /*
 36  * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
 37  *
 38  * This consists of a Host Controller Driver (HCD) and a peripheral
 39  * controller driver implementing the "Gadget" API; OTG support is
 40  * in the works.  These are normal Linux-USB controller drivers which
 41  * use IRQs and have no dedicated thread.
 42  *
 43  * This version of the driver has only been used with products from
 44  * Texas Instruments.  Those products integrate the Inventra logic
 45  * with other DMA, IRQ, and bus modules, as well as other logic that
 46  * needs to be reflected in this driver.
 47  *
 48  *
 49  * NOTE:  the original Mentor code here was pretty much a collection
 50  * of mechanisms that don't seem to have been fully integrated/working
 51  * for *any* Linux kernel version.  This version aims at Linux 2.6.now,
 52  * Key open issues include:
 53  *
 54  *  - Lack of host-side transaction scheduling, for all transfer types.
 55  *    The hardware doesn't do it; instead, software must.
 56  *
 57  *    This is not an issue for OTG devices that don't support external
 58  *    hubs, but for more "normal" USB hosts it's a user issue that the
 59  *    "multipoint" support doesn't scale in the expected ways.  That
 60  *    includes DaVinci EVM in a common non-OTG mode.
 61  *
 62  *      * Control and bulk use dedicated endpoints, and there's as
 63  *        yet no mechanism to either (a) reclaim the hardware when
 64  *        peripherals are NAKing, which gets complicated with bulk
 65  *        endpoints, or (b) use more than a single bulk endpoint in
 66  *        each direction.
 67  *
 68  *        RESULT:  one device may be perceived as blocking another one.
 69  *
 70  *      * Interrupt and isochronous will dynamically allocate endpoint
 71  *        hardware, but (a) there's no record keeping for bandwidth;
 72  *        (b) in the common case that few endpoints are available, there
 73  *        is no mechanism to reuse endpoints to talk to multiple devices.
 74  *
 75  *        RESULT:  At one extreme, bandwidth can be overcommitted in
 76  *        some hardware configurations, no faults will be reported.
 77  *        At the other extreme, the bandwidth capabilities which do
 78  *        exist tend to be severely undercommitted.  You can't yet hook
 79  *        up both a keyboard and a mouse to an external USB hub.
 80  */
 81 
 82 /*
 83  * This gets many kinds of configuration information:
 84  *      - Kconfig for everything user-configurable
 85  *      - platform_device for addressing, irq, and platform_data
 86  *      - platform_data is mostly for board-specific information
 87  *        (plus recentrly, SOC or family details)
 88  *
 89  * Most of the conditional compilation will (someday) vanish.
 90  */
 91 
 92 #include <linux/module.h>
 93 #include <linux/kernel.h>
 94 #include <linux/sched.h>
 95 #include <linux/slab.h>
 96 #include <linux/list.h>
 97 #include <linux/kobject.h>
 98 #include <linux/prefetch.h>
 99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102 
103 #include "musb_core.h"
104 
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106 
107 
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110 
111 #define MUSB_VERSION "6.0"
112 
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114 
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117 
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122 
123 
124 /*-------------------------------------------------------------------------*/
125 
126 static inline struct musb *dev_to_musb(struct device *dev)
127 {
128         return dev_get_drvdata(dev);
129 }
130 
131 /*-------------------------------------------------------------------------*/
132 
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
135 {
136         void __iomem *addr = phy->io_priv;
137         int     i = 0;
138         u8      r;
139         u8      power;
140         int     ret;
141 
142         pm_runtime_get_sync(phy->io_dev);
143 
144         /* Make sure the transceiver is not in low power mode */
145         power = musb_readb(addr, MUSB_POWER);
146         power &= ~MUSB_POWER_SUSPENDM;
147         musb_writeb(addr, MUSB_POWER, power);
148 
149         /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150          * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151          */
152 
153         musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154         musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155                         MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156 
157         while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158                                 & MUSB_ULPI_REG_CMPLT)) {
159                 i++;
160                 if (i == 10000) {
161                         ret = -ETIMEDOUT;
162                         goto out;
163                 }
164 
165         }
166         r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167         r &= ~MUSB_ULPI_REG_CMPLT;
168         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169 
170         ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171 
172 out:
173         pm_runtime_put(phy->io_dev);
174 
175         return ret;
176 }
177 
178 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
179 {
180         void __iomem *addr = phy->io_priv;
181         int     i = 0;
182         u8      r = 0;
183         u8      power;
184         int     ret = 0;
185 
186         pm_runtime_get_sync(phy->io_dev);
187 
188         /* Make sure the transceiver is not in low power mode */
189         power = musb_readb(addr, MUSB_POWER);
190         power &= ~MUSB_POWER_SUSPENDM;
191         musb_writeb(addr, MUSB_POWER, power);
192 
193         musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194         musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196 
197         while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198                                 & MUSB_ULPI_REG_CMPLT)) {
199                 i++;
200                 if (i == 10000) {
201                         ret = -ETIMEDOUT;
202                         goto out;
203                 }
204         }
205 
206         r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207         r &= ~MUSB_ULPI_REG_CMPLT;
208         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209 
210 out:
211         pm_runtime_put(phy->io_dev);
212 
213         return ret;
214 }
215 #else
216 #define musb_ulpi_read          NULL
217 #define musb_ulpi_write         NULL
218 #endif
219 
220 static struct usb_phy_io_ops musb_ulpi_access = {
221         .read = musb_ulpi_read,
222         .write = musb_ulpi_write,
223 };
224 
225 /*-------------------------------------------------------------------------*/
226 
227 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
228 
229 /*
230  * Load an endpoint's FIFO
231  */
232 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
233 {
234         struct musb *musb = hw_ep->musb;
235         void __iomem *fifo = hw_ep->fifo;
236 
237         if (unlikely(len == 0))
238                 return;
239 
240         prefetch((u8 *)src);
241 
242         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
243                         'T', hw_ep->epnum, fifo, len, src);
244 
245         /* we can't assume unaligned reads work */
246         if (likely((0x01 & (unsigned long) src) == 0)) {
247                 u16     index = 0;
248 
249                 /* best case is 32bit-aligned source address */
250                 if ((0x02 & (unsigned long) src) == 0) {
251                         if (len >= 4) {
252                                 iowrite32_rep(fifo, src + index, len >> 2);
253                                 index += len & ~0x03;
254                         }
255                         if (len & 0x02) {
256                                 musb_writew(fifo, 0, *(u16 *)&src[index]);
257                                 index += 2;
258                         }
259                 } else {
260                         if (len >= 2) {
261                                 iowrite16_rep(fifo, src + index, len >> 1);
262                                 index += len & ~0x01;
263                         }
264                 }
265                 if (len & 0x01)
266                         musb_writeb(fifo, 0, src[index]);
267         } else  {
268                 /* byte aligned */
269                 iowrite8_rep(fifo, src, len);
270         }
271 }
272 
273 #if !defined(CONFIG_USB_MUSB_AM35X)
274 /*
275  * Unload an endpoint's FIFO
276  */
277 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
278 {
279         struct musb *musb = hw_ep->musb;
280         void __iomem *fifo = hw_ep->fifo;
281 
282         if (unlikely(len == 0))
283                 return;
284 
285         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
286                         'R', hw_ep->epnum, fifo, len, dst);
287 
288         /* we can't assume unaligned writes work */
289         if (likely((0x01 & (unsigned long) dst) == 0)) {
290                 u16     index = 0;
291 
292                 /* best case is 32bit-aligned destination address */
293                 if ((0x02 & (unsigned long) dst) == 0) {
294                         if (len >= 4) {
295                                 ioread32_rep(fifo, dst, len >> 2);
296                                 index = len & ~0x03;
297                         }
298                         if (len & 0x02) {
299                                 *(u16 *)&dst[index] = musb_readw(fifo, 0);
300                                 index += 2;
301                         }
302                 } else {
303                         if (len >= 2) {
304                                 ioread16_rep(fifo, dst, len >> 1);
305                                 index = len & ~0x01;
306                         }
307                 }
308                 if (len & 0x01)
309                         dst[index] = musb_readb(fifo, 0);
310         } else  {
311                 /* byte aligned */
312                 ioread8_rep(fifo, dst, len);
313         }
314 }
315 #endif
316 
317 #endif  /* normal PIO */
318 
319 
320 /*-------------------------------------------------------------------------*/
321 
322 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
323 static const u8 musb_test_packet[53] = {
324         /* implicit SYNC then DATA0 to start */
325 
326         /* JKJKJKJK x9 */
327         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
328         /* JJKKJJKK x8 */
329         0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
330         /* JJJJKKKK x8 */
331         0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
332         /* JJJJJJJKKKKKKK x8 */
333         0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
334         /* JJJJJJJK x8 */
335         0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
336         /* JKKKKKKK x10, JK */
337         0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
338 
339         /* implicit CRC16 then EOP to end */
340 };
341 
342 void musb_load_testpacket(struct musb *musb)
343 {
344         void __iomem    *regs = musb->endpoints[0].regs;
345 
346         musb_ep_select(musb->mregs, 0);
347         musb_write_fifo(musb->control_ep,
348                         sizeof(musb_test_packet), musb_test_packet);
349         musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
350 }
351 
352 /*-------------------------------------------------------------------------*/
353 
354 /*
355  * Handles OTG hnp timeouts, such as b_ase0_brst
356  */
357 static void musb_otg_timer_func(unsigned long data)
358 {
359         struct musb     *musb = (struct musb *)data;
360         unsigned long   flags;
361 
362         spin_lock_irqsave(&musb->lock, flags);
363         switch (musb->xceiv->state) {
364         case OTG_STATE_B_WAIT_ACON:
365                 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
366                 musb_g_disconnect(musb);
367                 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
368                 musb->is_active = 0;
369                 break;
370         case OTG_STATE_A_SUSPEND:
371         case OTG_STATE_A_WAIT_BCON:
372                 dev_dbg(musb->controller, "HNP: %s timeout\n",
373                         usb_otg_state_string(musb->xceiv->state));
374                 musb_platform_set_vbus(musb, 0);
375                 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
376                 break;
377         default:
378                 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
379                         usb_otg_state_string(musb->xceiv->state));
380         }
381         spin_unlock_irqrestore(&musb->lock, flags);
382 }
383 
384 /*
385  * Stops the HNP transition. Caller must take care of locking.
386  */
387 void musb_hnp_stop(struct musb *musb)
388 {
389         struct usb_hcd  *hcd = musb->hcd;
390         void __iomem    *mbase = musb->mregs;
391         u8      reg;
392 
393         dev_dbg(musb->controller, "HNP: stop from %s\n",
394                         usb_otg_state_string(musb->xceiv->state));
395 
396         switch (musb->xceiv->state) {
397         case OTG_STATE_A_PERIPHERAL:
398                 musb_g_disconnect(musb);
399                 dev_dbg(musb->controller, "HNP: back to %s\n",
400                         usb_otg_state_string(musb->xceiv->state));
401                 break;
402         case OTG_STATE_B_HOST:
403                 dev_dbg(musb->controller, "HNP: Disabling HR\n");
404                 if (hcd)
405                         hcd->self.is_b_host = 0;
406                 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
407                 MUSB_DEV_MODE(musb);
408                 reg = musb_readb(mbase, MUSB_POWER);
409                 reg |= MUSB_POWER_SUSPENDM;
410                 musb_writeb(mbase, MUSB_POWER, reg);
411                 /* REVISIT: Start SESSION_REQUEST here? */
412                 break;
413         default:
414                 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
415                         usb_otg_state_string(musb->xceiv->state));
416         }
417 
418         /*
419          * When returning to A state after HNP, avoid hub_port_rebounce(),
420          * which cause occasional OPT A "Did not receive reset after connect"
421          * errors.
422          */
423         musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
424 }
425 
426 /*
427  * Interrupt Service Routine to record USB "global" interrupts.
428  * Since these do not happen often and signify things of
429  * paramount importance, it seems OK to check them individually;
430  * the order of the tests is specified in the manual
431  *
432  * @param musb instance pointer
433  * @param int_usb register contents
434  * @param devctl
435  * @param power
436  */
437 
438 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
439                                 u8 devctl)
440 {
441         irqreturn_t handled = IRQ_NONE;
442 
443         dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
444                 int_usb);
445 
446         /* in host mode, the peripheral may issue remote wakeup.
447          * in peripheral mode, the host may resume the link.
448          * spurious RESUME irqs happen too, paired with SUSPEND.
449          */
450         if (int_usb & MUSB_INTR_RESUME) {
451                 handled = IRQ_HANDLED;
452                 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->state));
453 
454                 if (devctl & MUSB_DEVCTL_HM) {
455                         void __iomem *mbase = musb->mregs;
456                         u8 power;
457 
458                         switch (musb->xceiv->state) {
459                         case OTG_STATE_A_SUSPEND:
460                                 /* remote wakeup?  later, GetPortStatus
461                                  * will stop RESUME signaling
462                                  */
463 
464                                 power = musb_readb(musb->mregs, MUSB_POWER);
465                                 if (power & MUSB_POWER_SUSPENDM) {
466                                         /* spurious */
467                                         musb->int_usb &= ~MUSB_INTR_SUSPEND;
468                                         dev_dbg(musb->controller, "Spurious SUSPENDM\n");
469                                         break;
470                                 }
471 
472                                 power &= ~MUSB_POWER_SUSPENDM;
473                                 musb_writeb(mbase, MUSB_POWER,
474                                                 power | MUSB_POWER_RESUME);
475 
476                                 musb->port1_status |=
477                                                 (USB_PORT_STAT_C_SUSPEND << 16)
478                                                 | MUSB_PORT_STAT_RESUME;
479                                 musb->rh_timer = jiffies
480                                                  + msecs_to_jiffies(20);
481                                 schedule_delayed_work(
482                                         &musb->finish_resume_work,
483                                         msecs_to_jiffies(20));
484 
485                                 musb->xceiv->state = OTG_STATE_A_HOST;
486                                 musb->is_active = 1;
487                                 musb_host_resume_root_hub(musb);
488                                 break;
489                         case OTG_STATE_B_WAIT_ACON:
490                                 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
491                                 musb->is_active = 1;
492                                 MUSB_DEV_MODE(musb);
493                                 break;
494                         default:
495                                 WARNING("bogus %s RESUME (%s)\n",
496                                         "host",
497                                         usb_otg_state_string(musb->xceiv->state));
498                         }
499                 } else {
500                         switch (musb->xceiv->state) {
501                         case OTG_STATE_A_SUSPEND:
502                                 /* possibly DISCONNECT is upcoming */
503                                 musb->xceiv->state = OTG_STATE_A_HOST;
504                                 musb_host_resume_root_hub(musb);
505                                 break;
506                         case OTG_STATE_B_WAIT_ACON:
507                         case OTG_STATE_B_PERIPHERAL:
508                                 /* disconnect while suspended?  we may
509                                  * not get a disconnect irq...
510                                  */
511                                 if ((devctl & MUSB_DEVCTL_VBUS)
512                                                 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
513                                                 ) {
514                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
515                                         musb->int_usb &= ~MUSB_INTR_SUSPEND;
516                                         break;
517                                 }
518                                 musb_g_resume(musb);
519                                 break;
520                         case OTG_STATE_B_IDLE:
521                                 musb->int_usb &= ~MUSB_INTR_SUSPEND;
522                                 break;
523                         default:
524                                 WARNING("bogus %s RESUME (%s)\n",
525                                         "peripheral",
526                                         usb_otg_state_string(musb->xceiv->state));
527                         }
528                 }
529         }
530 
531         /* see manual for the order of the tests */
532         if (int_usb & MUSB_INTR_SESSREQ) {
533                 void __iomem *mbase = musb->mregs;
534 
535                 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
536                                 && (devctl & MUSB_DEVCTL_BDEVICE)) {
537                         dev_dbg(musb->controller, "SessReq while on B state\n");
538                         return IRQ_HANDLED;
539                 }
540 
541                 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
542                         usb_otg_state_string(musb->xceiv->state));
543 
544                 /* IRQ arrives from ID pin sense or (later, if VBUS power
545                  * is removed) SRP.  responses are time critical:
546                  *  - turn on VBUS (with silicon-specific mechanism)
547                  *  - go through A_WAIT_VRISE
548                  *  - ... to A_WAIT_BCON.
549                  * a_wait_vrise_tmout triggers VBUS_ERROR transitions
550                  */
551                 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
552                 musb->ep0_stage = MUSB_EP0_START;
553                 musb->xceiv->state = OTG_STATE_A_IDLE;
554                 MUSB_HST_MODE(musb);
555                 musb_platform_set_vbus(musb, 1);
556 
557                 handled = IRQ_HANDLED;
558         }
559 
560         if (int_usb & MUSB_INTR_VBUSERROR) {
561                 int     ignore = 0;
562 
563                 /* During connection as an A-Device, we may see a short
564                  * current spikes causing voltage drop, because of cable
565                  * and peripheral capacitance combined with vbus draw.
566                  * (So: less common with truly self-powered devices, where
567                  * vbus doesn't act like a power supply.)
568                  *
569                  * Such spikes are short; usually less than ~500 usec, max
570                  * of ~2 msec.  That is, they're not sustained overcurrent
571                  * errors, though they're reported using VBUSERROR irqs.
572                  *
573                  * Workarounds:  (a) hardware: use self powered devices.
574                  * (b) software:  ignore non-repeated VBUS errors.
575                  *
576                  * REVISIT:  do delays from lots of DEBUG_KERNEL checks
577                  * make trouble here, keeping VBUS < 4.4V ?
578                  */
579                 switch (musb->xceiv->state) {
580                 case OTG_STATE_A_HOST:
581                         /* recovery is dicey once we've gotten past the
582                          * initial stages of enumeration, but if VBUS
583                          * stayed ok at the other end of the link, and
584                          * another reset is due (at least for high speed,
585                          * to redo the chirp etc), it might work OK...
586                          */
587                 case OTG_STATE_A_WAIT_BCON:
588                 case OTG_STATE_A_WAIT_VRISE:
589                         if (musb->vbuserr_retry) {
590                                 void __iomem *mbase = musb->mregs;
591 
592                                 musb->vbuserr_retry--;
593                                 ignore = 1;
594                                 devctl |= MUSB_DEVCTL_SESSION;
595                                 musb_writeb(mbase, MUSB_DEVCTL, devctl);
596                         } else {
597                                 musb->port1_status |=
598                                           USB_PORT_STAT_OVERCURRENT
599                                         | (USB_PORT_STAT_C_OVERCURRENT << 16);
600                         }
601                         break;
602                 default:
603                         break;
604                 }
605 
606                 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
607                                 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
608                                 usb_otg_state_string(musb->xceiv->state),
609                                 devctl,
610                                 ({ char *s;
611                                 switch (devctl & MUSB_DEVCTL_VBUS) {
612                                 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
613                                         s = "<SessEnd"; break;
614                                 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
615                                         s = "<AValid"; break;
616                                 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
617                                         s = "<VBusValid"; break;
618                                 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
619                                 default:
620                                         s = "VALID"; break;
621                                 } s; }),
622                                 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
623                                 musb->port1_status);
624 
625                 /* go through A_WAIT_VFALL then start a new session */
626                 if (!ignore)
627                         musb_platform_set_vbus(musb, 0);
628                 handled = IRQ_HANDLED;
629         }
630 
631         if (int_usb & MUSB_INTR_SUSPEND) {
632                 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
633                         usb_otg_state_string(musb->xceiv->state), devctl);
634                 handled = IRQ_HANDLED;
635 
636                 switch (musb->xceiv->state) {
637                 case OTG_STATE_A_PERIPHERAL:
638                         /* We also come here if the cable is removed, since
639                          * this silicon doesn't report ID-no-longer-grounded.
640                          *
641                          * We depend on T(a_wait_bcon) to shut us down, and
642                          * hope users don't do anything dicey during this
643                          * undesired detour through A_WAIT_BCON.
644                          */
645                         musb_hnp_stop(musb);
646                         musb_host_resume_root_hub(musb);
647                         musb_root_disconnect(musb);
648                         musb_platform_try_idle(musb, jiffies
649                                         + msecs_to_jiffies(musb->a_wait_bcon
650                                                 ? : OTG_TIME_A_WAIT_BCON));
651 
652                         break;
653                 case OTG_STATE_B_IDLE:
654                         if (!musb->is_active)
655                                 break;
656                 case OTG_STATE_B_PERIPHERAL:
657                         musb_g_suspend(musb);
658                         musb->is_active = musb->g.b_hnp_enable;
659                         if (musb->is_active) {
660                                 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
661                                 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
662                                 mod_timer(&musb->otg_timer, jiffies
663                                         + msecs_to_jiffies(
664                                                         OTG_TIME_B_ASE0_BRST));
665                         }
666                         break;
667                 case OTG_STATE_A_WAIT_BCON:
668                         if (musb->a_wait_bcon != 0)
669                                 musb_platform_try_idle(musb, jiffies
670                                         + msecs_to_jiffies(musb->a_wait_bcon));
671                         break;
672                 case OTG_STATE_A_HOST:
673                         musb->xceiv->state = OTG_STATE_A_SUSPEND;
674                         musb->is_active = musb->hcd->self.b_hnp_enable;
675                         break;
676                 case OTG_STATE_B_HOST:
677                         /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
678                         dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
679                         break;
680                 default:
681                         /* "should not happen" */
682                         musb->is_active = 0;
683                         break;
684                 }
685         }
686 
687         if (int_usb & MUSB_INTR_CONNECT) {
688                 struct usb_hcd *hcd = musb->hcd;
689 
690                 handled = IRQ_HANDLED;
691                 musb->is_active = 1;
692 
693                 musb->ep0_stage = MUSB_EP0_START;
694 
695                 /* flush endpoints when transitioning from Device Mode */
696                 if (is_peripheral_active(musb)) {
697                         /* REVISIT HNP; just force disconnect */
698                 }
699                 musb->intrtxe = musb->epmask;
700                 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
701                 musb->intrrxe = musb->epmask & 0xfffe;
702                 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
703                 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
704                 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
705                                         |USB_PORT_STAT_HIGH_SPEED
706                                         |USB_PORT_STAT_ENABLE
707                                         );
708                 musb->port1_status |= USB_PORT_STAT_CONNECTION
709                                         |(USB_PORT_STAT_C_CONNECTION << 16);
710 
711                 /* high vs full speed is just a guess until after reset */
712                 if (devctl & MUSB_DEVCTL_LSDEV)
713                         musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
714 
715                 /* indicate new connection to OTG machine */
716                 switch (musb->xceiv->state) {
717                 case OTG_STATE_B_PERIPHERAL:
718                         if (int_usb & MUSB_INTR_SUSPEND) {
719                                 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
720                                 int_usb &= ~MUSB_INTR_SUSPEND;
721                                 goto b_host;
722                         } else
723                                 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
724                         break;
725                 case OTG_STATE_B_WAIT_ACON:
726                         dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
727 b_host:
728                         musb->xceiv->state = OTG_STATE_B_HOST;
729                         if (musb->hcd)
730                                 musb->hcd->self.is_b_host = 1;
731                         del_timer(&musb->otg_timer);
732                         break;
733                 default:
734                         if ((devctl & MUSB_DEVCTL_VBUS)
735                                         == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
736                                 musb->xceiv->state = OTG_STATE_A_HOST;
737                                 if (hcd)
738                                         hcd->self.is_b_host = 0;
739                         }
740                         break;
741                 }
742 
743                 musb_host_poke_root_hub(musb);
744 
745                 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
746                                 usb_otg_state_string(musb->xceiv->state), devctl);
747         }
748 
749         if (int_usb & MUSB_INTR_DISCONNECT) {
750                 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
751                                 usb_otg_state_string(musb->xceiv->state),
752                                 MUSB_MODE(musb), devctl);
753                 handled = IRQ_HANDLED;
754 
755                 switch (musb->xceiv->state) {
756                 case OTG_STATE_A_HOST:
757                 case OTG_STATE_A_SUSPEND:
758                         musb_host_resume_root_hub(musb);
759                         musb_root_disconnect(musb);
760                         if (musb->a_wait_bcon != 0)
761                                 musb_platform_try_idle(musb, jiffies
762                                         + msecs_to_jiffies(musb->a_wait_bcon));
763                         break;
764                 case OTG_STATE_B_HOST:
765                         /* REVISIT this behaves for "real disconnect"
766                          * cases; make sure the other transitions from
767                          * from B_HOST act right too.  The B_HOST code
768                          * in hnp_stop() is currently not used...
769                          */
770                         musb_root_disconnect(musb);
771                         if (musb->hcd)
772                                 musb->hcd->self.is_b_host = 0;
773                         musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
774                         MUSB_DEV_MODE(musb);
775                         musb_g_disconnect(musb);
776                         break;
777                 case OTG_STATE_A_PERIPHERAL:
778                         musb_hnp_stop(musb);
779                         musb_root_disconnect(musb);
780                         /* FALLTHROUGH */
781                 case OTG_STATE_B_WAIT_ACON:
782                         /* FALLTHROUGH */
783                 case OTG_STATE_B_PERIPHERAL:
784                 case OTG_STATE_B_IDLE:
785                         musb_g_disconnect(musb);
786                         break;
787                 default:
788                         WARNING("unhandled DISCONNECT transition (%s)\n",
789                                 usb_otg_state_string(musb->xceiv->state));
790                         break;
791                 }
792         }
793 
794         /* mentor saves a bit: bus reset and babble share the same irq.
795          * only host sees babble; only peripheral sees bus reset.
796          */
797         if (int_usb & MUSB_INTR_RESET) {
798                 handled = IRQ_HANDLED;
799                 if ((devctl & MUSB_DEVCTL_HM) != 0) {
800                         /*
801                          * Looks like non-HS BABBLE can be ignored, but
802                          * HS BABBLE is an error condition. For HS the solution
803                          * is to avoid babble in the first place and fix what
804                          * caused BABBLE. When HS BABBLE happens we can only
805                          * stop the session.
806                          */
807                         if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
808                                 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
809                         else {
810                                 ERR("Stopping host session -- babble\n");
811                                 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
812                         }
813                 } else {
814                         dev_dbg(musb->controller, "BUS RESET as %s\n",
815                                 usb_otg_state_string(musb->xceiv->state));
816                         switch (musb->xceiv->state) {
817                         case OTG_STATE_A_SUSPEND:
818                                 musb_g_reset(musb);
819                                 /* FALLTHROUGH */
820                         case OTG_STATE_A_WAIT_BCON:     /* OPT TD.4.7-900ms */
821                                 /* never use invalid T(a_wait_bcon) */
822                                 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
823                                         usb_otg_state_string(musb->xceiv->state),
824                                         TA_WAIT_BCON(musb));
825                                 mod_timer(&musb->otg_timer, jiffies
826                                         + msecs_to_jiffies(TA_WAIT_BCON(musb)));
827                                 break;
828                         case OTG_STATE_A_PERIPHERAL:
829                                 del_timer(&musb->otg_timer);
830                                 musb_g_reset(musb);
831                                 break;
832                         case OTG_STATE_B_WAIT_ACON:
833                                 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
834                                         usb_otg_state_string(musb->xceiv->state));
835                                 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
836                                 musb_g_reset(musb);
837                                 break;
838                         case OTG_STATE_B_IDLE:
839                                 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
840                                 /* FALLTHROUGH */
841                         case OTG_STATE_B_PERIPHERAL:
842                                 musb_g_reset(musb);
843                                 break;
844                         default:
845                                 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
846                                         usb_otg_state_string(musb->xceiv->state));
847                         }
848                 }
849         }
850 
851         /* handle babble condition */
852         if (int_usb & MUSB_INTR_BABBLE && is_host_active(musb))
853                 schedule_work(&musb->recover_work);
854 
855 #if 0
856 /* REVISIT ... this would be for multiplexing periodic endpoints, or
857  * supporting transfer phasing to prevent exceeding ISO bandwidth
858  * limits of a given frame or microframe.
859  *
860  * It's not needed for peripheral side, which dedicates endpoints;
861  * though it _might_ use SOF irqs for other purposes.
862  *
863  * And it's not currently needed for host side, which also dedicates
864  * endpoints, relies on TX/RX interval registers, and isn't claimed
865  * to support ISO transfers yet.
866  */
867         if (int_usb & MUSB_INTR_SOF) {
868                 void __iomem *mbase = musb->mregs;
869                 struct musb_hw_ep       *ep;
870                 u8 epnum;
871                 u16 frame;
872 
873                 dev_dbg(musb->controller, "START_OF_FRAME\n");
874                 handled = IRQ_HANDLED;
875 
876                 /* start any periodic Tx transfers waiting for current frame */
877                 frame = musb_readw(mbase, MUSB_FRAME);
878                 ep = musb->endpoints;
879                 for (epnum = 1; (epnum < musb->nr_endpoints)
880                                         && (musb->epmask >= (1 << epnum));
881                                 epnum++, ep++) {
882                         /*
883                          * FIXME handle framecounter wraps (12 bits)
884                          * eliminate duplicated StartUrb logic
885                          */
886                         if (ep->dwWaitFrame >= frame) {
887                                 ep->dwWaitFrame = 0;
888                                 pr_debug("SOF --> periodic TX%s on %d\n",
889                                         ep->tx_channel ? " DMA" : "",
890                                         epnum);
891                                 if (!ep->tx_channel)
892                                         musb_h_tx_start(musb, epnum);
893                                 else
894                                         cppi_hostdma_start(musb, epnum);
895                         }
896                 }               /* end of for loop */
897         }
898 #endif
899 
900         schedule_work(&musb->irq_work);
901 
902         return handled;
903 }
904 
905 /*-------------------------------------------------------------------------*/
906 
907 static void musb_generic_disable(struct musb *musb)
908 {
909         void __iomem    *mbase = musb->mregs;
910         u16     temp;
911 
912         /* disable interrupts */
913         musb_writeb(mbase, MUSB_INTRUSBE, 0);
914         musb->intrtxe = 0;
915         musb_writew(mbase, MUSB_INTRTXE, 0);
916         musb->intrrxe = 0;
917         musb_writew(mbase, MUSB_INTRRXE, 0);
918 
919         /* off */
920         musb_writeb(mbase, MUSB_DEVCTL, 0);
921 
922         /*  flush pending interrupts */
923         temp = musb_readb(mbase, MUSB_INTRUSB);
924         temp = musb_readw(mbase, MUSB_INTRTX);
925         temp = musb_readw(mbase, MUSB_INTRRX);
926 
927 }
928 
929 /*
930  * Program the HDRC to start (enable interrupts, dma, etc.).
931  */
932 void musb_start(struct musb *musb)
933 {
934         void __iomem    *regs = musb->mregs;
935         u8              devctl = musb_readb(regs, MUSB_DEVCTL);
936 
937         dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
938 
939         /*  Set INT enable registers, enable interrupts */
940         musb->intrtxe = musb->epmask;
941         musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
942         musb->intrrxe = musb->epmask & 0xfffe;
943         musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
944         musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
945 
946         musb_writeb(regs, MUSB_TESTMODE, 0);
947 
948         /* put into basic highspeed mode and start session */
949         musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
950                         | MUSB_POWER_HSENAB
951                         /* ENSUSPEND wedges tusb */
952                         /* | MUSB_POWER_ENSUSPEND */
953                    );
954 
955         musb->is_active = 0;
956         devctl = musb_readb(regs, MUSB_DEVCTL);
957         devctl &= ~MUSB_DEVCTL_SESSION;
958 
959         /* session started after:
960          * (a) ID-grounded irq, host mode;
961          * (b) vbus present/connect IRQ, peripheral mode;
962          * (c) peripheral initiates, using SRP
963          */
964         if (musb->port_mode != MUSB_PORT_MODE_HOST &&
965                         (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
966                 musb->is_active = 1;
967         } else {
968                 devctl |= MUSB_DEVCTL_SESSION;
969         }
970 
971         musb_platform_enable(musb);
972         musb_writeb(regs, MUSB_DEVCTL, devctl);
973 }
974 
975 /*
976  * Make the HDRC stop (disable interrupts, etc.);
977  * reversible by musb_start
978  * called on gadget driver unregister
979  * with controller locked, irqs blocked
980  * acts as a NOP unless some role activated the hardware
981  */
982 void musb_stop(struct musb *musb)
983 {
984         /* stop IRQs, timers, ... */
985         musb_platform_disable(musb);
986         musb_generic_disable(musb);
987         dev_dbg(musb->controller, "HDRC disabled\n");
988 
989         /* FIXME
990          *  - mark host and/or peripheral drivers unusable/inactive
991          *  - disable DMA (and enable it in HdrcStart)
992          *  - make sure we can musb_start() after musb_stop(); with
993          *    OTG mode, gadget driver module rmmod/modprobe cycles that
994          *  - ...
995          */
996         musb_platform_try_idle(musb, 0);
997 }
998 
999 static void musb_shutdown(struct platform_device *pdev)
1000 {
1001         struct musb     *musb = dev_to_musb(&pdev->dev);
1002         unsigned long   flags;
1003 
1004         pm_runtime_get_sync(musb->controller);
1005 
1006         musb_host_cleanup(musb);
1007         musb_gadget_cleanup(musb);
1008 
1009         spin_lock_irqsave(&musb->lock, flags);
1010         musb_platform_disable(musb);
1011         musb_generic_disable(musb);
1012         spin_unlock_irqrestore(&musb->lock, flags);
1013 
1014         musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1015         musb_platform_exit(musb);
1016 
1017         pm_runtime_put(musb->controller);
1018         /* FIXME power down */
1019 }
1020 
1021 
1022 /*-------------------------------------------------------------------------*/
1023 
1024 /*
1025  * The silicon either has hard-wired endpoint configurations, or else
1026  * "dynamic fifo" sizing.  The driver has support for both, though at this
1027  * writing only the dynamic sizing is very well tested.   Since we switched
1028  * away from compile-time hardware parameters, we can no longer rely on
1029  * dead code elimination to leave only the relevant one in the object file.
1030  *
1031  * We don't currently use dynamic fifo setup capability to do anything
1032  * more than selecting one of a bunch of predefined configurations.
1033  */
1034 #if defined(CONFIG_USB_MUSB_TUSB6010)                   \
1035         || defined(CONFIG_USB_MUSB_TUSB6010_MODULE)     \
1036         || defined(CONFIG_USB_MUSB_OMAP2PLUS)           \
1037         || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE)    \
1038         || defined(CONFIG_USB_MUSB_AM35X)               \
1039         || defined(CONFIG_USB_MUSB_AM35X_MODULE)        \
1040         || defined(CONFIG_USB_MUSB_DSPS)                \
1041         || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1042 static ushort fifo_mode = 4;
1043 #elif defined(CONFIG_USB_MUSB_UX500)                    \
1044         || defined(CONFIG_USB_MUSB_UX500_MODULE)
1045 static ushort fifo_mode = 5;
1046 #else
1047 static ushort fifo_mode = 2;
1048 #endif
1049 
1050 /* "modprobe ... fifo_mode=1" etc */
1051 module_param(fifo_mode, ushort, 0);
1052 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1053 
1054 /*
1055  * tables defining fifo_mode values.  define more if you like.
1056  * for host side, make sure both halves of ep1 are set up.
1057  */
1058 
1059 /* mode 0 - fits in 2KB */
1060 static struct musb_fifo_cfg mode_0_cfg[] = {
1061 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1062 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1063 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1064 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1065 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1066 };
1067 
1068 /* mode 1 - fits in 4KB */
1069 static struct musb_fifo_cfg mode_1_cfg[] = {
1070 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1071 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1072 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1073 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1074 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1075 };
1076 
1077 /* mode 2 - fits in 4KB */
1078 static struct musb_fifo_cfg mode_2_cfg[] = {
1079 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1080 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1081 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1082 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1083 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1084 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1085 };
1086 
1087 /* mode 3 - fits in 4KB */
1088 static struct musb_fifo_cfg mode_3_cfg[] = {
1089 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1090 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1091 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1092 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1093 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1094 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1095 };
1096 
1097 /* mode 4 - fits in 16KB */
1098 static struct musb_fifo_cfg mode_4_cfg[] = {
1099 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1100 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1101 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1102 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1103 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1104 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1105 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1106 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1107 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1108 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1109 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 512, },
1110 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 512, },
1111 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 512, },
1112 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 512, },
1113 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 512, },
1114 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
1115 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
1116 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
1117 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
1118 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
1119 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
1120 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
1121 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
1122 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
1123 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1124 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1125 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1126 };
1127 
1128 /* mode 5 - fits in 8KB */
1129 static struct musb_fifo_cfg mode_5_cfg[] = {
1130 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1131 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1132 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1133 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1134 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1135 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1136 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1137 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1138 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1139 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1140 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 32, },
1141 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 32, },
1142 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 32, },
1143 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 32, },
1144 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 32, },
1145 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 32, },
1146 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 32, },
1147 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 32, },
1148 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 32, },
1149 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 32, },
1150 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 32, },
1151 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 32, },
1152 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 32, },
1153 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 32, },
1154 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1155 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1156 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1157 };
1158 
1159 /*
1160  * configure a fifo; for non-shared endpoints, this may be called
1161  * once for a tx fifo and once for an rx fifo.
1162  *
1163  * returns negative errno or offset for next fifo.
1164  */
1165 static int
1166 fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
1167                 const struct musb_fifo_cfg *cfg, u16 offset)
1168 {
1169         void __iomem    *mbase = musb->mregs;
1170         int     size = 0;
1171         u16     maxpacket = cfg->maxpacket;
1172         u16     c_off = offset >> 3;
1173         u8      c_size;
1174 
1175         /* expect hw_ep has already been zero-initialized */
1176 
1177         size = ffs(max(maxpacket, (u16) 8)) - 1;
1178         maxpacket = 1 << size;
1179 
1180         c_size = size - 3;
1181         if (cfg->mode == BUF_DOUBLE) {
1182                 if ((offset + (maxpacket << 1)) >
1183                                 (1 << (musb->config->ram_bits + 2)))
1184                         return -EMSGSIZE;
1185                 c_size |= MUSB_FIFOSZ_DPB;
1186         } else {
1187                 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1188                         return -EMSGSIZE;
1189         }
1190 
1191         /* configure the FIFO */
1192         musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1193 
1194         /* EP0 reserved endpoint for control, bidirectional;
1195          * EP1 reserved for bulk, two unidirectional halves.
1196          */
1197         if (hw_ep->epnum == 1)
1198                 musb->bulk_ep = hw_ep;
1199         /* REVISIT error check:  be sure ep0 can both rx and tx ... */
1200         switch (cfg->style) {
1201         case FIFO_TX:
1202                 musb_write_txfifosz(mbase, c_size);
1203                 musb_write_txfifoadd(mbase, c_off);
1204                 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1205                 hw_ep->max_packet_sz_tx = maxpacket;
1206                 break;
1207         case FIFO_RX:
1208                 musb_write_rxfifosz(mbase, c_size);
1209                 musb_write_rxfifoadd(mbase, c_off);
1210                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1211                 hw_ep->max_packet_sz_rx = maxpacket;
1212                 break;
1213         case FIFO_RXTX:
1214                 musb_write_txfifosz(mbase, c_size);
1215                 musb_write_txfifoadd(mbase, c_off);
1216                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1217                 hw_ep->max_packet_sz_rx = maxpacket;
1218 
1219                 musb_write_rxfifosz(mbase, c_size);
1220                 musb_write_rxfifoadd(mbase, c_off);
1221                 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1222                 hw_ep->max_packet_sz_tx = maxpacket;
1223 
1224                 hw_ep->is_shared_fifo = true;
1225                 break;
1226         }
1227 
1228         /* NOTE rx and tx endpoint irqs aren't managed separately,
1229          * which happens to be ok
1230          */
1231         musb->epmask |= (1 << hw_ep->epnum);
1232 
1233         return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1234 }
1235 
1236 static struct musb_fifo_cfg ep0_cfg = {
1237         .style = FIFO_RXTX, .maxpacket = 64,
1238 };
1239 
1240 static int ep_config_from_table(struct musb *musb)
1241 {
1242         const struct musb_fifo_cfg      *cfg;
1243         unsigned                i, n;
1244         int                     offset;
1245         struct musb_hw_ep       *hw_ep = musb->endpoints;
1246 
1247         if (musb->config->fifo_cfg) {
1248                 cfg = musb->config->fifo_cfg;
1249                 n = musb->config->fifo_cfg_size;
1250                 goto done;
1251         }
1252 
1253         switch (fifo_mode) {
1254         default:
1255                 fifo_mode = 0;
1256                 /* FALLTHROUGH */
1257         case 0:
1258                 cfg = mode_0_cfg;
1259                 n = ARRAY_SIZE(mode_0_cfg);
1260                 break;
1261         case 1:
1262                 cfg = mode_1_cfg;
1263                 n = ARRAY_SIZE(mode_1_cfg);
1264                 break;
1265         case 2:
1266                 cfg = mode_2_cfg;
1267                 n = ARRAY_SIZE(mode_2_cfg);
1268                 break;
1269         case 3:
1270                 cfg = mode_3_cfg;
1271                 n = ARRAY_SIZE(mode_3_cfg);
1272                 break;
1273         case 4:
1274                 cfg = mode_4_cfg;
1275                 n = ARRAY_SIZE(mode_4_cfg);
1276                 break;
1277         case 5:
1278                 cfg = mode_5_cfg;
1279                 n = ARRAY_SIZE(mode_5_cfg);
1280                 break;
1281         }
1282 
1283         printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1284                         musb_driver_name, fifo_mode);
1285 
1286 
1287 done:
1288         offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1289         /* assert(offset > 0) */
1290 
1291         /* NOTE:  for RTL versions >= 1.400 EPINFO and RAMINFO would
1292          * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1293          */
1294 
1295         for (i = 0; i < n; i++) {
1296                 u8      epn = cfg->hw_ep_num;
1297 
1298                 if (epn >= musb->config->num_eps) {
1299                         pr_debug("%s: invalid ep %d\n",
1300                                         musb_driver_name, epn);
1301                         return -EINVAL;
1302                 }
1303                 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1304                 if (offset < 0) {
1305                         pr_debug("%s: mem overrun, ep %d\n",
1306                                         musb_driver_name, epn);
1307                         return offset;
1308                 }
1309                 epn++;
1310                 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1311         }
1312 
1313         printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1314                         musb_driver_name,
1315                         n + 1, musb->config->num_eps * 2 - 1,
1316                         offset, (1 << (musb->config->ram_bits + 2)));
1317 
1318         if (!musb->bulk_ep) {
1319                 pr_debug("%s: missing bulk\n", musb_driver_name);
1320                 return -EINVAL;
1321         }
1322 
1323         return 0;
1324 }
1325 
1326 
1327 /*
1328  * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1329  * @param musb the controller
1330  */
1331 static int ep_config_from_hw(struct musb *musb)
1332 {
1333         u8 epnum = 0;
1334         struct musb_hw_ep *hw_ep;
1335         void __iomem *mbase = musb->mregs;
1336         int ret = 0;
1337 
1338         dev_dbg(musb->controller, "<== static silicon ep config\n");
1339 
1340         /* FIXME pick up ep0 maxpacket size */
1341 
1342         for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1343                 musb_ep_select(mbase, epnum);
1344                 hw_ep = musb->endpoints + epnum;
1345 
1346                 ret = musb_read_fifosize(musb, hw_ep, epnum);
1347                 if (ret < 0)
1348                         break;
1349 
1350                 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1351 
1352                 /* pick an RX/TX endpoint for bulk */
1353                 if (hw_ep->max_packet_sz_tx < 512
1354                                 || hw_ep->max_packet_sz_rx < 512)
1355                         continue;
1356 
1357                 /* REVISIT:  this algorithm is lazy, we should at least
1358                  * try to pick a double buffered endpoint.
1359                  */
1360                 if (musb->bulk_ep)
1361                         continue;
1362                 musb->bulk_ep = hw_ep;
1363         }
1364 
1365         if (!musb->bulk_ep) {
1366                 pr_debug("%s: missing bulk\n", musb_driver_name);
1367                 return -EINVAL;
1368         }
1369 
1370         return 0;
1371 }
1372 
1373 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1374 
1375 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1376  * configure endpoints, or take their config from silicon
1377  */
1378 static int musb_core_init(u16 musb_type, struct musb *musb)
1379 {
1380         u8 reg;
1381         char *type;
1382         char aInfo[90], aRevision[32], aDate[12];
1383         void __iomem    *mbase = musb->mregs;
1384         int             status = 0;
1385         int             i;
1386 
1387         /* log core options (read using indexed model) */
1388         reg = musb_read_configdata(mbase);
1389 
1390         strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1391         if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1392                 strcat(aInfo, ", dyn FIFOs");
1393                 musb->dyn_fifo = true;
1394         }
1395         if (reg & MUSB_CONFIGDATA_MPRXE) {
1396                 strcat(aInfo, ", bulk combine");
1397                 musb->bulk_combine = true;
1398         }
1399         if (reg & MUSB_CONFIGDATA_MPTXE) {
1400                 strcat(aInfo, ", bulk split");
1401                 musb->bulk_split = true;
1402         }
1403         if (reg & MUSB_CONFIGDATA_HBRXE) {
1404                 strcat(aInfo, ", HB-ISO Rx");
1405                 musb->hb_iso_rx = true;
1406         }
1407         if (reg & MUSB_CONFIGDATA_HBTXE) {
1408                 strcat(aInfo, ", HB-ISO Tx");
1409                 musb->hb_iso_tx = true;
1410         }
1411         if (reg & MUSB_CONFIGDATA_SOFTCONE)
1412                 strcat(aInfo, ", SoftConn");
1413 
1414         printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1415                         musb_driver_name, reg, aInfo);
1416 
1417         aDate[0] = 0;
1418         if (MUSB_CONTROLLER_MHDRC == musb_type) {
1419                 musb->is_multipoint = 1;
1420                 type = "M";
1421         } else {
1422                 musb->is_multipoint = 0;
1423                 type = "";
1424 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1425                 printk(KERN_ERR
1426                         "%s: kernel must blacklist external hubs\n",
1427                         musb_driver_name);
1428 #endif
1429         }
1430 
1431         /* log release info */
1432         musb->hwvers = musb_read_hwvers(mbase);
1433         snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1434                 MUSB_HWVERS_MINOR(musb->hwvers),
1435                 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1436         printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1437                         musb_driver_name, type, aRevision, aDate);
1438 
1439         /* configure ep0 */
1440         musb_configure_ep0(musb);
1441 
1442         /* discover endpoint configuration */
1443         musb->nr_endpoints = 1;
1444         musb->epmask = 1;
1445 
1446         if (musb->dyn_fifo)
1447                 status = ep_config_from_table(musb);
1448         else
1449                 status = ep_config_from_hw(musb);
1450 
1451         if (status < 0)
1452                 return status;
1453 
1454         /* finish init, and print endpoint config */
1455         for (i = 0; i < musb->nr_endpoints; i++) {
1456                 struct musb_hw_ep       *hw_ep = musb->endpoints + i;
1457 
1458                 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1459 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1460                 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1461                 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1462                 hw_ep->fifo_sync_va =
1463                         musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1464 
1465                 if (i == 0)
1466                         hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1467                 else
1468                         hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1469 #endif
1470 
1471                 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1472                 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1473                 hw_ep->rx_reinit = 1;
1474                 hw_ep->tx_reinit = 1;
1475 
1476                 if (hw_ep->max_packet_sz_tx) {
1477                         dev_dbg(musb->controller,
1478                                 "%s: hw_ep %d%s, %smax %d\n",
1479                                 musb_driver_name, i,
1480                                 hw_ep->is_shared_fifo ? "shared" : "tx",
1481                                 hw_ep->tx_double_buffered
1482                                         ? "doublebuffer, " : "",
1483                                 hw_ep->max_packet_sz_tx);
1484                 }
1485                 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1486                         dev_dbg(musb->controller,
1487                                 "%s: hw_ep %d%s, %smax %d\n",
1488                                 musb_driver_name, i,
1489                                 "rx",
1490                                 hw_ep->rx_double_buffered
1491                                         ? "doublebuffer, " : "",
1492                                 hw_ep->max_packet_sz_rx);
1493                 }
1494                 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1495                         dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1496         }
1497 
1498         return 0;
1499 }
1500 
1501 /*-------------------------------------------------------------------------*/
1502 
1503 /*
1504  * handle all the irqs defined by the HDRC core. for now we expect:  other
1505  * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1506  * will be assigned, and the irq will already have been acked.
1507  *
1508  * called in irq context with spinlock held, irqs blocked
1509  */
1510 irqreturn_t musb_interrupt(struct musb *musb)
1511 {
1512         irqreturn_t     retval = IRQ_NONE;
1513         u8              devctl;
1514         int             ep_num;
1515         u32             reg;
1516 
1517         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1518 
1519         dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1520                 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1521                 musb->int_usb, musb->int_tx, musb->int_rx);
1522 
1523         /* the core can interrupt us for multiple reasons; docs have
1524          * a generic interrupt flowchart to follow
1525          */
1526         if (musb->int_usb)
1527                 retval |= musb_stage0_irq(musb, musb->int_usb,
1528                                 devctl);
1529 
1530         /* "stage 1" is handling endpoint irqs */
1531 
1532         /* handle endpoint 0 first */
1533         if (musb->int_tx & 1) {
1534                 if (devctl & MUSB_DEVCTL_HM)
1535                         retval |= musb_h_ep0_irq(musb);
1536                 else
1537                         retval |= musb_g_ep0_irq(musb);
1538         }
1539 
1540         /* RX on endpoints 1-15 */
1541         reg = musb->int_rx >> 1;
1542         ep_num = 1;
1543         while (reg) {
1544                 if (reg & 1) {
1545                         /* musb_ep_select(musb->mregs, ep_num); */
1546                         /* REVISIT just retval = ep->rx_irq(...) */
1547                         retval = IRQ_HANDLED;
1548                         if (devctl & MUSB_DEVCTL_HM)
1549                                 musb_host_rx(musb, ep_num);
1550                         else
1551                                 musb_g_rx(musb, ep_num);
1552                 }
1553 
1554                 reg >>= 1;
1555                 ep_num++;
1556         }
1557 
1558         /* TX on endpoints 1-15 */
1559         reg = musb->int_tx >> 1;
1560         ep_num = 1;
1561         while (reg) {
1562                 if (reg & 1) {
1563                         /* musb_ep_select(musb->mregs, ep_num); */
1564                         /* REVISIT just retval |= ep->tx_irq(...) */
1565                         retval = IRQ_HANDLED;
1566                         if (devctl & MUSB_DEVCTL_HM)
1567                                 musb_host_tx(musb, ep_num);
1568                         else
1569                                 musb_g_tx(musb, ep_num);
1570                 }
1571                 reg >>= 1;
1572                 ep_num++;
1573         }
1574 
1575         return retval;
1576 }
1577 EXPORT_SYMBOL_GPL(musb_interrupt);
1578 
1579 #ifndef CONFIG_MUSB_PIO_ONLY
1580 static bool use_dma = 1;
1581 
1582 /* "modprobe ... use_dma=0" etc */
1583 module_param(use_dma, bool, 0);
1584 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1585 
1586 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1587 {
1588         u8      devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1589 
1590         /* called with controller lock already held */
1591 
1592         if (!epnum) {
1593 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1594                 if (!is_cppi_enabled()) {
1595                         /* endpoint 0 */
1596                         if (devctl & MUSB_DEVCTL_HM)
1597                                 musb_h_ep0_irq(musb);
1598                         else
1599                                 musb_g_ep0_irq(musb);
1600                 }
1601 #endif
1602         } else {
1603                 /* endpoints 1..15 */
1604                 if (transmit) {
1605                         if (devctl & MUSB_DEVCTL_HM)
1606                                 musb_host_tx(musb, epnum);
1607                         else
1608                                 musb_g_tx(musb, epnum);
1609                 } else {
1610                         /* receive */
1611                         if (devctl & MUSB_DEVCTL_HM)
1612                                 musb_host_rx(musb, epnum);
1613                         else
1614                                 musb_g_rx(musb, epnum);
1615                 }
1616         }
1617 }
1618 EXPORT_SYMBOL_GPL(musb_dma_completion);
1619 
1620 #else
1621 #define use_dma                 0
1622 #endif
1623 
1624 /*-------------------------------------------------------------------------*/
1625 
1626 static ssize_t
1627 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1628 {
1629         struct musb *musb = dev_to_musb(dev);
1630         unsigned long flags;
1631         int ret = -EINVAL;
1632 
1633         spin_lock_irqsave(&musb->lock, flags);
1634         ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->state));
1635         spin_unlock_irqrestore(&musb->lock, flags);
1636 
1637         return ret;
1638 }
1639 
1640 static ssize_t
1641 musb_mode_store(struct device *dev, struct device_attribute *attr,
1642                 const char *buf, size_t n)
1643 {
1644         struct musb     *musb = dev_to_musb(dev);
1645         unsigned long   flags;
1646         int             status;
1647 
1648         spin_lock_irqsave(&musb->lock, flags);
1649         if (sysfs_streq(buf, "host"))
1650                 status = musb_platform_set_mode(musb, MUSB_HOST);
1651         else if (sysfs_streq(buf, "peripheral"))
1652                 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1653         else if (sysfs_streq(buf, "otg"))
1654                 status = musb_platform_set_mode(musb, MUSB_OTG);
1655         else
1656                 status = -EINVAL;
1657         spin_unlock_irqrestore(&musb->lock, flags);
1658 
1659         return (status == 0) ? n : status;
1660 }
1661 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1662 
1663 static ssize_t
1664 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1665                 const char *buf, size_t n)
1666 {
1667         struct musb     *musb = dev_to_musb(dev);
1668         unsigned long   flags;
1669         unsigned long   val;
1670 
1671         if (sscanf(buf, "%lu", &val) < 1) {
1672                 dev_err(dev, "Invalid VBUS timeout ms value\n");
1673                 return -EINVAL;
1674         }
1675 
1676         spin_lock_irqsave(&musb->lock, flags);
1677         /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1678         musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1679         if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1680                 musb->is_active = 0;
1681         musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1682         spin_unlock_irqrestore(&musb->lock, flags);
1683 
1684         return n;
1685 }
1686 
1687 static ssize_t
1688 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1689 {
1690         struct musb     *musb = dev_to_musb(dev);
1691         unsigned long   flags;
1692         unsigned long   val;
1693         int             vbus;
1694 
1695         spin_lock_irqsave(&musb->lock, flags);
1696         val = musb->a_wait_bcon;
1697         /* FIXME get_vbus_status() is normally #defined as false...
1698          * and is effectively TUSB-specific.
1699          */
1700         vbus = musb_platform_get_vbus_status(musb);
1701         spin_unlock_irqrestore(&musb->lock, flags);
1702 
1703         return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1704                         vbus ? "on" : "off", val);
1705 }
1706 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1707 
1708 /* Gadget drivers can't know that a host is connected so they might want
1709  * to start SRP, but users can.  This allows userspace to trigger SRP.
1710  */
1711 static ssize_t
1712 musb_srp_store(struct device *dev, struct device_attribute *attr,
1713                 const char *buf, size_t n)
1714 {
1715         struct musb     *musb = dev_to_musb(dev);
1716         unsigned short  srp;
1717 
1718         if (sscanf(buf, "%hu", &srp) != 1
1719                         || (srp != 1)) {
1720                 dev_err(dev, "SRP: Value must be 1\n");
1721                 return -EINVAL;
1722         }
1723 
1724         if (srp == 1)
1725                 musb_g_wakeup(musb);
1726 
1727         return n;
1728 }
1729 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1730 
1731 static struct attribute *musb_attributes[] = {
1732         &dev_attr_mode.attr,
1733         &dev_attr_vbus.attr,
1734         &dev_attr_srp.attr,
1735         NULL
1736 };
1737 
1738 static const struct attribute_group musb_attr_group = {
1739         .attrs = musb_attributes,
1740 };
1741 
1742 /* Only used to provide driver mode change events */
1743 static void musb_irq_work(struct work_struct *data)
1744 {
1745         struct musb *musb = container_of(data, struct musb, irq_work);
1746 
1747         if (musb->xceiv->state != musb->xceiv_old_state) {
1748                 musb->xceiv_old_state = musb->xceiv->state;
1749                 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1750         }
1751 }
1752 
1753 /* Recover from babble interrupt conditions */
1754 static void musb_recover_work(struct work_struct *data)
1755 {
1756         struct musb *musb = container_of(data, struct musb, recover_work);
1757         int status;
1758 
1759         musb_platform_reset(musb);
1760 
1761         usb_phy_vbus_off(musb->xceiv);
1762         udelay(100);
1763 
1764         usb_phy_vbus_on(musb->xceiv);
1765         udelay(100);
1766 
1767         /*
1768          * When a babble condition occurs, the musb controller removes the
1769          * session bit and the endpoint config is lost.
1770          */
1771         if (musb->dyn_fifo)
1772                 status = ep_config_from_table(musb);
1773         else
1774                 status = ep_config_from_hw(musb);
1775 
1776         /* start the session again */
1777         if (status == 0)
1778                 musb_start(musb);
1779 }
1780 
1781 /* --------------------------------------------------------------------------
1782  * Init support
1783  */
1784 
1785 static struct musb *allocate_instance(struct device *dev,
1786                 struct musb_hdrc_config *config, void __iomem *mbase)
1787 {
1788         struct musb             *musb;
1789         struct musb_hw_ep       *ep;
1790         int                     epnum;
1791         int                     ret;
1792 
1793         musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1794         if (!musb)
1795                 return NULL;
1796 
1797         INIT_LIST_HEAD(&musb->control);
1798         INIT_LIST_HEAD(&musb->in_bulk);
1799         INIT_LIST_HEAD(&musb->out_bulk);
1800 
1801         musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1802         musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1803         musb->mregs = mbase;
1804         musb->ctrl_base = mbase;
1805         musb->nIrq = -ENODEV;
1806         musb->config = config;
1807         BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1808         for (epnum = 0, ep = musb->endpoints;
1809                         epnum < musb->config->num_eps;
1810                         epnum++, ep++) {
1811                 ep->musb = musb;
1812                 ep->epnum = epnum;
1813         }
1814 
1815         musb->controller = dev;
1816 
1817         ret = musb_host_alloc(musb);
1818         if (ret < 0)
1819                 goto err_free;
1820 
1821         dev_set_drvdata(dev, musb);
1822 
1823         return musb;
1824 
1825 err_free:
1826         return NULL;
1827 }
1828 
1829 static void musb_free(struct musb *musb)
1830 {
1831         /* this has multiple entry modes. it handles fault cleanup after
1832          * probe(), where things may be partially set up, as well as rmmod
1833          * cleanup after everything's been de-activated.
1834          */
1835 
1836 #ifdef CONFIG_SYSFS
1837         sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1838 #endif
1839 
1840         if (musb->nIrq >= 0) {
1841                 if (musb->irq_wake)
1842                         disable_irq_wake(musb->nIrq);
1843                 free_irq(musb->nIrq, musb);
1844         }
1845 
1846         musb_host_free(musb);
1847 }
1848 
1849 static void musb_deassert_reset(struct work_struct *work)
1850 {
1851         struct musb *musb;
1852         unsigned long flags;
1853 
1854         musb = container_of(work, struct musb, deassert_reset_work.work);
1855 
1856         spin_lock_irqsave(&musb->lock, flags);
1857 
1858         if (musb->port1_status & USB_PORT_STAT_RESET)
1859                 musb_port_reset(musb, false);
1860 
1861         spin_unlock_irqrestore(&musb->lock, flags);
1862 }
1863 
1864 /*
1865  * Perform generic per-controller initialization.
1866  *
1867  * @dev: the controller (already clocked, etc)
1868  * @nIrq: IRQ number
1869  * @ctrl: virtual address of controller registers,
1870  *      not yet corrected for platform-specific offsets
1871  */
1872 static int
1873 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1874 {
1875         int                     status;
1876         struct musb             *musb;
1877         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1878 
1879         /* The driver might handle more features than the board; OK.
1880          * Fail when the board needs a feature that's not enabled.
1881          */
1882         if (!plat) {
1883                 dev_dbg(dev, "no platform_data?\n");
1884                 status = -ENODEV;
1885                 goto fail0;
1886         }
1887 
1888         /* allocate */
1889         musb = allocate_instance(dev, plat->config, ctrl);
1890         if (!musb) {
1891                 status = -ENOMEM;
1892                 goto fail0;
1893         }
1894 
1895         pm_runtime_use_autosuspend(musb->controller);
1896         pm_runtime_set_autosuspend_delay(musb->controller, 200);
1897         pm_runtime_enable(musb->controller);
1898 
1899         spin_lock_init(&musb->lock);
1900         musb->board_set_power = plat->set_power;
1901         musb->min_power = plat->min_power;
1902         musb->ops = plat->platform_ops;
1903         musb->port_mode = plat->mode;
1904 
1905         /* The musb_platform_init() call:
1906          *   - adjusts musb->mregs
1907          *   - sets the musb->isr
1908          *   - may initialize an integrated transceiver
1909          *   - initializes musb->xceiv, usually by otg_get_phy()
1910          *   - stops powering VBUS
1911          *
1912          * There are various transceiver configurations.  Blackfin,
1913          * DaVinci, TUSB60x0, and others integrate them.  OMAP3 uses
1914          * external/discrete ones in various flavors (twl4030 family,
1915          * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1916          */
1917         status = musb_platform_init(musb);
1918         if (status < 0)
1919                 goto fail1;
1920 
1921         if (!musb->isr) {
1922                 status = -ENODEV;
1923                 goto fail2;
1924         }
1925 
1926         if (!musb->xceiv->io_ops) {
1927                 musb->xceiv->io_dev = musb->controller;
1928                 musb->xceiv->io_priv = musb->mregs;
1929                 musb->xceiv->io_ops = &musb_ulpi_access;
1930         }
1931 
1932         pm_runtime_get_sync(musb->controller);
1933 
1934         if (use_dma && dev->dma_mask) {
1935                 musb->dma_controller = dma_controller_create(musb, musb->mregs);
1936                 if (IS_ERR(musb->dma_controller)) {
1937                         status = PTR_ERR(musb->dma_controller);
1938                         goto fail2_5;
1939                 }
1940         }
1941 
1942         /* be sure interrupts are disabled before connecting ISR */
1943         musb_platform_disable(musb);
1944         musb_generic_disable(musb);
1945 
1946         /* Init IRQ workqueue before request_irq */
1947         INIT_WORK(&musb->irq_work, musb_irq_work);
1948         INIT_WORK(&musb->recover_work, musb_recover_work);
1949         INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
1950         INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
1951 
1952         /* setup musb parts of the core (especially endpoints) */
1953         status = musb_core_init(plat->config->multipoint
1954                         ? MUSB_CONTROLLER_MHDRC
1955                         : MUSB_CONTROLLER_HDRC, musb);
1956         if (status < 0)
1957                 goto fail3;
1958 
1959         setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1960 
1961         /* attach to the IRQ */
1962         if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1963                 dev_err(dev, "request_irq %d failed!\n", nIrq);
1964                 status = -ENODEV;
1965                 goto fail3;
1966         }
1967         musb->nIrq = nIrq;
1968         /* FIXME this handles wakeup irqs wrong */
1969         if (enable_irq_wake(nIrq) == 0) {
1970                 musb->irq_wake = 1;
1971                 device_init_wakeup(dev, 1);
1972         } else {
1973                 musb->irq_wake = 0;
1974         }
1975 
1976         /* program PHY to use external vBus if required */
1977         if (plat->extvbus) {
1978                 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1979                 busctl |= MUSB_ULPI_USE_EXTVBUS;
1980                 musb_write_ulpi_buscontrol(musb->mregs, busctl);
1981         }
1982 
1983         if (musb->xceiv->otg->default_a) {
1984                 MUSB_HST_MODE(musb);
1985                 musb->xceiv->state = OTG_STATE_A_IDLE;
1986         } else {
1987                 MUSB_DEV_MODE(musb);
1988                 musb->xceiv->state = OTG_STATE_B_IDLE;
1989         }
1990 
1991         switch (musb->port_mode) {
1992         case MUSB_PORT_MODE_HOST:
1993                 status = musb_host_setup(musb, plat->power);
1994                 if (status < 0)
1995                         goto fail3;
1996                 status = musb_platform_set_mode(musb, MUSB_HOST);
1997                 break;
1998         case MUSB_PORT_MODE_GADGET:
1999                 status = musb_gadget_setup(musb);
2000                 if (status < 0)
2001                         goto fail3;
2002                 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2003                 break;
2004         case MUSB_PORT_MODE_DUAL_ROLE:
2005                 status = musb_host_setup(musb, plat->power);
2006                 if (status < 0)
2007                         goto fail3;
2008                 status = musb_gadget_setup(musb);
2009                 if (status) {
2010                         musb_host_cleanup(musb);
2011                         goto fail3;
2012                 }
2013                 status = musb_platform_set_mode(musb, MUSB_OTG);
2014                 break;
2015         default:
2016                 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2017                 break;
2018         }
2019 
2020         if (status < 0)
2021                 goto fail3;
2022 
2023         status = musb_init_debugfs(musb);
2024         if (status < 0)
2025                 goto fail4;
2026 
2027         status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2028         if (status)
2029                 goto fail5;
2030 
2031         pm_runtime_put(musb->controller);
2032 
2033         return 0;
2034 
2035 fail5:
2036         musb_exit_debugfs(musb);
2037 
2038 fail4:
2039         musb_gadget_cleanup(musb);
2040         musb_host_cleanup(musb);
2041 
2042 fail3:
2043         cancel_work_sync(&musb->irq_work);
2044         cancel_work_sync(&musb->recover_work);
2045         cancel_delayed_work_sync(&musb->finish_resume_work);
2046         cancel_delayed_work_sync(&musb->deassert_reset_work);
2047         if (musb->dma_controller)
2048                 dma_controller_destroy(musb->dma_controller);
2049 fail2_5:
2050         pm_runtime_put_sync(musb->controller);
2051 
2052 fail2:
2053         if (musb->irq_wake)
2054                 device_init_wakeup(dev, 0);
2055         musb_platform_exit(musb);
2056 
2057 fail1:
2058         pm_runtime_disable(musb->controller);
2059         dev_err(musb->controller,
2060                 "musb_init_controller failed with status %d\n", status);
2061 
2062         musb_free(musb);
2063 
2064 fail0:
2065 
2066         return status;
2067 
2068 }
2069 
2070 /*-------------------------------------------------------------------------*/
2071 
2072 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2073  * bridge to a platform device; this driver then suffices.
2074  */
2075 static int musb_probe(struct platform_device *pdev)
2076 {
2077         struct device   *dev = &pdev->dev;
2078         int             irq = platform_get_irq_byname(pdev, "mc");
2079         struct resource *iomem;
2080         void __iomem    *base;
2081 
2082         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2083         if (!iomem || irq <= 0)
2084                 return -ENODEV;
2085 
2086         base = devm_ioremap_resource(dev, iomem);
2087         if (IS_ERR(base))
2088                 return PTR_ERR(base);
2089 
2090         return musb_init_controller(dev, irq, base);
2091 }
2092 
2093 static int musb_remove(struct platform_device *pdev)
2094 {
2095         struct device   *dev = &pdev->dev;
2096         struct musb     *musb = dev_to_musb(dev);
2097 
2098         /* this gets called on rmmod.
2099          *  - Host mode: host may still be active
2100          *  - Peripheral mode: peripheral is deactivated (or never-activated)
2101          *  - OTG mode: both roles are deactivated (or never-activated)
2102          */
2103         musb_exit_debugfs(musb);
2104         musb_shutdown(pdev);
2105 
2106         if (musb->dma_controller)
2107                 dma_controller_destroy(musb->dma_controller);
2108 
2109         cancel_work_sync(&musb->irq_work);
2110         cancel_work_sync(&musb->recover_work);
2111         cancel_delayed_work_sync(&musb->finish_resume_work);
2112         cancel_delayed_work_sync(&musb->deassert_reset_work);
2113         musb_free(musb);
2114         device_init_wakeup(dev, 0);
2115         return 0;
2116 }
2117 
2118 #ifdef  CONFIG_PM
2119 
2120 static void musb_save_context(struct musb *musb)
2121 {
2122         int i;
2123         void __iomem *musb_base = musb->mregs;
2124         void __iomem *epio;
2125 
2126         musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2127         musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2128         musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2129         musb->context.power = musb_readb(musb_base, MUSB_POWER);
2130         musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2131         musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2132         musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2133 
2134         for (i = 0; i < musb->config->num_eps; ++i) {
2135                 struct musb_hw_ep       *hw_ep;
2136 
2137                 hw_ep = &musb->endpoints[i];
2138                 if (!hw_ep)
2139                         continue;
2140 
2141                 epio = hw_ep->regs;
2142                 if (!epio)
2143                         continue;
2144 
2145                 musb_writeb(musb_base, MUSB_INDEX, i);
2146                 musb->context.index_regs[i].txmaxp =
2147                         musb_readw(epio, MUSB_TXMAXP);
2148                 musb->context.index_regs[i].txcsr =
2149                         musb_readw(epio, MUSB_TXCSR);
2150                 musb->context.index_regs[i].rxmaxp =
2151                         musb_readw(epio, MUSB_RXMAXP);
2152                 musb->context.index_regs[i].rxcsr =
2153                         musb_readw(epio, MUSB_RXCSR);
2154 
2155                 if (musb->dyn_fifo) {
2156                         musb->context.index_regs[i].txfifoadd =
2157                                         musb_read_txfifoadd(musb_base);
2158                         musb->context.index_regs[i].rxfifoadd =
2159                                         musb_read_rxfifoadd(musb_base);
2160                         musb->context.index_regs[i].txfifosz =
2161                                         musb_read_txfifosz(musb_base);
2162                         musb->context.index_regs[i].rxfifosz =
2163                                         musb_read_rxfifosz(musb_base);
2164                 }
2165 
2166                 musb->context.index_regs[i].txtype =
2167                         musb_readb(epio, MUSB_TXTYPE);
2168                 musb->context.index_regs[i].txinterval =
2169                         musb_readb(epio, MUSB_TXINTERVAL);
2170                 musb->context.index_regs[i].rxtype =
2171                         musb_readb(epio, MUSB_RXTYPE);
2172                 musb->context.index_regs[i].rxinterval =
2173                         musb_readb(epio, MUSB_RXINTERVAL);
2174 
2175                 musb->context.index_regs[i].txfunaddr =
2176                         musb_read_txfunaddr(musb_base, i);
2177                 musb->context.index_regs[i].txhubaddr =
2178                         musb_read_txhubaddr(musb_base, i);
2179                 musb->context.index_regs[i].txhubport =
2180                         musb_read_txhubport(musb_base, i);
2181 
2182                 musb->context.index_regs[i].rxfunaddr =
2183                         musb_read_rxfunaddr(musb_base, i);
2184                 musb->context.index_regs[i].rxhubaddr =
2185                         musb_read_rxhubaddr(musb_base, i);
2186                 musb->context.index_regs[i].rxhubport =
2187                         musb_read_rxhubport(musb_base, i);
2188         }
2189 }
2190 
2191 static void musb_restore_context(struct musb *musb)
2192 {
2193         int i;
2194         void __iomem *musb_base = musb->mregs;
2195         void __iomem *ep_target_regs;
2196         void __iomem *epio;
2197         u8 power;
2198 
2199         musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2200         musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2201         musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2202 
2203         /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2204         power = musb_readb(musb_base, MUSB_POWER);
2205         power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2206         musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2207         power |= musb->context.power;
2208         musb_writeb(musb_base, MUSB_POWER, power);
2209 
2210         musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2211         musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2212         musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2213         musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2214 
2215         for (i = 0; i < musb->config->num_eps; ++i) {
2216                 struct musb_hw_ep       *hw_ep;
2217 
2218                 hw_ep = &musb->endpoints[i];
2219                 if (!hw_ep)
2220                         continue;
2221 
2222                 epio = hw_ep->regs;
2223                 if (!epio)
2224                         continue;
2225 
2226                 musb_writeb(musb_base, MUSB_INDEX, i);
2227                 musb_writew(epio, MUSB_TXMAXP,
2228                         musb->context.index_regs[i].txmaxp);
2229                 musb_writew(epio, MUSB_TXCSR,
2230                         musb->context.index_regs[i].txcsr);
2231                 musb_writew(epio, MUSB_RXMAXP,
2232                         musb->context.index_regs[i].rxmaxp);
2233                 musb_writew(epio, MUSB_RXCSR,
2234                         musb->context.index_regs[i].rxcsr);
2235 
2236                 if (musb->dyn_fifo) {
2237                         musb_write_txfifosz(musb_base,
2238                                 musb->context.index_regs[i].txfifosz);
2239                         musb_write_rxfifosz(musb_base,
2240                                 musb->context.index_regs[i].rxfifosz);
2241                         musb_write_txfifoadd(musb_base,
2242                                 musb->context.index_regs[i].txfifoadd);
2243                         musb_write_rxfifoadd(musb_base,
2244                                 musb->context.index_regs[i].rxfifoadd);
2245                 }
2246 
2247                 musb_writeb(epio, MUSB_TXTYPE,
2248                                 musb->context.index_regs[i].txtype);
2249                 musb_writeb(epio, MUSB_TXINTERVAL,
2250                                 musb->context.index_regs[i].txinterval);
2251                 musb_writeb(epio, MUSB_RXTYPE,
2252                                 musb->context.index_regs[i].rxtype);
2253                 musb_writeb(epio, MUSB_RXINTERVAL,
2254 
2255                                 musb->context.index_regs[i].rxinterval);
2256                 musb_write_txfunaddr(musb_base, i,
2257                                 musb->context.index_regs[i].txfunaddr);
2258                 musb_write_txhubaddr(musb_base, i,
2259                                 musb->context.index_regs[i].txhubaddr);
2260                 musb_write_txhubport(musb_base, i,
2261                                 musb->context.index_regs[i].txhubport);
2262 
2263                 ep_target_regs =
2264                         musb_read_target_reg_base(i, musb_base);
2265 
2266                 musb_write_rxfunaddr(ep_target_regs,
2267                                 musb->context.index_regs[i].rxfunaddr);
2268                 musb_write_rxhubaddr(ep_target_regs,
2269                                 musb->context.index_regs[i].rxhubaddr);
2270                 musb_write_rxhubport(ep_target_regs,
2271                                 musb->context.index_regs[i].rxhubport);
2272         }
2273         musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2274 }
2275 
2276 static int musb_suspend(struct device *dev)
2277 {
2278         struct musb     *musb = dev_to_musb(dev);
2279         unsigned long   flags;
2280 
2281         spin_lock_irqsave(&musb->lock, flags);
2282 
2283         if (is_peripheral_active(musb)) {
2284                 /* FIXME force disconnect unless we know USB will wake
2285                  * the system up quickly enough to respond ...
2286                  */
2287         } else if (is_host_active(musb)) {
2288                 /* we know all the children are suspended; sometimes
2289                  * they will even be wakeup-enabled.
2290                  */
2291         }
2292 
2293         musb_save_context(musb);
2294 
2295         spin_unlock_irqrestore(&musb->lock, flags);
2296         return 0;
2297 }
2298 
2299 static int musb_resume_noirq(struct device *dev)
2300 {
2301         struct musb     *musb = dev_to_musb(dev);
2302 
2303         /*
2304          * For static cmos like DaVinci, register values were preserved
2305          * unless for some reason the whole soc powered down or the USB
2306          * module got reset through the PSC (vs just being disabled).
2307          *
2308          * For the DSPS glue layer though, a full register restore has to
2309          * be done. As it shouldn't harm other platforms, we do it
2310          * unconditionally.
2311          */
2312 
2313         musb_restore_context(musb);
2314 
2315         return 0;
2316 }
2317 
2318 static int musb_runtime_suspend(struct device *dev)
2319 {
2320         struct musb     *musb = dev_to_musb(dev);
2321 
2322         musb_save_context(musb);
2323 
2324         return 0;
2325 }
2326 
2327 static int musb_runtime_resume(struct device *dev)
2328 {
2329         struct musb     *musb = dev_to_musb(dev);
2330         static int      first = 1;
2331 
2332         /*
2333          * When pm_runtime_get_sync called for the first time in driver
2334          * init,  some of the structure is still not initialized which is
2335          * used in restore function. But clock needs to be
2336          * enabled before any register access, so
2337          * pm_runtime_get_sync has to be called.
2338          * Also context restore without save does not make
2339          * any sense
2340          */
2341         if (!first)
2342                 musb_restore_context(musb);
2343         first = 0;
2344 
2345         return 0;
2346 }
2347 
2348 static const struct dev_pm_ops musb_dev_pm_ops = {
2349         .suspend        = musb_suspend,
2350         .resume_noirq   = musb_resume_noirq,
2351         .runtime_suspend = musb_runtime_suspend,
2352         .runtime_resume = musb_runtime_resume,
2353 };
2354 
2355 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2356 #else
2357 #define MUSB_DEV_PM_OPS NULL
2358 #endif
2359 
2360 static struct platform_driver musb_driver = {
2361         .driver = {
2362                 .name           = (char *)musb_driver_name,
2363                 .bus            = &platform_bus_type,
2364                 .owner          = THIS_MODULE,
2365                 .pm             = MUSB_DEV_PM_OPS,
2366         },
2367         .probe          = musb_probe,
2368         .remove         = musb_remove,
2369         .shutdown       = musb_shutdown,
2370 };
2371 
2372 module_platform_driver(musb_driver);
2373 

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