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Linux/drivers/usb/musb/musb_core.c

  1 /*
  2  * MUSB OTG driver core code
  3  *
  4  * Copyright 2005 Mentor Graphics Corporation
  5  * Copyright (C) 2005-2006 by Texas Instruments
  6  * Copyright (C) 2006-2007 Nokia Corporation
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License
 10  * version 2 as published by the Free Software Foundation.
 11  *
 12  * This program is distributed in the hope that it will be useful, but
 13  * WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 15  * General Public License for more details.
 16  *
 17  * You should have received a copy of the GNU General Public License
 18  * along with this program; if not, write to the Free Software
 19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 20  * 02110-1301 USA
 21  *
 22  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 25  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 32  *
 33  */
 34 
 35 /*
 36  * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
 37  *
 38  * This consists of a Host Controller Driver (HCD) and a peripheral
 39  * controller driver implementing the "Gadget" API; OTG support is
 40  * in the works.  These are normal Linux-USB controller drivers which
 41  * use IRQs and have no dedicated thread.
 42  *
 43  * This version of the driver has only been used with products from
 44  * Texas Instruments.  Those products integrate the Inventra logic
 45  * with other DMA, IRQ, and bus modules, as well as other logic that
 46  * needs to be reflected in this driver.
 47  *
 48  *
 49  * NOTE:  the original Mentor code here was pretty much a collection
 50  * of mechanisms that don't seem to have been fully integrated/working
 51  * for *any* Linux kernel version.  This version aims at Linux 2.6.now,
 52  * Key open issues include:
 53  *
 54  *  - Lack of host-side transaction scheduling, for all transfer types.
 55  *    The hardware doesn't do it; instead, software must.
 56  *
 57  *    This is not an issue for OTG devices that don't support external
 58  *    hubs, but for more "normal" USB hosts it's a user issue that the
 59  *    "multipoint" support doesn't scale in the expected ways.  That
 60  *    includes DaVinci EVM in a common non-OTG mode.
 61  *
 62  *      * Control and bulk use dedicated endpoints, and there's as
 63  *        yet no mechanism to either (a) reclaim the hardware when
 64  *        peripherals are NAKing, which gets complicated with bulk
 65  *        endpoints, or (b) use more than a single bulk endpoint in
 66  *        each direction.
 67  *
 68  *        RESULT:  one device may be perceived as blocking another one.
 69  *
 70  *      * Interrupt and isochronous will dynamically allocate endpoint
 71  *        hardware, but (a) there's no record keeping for bandwidth;
 72  *        (b) in the common case that few endpoints are available, there
 73  *        is no mechanism to reuse endpoints to talk to multiple devices.
 74  *
 75  *        RESULT:  At one extreme, bandwidth can be overcommitted in
 76  *        some hardware configurations, no faults will be reported.
 77  *        At the other extreme, the bandwidth capabilities which do
 78  *        exist tend to be severely undercommitted.  You can't yet hook
 79  *        up both a keyboard and a mouse to an external USB hub.
 80  */
 81 
 82 /*
 83  * This gets many kinds of configuration information:
 84  *      - Kconfig for everything user-configurable
 85  *      - platform_device for addressing, irq, and platform_data
 86  *      - platform_data is mostly for board-specific information
 87  *        (plus recentrly, SOC or family details)
 88  *
 89  * Most of the conditional compilation will (someday) vanish.
 90  */
 91 
 92 #include <linux/module.h>
 93 #include <linux/kernel.h>
 94 #include <linux/sched.h>
 95 #include <linux/slab.h>
 96 #include <linux/list.h>
 97 #include <linux/kobject.h>
 98 #include <linux/prefetch.h>
 99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102 #include <linux/usb.h>
103 #include <linux/usb/of.h>
104 
105 #include "musb_core.h"
106 #include "musb_trace.h"
107 
108 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
109 
110 
111 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
112 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
113 
114 #define MUSB_VERSION "6.0"
115 
116 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
117 
118 #define MUSB_DRIVER_NAME "musb-hdrc"
119 const char musb_driver_name[] = MUSB_DRIVER_NAME;
120 
121 MODULE_DESCRIPTION(DRIVER_INFO);
122 MODULE_AUTHOR(DRIVER_AUTHOR);
123 MODULE_LICENSE("GPL");
124 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
125 
126 
127 /*-------------------------------------------------------------------------*/
128 
129 static inline struct musb *dev_to_musb(struct device *dev)
130 {
131         return dev_get_drvdata(dev);
132 }
133 
134 enum musb_mode musb_get_mode(struct device *dev)
135 {
136         enum usb_dr_mode mode;
137 
138         mode = usb_get_dr_mode(dev);
139         switch (mode) {
140         case USB_DR_MODE_HOST:
141                 return MUSB_HOST;
142         case USB_DR_MODE_PERIPHERAL:
143                 return MUSB_PERIPHERAL;
144         case USB_DR_MODE_OTG:
145         case USB_DR_MODE_UNKNOWN:
146         default:
147                 return MUSB_OTG;
148         }
149 }
150 EXPORT_SYMBOL_GPL(musb_get_mode);
151 
152 /*-------------------------------------------------------------------------*/
153 
154 #ifndef CONFIG_BLACKFIN
155 static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
156 {
157         void __iomem *addr = phy->io_priv;
158         int     i = 0;
159         u8      r;
160         u8      power;
161         int     ret;
162 
163         pm_runtime_get_sync(phy->io_dev);
164 
165         /* Make sure the transceiver is not in low power mode */
166         power = musb_readb(addr, MUSB_POWER);
167         power &= ~MUSB_POWER_SUSPENDM;
168         musb_writeb(addr, MUSB_POWER, power);
169 
170         /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
171          * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
172          */
173 
174         musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
175         musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
176                         MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
177 
178         while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
179                                 & MUSB_ULPI_REG_CMPLT)) {
180                 i++;
181                 if (i == 10000) {
182                         ret = -ETIMEDOUT;
183                         goto out;
184                 }
185 
186         }
187         r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
188         r &= ~MUSB_ULPI_REG_CMPLT;
189         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
190 
191         ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
192 
193 out:
194         pm_runtime_put(phy->io_dev);
195 
196         return ret;
197 }
198 
199 static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
200 {
201         void __iomem *addr = phy->io_priv;
202         int     i = 0;
203         u8      r = 0;
204         u8      power;
205         int     ret = 0;
206 
207         pm_runtime_get_sync(phy->io_dev);
208 
209         /* Make sure the transceiver is not in low power mode */
210         power = musb_readb(addr, MUSB_POWER);
211         power &= ~MUSB_POWER_SUSPENDM;
212         musb_writeb(addr, MUSB_POWER, power);
213 
214         musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
215         musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
216         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
217 
218         while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
219                                 & MUSB_ULPI_REG_CMPLT)) {
220                 i++;
221                 if (i == 10000) {
222                         ret = -ETIMEDOUT;
223                         goto out;
224                 }
225         }
226 
227         r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
228         r &= ~MUSB_ULPI_REG_CMPLT;
229         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
230 
231 out:
232         pm_runtime_put(phy->io_dev);
233 
234         return ret;
235 }
236 #else
237 #define musb_ulpi_read          NULL
238 #define musb_ulpi_write         NULL
239 #endif
240 
241 static struct usb_phy_io_ops musb_ulpi_access = {
242         .read = musb_ulpi_read,
243         .write = musb_ulpi_write,
244 };
245 
246 /*-------------------------------------------------------------------------*/
247 
248 static u32 musb_default_fifo_offset(u8 epnum)
249 {
250         return 0x20 + (epnum * 4);
251 }
252 
253 /* "flat" mapping: each endpoint has its own i/o address */
254 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
255 {
256 }
257 
258 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
259 {
260         return 0x100 + (0x10 * epnum) + offset;
261 }
262 
263 /* "indexed" mapping: INDEX register controls register bank select */
264 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
265 {
266         musb_writeb(mbase, MUSB_INDEX, epnum);
267 }
268 
269 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
270 {
271         return 0x10 + offset;
272 }
273 
274 static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
275 {
276         return 0x80 + (0x08 * epnum) + offset;
277 }
278 
279 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
280 {
281         u8 data =  __raw_readb(addr + offset);
282 
283         trace_musb_readb(__builtin_return_address(0), addr, offset, data);
284         return data;
285 }
286 
287 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
288 {
289         trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
290         __raw_writeb(data, addr + offset);
291 }
292 
293 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
294 {
295         u16 data = __raw_readw(addr + offset);
296 
297         trace_musb_readw(__builtin_return_address(0), addr, offset, data);
298         return data;
299 }
300 
301 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
302 {
303         trace_musb_writew(__builtin_return_address(0), addr, offset, data);
304         __raw_writew(data, addr + offset);
305 }
306 
307 static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
308 {
309         u32 data = __raw_readl(addr + offset);
310 
311         trace_musb_readl(__builtin_return_address(0), addr, offset, data);
312         return data;
313 }
314 
315 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
316 {
317         trace_musb_writel(__builtin_return_address(0), addr, offset, data);
318         __raw_writel(data, addr + offset);
319 }
320 
321 /*
322  * Load an endpoint's FIFO
323  */
324 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
325                                     const u8 *src)
326 {
327         struct musb *musb = hw_ep->musb;
328         void __iomem *fifo = hw_ep->fifo;
329 
330         if (unlikely(len == 0))
331                 return;
332 
333         prefetch((u8 *)src);
334 
335         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
336                         'T', hw_ep->epnum, fifo, len, src);
337 
338         /* we can't assume unaligned reads work */
339         if (likely((0x01 & (unsigned long) src) == 0)) {
340                 u16     index = 0;
341 
342                 /* best case is 32bit-aligned source address */
343                 if ((0x02 & (unsigned long) src) == 0) {
344                         if (len >= 4) {
345                                 iowrite32_rep(fifo, src + index, len >> 2);
346                                 index += len & ~0x03;
347                         }
348                         if (len & 0x02) {
349                                 __raw_writew(*(u16 *)&src[index], fifo);
350                                 index += 2;
351                         }
352                 } else {
353                         if (len >= 2) {
354                                 iowrite16_rep(fifo, src + index, len >> 1);
355                                 index += len & ~0x01;
356                         }
357                 }
358                 if (len & 0x01)
359                         __raw_writeb(src[index], fifo);
360         } else  {
361                 /* byte aligned */
362                 iowrite8_rep(fifo, src, len);
363         }
364 }
365 
366 /*
367  * Unload an endpoint's FIFO
368  */
369 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
370 {
371         struct musb *musb = hw_ep->musb;
372         void __iomem *fifo = hw_ep->fifo;
373 
374         if (unlikely(len == 0))
375                 return;
376 
377         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
378                         'R', hw_ep->epnum, fifo, len, dst);
379 
380         /* we can't assume unaligned writes work */
381         if (likely((0x01 & (unsigned long) dst) == 0)) {
382                 u16     index = 0;
383 
384                 /* best case is 32bit-aligned destination address */
385                 if ((0x02 & (unsigned long) dst) == 0) {
386                         if (len >= 4) {
387                                 ioread32_rep(fifo, dst, len >> 2);
388                                 index = len & ~0x03;
389                         }
390                         if (len & 0x02) {
391                                 *(u16 *)&dst[index] = __raw_readw(fifo);
392                                 index += 2;
393                         }
394                 } else {
395                         if (len >= 2) {
396                                 ioread16_rep(fifo, dst, len >> 1);
397                                 index = len & ~0x01;
398                         }
399                 }
400                 if (len & 0x01)
401                         dst[index] = __raw_readb(fifo);
402         } else  {
403                 /* byte aligned */
404                 ioread8_rep(fifo, dst, len);
405         }
406 }
407 
408 /*
409  * Old style IO functions
410  */
411 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
412 EXPORT_SYMBOL_GPL(musb_readb);
413 
414 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
415 EXPORT_SYMBOL_GPL(musb_writeb);
416 
417 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
418 EXPORT_SYMBOL_GPL(musb_readw);
419 
420 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
421 EXPORT_SYMBOL_GPL(musb_writew);
422 
423 u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
424 EXPORT_SYMBOL_GPL(musb_readl);
425 
426 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
427 EXPORT_SYMBOL_GPL(musb_writel);
428 
429 #ifndef CONFIG_MUSB_PIO_ONLY
430 struct dma_controller *
431 (*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
432 EXPORT_SYMBOL(musb_dma_controller_create);
433 
434 void (*musb_dma_controller_destroy)(struct dma_controller *c);
435 EXPORT_SYMBOL(musb_dma_controller_destroy);
436 #endif
437 
438 /*
439  * New style IO functions
440  */
441 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
442 {
443         return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
444 }
445 
446 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
447 {
448         return hw_ep->musb->io.write_fifo(hw_ep, len, src);
449 }
450 
451 /*-------------------------------------------------------------------------*/
452 
453 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
454 static const u8 musb_test_packet[53] = {
455         /* implicit SYNC then DATA0 to start */
456 
457         /* JKJKJKJK x9 */
458         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
459         /* JJKKJJKK x8 */
460         0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
461         /* JJJJKKKK x8 */
462         0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
463         /* JJJJJJJKKKKKKK x8 */
464         0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
465         /* JJJJJJJK x8 */
466         0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
467         /* JKKKKKKK x10, JK */
468         0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
469 
470         /* implicit CRC16 then EOP to end */
471 };
472 
473 void musb_load_testpacket(struct musb *musb)
474 {
475         void __iomem    *regs = musb->endpoints[0].regs;
476 
477         musb_ep_select(musb->mregs, 0);
478         musb_write_fifo(musb->control_ep,
479                         sizeof(musb_test_packet), musb_test_packet);
480         musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
481 }
482 
483 /*-------------------------------------------------------------------------*/
484 
485 /*
486  * Handles OTG hnp timeouts, such as b_ase0_brst
487  */
488 static void musb_otg_timer_func(unsigned long data)
489 {
490         struct musb     *musb = (struct musb *)data;
491         unsigned long   flags;
492 
493         spin_lock_irqsave(&musb->lock, flags);
494         switch (musb->xceiv->otg->state) {
495         case OTG_STATE_B_WAIT_ACON:
496                 musb_dbg(musb,
497                         "HNP: b_wait_acon timeout; back to b_peripheral");
498                 musb_g_disconnect(musb);
499                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
500                 musb->is_active = 0;
501                 break;
502         case OTG_STATE_A_SUSPEND:
503         case OTG_STATE_A_WAIT_BCON:
504                 musb_dbg(musb, "HNP: %s timeout",
505                         usb_otg_state_string(musb->xceiv->otg->state));
506                 musb_platform_set_vbus(musb, 0);
507                 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
508                 break;
509         default:
510                 musb_dbg(musb, "HNP: Unhandled mode %s",
511                         usb_otg_state_string(musb->xceiv->otg->state));
512         }
513         spin_unlock_irqrestore(&musb->lock, flags);
514 }
515 
516 /*
517  * Stops the HNP transition. Caller must take care of locking.
518  */
519 void musb_hnp_stop(struct musb *musb)
520 {
521         struct usb_hcd  *hcd = musb->hcd;
522         void __iomem    *mbase = musb->mregs;
523         u8      reg;
524 
525         musb_dbg(musb, "HNP: stop from %s",
526                         usb_otg_state_string(musb->xceiv->otg->state));
527 
528         switch (musb->xceiv->otg->state) {
529         case OTG_STATE_A_PERIPHERAL:
530                 musb_g_disconnect(musb);
531                 musb_dbg(musb, "HNP: back to %s",
532                         usb_otg_state_string(musb->xceiv->otg->state));
533                 break;
534         case OTG_STATE_B_HOST:
535                 musb_dbg(musb, "HNP: Disabling HR");
536                 if (hcd)
537                         hcd->self.is_b_host = 0;
538                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
539                 MUSB_DEV_MODE(musb);
540                 reg = musb_readb(mbase, MUSB_POWER);
541                 reg |= MUSB_POWER_SUSPENDM;
542                 musb_writeb(mbase, MUSB_POWER, reg);
543                 /* REVISIT: Start SESSION_REQUEST here? */
544                 break;
545         default:
546                 musb_dbg(musb, "HNP: Stopping in unknown state %s",
547                         usb_otg_state_string(musb->xceiv->otg->state));
548         }
549 
550         /*
551          * When returning to A state after HNP, avoid hub_port_rebounce(),
552          * which cause occasional OPT A "Did not receive reset after connect"
553          * errors.
554          */
555         musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
556 }
557 
558 static void musb_recover_from_babble(struct musb *musb);
559 
560 /*
561  * Interrupt Service Routine to record USB "global" interrupts.
562  * Since these do not happen often and signify things of
563  * paramount importance, it seems OK to check them individually;
564  * the order of the tests is specified in the manual
565  *
566  * @param musb instance pointer
567  * @param int_usb register contents
568  * @param devctl
569  * @param power
570  */
571 
572 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
573                                 u8 devctl)
574 {
575         irqreturn_t handled = IRQ_NONE;
576 
577         musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
578 
579         /* in host mode, the peripheral may issue remote wakeup.
580          * in peripheral mode, the host may resume the link.
581          * spurious RESUME irqs happen too, paired with SUSPEND.
582          */
583         if (int_usb & MUSB_INTR_RESUME) {
584                 handled = IRQ_HANDLED;
585                 musb_dbg(musb, "RESUME (%s)",
586                                 usb_otg_state_string(musb->xceiv->otg->state));
587 
588                 if (devctl & MUSB_DEVCTL_HM) {
589                         switch (musb->xceiv->otg->state) {
590                         case OTG_STATE_A_SUSPEND:
591                                 /* remote wakeup? */
592                                 musb->port1_status |=
593                                                 (USB_PORT_STAT_C_SUSPEND << 16)
594                                                 | MUSB_PORT_STAT_RESUME;
595                                 musb->rh_timer = jiffies
596                                         + msecs_to_jiffies(USB_RESUME_TIMEOUT);
597                                 musb->xceiv->otg->state = OTG_STATE_A_HOST;
598                                 musb->is_active = 1;
599                                 musb_host_resume_root_hub(musb);
600                                 schedule_delayed_work(&musb->finish_resume_work,
601                                         msecs_to_jiffies(USB_RESUME_TIMEOUT));
602                                 break;
603                         case OTG_STATE_B_WAIT_ACON:
604                                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
605                                 musb->is_active = 1;
606                                 MUSB_DEV_MODE(musb);
607                                 break;
608                         default:
609                                 WARNING("bogus %s RESUME (%s)\n",
610                                         "host",
611                                         usb_otg_state_string(musb->xceiv->otg->state));
612                         }
613                 } else {
614                         switch (musb->xceiv->otg->state) {
615                         case OTG_STATE_A_SUSPEND:
616                                 /* possibly DISCONNECT is upcoming */
617                                 musb->xceiv->otg->state = OTG_STATE_A_HOST;
618                                 musb_host_resume_root_hub(musb);
619                                 break;
620                         case OTG_STATE_B_WAIT_ACON:
621                         case OTG_STATE_B_PERIPHERAL:
622                                 /* disconnect while suspended?  we may
623                                  * not get a disconnect irq...
624                                  */
625                                 if ((devctl & MUSB_DEVCTL_VBUS)
626                                                 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
627                                                 ) {
628                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
629                                         musb->int_usb &= ~MUSB_INTR_SUSPEND;
630                                         break;
631                                 }
632                                 musb_g_resume(musb);
633                                 break;
634                         case OTG_STATE_B_IDLE:
635                                 musb->int_usb &= ~MUSB_INTR_SUSPEND;
636                                 break;
637                         default:
638                                 WARNING("bogus %s RESUME (%s)\n",
639                                         "peripheral",
640                                         usb_otg_state_string(musb->xceiv->otg->state));
641                         }
642                 }
643         }
644 
645         /* see manual for the order of the tests */
646         if (int_usb & MUSB_INTR_SESSREQ) {
647                 void __iomem *mbase = musb->mregs;
648 
649                 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
650                                 && (devctl & MUSB_DEVCTL_BDEVICE)) {
651                         musb_dbg(musb, "SessReq while on B state");
652                         return IRQ_HANDLED;
653                 }
654 
655                 musb_dbg(musb, "SESSION_REQUEST (%s)",
656                         usb_otg_state_string(musb->xceiv->otg->state));
657 
658                 /* IRQ arrives from ID pin sense or (later, if VBUS power
659                  * is removed) SRP.  responses are time critical:
660                  *  - turn on VBUS (with silicon-specific mechanism)
661                  *  - go through A_WAIT_VRISE
662                  *  - ... to A_WAIT_BCON.
663                  * a_wait_vrise_tmout triggers VBUS_ERROR transitions
664                  */
665                 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
666                 musb->ep0_stage = MUSB_EP0_START;
667                 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
668                 MUSB_HST_MODE(musb);
669                 musb_platform_set_vbus(musb, 1);
670 
671                 handled = IRQ_HANDLED;
672         }
673 
674         if (int_usb & MUSB_INTR_VBUSERROR) {
675                 int     ignore = 0;
676 
677                 /* During connection as an A-Device, we may see a short
678                  * current spikes causing voltage drop, because of cable
679                  * and peripheral capacitance combined with vbus draw.
680                  * (So: less common with truly self-powered devices, where
681                  * vbus doesn't act like a power supply.)
682                  *
683                  * Such spikes are short; usually less than ~500 usec, max
684                  * of ~2 msec.  That is, they're not sustained overcurrent
685                  * errors, though they're reported using VBUSERROR irqs.
686                  *
687                  * Workarounds:  (a) hardware: use self powered devices.
688                  * (b) software:  ignore non-repeated VBUS errors.
689                  *
690                  * REVISIT:  do delays from lots of DEBUG_KERNEL checks
691                  * make trouble here, keeping VBUS < 4.4V ?
692                  */
693                 switch (musb->xceiv->otg->state) {
694                 case OTG_STATE_A_HOST:
695                         /* recovery is dicey once we've gotten past the
696                          * initial stages of enumeration, but if VBUS
697                          * stayed ok at the other end of the link, and
698                          * another reset is due (at least for high speed,
699                          * to redo the chirp etc), it might work OK...
700                          */
701                 case OTG_STATE_A_WAIT_BCON:
702                 case OTG_STATE_A_WAIT_VRISE:
703                         if (musb->vbuserr_retry) {
704                                 void __iomem *mbase = musb->mregs;
705 
706                                 musb->vbuserr_retry--;
707                                 ignore = 1;
708                                 devctl |= MUSB_DEVCTL_SESSION;
709                                 musb_writeb(mbase, MUSB_DEVCTL, devctl);
710                         } else {
711                                 musb->port1_status |=
712                                           USB_PORT_STAT_OVERCURRENT
713                                         | (USB_PORT_STAT_C_OVERCURRENT << 16);
714                         }
715                         break;
716                 default:
717                         break;
718                 }
719 
720                 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
721                                 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
722                                 usb_otg_state_string(musb->xceiv->otg->state),
723                                 devctl,
724                                 ({ char *s;
725                                 switch (devctl & MUSB_DEVCTL_VBUS) {
726                                 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
727                                         s = "<SessEnd"; break;
728                                 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
729                                         s = "<AValid"; break;
730                                 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
731                                         s = "<VBusValid"; break;
732                                 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
733                                 default:
734                                         s = "VALID"; break;
735                                 } s; }),
736                                 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
737                                 musb->port1_status);
738 
739                 /* go through A_WAIT_VFALL then start a new session */
740                 if (!ignore)
741                         musb_platform_set_vbus(musb, 0);
742                 handled = IRQ_HANDLED;
743         }
744 
745         if (int_usb & MUSB_INTR_SUSPEND) {
746                 musb_dbg(musb, "SUSPEND (%s) devctl %02x",
747                         usb_otg_state_string(musb->xceiv->otg->state), devctl);
748                 handled = IRQ_HANDLED;
749 
750                 switch (musb->xceiv->otg->state) {
751                 case OTG_STATE_A_PERIPHERAL:
752                         /* We also come here if the cable is removed, since
753                          * this silicon doesn't report ID-no-longer-grounded.
754                          *
755                          * We depend on T(a_wait_bcon) to shut us down, and
756                          * hope users don't do anything dicey during this
757                          * undesired detour through A_WAIT_BCON.
758                          */
759                         musb_hnp_stop(musb);
760                         musb_host_resume_root_hub(musb);
761                         musb_root_disconnect(musb);
762                         musb_platform_try_idle(musb, jiffies
763                                         + msecs_to_jiffies(musb->a_wait_bcon
764                                                 ? : OTG_TIME_A_WAIT_BCON));
765 
766                         break;
767                 case OTG_STATE_B_IDLE:
768                         if (!musb->is_active)
769                                 break;
770                 case OTG_STATE_B_PERIPHERAL:
771                         musb_g_suspend(musb);
772                         musb->is_active = musb->g.b_hnp_enable;
773                         if (musb->is_active) {
774                                 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
775                                 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
776                                 mod_timer(&musb->otg_timer, jiffies
777                                         + msecs_to_jiffies(
778                                                         OTG_TIME_B_ASE0_BRST));
779                         }
780                         break;
781                 case OTG_STATE_A_WAIT_BCON:
782                         if (musb->a_wait_bcon != 0)
783                                 musb_platform_try_idle(musb, jiffies
784                                         + msecs_to_jiffies(musb->a_wait_bcon));
785                         break;
786                 case OTG_STATE_A_HOST:
787                         musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
788                         musb->is_active = musb->hcd->self.b_hnp_enable;
789                         break;
790                 case OTG_STATE_B_HOST:
791                         /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
792                         musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
793                         break;
794                 default:
795                         /* "should not happen" */
796                         musb->is_active = 0;
797                         break;
798                 }
799         }
800 
801         if (int_usb & MUSB_INTR_CONNECT) {
802                 struct usb_hcd *hcd = musb->hcd;
803 
804                 handled = IRQ_HANDLED;
805                 musb->is_active = 1;
806 
807                 musb->ep0_stage = MUSB_EP0_START;
808 
809                 musb->intrtxe = musb->epmask;
810                 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
811                 musb->intrrxe = musb->epmask & 0xfffe;
812                 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
813                 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
814                 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
815                                         |USB_PORT_STAT_HIGH_SPEED
816                                         |USB_PORT_STAT_ENABLE
817                                         );
818                 musb->port1_status |= USB_PORT_STAT_CONNECTION
819                                         |(USB_PORT_STAT_C_CONNECTION << 16);
820 
821                 /* high vs full speed is just a guess until after reset */
822                 if (devctl & MUSB_DEVCTL_LSDEV)
823                         musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
824 
825                 /* indicate new connection to OTG machine */
826                 switch (musb->xceiv->otg->state) {
827                 case OTG_STATE_B_PERIPHERAL:
828                         if (int_usb & MUSB_INTR_SUSPEND) {
829                                 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
830                                 int_usb &= ~MUSB_INTR_SUSPEND;
831                                 goto b_host;
832                         } else
833                                 musb_dbg(musb, "CONNECT as b_peripheral???");
834                         break;
835                 case OTG_STATE_B_WAIT_ACON:
836                         musb_dbg(musb, "HNP: CONNECT, now b_host");
837 b_host:
838                         musb->xceiv->otg->state = OTG_STATE_B_HOST;
839                         if (musb->hcd)
840                                 musb->hcd->self.is_b_host = 1;
841                         del_timer(&musb->otg_timer);
842                         break;
843                 default:
844                         if ((devctl & MUSB_DEVCTL_VBUS)
845                                         == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
846                                 musb->xceiv->otg->state = OTG_STATE_A_HOST;
847                                 if (hcd)
848                                         hcd->self.is_b_host = 0;
849                         }
850                         break;
851                 }
852 
853                 musb_host_poke_root_hub(musb);
854 
855                 musb_dbg(musb, "CONNECT (%s) devctl %02x",
856                                 usb_otg_state_string(musb->xceiv->otg->state), devctl);
857         }
858 
859         if (int_usb & MUSB_INTR_DISCONNECT) {
860                 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
861                                 usb_otg_state_string(musb->xceiv->otg->state),
862                                 MUSB_MODE(musb), devctl);
863                 handled = IRQ_HANDLED;
864 
865                 switch (musb->xceiv->otg->state) {
866                 case OTG_STATE_A_HOST:
867                 case OTG_STATE_A_SUSPEND:
868                         musb_host_resume_root_hub(musb);
869                         musb_root_disconnect(musb);
870                         if (musb->a_wait_bcon != 0)
871                                 musb_platform_try_idle(musb, jiffies
872                                         + msecs_to_jiffies(musb->a_wait_bcon));
873                         break;
874                 case OTG_STATE_B_HOST:
875                         /* REVISIT this behaves for "real disconnect"
876                          * cases; make sure the other transitions from
877                          * from B_HOST act right too.  The B_HOST code
878                          * in hnp_stop() is currently not used...
879                          */
880                         musb_root_disconnect(musb);
881                         if (musb->hcd)
882                                 musb->hcd->self.is_b_host = 0;
883                         musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
884                         MUSB_DEV_MODE(musb);
885                         musb_g_disconnect(musb);
886                         break;
887                 case OTG_STATE_A_PERIPHERAL:
888                         musb_hnp_stop(musb);
889                         musb_root_disconnect(musb);
890                         /* FALLTHROUGH */
891                 case OTG_STATE_B_WAIT_ACON:
892                         /* FALLTHROUGH */
893                 case OTG_STATE_B_PERIPHERAL:
894                 case OTG_STATE_B_IDLE:
895                         musb_g_disconnect(musb);
896                         break;
897                 default:
898                         WARNING("unhandled DISCONNECT transition (%s)\n",
899                                 usb_otg_state_string(musb->xceiv->otg->state));
900                         break;
901                 }
902         }
903 
904         /* mentor saves a bit: bus reset and babble share the same irq.
905          * only host sees babble; only peripheral sees bus reset.
906          */
907         if (int_usb & MUSB_INTR_RESET) {
908                 handled = IRQ_HANDLED;
909                 if (devctl & MUSB_DEVCTL_HM) {
910                         /*
911                          * When BABBLE happens what we can depends on which
912                          * platform MUSB is running, because some platforms
913                          * implemented proprietary means for 'recovering' from
914                          * Babble conditions. One such platform is AM335x. In
915                          * most cases, however, the only thing we can do is
916                          * drop the session.
917                          */
918                         dev_err(musb->controller, "Babble\n");
919 
920                         if (is_host_active(musb))
921                                 musb_recover_from_babble(musb);
922                 } else {
923                         musb_dbg(musb, "BUS RESET as %s",
924                                 usb_otg_state_string(musb->xceiv->otg->state));
925                         switch (musb->xceiv->otg->state) {
926                         case OTG_STATE_A_SUSPEND:
927                                 musb_g_reset(musb);
928                                 /* FALLTHROUGH */
929                         case OTG_STATE_A_WAIT_BCON:     /* OPT TD.4.7-900ms */
930                                 /* never use invalid T(a_wait_bcon) */
931                                 musb_dbg(musb, "HNP: in %s, %d msec timeout",
932                                         usb_otg_state_string(musb->xceiv->otg->state),
933                                         TA_WAIT_BCON(musb));
934                                 mod_timer(&musb->otg_timer, jiffies
935                                         + msecs_to_jiffies(TA_WAIT_BCON(musb)));
936                                 break;
937                         case OTG_STATE_A_PERIPHERAL:
938                                 del_timer(&musb->otg_timer);
939                                 musb_g_reset(musb);
940                                 break;
941                         case OTG_STATE_B_WAIT_ACON:
942                                 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
943                                         usb_otg_state_string(musb->xceiv->otg->state));
944                                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
945                                 musb_g_reset(musb);
946                                 break;
947                         case OTG_STATE_B_IDLE:
948                                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
949                                 /* FALLTHROUGH */
950                         case OTG_STATE_B_PERIPHERAL:
951                                 musb_g_reset(musb);
952                                 break;
953                         default:
954                                 musb_dbg(musb, "Unhandled BUS RESET as %s",
955                                         usb_otg_state_string(musb->xceiv->otg->state));
956                         }
957                 }
958         }
959 
960 #if 0
961 /* REVISIT ... this would be for multiplexing periodic endpoints, or
962  * supporting transfer phasing to prevent exceeding ISO bandwidth
963  * limits of a given frame or microframe.
964  *
965  * It's not needed for peripheral side, which dedicates endpoints;
966  * though it _might_ use SOF irqs for other purposes.
967  *
968  * And it's not currently needed for host side, which also dedicates
969  * endpoints, relies on TX/RX interval registers, and isn't claimed
970  * to support ISO transfers yet.
971  */
972         if (int_usb & MUSB_INTR_SOF) {
973                 void __iomem *mbase = musb->mregs;
974                 struct musb_hw_ep       *ep;
975                 u8 epnum;
976                 u16 frame;
977 
978                 dev_dbg(musb->controller, "START_OF_FRAME\n");
979                 handled = IRQ_HANDLED;
980 
981                 /* start any periodic Tx transfers waiting for current frame */
982                 frame = musb_readw(mbase, MUSB_FRAME);
983                 ep = musb->endpoints;
984                 for (epnum = 1; (epnum < musb->nr_endpoints)
985                                         && (musb->epmask >= (1 << epnum));
986                                 epnum++, ep++) {
987                         /*
988                          * FIXME handle framecounter wraps (12 bits)
989                          * eliminate duplicated StartUrb logic
990                          */
991                         if (ep->dwWaitFrame >= frame) {
992                                 ep->dwWaitFrame = 0;
993                                 pr_debug("SOF --> periodic TX%s on %d\n",
994                                         ep->tx_channel ? " DMA" : "",
995                                         epnum);
996                                 if (!ep->tx_channel)
997                                         musb_h_tx_start(musb, epnum);
998                                 else
999                                         cppi_hostdma_start(musb, epnum);
1000                         }
1001                 }               /* end of for loop */
1002         }
1003 #endif
1004 
1005         schedule_delayed_work(&musb->irq_work, 0);
1006 
1007         return handled;
1008 }
1009 
1010 /*-------------------------------------------------------------------------*/
1011 
1012 static void musb_disable_interrupts(struct musb *musb)
1013 {
1014         void __iomem    *mbase = musb->mregs;
1015         u16     temp;
1016 
1017         /* disable interrupts */
1018         musb_writeb(mbase, MUSB_INTRUSBE, 0);
1019         musb->intrtxe = 0;
1020         musb_writew(mbase, MUSB_INTRTXE, 0);
1021         musb->intrrxe = 0;
1022         musb_writew(mbase, MUSB_INTRRXE, 0);
1023 
1024         /*  flush pending interrupts */
1025         temp = musb_readb(mbase, MUSB_INTRUSB);
1026         temp = musb_readw(mbase, MUSB_INTRTX);
1027         temp = musb_readw(mbase, MUSB_INTRRX);
1028 }
1029 
1030 static void musb_enable_interrupts(struct musb *musb)
1031 {
1032         void __iomem    *regs = musb->mregs;
1033 
1034         /*  Set INT enable registers, enable interrupts */
1035         musb->intrtxe = musb->epmask;
1036         musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1037         musb->intrrxe = musb->epmask & 0xfffe;
1038         musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1039         musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1040 
1041 }
1042 
1043 static void musb_generic_disable(struct musb *musb)
1044 {
1045         void __iomem    *mbase = musb->mregs;
1046 
1047         musb_disable_interrupts(musb);
1048 
1049         /* off */
1050         musb_writeb(mbase, MUSB_DEVCTL, 0);
1051 }
1052 
1053 /*
1054  * Program the HDRC to start (enable interrupts, dma, etc.).
1055  */
1056 void musb_start(struct musb *musb)
1057 {
1058         void __iomem    *regs = musb->mregs;
1059         u8              devctl = musb_readb(regs, MUSB_DEVCTL);
1060         u8              power;
1061 
1062         musb_dbg(musb, "<== devctl %02x", devctl);
1063 
1064         musb_enable_interrupts(musb);
1065         musb_writeb(regs, MUSB_TESTMODE, 0);
1066 
1067         power = MUSB_POWER_ISOUPDATE;
1068         /*
1069          * treating UNKNOWN as unspecified maximum speed, in which case
1070          * we will default to high-speed.
1071          */
1072         if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1073                         musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1074                 power |= MUSB_POWER_HSENAB;
1075         musb_writeb(regs, MUSB_POWER, power);
1076 
1077         musb->is_active = 0;
1078         devctl = musb_readb(regs, MUSB_DEVCTL);
1079         devctl &= ~MUSB_DEVCTL_SESSION;
1080 
1081         /* session started after:
1082          * (a) ID-grounded irq, host mode;
1083          * (b) vbus present/connect IRQ, peripheral mode;
1084          * (c) peripheral initiates, using SRP
1085          */
1086         if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1087                         musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1088                         (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1089                 musb->is_active = 1;
1090         } else {
1091                 devctl |= MUSB_DEVCTL_SESSION;
1092         }
1093 
1094         musb_platform_enable(musb);
1095         musb_writeb(regs, MUSB_DEVCTL, devctl);
1096 }
1097 
1098 /*
1099  * Make the HDRC stop (disable interrupts, etc.);
1100  * reversible by musb_start
1101  * called on gadget driver unregister
1102  * with controller locked, irqs blocked
1103  * acts as a NOP unless some role activated the hardware
1104  */
1105 void musb_stop(struct musb *musb)
1106 {
1107         /* stop IRQs, timers, ... */
1108         musb_platform_disable(musb);
1109         musb_generic_disable(musb);
1110         musb_dbg(musb, "HDRC disabled");
1111 
1112         /* FIXME
1113          *  - mark host and/or peripheral drivers unusable/inactive
1114          *  - disable DMA (and enable it in HdrcStart)
1115          *  - make sure we can musb_start() after musb_stop(); with
1116          *    OTG mode, gadget driver module rmmod/modprobe cycles that
1117          *  - ...
1118          */
1119         musb_platform_try_idle(musb, 0);
1120 }
1121 
1122 /*-------------------------------------------------------------------------*/
1123 
1124 /*
1125  * The silicon either has hard-wired endpoint configurations, or else
1126  * "dynamic fifo" sizing.  The driver has support for both, though at this
1127  * writing only the dynamic sizing is very well tested.   Since we switched
1128  * away from compile-time hardware parameters, we can no longer rely on
1129  * dead code elimination to leave only the relevant one in the object file.
1130  *
1131  * We don't currently use dynamic fifo setup capability to do anything
1132  * more than selecting one of a bunch of predefined configurations.
1133  */
1134 static ushort fifo_mode;
1135 
1136 /* "modprobe ... fifo_mode=1" etc */
1137 module_param(fifo_mode, ushort, 0);
1138 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1139 
1140 /*
1141  * tables defining fifo_mode values.  define more if you like.
1142  * for host side, make sure both halves of ep1 are set up.
1143  */
1144 
1145 /* mode 0 - fits in 2KB */
1146 static struct musb_fifo_cfg mode_0_cfg[] = {
1147 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1148 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1149 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1150 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1151 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1152 };
1153 
1154 /* mode 1 - fits in 4KB */
1155 static struct musb_fifo_cfg mode_1_cfg[] = {
1156 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1157 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1158 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1159 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1160 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1161 };
1162 
1163 /* mode 2 - fits in 4KB */
1164 static struct musb_fifo_cfg mode_2_cfg[] = {
1165 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1166 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1167 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1168 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1169 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1170 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1171 };
1172 
1173 /* mode 3 - fits in 4KB */
1174 static struct musb_fifo_cfg mode_3_cfg[] = {
1175 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1176 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1177 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1178 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1179 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1180 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1181 };
1182 
1183 /* mode 4 - fits in 16KB */
1184 static struct musb_fifo_cfg mode_4_cfg[] = {
1185 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1186 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1187 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1188 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1189 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1190 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1191 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1192 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1193 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1194 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1195 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 512, },
1196 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 512, },
1197 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 512, },
1198 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 512, },
1199 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 512, },
1200 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
1201 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
1202 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
1203 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
1204 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
1205 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
1206 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
1207 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
1208 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
1209 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1210 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1211 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1212 };
1213 
1214 /* mode 5 - fits in 8KB */
1215 static struct musb_fifo_cfg mode_5_cfg[] = {
1216 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1217 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1218 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1219 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1220 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1221 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1222 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1223 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1224 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1225 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1226 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 32, },
1227 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 32, },
1228 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 32, },
1229 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 32, },
1230 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 32, },
1231 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 32, },
1232 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 32, },
1233 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 32, },
1234 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 32, },
1235 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 32, },
1236 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 32, },
1237 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 32, },
1238 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 32, },
1239 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 32, },
1240 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1241 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1242 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1243 };
1244 
1245 /*
1246  * configure a fifo; for non-shared endpoints, this may be called
1247  * once for a tx fifo and once for an rx fifo.
1248  *
1249  * returns negative errno or offset for next fifo.
1250  */
1251 static int
1252 fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
1253                 const struct musb_fifo_cfg *cfg, u16 offset)
1254 {
1255         void __iomem    *mbase = musb->mregs;
1256         int     size = 0;
1257         u16     maxpacket = cfg->maxpacket;
1258         u16     c_off = offset >> 3;
1259         u8      c_size;
1260 
1261         /* expect hw_ep has already been zero-initialized */
1262 
1263         size = ffs(max(maxpacket, (u16) 8)) - 1;
1264         maxpacket = 1 << size;
1265 
1266         c_size = size - 3;
1267         if (cfg->mode == BUF_DOUBLE) {
1268                 if ((offset + (maxpacket << 1)) >
1269                                 (1 << (musb->config->ram_bits + 2)))
1270                         return -EMSGSIZE;
1271                 c_size |= MUSB_FIFOSZ_DPB;
1272         } else {
1273                 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1274                         return -EMSGSIZE;
1275         }
1276 
1277         /* configure the FIFO */
1278         musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1279 
1280         /* EP0 reserved endpoint for control, bidirectional;
1281          * EP1 reserved for bulk, two unidirectional halves.
1282          */
1283         if (hw_ep->epnum == 1)
1284                 musb->bulk_ep = hw_ep;
1285         /* REVISIT error check:  be sure ep0 can both rx and tx ... */
1286         switch (cfg->style) {
1287         case FIFO_TX:
1288                 musb_write_txfifosz(mbase, c_size);
1289                 musb_write_txfifoadd(mbase, c_off);
1290                 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1291                 hw_ep->max_packet_sz_tx = maxpacket;
1292                 break;
1293         case FIFO_RX:
1294                 musb_write_rxfifosz(mbase, c_size);
1295                 musb_write_rxfifoadd(mbase, c_off);
1296                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1297                 hw_ep->max_packet_sz_rx = maxpacket;
1298                 break;
1299         case FIFO_RXTX:
1300                 musb_write_txfifosz(mbase, c_size);
1301                 musb_write_txfifoadd(mbase, c_off);
1302                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1303                 hw_ep->max_packet_sz_rx = maxpacket;
1304 
1305                 musb_write_rxfifosz(mbase, c_size);
1306                 musb_write_rxfifoadd(mbase, c_off);
1307                 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1308                 hw_ep->max_packet_sz_tx = maxpacket;
1309 
1310                 hw_ep->is_shared_fifo = true;
1311                 break;
1312         }
1313 
1314         /* NOTE rx and tx endpoint irqs aren't managed separately,
1315          * which happens to be ok
1316          */
1317         musb->epmask |= (1 << hw_ep->epnum);
1318 
1319         return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1320 }
1321 
1322 static struct musb_fifo_cfg ep0_cfg = {
1323         .style = FIFO_RXTX, .maxpacket = 64,
1324 };
1325 
1326 static int ep_config_from_table(struct musb *musb)
1327 {
1328         const struct musb_fifo_cfg      *cfg;
1329         unsigned                i, n;
1330         int                     offset;
1331         struct musb_hw_ep       *hw_ep = musb->endpoints;
1332 
1333         if (musb->config->fifo_cfg) {
1334                 cfg = musb->config->fifo_cfg;
1335                 n = musb->config->fifo_cfg_size;
1336                 goto done;
1337         }
1338 
1339         switch (fifo_mode) {
1340         default:
1341                 fifo_mode = 0;
1342                 /* FALLTHROUGH */
1343         case 0:
1344                 cfg = mode_0_cfg;
1345                 n = ARRAY_SIZE(mode_0_cfg);
1346                 break;
1347         case 1:
1348                 cfg = mode_1_cfg;
1349                 n = ARRAY_SIZE(mode_1_cfg);
1350                 break;
1351         case 2:
1352                 cfg = mode_2_cfg;
1353                 n = ARRAY_SIZE(mode_2_cfg);
1354                 break;
1355         case 3:
1356                 cfg = mode_3_cfg;
1357                 n = ARRAY_SIZE(mode_3_cfg);
1358                 break;
1359         case 4:
1360                 cfg = mode_4_cfg;
1361                 n = ARRAY_SIZE(mode_4_cfg);
1362                 break;
1363         case 5:
1364                 cfg = mode_5_cfg;
1365                 n = ARRAY_SIZE(mode_5_cfg);
1366                 break;
1367         }
1368 
1369         pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1370 
1371 
1372 done:
1373         offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1374         /* assert(offset > 0) */
1375 
1376         /* NOTE:  for RTL versions >= 1.400 EPINFO and RAMINFO would
1377          * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1378          */
1379 
1380         for (i = 0; i < n; i++) {
1381                 u8      epn = cfg->hw_ep_num;
1382 
1383                 if (epn >= musb->config->num_eps) {
1384                         pr_debug("%s: invalid ep %d\n",
1385                                         musb_driver_name, epn);
1386                         return -EINVAL;
1387                 }
1388                 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1389                 if (offset < 0) {
1390                         pr_debug("%s: mem overrun, ep %d\n",
1391                                         musb_driver_name, epn);
1392                         return offset;
1393                 }
1394                 epn++;
1395                 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1396         }
1397 
1398         pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1399                         musb_driver_name,
1400                         n + 1, musb->config->num_eps * 2 - 1,
1401                         offset, (1 << (musb->config->ram_bits + 2)));
1402 
1403         if (!musb->bulk_ep) {
1404                 pr_debug("%s: missing bulk\n", musb_driver_name);
1405                 return -EINVAL;
1406         }
1407 
1408         return 0;
1409 }
1410 
1411 
1412 /*
1413  * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1414  * @param musb the controller
1415  */
1416 static int ep_config_from_hw(struct musb *musb)
1417 {
1418         u8 epnum = 0;
1419         struct musb_hw_ep *hw_ep;
1420         void __iomem *mbase = musb->mregs;
1421         int ret = 0;
1422 
1423         musb_dbg(musb, "<== static silicon ep config");
1424 
1425         /* FIXME pick up ep0 maxpacket size */
1426 
1427         for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1428                 musb_ep_select(mbase, epnum);
1429                 hw_ep = musb->endpoints + epnum;
1430 
1431                 ret = musb_read_fifosize(musb, hw_ep, epnum);
1432                 if (ret < 0)
1433                         break;
1434 
1435                 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1436 
1437                 /* pick an RX/TX endpoint for bulk */
1438                 if (hw_ep->max_packet_sz_tx < 512
1439                                 || hw_ep->max_packet_sz_rx < 512)
1440                         continue;
1441 
1442                 /* REVISIT:  this algorithm is lazy, we should at least
1443                  * try to pick a double buffered endpoint.
1444                  */
1445                 if (musb->bulk_ep)
1446                         continue;
1447                 musb->bulk_ep = hw_ep;
1448         }
1449 
1450         if (!musb->bulk_ep) {
1451                 pr_debug("%s: missing bulk\n", musb_driver_name);
1452                 return -EINVAL;
1453         }
1454 
1455         return 0;
1456 }
1457 
1458 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1459 
1460 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1461  * configure endpoints, or take their config from silicon
1462  */
1463 static int musb_core_init(u16 musb_type, struct musb *musb)
1464 {
1465         u8 reg;
1466         char *type;
1467         char aInfo[90];
1468         void __iomem    *mbase = musb->mregs;
1469         int             status = 0;
1470         int             i;
1471 
1472         /* log core options (read using indexed model) */
1473         reg = musb_read_configdata(mbase);
1474 
1475         strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1476         if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1477                 strcat(aInfo, ", dyn FIFOs");
1478                 musb->dyn_fifo = true;
1479         }
1480         if (reg & MUSB_CONFIGDATA_MPRXE) {
1481                 strcat(aInfo, ", bulk combine");
1482                 musb->bulk_combine = true;
1483         }
1484         if (reg & MUSB_CONFIGDATA_MPTXE) {
1485                 strcat(aInfo, ", bulk split");
1486                 musb->bulk_split = true;
1487         }
1488         if (reg & MUSB_CONFIGDATA_HBRXE) {
1489                 strcat(aInfo, ", HB-ISO Rx");
1490                 musb->hb_iso_rx = true;
1491         }
1492         if (reg & MUSB_CONFIGDATA_HBTXE) {
1493                 strcat(aInfo, ", HB-ISO Tx");
1494                 musb->hb_iso_tx = true;
1495         }
1496         if (reg & MUSB_CONFIGDATA_SOFTCONE)
1497                 strcat(aInfo, ", SoftConn");
1498 
1499         pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1500 
1501         if (MUSB_CONTROLLER_MHDRC == musb_type) {
1502                 musb->is_multipoint = 1;
1503                 type = "M";
1504         } else {
1505                 musb->is_multipoint = 0;
1506                 type = "";
1507 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1508                 pr_err("%s: kernel must blacklist external hubs\n",
1509                        musb_driver_name);
1510 #endif
1511         }
1512 
1513         /* log release info */
1514         musb->hwvers = musb_read_hwvers(mbase);
1515         pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1516                  musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1517                  MUSB_HWVERS_MINOR(musb->hwvers),
1518                  (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1519 
1520         /* configure ep0 */
1521         musb_configure_ep0(musb);
1522 
1523         /* discover endpoint configuration */
1524         musb->nr_endpoints = 1;
1525         musb->epmask = 1;
1526 
1527         if (musb->dyn_fifo)
1528                 status = ep_config_from_table(musb);
1529         else
1530                 status = ep_config_from_hw(musb);
1531 
1532         if (status < 0)
1533                 return status;
1534 
1535         /* finish init, and print endpoint config */
1536         for (i = 0; i < musb->nr_endpoints; i++) {
1537                 struct musb_hw_ep       *hw_ep = musb->endpoints + i;
1538 
1539                 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1540 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1541                 if (musb->io.quirks & MUSB_IN_TUSB) {
1542                         hw_ep->fifo_async = musb->async + 0x400 +
1543                                 musb->io.fifo_offset(i);
1544                         hw_ep->fifo_sync = musb->sync + 0x400 +
1545                                 musb->io.fifo_offset(i);
1546                         hw_ep->fifo_sync_va =
1547                                 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1548 
1549                         if (i == 0)
1550                                 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1551                         else
1552                                 hw_ep->conf = mbase + 0x400 +
1553                                         (((i - 1) & 0xf) << 2);
1554                 }
1555 #endif
1556 
1557                 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1558                 hw_ep->rx_reinit = 1;
1559                 hw_ep->tx_reinit = 1;
1560 
1561                 if (hw_ep->max_packet_sz_tx) {
1562                         musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1563                                 musb_driver_name, i,
1564                                 hw_ep->is_shared_fifo ? "shared" : "tx",
1565                                 hw_ep->tx_double_buffered
1566                                         ? "doublebuffer, " : "",
1567                                 hw_ep->max_packet_sz_tx);
1568                 }
1569                 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1570                         musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1571                                 musb_driver_name, i,
1572                                 "rx",
1573                                 hw_ep->rx_double_buffered
1574                                         ? "doublebuffer, " : "",
1575                                 hw_ep->max_packet_sz_rx);
1576                 }
1577                 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1578                         musb_dbg(musb, "hw_ep %d not configured", i);
1579         }
1580 
1581         return 0;
1582 }
1583 
1584 /*-------------------------------------------------------------------------*/
1585 
1586 /*
1587  * handle all the irqs defined by the HDRC core. for now we expect:  other
1588  * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1589  * will be assigned, and the irq will already have been acked.
1590  *
1591  * called in irq context with spinlock held, irqs blocked
1592  */
1593 irqreturn_t musb_interrupt(struct musb *musb)
1594 {
1595         irqreturn_t     retval = IRQ_NONE;
1596         unsigned long   status;
1597         unsigned long   epnum;
1598         u8              devctl;
1599 
1600         if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1601                 return IRQ_NONE;
1602 
1603         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1604 
1605         trace_musb_isr(musb);
1606 
1607         /**
1608          * According to Mentor Graphics' documentation, flowchart on page 98,
1609          * IRQ should be handled as follows:
1610          *
1611          * . Resume IRQ
1612          * . Session Request IRQ
1613          * . VBUS Error IRQ
1614          * . Suspend IRQ
1615          * . Connect IRQ
1616          * . Disconnect IRQ
1617          * . Reset/Babble IRQ
1618          * . SOF IRQ (we're not using this one)
1619          * . Endpoint 0 IRQ
1620          * . TX Endpoints
1621          * . RX Endpoints
1622          *
1623          * We will be following that flowchart in order to avoid any problems
1624          * that might arise with internal Finite State Machine.
1625          */
1626 
1627         if (musb->int_usb)
1628                 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1629 
1630         if (musb->int_tx & 1) {
1631                 if (is_host_active(musb))
1632                         retval |= musb_h_ep0_irq(musb);
1633                 else
1634                         retval |= musb_g_ep0_irq(musb);
1635 
1636                 /* we have just handled endpoint 0 IRQ, clear it */
1637                 musb->int_tx &= ~BIT(0);
1638         }
1639 
1640         status = musb->int_tx;
1641 
1642         for_each_set_bit(epnum, &status, 16) {
1643                 retval = IRQ_HANDLED;
1644                 if (is_host_active(musb))
1645                         musb_host_tx(musb, epnum);
1646                 else
1647                         musb_g_tx(musb, epnum);
1648         }
1649 
1650         status = musb->int_rx;
1651 
1652         for_each_set_bit(epnum, &status, 16) {
1653                 retval = IRQ_HANDLED;
1654                 if (is_host_active(musb))
1655                         musb_host_rx(musb, epnum);
1656                 else
1657                         musb_g_rx(musb, epnum);
1658         }
1659 
1660         return retval;
1661 }
1662 EXPORT_SYMBOL_GPL(musb_interrupt);
1663 
1664 #ifndef CONFIG_MUSB_PIO_ONLY
1665 static bool use_dma = 1;
1666 
1667 /* "modprobe ... use_dma=0" etc */
1668 module_param(use_dma, bool, 0644);
1669 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1670 
1671 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1672 {
1673         /* called with controller lock already held */
1674 
1675         if (!epnum) {
1676                 if (!is_cppi_enabled(musb)) {
1677                         /* endpoint 0 */
1678                         if (is_host_active(musb))
1679                                 musb_h_ep0_irq(musb);
1680                         else
1681                                 musb_g_ep0_irq(musb);
1682                 }
1683         } else {
1684                 /* endpoints 1..15 */
1685                 if (transmit) {
1686                         if (is_host_active(musb))
1687                                 musb_host_tx(musb, epnum);
1688                         else
1689                                 musb_g_tx(musb, epnum);
1690                 } else {
1691                         /* receive */
1692                         if (is_host_active(musb))
1693                                 musb_host_rx(musb, epnum);
1694                         else
1695                                 musb_g_rx(musb, epnum);
1696                 }
1697         }
1698 }
1699 EXPORT_SYMBOL_GPL(musb_dma_completion);
1700 
1701 #else
1702 #define use_dma                 0
1703 #endif
1704 
1705 static int (*musb_phy_callback)(enum musb_vbus_id_status status);
1706 
1707 /*
1708  * musb_mailbox - optional phy notifier function
1709  * @status phy state change
1710  *
1711  * Optionally gets called from the USB PHY. Note that the USB PHY must be
1712  * disabled at the point the phy_callback is registered or unregistered.
1713  */
1714 int musb_mailbox(enum musb_vbus_id_status status)
1715 {
1716         if (musb_phy_callback)
1717                 return musb_phy_callback(status);
1718 
1719         return -ENODEV;
1720 };
1721 EXPORT_SYMBOL_GPL(musb_mailbox);
1722 
1723 /*-------------------------------------------------------------------------*/
1724 
1725 static ssize_t
1726 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1727 {
1728         struct musb *musb = dev_to_musb(dev);
1729         unsigned long flags;
1730         int ret = -EINVAL;
1731 
1732         spin_lock_irqsave(&musb->lock, flags);
1733         ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1734         spin_unlock_irqrestore(&musb->lock, flags);
1735 
1736         return ret;
1737 }
1738 
1739 static ssize_t
1740 musb_mode_store(struct device *dev, struct device_attribute *attr,
1741                 const char *buf, size_t n)
1742 {
1743         struct musb     *musb = dev_to_musb(dev);
1744         unsigned long   flags;
1745         int             status;
1746 
1747         spin_lock_irqsave(&musb->lock, flags);
1748         if (sysfs_streq(buf, "host"))
1749                 status = musb_platform_set_mode(musb, MUSB_HOST);
1750         else if (sysfs_streq(buf, "peripheral"))
1751                 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1752         else if (sysfs_streq(buf, "otg"))
1753                 status = musb_platform_set_mode(musb, MUSB_OTG);
1754         else
1755                 status = -EINVAL;
1756         spin_unlock_irqrestore(&musb->lock, flags);
1757 
1758         return (status == 0) ? n : status;
1759 }
1760 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1761 
1762 static ssize_t
1763 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1764                 const char *buf, size_t n)
1765 {
1766         struct musb     *musb = dev_to_musb(dev);
1767         unsigned long   flags;
1768         unsigned long   val;
1769 
1770         if (sscanf(buf, "%lu", &val) < 1) {
1771                 dev_err(dev, "Invalid VBUS timeout ms value\n");
1772                 return -EINVAL;
1773         }
1774 
1775         spin_lock_irqsave(&musb->lock, flags);
1776         /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1777         musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1778         if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1779                 musb->is_active = 0;
1780         musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1781         spin_unlock_irqrestore(&musb->lock, flags);
1782 
1783         return n;
1784 }
1785 
1786 static ssize_t
1787 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1788 {
1789         struct musb     *musb = dev_to_musb(dev);
1790         unsigned long   flags;
1791         unsigned long   val;
1792         int             vbus;
1793         u8              devctl;
1794 
1795         spin_lock_irqsave(&musb->lock, flags);
1796         val = musb->a_wait_bcon;
1797         vbus = musb_platform_get_vbus_status(musb);
1798         if (vbus < 0) {
1799                 /* Use default MUSB method by means of DEVCTL register */
1800                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1801                 if ((devctl & MUSB_DEVCTL_VBUS)
1802                                 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1803                         vbus = 1;
1804                 else
1805                         vbus = 0;
1806         }
1807         spin_unlock_irqrestore(&musb->lock, flags);
1808 
1809         return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1810                         vbus ? "on" : "off", val);
1811 }
1812 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1813 
1814 /* Gadget drivers can't know that a host is connected so they might want
1815  * to start SRP, but users can.  This allows userspace to trigger SRP.
1816  */
1817 static ssize_t
1818 musb_srp_store(struct device *dev, struct device_attribute *attr,
1819                 const char *buf, size_t n)
1820 {
1821         struct musb     *musb = dev_to_musb(dev);
1822         unsigned short  srp;
1823 
1824         if (sscanf(buf, "%hu", &srp) != 1
1825                         || (srp != 1)) {
1826                 dev_err(dev, "SRP: Value must be 1\n");
1827                 return -EINVAL;
1828         }
1829 
1830         if (srp == 1)
1831                 musb_g_wakeup(musb);
1832 
1833         return n;
1834 }
1835 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1836 
1837 static struct attribute *musb_attributes[] = {
1838         &dev_attr_mode.attr,
1839         &dev_attr_vbus.attr,
1840         &dev_attr_srp.attr,
1841         NULL
1842 };
1843 
1844 static const struct attribute_group musb_attr_group = {
1845         .attrs = musb_attributes,
1846 };
1847 
1848 #define MUSB_QUIRK_B_INVALID_VBUS_91    (MUSB_DEVCTL_BDEVICE | \
1849                                          (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1850                                          MUSB_DEVCTL_SESSION)
1851 #define MUSB_QUIRK_A_DISCONNECT_19      ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1852                                          MUSB_DEVCTL_SESSION)
1853 
1854 /*
1855  * Check the musb devctl session bit to determine if we want to
1856  * allow PM runtime for the device. In general, we want to keep things
1857  * active when the session bit is set except after host disconnect.
1858  *
1859  * Only called from musb_irq_work. If this ever needs to get called
1860  * elsewhere, proper locking must be implemented for musb->session.
1861  */
1862 static void musb_pm_runtime_check_session(struct musb *musb)
1863 {
1864         u8 devctl, s;
1865         int error;
1866 
1867         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1868 
1869         /* Handle session status quirks first */
1870         s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
1871                 MUSB_DEVCTL_HR;
1872         switch (devctl & ~s) {
1873         case MUSB_QUIRK_B_INVALID_VBUS_91:
1874                 if (musb->quirk_retries--) {
1875                         musb_dbg(musb,
1876                                  "Poll devctl on invalid vbus, assume no session");
1877                         schedule_delayed_work(&musb->irq_work,
1878                                               msecs_to_jiffies(1000));
1879 
1880                         return;
1881                 }
1882         case MUSB_QUIRK_A_DISCONNECT_19:
1883                 if (musb->quirk_retries--) {
1884                         musb_dbg(musb,
1885                                  "Poll devctl on possible host mode disconnect");
1886                         schedule_delayed_work(&musb->irq_work,
1887                                               msecs_to_jiffies(1000));
1888 
1889                         return;
1890                 }
1891                 if (!musb->session)
1892                         break;
1893                 musb_dbg(musb, "Allow PM on possible host mode disconnect");
1894                 pm_runtime_mark_last_busy(musb->controller);
1895                 pm_runtime_put_autosuspend(musb->controller);
1896                 musb->session = false;
1897                 return;
1898         default:
1899                 break;
1900         }
1901 
1902         /* No need to do anything if session has not changed */
1903         s = devctl & MUSB_DEVCTL_SESSION;
1904         if (s == musb->session)
1905                 return;
1906 
1907         /* Block PM or allow PM? */
1908         if (s) {
1909                 musb_dbg(musb, "Block PM on active session: %02x", devctl);
1910                 error = pm_runtime_get_sync(musb->controller);
1911                 if (error < 0)
1912                         dev_err(musb->controller, "Could not enable: %i\n",
1913                                 error);
1914                 musb->quirk_retries = 3;
1915         } else {
1916                 musb_dbg(musb, "Allow PM with no session: %02x", devctl);
1917                 pm_runtime_mark_last_busy(musb->controller);
1918                 pm_runtime_put_autosuspend(musb->controller);
1919         }
1920 
1921         musb->session = s;
1922 }
1923 
1924 /* Only used to provide driver mode change events */
1925 static void musb_irq_work(struct work_struct *data)
1926 {
1927         struct musb *musb = container_of(data, struct musb, irq_work.work);
1928         int error;
1929 
1930         error = pm_runtime_get_sync(musb->controller);
1931         if (error < 0) {
1932                 dev_err(musb->controller, "Could not enable: %i\n", error);
1933 
1934                 return;
1935         }
1936 
1937         musb_pm_runtime_check_session(musb);
1938 
1939         if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1940                 musb->xceiv_old_state = musb->xceiv->otg->state;
1941                 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1942         }
1943 
1944         pm_runtime_mark_last_busy(musb->controller);
1945         pm_runtime_put_autosuspend(musb->controller);
1946 }
1947 
1948 static void musb_recover_from_babble(struct musb *musb)
1949 {
1950         int ret;
1951         u8 devctl;
1952 
1953         musb_disable_interrupts(musb);
1954 
1955         /*
1956          * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1957          * it some slack and wait for 10us.
1958          */
1959         udelay(10);
1960 
1961         ret  = musb_platform_recover(musb);
1962         if (ret) {
1963                 musb_enable_interrupts(musb);
1964                 return;
1965         }
1966 
1967         /* drop session bit */
1968         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1969         devctl &= ~MUSB_DEVCTL_SESSION;
1970         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1971 
1972         /* tell usbcore about it */
1973         musb_root_disconnect(musb);
1974 
1975         /*
1976          * When a babble condition occurs, the musb controller
1977          * removes the session bit and the endpoint config is lost.
1978          */
1979         if (musb->dyn_fifo)
1980                 ret = ep_config_from_table(musb);
1981         else
1982                 ret = ep_config_from_hw(musb);
1983 
1984         /* restart session */
1985         if (ret == 0)
1986                 musb_start(musb);
1987 }
1988 
1989 /* --------------------------------------------------------------------------
1990  * Init support
1991  */
1992 
1993 static struct musb *allocate_instance(struct device *dev,
1994                 const struct musb_hdrc_config *config, void __iomem *mbase)
1995 {
1996         struct musb             *musb;
1997         struct musb_hw_ep       *ep;
1998         int                     epnum;
1999         int                     ret;
2000 
2001         musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
2002         if (!musb)
2003                 return NULL;
2004 
2005         INIT_LIST_HEAD(&musb->control);
2006         INIT_LIST_HEAD(&musb->in_bulk);
2007         INIT_LIST_HEAD(&musb->out_bulk);
2008         INIT_LIST_HEAD(&musb->pending_list);
2009 
2010         musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
2011         musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
2012         musb->mregs = mbase;
2013         musb->ctrl_base = mbase;
2014         musb->nIrq = -ENODEV;
2015         musb->config = config;
2016         BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
2017         for (epnum = 0, ep = musb->endpoints;
2018                         epnum < musb->config->num_eps;
2019                         epnum++, ep++) {
2020                 ep->musb = musb;
2021                 ep->epnum = epnum;
2022         }
2023 
2024         musb->controller = dev;
2025 
2026         ret = musb_host_alloc(musb);
2027         if (ret < 0)
2028                 goto err_free;
2029 
2030         dev_set_drvdata(dev, musb);
2031 
2032         return musb;
2033 
2034 err_free:
2035         return NULL;
2036 }
2037 
2038 static void musb_free(struct musb *musb)
2039 {
2040         /* this has multiple entry modes. it handles fault cleanup after
2041          * probe(), where things may be partially set up, as well as rmmod
2042          * cleanup after everything's been de-activated.
2043          */
2044 
2045 #ifdef CONFIG_SYSFS
2046         sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
2047 #endif
2048 
2049         if (musb->nIrq >= 0) {
2050                 if (musb->irq_wake)
2051                         disable_irq_wake(musb->nIrq);
2052                 free_irq(musb->nIrq, musb);
2053         }
2054 
2055         musb_host_free(musb);
2056 }
2057 
2058 struct musb_pending_work {
2059         int (*callback)(struct musb *musb, void *data);
2060         void *data;
2061         struct list_head node;
2062 };
2063 
2064 #ifdef CONFIG_PM
2065 /*
2066  * Called from musb_runtime_resume(), musb_resume(), and
2067  * musb_queue_resume_work(). Callers must take musb->lock.
2068  */
2069 static int musb_run_resume_work(struct musb *musb)
2070 {
2071         struct musb_pending_work *w, *_w;
2072         unsigned long flags;
2073         int error = 0;
2074 
2075         spin_lock_irqsave(&musb->list_lock, flags);
2076         list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
2077                 if (w->callback) {
2078                         error = w->callback(musb, w->data);
2079                         if (error < 0) {
2080                                 dev_err(musb->controller,
2081                                         "resume callback %p failed: %i\n",
2082                                         w->callback, error);
2083                         }
2084                 }
2085                 list_del(&w->node);
2086                 devm_kfree(musb->controller, w);
2087         }
2088         spin_unlock_irqrestore(&musb->list_lock, flags);
2089 
2090         return error;
2091 }
2092 #endif
2093 
2094 /*
2095  * Called to run work if device is active or else queue the work to happen
2096  * on resume. Caller must take musb->lock and must hold an RPM reference.
2097  *
2098  * Note that we cowardly refuse queuing work after musb PM runtime
2099  * resume is done calling musb_run_resume_work() and return -EINPROGRESS
2100  * instead.
2101  */
2102 int musb_queue_resume_work(struct musb *musb,
2103                            int (*callback)(struct musb *musb, void *data),
2104                            void *data)
2105 {
2106         struct musb_pending_work *w;
2107         unsigned long flags;
2108         int error;
2109 
2110         if (WARN_ON(!callback))
2111                 return -EINVAL;
2112 
2113         if (pm_runtime_active(musb->controller))
2114                 return callback(musb, data);
2115 
2116         w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
2117         if (!w)
2118                 return -ENOMEM;
2119 
2120         w->callback = callback;
2121         w->data = data;
2122         spin_lock_irqsave(&musb->list_lock, flags);
2123         if (musb->is_runtime_suspended) {
2124                 list_add_tail(&w->node, &musb->pending_list);
2125                 error = 0;
2126         } else {
2127                 dev_err(musb->controller, "could not add resume work %p\n",
2128                         callback);
2129                 devm_kfree(musb->controller, w);
2130                 error = -EINPROGRESS;
2131         }
2132         spin_unlock_irqrestore(&musb->list_lock, flags);
2133 
2134         return error;
2135 }
2136 EXPORT_SYMBOL_GPL(musb_queue_resume_work);
2137 
2138 static void musb_deassert_reset(struct work_struct *work)
2139 {
2140         struct musb *musb;
2141         unsigned long flags;
2142 
2143         musb = container_of(work, struct musb, deassert_reset_work.work);
2144 
2145         spin_lock_irqsave(&musb->lock, flags);
2146 
2147         if (musb->port1_status & USB_PORT_STAT_RESET)
2148                 musb_port_reset(musb, false);
2149 
2150         spin_unlock_irqrestore(&musb->lock, flags);
2151 }
2152 
2153 /*
2154  * Perform generic per-controller initialization.
2155  *
2156  * @dev: the controller (already clocked, etc)
2157  * @nIrq: IRQ number
2158  * @ctrl: virtual address of controller registers,
2159  *      not yet corrected for platform-specific offsets
2160  */
2161 static int
2162 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2163 {
2164         int                     status;
2165         struct musb             *musb;
2166         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
2167 
2168         /* The driver might handle more features than the board; OK.
2169          * Fail when the board needs a feature that's not enabled.
2170          */
2171         if (!plat) {
2172                 dev_err(dev, "no platform_data?\n");
2173                 status = -ENODEV;
2174                 goto fail0;
2175         }
2176 
2177         /* allocate */
2178         musb = allocate_instance(dev, plat->config, ctrl);
2179         if (!musb) {
2180                 status = -ENOMEM;
2181                 goto fail0;
2182         }
2183 
2184         spin_lock_init(&musb->lock);
2185         spin_lock_init(&musb->list_lock);
2186         musb->board_set_power = plat->set_power;
2187         musb->min_power = plat->min_power;
2188         musb->ops = plat->platform_ops;
2189         musb->port_mode = plat->mode;
2190 
2191         /*
2192          * Initialize the default IO functions. At least omap2430 needs
2193          * these early. We initialize the platform specific IO functions
2194          * later on.
2195          */
2196         musb_readb = musb_default_readb;
2197         musb_writeb = musb_default_writeb;
2198         musb_readw = musb_default_readw;
2199         musb_writew = musb_default_writew;
2200         musb_readl = musb_default_readl;
2201         musb_writel = musb_default_writel;
2202 
2203         /* The musb_platform_init() call:
2204          *   - adjusts musb->mregs
2205          *   - sets the musb->isr
2206          *   - may initialize an integrated transceiver
2207          *   - initializes musb->xceiv, usually by otg_get_phy()
2208          *   - stops powering VBUS
2209          *
2210          * There are various transceiver configurations.  Blackfin,
2211          * DaVinci, TUSB60x0, and others integrate them.  OMAP3 uses
2212          * external/discrete ones in various flavors (twl4030 family,
2213          * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2214          */
2215         status = musb_platform_init(musb);
2216         if (status < 0)
2217                 goto fail1;
2218 
2219         if (!musb->isr) {
2220                 status = -ENODEV;
2221                 goto fail2;
2222         }
2223 
2224         if (musb->ops->quirks)
2225                 musb->io.quirks = musb->ops->quirks;
2226 
2227         /* Most devices use indexed offset or flat offset */
2228         if (musb->io.quirks & MUSB_INDEXED_EP) {
2229                 musb->io.ep_offset = musb_indexed_ep_offset;
2230                 musb->io.ep_select = musb_indexed_ep_select;
2231         } else {
2232                 musb->io.ep_offset = musb_flat_ep_offset;
2233                 musb->io.ep_select = musb_flat_ep_select;
2234         }
2235 
2236         /* At least tusb6010 has its own offsets */
2237         if (musb->ops->ep_offset)
2238                 musb->io.ep_offset = musb->ops->ep_offset;
2239         if (musb->ops->ep_select)
2240                 musb->io.ep_select = musb->ops->ep_select;
2241 
2242         if (musb->ops->fifo_mode)
2243                 fifo_mode = musb->ops->fifo_mode;
2244         else
2245                 fifo_mode = 4;
2246 
2247         if (musb->ops->fifo_offset)
2248                 musb->io.fifo_offset = musb->ops->fifo_offset;
2249         else
2250                 musb->io.fifo_offset = musb_default_fifo_offset;
2251 
2252         if (musb->ops->busctl_offset)
2253                 musb->io.busctl_offset = musb->ops->busctl_offset;
2254         else
2255                 musb->io.busctl_offset = musb_default_busctl_offset;
2256 
2257         if (musb->ops->readb)
2258                 musb_readb = musb->ops->readb;
2259         if (musb->ops->writeb)
2260                 musb_writeb = musb->ops->writeb;
2261         if (musb->ops->readw)
2262                 musb_readw = musb->ops->readw;
2263         if (musb->ops->writew)
2264                 musb_writew = musb->ops->writew;
2265         if (musb->ops->readl)
2266                 musb_readl = musb->ops->readl;
2267         if (musb->ops->writel)
2268                 musb_writel = musb->ops->writel;
2269 
2270 #ifndef CONFIG_MUSB_PIO_ONLY
2271         if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2272                 dev_err(dev, "DMA controller not set\n");
2273                 status = -ENODEV;
2274                 goto fail2;
2275         }
2276         musb_dma_controller_create = musb->ops->dma_init;
2277         musb_dma_controller_destroy = musb->ops->dma_exit;
2278 #endif
2279 
2280         if (musb->ops->read_fifo)
2281                 musb->io.read_fifo = musb->ops->read_fifo;
2282         else
2283                 musb->io.read_fifo = musb_default_read_fifo;
2284 
2285         if (musb->ops->write_fifo)
2286                 musb->io.write_fifo = musb->ops->write_fifo;
2287         else
2288                 musb->io.write_fifo = musb_default_write_fifo;
2289 
2290         if (!musb->xceiv->io_ops) {
2291                 musb->xceiv->io_dev = musb->controller;
2292                 musb->xceiv->io_priv = musb->mregs;
2293                 musb->xceiv->io_ops = &musb_ulpi_access;
2294         }
2295 
2296         if (musb->ops->phy_callback)
2297                 musb_phy_callback = musb->ops->phy_callback;
2298 
2299         /*
2300          * We need musb_read/write functions initialized for PM.
2301          * Note that at least 2430 glue needs autosuspend delay
2302          * somewhere above 300 ms for the hardware to idle properly
2303          * after disconnecting the cable in host mode. Let's use
2304          * 500 ms for some margin.
2305          */
2306         pm_runtime_use_autosuspend(musb->controller);
2307         pm_runtime_set_autosuspend_delay(musb->controller, 500);
2308         pm_runtime_enable(musb->controller);
2309         pm_runtime_get_sync(musb->controller);
2310 
2311         status = usb_phy_init(musb->xceiv);
2312         if (status < 0)
2313                 goto err_usb_phy_init;
2314 
2315         if (use_dma && dev->dma_mask) {
2316                 musb->dma_controller =
2317                         musb_dma_controller_create(musb, musb->mregs);
2318                 if (IS_ERR(musb->dma_controller)) {
2319                         status = PTR_ERR(musb->dma_controller);
2320                         goto fail2_5;
2321                 }
2322         }
2323 
2324         /* be sure interrupts are disabled before connecting ISR */
2325         musb_platform_disable(musb);
2326         musb_generic_disable(musb);
2327 
2328         /* Init IRQ workqueue before request_irq */
2329         INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
2330         INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2331         INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2332 
2333         /* setup musb parts of the core (especially endpoints) */
2334         status = musb_core_init(plat->config->multipoint
2335                         ? MUSB_CONTROLLER_MHDRC
2336                         : MUSB_CONTROLLER_HDRC, musb);
2337         if (status < 0)
2338                 goto fail3;
2339 
2340         setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2341 
2342         /* attach to the IRQ */
2343         if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2344                 dev_err(dev, "request_irq %d failed!\n", nIrq);
2345                 status = -ENODEV;
2346                 goto fail3;
2347         }
2348         musb->nIrq = nIrq;
2349         /* FIXME this handles wakeup irqs wrong */
2350         if (enable_irq_wake(nIrq) == 0) {
2351                 musb->irq_wake = 1;
2352                 device_init_wakeup(dev, 1);
2353         } else {
2354                 musb->irq_wake = 0;
2355         }
2356 
2357         /* program PHY to use external vBus if required */
2358         if (plat->extvbus) {
2359                 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2360                 busctl |= MUSB_ULPI_USE_EXTVBUS;
2361                 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2362         }
2363 
2364         if (musb->xceiv->otg->default_a) {
2365                 MUSB_HST_MODE(musb);
2366                 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2367         } else {
2368                 MUSB_DEV_MODE(musb);
2369                 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2370         }
2371 
2372         switch (musb->port_mode) {
2373         case MUSB_PORT_MODE_HOST:
2374                 status = musb_host_setup(musb, plat->power);
2375                 if (status < 0)
2376                         goto fail3;
2377                 status = musb_platform_set_mode(musb, MUSB_HOST);
2378                 break;
2379         case MUSB_PORT_MODE_GADGET:
2380                 status = musb_gadget_setup(musb);
2381                 if (status < 0)
2382                         goto fail3;
2383                 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2384                 break;
2385         case MUSB_PORT_MODE_DUAL_ROLE:
2386                 status = musb_host_setup(musb, plat->power);
2387                 if (status < 0)
2388                         goto fail3;
2389                 status = musb_gadget_setup(musb);
2390                 if (status) {
2391                         musb_host_cleanup(musb);
2392                         goto fail3;
2393                 }
2394                 status = musb_platform_set_mode(musb, MUSB_OTG);
2395                 break;
2396         default:
2397                 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2398                 break;
2399         }
2400 
2401         if (status < 0)
2402                 goto fail3;
2403 
2404         status = musb_init_debugfs(musb);
2405         if (status < 0)
2406                 goto fail4;
2407 
2408         status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2409         if (status)
2410                 goto fail5;
2411 
2412         musb->is_initialized = 1;
2413         pm_runtime_mark_last_busy(musb->controller);
2414         pm_runtime_put_autosuspend(musb->controller);
2415 
2416         return 0;
2417 
2418 fail5:
2419         musb_exit_debugfs(musb);
2420 
2421 fail4:
2422         musb_gadget_cleanup(musb);
2423         musb_host_cleanup(musb);
2424 
2425 fail3:
2426         cancel_delayed_work_sync(&musb->irq_work);
2427         cancel_delayed_work_sync(&musb->finish_resume_work);
2428         cancel_delayed_work_sync(&musb->deassert_reset_work);
2429         if (musb->dma_controller)
2430                 musb_dma_controller_destroy(musb->dma_controller);
2431 
2432 fail2_5:
2433         usb_phy_shutdown(musb->xceiv);
2434 
2435 err_usb_phy_init:
2436         pm_runtime_dont_use_autosuspend(musb->controller);
2437         pm_runtime_put_sync(musb->controller);
2438         pm_runtime_disable(musb->controller);
2439 
2440 fail2:
2441         if (musb->irq_wake)
2442                 device_init_wakeup(dev, 0);
2443         musb_platform_exit(musb);
2444 
2445 fail1:
2446         if (status != -EPROBE_DEFER)
2447                 dev_err(musb->controller,
2448                         "%s failed with status %d\n", __func__, status);
2449 
2450         musb_free(musb);
2451 
2452 fail0:
2453 
2454         return status;
2455 
2456 }
2457 
2458 /*-------------------------------------------------------------------------*/
2459 
2460 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2461  * bridge to a platform device; this driver then suffices.
2462  */
2463 static int musb_probe(struct platform_device *pdev)
2464 {
2465         struct device   *dev = &pdev->dev;
2466         int             irq = platform_get_irq_byname(pdev, "mc");
2467         struct resource *iomem;
2468         void __iomem    *base;
2469 
2470         if (irq <= 0)
2471                 return -ENODEV;
2472 
2473         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2474         base = devm_ioremap_resource(dev, iomem);
2475         if (IS_ERR(base))
2476                 return PTR_ERR(base);
2477 
2478         return musb_init_controller(dev, irq, base);
2479 }
2480 
2481 static int musb_remove(struct platform_device *pdev)
2482 {
2483         struct device   *dev = &pdev->dev;
2484         struct musb     *musb = dev_to_musb(dev);
2485         unsigned long   flags;
2486 
2487         /* this gets called on rmmod.
2488          *  - Host mode: host may still be active
2489          *  - Peripheral mode: peripheral is deactivated (or never-activated)
2490          *  - OTG mode: both roles are deactivated (or never-activated)
2491          */
2492         musb_exit_debugfs(musb);
2493 
2494         cancel_delayed_work_sync(&musb->irq_work);
2495         cancel_delayed_work_sync(&musb->finish_resume_work);
2496         cancel_delayed_work_sync(&musb->deassert_reset_work);
2497         pm_runtime_get_sync(musb->controller);
2498         musb_host_cleanup(musb);
2499         musb_gadget_cleanup(musb);
2500         spin_lock_irqsave(&musb->lock, flags);
2501         musb_platform_disable(musb);
2502         musb_generic_disable(musb);
2503         spin_unlock_irqrestore(&musb->lock, flags);
2504         musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2505         pm_runtime_dont_use_autosuspend(musb->controller);
2506         pm_runtime_put_sync(musb->controller);
2507         pm_runtime_disable(musb->controller);
2508         musb_platform_exit(musb);
2509         musb_phy_callback = NULL;
2510         if (musb->dma_controller)
2511                 musb_dma_controller_destroy(musb->dma_controller);
2512         usb_phy_shutdown(musb->xceiv);
2513         musb_free(musb);
2514         device_init_wakeup(dev, 0);
2515         return 0;
2516 }
2517 
2518 #ifdef  CONFIG_PM
2519 
2520 static void musb_save_context(struct musb *musb)
2521 {
2522         int i;
2523         void __iomem *musb_base = musb->mregs;
2524         void __iomem *epio;
2525 
2526         musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2527         musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2528         musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2529         musb->context.power = musb_readb(musb_base, MUSB_POWER);
2530         musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2531         musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2532         musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2533 
2534         for (i = 0; i < musb->config->num_eps; ++i) {
2535                 struct musb_hw_ep       *hw_ep;
2536 
2537                 hw_ep = &musb->endpoints[i];
2538                 if (!hw_ep)
2539                         continue;
2540 
2541                 epio = hw_ep->regs;
2542                 if (!epio)
2543                         continue;
2544 
2545                 musb_writeb(musb_base, MUSB_INDEX, i);
2546                 musb->context.index_regs[i].txmaxp =
2547                         musb_readw(epio, MUSB_TXMAXP);
2548                 musb->context.index_regs[i].txcsr =
2549                         musb_readw(epio, MUSB_TXCSR);
2550                 musb->context.index_regs[i].rxmaxp =
2551                         musb_readw(epio, MUSB_RXMAXP);
2552                 musb->context.index_regs[i].rxcsr =
2553                         musb_readw(epio, MUSB_RXCSR);
2554 
2555                 if (musb->dyn_fifo) {
2556                         musb->context.index_regs[i].txfifoadd =
2557                                         musb_read_txfifoadd(musb_base);
2558                         musb->context.index_regs[i].rxfifoadd =
2559                                         musb_read_rxfifoadd(musb_base);
2560                         musb->context.index_regs[i].txfifosz =
2561                                         musb_read_txfifosz(musb_base);
2562                         musb->context.index_regs[i].rxfifosz =
2563                                         musb_read_rxfifosz(musb_base);
2564                 }
2565 
2566                 musb->context.index_regs[i].txtype =
2567                         musb_readb(epio, MUSB_TXTYPE);
2568                 musb->context.index_regs[i].txinterval =
2569                         musb_readb(epio, MUSB_TXINTERVAL);
2570                 musb->context.index_regs[i].rxtype =
2571                         musb_readb(epio, MUSB_RXTYPE);
2572                 musb->context.index_regs[i].rxinterval =
2573                         musb_readb(epio, MUSB_RXINTERVAL);
2574 
2575                 musb->context.index_regs[i].txfunaddr =
2576                         musb_read_txfunaddr(musb, i);
2577                 musb->context.index_regs[i].txhubaddr =
2578                         musb_read_txhubaddr(musb, i);
2579                 musb->context.index_regs[i].txhubport =
2580                         musb_read_txhubport(musb, i);
2581 
2582                 musb->context.index_regs[i].rxfunaddr =
2583                         musb_read_rxfunaddr(musb, i);
2584                 musb->context.index_regs[i].rxhubaddr =
2585                         musb_read_rxhubaddr(musb, i);
2586                 musb->context.index_regs[i].rxhubport =
2587                         musb_read_rxhubport(musb, i);
2588         }
2589 }
2590 
2591 static void musb_restore_context(struct musb *musb)
2592 {
2593         int i;
2594         void __iomem *musb_base = musb->mregs;
2595         void __iomem *epio;
2596         u8 power;
2597 
2598         musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2599         musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2600         musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2601 
2602         /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2603         power = musb_readb(musb_base, MUSB_POWER);
2604         power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2605         musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2606         power |= musb->context.power;
2607         musb_writeb(musb_base, MUSB_POWER, power);
2608 
2609         musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2610         musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2611         musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2612         if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2613                 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2614 
2615         for (i = 0; i < musb->config->num_eps; ++i) {
2616                 struct musb_hw_ep       *hw_ep;
2617 
2618                 hw_ep = &musb->endpoints[i];
2619                 if (!hw_ep)
2620                         continue;
2621 
2622                 epio = hw_ep->regs;
2623                 if (!epio)
2624                         continue;
2625 
2626                 musb_writeb(musb_base, MUSB_INDEX, i);
2627                 musb_writew(epio, MUSB_TXMAXP,
2628                         musb->context.index_regs[i].txmaxp);
2629                 musb_writew(epio, MUSB_TXCSR,
2630                         musb->context.index_regs[i].txcsr);
2631                 musb_writew(epio, MUSB_RXMAXP,
2632                         musb->context.index_regs[i].rxmaxp);
2633                 musb_writew(epio, MUSB_RXCSR,
2634                         musb->context.index_regs[i].rxcsr);
2635 
2636                 if (musb->dyn_fifo) {
2637                         musb_write_txfifosz(musb_base,
2638                                 musb->context.index_regs[i].txfifosz);
2639                         musb_write_rxfifosz(musb_base,
2640                                 musb->context.index_regs[i].rxfifosz);
2641                         musb_write_txfifoadd(musb_base,
2642                                 musb->context.index_regs[i].txfifoadd);
2643                         musb_write_rxfifoadd(musb_base,
2644                                 musb->context.index_regs[i].rxfifoadd);
2645                 }
2646 
2647                 musb_writeb(epio, MUSB_TXTYPE,
2648                                 musb->context.index_regs[i].txtype);
2649                 musb_writeb(epio, MUSB_TXINTERVAL,
2650                                 musb->context.index_regs[i].txinterval);
2651                 musb_writeb(epio, MUSB_RXTYPE,
2652                                 musb->context.index_regs[i].rxtype);
2653                 musb_writeb(epio, MUSB_RXINTERVAL,
2654 
2655                                 musb->context.index_regs[i].rxinterval);
2656                 musb_write_txfunaddr(musb, i,
2657                                 musb->context.index_regs[i].txfunaddr);
2658                 musb_write_txhubaddr(musb, i,
2659                                 musb->context.index_regs[i].txhubaddr);
2660                 musb_write_txhubport(musb, i,
2661                                 musb->context.index_regs[i].txhubport);
2662 
2663                 musb_write_rxfunaddr(musb, i,
2664                                 musb->context.index_regs[i].rxfunaddr);
2665                 musb_write_rxhubaddr(musb, i,
2666                                 musb->context.index_regs[i].rxhubaddr);
2667                 musb_write_rxhubport(musb, i,
2668                                 musb->context.index_regs[i].rxhubport);
2669         }
2670         musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2671 }
2672 
2673 static int musb_suspend(struct device *dev)
2674 {
2675         struct musb     *musb = dev_to_musb(dev);
2676         unsigned long   flags;
2677 
2678         musb_platform_disable(musb);
2679         musb_generic_disable(musb);
2680         WARN_ON(!list_empty(&musb->pending_list));
2681 
2682         spin_lock_irqsave(&musb->lock, flags);
2683 
2684         if (is_peripheral_active(musb)) {
2685                 /* FIXME force disconnect unless we know USB will wake
2686                  * the system up quickly enough to respond ...
2687                  */
2688         } else if (is_host_active(musb)) {
2689                 /* we know all the children are suspended; sometimes
2690                  * they will even be wakeup-enabled.
2691                  */
2692         }
2693 
2694         musb_save_context(musb);
2695 
2696         spin_unlock_irqrestore(&musb->lock, flags);
2697         return 0;
2698 }
2699 
2700 static int musb_resume(struct device *dev)
2701 {
2702         struct musb *musb = dev_to_musb(dev);
2703         unsigned long flags;
2704         int error;
2705         u8 devctl;
2706         u8 mask;
2707 
2708         /*
2709          * For static cmos like DaVinci, register values were preserved
2710          * unless for some reason the whole soc powered down or the USB
2711          * module got reset through the PSC (vs just being disabled).
2712          *
2713          * For the DSPS glue layer though, a full register restore has to
2714          * be done. As it shouldn't harm other platforms, we do it
2715          * unconditionally.
2716          */
2717 
2718         musb_restore_context(musb);
2719 
2720         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2721         mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2722         if ((devctl & mask) != (musb->context.devctl & mask))
2723                 musb->port1_status = 0;
2724 
2725         /*
2726          * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2727          * out of suspend
2728          */
2729         pm_runtime_disable(dev);
2730         pm_runtime_set_active(dev);
2731         pm_runtime_enable(dev);
2732 
2733         musb_start(musb);
2734 
2735         spin_lock_irqsave(&musb->lock, flags);
2736         error = musb_run_resume_work(musb);
2737         if (error)
2738                 dev_err(musb->controller, "resume work failed with %i\n",
2739                         error);
2740         spin_unlock_irqrestore(&musb->lock, flags);
2741 
2742         return 0;
2743 }
2744 
2745 static int musb_runtime_suspend(struct device *dev)
2746 {
2747         struct musb     *musb = dev_to_musb(dev);
2748 
2749         musb_save_context(musb);
2750         musb->is_runtime_suspended = 1;
2751 
2752         return 0;
2753 }
2754 
2755 static int musb_runtime_resume(struct device *dev)
2756 {
2757         struct musb *musb = dev_to_musb(dev);
2758         unsigned long flags;
2759         int error;
2760 
2761         /*
2762          * When pm_runtime_get_sync called for the first time in driver
2763          * init,  some of the structure is still not initialized which is
2764          * used in restore function. But clock needs to be
2765          * enabled before any register access, so
2766          * pm_runtime_get_sync has to be called.
2767          * Also context restore without save does not make
2768          * any sense
2769          */
2770         if (!musb->is_initialized)
2771                 return 0;
2772 
2773         musb_restore_context(musb);
2774 
2775         spin_lock_irqsave(&musb->lock, flags);
2776         error = musb_run_resume_work(musb);
2777         if (error)
2778                 dev_err(musb->controller, "resume work failed with %i\n",
2779                         error);
2780         musb->is_runtime_suspended = 0;
2781         spin_unlock_irqrestore(&musb->lock, flags);
2782 
2783         return 0;
2784 }
2785 
2786 static const struct dev_pm_ops musb_dev_pm_ops = {
2787         .suspend        = musb_suspend,
2788         .resume         = musb_resume,
2789         .runtime_suspend = musb_runtime_suspend,
2790         .runtime_resume = musb_runtime_resume,
2791 };
2792 
2793 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2794 #else
2795 #define MUSB_DEV_PM_OPS NULL
2796 #endif
2797 
2798 static struct platform_driver musb_driver = {
2799         .driver = {
2800                 .name           = (char *)musb_driver_name,
2801                 .bus            = &platform_bus_type,
2802                 .pm             = MUSB_DEV_PM_OPS,
2803         },
2804         .probe          = musb_probe,
2805         .remove         = musb_remove,
2806 };
2807 
2808 module_platform_driver(musb_driver);
2809 

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