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Linux/drivers/usb/musb/musb_core.c

  1 /*
  2  * MUSB OTG driver core code
  3  *
  4  * Copyright 2005 Mentor Graphics Corporation
  5  * Copyright (C) 2005-2006 by Texas Instruments
  6  * Copyright (C) 2006-2007 Nokia Corporation
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License
 10  * version 2 as published by the Free Software Foundation.
 11  *
 12  * This program is distributed in the hope that it will be useful, but
 13  * WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 15  * General Public License for more details.
 16  *
 17  * You should have received a copy of the GNU General Public License
 18  * along with this program; if not, write to the Free Software
 19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 20  * 02110-1301 USA
 21  *
 22  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 25  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 32  *
 33  */
 34 
 35 /*
 36  * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
 37  *
 38  * This consists of a Host Controller Driver (HCD) and a peripheral
 39  * controller driver implementing the "Gadget" API; OTG support is
 40  * in the works.  These are normal Linux-USB controller drivers which
 41  * use IRQs and have no dedicated thread.
 42  *
 43  * This version of the driver has only been used with products from
 44  * Texas Instruments.  Those products integrate the Inventra logic
 45  * with other DMA, IRQ, and bus modules, as well as other logic that
 46  * needs to be reflected in this driver.
 47  *
 48  *
 49  * NOTE:  the original Mentor code here was pretty much a collection
 50  * of mechanisms that don't seem to have been fully integrated/working
 51  * for *any* Linux kernel version.  This version aims at Linux 2.6.now,
 52  * Key open issues include:
 53  *
 54  *  - Lack of host-side transaction scheduling, for all transfer types.
 55  *    The hardware doesn't do it; instead, software must.
 56  *
 57  *    This is not an issue for OTG devices that don't support external
 58  *    hubs, but for more "normal" USB hosts it's a user issue that the
 59  *    "multipoint" support doesn't scale in the expected ways.  That
 60  *    includes DaVinci EVM in a common non-OTG mode.
 61  *
 62  *      * Control and bulk use dedicated endpoints, and there's as
 63  *        yet no mechanism to either (a) reclaim the hardware when
 64  *        peripherals are NAKing, which gets complicated with bulk
 65  *        endpoints, or (b) use more than a single bulk endpoint in
 66  *        each direction.
 67  *
 68  *        RESULT:  one device may be perceived as blocking another one.
 69  *
 70  *      * Interrupt and isochronous will dynamically allocate endpoint
 71  *        hardware, but (a) there's no record keeping for bandwidth;
 72  *        (b) in the common case that few endpoints are available, there
 73  *        is no mechanism to reuse endpoints to talk to multiple devices.
 74  *
 75  *        RESULT:  At one extreme, bandwidth can be overcommitted in
 76  *        some hardware configurations, no faults will be reported.
 77  *        At the other extreme, the bandwidth capabilities which do
 78  *        exist tend to be severely undercommitted.  You can't yet hook
 79  *        up both a keyboard and a mouse to an external USB hub.
 80  */
 81 
 82 /*
 83  * This gets many kinds of configuration information:
 84  *      - Kconfig for everything user-configurable
 85  *      - platform_device for addressing, irq, and platform_data
 86  *      - platform_data is mostly for board-specific information
 87  *        (plus recentrly, SOC or family details)
 88  *
 89  * Most of the conditional compilation will (someday) vanish.
 90  */
 91 
 92 #include <linux/module.h>
 93 #include <linux/kernel.h>
 94 #include <linux/sched.h>
 95 #include <linux/slab.h>
 96 #include <linux/list.h>
 97 #include <linux/kobject.h>
 98 #include <linux/prefetch.h>
 99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102 
103 #include "musb_core.h"
104 
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106 
107 
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110 
111 #define MUSB_VERSION "6.0"
112 
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114 
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117 
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122 
123 
124 /*-------------------------------------------------------------------------*/
125 
126 static inline struct musb *dev_to_musb(struct device *dev)
127 {
128         return dev_get_drvdata(dev);
129 }
130 
131 /*-------------------------------------------------------------------------*/
132 
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
135 {
136         void __iomem *addr = phy->io_priv;
137         int     i = 0;
138         u8      r;
139         u8      power;
140         int     ret;
141 
142         pm_runtime_get_sync(phy->io_dev);
143 
144         /* Make sure the transceiver is not in low power mode */
145         power = musb_readb(addr, MUSB_POWER);
146         power &= ~MUSB_POWER_SUSPENDM;
147         musb_writeb(addr, MUSB_POWER, power);
148 
149         /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150          * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151          */
152 
153         musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154         musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155                         MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156 
157         while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158                                 & MUSB_ULPI_REG_CMPLT)) {
159                 i++;
160                 if (i == 10000) {
161                         ret = -ETIMEDOUT;
162                         goto out;
163                 }
164 
165         }
166         r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167         r &= ~MUSB_ULPI_REG_CMPLT;
168         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169 
170         ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171 
172 out:
173         pm_runtime_put(phy->io_dev);
174 
175         return ret;
176 }
177 
178 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
179 {
180         void __iomem *addr = phy->io_priv;
181         int     i = 0;
182         u8      r = 0;
183         u8      power;
184         int     ret = 0;
185 
186         pm_runtime_get_sync(phy->io_dev);
187 
188         /* Make sure the transceiver is not in low power mode */
189         power = musb_readb(addr, MUSB_POWER);
190         power &= ~MUSB_POWER_SUSPENDM;
191         musb_writeb(addr, MUSB_POWER, power);
192 
193         musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194         musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196 
197         while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198                                 & MUSB_ULPI_REG_CMPLT)) {
199                 i++;
200                 if (i == 10000) {
201                         ret = -ETIMEDOUT;
202                         goto out;
203                 }
204         }
205 
206         r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207         r &= ~MUSB_ULPI_REG_CMPLT;
208         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209 
210 out:
211         pm_runtime_put(phy->io_dev);
212 
213         return ret;
214 }
215 #else
216 #define musb_ulpi_read          NULL
217 #define musb_ulpi_write         NULL
218 #endif
219 
220 static struct usb_phy_io_ops musb_ulpi_access = {
221         .read = musb_ulpi_read,
222         .write = musb_ulpi_write,
223 };
224 
225 /*-------------------------------------------------------------------------*/
226 
227 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
228 
229 /*
230  * Load an endpoint's FIFO
231  */
232 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
233 {
234         struct musb *musb = hw_ep->musb;
235         void __iomem *fifo = hw_ep->fifo;
236 
237         if (unlikely(len == 0))
238                 return;
239 
240         prefetch((u8 *)src);
241 
242         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
243                         'T', hw_ep->epnum, fifo, len, src);
244 
245         /* we can't assume unaligned reads work */
246         if (likely((0x01 & (unsigned long) src) == 0)) {
247                 u16     index = 0;
248 
249                 /* best case is 32bit-aligned source address */
250                 if ((0x02 & (unsigned long) src) == 0) {
251                         if (len >= 4) {
252                                 iowrite32_rep(fifo, src + index, len >> 2);
253                                 index += len & ~0x03;
254                         }
255                         if (len & 0x02) {
256                                 musb_writew(fifo, 0, *(u16 *)&src[index]);
257                                 index += 2;
258                         }
259                 } else {
260                         if (len >= 2) {
261                                 iowrite16_rep(fifo, src + index, len >> 1);
262                                 index += len & ~0x01;
263                         }
264                 }
265                 if (len & 0x01)
266                         musb_writeb(fifo, 0, src[index]);
267         } else  {
268                 /* byte aligned */
269                 iowrite8_rep(fifo, src, len);
270         }
271 }
272 
273 #if !defined(CONFIG_USB_MUSB_AM35X)
274 /*
275  * Unload an endpoint's FIFO
276  */
277 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
278 {
279         struct musb *musb = hw_ep->musb;
280         void __iomem *fifo = hw_ep->fifo;
281 
282         if (unlikely(len == 0))
283                 return;
284 
285         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
286                         'R', hw_ep->epnum, fifo, len, dst);
287 
288         /* we can't assume unaligned writes work */
289         if (likely((0x01 & (unsigned long) dst) == 0)) {
290                 u16     index = 0;
291 
292                 /* best case is 32bit-aligned destination address */
293                 if ((0x02 & (unsigned long) dst) == 0) {
294                         if (len >= 4) {
295                                 ioread32_rep(fifo, dst, len >> 2);
296                                 index = len & ~0x03;
297                         }
298                         if (len & 0x02) {
299                                 *(u16 *)&dst[index] = musb_readw(fifo, 0);
300                                 index += 2;
301                         }
302                 } else {
303                         if (len >= 2) {
304                                 ioread16_rep(fifo, dst, len >> 1);
305                                 index = len & ~0x01;
306                         }
307                 }
308                 if (len & 0x01)
309                         dst[index] = musb_readb(fifo, 0);
310         } else  {
311                 /* byte aligned */
312                 ioread8_rep(fifo, dst, len);
313         }
314 }
315 #endif
316 
317 #endif  /* normal PIO */
318 
319 
320 /*-------------------------------------------------------------------------*/
321 
322 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
323 static const u8 musb_test_packet[53] = {
324         /* implicit SYNC then DATA0 to start */
325 
326         /* JKJKJKJK x9 */
327         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
328         /* JJKKJJKK x8 */
329         0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
330         /* JJJJKKKK x8 */
331         0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
332         /* JJJJJJJKKKKKKK x8 */
333         0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
334         /* JJJJJJJK x8 */
335         0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
336         /* JKKKKKKK x10, JK */
337         0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
338 
339         /* implicit CRC16 then EOP to end */
340 };
341 
342 void musb_load_testpacket(struct musb *musb)
343 {
344         void __iomem    *regs = musb->endpoints[0].regs;
345 
346         musb_ep_select(musb->mregs, 0);
347         musb_write_fifo(musb->control_ep,
348                         sizeof(musb_test_packet), musb_test_packet);
349         musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
350 }
351 
352 /*-------------------------------------------------------------------------*/
353 
354 /*
355  * Handles OTG hnp timeouts, such as b_ase0_brst
356  */
357 static void musb_otg_timer_func(unsigned long data)
358 {
359         struct musb     *musb = (struct musb *)data;
360         unsigned long   flags;
361 
362         spin_lock_irqsave(&musb->lock, flags);
363         switch (musb->xceiv->state) {
364         case OTG_STATE_B_WAIT_ACON:
365                 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
366                 musb_g_disconnect(musb);
367                 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
368                 musb->is_active = 0;
369                 break;
370         case OTG_STATE_A_SUSPEND:
371         case OTG_STATE_A_WAIT_BCON:
372                 dev_dbg(musb->controller, "HNP: %s timeout\n",
373                         usb_otg_state_string(musb->xceiv->state));
374                 musb_platform_set_vbus(musb, 0);
375                 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
376                 break;
377         default:
378                 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
379                         usb_otg_state_string(musb->xceiv->state));
380         }
381         spin_unlock_irqrestore(&musb->lock, flags);
382 }
383 
384 /*
385  * Stops the HNP transition. Caller must take care of locking.
386  */
387 void musb_hnp_stop(struct musb *musb)
388 {
389         struct usb_hcd  *hcd = musb->hcd;
390         void __iomem    *mbase = musb->mregs;
391         u8      reg;
392 
393         dev_dbg(musb->controller, "HNP: stop from %s\n",
394                         usb_otg_state_string(musb->xceiv->state));
395 
396         switch (musb->xceiv->state) {
397         case OTG_STATE_A_PERIPHERAL:
398                 musb_g_disconnect(musb);
399                 dev_dbg(musb->controller, "HNP: back to %s\n",
400                         usb_otg_state_string(musb->xceiv->state));
401                 break;
402         case OTG_STATE_B_HOST:
403                 dev_dbg(musb->controller, "HNP: Disabling HR\n");
404                 if (hcd)
405                         hcd->self.is_b_host = 0;
406                 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
407                 MUSB_DEV_MODE(musb);
408                 reg = musb_readb(mbase, MUSB_POWER);
409                 reg |= MUSB_POWER_SUSPENDM;
410                 musb_writeb(mbase, MUSB_POWER, reg);
411                 /* REVISIT: Start SESSION_REQUEST here? */
412                 break;
413         default:
414                 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
415                         usb_otg_state_string(musb->xceiv->state));
416         }
417 
418         /*
419          * When returning to A state after HNP, avoid hub_port_rebounce(),
420          * which cause occasional OPT A "Did not receive reset after connect"
421          * errors.
422          */
423         musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
424 }
425 
426 /*
427  * Interrupt Service Routine to record USB "global" interrupts.
428  * Since these do not happen often and signify things of
429  * paramount importance, it seems OK to check them individually;
430  * the order of the tests is specified in the manual
431  *
432  * @param musb instance pointer
433  * @param int_usb register contents
434  * @param devctl
435  * @param power
436  */
437 
438 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
439                                 u8 devctl)
440 {
441         irqreturn_t handled = IRQ_NONE;
442 
443         dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
444                 int_usb);
445 
446         /* in host mode, the peripheral may issue remote wakeup.
447          * in peripheral mode, the host may resume the link.
448          * spurious RESUME irqs happen too, paired with SUSPEND.
449          */
450         if (int_usb & MUSB_INTR_RESUME) {
451                 handled = IRQ_HANDLED;
452                 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->state));
453 
454                 if (devctl & MUSB_DEVCTL_HM) {
455                         void __iomem *mbase = musb->mregs;
456                         u8 power;
457 
458                         switch (musb->xceiv->state) {
459                         case OTG_STATE_A_SUSPEND:
460                                 /* remote wakeup?  later, GetPortStatus
461                                  * will stop RESUME signaling
462                                  */
463 
464                                 power = musb_readb(musb->mregs, MUSB_POWER);
465                                 if (power & MUSB_POWER_SUSPENDM) {
466                                         /* spurious */
467                                         musb->int_usb &= ~MUSB_INTR_SUSPEND;
468                                         dev_dbg(musb->controller, "Spurious SUSPENDM\n");
469                                         break;
470                                 }
471 
472                                 power &= ~MUSB_POWER_SUSPENDM;
473                                 musb_writeb(mbase, MUSB_POWER,
474                                                 power | MUSB_POWER_RESUME);
475 
476                                 musb->port1_status |=
477                                                 (USB_PORT_STAT_C_SUSPEND << 16)
478                                                 | MUSB_PORT_STAT_RESUME;
479                                 musb->rh_timer = jiffies
480                                                  + msecs_to_jiffies(20);
481                                 schedule_delayed_work(
482                                         &musb->finish_resume_work,
483                                         msecs_to_jiffies(20));
484 
485                                 musb->xceiv->state = OTG_STATE_A_HOST;
486                                 musb->is_active = 1;
487                                 musb_host_resume_root_hub(musb);
488                                 break;
489                         case OTG_STATE_B_WAIT_ACON:
490                                 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
491                                 musb->is_active = 1;
492                                 MUSB_DEV_MODE(musb);
493                                 break;
494                         default:
495                                 WARNING("bogus %s RESUME (%s)\n",
496                                         "host",
497                                         usb_otg_state_string(musb->xceiv->state));
498                         }
499                 } else {
500                         switch (musb->xceiv->state) {
501                         case OTG_STATE_A_SUSPEND:
502                                 /* possibly DISCONNECT is upcoming */
503                                 musb->xceiv->state = OTG_STATE_A_HOST;
504                                 musb_host_resume_root_hub(musb);
505                                 break;
506                         case OTG_STATE_B_WAIT_ACON:
507                         case OTG_STATE_B_PERIPHERAL:
508                                 /* disconnect while suspended?  we may
509                                  * not get a disconnect irq...
510                                  */
511                                 if ((devctl & MUSB_DEVCTL_VBUS)
512                                                 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
513                                                 ) {
514                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
515                                         musb->int_usb &= ~MUSB_INTR_SUSPEND;
516                                         break;
517                                 }
518                                 musb_g_resume(musb);
519                                 break;
520                         case OTG_STATE_B_IDLE:
521                                 musb->int_usb &= ~MUSB_INTR_SUSPEND;
522                                 break;
523                         default:
524                                 WARNING("bogus %s RESUME (%s)\n",
525                                         "peripheral",
526                                         usb_otg_state_string(musb->xceiv->state));
527                         }
528                 }
529         }
530 
531         /* see manual for the order of the tests */
532         if (int_usb & MUSB_INTR_SESSREQ) {
533                 void __iomem *mbase = musb->mregs;
534 
535                 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
536                                 && (devctl & MUSB_DEVCTL_BDEVICE)) {
537                         dev_dbg(musb->controller, "SessReq while on B state\n");
538                         return IRQ_HANDLED;
539                 }
540 
541                 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
542                         usb_otg_state_string(musb->xceiv->state));
543 
544                 /* IRQ arrives from ID pin sense or (later, if VBUS power
545                  * is removed) SRP.  responses are time critical:
546                  *  - turn on VBUS (with silicon-specific mechanism)
547                  *  - go through A_WAIT_VRISE
548                  *  - ... to A_WAIT_BCON.
549                  * a_wait_vrise_tmout triggers VBUS_ERROR transitions
550                  */
551                 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
552                 musb->ep0_stage = MUSB_EP0_START;
553                 musb->xceiv->state = OTG_STATE_A_IDLE;
554                 MUSB_HST_MODE(musb);
555                 musb_platform_set_vbus(musb, 1);
556 
557                 handled = IRQ_HANDLED;
558         }
559 
560         if (int_usb & MUSB_INTR_VBUSERROR) {
561                 int     ignore = 0;
562 
563                 /* During connection as an A-Device, we may see a short
564                  * current spikes causing voltage drop, because of cable
565                  * and peripheral capacitance combined with vbus draw.
566                  * (So: less common with truly self-powered devices, where
567                  * vbus doesn't act like a power supply.)
568                  *
569                  * Such spikes are short; usually less than ~500 usec, max
570                  * of ~2 msec.  That is, they're not sustained overcurrent
571                  * errors, though they're reported using VBUSERROR irqs.
572                  *
573                  * Workarounds:  (a) hardware: use self powered devices.
574                  * (b) software:  ignore non-repeated VBUS errors.
575                  *
576                  * REVISIT:  do delays from lots of DEBUG_KERNEL checks
577                  * make trouble here, keeping VBUS < 4.4V ?
578                  */
579                 switch (musb->xceiv->state) {
580                 case OTG_STATE_A_HOST:
581                         /* recovery is dicey once we've gotten past the
582                          * initial stages of enumeration, but if VBUS
583                          * stayed ok at the other end of the link, and
584                          * another reset is due (at least for high speed,
585                          * to redo the chirp etc), it might work OK...
586                          */
587                 case OTG_STATE_A_WAIT_BCON:
588                 case OTG_STATE_A_WAIT_VRISE:
589                         if (musb->vbuserr_retry) {
590                                 void __iomem *mbase = musb->mregs;
591 
592                                 musb->vbuserr_retry--;
593                                 ignore = 1;
594                                 devctl |= MUSB_DEVCTL_SESSION;
595                                 musb_writeb(mbase, MUSB_DEVCTL, devctl);
596                         } else {
597                                 musb->port1_status |=
598                                           USB_PORT_STAT_OVERCURRENT
599                                         | (USB_PORT_STAT_C_OVERCURRENT << 16);
600                         }
601                         break;
602                 default:
603                         break;
604                 }
605 
606                 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
607                                 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
608                                 usb_otg_state_string(musb->xceiv->state),
609                                 devctl,
610                                 ({ char *s;
611                                 switch (devctl & MUSB_DEVCTL_VBUS) {
612                                 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
613                                         s = "<SessEnd"; break;
614                                 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
615                                         s = "<AValid"; break;
616                                 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
617                                         s = "<VBusValid"; break;
618                                 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
619                                 default:
620                                         s = "VALID"; break;
621                                 } s; }),
622                                 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
623                                 musb->port1_status);
624 
625                 /* go through A_WAIT_VFALL then start a new session */
626                 if (!ignore)
627                         musb_platform_set_vbus(musb, 0);
628                 handled = IRQ_HANDLED;
629         }
630 
631         if (int_usb & MUSB_INTR_SUSPEND) {
632                 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
633                         usb_otg_state_string(musb->xceiv->state), devctl);
634                 handled = IRQ_HANDLED;
635 
636                 switch (musb->xceiv->state) {
637                 case OTG_STATE_A_PERIPHERAL:
638                         /* We also come here if the cable is removed, since
639                          * this silicon doesn't report ID-no-longer-grounded.
640                          *
641                          * We depend on T(a_wait_bcon) to shut us down, and
642                          * hope users don't do anything dicey during this
643                          * undesired detour through A_WAIT_BCON.
644                          */
645                         musb_hnp_stop(musb);
646                         musb_host_resume_root_hub(musb);
647                         musb_root_disconnect(musb);
648                         musb_platform_try_idle(musb, jiffies
649                                         + msecs_to_jiffies(musb->a_wait_bcon
650                                                 ? : OTG_TIME_A_WAIT_BCON));
651 
652                         break;
653                 case OTG_STATE_B_IDLE:
654                         if (!musb->is_active)
655                                 break;
656                 case OTG_STATE_B_PERIPHERAL:
657                         musb_g_suspend(musb);
658                         musb->is_active = musb->g.b_hnp_enable;
659                         if (musb->is_active) {
660                                 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
661                                 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
662                                 mod_timer(&musb->otg_timer, jiffies
663                                         + msecs_to_jiffies(
664                                                         OTG_TIME_B_ASE0_BRST));
665                         }
666                         break;
667                 case OTG_STATE_A_WAIT_BCON:
668                         if (musb->a_wait_bcon != 0)
669                                 musb_platform_try_idle(musb, jiffies
670                                         + msecs_to_jiffies(musb->a_wait_bcon));
671                         break;
672                 case OTG_STATE_A_HOST:
673                         musb->xceiv->state = OTG_STATE_A_SUSPEND;
674                         musb->is_active = musb->hcd->self.b_hnp_enable;
675                         break;
676                 case OTG_STATE_B_HOST:
677                         /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
678                         dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
679                         break;
680                 default:
681                         /* "should not happen" */
682                         musb->is_active = 0;
683                         break;
684                 }
685         }
686 
687         if (int_usb & MUSB_INTR_CONNECT) {
688                 struct usb_hcd *hcd = musb->hcd;
689 
690                 handled = IRQ_HANDLED;
691                 musb->is_active = 1;
692 
693                 musb->ep0_stage = MUSB_EP0_START;
694 
695                 /* flush endpoints when transitioning from Device Mode */
696                 if (is_peripheral_active(musb)) {
697                         /* REVISIT HNP; just force disconnect */
698                 }
699                 musb->intrtxe = musb->epmask;
700                 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
701                 musb->intrrxe = musb->epmask & 0xfffe;
702                 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
703                 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
704                 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
705                                         |USB_PORT_STAT_HIGH_SPEED
706                                         |USB_PORT_STAT_ENABLE
707                                         );
708                 musb->port1_status |= USB_PORT_STAT_CONNECTION
709                                         |(USB_PORT_STAT_C_CONNECTION << 16);
710 
711                 /* high vs full speed is just a guess until after reset */
712                 if (devctl & MUSB_DEVCTL_LSDEV)
713                         musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
714 
715                 /* indicate new connection to OTG machine */
716                 switch (musb->xceiv->state) {
717                 case OTG_STATE_B_PERIPHERAL:
718                         if (int_usb & MUSB_INTR_SUSPEND) {
719                                 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
720                                 int_usb &= ~MUSB_INTR_SUSPEND;
721                                 goto b_host;
722                         } else
723                                 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
724                         break;
725                 case OTG_STATE_B_WAIT_ACON:
726                         dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
727 b_host:
728                         musb->xceiv->state = OTG_STATE_B_HOST;
729                         if (musb->hcd)
730                                 musb->hcd->self.is_b_host = 1;
731                         del_timer(&musb->otg_timer);
732                         break;
733                 default:
734                         if ((devctl & MUSB_DEVCTL_VBUS)
735                                         == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
736                                 musb->xceiv->state = OTG_STATE_A_HOST;
737                                 if (hcd)
738                                         hcd->self.is_b_host = 0;
739                         }
740                         break;
741                 }
742 
743                 musb_host_poke_root_hub(musb);
744 
745                 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
746                                 usb_otg_state_string(musb->xceiv->state), devctl);
747         }
748 
749         if (int_usb & MUSB_INTR_DISCONNECT) {
750                 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
751                                 usb_otg_state_string(musb->xceiv->state),
752                                 MUSB_MODE(musb), devctl);
753                 handled = IRQ_HANDLED;
754 
755                 switch (musb->xceiv->state) {
756                 case OTG_STATE_A_HOST:
757                 case OTG_STATE_A_SUSPEND:
758                         musb_host_resume_root_hub(musb);
759                         musb_root_disconnect(musb);
760                         if (musb->a_wait_bcon != 0)
761                                 musb_platform_try_idle(musb, jiffies
762                                         + msecs_to_jiffies(musb->a_wait_bcon));
763                         break;
764                 case OTG_STATE_B_HOST:
765                         /* REVISIT this behaves for "real disconnect"
766                          * cases; make sure the other transitions from
767                          * from B_HOST act right too.  The B_HOST code
768                          * in hnp_stop() is currently not used...
769                          */
770                         musb_root_disconnect(musb);
771                         if (musb->hcd)
772                                 musb->hcd->self.is_b_host = 0;
773                         musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
774                         MUSB_DEV_MODE(musb);
775                         musb_g_disconnect(musb);
776                         break;
777                 case OTG_STATE_A_PERIPHERAL:
778                         musb_hnp_stop(musb);
779                         musb_root_disconnect(musb);
780                         /* FALLTHROUGH */
781                 case OTG_STATE_B_WAIT_ACON:
782                         /* FALLTHROUGH */
783                 case OTG_STATE_B_PERIPHERAL:
784                 case OTG_STATE_B_IDLE:
785                         musb_g_disconnect(musb);
786                         break;
787                 default:
788                         WARNING("unhandled DISCONNECT transition (%s)\n",
789                                 usb_otg_state_string(musb->xceiv->state));
790                         break;
791                 }
792         }
793 
794         /* mentor saves a bit: bus reset and babble share the same irq.
795          * only host sees babble; only peripheral sees bus reset.
796          */
797         if (int_usb & MUSB_INTR_RESET) {
798                 handled = IRQ_HANDLED;
799                 if ((devctl & MUSB_DEVCTL_HM) != 0) {
800                         /*
801                          * Looks like non-HS BABBLE can be ignored, but
802                          * HS BABBLE is an error condition. For HS the solution
803                          * is to avoid babble in the first place and fix what
804                          * caused BABBLE. When HS BABBLE happens we can only
805                          * stop the session.
806                          */
807                         if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
808                                 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
809                         else {
810                                 ERR("Stopping host session -- babble\n");
811                                 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
812                         }
813                 } else {
814                         dev_dbg(musb->controller, "BUS RESET as %s\n",
815                                 usb_otg_state_string(musb->xceiv->state));
816                         switch (musb->xceiv->state) {
817                         case OTG_STATE_A_SUSPEND:
818                                 musb_g_reset(musb);
819                                 /* FALLTHROUGH */
820                         case OTG_STATE_A_WAIT_BCON:     /* OPT TD.4.7-900ms */
821                                 /* never use invalid T(a_wait_bcon) */
822                                 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
823                                         usb_otg_state_string(musb->xceiv->state),
824                                         TA_WAIT_BCON(musb));
825                                 mod_timer(&musb->otg_timer, jiffies
826                                         + msecs_to_jiffies(TA_WAIT_BCON(musb)));
827                                 break;
828                         case OTG_STATE_A_PERIPHERAL:
829                                 del_timer(&musb->otg_timer);
830                                 musb_g_reset(musb);
831                                 break;
832                         case OTG_STATE_B_WAIT_ACON:
833                                 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
834                                         usb_otg_state_string(musb->xceiv->state));
835                                 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
836                                 musb_g_reset(musb);
837                                 break;
838                         case OTG_STATE_B_IDLE:
839                                 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
840                                 /* FALLTHROUGH */
841                         case OTG_STATE_B_PERIPHERAL:
842                                 musb_g_reset(musb);
843                                 break;
844                         default:
845                                 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
846                                         usb_otg_state_string(musb->xceiv->state));
847                         }
848                 }
849         }
850 
851 #if 0
852 /* REVISIT ... this would be for multiplexing periodic endpoints, or
853  * supporting transfer phasing to prevent exceeding ISO bandwidth
854  * limits of a given frame or microframe.
855  *
856  * It's not needed for peripheral side, which dedicates endpoints;
857  * though it _might_ use SOF irqs for other purposes.
858  *
859  * And it's not currently needed for host side, which also dedicates
860  * endpoints, relies on TX/RX interval registers, and isn't claimed
861  * to support ISO transfers yet.
862  */
863         if (int_usb & MUSB_INTR_SOF) {
864                 void __iomem *mbase = musb->mregs;
865                 struct musb_hw_ep       *ep;
866                 u8 epnum;
867                 u16 frame;
868 
869                 dev_dbg(musb->controller, "START_OF_FRAME\n");
870                 handled = IRQ_HANDLED;
871 
872                 /* start any periodic Tx transfers waiting for current frame */
873                 frame = musb_readw(mbase, MUSB_FRAME);
874                 ep = musb->endpoints;
875                 for (epnum = 1; (epnum < musb->nr_endpoints)
876                                         && (musb->epmask >= (1 << epnum));
877                                 epnum++, ep++) {
878                         /*
879                          * FIXME handle framecounter wraps (12 bits)
880                          * eliminate duplicated StartUrb logic
881                          */
882                         if (ep->dwWaitFrame >= frame) {
883                                 ep->dwWaitFrame = 0;
884                                 pr_debug("SOF --> periodic TX%s on %d\n",
885                                         ep->tx_channel ? " DMA" : "",
886                                         epnum);
887                                 if (!ep->tx_channel)
888                                         musb_h_tx_start(musb, epnum);
889                                 else
890                                         cppi_hostdma_start(musb, epnum);
891                         }
892                 }               /* end of for loop */
893         }
894 #endif
895 
896         schedule_work(&musb->irq_work);
897 
898         return handled;
899 }
900 
901 /*-------------------------------------------------------------------------*/
902 
903 static void musb_generic_disable(struct musb *musb)
904 {
905         void __iomem    *mbase = musb->mregs;
906         u16     temp;
907 
908         /* disable interrupts */
909         musb_writeb(mbase, MUSB_INTRUSBE, 0);
910         musb->intrtxe = 0;
911         musb_writew(mbase, MUSB_INTRTXE, 0);
912         musb->intrrxe = 0;
913         musb_writew(mbase, MUSB_INTRRXE, 0);
914 
915         /* off */
916         musb_writeb(mbase, MUSB_DEVCTL, 0);
917 
918         /*  flush pending interrupts */
919         temp = musb_readb(mbase, MUSB_INTRUSB);
920         temp = musb_readw(mbase, MUSB_INTRTX);
921         temp = musb_readw(mbase, MUSB_INTRRX);
922 
923 }
924 
925 /*
926  * Program the HDRC to start (enable interrupts, dma, etc.).
927  */
928 void musb_start(struct musb *musb)
929 {
930         void __iomem    *regs = musb->mregs;
931         u8              devctl = musb_readb(regs, MUSB_DEVCTL);
932 
933         dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
934 
935         /*  Set INT enable registers, enable interrupts */
936         musb->intrtxe = musb->epmask;
937         musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
938         musb->intrrxe = musb->epmask & 0xfffe;
939         musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
940         musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
941 
942         musb_writeb(regs, MUSB_TESTMODE, 0);
943 
944         /* put into basic highspeed mode and start session */
945         musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
946                         | MUSB_POWER_HSENAB
947                         /* ENSUSPEND wedges tusb */
948                         /* | MUSB_POWER_ENSUSPEND */
949                    );
950 
951         musb->is_active = 0;
952         devctl = musb_readb(regs, MUSB_DEVCTL);
953         devctl &= ~MUSB_DEVCTL_SESSION;
954 
955         /* session started after:
956          * (a) ID-grounded irq, host mode;
957          * (b) vbus present/connect IRQ, peripheral mode;
958          * (c) peripheral initiates, using SRP
959          */
960         if (musb->port_mode != MUSB_PORT_MODE_HOST &&
961                         (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
962                 musb->is_active = 1;
963         } else {
964                 devctl |= MUSB_DEVCTL_SESSION;
965         }
966 
967         musb_platform_enable(musb);
968         musb_writeb(regs, MUSB_DEVCTL, devctl);
969 }
970 
971 /*
972  * Make the HDRC stop (disable interrupts, etc.);
973  * reversible by musb_start
974  * called on gadget driver unregister
975  * with controller locked, irqs blocked
976  * acts as a NOP unless some role activated the hardware
977  */
978 void musb_stop(struct musb *musb)
979 {
980         /* stop IRQs, timers, ... */
981         musb_platform_disable(musb);
982         musb_generic_disable(musb);
983         dev_dbg(musb->controller, "HDRC disabled\n");
984 
985         /* FIXME
986          *  - mark host and/or peripheral drivers unusable/inactive
987          *  - disable DMA (and enable it in HdrcStart)
988          *  - make sure we can musb_start() after musb_stop(); with
989          *    OTG mode, gadget driver module rmmod/modprobe cycles that
990          *  - ...
991          */
992         musb_platform_try_idle(musb, 0);
993 }
994 
995 static void musb_shutdown(struct platform_device *pdev)
996 {
997         struct musb     *musb = dev_to_musb(&pdev->dev);
998         unsigned long   flags;
999 
1000         pm_runtime_get_sync(musb->controller);
1001 
1002         musb_host_cleanup(musb);
1003         musb_gadget_cleanup(musb);
1004 
1005         spin_lock_irqsave(&musb->lock, flags);
1006         musb_platform_disable(musb);
1007         musb_generic_disable(musb);
1008         spin_unlock_irqrestore(&musb->lock, flags);
1009 
1010         musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1011         musb_platform_exit(musb);
1012 
1013         pm_runtime_put(musb->controller);
1014         /* FIXME power down */
1015 }
1016 
1017 
1018 /*-------------------------------------------------------------------------*/
1019 
1020 /*
1021  * The silicon either has hard-wired endpoint configurations, or else
1022  * "dynamic fifo" sizing.  The driver has support for both, though at this
1023  * writing only the dynamic sizing is very well tested.   Since we switched
1024  * away from compile-time hardware parameters, we can no longer rely on
1025  * dead code elimination to leave only the relevant one in the object file.
1026  *
1027  * We don't currently use dynamic fifo setup capability to do anything
1028  * more than selecting one of a bunch of predefined configurations.
1029  */
1030 #if defined(CONFIG_USB_MUSB_TUSB6010)                   \
1031         || defined(CONFIG_USB_MUSB_TUSB6010_MODULE)     \
1032         || defined(CONFIG_USB_MUSB_OMAP2PLUS)           \
1033         || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE)    \
1034         || defined(CONFIG_USB_MUSB_AM35X)               \
1035         || defined(CONFIG_USB_MUSB_AM35X_MODULE)        \
1036         || defined(CONFIG_USB_MUSB_DSPS)                \
1037         || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1038 static ushort fifo_mode = 4;
1039 #elif defined(CONFIG_USB_MUSB_UX500)                    \
1040         || defined(CONFIG_USB_MUSB_UX500_MODULE)
1041 static ushort fifo_mode = 5;
1042 #else
1043 static ushort fifo_mode = 2;
1044 #endif
1045 
1046 /* "modprobe ... fifo_mode=1" etc */
1047 module_param(fifo_mode, ushort, 0);
1048 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1049 
1050 /*
1051  * tables defining fifo_mode values.  define more if you like.
1052  * for host side, make sure both halves of ep1 are set up.
1053  */
1054 
1055 /* mode 0 - fits in 2KB */
1056 static struct musb_fifo_cfg mode_0_cfg[] = {
1057 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1058 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1059 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1060 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1061 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1062 };
1063 
1064 /* mode 1 - fits in 4KB */
1065 static struct musb_fifo_cfg mode_1_cfg[] = {
1066 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1067 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1068 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1069 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1070 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1071 };
1072 
1073 /* mode 2 - fits in 4KB */
1074 static struct musb_fifo_cfg mode_2_cfg[] = {
1075 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1076 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1077 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1078 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1079 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1080 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1081 };
1082 
1083 /* mode 3 - fits in 4KB */
1084 static struct musb_fifo_cfg mode_3_cfg[] = {
1085 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1086 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1087 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1088 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1089 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1090 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1091 };
1092 
1093 /* mode 4 - fits in 16KB */
1094 static struct musb_fifo_cfg mode_4_cfg[] = {
1095 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1096 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1097 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1098 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1099 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1100 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1101 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1102 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1103 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1104 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1105 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 512, },
1106 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 512, },
1107 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 512, },
1108 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 512, },
1109 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 512, },
1110 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
1111 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
1112 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
1113 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
1114 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
1115 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
1116 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
1117 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
1118 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
1119 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1120 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1121 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1122 };
1123 
1124 /* mode 5 - fits in 8KB */
1125 static struct musb_fifo_cfg mode_5_cfg[] = {
1126 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1127 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1128 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1129 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1130 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1131 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1132 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1133 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1134 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1135 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1136 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 32, },
1137 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 32, },
1138 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 32, },
1139 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 32, },
1140 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 32, },
1141 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 32, },
1142 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 32, },
1143 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 32, },
1144 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 32, },
1145 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 32, },
1146 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 32, },
1147 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 32, },
1148 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 32, },
1149 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 32, },
1150 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1151 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1152 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1153 };
1154 
1155 /*
1156  * configure a fifo; for non-shared endpoints, this may be called
1157  * once for a tx fifo and once for an rx fifo.
1158  *
1159  * returns negative errno or offset for next fifo.
1160  */
1161 static int
1162 fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
1163                 const struct musb_fifo_cfg *cfg, u16 offset)
1164 {
1165         void __iomem    *mbase = musb->mregs;
1166         int     size = 0;
1167         u16     maxpacket = cfg->maxpacket;
1168         u16     c_off = offset >> 3;
1169         u8      c_size;
1170 
1171         /* expect hw_ep has already been zero-initialized */
1172 
1173         size = ffs(max(maxpacket, (u16) 8)) - 1;
1174         maxpacket = 1 << size;
1175 
1176         c_size = size - 3;
1177         if (cfg->mode == BUF_DOUBLE) {
1178                 if ((offset + (maxpacket << 1)) >
1179                                 (1 << (musb->config->ram_bits + 2)))
1180                         return -EMSGSIZE;
1181                 c_size |= MUSB_FIFOSZ_DPB;
1182         } else {
1183                 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1184                         return -EMSGSIZE;
1185         }
1186 
1187         /* configure the FIFO */
1188         musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1189 
1190         /* EP0 reserved endpoint for control, bidirectional;
1191          * EP1 reserved for bulk, two unidirectional halves.
1192          */
1193         if (hw_ep->epnum == 1)
1194                 musb->bulk_ep = hw_ep;
1195         /* REVISIT error check:  be sure ep0 can both rx and tx ... */
1196         switch (cfg->style) {
1197         case FIFO_TX:
1198                 musb_write_txfifosz(mbase, c_size);
1199                 musb_write_txfifoadd(mbase, c_off);
1200                 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1201                 hw_ep->max_packet_sz_tx = maxpacket;
1202                 break;
1203         case FIFO_RX:
1204                 musb_write_rxfifosz(mbase, c_size);
1205                 musb_write_rxfifoadd(mbase, c_off);
1206                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1207                 hw_ep->max_packet_sz_rx = maxpacket;
1208                 break;
1209         case FIFO_RXTX:
1210                 musb_write_txfifosz(mbase, c_size);
1211                 musb_write_txfifoadd(mbase, c_off);
1212                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1213                 hw_ep->max_packet_sz_rx = maxpacket;
1214 
1215                 musb_write_rxfifosz(mbase, c_size);
1216                 musb_write_rxfifoadd(mbase, c_off);
1217                 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1218                 hw_ep->max_packet_sz_tx = maxpacket;
1219 
1220                 hw_ep->is_shared_fifo = true;
1221                 break;
1222         }
1223 
1224         /* NOTE rx and tx endpoint irqs aren't managed separately,
1225          * which happens to be ok
1226          */
1227         musb->epmask |= (1 << hw_ep->epnum);
1228 
1229         return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1230 }
1231 
1232 static struct musb_fifo_cfg ep0_cfg = {
1233         .style = FIFO_RXTX, .maxpacket = 64,
1234 };
1235 
1236 static int ep_config_from_table(struct musb *musb)
1237 {
1238         const struct musb_fifo_cfg      *cfg;
1239         unsigned                i, n;
1240         int                     offset;
1241         struct musb_hw_ep       *hw_ep = musb->endpoints;
1242 
1243         if (musb->config->fifo_cfg) {
1244                 cfg = musb->config->fifo_cfg;
1245                 n = musb->config->fifo_cfg_size;
1246                 goto done;
1247         }
1248 
1249         switch (fifo_mode) {
1250         default:
1251                 fifo_mode = 0;
1252                 /* FALLTHROUGH */
1253         case 0:
1254                 cfg = mode_0_cfg;
1255                 n = ARRAY_SIZE(mode_0_cfg);
1256                 break;
1257         case 1:
1258                 cfg = mode_1_cfg;
1259                 n = ARRAY_SIZE(mode_1_cfg);
1260                 break;
1261         case 2:
1262                 cfg = mode_2_cfg;
1263                 n = ARRAY_SIZE(mode_2_cfg);
1264                 break;
1265         case 3:
1266                 cfg = mode_3_cfg;
1267                 n = ARRAY_SIZE(mode_3_cfg);
1268                 break;
1269         case 4:
1270                 cfg = mode_4_cfg;
1271                 n = ARRAY_SIZE(mode_4_cfg);
1272                 break;
1273         case 5:
1274                 cfg = mode_5_cfg;
1275                 n = ARRAY_SIZE(mode_5_cfg);
1276                 break;
1277         }
1278 
1279         printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1280                         musb_driver_name, fifo_mode);
1281 
1282 
1283 done:
1284         offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1285         /* assert(offset > 0) */
1286 
1287         /* NOTE:  for RTL versions >= 1.400 EPINFO and RAMINFO would
1288          * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1289          */
1290 
1291         for (i = 0; i < n; i++) {
1292                 u8      epn = cfg->hw_ep_num;
1293 
1294                 if (epn >= musb->config->num_eps) {
1295                         pr_debug("%s: invalid ep %d\n",
1296                                         musb_driver_name, epn);
1297                         return -EINVAL;
1298                 }
1299                 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1300                 if (offset < 0) {
1301                         pr_debug("%s: mem overrun, ep %d\n",
1302                                         musb_driver_name, epn);
1303                         return offset;
1304                 }
1305                 epn++;
1306                 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1307         }
1308 
1309         printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1310                         musb_driver_name,
1311                         n + 1, musb->config->num_eps * 2 - 1,
1312                         offset, (1 << (musb->config->ram_bits + 2)));
1313 
1314         if (!musb->bulk_ep) {
1315                 pr_debug("%s: missing bulk\n", musb_driver_name);
1316                 return -EINVAL;
1317         }
1318 
1319         return 0;
1320 }
1321 
1322 
1323 /*
1324  * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1325  * @param musb the controller
1326  */
1327 static int ep_config_from_hw(struct musb *musb)
1328 {
1329         u8 epnum = 0;
1330         struct musb_hw_ep *hw_ep;
1331         void __iomem *mbase = musb->mregs;
1332         int ret = 0;
1333 
1334         dev_dbg(musb->controller, "<== static silicon ep config\n");
1335 
1336         /* FIXME pick up ep0 maxpacket size */
1337 
1338         for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1339                 musb_ep_select(mbase, epnum);
1340                 hw_ep = musb->endpoints + epnum;
1341 
1342                 ret = musb_read_fifosize(musb, hw_ep, epnum);
1343                 if (ret < 0)
1344                         break;
1345 
1346                 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1347 
1348                 /* pick an RX/TX endpoint for bulk */
1349                 if (hw_ep->max_packet_sz_tx < 512
1350                                 || hw_ep->max_packet_sz_rx < 512)
1351                         continue;
1352 
1353                 /* REVISIT:  this algorithm is lazy, we should at least
1354                  * try to pick a double buffered endpoint.
1355                  */
1356                 if (musb->bulk_ep)
1357                         continue;
1358                 musb->bulk_ep = hw_ep;
1359         }
1360 
1361         if (!musb->bulk_ep) {
1362                 pr_debug("%s: missing bulk\n", musb_driver_name);
1363                 return -EINVAL;
1364         }
1365 
1366         return 0;
1367 }
1368 
1369 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1370 
1371 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1372  * configure endpoints, or take their config from silicon
1373  */
1374 static int musb_core_init(u16 musb_type, struct musb *musb)
1375 {
1376         u8 reg;
1377         char *type;
1378         char aInfo[90], aRevision[32], aDate[12];
1379         void __iomem    *mbase = musb->mregs;
1380         int             status = 0;
1381         int             i;
1382 
1383         /* log core options (read using indexed model) */
1384         reg = musb_read_configdata(mbase);
1385 
1386         strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1387         if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1388                 strcat(aInfo, ", dyn FIFOs");
1389                 musb->dyn_fifo = true;
1390         }
1391         if (reg & MUSB_CONFIGDATA_MPRXE) {
1392                 strcat(aInfo, ", bulk combine");
1393                 musb->bulk_combine = true;
1394         }
1395         if (reg & MUSB_CONFIGDATA_MPTXE) {
1396                 strcat(aInfo, ", bulk split");
1397                 musb->bulk_split = true;
1398         }
1399         if (reg & MUSB_CONFIGDATA_HBRXE) {
1400                 strcat(aInfo, ", HB-ISO Rx");
1401                 musb->hb_iso_rx = true;
1402         }
1403         if (reg & MUSB_CONFIGDATA_HBTXE) {
1404                 strcat(aInfo, ", HB-ISO Tx");
1405                 musb->hb_iso_tx = true;
1406         }
1407         if (reg & MUSB_CONFIGDATA_SOFTCONE)
1408                 strcat(aInfo, ", SoftConn");
1409 
1410         printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1411                         musb_driver_name, reg, aInfo);
1412 
1413         aDate[0] = 0;
1414         if (MUSB_CONTROLLER_MHDRC == musb_type) {
1415                 musb->is_multipoint = 1;
1416                 type = "M";
1417         } else {
1418                 musb->is_multipoint = 0;
1419                 type = "";
1420 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1421                 printk(KERN_ERR
1422                         "%s: kernel must blacklist external hubs\n",
1423                         musb_driver_name);
1424 #endif
1425         }
1426 
1427         /* log release info */
1428         musb->hwvers = musb_read_hwvers(mbase);
1429         snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1430                 MUSB_HWVERS_MINOR(musb->hwvers),
1431                 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1432         printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1433                         musb_driver_name, type, aRevision, aDate);
1434 
1435         /* configure ep0 */
1436         musb_configure_ep0(musb);
1437 
1438         /* discover endpoint configuration */
1439         musb->nr_endpoints = 1;
1440         musb->epmask = 1;
1441 
1442         if (musb->dyn_fifo)
1443                 status = ep_config_from_table(musb);
1444         else
1445                 status = ep_config_from_hw(musb);
1446 
1447         if (status < 0)
1448                 return status;
1449 
1450         /* finish init, and print endpoint config */
1451         for (i = 0; i < musb->nr_endpoints; i++) {
1452                 struct musb_hw_ep       *hw_ep = musb->endpoints + i;
1453 
1454                 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1455 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1456                 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1457                 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1458                 hw_ep->fifo_sync_va =
1459                         musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1460 
1461                 if (i == 0)
1462                         hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1463                 else
1464                         hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1465 #endif
1466 
1467                 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1468                 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1469                 hw_ep->rx_reinit = 1;
1470                 hw_ep->tx_reinit = 1;
1471 
1472                 if (hw_ep->max_packet_sz_tx) {
1473                         dev_dbg(musb->controller,
1474                                 "%s: hw_ep %d%s, %smax %d\n",
1475                                 musb_driver_name, i,
1476                                 hw_ep->is_shared_fifo ? "shared" : "tx",
1477                                 hw_ep->tx_double_buffered
1478                                         ? "doublebuffer, " : "",
1479                                 hw_ep->max_packet_sz_tx);
1480                 }
1481                 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1482                         dev_dbg(musb->controller,
1483                                 "%s: hw_ep %d%s, %smax %d\n",
1484                                 musb_driver_name, i,
1485                                 "rx",
1486                                 hw_ep->rx_double_buffered
1487                                         ? "doublebuffer, " : "",
1488                                 hw_ep->max_packet_sz_rx);
1489                 }
1490                 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1491                         dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1492         }
1493 
1494         return 0;
1495 }
1496 
1497 /*-------------------------------------------------------------------------*/
1498 
1499 /*
1500  * handle all the irqs defined by the HDRC core. for now we expect:  other
1501  * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1502  * will be assigned, and the irq will already have been acked.
1503  *
1504  * called in irq context with spinlock held, irqs blocked
1505  */
1506 irqreturn_t musb_interrupt(struct musb *musb)
1507 {
1508         irqreturn_t     retval = IRQ_NONE;
1509         u8              devctl;
1510         int             ep_num;
1511         u32             reg;
1512 
1513         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1514 
1515         dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1516                 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1517                 musb->int_usb, musb->int_tx, musb->int_rx);
1518 
1519         /* the core can interrupt us for multiple reasons; docs have
1520          * a generic interrupt flowchart to follow
1521          */
1522         if (musb->int_usb)
1523                 retval |= musb_stage0_irq(musb, musb->int_usb,
1524                                 devctl);
1525 
1526         /* "stage 1" is handling endpoint irqs */
1527 
1528         /* handle endpoint 0 first */
1529         if (musb->int_tx & 1) {
1530                 if (devctl & MUSB_DEVCTL_HM)
1531                         retval |= musb_h_ep0_irq(musb);
1532                 else
1533                         retval |= musb_g_ep0_irq(musb);
1534         }
1535 
1536         /* RX on endpoints 1-15 */
1537         reg = musb->int_rx >> 1;
1538         ep_num = 1;
1539         while (reg) {
1540                 if (reg & 1) {
1541                         /* musb_ep_select(musb->mregs, ep_num); */
1542                         /* REVISIT just retval = ep->rx_irq(...) */
1543                         retval = IRQ_HANDLED;
1544                         if (devctl & MUSB_DEVCTL_HM)
1545                                 musb_host_rx(musb, ep_num);
1546                         else
1547                                 musb_g_rx(musb, ep_num);
1548                 }
1549 
1550                 reg >>= 1;
1551                 ep_num++;
1552         }
1553 
1554         /* TX on endpoints 1-15 */
1555         reg = musb->int_tx >> 1;
1556         ep_num = 1;
1557         while (reg) {
1558                 if (reg & 1) {
1559                         /* musb_ep_select(musb->mregs, ep_num); */
1560                         /* REVISIT just retval |= ep->tx_irq(...) */
1561                         retval = IRQ_HANDLED;
1562                         if (devctl & MUSB_DEVCTL_HM)
1563                                 musb_host_tx(musb, ep_num);
1564                         else
1565                                 musb_g_tx(musb, ep_num);
1566                 }
1567                 reg >>= 1;
1568                 ep_num++;
1569         }
1570 
1571         return retval;
1572 }
1573 EXPORT_SYMBOL_GPL(musb_interrupt);
1574 
1575 #ifndef CONFIG_MUSB_PIO_ONLY
1576 static bool use_dma = 1;
1577 
1578 /* "modprobe ... use_dma=0" etc */
1579 module_param(use_dma, bool, 0);
1580 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1581 
1582 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1583 {
1584         u8      devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1585 
1586         /* called with controller lock already held */
1587 
1588         if (!epnum) {
1589 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1590                 if (!is_cppi_enabled()) {
1591                         /* endpoint 0 */
1592                         if (devctl & MUSB_DEVCTL_HM)
1593                                 musb_h_ep0_irq(musb);
1594                         else
1595                                 musb_g_ep0_irq(musb);
1596                 }
1597 #endif
1598         } else {
1599                 /* endpoints 1..15 */
1600                 if (transmit) {
1601                         if (devctl & MUSB_DEVCTL_HM)
1602                                 musb_host_tx(musb, epnum);
1603                         else
1604                                 musb_g_tx(musb, epnum);
1605                 } else {
1606                         /* receive */
1607                         if (devctl & MUSB_DEVCTL_HM)
1608                                 musb_host_rx(musb, epnum);
1609                         else
1610                                 musb_g_rx(musb, epnum);
1611                 }
1612         }
1613 }
1614 EXPORT_SYMBOL_GPL(musb_dma_completion);
1615 
1616 #else
1617 #define use_dma                 0
1618 #endif
1619 
1620 /*-------------------------------------------------------------------------*/
1621 
1622 static ssize_t
1623 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1624 {
1625         struct musb *musb = dev_to_musb(dev);
1626         unsigned long flags;
1627         int ret = -EINVAL;
1628 
1629         spin_lock_irqsave(&musb->lock, flags);
1630         ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->state));
1631         spin_unlock_irqrestore(&musb->lock, flags);
1632 
1633         return ret;
1634 }
1635 
1636 static ssize_t
1637 musb_mode_store(struct device *dev, struct device_attribute *attr,
1638                 const char *buf, size_t n)
1639 {
1640         struct musb     *musb = dev_to_musb(dev);
1641         unsigned long   flags;
1642         int             status;
1643 
1644         spin_lock_irqsave(&musb->lock, flags);
1645         if (sysfs_streq(buf, "host"))
1646                 status = musb_platform_set_mode(musb, MUSB_HOST);
1647         else if (sysfs_streq(buf, "peripheral"))
1648                 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1649         else if (sysfs_streq(buf, "otg"))
1650                 status = musb_platform_set_mode(musb, MUSB_OTG);
1651         else
1652                 status = -EINVAL;
1653         spin_unlock_irqrestore(&musb->lock, flags);
1654 
1655         return (status == 0) ? n : status;
1656 }
1657 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1658 
1659 static ssize_t
1660 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1661                 const char *buf, size_t n)
1662 {
1663         struct musb     *musb = dev_to_musb(dev);
1664         unsigned long   flags;
1665         unsigned long   val;
1666 
1667         if (sscanf(buf, "%lu", &val) < 1) {
1668                 dev_err(dev, "Invalid VBUS timeout ms value\n");
1669                 return -EINVAL;
1670         }
1671 
1672         spin_lock_irqsave(&musb->lock, flags);
1673         /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1674         musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1675         if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1676                 musb->is_active = 0;
1677         musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1678         spin_unlock_irqrestore(&musb->lock, flags);
1679 
1680         return n;
1681 }
1682 
1683 static ssize_t
1684 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1685 {
1686         struct musb     *musb = dev_to_musb(dev);
1687         unsigned long   flags;
1688         unsigned long   val;
1689         int             vbus;
1690 
1691         spin_lock_irqsave(&musb->lock, flags);
1692         val = musb->a_wait_bcon;
1693         /* FIXME get_vbus_status() is normally #defined as false...
1694          * and is effectively TUSB-specific.
1695          */
1696         vbus = musb_platform_get_vbus_status(musb);
1697         spin_unlock_irqrestore(&musb->lock, flags);
1698 
1699         return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1700                         vbus ? "on" : "off", val);
1701 }
1702 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1703 
1704 /* Gadget drivers can't know that a host is connected so they might want
1705  * to start SRP, but users can.  This allows userspace to trigger SRP.
1706  */
1707 static ssize_t
1708 musb_srp_store(struct device *dev, struct device_attribute *attr,
1709                 const char *buf, size_t n)
1710 {
1711         struct musb     *musb = dev_to_musb(dev);
1712         unsigned short  srp;
1713 
1714         if (sscanf(buf, "%hu", &srp) != 1
1715                         || (srp != 1)) {
1716                 dev_err(dev, "SRP: Value must be 1\n");
1717                 return -EINVAL;
1718         }
1719 
1720         if (srp == 1)
1721                 musb_g_wakeup(musb);
1722 
1723         return n;
1724 }
1725 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1726 
1727 static struct attribute *musb_attributes[] = {
1728         &dev_attr_mode.attr,
1729         &dev_attr_vbus.attr,
1730         &dev_attr_srp.attr,
1731         NULL
1732 };
1733 
1734 static const struct attribute_group musb_attr_group = {
1735         .attrs = musb_attributes,
1736 };
1737 
1738 /* Only used to provide driver mode change events */
1739 static void musb_irq_work(struct work_struct *data)
1740 {
1741         struct musb *musb = container_of(data, struct musb, irq_work);
1742 
1743         if (musb->xceiv->state != musb->xceiv_old_state) {
1744                 musb->xceiv_old_state = musb->xceiv->state;
1745                 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1746         }
1747 }
1748 
1749 /* --------------------------------------------------------------------------
1750  * Init support
1751  */
1752 
1753 static struct musb *allocate_instance(struct device *dev,
1754                 struct musb_hdrc_config *config, void __iomem *mbase)
1755 {
1756         struct musb             *musb;
1757         struct musb_hw_ep       *ep;
1758         int                     epnum;
1759         int                     ret;
1760 
1761         musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1762         if (!musb)
1763                 return NULL;
1764 
1765         INIT_LIST_HEAD(&musb->control);
1766         INIT_LIST_HEAD(&musb->in_bulk);
1767         INIT_LIST_HEAD(&musb->out_bulk);
1768 
1769         musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1770         musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1771         musb->mregs = mbase;
1772         musb->ctrl_base = mbase;
1773         musb->nIrq = -ENODEV;
1774         musb->config = config;
1775         BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1776         for (epnum = 0, ep = musb->endpoints;
1777                         epnum < musb->config->num_eps;
1778                         epnum++, ep++) {
1779                 ep->musb = musb;
1780                 ep->epnum = epnum;
1781         }
1782 
1783         musb->controller = dev;
1784 
1785         ret = musb_host_alloc(musb);
1786         if (ret < 0)
1787                 goto err_free;
1788 
1789         dev_set_drvdata(dev, musb);
1790 
1791         return musb;
1792 
1793 err_free:
1794         return NULL;
1795 }
1796 
1797 static void musb_free(struct musb *musb)
1798 {
1799         /* this has multiple entry modes. it handles fault cleanup after
1800          * probe(), where things may be partially set up, as well as rmmod
1801          * cleanup after everything's been de-activated.
1802          */
1803 
1804 #ifdef CONFIG_SYSFS
1805         sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1806 #endif
1807 
1808         if (musb->nIrq >= 0) {
1809                 if (musb->irq_wake)
1810                         disable_irq_wake(musb->nIrq);
1811                 free_irq(musb->nIrq, musb);
1812         }
1813 
1814         musb_host_free(musb);
1815 }
1816 
1817 static void musb_deassert_reset(struct work_struct *work)
1818 {
1819         struct musb *musb;
1820         unsigned long flags;
1821 
1822         musb = container_of(work, struct musb, deassert_reset_work.work);
1823 
1824         spin_lock_irqsave(&musb->lock, flags);
1825 
1826         if (musb->port1_status & USB_PORT_STAT_RESET)
1827                 musb_port_reset(musb, false);
1828 
1829         spin_unlock_irqrestore(&musb->lock, flags);
1830 }
1831 
1832 /*
1833  * Perform generic per-controller initialization.
1834  *
1835  * @dev: the controller (already clocked, etc)
1836  * @nIrq: IRQ number
1837  * @ctrl: virtual address of controller registers,
1838  *      not yet corrected for platform-specific offsets
1839  */
1840 static int
1841 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1842 {
1843         int                     status;
1844         struct musb             *musb;
1845         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1846 
1847         /* The driver might handle more features than the board; OK.
1848          * Fail when the board needs a feature that's not enabled.
1849          */
1850         if (!plat) {
1851                 dev_dbg(dev, "no platform_data?\n");
1852                 status = -ENODEV;
1853                 goto fail0;
1854         }
1855 
1856         /* allocate */
1857         musb = allocate_instance(dev, plat->config, ctrl);
1858         if (!musb) {
1859                 status = -ENOMEM;
1860                 goto fail0;
1861         }
1862 
1863         pm_runtime_use_autosuspend(musb->controller);
1864         pm_runtime_set_autosuspend_delay(musb->controller, 200);
1865         pm_runtime_enable(musb->controller);
1866 
1867         spin_lock_init(&musb->lock);
1868         musb->board_set_power = plat->set_power;
1869         musb->min_power = plat->min_power;
1870         musb->ops = plat->platform_ops;
1871         musb->port_mode = plat->mode;
1872 
1873         /* The musb_platform_init() call:
1874          *   - adjusts musb->mregs
1875          *   - sets the musb->isr
1876          *   - may initialize an integrated transceiver
1877          *   - initializes musb->xceiv, usually by otg_get_phy()
1878          *   - stops powering VBUS
1879          *
1880          * There are various transceiver configurations.  Blackfin,
1881          * DaVinci, TUSB60x0, and others integrate them.  OMAP3 uses
1882          * external/discrete ones in various flavors (twl4030 family,
1883          * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1884          */
1885         status = musb_platform_init(musb);
1886         if (status < 0)
1887                 goto fail1;
1888 
1889         if (!musb->isr) {
1890                 status = -ENODEV;
1891                 goto fail2;
1892         }
1893 
1894         if (!musb->xceiv->io_ops) {
1895                 musb->xceiv->io_dev = musb->controller;
1896                 musb->xceiv->io_priv = musb->mregs;
1897                 musb->xceiv->io_ops = &musb_ulpi_access;
1898         }
1899 
1900         pm_runtime_get_sync(musb->controller);
1901 
1902         if (use_dma && dev->dma_mask) {
1903                 musb->dma_controller = dma_controller_create(musb, musb->mregs);
1904                 if (IS_ERR(musb->dma_controller)) {
1905                         status = PTR_ERR(musb->dma_controller);
1906                         goto fail2_5;
1907                 }
1908         }
1909 
1910         /* be sure interrupts are disabled before connecting ISR */
1911         musb_platform_disable(musb);
1912         musb_generic_disable(musb);
1913 
1914         /* Init IRQ workqueue before request_irq */
1915         INIT_WORK(&musb->irq_work, musb_irq_work);
1916         INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
1917         INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
1918 
1919         /* setup musb parts of the core (especially endpoints) */
1920         status = musb_core_init(plat->config->multipoint
1921                         ? MUSB_CONTROLLER_MHDRC
1922                         : MUSB_CONTROLLER_HDRC, musb);
1923         if (status < 0)
1924                 goto fail3;
1925 
1926         setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1927 
1928         /* attach to the IRQ */
1929         if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1930                 dev_err(dev, "request_irq %d failed!\n", nIrq);
1931                 status = -ENODEV;
1932                 goto fail3;
1933         }
1934         musb->nIrq = nIrq;
1935         /* FIXME this handles wakeup irqs wrong */
1936         if (enable_irq_wake(nIrq) == 0) {
1937                 musb->irq_wake = 1;
1938                 device_init_wakeup(dev, 1);
1939         } else {
1940                 musb->irq_wake = 0;
1941         }
1942 
1943         /* program PHY to use external vBus if required */
1944         if (plat->extvbus) {
1945                 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1946                 busctl |= MUSB_ULPI_USE_EXTVBUS;
1947                 musb_write_ulpi_buscontrol(musb->mregs, busctl);
1948         }
1949 
1950         if (musb->xceiv->otg->default_a) {
1951                 MUSB_HST_MODE(musb);
1952                 musb->xceiv->state = OTG_STATE_A_IDLE;
1953         } else {
1954                 MUSB_DEV_MODE(musb);
1955                 musb->xceiv->state = OTG_STATE_B_IDLE;
1956         }
1957 
1958         switch (musb->port_mode) {
1959         case MUSB_PORT_MODE_HOST:
1960                 status = musb_host_setup(musb, plat->power);
1961                 if (status < 0)
1962                         goto fail3;
1963                 status = musb_platform_set_mode(musb, MUSB_HOST);
1964                 break;
1965         case MUSB_PORT_MODE_GADGET:
1966                 status = musb_gadget_setup(musb);
1967                 if (status < 0)
1968                         goto fail3;
1969                 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1970                 break;
1971         case MUSB_PORT_MODE_DUAL_ROLE:
1972                 status = musb_host_setup(musb, plat->power);
1973                 if (status < 0)
1974                         goto fail3;
1975                 status = musb_gadget_setup(musb);
1976                 if (status) {
1977                         musb_host_cleanup(musb);
1978                         goto fail3;
1979                 }
1980                 status = musb_platform_set_mode(musb, MUSB_OTG);
1981                 break;
1982         default:
1983                 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
1984                 break;
1985         }
1986 
1987         if (status < 0)
1988                 goto fail3;
1989 
1990         status = musb_init_debugfs(musb);
1991         if (status < 0)
1992                 goto fail4;
1993 
1994         status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
1995         if (status)
1996                 goto fail5;
1997 
1998         pm_runtime_put(musb->controller);
1999 
2000         return 0;
2001 
2002 fail5:
2003         musb_exit_debugfs(musb);
2004 
2005 fail4:
2006         musb_gadget_cleanup(musb);
2007         musb_host_cleanup(musb);
2008 
2009 fail3:
2010         cancel_work_sync(&musb->irq_work);
2011         cancel_delayed_work_sync(&musb->finish_resume_work);
2012         cancel_delayed_work_sync(&musb->deassert_reset_work);
2013         if (musb->dma_controller)
2014                 dma_controller_destroy(musb->dma_controller);
2015 fail2_5:
2016         pm_runtime_put_sync(musb->controller);
2017 
2018 fail2:
2019         if (musb->irq_wake)
2020                 device_init_wakeup(dev, 0);
2021         musb_platform_exit(musb);
2022 
2023 fail1:
2024         pm_runtime_disable(musb->controller);
2025         dev_err(musb->controller,
2026                 "musb_init_controller failed with status %d\n", status);
2027 
2028         musb_free(musb);
2029 
2030 fail0:
2031 
2032         return status;
2033 
2034 }
2035 
2036 /*-------------------------------------------------------------------------*/
2037 
2038 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2039  * bridge to a platform device; this driver then suffices.
2040  */
2041 static int musb_probe(struct platform_device *pdev)
2042 {
2043         struct device   *dev = &pdev->dev;
2044         int             irq = platform_get_irq_byname(pdev, "mc");
2045         struct resource *iomem;
2046         void __iomem    *base;
2047 
2048         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2049         if (!iomem || irq <= 0)
2050                 return -ENODEV;
2051 
2052         base = devm_ioremap_resource(dev, iomem);
2053         if (IS_ERR(base))
2054                 return PTR_ERR(base);
2055 
2056         return musb_init_controller(dev, irq, base);
2057 }
2058 
2059 static int musb_remove(struct platform_device *pdev)
2060 {
2061         struct device   *dev = &pdev->dev;
2062         struct musb     *musb = dev_to_musb(dev);
2063 
2064         /* this gets called on rmmod.
2065          *  - Host mode: host may still be active
2066          *  - Peripheral mode: peripheral is deactivated (or never-activated)
2067          *  - OTG mode: both roles are deactivated (or never-activated)
2068          */
2069         musb_exit_debugfs(musb);
2070         musb_shutdown(pdev);
2071 
2072         if (musb->dma_controller)
2073                 dma_controller_destroy(musb->dma_controller);
2074 
2075         cancel_work_sync(&musb->irq_work);
2076         cancel_delayed_work_sync(&musb->finish_resume_work);
2077         cancel_delayed_work_sync(&musb->deassert_reset_work);
2078         musb_free(musb);
2079         device_init_wakeup(dev, 0);
2080         return 0;
2081 }
2082 
2083 #ifdef  CONFIG_PM
2084 
2085 static void musb_save_context(struct musb *musb)
2086 {
2087         int i;
2088         void __iomem *musb_base = musb->mregs;
2089         void __iomem *epio;
2090 
2091         musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2092         musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2093         musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2094         musb->context.power = musb_readb(musb_base, MUSB_POWER);
2095         musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2096         musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2097         musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2098 
2099         for (i = 0; i < musb->config->num_eps; ++i) {
2100                 struct musb_hw_ep       *hw_ep;
2101 
2102                 hw_ep = &musb->endpoints[i];
2103                 if (!hw_ep)
2104                         continue;
2105 
2106                 epio = hw_ep->regs;
2107                 if (!epio)
2108                         continue;
2109 
2110                 musb_writeb(musb_base, MUSB_INDEX, i);
2111                 musb->context.index_regs[i].txmaxp =
2112                         musb_readw(epio, MUSB_TXMAXP);
2113                 musb->context.index_regs[i].txcsr =
2114                         musb_readw(epio, MUSB_TXCSR);
2115                 musb->context.index_regs[i].rxmaxp =
2116                         musb_readw(epio, MUSB_RXMAXP);
2117                 musb->context.index_regs[i].rxcsr =
2118                         musb_readw(epio, MUSB_RXCSR);
2119 
2120                 if (musb->dyn_fifo) {
2121                         musb->context.index_regs[i].txfifoadd =
2122                                         musb_read_txfifoadd(musb_base);
2123                         musb->context.index_regs[i].rxfifoadd =
2124                                         musb_read_rxfifoadd(musb_base);
2125                         musb->context.index_regs[i].txfifosz =
2126                                         musb_read_txfifosz(musb_base);
2127                         musb->context.index_regs[i].rxfifosz =
2128                                         musb_read_rxfifosz(musb_base);
2129                 }
2130 
2131                 musb->context.index_regs[i].txtype =
2132                         musb_readb(epio, MUSB_TXTYPE);
2133                 musb->context.index_regs[i].txinterval =
2134                         musb_readb(epio, MUSB_TXINTERVAL);
2135                 musb->context.index_regs[i].rxtype =
2136                         musb_readb(epio, MUSB_RXTYPE);
2137                 musb->context.index_regs[i].rxinterval =
2138                         musb_readb(epio, MUSB_RXINTERVAL);
2139 
2140                 musb->context.index_regs[i].txfunaddr =
2141                         musb_read_txfunaddr(musb_base, i);
2142                 musb->context.index_regs[i].txhubaddr =
2143                         musb_read_txhubaddr(musb_base, i);
2144                 musb->context.index_regs[i].txhubport =
2145                         musb_read_txhubport(musb_base, i);
2146 
2147                 musb->context.index_regs[i].rxfunaddr =
2148                         musb_read_rxfunaddr(musb_base, i);
2149                 musb->context.index_regs[i].rxhubaddr =
2150                         musb_read_rxhubaddr(musb_base, i);
2151                 musb->context.index_regs[i].rxhubport =
2152                         musb_read_rxhubport(musb_base, i);
2153         }
2154 }
2155 
2156 static void musb_restore_context(struct musb *musb)
2157 {
2158         int i;
2159         void __iomem *musb_base = musb->mregs;
2160         void __iomem *ep_target_regs;
2161         void __iomem *epio;
2162         u8 power;
2163 
2164         musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2165         musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2166         musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2167 
2168         /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2169         power = musb_readb(musb_base, MUSB_POWER);
2170         power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2171         musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2172         power |= musb->context.power;
2173         musb_writeb(musb_base, MUSB_POWER, power);
2174 
2175         musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2176         musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2177         musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2178         musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2179 
2180         for (i = 0; i < musb->config->num_eps; ++i) {
2181                 struct musb_hw_ep       *hw_ep;
2182 
2183                 hw_ep = &musb->endpoints[i];
2184                 if (!hw_ep)
2185                         continue;
2186 
2187                 epio = hw_ep->regs;
2188                 if (!epio)
2189                         continue;
2190 
2191                 musb_writeb(musb_base, MUSB_INDEX, i);
2192                 musb_writew(epio, MUSB_TXMAXP,
2193                         musb->context.index_regs[i].txmaxp);
2194                 musb_writew(epio, MUSB_TXCSR,
2195                         musb->context.index_regs[i].txcsr);
2196                 musb_writew(epio, MUSB_RXMAXP,
2197                         musb->context.index_regs[i].rxmaxp);
2198                 musb_writew(epio, MUSB_RXCSR,
2199                         musb->context.index_regs[i].rxcsr);
2200 
2201                 if (musb->dyn_fifo) {
2202                         musb_write_txfifosz(musb_base,
2203                                 musb->context.index_regs[i].txfifosz);
2204                         musb_write_rxfifosz(musb_base,
2205                                 musb->context.index_regs[i].rxfifosz);
2206                         musb_write_txfifoadd(musb_base,
2207                                 musb->context.index_regs[i].txfifoadd);
2208                         musb_write_rxfifoadd(musb_base,
2209                                 musb->context.index_regs[i].rxfifoadd);
2210                 }
2211 
2212                 musb_writeb(epio, MUSB_TXTYPE,
2213                                 musb->context.index_regs[i].txtype);
2214                 musb_writeb(epio, MUSB_TXINTERVAL,
2215                                 musb->context.index_regs[i].txinterval);
2216                 musb_writeb(epio, MUSB_RXTYPE,
2217                                 musb->context.index_regs[i].rxtype);
2218                 musb_writeb(epio, MUSB_RXINTERVAL,
2219 
2220                                 musb->context.index_regs[i].rxinterval);
2221                 musb_write_txfunaddr(musb_base, i,
2222                                 musb->context.index_regs[i].txfunaddr);
2223                 musb_write_txhubaddr(musb_base, i,
2224                                 musb->context.index_regs[i].txhubaddr);
2225                 musb_write_txhubport(musb_base, i,
2226                                 musb->context.index_regs[i].txhubport);
2227 
2228                 ep_target_regs =
2229                         musb_read_target_reg_base(i, musb_base);
2230 
2231                 musb_write_rxfunaddr(ep_target_regs,
2232                                 musb->context.index_regs[i].rxfunaddr);
2233                 musb_write_rxhubaddr(ep_target_regs,
2234                                 musb->context.index_regs[i].rxhubaddr);
2235                 musb_write_rxhubport(ep_target_regs,
2236                                 musb->context.index_regs[i].rxhubport);
2237         }
2238         musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2239 }
2240 
2241 static int musb_suspend(struct device *dev)
2242 {
2243         struct musb     *musb = dev_to_musb(dev);
2244         unsigned long   flags;
2245 
2246         spin_lock_irqsave(&musb->lock, flags);
2247 
2248         if (is_peripheral_active(musb)) {
2249                 /* FIXME force disconnect unless we know USB will wake
2250                  * the system up quickly enough to respond ...
2251                  */
2252         } else if (is_host_active(musb)) {
2253                 /* we know all the children are suspended; sometimes
2254                  * they will even be wakeup-enabled.
2255                  */
2256         }
2257 
2258         musb_save_context(musb);
2259 
2260         spin_unlock_irqrestore(&musb->lock, flags);
2261         return 0;
2262 }
2263 
2264 static int musb_resume_noirq(struct device *dev)
2265 {
2266         struct musb     *musb = dev_to_musb(dev);
2267 
2268         /*
2269          * For static cmos like DaVinci, register values were preserved
2270          * unless for some reason the whole soc powered down or the USB
2271          * module got reset through the PSC (vs just being disabled).
2272          *
2273          * For the DSPS glue layer though, a full register restore has to
2274          * be done. As it shouldn't harm other platforms, we do it
2275          * unconditionally.
2276          */
2277 
2278         musb_restore_context(musb);
2279 
2280         return 0;
2281 }
2282 
2283 static int musb_runtime_suspend(struct device *dev)
2284 {
2285         struct musb     *musb = dev_to_musb(dev);
2286 
2287         musb_save_context(musb);
2288 
2289         return 0;
2290 }
2291 
2292 static int musb_runtime_resume(struct device *dev)
2293 {
2294         struct musb     *musb = dev_to_musb(dev);
2295         static int      first = 1;
2296 
2297         /*
2298          * When pm_runtime_get_sync called for the first time in driver
2299          * init,  some of the structure is still not initialized which is
2300          * used in restore function. But clock needs to be
2301          * enabled before any register access, so
2302          * pm_runtime_get_sync has to be called.
2303          * Also context restore without save does not make
2304          * any sense
2305          */
2306         if (!first)
2307                 musb_restore_context(musb);
2308         first = 0;
2309 
2310         return 0;
2311 }
2312 
2313 static const struct dev_pm_ops musb_dev_pm_ops = {
2314         .suspend        = musb_suspend,
2315         .resume_noirq   = musb_resume_noirq,
2316         .runtime_suspend = musb_runtime_suspend,
2317         .runtime_resume = musb_runtime_resume,
2318 };
2319 
2320 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2321 #else
2322 #define MUSB_DEV_PM_OPS NULL
2323 #endif
2324 
2325 static struct platform_driver musb_driver = {
2326         .driver = {
2327                 .name           = (char *)musb_driver_name,
2328                 .bus            = &platform_bus_type,
2329                 .owner          = THIS_MODULE,
2330                 .pm             = MUSB_DEV_PM_OPS,
2331         },
2332         .probe          = musb_probe,
2333         .remove         = musb_remove,
2334         .shutdown       = musb_shutdown,
2335 };
2336 
2337 module_platform_driver(musb_driver);
2338 

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