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Linux/drivers/usb/musb/musb_core.c

  1 /*
  2  * MUSB OTG driver core code
  3  *
  4  * Copyright 2005 Mentor Graphics Corporation
  5  * Copyright (C) 2005-2006 by Texas Instruments
  6  * Copyright (C) 2006-2007 Nokia Corporation
  7  *
  8  * This program is free software; you can redistribute it and/or
  9  * modify it under the terms of the GNU General Public License
 10  * version 2 as published by the Free Software Foundation.
 11  *
 12  * This program is distributed in the hope that it will be useful, but
 13  * WITHOUT ANY WARRANTY; without even the implied warranty of
 14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 15  * General Public License for more details.
 16  *
 17  * You should have received a copy of the GNU General Public License
 18  * along with this program; if not, write to the Free Software
 19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 20  * 02110-1301 USA
 21  *
 22  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 25  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 32  *
 33  */
 34 
 35 /*
 36  * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
 37  *
 38  * This consists of a Host Controller Driver (HCD) and a peripheral
 39  * controller driver implementing the "Gadget" API; OTG support is
 40  * in the works.  These are normal Linux-USB controller drivers which
 41  * use IRQs and have no dedicated thread.
 42  *
 43  * This version of the driver has only been used with products from
 44  * Texas Instruments.  Those products integrate the Inventra logic
 45  * with other DMA, IRQ, and bus modules, as well as other logic that
 46  * needs to be reflected in this driver.
 47  *
 48  *
 49  * NOTE:  the original Mentor code here was pretty much a collection
 50  * of mechanisms that don't seem to have been fully integrated/working
 51  * for *any* Linux kernel version.  This version aims at Linux 2.6.now,
 52  * Key open issues include:
 53  *
 54  *  - Lack of host-side transaction scheduling, for all transfer types.
 55  *    The hardware doesn't do it; instead, software must.
 56  *
 57  *    This is not an issue for OTG devices that don't support external
 58  *    hubs, but for more "normal" USB hosts it's a user issue that the
 59  *    "multipoint" support doesn't scale in the expected ways.  That
 60  *    includes DaVinci EVM in a common non-OTG mode.
 61  *
 62  *      * Control and bulk use dedicated endpoints, and there's as
 63  *        yet no mechanism to either (a) reclaim the hardware when
 64  *        peripherals are NAKing, which gets complicated with bulk
 65  *        endpoints, or (b) use more than a single bulk endpoint in
 66  *        each direction.
 67  *
 68  *        RESULT:  one device may be perceived as blocking another one.
 69  *
 70  *      * Interrupt and isochronous will dynamically allocate endpoint
 71  *        hardware, but (a) there's no record keeping for bandwidth;
 72  *        (b) in the common case that few endpoints are available, there
 73  *        is no mechanism to reuse endpoints to talk to multiple devices.
 74  *
 75  *        RESULT:  At one extreme, bandwidth can be overcommitted in
 76  *        some hardware configurations, no faults will be reported.
 77  *        At the other extreme, the bandwidth capabilities which do
 78  *        exist tend to be severely undercommitted.  You can't yet hook
 79  *        up both a keyboard and a mouse to an external USB hub.
 80  */
 81 
 82 /*
 83  * This gets many kinds of configuration information:
 84  *      - Kconfig for everything user-configurable
 85  *      - platform_device for addressing, irq, and platform_data
 86  *      - platform_data is mostly for board-specific information
 87  *        (plus recentrly, SOC or family details)
 88  *
 89  * Most of the conditional compilation will (someday) vanish.
 90  */
 91 
 92 #include <linux/module.h>
 93 #include <linux/kernel.h>
 94 #include <linux/sched.h>
 95 #include <linux/slab.h>
 96 #include <linux/list.h>
 97 #include <linux/kobject.h>
 98 #include <linux/prefetch.h>
 99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102 #include <linux/usb.h>
103 
104 #include "musb_core.h"
105 
106 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
107 
108 
109 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
110 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111 
112 #define MUSB_VERSION "6.0"
113 
114 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115 
116 #define MUSB_DRIVER_NAME "musb-hdrc"
117 const char musb_driver_name[] = MUSB_DRIVER_NAME;
118 
119 MODULE_DESCRIPTION(DRIVER_INFO);
120 MODULE_AUTHOR(DRIVER_AUTHOR);
121 MODULE_LICENSE("GPL");
122 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
123 
124 
125 /*-------------------------------------------------------------------------*/
126 
127 static inline struct musb *dev_to_musb(struct device *dev)
128 {
129         return dev_get_drvdata(dev);
130 }
131 
132 /*-------------------------------------------------------------------------*/
133 
134 #ifndef CONFIG_BLACKFIN
135 static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
136 {
137         void __iomem *addr = phy->io_priv;
138         int     i = 0;
139         u8      r;
140         u8      power;
141         int     ret;
142 
143         pm_runtime_get_sync(phy->io_dev);
144 
145         /* Make sure the transceiver is not in low power mode */
146         power = musb_readb(addr, MUSB_POWER);
147         power &= ~MUSB_POWER_SUSPENDM;
148         musb_writeb(addr, MUSB_POWER, power);
149 
150         /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
151          * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
152          */
153 
154         musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
155         musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
156                         MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
157 
158         while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
159                                 & MUSB_ULPI_REG_CMPLT)) {
160                 i++;
161                 if (i == 10000) {
162                         ret = -ETIMEDOUT;
163                         goto out;
164                 }
165 
166         }
167         r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
168         r &= ~MUSB_ULPI_REG_CMPLT;
169         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
170 
171         ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
172 
173 out:
174         pm_runtime_put(phy->io_dev);
175 
176         return ret;
177 }
178 
179 static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
180 {
181         void __iomem *addr = phy->io_priv;
182         int     i = 0;
183         u8      r = 0;
184         u8      power;
185         int     ret = 0;
186 
187         pm_runtime_get_sync(phy->io_dev);
188 
189         /* Make sure the transceiver is not in low power mode */
190         power = musb_readb(addr, MUSB_POWER);
191         power &= ~MUSB_POWER_SUSPENDM;
192         musb_writeb(addr, MUSB_POWER, power);
193 
194         musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
195         musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
196         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
197 
198         while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
199                                 & MUSB_ULPI_REG_CMPLT)) {
200                 i++;
201                 if (i == 10000) {
202                         ret = -ETIMEDOUT;
203                         goto out;
204                 }
205         }
206 
207         r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
208         r &= ~MUSB_ULPI_REG_CMPLT;
209         musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
210 
211 out:
212         pm_runtime_put(phy->io_dev);
213 
214         return ret;
215 }
216 #else
217 #define musb_ulpi_read          NULL
218 #define musb_ulpi_write         NULL
219 #endif
220 
221 static struct usb_phy_io_ops musb_ulpi_access = {
222         .read = musb_ulpi_read,
223         .write = musb_ulpi_write,
224 };
225 
226 /*-------------------------------------------------------------------------*/
227 
228 static u32 musb_default_fifo_offset(u8 epnum)
229 {
230         return 0x20 + (epnum * 4);
231 }
232 
233 /* "flat" mapping: each endpoint has its own i/o address */
234 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
235 {
236 }
237 
238 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
239 {
240         return 0x100 + (0x10 * epnum) + offset;
241 }
242 
243 /* "indexed" mapping: INDEX register controls register bank select */
244 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
245 {
246         musb_writeb(mbase, MUSB_INDEX, epnum);
247 }
248 
249 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
250 {
251         return 0x10 + offset;
252 }
253 
254 static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
255 {
256         return 0x80 + (0x08 * epnum) + offset;
257 }
258 
259 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
260 {
261         return __raw_readb(addr + offset);
262 }
263 
264 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
265 {
266         __raw_writeb(data, addr + offset);
267 }
268 
269 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
270 {
271         return __raw_readw(addr + offset);
272 }
273 
274 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
275 {
276         __raw_writew(data, addr + offset);
277 }
278 
279 static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
280 {
281         return __raw_readl(addr + offset);
282 }
283 
284 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
285 {
286         __raw_writel(data, addr + offset);
287 }
288 
289 /*
290  * Load an endpoint's FIFO
291  */
292 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
293                                     const u8 *src)
294 {
295         struct musb *musb = hw_ep->musb;
296         void __iomem *fifo = hw_ep->fifo;
297 
298         if (unlikely(len == 0))
299                 return;
300 
301         prefetch((u8 *)src);
302 
303         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
304                         'T', hw_ep->epnum, fifo, len, src);
305 
306         /* we can't assume unaligned reads work */
307         if (likely((0x01 & (unsigned long) src) == 0)) {
308                 u16     index = 0;
309 
310                 /* best case is 32bit-aligned source address */
311                 if ((0x02 & (unsigned long) src) == 0) {
312                         if (len >= 4) {
313                                 iowrite32_rep(fifo, src + index, len >> 2);
314                                 index += len & ~0x03;
315                         }
316                         if (len & 0x02) {
317                                 __raw_writew(*(u16 *)&src[index], fifo);
318                                 index += 2;
319                         }
320                 } else {
321                         if (len >= 2) {
322                                 iowrite16_rep(fifo, src + index, len >> 1);
323                                 index += len & ~0x01;
324                         }
325                 }
326                 if (len & 0x01)
327                         __raw_writeb(src[index], fifo);
328         } else  {
329                 /* byte aligned */
330                 iowrite8_rep(fifo, src, len);
331         }
332 }
333 
334 /*
335  * Unload an endpoint's FIFO
336  */
337 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
338 {
339         struct musb *musb = hw_ep->musb;
340         void __iomem *fifo = hw_ep->fifo;
341 
342         if (unlikely(len == 0))
343                 return;
344 
345         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
346                         'R', hw_ep->epnum, fifo, len, dst);
347 
348         /* we can't assume unaligned writes work */
349         if (likely((0x01 & (unsigned long) dst) == 0)) {
350                 u16     index = 0;
351 
352                 /* best case is 32bit-aligned destination address */
353                 if ((0x02 & (unsigned long) dst) == 0) {
354                         if (len >= 4) {
355                                 ioread32_rep(fifo, dst, len >> 2);
356                                 index = len & ~0x03;
357                         }
358                         if (len & 0x02) {
359                                 *(u16 *)&dst[index] = __raw_readw(fifo);
360                                 index += 2;
361                         }
362                 } else {
363                         if (len >= 2) {
364                                 ioread16_rep(fifo, dst, len >> 1);
365                                 index = len & ~0x01;
366                         }
367                 }
368                 if (len & 0x01)
369                         dst[index] = __raw_readb(fifo);
370         } else  {
371                 /* byte aligned */
372                 ioread8_rep(fifo, dst, len);
373         }
374 }
375 
376 /*
377  * Old style IO functions
378  */
379 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
380 EXPORT_SYMBOL_GPL(musb_readb);
381 
382 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
383 EXPORT_SYMBOL_GPL(musb_writeb);
384 
385 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
386 EXPORT_SYMBOL_GPL(musb_readw);
387 
388 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
389 EXPORT_SYMBOL_GPL(musb_writew);
390 
391 u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
392 EXPORT_SYMBOL_GPL(musb_readl);
393 
394 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
395 EXPORT_SYMBOL_GPL(musb_writel);
396 
397 #ifndef CONFIG_MUSB_PIO_ONLY
398 struct dma_controller *
399 (*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
400 EXPORT_SYMBOL(musb_dma_controller_create);
401 
402 void (*musb_dma_controller_destroy)(struct dma_controller *c);
403 EXPORT_SYMBOL(musb_dma_controller_destroy);
404 #endif
405 
406 /*
407  * New style IO functions
408  */
409 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
410 {
411         return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
412 }
413 
414 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
415 {
416         return hw_ep->musb->io.write_fifo(hw_ep, len, src);
417 }
418 
419 /*-------------------------------------------------------------------------*/
420 
421 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
422 static const u8 musb_test_packet[53] = {
423         /* implicit SYNC then DATA0 to start */
424 
425         /* JKJKJKJK x9 */
426         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
427         /* JJKKJJKK x8 */
428         0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
429         /* JJJJKKKK x8 */
430         0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
431         /* JJJJJJJKKKKKKK x8 */
432         0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
433         /* JJJJJJJK x8 */
434         0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
435         /* JKKKKKKK x10, JK */
436         0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
437 
438         /* implicit CRC16 then EOP to end */
439 };
440 
441 void musb_load_testpacket(struct musb *musb)
442 {
443         void __iomem    *regs = musb->endpoints[0].regs;
444 
445         musb_ep_select(musb->mregs, 0);
446         musb_write_fifo(musb->control_ep,
447                         sizeof(musb_test_packet), musb_test_packet);
448         musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
449 }
450 
451 /*-------------------------------------------------------------------------*/
452 
453 /*
454  * Handles OTG hnp timeouts, such as b_ase0_brst
455  */
456 static void musb_otg_timer_func(unsigned long data)
457 {
458         struct musb     *musb = (struct musb *)data;
459         unsigned long   flags;
460 
461         spin_lock_irqsave(&musb->lock, flags);
462         switch (musb->xceiv->otg->state) {
463         case OTG_STATE_B_WAIT_ACON:
464                 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
465                 musb_g_disconnect(musb);
466                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
467                 musb->is_active = 0;
468                 break;
469         case OTG_STATE_A_SUSPEND:
470         case OTG_STATE_A_WAIT_BCON:
471                 dev_dbg(musb->controller, "HNP: %s timeout\n",
472                         usb_otg_state_string(musb->xceiv->otg->state));
473                 musb_platform_set_vbus(musb, 0);
474                 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
475                 break;
476         default:
477                 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
478                         usb_otg_state_string(musb->xceiv->otg->state));
479         }
480         spin_unlock_irqrestore(&musb->lock, flags);
481 }
482 
483 /*
484  * Stops the HNP transition. Caller must take care of locking.
485  */
486 void musb_hnp_stop(struct musb *musb)
487 {
488         struct usb_hcd  *hcd = musb->hcd;
489         void __iomem    *mbase = musb->mregs;
490         u8      reg;
491 
492         dev_dbg(musb->controller, "HNP: stop from %s\n",
493                         usb_otg_state_string(musb->xceiv->otg->state));
494 
495         switch (musb->xceiv->otg->state) {
496         case OTG_STATE_A_PERIPHERAL:
497                 musb_g_disconnect(musb);
498                 dev_dbg(musb->controller, "HNP: back to %s\n",
499                         usb_otg_state_string(musb->xceiv->otg->state));
500                 break;
501         case OTG_STATE_B_HOST:
502                 dev_dbg(musb->controller, "HNP: Disabling HR\n");
503                 if (hcd)
504                         hcd->self.is_b_host = 0;
505                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
506                 MUSB_DEV_MODE(musb);
507                 reg = musb_readb(mbase, MUSB_POWER);
508                 reg |= MUSB_POWER_SUSPENDM;
509                 musb_writeb(mbase, MUSB_POWER, reg);
510                 /* REVISIT: Start SESSION_REQUEST here? */
511                 break;
512         default:
513                 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
514                         usb_otg_state_string(musb->xceiv->otg->state));
515         }
516 
517         /*
518          * When returning to A state after HNP, avoid hub_port_rebounce(),
519          * which cause occasional OPT A "Did not receive reset after connect"
520          * errors.
521          */
522         musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
523 }
524 
525 static void musb_recover_from_babble(struct musb *musb);
526 
527 /*
528  * Interrupt Service Routine to record USB "global" interrupts.
529  * Since these do not happen often and signify things of
530  * paramount importance, it seems OK to check them individually;
531  * the order of the tests is specified in the manual
532  *
533  * @param musb instance pointer
534  * @param int_usb register contents
535  * @param devctl
536  * @param power
537  */
538 
539 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
540                                 u8 devctl)
541 {
542         irqreturn_t handled = IRQ_NONE;
543 
544         dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
545                 int_usb);
546 
547         /* in host mode, the peripheral may issue remote wakeup.
548          * in peripheral mode, the host may resume the link.
549          * spurious RESUME irqs happen too, paired with SUSPEND.
550          */
551         if (int_usb & MUSB_INTR_RESUME) {
552                 handled = IRQ_HANDLED;
553                 dev_dbg(musb->controller, "RESUME (%s)\n",
554                                 usb_otg_state_string(musb->xceiv->otg->state));
555 
556                 if (devctl & MUSB_DEVCTL_HM) {
557                         switch (musb->xceiv->otg->state) {
558                         case OTG_STATE_A_SUSPEND:
559                                 /* remote wakeup?  later, GetPortStatus
560                                  * will stop RESUME signaling
561                                  */
562 
563                                 musb->port1_status |=
564                                                 (USB_PORT_STAT_C_SUSPEND << 16)
565                                                 | MUSB_PORT_STAT_RESUME;
566                                 musb->rh_timer = jiffies
567                                         + msecs_to_jiffies(USB_RESUME_TIMEOUT);
568                                 musb->need_finish_resume = 1;
569 
570                                 musb->xceiv->otg->state = OTG_STATE_A_HOST;
571                                 musb->is_active = 1;
572                                 musb_host_resume_root_hub(musb);
573                                 break;
574                         case OTG_STATE_B_WAIT_ACON:
575                                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
576                                 musb->is_active = 1;
577                                 MUSB_DEV_MODE(musb);
578                                 break;
579                         default:
580                                 WARNING("bogus %s RESUME (%s)\n",
581                                         "host",
582                                         usb_otg_state_string(musb->xceiv->otg->state));
583                         }
584                 } else {
585                         switch (musb->xceiv->otg->state) {
586                         case OTG_STATE_A_SUSPEND:
587                                 /* possibly DISCONNECT is upcoming */
588                                 musb->xceiv->otg->state = OTG_STATE_A_HOST;
589                                 musb_host_resume_root_hub(musb);
590                                 break;
591                         case OTG_STATE_B_WAIT_ACON:
592                         case OTG_STATE_B_PERIPHERAL:
593                                 /* disconnect while suspended?  we may
594                                  * not get a disconnect irq...
595                                  */
596                                 if ((devctl & MUSB_DEVCTL_VBUS)
597                                                 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
598                                                 ) {
599                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
600                                         musb->int_usb &= ~MUSB_INTR_SUSPEND;
601                                         break;
602                                 }
603                                 musb_g_resume(musb);
604                                 break;
605                         case OTG_STATE_B_IDLE:
606                                 musb->int_usb &= ~MUSB_INTR_SUSPEND;
607                                 break;
608                         default:
609                                 WARNING("bogus %s RESUME (%s)\n",
610                                         "peripheral",
611                                         usb_otg_state_string(musb->xceiv->otg->state));
612                         }
613                 }
614         }
615 
616         /* see manual for the order of the tests */
617         if (int_usb & MUSB_INTR_SESSREQ) {
618                 void __iomem *mbase = musb->mregs;
619 
620                 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
621                                 && (devctl & MUSB_DEVCTL_BDEVICE)) {
622                         dev_dbg(musb->controller, "SessReq while on B state\n");
623                         return IRQ_HANDLED;
624                 }
625 
626                 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
627                         usb_otg_state_string(musb->xceiv->otg->state));
628 
629                 /* IRQ arrives from ID pin sense or (later, if VBUS power
630                  * is removed) SRP.  responses are time critical:
631                  *  - turn on VBUS (with silicon-specific mechanism)
632                  *  - go through A_WAIT_VRISE
633                  *  - ... to A_WAIT_BCON.
634                  * a_wait_vrise_tmout triggers VBUS_ERROR transitions
635                  */
636                 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
637                 musb->ep0_stage = MUSB_EP0_START;
638                 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
639                 MUSB_HST_MODE(musb);
640                 musb_platform_set_vbus(musb, 1);
641 
642                 handled = IRQ_HANDLED;
643         }
644 
645         if (int_usb & MUSB_INTR_VBUSERROR) {
646                 int     ignore = 0;
647 
648                 /* During connection as an A-Device, we may see a short
649                  * current spikes causing voltage drop, because of cable
650                  * and peripheral capacitance combined with vbus draw.
651                  * (So: less common with truly self-powered devices, where
652                  * vbus doesn't act like a power supply.)
653                  *
654                  * Such spikes are short; usually less than ~500 usec, max
655                  * of ~2 msec.  That is, they're not sustained overcurrent
656                  * errors, though they're reported using VBUSERROR irqs.
657                  *
658                  * Workarounds:  (a) hardware: use self powered devices.
659                  * (b) software:  ignore non-repeated VBUS errors.
660                  *
661                  * REVISIT:  do delays from lots of DEBUG_KERNEL checks
662                  * make trouble here, keeping VBUS < 4.4V ?
663                  */
664                 switch (musb->xceiv->otg->state) {
665                 case OTG_STATE_A_HOST:
666                         /* recovery is dicey once we've gotten past the
667                          * initial stages of enumeration, but if VBUS
668                          * stayed ok at the other end of the link, and
669                          * another reset is due (at least for high speed,
670                          * to redo the chirp etc), it might work OK...
671                          */
672                 case OTG_STATE_A_WAIT_BCON:
673                 case OTG_STATE_A_WAIT_VRISE:
674                         if (musb->vbuserr_retry) {
675                                 void __iomem *mbase = musb->mregs;
676 
677                                 musb->vbuserr_retry--;
678                                 ignore = 1;
679                                 devctl |= MUSB_DEVCTL_SESSION;
680                                 musb_writeb(mbase, MUSB_DEVCTL, devctl);
681                         } else {
682                                 musb->port1_status |=
683                                           USB_PORT_STAT_OVERCURRENT
684                                         | (USB_PORT_STAT_C_OVERCURRENT << 16);
685                         }
686                         break;
687                 default:
688                         break;
689                 }
690 
691                 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
692                                 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
693                                 usb_otg_state_string(musb->xceiv->otg->state),
694                                 devctl,
695                                 ({ char *s;
696                                 switch (devctl & MUSB_DEVCTL_VBUS) {
697                                 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
698                                         s = "<SessEnd"; break;
699                                 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
700                                         s = "<AValid"; break;
701                                 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
702                                         s = "<VBusValid"; break;
703                                 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
704                                 default:
705                                         s = "VALID"; break;
706                                 } s; }),
707                                 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
708                                 musb->port1_status);
709 
710                 /* go through A_WAIT_VFALL then start a new session */
711                 if (!ignore)
712                         musb_platform_set_vbus(musb, 0);
713                 handled = IRQ_HANDLED;
714         }
715 
716         if (int_usb & MUSB_INTR_SUSPEND) {
717                 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
718                         usb_otg_state_string(musb->xceiv->otg->state), devctl);
719                 handled = IRQ_HANDLED;
720 
721                 switch (musb->xceiv->otg->state) {
722                 case OTG_STATE_A_PERIPHERAL:
723                         /* We also come here if the cable is removed, since
724                          * this silicon doesn't report ID-no-longer-grounded.
725                          *
726                          * We depend on T(a_wait_bcon) to shut us down, and
727                          * hope users don't do anything dicey during this
728                          * undesired detour through A_WAIT_BCON.
729                          */
730                         musb_hnp_stop(musb);
731                         musb_host_resume_root_hub(musb);
732                         musb_root_disconnect(musb);
733                         musb_platform_try_idle(musb, jiffies
734                                         + msecs_to_jiffies(musb->a_wait_bcon
735                                                 ? : OTG_TIME_A_WAIT_BCON));
736 
737                         break;
738                 case OTG_STATE_B_IDLE:
739                         if (!musb->is_active)
740                                 break;
741                 case OTG_STATE_B_PERIPHERAL:
742                         musb_g_suspend(musb);
743                         musb->is_active = musb->g.b_hnp_enable;
744                         if (musb->is_active) {
745                                 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
746                                 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
747                                 mod_timer(&musb->otg_timer, jiffies
748                                         + msecs_to_jiffies(
749                                                         OTG_TIME_B_ASE0_BRST));
750                         }
751                         break;
752                 case OTG_STATE_A_WAIT_BCON:
753                         if (musb->a_wait_bcon != 0)
754                                 musb_platform_try_idle(musb, jiffies
755                                         + msecs_to_jiffies(musb->a_wait_bcon));
756                         break;
757                 case OTG_STATE_A_HOST:
758                         musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
759                         musb->is_active = musb->hcd->self.b_hnp_enable;
760                         break;
761                 case OTG_STATE_B_HOST:
762                         /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
763                         dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
764                         break;
765                 default:
766                         /* "should not happen" */
767                         musb->is_active = 0;
768                         break;
769                 }
770         }
771 
772         if (int_usb & MUSB_INTR_CONNECT) {
773                 struct usb_hcd *hcd = musb->hcd;
774 
775                 handled = IRQ_HANDLED;
776                 musb->is_active = 1;
777 
778                 musb->ep0_stage = MUSB_EP0_START;
779 
780                 musb->intrtxe = musb->epmask;
781                 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
782                 musb->intrrxe = musb->epmask & 0xfffe;
783                 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
784                 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
785                 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
786                                         |USB_PORT_STAT_HIGH_SPEED
787                                         |USB_PORT_STAT_ENABLE
788                                         );
789                 musb->port1_status |= USB_PORT_STAT_CONNECTION
790                                         |(USB_PORT_STAT_C_CONNECTION << 16);
791 
792                 /* high vs full speed is just a guess until after reset */
793                 if (devctl & MUSB_DEVCTL_LSDEV)
794                         musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
795 
796                 /* indicate new connection to OTG machine */
797                 switch (musb->xceiv->otg->state) {
798                 case OTG_STATE_B_PERIPHERAL:
799                         if (int_usb & MUSB_INTR_SUSPEND) {
800                                 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
801                                 int_usb &= ~MUSB_INTR_SUSPEND;
802                                 goto b_host;
803                         } else
804                                 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
805                         break;
806                 case OTG_STATE_B_WAIT_ACON:
807                         dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
808 b_host:
809                         musb->xceiv->otg->state = OTG_STATE_B_HOST;
810                         if (musb->hcd)
811                                 musb->hcd->self.is_b_host = 1;
812                         del_timer(&musb->otg_timer);
813                         break;
814                 default:
815                         if ((devctl & MUSB_DEVCTL_VBUS)
816                                         == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
817                                 musb->xceiv->otg->state = OTG_STATE_A_HOST;
818                                 if (hcd)
819                                         hcd->self.is_b_host = 0;
820                         }
821                         break;
822                 }
823 
824                 musb_host_poke_root_hub(musb);
825 
826                 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
827                                 usb_otg_state_string(musb->xceiv->otg->state), devctl);
828         }
829 
830         if (int_usb & MUSB_INTR_DISCONNECT) {
831                 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
832                                 usb_otg_state_string(musb->xceiv->otg->state),
833                                 MUSB_MODE(musb), devctl);
834                 handled = IRQ_HANDLED;
835 
836                 switch (musb->xceiv->otg->state) {
837                 case OTG_STATE_A_HOST:
838                 case OTG_STATE_A_SUSPEND:
839                         musb_host_resume_root_hub(musb);
840                         musb_root_disconnect(musb);
841                         if (musb->a_wait_bcon != 0)
842                                 musb_platform_try_idle(musb, jiffies
843                                         + msecs_to_jiffies(musb->a_wait_bcon));
844                         break;
845                 case OTG_STATE_B_HOST:
846                         /* REVISIT this behaves for "real disconnect"
847                          * cases; make sure the other transitions from
848                          * from B_HOST act right too.  The B_HOST code
849                          * in hnp_stop() is currently not used...
850                          */
851                         musb_root_disconnect(musb);
852                         if (musb->hcd)
853                                 musb->hcd->self.is_b_host = 0;
854                         musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
855                         MUSB_DEV_MODE(musb);
856                         musb_g_disconnect(musb);
857                         break;
858                 case OTG_STATE_A_PERIPHERAL:
859                         musb_hnp_stop(musb);
860                         musb_root_disconnect(musb);
861                         /* FALLTHROUGH */
862                 case OTG_STATE_B_WAIT_ACON:
863                         /* FALLTHROUGH */
864                 case OTG_STATE_B_PERIPHERAL:
865                 case OTG_STATE_B_IDLE:
866                         musb_g_disconnect(musb);
867                         break;
868                 default:
869                         WARNING("unhandled DISCONNECT transition (%s)\n",
870                                 usb_otg_state_string(musb->xceiv->otg->state));
871                         break;
872                 }
873         }
874 
875         /* mentor saves a bit: bus reset and babble share the same irq.
876          * only host sees babble; only peripheral sees bus reset.
877          */
878         if (int_usb & MUSB_INTR_RESET) {
879                 handled = IRQ_HANDLED;
880                 if (devctl & MUSB_DEVCTL_HM) {
881                         /*
882                          * When BABBLE happens what we can depends on which
883                          * platform MUSB is running, because some platforms
884                          * implemented proprietary means for 'recovering' from
885                          * Babble conditions. One such platform is AM335x. In
886                          * most cases, however, the only thing we can do is
887                          * drop the session.
888                          */
889                         dev_err(musb->controller, "Babble\n");
890 
891                         if (is_host_active(musb))
892                                 musb_recover_from_babble(musb);
893                 } else {
894                         dev_dbg(musb->controller, "BUS RESET as %s\n",
895                                 usb_otg_state_string(musb->xceiv->otg->state));
896                         switch (musb->xceiv->otg->state) {
897                         case OTG_STATE_A_SUSPEND:
898                                 musb_g_reset(musb);
899                                 /* FALLTHROUGH */
900                         case OTG_STATE_A_WAIT_BCON:     /* OPT TD.4.7-900ms */
901                                 /* never use invalid T(a_wait_bcon) */
902                                 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
903                                         usb_otg_state_string(musb->xceiv->otg->state),
904                                         TA_WAIT_BCON(musb));
905                                 mod_timer(&musb->otg_timer, jiffies
906                                         + msecs_to_jiffies(TA_WAIT_BCON(musb)));
907                                 break;
908                         case OTG_STATE_A_PERIPHERAL:
909                                 del_timer(&musb->otg_timer);
910                                 musb_g_reset(musb);
911                                 break;
912                         case OTG_STATE_B_WAIT_ACON:
913                                 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
914                                         usb_otg_state_string(musb->xceiv->otg->state));
915                                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
916                                 musb_g_reset(musb);
917                                 break;
918                         case OTG_STATE_B_IDLE:
919                                 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
920                                 /* FALLTHROUGH */
921                         case OTG_STATE_B_PERIPHERAL:
922                                 musb_g_reset(musb);
923                                 break;
924                         default:
925                                 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
926                                         usb_otg_state_string(musb->xceiv->otg->state));
927                         }
928                 }
929         }
930 
931 #if 0
932 /* REVISIT ... this would be for multiplexing periodic endpoints, or
933  * supporting transfer phasing to prevent exceeding ISO bandwidth
934  * limits of a given frame or microframe.
935  *
936  * It's not needed for peripheral side, which dedicates endpoints;
937  * though it _might_ use SOF irqs for other purposes.
938  *
939  * And it's not currently needed for host side, which also dedicates
940  * endpoints, relies on TX/RX interval registers, and isn't claimed
941  * to support ISO transfers yet.
942  */
943         if (int_usb & MUSB_INTR_SOF) {
944                 void __iomem *mbase = musb->mregs;
945                 struct musb_hw_ep       *ep;
946                 u8 epnum;
947                 u16 frame;
948 
949                 dev_dbg(musb->controller, "START_OF_FRAME\n");
950                 handled = IRQ_HANDLED;
951 
952                 /* start any periodic Tx transfers waiting for current frame */
953                 frame = musb_readw(mbase, MUSB_FRAME);
954                 ep = musb->endpoints;
955                 for (epnum = 1; (epnum < musb->nr_endpoints)
956                                         && (musb->epmask >= (1 << epnum));
957                                 epnum++, ep++) {
958                         /*
959                          * FIXME handle framecounter wraps (12 bits)
960                          * eliminate duplicated StartUrb logic
961                          */
962                         if (ep->dwWaitFrame >= frame) {
963                                 ep->dwWaitFrame = 0;
964                                 pr_debug("SOF --> periodic TX%s on %d\n",
965                                         ep->tx_channel ? " DMA" : "",
966                                         epnum);
967                                 if (!ep->tx_channel)
968                                         musb_h_tx_start(musb, epnum);
969                                 else
970                                         cppi_hostdma_start(musb, epnum);
971                         }
972                 }               /* end of for loop */
973         }
974 #endif
975 
976         schedule_work(&musb->irq_work);
977 
978         return handled;
979 }
980 
981 /*-------------------------------------------------------------------------*/
982 
983 static void musb_disable_interrupts(struct musb *musb)
984 {
985         void __iomem    *mbase = musb->mregs;
986         u16     temp;
987 
988         /* disable interrupts */
989         musb_writeb(mbase, MUSB_INTRUSBE, 0);
990         musb->intrtxe = 0;
991         musb_writew(mbase, MUSB_INTRTXE, 0);
992         musb->intrrxe = 0;
993         musb_writew(mbase, MUSB_INTRRXE, 0);
994 
995         /*  flush pending interrupts */
996         temp = musb_readb(mbase, MUSB_INTRUSB);
997         temp = musb_readw(mbase, MUSB_INTRTX);
998         temp = musb_readw(mbase, MUSB_INTRRX);
999 }
1000 
1001 static void musb_enable_interrupts(struct musb *musb)
1002 {
1003         void __iomem    *regs = musb->mregs;
1004 
1005         /*  Set INT enable registers, enable interrupts */
1006         musb->intrtxe = musb->epmask;
1007         musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1008         musb->intrrxe = musb->epmask & 0xfffe;
1009         musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1010         musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1011 
1012 }
1013 
1014 static void musb_generic_disable(struct musb *musb)
1015 {
1016         void __iomem    *mbase = musb->mregs;
1017 
1018         musb_disable_interrupts(musb);
1019 
1020         /* off */
1021         musb_writeb(mbase, MUSB_DEVCTL, 0);
1022 }
1023 
1024 /*
1025  * Program the HDRC to start (enable interrupts, dma, etc.).
1026  */
1027 void musb_start(struct musb *musb)
1028 {
1029         void __iomem    *regs = musb->mregs;
1030         u8              devctl = musb_readb(regs, MUSB_DEVCTL);
1031         u8              power;
1032 
1033         dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1034 
1035         musb_enable_interrupts(musb);
1036         musb_writeb(regs, MUSB_TESTMODE, 0);
1037 
1038         power = MUSB_POWER_ISOUPDATE;
1039         /*
1040          * treating UNKNOWN as unspecified maximum speed, in which case
1041          * we will default to high-speed.
1042          */
1043         if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1044                         musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1045                 power |= MUSB_POWER_HSENAB;
1046         musb_writeb(regs, MUSB_POWER, power);
1047 
1048         musb->is_active = 0;
1049         devctl = musb_readb(regs, MUSB_DEVCTL);
1050         devctl &= ~MUSB_DEVCTL_SESSION;
1051 
1052         /* session started after:
1053          * (a) ID-grounded irq, host mode;
1054          * (b) vbus present/connect IRQ, peripheral mode;
1055          * (c) peripheral initiates, using SRP
1056          */
1057         if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1058                         musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1059                         (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1060                 musb->is_active = 1;
1061         } else {
1062                 devctl |= MUSB_DEVCTL_SESSION;
1063         }
1064 
1065         musb_platform_enable(musb);
1066         musb_writeb(regs, MUSB_DEVCTL, devctl);
1067 }
1068 
1069 /*
1070  * Make the HDRC stop (disable interrupts, etc.);
1071  * reversible by musb_start
1072  * called on gadget driver unregister
1073  * with controller locked, irqs blocked
1074  * acts as a NOP unless some role activated the hardware
1075  */
1076 void musb_stop(struct musb *musb)
1077 {
1078         /* stop IRQs, timers, ... */
1079         musb_platform_disable(musb);
1080         musb_generic_disable(musb);
1081         dev_dbg(musb->controller, "HDRC disabled\n");
1082 
1083         /* FIXME
1084          *  - mark host and/or peripheral drivers unusable/inactive
1085          *  - disable DMA (and enable it in HdrcStart)
1086          *  - make sure we can musb_start() after musb_stop(); with
1087          *    OTG mode, gadget driver module rmmod/modprobe cycles that
1088          *  - ...
1089          */
1090         musb_platform_try_idle(musb, 0);
1091 }
1092 
1093 static void musb_shutdown(struct platform_device *pdev)
1094 {
1095         struct musb     *musb = dev_to_musb(&pdev->dev);
1096         unsigned long   flags;
1097 
1098         pm_runtime_get_sync(musb->controller);
1099 
1100         musb_host_cleanup(musb);
1101         musb_gadget_cleanup(musb);
1102 
1103         spin_lock_irqsave(&musb->lock, flags);
1104         musb_platform_disable(musb);
1105         musb_generic_disable(musb);
1106         spin_unlock_irqrestore(&musb->lock, flags);
1107 
1108         musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1109         musb_platform_exit(musb);
1110 
1111         pm_runtime_put(musb->controller);
1112         /* FIXME power down */
1113 }
1114 
1115 
1116 /*-------------------------------------------------------------------------*/
1117 
1118 /*
1119  * The silicon either has hard-wired endpoint configurations, or else
1120  * "dynamic fifo" sizing.  The driver has support for both, though at this
1121  * writing only the dynamic sizing is very well tested.   Since we switched
1122  * away from compile-time hardware parameters, we can no longer rely on
1123  * dead code elimination to leave only the relevant one in the object file.
1124  *
1125  * We don't currently use dynamic fifo setup capability to do anything
1126  * more than selecting one of a bunch of predefined configurations.
1127  */
1128 static ushort fifo_mode;
1129 
1130 /* "modprobe ... fifo_mode=1" etc */
1131 module_param(fifo_mode, ushort, 0);
1132 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1133 
1134 /*
1135  * tables defining fifo_mode values.  define more if you like.
1136  * for host side, make sure both halves of ep1 are set up.
1137  */
1138 
1139 /* mode 0 - fits in 2KB */
1140 static struct musb_fifo_cfg mode_0_cfg[] = {
1141 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1142 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1143 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1144 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1145 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1146 };
1147 
1148 /* mode 1 - fits in 4KB */
1149 static struct musb_fifo_cfg mode_1_cfg[] = {
1150 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1151 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1152 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1153 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1154 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1155 };
1156 
1157 /* mode 2 - fits in 4KB */
1158 static struct musb_fifo_cfg mode_2_cfg[] = {
1159 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1160 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1161 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1162 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1163 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1164 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1165 };
1166 
1167 /* mode 3 - fits in 4KB */
1168 static struct musb_fifo_cfg mode_3_cfg[] = {
1169 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1170 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1171 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1172 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1173 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1174 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1175 };
1176 
1177 /* mode 4 - fits in 16KB */
1178 static struct musb_fifo_cfg mode_4_cfg[] = {
1179 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1180 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1181 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1182 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1183 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1184 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1185 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1186 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1187 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1188 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1189 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 512, },
1190 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 512, },
1191 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 512, },
1192 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 512, },
1193 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 512, },
1194 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
1195 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
1196 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
1197 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
1198 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
1199 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
1200 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
1201 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
1202 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
1203 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1204 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1205 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1206 };
1207 
1208 /* mode 5 - fits in 8KB */
1209 static struct musb_fifo_cfg mode_5_cfg[] = {
1210 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1211 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1212 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1213 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1214 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1215 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1216 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1217 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1218 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1219 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1220 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 32, },
1221 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 32, },
1222 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 32, },
1223 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 32, },
1224 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 32, },
1225 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 32, },
1226 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 32, },
1227 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 32, },
1228 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 32, },
1229 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 32, },
1230 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 32, },
1231 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 32, },
1232 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 32, },
1233 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 32, },
1234 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1235 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1236 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1237 };
1238 
1239 /*
1240  * configure a fifo; for non-shared endpoints, this may be called
1241  * once for a tx fifo and once for an rx fifo.
1242  *
1243  * returns negative errno or offset for next fifo.
1244  */
1245 static int
1246 fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
1247                 const struct musb_fifo_cfg *cfg, u16 offset)
1248 {
1249         void __iomem    *mbase = musb->mregs;
1250         int     size = 0;
1251         u16     maxpacket = cfg->maxpacket;
1252         u16     c_off = offset >> 3;
1253         u8      c_size;
1254 
1255         /* expect hw_ep has already been zero-initialized */
1256 
1257         size = ffs(max(maxpacket, (u16) 8)) - 1;
1258         maxpacket = 1 << size;
1259 
1260         c_size = size - 3;
1261         if (cfg->mode == BUF_DOUBLE) {
1262                 if ((offset + (maxpacket << 1)) >
1263                                 (1 << (musb->config->ram_bits + 2)))
1264                         return -EMSGSIZE;
1265                 c_size |= MUSB_FIFOSZ_DPB;
1266         } else {
1267                 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1268                         return -EMSGSIZE;
1269         }
1270 
1271         /* configure the FIFO */
1272         musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1273 
1274         /* EP0 reserved endpoint for control, bidirectional;
1275          * EP1 reserved for bulk, two unidirectional halves.
1276          */
1277         if (hw_ep->epnum == 1)
1278                 musb->bulk_ep = hw_ep;
1279         /* REVISIT error check:  be sure ep0 can both rx and tx ... */
1280         switch (cfg->style) {
1281         case FIFO_TX:
1282                 musb_write_txfifosz(mbase, c_size);
1283                 musb_write_txfifoadd(mbase, c_off);
1284                 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1285                 hw_ep->max_packet_sz_tx = maxpacket;
1286                 break;
1287         case FIFO_RX:
1288                 musb_write_rxfifosz(mbase, c_size);
1289                 musb_write_rxfifoadd(mbase, c_off);
1290                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1291                 hw_ep->max_packet_sz_rx = maxpacket;
1292                 break;
1293         case FIFO_RXTX:
1294                 musb_write_txfifosz(mbase, c_size);
1295                 musb_write_txfifoadd(mbase, c_off);
1296                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1297                 hw_ep->max_packet_sz_rx = maxpacket;
1298 
1299                 musb_write_rxfifosz(mbase, c_size);
1300                 musb_write_rxfifoadd(mbase, c_off);
1301                 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1302                 hw_ep->max_packet_sz_tx = maxpacket;
1303 
1304                 hw_ep->is_shared_fifo = true;
1305                 break;
1306         }
1307 
1308         /* NOTE rx and tx endpoint irqs aren't managed separately,
1309          * which happens to be ok
1310          */
1311         musb->epmask |= (1 << hw_ep->epnum);
1312 
1313         return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1314 }
1315 
1316 static struct musb_fifo_cfg ep0_cfg = {
1317         .style = FIFO_RXTX, .maxpacket = 64,
1318 };
1319 
1320 static int ep_config_from_table(struct musb *musb)
1321 {
1322         const struct musb_fifo_cfg      *cfg;
1323         unsigned                i, n;
1324         int                     offset;
1325         struct musb_hw_ep       *hw_ep = musb->endpoints;
1326 
1327         if (musb->config->fifo_cfg) {
1328                 cfg = musb->config->fifo_cfg;
1329                 n = musb->config->fifo_cfg_size;
1330                 goto done;
1331         }
1332 
1333         switch (fifo_mode) {
1334         default:
1335                 fifo_mode = 0;
1336                 /* FALLTHROUGH */
1337         case 0:
1338                 cfg = mode_0_cfg;
1339                 n = ARRAY_SIZE(mode_0_cfg);
1340                 break;
1341         case 1:
1342                 cfg = mode_1_cfg;
1343                 n = ARRAY_SIZE(mode_1_cfg);
1344                 break;
1345         case 2:
1346                 cfg = mode_2_cfg;
1347                 n = ARRAY_SIZE(mode_2_cfg);
1348                 break;
1349         case 3:
1350                 cfg = mode_3_cfg;
1351                 n = ARRAY_SIZE(mode_3_cfg);
1352                 break;
1353         case 4:
1354                 cfg = mode_4_cfg;
1355                 n = ARRAY_SIZE(mode_4_cfg);
1356                 break;
1357         case 5:
1358                 cfg = mode_5_cfg;
1359                 n = ARRAY_SIZE(mode_5_cfg);
1360                 break;
1361         }
1362 
1363         pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1364 
1365 
1366 done:
1367         offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1368         /* assert(offset > 0) */
1369 
1370         /* NOTE:  for RTL versions >= 1.400 EPINFO and RAMINFO would
1371          * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1372          */
1373 
1374         for (i = 0; i < n; i++) {
1375                 u8      epn = cfg->hw_ep_num;
1376 
1377                 if (epn >= musb->config->num_eps) {
1378                         pr_debug("%s: invalid ep %d\n",
1379                                         musb_driver_name, epn);
1380                         return -EINVAL;
1381                 }
1382                 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1383                 if (offset < 0) {
1384                         pr_debug("%s: mem overrun, ep %d\n",
1385                                         musb_driver_name, epn);
1386                         return offset;
1387                 }
1388                 epn++;
1389                 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1390         }
1391 
1392         pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1393                         musb_driver_name,
1394                         n + 1, musb->config->num_eps * 2 - 1,
1395                         offset, (1 << (musb->config->ram_bits + 2)));
1396 
1397         if (!musb->bulk_ep) {
1398                 pr_debug("%s: missing bulk\n", musb_driver_name);
1399                 return -EINVAL;
1400         }
1401 
1402         return 0;
1403 }
1404 
1405 
1406 /*
1407  * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1408  * @param musb the controller
1409  */
1410 static int ep_config_from_hw(struct musb *musb)
1411 {
1412         u8 epnum = 0;
1413         struct musb_hw_ep *hw_ep;
1414         void __iomem *mbase = musb->mregs;
1415         int ret = 0;
1416 
1417         dev_dbg(musb->controller, "<== static silicon ep config\n");
1418 
1419         /* FIXME pick up ep0 maxpacket size */
1420 
1421         for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1422                 musb_ep_select(mbase, epnum);
1423                 hw_ep = musb->endpoints + epnum;
1424 
1425                 ret = musb_read_fifosize(musb, hw_ep, epnum);
1426                 if (ret < 0)
1427                         break;
1428 
1429                 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1430 
1431                 /* pick an RX/TX endpoint for bulk */
1432                 if (hw_ep->max_packet_sz_tx < 512
1433                                 || hw_ep->max_packet_sz_rx < 512)
1434                         continue;
1435 
1436                 /* REVISIT:  this algorithm is lazy, we should at least
1437                  * try to pick a double buffered endpoint.
1438                  */
1439                 if (musb->bulk_ep)
1440                         continue;
1441                 musb->bulk_ep = hw_ep;
1442         }
1443 
1444         if (!musb->bulk_ep) {
1445                 pr_debug("%s: missing bulk\n", musb_driver_name);
1446                 return -EINVAL;
1447         }
1448 
1449         return 0;
1450 }
1451 
1452 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1453 
1454 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1455  * configure endpoints, or take their config from silicon
1456  */
1457 static int musb_core_init(u16 musb_type, struct musb *musb)
1458 {
1459         u8 reg;
1460         char *type;
1461         char aInfo[90], aRevision[32], aDate[12];
1462         void __iomem    *mbase = musb->mregs;
1463         int             status = 0;
1464         int             i;
1465 
1466         /* log core options (read using indexed model) */
1467         reg = musb_read_configdata(mbase);
1468 
1469         strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1470         if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1471                 strcat(aInfo, ", dyn FIFOs");
1472                 musb->dyn_fifo = true;
1473         }
1474         if (reg & MUSB_CONFIGDATA_MPRXE) {
1475                 strcat(aInfo, ", bulk combine");
1476                 musb->bulk_combine = true;
1477         }
1478         if (reg & MUSB_CONFIGDATA_MPTXE) {
1479                 strcat(aInfo, ", bulk split");
1480                 musb->bulk_split = true;
1481         }
1482         if (reg & MUSB_CONFIGDATA_HBRXE) {
1483                 strcat(aInfo, ", HB-ISO Rx");
1484                 musb->hb_iso_rx = true;
1485         }
1486         if (reg & MUSB_CONFIGDATA_HBTXE) {
1487                 strcat(aInfo, ", HB-ISO Tx");
1488                 musb->hb_iso_tx = true;
1489         }
1490         if (reg & MUSB_CONFIGDATA_SOFTCONE)
1491                 strcat(aInfo, ", SoftConn");
1492 
1493         pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1494 
1495         aDate[0] = 0;
1496         if (MUSB_CONTROLLER_MHDRC == musb_type) {
1497                 musb->is_multipoint = 1;
1498                 type = "M";
1499         } else {
1500                 musb->is_multipoint = 0;
1501                 type = "";
1502 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1503                 pr_err("%s: kernel must blacklist external hubs\n",
1504                        musb_driver_name);
1505 #endif
1506         }
1507 
1508         /* log release info */
1509         musb->hwvers = musb_read_hwvers(mbase);
1510         snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1511                 MUSB_HWVERS_MINOR(musb->hwvers),
1512                 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1513         pr_debug("%s: %sHDRC RTL version %s %s\n",
1514                  musb_driver_name, type, aRevision, aDate);
1515 
1516         /* configure ep0 */
1517         musb_configure_ep0(musb);
1518 
1519         /* discover endpoint configuration */
1520         musb->nr_endpoints = 1;
1521         musb->epmask = 1;
1522 
1523         if (musb->dyn_fifo)
1524                 status = ep_config_from_table(musb);
1525         else
1526                 status = ep_config_from_hw(musb);
1527 
1528         if (status < 0)
1529                 return status;
1530 
1531         /* finish init, and print endpoint config */
1532         for (i = 0; i < musb->nr_endpoints; i++) {
1533                 struct musb_hw_ep       *hw_ep = musb->endpoints + i;
1534 
1535                 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1536 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1537                 if (musb->io.quirks & MUSB_IN_TUSB) {
1538                         hw_ep->fifo_async = musb->async + 0x400 +
1539                                 musb->io.fifo_offset(i);
1540                         hw_ep->fifo_sync = musb->sync + 0x400 +
1541                                 musb->io.fifo_offset(i);
1542                         hw_ep->fifo_sync_va =
1543                                 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1544 
1545                         if (i == 0)
1546                                 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1547                         else
1548                                 hw_ep->conf = mbase + 0x400 +
1549                                         (((i - 1) & 0xf) << 2);
1550                 }
1551 #endif
1552 
1553                 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1554                 hw_ep->rx_reinit = 1;
1555                 hw_ep->tx_reinit = 1;
1556 
1557                 if (hw_ep->max_packet_sz_tx) {
1558                         dev_dbg(musb->controller,
1559                                 "%s: hw_ep %d%s, %smax %d\n",
1560                                 musb_driver_name, i,
1561                                 hw_ep->is_shared_fifo ? "shared" : "tx",
1562                                 hw_ep->tx_double_buffered
1563                                         ? "doublebuffer, " : "",
1564                                 hw_ep->max_packet_sz_tx);
1565                 }
1566                 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1567                         dev_dbg(musb->controller,
1568                                 "%s: hw_ep %d%s, %smax %d\n",
1569                                 musb_driver_name, i,
1570                                 "rx",
1571                                 hw_ep->rx_double_buffered
1572                                         ? "doublebuffer, " : "",
1573                                 hw_ep->max_packet_sz_rx);
1574                 }
1575                 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1576                         dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1577         }
1578 
1579         return 0;
1580 }
1581 
1582 /*-------------------------------------------------------------------------*/
1583 
1584 /*
1585  * handle all the irqs defined by the HDRC core. for now we expect:  other
1586  * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1587  * will be assigned, and the irq will already have been acked.
1588  *
1589  * called in irq context with spinlock held, irqs blocked
1590  */
1591 irqreturn_t musb_interrupt(struct musb *musb)
1592 {
1593         irqreturn_t     retval = IRQ_NONE;
1594         unsigned long   status;
1595         unsigned long   epnum;
1596         u8              devctl;
1597 
1598         if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1599                 return IRQ_NONE;
1600 
1601         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1602 
1603         dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1604                 is_host_active(musb) ? "host" : "peripheral",
1605                 musb->int_usb, musb->int_tx, musb->int_rx);
1606 
1607         /**
1608          * According to Mentor Graphics' documentation, flowchart on page 98,
1609          * IRQ should be handled as follows:
1610          *
1611          * . Resume IRQ
1612          * . Session Request IRQ
1613          * . VBUS Error IRQ
1614          * . Suspend IRQ
1615          * . Connect IRQ
1616          * . Disconnect IRQ
1617          * . Reset/Babble IRQ
1618          * . SOF IRQ (we're not using this one)
1619          * . Endpoint 0 IRQ
1620          * . TX Endpoints
1621          * . RX Endpoints
1622          *
1623          * We will be following that flowchart in order to avoid any problems
1624          * that might arise with internal Finite State Machine.
1625          */
1626 
1627         if (musb->int_usb)
1628                 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1629 
1630         if (musb->int_tx & 1) {
1631                 if (is_host_active(musb))
1632                         retval |= musb_h_ep0_irq(musb);
1633                 else
1634                         retval |= musb_g_ep0_irq(musb);
1635 
1636                 /* we have just handled endpoint 0 IRQ, clear it */
1637                 musb->int_tx &= ~BIT(0);
1638         }
1639 
1640         status = musb->int_tx;
1641 
1642         for_each_set_bit(epnum, &status, 16) {
1643                 retval = IRQ_HANDLED;
1644                 if (is_host_active(musb))
1645                         musb_host_tx(musb, epnum);
1646                 else
1647                         musb_g_tx(musb, epnum);
1648         }
1649 
1650         status = musb->int_rx;
1651 
1652         for_each_set_bit(epnum, &status, 16) {
1653                 retval = IRQ_HANDLED;
1654                 if (is_host_active(musb))
1655                         musb_host_rx(musb, epnum);
1656                 else
1657                         musb_g_rx(musb, epnum);
1658         }
1659 
1660         return retval;
1661 }
1662 EXPORT_SYMBOL_GPL(musb_interrupt);
1663 
1664 #ifndef CONFIG_MUSB_PIO_ONLY
1665 static bool use_dma = 1;
1666 
1667 /* "modprobe ... use_dma=0" etc */
1668 module_param(use_dma, bool, 0644);
1669 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1670 
1671 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1672 {
1673         /* called with controller lock already held */
1674 
1675         if (!epnum) {
1676                 if (!is_cppi_enabled(musb)) {
1677                         /* endpoint 0 */
1678                         if (is_host_active(musb))
1679                                 musb_h_ep0_irq(musb);
1680                         else
1681                                 musb_g_ep0_irq(musb);
1682                 }
1683         } else {
1684                 /* endpoints 1..15 */
1685                 if (transmit) {
1686                         if (is_host_active(musb))
1687                                 musb_host_tx(musb, epnum);
1688                         else
1689                                 musb_g_tx(musb, epnum);
1690                 } else {
1691                         /* receive */
1692                         if (is_host_active(musb))
1693                                 musb_host_rx(musb, epnum);
1694                         else
1695                                 musb_g_rx(musb, epnum);
1696                 }
1697         }
1698 }
1699 EXPORT_SYMBOL_GPL(musb_dma_completion);
1700 
1701 #else
1702 #define use_dma                 0
1703 #endif
1704 
1705 static void (*musb_phy_callback)(enum musb_vbus_id_status status);
1706 
1707 /*
1708  * musb_mailbox - optional phy notifier function
1709  * @status phy state change
1710  *
1711  * Optionally gets called from the USB PHY. Note that the USB PHY must be
1712  * disabled at the point the phy_callback is registered or unregistered.
1713  */
1714 void musb_mailbox(enum musb_vbus_id_status status)
1715 {
1716         if (musb_phy_callback)
1717                 musb_phy_callback(status);
1718 
1719 };
1720 EXPORT_SYMBOL_GPL(musb_mailbox);
1721 
1722 /*-------------------------------------------------------------------------*/
1723 
1724 static ssize_t
1725 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1726 {
1727         struct musb *musb = dev_to_musb(dev);
1728         unsigned long flags;
1729         int ret = -EINVAL;
1730 
1731         spin_lock_irqsave(&musb->lock, flags);
1732         ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1733         spin_unlock_irqrestore(&musb->lock, flags);
1734 
1735         return ret;
1736 }
1737 
1738 static ssize_t
1739 musb_mode_store(struct device *dev, struct device_attribute *attr,
1740                 const char *buf, size_t n)
1741 {
1742         struct musb     *musb = dev_to_musb(dev);
1743         unsigned long   flags;
1744         int             status;
1745 
1746         spin_lock_irqsave(&musb->lock, flags);
1747         if (sysfs_streq(buf, "host"))
1748                 status = musb_platform_set_mode(musb, MUSB_HOST);
1749         else if (sysfs_streq(buf, "peripheral"))
1750                 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1751         else if (sysfs_streq(buf, "otg"))
1752                 status = musb_platform_set_mode(musb, MUSB_OTG);
1753         else
1754                 status = -EINVAL;
1755         spin_unlock_irqrestore(&musb->lock, flags);
1756 
1757         return (status == 0) ? n : status;
1758 }
1759 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1760 
1761 static ssize_t
1762 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1763                 const char *buf, size_t n)
1764 {
1765         struct musb     *musb = dev_to_musb(dev);
1766         unsigned long   flags;
1767         unsigned long   val;
1768 
1769         if (sscanf(buf, "%lu", &val) < 1) {
1770                 dev_err(dev, "Invalid VBUS timeout ms value\n");
1771                 return -EINVAL;
1772         }
1773 
1774         spin_lock_irqsave(&musb->lock, flags);
1775         /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1776         musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1777         if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1778                 musb->is_active = 0;
1779         musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1780         spin_unlock_irqrestore(&musb->lock, flags);
1781 
1782         return n;
1783 }
1784 
1785 static ssize_t
1786 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1787 {
1788         struct musb     *musb = dev_to_musb(dev);
1789         unsigned long   flags;
1790         unsigned long   val;
1791         int             vbus;
1792         u8              devctl;
1793 
1794         spin_lock_irqsave(&musb->lock, flags);
1795         val = musb->a_wait_bcon;
1796         vbus = musb_platform_get_vbus_status(musb);
1797         if (vbus < 0) {
1798                 /* Use default MUSB method by means of DEVCTL register */
1799                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1800                 if ((devctl & MUSB_DEVCTL_VBUS)
1801                                 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1802                         vbus = 1;
1803                 else
1804                         vbus = 0;
1805         }
1806         spin_unlock_irqrestore(&musb->lock, flags);
1807 
1808         return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1809                         vbus ? "on" : "off", val);
1810 }
1811 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1812 
1813 /* Gadget drivers can't know that a host is connected so they might want
1814  * to start SRP, but users can.  This allows userspace to trigger SRP.
1815  */
1816 static ssize_t
1817 musb_srp_store(struct device *dev, struct device_attribute *attr,
1818                 const char *buf, size_t n)
1819 {
1820         struct musb     *musb = dev_to_musb(dev);
1821         unsigned short  srp;
1822 
1823         if (sscanf(buf, "%hu", &srp) != 1
1824                         || (srp != 1)) {
1825                 dev_err(dev, "SRP: Value must be 1\n");
1826                 return -EINVAL;
1827         }
1828 
1829         if (srp == 1)
1830                 musb_g_wakeup(musb);
1831 
1832         return n;
1833 }
1834 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1835 
1836 static struct attribute *musb_attributes[] = {
1837         &dev_attr_mode.attr,
1838         &dev_attr_vbus.attr,
1839         &dev_attr_srp.attr,
1840         NULL
1841 };
1842 
1843 static const struct attribute_group musb_attr_group = {
1844         .attrs = musb_attributes,
1845 };
1846 
1847 /* Only used to provide driver mode change events */
1848 static void musb_irq_work(struct work_struct *data)
1849 {
1850         struct musb *musb = container_of(data, struct musb, irq_work);
1851 
1852         if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1853                 musb->xceiv_old_state = musb->xceiv->otg->state;
1854                 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1855         }
1856 }
1857 
1858 static void musb_recover_from_babble(struct musb *musb)
1859 {
1860         int ret;
1861         u8 devctl;
1862 
1863         musb_disable_interrupts(musb);
1864 
1865         /*
1866          * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1867          * it some slack and wait for 10us.
1868          */
1869         udelay(10);
1870 
1871         ret  = musb_platform_recover(musb);
1872         if (ret) {
1873                 musb_enable_interrupts(musb);
1874                 return;
1875         }
1876 
1877         /* drop session bit */
1878         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1879         devctl &= ~MUSB_DEVCTL_SESSION;
1880         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1881 
1882         /* tell usbcore about it */
1883         musb_root_disconnect(musb);
1884 
1885         /*
1886          * When a babble condition occurs, the musb controller
1887          * removes the session bit and the endpoint config is lost.
1888          */
1889         if (musb->dyn_fifo)
1890                 ret = ep_config_from_table(musb);
1891         else
1892                 ret = ep_config_from_hw(musb);
1893 
1894         /* restart session */
1895         if (ret == 0)
1896                 musb_start(musb);
1897 }
1898 
1899 /* --------------------------------------------------------------------------
1900  * Init support
1901  */
1902 
1903 static struct musb *allocate_instance(struct device *dev,
1904                 struct musb_hdrc_config *config, void __iomem *mbase)
1905 {
1906         struct musb             *musb;
1907         struct musb_hw_ep       *ep;
1908         int                     epnum;
1909         int                     ret;
1910 
1911         musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1912         if (!musb)
1913                 return NULL;
1914 
1915         INIT_LIST_HEAD(&musb->control);
1916         INIT_LIST_HEAD(&musb->in_bulk);
1917         INIT_LIST_HEAD(&musb->out_bulk);
1918 
1919         musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1920         musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1921         musb->mregs = mbase;
1922         musb->ctrl_base = mbase;
1923         musb->nIrq = -ENODEV;
1924         musb->config = config;
1925         BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1926         for (epnum = 0, ep = musb->endpoints;
1927                         epnum < musb->config->num_eps;
1928                         epnum++, ep++) {
1929                 ep->musb = musb;
1930                 ep->epnum = epnum;
1931         }
1932 
1933         musb->controller = dev;
1934 
1935         ret = musb_host_alloc(musb);
1936         if (ret < 0)
1937                 goto err_free;
1938 
1939         dev_set_drvdata(dev, musb);
1940 
1941         return musb;
1942 
1943 err_free:
1944         return NULL;
1945 }
1946 
1947 static void musb_free(struct musb *musb)
1948 {
1949         /* this has multiple entry modes. it handles fault cleanup after
1950          * probe(), where things may be partially set up, as well as rmmod
1951          * cleanup after everything's been de-activated.
1952          */
1953 
1954 #ifdef CONFIG_SYSFS
1955         sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1956 #endif
1957 
1958         if (musb->nIrq >= 0) {
1959                 if (musb->irq_wake)
1960                         disable_irq_wake(musb->nIrq);
1961                 free_irq(musb->nIrq, musb);
1962         }
1963 
1964         musb_host_free(musb);
1965 }
1966 
1967 static void musb_deassert_reset(struct work_struct *work)
1968 {
1969         struct musb *musb;
1970         unsigned long flags;
1971 
1972         musb = container_of(work, struct musb, deassert_reset_work.work);
1973 
1974         spin_lock_irqsave(&musb->lock, flags);
1975 
1976         if (musb->port1_status & USB_PORT_STAT_RESET)
1977                 musb_port_reset(musb, false);
1978 
1979         spin_unlock_irqrestore(&musb->lock, flags);
1980 }
1981 
1982 /*
1983  * Perform generic per-controller initialization.
1984  *
1985  * @dev: the controller (already clocked, etc)
1986  * @nIrq: IRQ number
1987  * @ctrl: virtual address of controller registers,
1988  *      not yet corrected for platform-specific offsets
1989  */
1990 static int
1991 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1992 {
1993         int                     status;
1994         struct musb             *musb;
1995         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1996 
1997         /* The driver might handle more features than the board; OK.
1998          * Fail when the board needs a feature that's not enabled.
1999          */
2000         if (!plat) {
2001                 dev_dbg(dev, "no platform_data?\n");
2002                 status = -ENODEV;
2003                 goto fail0;
2004         }
2005 
2006         /* allocate */
2007         musb = allocate_instance(dev, plat->config, ctrl);
2008         if (!musb) {
2009                 status = -ENOMEM;
2010                 goto fail0;
2011         }
2012 
2013         spin_lock_init(&musb->lock);
2014         musb->board_set_power = plat->set_power;
2015         musb->min_power = plat->min_power;
2016         musb->ops = plat->platform_ops;
2017         musb->port_mode = plat->mode;
2018 
2019         /*
2020          * Initialize the default IO functions. At least omap2430 needs
2021          * these early. We initialize the platform specific IO functions
2022          * later on.
2023          */
2024         musb_readb = musb_default_readb;
2025         musb_writeb = musb_default_writeb;
2026         musb_readw = musb_default_readw;
2027         musb_writew = musb_default_writew;
2028         musb_readl = musb_default_readl;
2029         musb_writel = musb_default_writel;
2030 
2031         /* We need musb_read/write functions initialized for PM */
2032         pm_runtime_use_autosuspend(musb->controller);
2033         pm_runtime_set_autosuspend_delay(musb->controller, 200);
2034         pm_runtime_enable(musb->controller);
2035 
2036         /* The musb_platform_init() call:
2037          *   - adjusts musb->mregs
2038          *   - sets the musb->isr
2039          *   - may initialize an integrated transceiver
2040          *   - initializes musb->xceiv, usually by otg_get_phy()
2041          *   - stops powering VBUS
2042          *
2043          * There are various transceiver configurations.  Blackfin,
2044          * DaVinci, TUSB60x0, and others integrate them.  OMAP3 uses
2045          * external/discrete ones in various flavors (twl4030 family,
2046          * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2047          */
2048         status = musb_platform_init(musb);
2049         if (status < 0)
2050                 goto fail1;
2051 
2052         if (!musb->isr) {
2053                 status = -ENODEV;
2054                 goto fail2;
2055         }
2056 
2057         if (musb->ops->quirks)
2058                 musb->io.quirks = musb->ops->quirks;
2059 
2060         /* Most devices use indexed offset or flat offset */
2061         if (musb->io.quirks & MUSB_INDEXED_EP) {
2062                 musb->io.ep_offset = musb_indexed_ep_offset;
2063                 musb->io.ep_select = musb_indexed_ep_select;
2064         } else {
2065                 musb->io.ep_offset = musb_flat_ep_offset;
2066                 musb->io.ep_select = musb_flat_ep_select;
2067         }
2068         /* And override them with platform specific ops if specified. */
2069         if (musb->ops->ep_offset)
2070                 musb->io.ep_offset = musb->ops->ep_offset;
2071         if (musb->ops->ep_select)
2072                 musb->io.ep_select = musb->ops->ep_select;
2073 
2074         /* At least tusb6010 has its own offsets */
2075         if (musb->ops->ep_offset)
2076                 musb->io.ep_offset = musb->ops->ep_offset;
2077         if (musb->ops->ep_select)
2078                 musb->io.ep_select = musb->ops->ep_select;
2079 
2080         if (musb->ops->fifo_mode)
2081                 fifo_mode = musb->ops->fifo_mode;
2082         else
2083                 fifo_mode = 4;
2084 
2085         if (musb->ops->fifo_offset)
2086                 musb->io.fifo_offset = musb->ops->fifo_offset;
2087         else
2088                 musb->io.fifo_offset = musb_default_fifo_offset;
2089 
2090         if (musb->ops->busctl_offset)
2091                 musb->io.busctl_offset = musb->ops->busctl_offset;
2092         else
2093                 musb->io.busctl_offset = musb_default_busctl_offset;
2094 
2095         if (musb->ops->readb)
2096                 musb_readb = musb->ops->readb;
2097         if (musb->ops->writeb)
2098                 musb_writeb = musb->ops->writeb;
2099         if (musb->ops->readw)
2100                 musb_readw = musb->ops->readw;
2101         if (musb->ops->writew)
2102                 musb_writew = musb->ops->writew;
2103         if (musb->ops->readl)
2104                 musb_readl = musb->ops->readl;
2105         if (musb->ops->writel)
2106                 musb_writel = musb->ops->writel;
2107 
2108 #ifndef CONFIG_MUSB_PIO_ONLY
2109         if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2110                 dev_err(dev, "DMA controller not set\n");
2111                 status = -ENODEV;
2112                 goto fail2;
2113         }
2114         musb_dma_controller_create = musb->ops->dma_init;
2115         musb_dma_controller_destroy = musb->ops->dma_exit;
2116 #endif
2117 
2118         if (musb->ops->read_fifo)
2119                 musb->io.read_fifo = musb->ops->read_fifo;
2120         else
2121                 musb->io.read_fifo = musb_default_read_fifo;
2122 
2123         if (musb->ops->write_fifo)
2124                 musb->io.write_fifo = musb->ops->write_fifo;
2125         else
2126                 musb->io.write_fifo = musb_default_write_fifo;
2127 
2128         if (!musb->xceiv->io_ops) {
2129                 musb->xceiv->io_dev = musb->controller;
2130                 musb->xceiv->io_priv = musb->mregs;
2131                 musb->xceiv->io_ops = &musb_ulpi_access;
2132         }
2133 
2134         if (musb->ops->phy_callback)
2135                 musb_phy_callback = musb->ops->phy_callback;
2136 
2137         pm_runtime_get_sync(musb->controller);
2138 
2139         status = usb_phy_init(musb->xceiv);
2140         if (status < 0)
2141                 goto err_usb_phy_init;
2142 
2143         if (use_dma && dev->dma_mask) {
2144                 musb->dma_controller =
2145                         musb_dma_controller_create(musb, musb->mregs);
2146                 if (IS_ERR(musb->dma_controller)) {
2147                         status = PTR_ERR(musb->dma_controller);
2148                         goto fail2_5;
2149                 }
2150         }
2151 
2152         /* be sure interrupts are disabled before connecting ISR */
2153         musb_platform_disable(musb);
2154         musb_generic_disable(musb);
2155 
2156         /* Init IRQ workqueue before request_irq */
2157         INIT_WORK(&musb->irq_work, musb_irq_work);
2158         INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2159         INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2160 
2161         /* setup musb parts of the core (especially endpoints) */
2162         status = musb_core_init(plat->config->multipoint
2163                         ? MUSB_CONTROLLER_MHDRC
2164                         : MUSB_CONTROLLER_HDRC, musb);
2165         if (status < 0)
2166                 goto fail3;
2167 
2168         setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2169 
2170         /* attach to the IRQ */
2171         if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2172                 dev_err(dev, "request_irq %d failed!\n", nIrq);
2173                 status = -ENODEV;
2174                 goto fail3;
2175         }
2176         musb->nIrq = nIrq;
2177         /* FIXME this handles wakeup irqs wrong */
2178         if (enable_irq_wake(nIrq) == 0) {
2179                 musb->irq_wake = 1;
2180                 device_init_wakeup(dev, 1);
2181         } else {
2182                 musb->irq_wake = 0;
2183         }
2184 
2185         /* program PHY to use external vBus if required */
2186         if (plat->extvbus) {
2187                 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2188                 busctl |= MUSB_ULPI_USE_EXTVBUS;
2189                 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2190         }
2191 
2192         if (musb->xceiv->otg->default_a) {
2193                 MUSB_HST_MODE(musb);
2194                 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2195         } else {
2196                 MUSB_DEV_MODE(musb);
2197                 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2198         }
2199 
2200         switch (musb->port_mode) {
2201         case MUSB_PORT_MODE_HOST:
2202                 status = musb_host_setup(musb, plat->power);
2203                 if (status < 0)
2204                         goto fail3;
2205                 status = musb_platform_set_mode(musb, MUSB_HOST);
2206                 break;
2207         case MUSB_PORT_MODE_GADGET:
2208                 status = musb_gadget_setup(musb);
2209                 if (status < 0)
2210                         goto fail3;
2211                 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2212                 break;
2213         case MUSB_PORT_MODE_DUAL_ROLE:
2214                 status = musb_host_setup(musb, plat->power);
2215                 if (status < 0)
2216                         goto fail3;
2217                 status = musb_gadget_setup(musb);
2218                 if (status) {
2219                         musb_host_cleanup(musb);
2220                         goto fail3;
2221                 }
2222                 status = musb_platform_set_mode(musb, MUSB_OTG);
2223                 break;
2224         default:
2225                 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2226                 break;
2227         }
2228 
2229         if (status < 0)
2230                 goto fail3;
2231 
2232         status = musb_init_debugfs(musb);
2233         if (status < 0)
2234                 goto fail4;
2235 
2236         status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2237         if (status)
2238                 goto fail5;
2239 
2240         pm_runtime_put(musb->controller);
2241 
2242         /*
2243          * For why this is currently needed, see commit 3e43a0725637
2244          * ("usb: musb: core: add pm_runtime_irq_safe()")
2245          */
2246         pm_runtime_irq_safe(musb->controller);
2247 
2248         return 0;
2249 
2250 fail5:
2251         musb_exit_debugfs(musb);
2252 
2253 fail4:
2254         musb_gadget_cleanup(musb);
2255         musb_host_cleanup(musb);
2256 
2257 fail3:
2258         cancel_work_sync(&musb->irq_work);
2259         cancel_delayed_work_sync(&musb->finish_resume_work);
2260         cancel_delayed_work_sync(&musb->deassert_reset_work);
2261         if (musb->dma_controller)
2262                 musb_dma_controller_destroy(musb->dma_controller);
2263 
2264 fail2_5:
2265         usb_phy_shutdown(musb->xceiv);
2266 
2267 err_usb_phy_init:
2268         pm_runtime_put_sync(musb->controller);
2269 
2270 fail2:
2271         if (musb->irq_wake)
2272                 device_init_wakeup(dev, 0);
2273         musb_platform_exit(musb);
2274 
2275 fail1:
2276         pm_runtime_disable(musb->controller);
2277         dev_err(musb->controller,
2278                 "musb_init_controller failed with status %d\n", status);
2279 
2280         musb_free(musb);
2281 
2282 fail0:
2283 
2284         return status;
2285 
2286 }
2287 
2288 /*-------------------------------------------------------------------------*/
2289 
2290 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2291  * bridge to a platform device; this driver then suffices.
2292  */
2293 static int musb_probe(struct platform_device *pdev)
2294 {
2295         struct device   *dev = &pdev->dev;
2296         int             irq = platform_get_irq_byname(pdev, "mc");
2297         struct resource *iomem;
2298         void __iomem    *base;
2299 
2300         if (irq <= 0)
2301                 return -ENODEV;
2302 
2303         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2304         base = devm_ioremap_resource(dev, iomem);
2305         if (IS_ERR(base))
2306                 return PTR_ERR(base);
2307 
2308         return musb_init_controller(dev, irq, base);
2309 }
2310 
2311 static int musb_remove(struct platform_device *pdev)
2312 {
2313         struct device   *dev = &pdev->dev;
2314         struct musb     *musb = dev_to_musb(dev);
2315 
2316         /* this gets called on rmmod.
2317          *  - Host mode: host may still be active
2318          *  - Peripheral mode: peripheral is deactivated (or never-activated)
2319          *  - OTG mode: both roles are deactivated (or never-activated)
2320          */
2321         musb_exit_debugfs(musb);
2322         musb_shutdown(pdev);
2323         musb_phy_callback = NULL;
2324 
2325         if (musb->dma_controller)
2326                 musb_dma_controller_destroy(musb->dma_controller);
2327 
2328         usb_phy_shutdown(musb->xceiv);
2329 
2330         cancel_work_sync(&musb->irq_work);
2331         cancel_delayed_work_sync(&musb->finish_resume_work);
2332         cancel_delayed_work_sync(&musb->deassert_reset_work);
2333         musb_free(musb);
2334         device_init_wakeup(dev, 0);
2335         return 0;
2336 }
2337 
2338 #ifdef  CONFIG_PM
2339 
2340 static void musb_save_context(struct musb *musb)
2341 {
2342         int i;
2343         void __iomem *musb_base = musb->mregs;
2344         void __iomem *epio;
2345 
2346         musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2347         musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2348         musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2349         musb->context.power = musb_readb(musb_base, MUSB_POWER);
2350         musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2351         musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2352         musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2353 
2354         for (i = 0; i < musb->config->num_eps; ++i) {
2355                 struct musb_hw_ep       *hw_ep;
2356 
2357                 hw_ep = &musb->endpoints[i];
2358                 if (!hw_ep)
2359                         continue;
2360 
2361                 epio = hw_ep->regs;
2362                 if (!epio)
2363                         continue;
2364 
2365                 musb_writeb(musb_base, MUSB_INDEX, i);
2366                 musb->context.index_regs[i].txmaxp =
2367                         musb_readw(epio, MUSB_TXMAXP);
2368                 musb->context.index_regs[i].txcsr =
2369                         musb_readw(epio, MUSB_TXCSR);
2370                 musb->context.index_regs[i].rxmaxp =
2371                         musb_readw(epio, MUSB_RXMAXP);
2372                 musb->context.index_regs[i].rxcsr =
2373                         musb_readw(epio, MUSB_RXCSR);
2374 
2375                 if (musb->dyn_fifo) {
2376                         musb->context.index_regs[i].txfifoadd =
2377                                         musb_read_txfifoadd(musb_base);
2378                         musb->context.index_regs[i].rxfifoadd =
2379                                         musb_read_rxfifoadd(musb_base);
2380                         musb->context.index_regs[i].txfifosz =
2381                                         musb_read_txfifosz(musb_base);
2382                         musb->context.index_regs[i].rxfifosz =
2383                                         musb_read_rxfifosz(musb_base);
2384                 }
2385 
2386                 musb->context.index_regs[i].txtype =
2387                         musb_readb(epio, MUSB_TXTYPE);
2388                 musb->context.index_regs[i].txinterval =
2389                         musb_readb(epio, MUSB_TXINTERVAL);
2390                 musb->context.index_regs[i].rxtype =
2391                         musb_readb(epio, MUSB_RXTYPE);
2392                 musb->context.index_regs[i].rxinterval =
2393                         musb_readb(epio, MUSB_RXINTERVAL);
2394 
2395                 musb->context.index_regs[i].txfunaddr =
2396                         musb_read_txfunaddr(musb, i);
2397                 musb->context.index_regs[i].txhubaddr =
2398                         musb_read_txhubaddr(musb, i);
2399                 musb->context.index_regs[i].txhubport =
2400                         musb_read_txhubport(musb, i);
2401 
2402                 musb->context.index_regs[i].rxfunaddr =
2403                         musb_read_rxfunaddr(musb, i);
2404                 musb->context.index_regs[i].rxhubaddr =
2405                         musb_read_rxhubaddr(musb, i);
2406                 musb->context.index_regs[i].rxhubport =
2407                         musb_read_rxhubport(musb, i);
2408         }
2409 }
2410 
2411 static void musb_restore_context(struct musb *musb)
2412 {
2413         int i;
2414         void __iomem *musb_base = musb->mregs;
2415         void __iomem *epio;
2416         u8 power;
2417 
2418         musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2419         musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2420         musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2421 
2422         /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2423         power = musb_readb(musb_base, MUSB_POWER);
2424         power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2425         musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2426         power |= musb->context.power;
2427         musb_writeb(musb_base, MUSB_POWER, power);
2428 
2429         musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2430         musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2431         musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2432         musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2433 
2434         for (i = 0; i < musb->config->num_eps; ++i) {
2435                 struct musb_hw_ep       *hw_ep;
2436 
2437                 hw_ep = &musb->endpoints[i];
2438                 if (!hw_ep)
2439                         continue;
2440 
2441                 epio = hw_ep->regs;
2442                 if (!epio)
2443                         continue;
2444 
2445                 musb_writeb(musb_base, MUSB_INDEX, i);
2446                 musb_writew(epio, MUSB_TXMAXP,
2447                         musb->context.index_regs[i].txmaxp);
2448                 musb_writew(epio, MUSB_TXCSR,
2449                         musb->context.index_regs[i].txcsr);
2450                 musb_writew(epio, MUSB_RXMAXP,
2451                         musb->context.index_regs[i].rxmaxp);
2452                 musb_writew(epio, MUSB_RXCSR,
2453                         musb->context.index_regs[i].rxcsr);
2454 
2455                 if (musb->dyn_fifo) {
2456                         musb_write_txfifosz(musb_base,
2457                                 musb->context.index_regs[i].txfifosz);
2458                         musb_write_rxfifosz(musb_base,
2459                                 musb->context.index_regs[i].rxfifosz);
2460                         musb_write_txfifoadd(musb_base,
2461                                 musb->context.index_regs[i].txfifoadd);
2462                         musb_write_rxfifoadd(musb_base,
2463                                 musb->context.index_regs[i].rxfifoadd);
2464                 }
2465 
2466                 musb_writeb(epio, MUSB_TXTYPE,
2467                                 musb->context.index_regs[i].txtype);
2468                 musb_writeb(epio, MUSB_TXINTERVAL,
2469                                 musb->context.index_regs[i].txinterval);
2470                 musb_writeb(epio, MUSB_RXTYPE,
2471                                 musb->context.index_regs[i].rxtype);
2472                 musb_writeb(epio, MUSB_RXINTERVAL,
2473 
2474                                 musb->context.index_regs[i].rxinterval);
2475                 musb_write_txfunaddr(musb, i,
2476                                 musb->context.index_regs[i].txfunaddr);
2477                 musb_write_txhubaddr(musb, i,
2478                                 musb->context.index_regs[i].txhubaddr);
2479                 musb_write_txhubport(musb, i,
2480                                 musb->context.index_regs[i].txhubport);
2481 
2482                 musb_write_rxfunaddr(musb, i,
2483                                 musb->context.index_regs[i].rxfunaddr);
2484                 musb_write_rxhubaddr(musb, i,
2485                                 musb->context.index_regs[i].rxhubaddr);
2486                 musb_write_rxhubport(musb, i,
2487                                 musb->context.index_regs[i].rxhubport);
2488         }
2489         musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2490 }
2491 
2492 static int musb_suspend(struct device *dev)
2493 {
2494         struct musb     *musb = dev_to_musb(dev);
2495         unsigned long   flags;
2496 
2497         musb_platform_disable(musb);
2498         musb_generic_disable(musb);
2499 
2500         spin_lock_irqsave(&musb->lock, flags);
2501 
2502         if (is_peripheral_active(musb)) {
2503                 /* FIXME force disconnect unless we know USB will wake
2504                  * the system up quickly enough to respond ...
2505                  */
2506         } else if (is_host_active(musb)) {
2507                 /* we know all the children are suspended; sometimes
2508                  * they will even be wakeup-enabled.
2509                  */
2510         }
2511 
2512         musb_save_context(musb);
2513 
2514         spin_unlock_irqrestore(&musb->lock, flags);
2515         return 0;
2516 }
2517 
2518 static int musb_resume(struct device *dev)
2519 {
2520         struct musb     *musb = dev_to_musb(dev);
2521         u8              devctl;
2522         u8              mask;
2523 
2524         /*
2525          * For static cmos like DaVinci, register values were preserved
2526          * unless for some reason the whole soc powered down or the USB
2527          * module got reset through the PSC (vs just being disabled).
2528          *
2529          * For the DSPS glue layer though, a full register restore has to
2530          * be done. As it shouldn't harm other platforms, we do it
2531          * unconditionally.
2532          */
2533 
2534         musb_restore_context(musb);
2535 
2536         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2537         mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2538         if ((devctl & mask) != (musb->context.devctl & mask))
2539                 musb->port1_status = 0;
2540         if (musb->need_finish_resume) {
2541                 musb->need_finish_resume = 0;
2542                 schedule_delayed_work(&musb->finish_resume_work,
2543                                       msecs_to_jiffies(USB_RESUME_TIMEOUT));
2544         }
2545 
2546         /*
2547          * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2548          * out of suspend
2549          */
2550         pm_runtime_disable(dev);
2551         pm_runtime_set_active(dev);
2552         pm_runtime_enable(dev);
2553 
2554         musb_start(musb);
2555 
2556         return 0;
2557 }
2558 
2559 static int musb_runtime_suspend(struct device *dev)
2560 {
2561         struct musb     *musb = dev_to_musb(dev);
2562 
2563         musb_save_context(musb);
2564 
2565         return 0;
2566 }
2567 
2568 static int musb_runtime_resume(struct device *dev)
2569 {
2570         struct musb     *musb = dev_to_musb(dev);
2571         static int      first = 1;
2572 
2573         /*
2574          * When pm_runtime_get_sync called for the first time in driver
2575          * init,  some of the structure is still not initialized which is
2576          * used in restore function. But clock needs to be
2577          * enabled before any register access, so
2578          * pm_runtime_get_sync has to be called.
2579          * Also context restore without save does not make
2580          * any sense
2581          */
2582         if (!first)
2583                 musb_restore_context(musb);
2584         first = 0;
2585 
2586         if (musb->need_finish_resume) {
2587                 musb->need_finish_resume = 0;
2588                 schedule_delayed_work(&musb->finish_resume_work,
2589                                 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2590         }
2591 
2592         return 0;
2593 }
2594 
2595 static const struct dev_pm_ops musb_dev_pm_ops = {
2596         .suspend        = musb_suspend,
2597         .resume         = musb_resume,
2598         .runtime_suspend = musb_runtime_suspend,
2599         .runtime_resume = musb_runtime_resume,
2600 };
2601 
2602 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2603 #else
2604 #define MUSB_DEV_PM_OPS NULL
2605 #endif
2606 
2607 static struct platform_driver musb_driver = {
2608         .driver = {
2609                 .name           = (char *)musb_driver_name,
2610                 .bus            = &platform_bus_type,
2611                 .pm             = MUSB_DEV_PM_OPS,
2612         },
2613         .probe          = musb_probe,
2614         .remove         = musb_remove,
2615         .shutdown       = musb_shutdown,
2616 };
2617 
2618 module_platform_driver(musb_driver);
2619 

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