Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/usb/musb/blackfin.c

  1 /*
  2  * MUSB OTG controller driver for Blackfin Processors
  3  *
  4  * Copyright 2006-2008 Analog Devices Inc.
  5  *
  6  * Enter bugs at http://blackfin.uclinux.org/
  7  *
  8  * Licensed under the GPL-2 or later.
  9  */
 10 
 11 #include <linux/module.h>
 12 #include <linux/kernel.h>
 13 #include <linux/sched.h>
 14 #include <linux/list.h>
 15 #include <linux/gpio.h>
 16 #include <linux/io.h>
 17 #include <linux/err.h>
 18 #include <linux/platform_device.h>
 19 #include <linux/dma-mapping.h>
 20 #include <linux/prefetch.h>
 21 #include <linux/usb/usb_phy_generic.h>
 22 
 23 #include <asm/cacheflush.h>
 24 
 25 #include "musb_core.h"
 26 #include "musbhsdma.h"
 27 #include "blackfin.h"
 28 
 29 struct bfin_glue {
 30         struct device           *dev;
 31         struct platform_device  *musb;
 32         struct platform_device  *phy;
 33 };
 34 #define glue_to_musb(g)         platform_get_drvdata(g->musb)
 35 
 36 /*
 37  * Load an endpoint's FIFO
 38  */
 39 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
 40 {
 41         struct musb *musb = hw_ep->musb;
 42         void __iomem *fifo = hw_ep->fifo;
 43         void __iomem *epio = hw_ep->regs;
 44         u8 epnum = hw_ep->epnum;
 45 
 46         prefetch((u8 *)src);
 47 
 48         musb_writew(epio, MUSB_TXCOUNT, len);
 49 
 50         dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
 51                         hw_ep->epnum, fifo, len, src, epio);
 52 
 53         dump_fifo_data(src, len);
 54 
 55         if (!ANOMALY_05000380 && epnum != 0) {
 56                 u16 dma_reg;
 57 
 58                 flush_dcache_range((unsigned long)src,
 59                         (unsigned long)(src + len));
 60 
 61                 /* Setup DMA address register */
 62                 dma_reg = (u32)src;
 63                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
 64                 SSYNC();
 65 
 66                 dma_reg = (u32)src >> 16;
 67                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
 68                 SSYNC();
 69 
 70                 /* Setup DMA count register */
 71                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
 72                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
 73                 SSYNC();
 74 
 75                 /* Enable the DMA */
 76                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
 77                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
 78                 SSYNC();
 79 
 80                 /* Wait for complete */
 81                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
 82                         cpu_relax();
 83 
 84                 /* acknowledge dma interrupt */
 85                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
 86                 SSYNC();
 87 
 88                 /* Reset DMA */
 89                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
 90                 SSYNC();
 91         } else {
 92                 SSYNC();
 93 
 94                 if (unlikely((unsigned long)src & 0x01))
 95                         outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
 96                 else
 97                         outsw((unsigned long)fifo, src, (len + 1) >> 1);
 98         }
 99 }
100 /*
101  * Unload an endpoint's FIFO
102  */
103 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
104 {
105         struct musb *musb = hw_ep->musb;
106         void __iomem *fifo = hw_ep->fifo;
107         u8 epnum = hw_ep->epnum;
108 
109         if (ANOMALY_05000467 && epnum != 0) {
110                 u16 dma_reg;
111 
112                 invalidate_dcache_range((unsigned long)dst,
113                         (unsigned long)(dst + len));
114 
115                 /* Setup DMA address register */
116                 dma_reg = (u32)dst;
117                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
118                 SSYNC();
119 
120                 dma_reg = (u32)dst >> 16;
121                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
122                 SSYNC();
123 
124                 /* Setup DMA count register */
125                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
126                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
127                 SSYNC();
128 
129                 /* Enable the DMA */
130                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
131                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
132                 SSYNC();
133 
134                 /* Wait for complete */
135                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
136                         cpu_relax();
137 
138                 /* acknowledge dma interrupt */
139                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
140                 SSYNC();
141 
142                 /* Reset DMA */
143                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
144                 SSYNC();
145         } else {
146                 SSYNC();
147                 /* Read the last byte of packet with odd size from address fifo + 4
148                  * to trigger 1 byte access to EP0 FIFO.
149                  */
150                 if (len == 1)
151                         *dst = (u8)inw((unsigned long)fifo + 4);
152                 else {
153                         if (unlikely((unsigned long)dst & 0x01))
154                                 insw_8((unsigned long)fifo, dst, len >> 1);
155                         else
156                                 insw((unsigned long)fifo, dst, len >> 1);
157 
158                         if (len & 0x01)
159                                 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
160                 }
161         }
162         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
163                         'R', hw_ep->epnum, fifo, len, dst);
164 
165         dump_fifo_data(dst, len);
166 }
167 
168 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
169 {
170         unsigned long   flags;
171         irqreturn_t     retval = IRQ_NONE;
172         struct musb     *musb = __hci;
173 
174         spin_lock_irqsave(&musb->lock, flags);
175 
176         musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
177         musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
178         musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
179 
180         if (musb->int_usb || musb->int_tx || musb->int_rx) {
181                 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
182                 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
183                 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
184                 retval = musb_interrupt(musb);
185         }
186 
187         /* Start sampling ID pin, when plug is removed from MUSB */
188         if ((musb->xceiv->state == OTG_STATE_B_IDLE
189                 || musb->xceiv->state == OTG_STATE_A_WAIT_BCON) ||
190                 (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
191                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
192                 musb->a_wait_bcon = TIMER_DELAY;
193         }
194 
195         spin_unlock_irqrestore(&musb->lock, flags);
196 
197         return retval;
198 }
199 
200 static void musb_conn_timer_handler(unsigned long _musb)
201 {
202         struct musb *musb = (void *)_musb;
203         unsigned long flags;
204         u16 val;
205         static u8 toggle;
206 
207         spin_lock_irqsave(&musb->lock, flags);
208         switch (musb->xceiv->state) {
209         case OTG_STATE_A_IDLE:
210         case OTG_STATE_A_WAIT_BCON:
211                 /* Start a new session */
212                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
213                 val &= ~MUSB_DEVCTL_SESSION;
214                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
215                 val |= MUSB_DEVCTL_SESSION;
216                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
217                 /* Check if musb is host or peripheral. */
218                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
219 
220                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
221                         gpio_set_value(musb->config->gpio_vrsel, 1);
222                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
223                 } else {
224                         gpio_set_value(musb->config->gpio_vrsel, 0);
225                         /* Ignore VBUSERROR and SUSPEND IRQ */
226                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
227                         val &= ~MUSB_INTR_VBUSERROR;
228                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
229 
230                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
231                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
232                         musb->xceiv->state = OTG_STATE_B_IDLE;
233                 }
234                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
235                 break;
236         case OTG_STATE_B_IDLE:
237                 /*
238                  * Start a new session.  It seems that MUSB needs taking
239                  * some time to recognize the type of the plug inserted?
240                  */
241                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
242                 val |= MUSB_DEVCTL_SESSION;
243                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
244                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
245 
246                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
247                         gpio_set_value(musb->config->gpio_vrsel, 1);
248                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
249                 } else {
250                         gpio_set_value(musb->config->gpio_vrsel, 0);
251 
252                         /* Ignore VBUSERROR and SUSPEND IRQ */
253                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
254                         val &= ~MUSB_INTR_VBUSERROR;
255                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
256 
257                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
258                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
259 
260                         /* Toggle the Soft Conn bit, so that we can response to
261                          * the inserting of either A-plug or B-plug.
262                          */
263                         if (toggle) {
264                                 val = musb_readb(musb->mregs, MUSB_POWER);
265                                 val &= ~MUSB_POWER_SOFTCONN;
266                                 musb_writeb(musb->mregs, MUSB_POWER, val);
267                                 toggle = 0;
268                         } else {
269                                 val = musb_readb(musb->mregs, MUSB_POWER);
270                                 val |= MUSB_POWER_SOFTCONN;
271                                 musb_writeb(musb->mregs, MUSB_POWER, val);
272                                 toggle = 1;
273                         }
274                         /* The delay time is set to 1/4 second by default,
275                          * shortening it, if accelerating A-plug detection
276                          * is needed in OTG mode.
277                          */
278                         mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
279                 }
280                 break;
281         default:
282                 dev_dbg(musb->controller, "%s state not handled\n",
283                         usb_otg_state_string(musb->xceiv->state));
284                 break;
285         }
286         spin_unlock_irqrestore(&musb->lock, flags);
287 
288         dev_dbg(musb->controller, "state is %s\n",
289                 usb_otg_state_string(musb->xceiv->state));
290 }
291 
292 static void bfin_musb_enable(struct musb *musb)
293 {
294         /* REVISIT is this really correct ? */
295 }
296 
297 static void bfin_musb_disable(struct musb *musb)
298 {
299 }
300 
301 static void bfin_musb_set_vbus(struct musb *musb, int is_on)
302 {
303         int value = musb->config->gpio_vrsel_active;
304         if (!is_on)
305                 value = !value;
306         gpio_set_value(musb->config->gpio_vrsel, value);
307 
308         dev_dbg(musb->controller, "VBUS %s, devctl %02x "
309                 /* otg %3x conf %08x prcm %08x */ "\n",
310                 usb_otg_state_string(musb->xceiv->state),
311                 musb_readb(musb->mregs, MUSB_DEVCTL));
312 }
313 
314 static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
315 {
316         return 0;
317 }
318 
319 static int bfin_musb_vbus_status(struct musb *musb)
320 {
321         return 0;
322 }
323 
324 static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
325 {
326         return -EIO;
327 }
328 
329 static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
330                                 u16 packet_sz, u8 *mode,
331                                 dma_addr_t *dma_addr, u32 *len)
332 {
333         struct musb_dma_channel *musb_channel = channel->private_data;
334 
335         /*
336          * Anomaly 05000450 might cause data corruption when using DMA
337          * MODE 1 transmits with short packet.  So to work around this,
338          * we truncate all MODE 1 transfers down to a multiple of the
339          * max packet size, and then do the last short packet transfer
340          * (if there is any) using MODE 0.
341          */
342         if (ANOMALY_05000450) {
343                 if (musb_channel->transmit && *mode == 1)
344                         *len = *len - (*len % packet_sz);
345         }
346 
347         return 0;
348 }
349 
350 static void bfin_musb_reg_init(struct musb *musb)
351 {
352         if (ANOMALY_05000346) {
353                 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
354                 SSYNC();
355         }
356 
357         if (ANOMALY_05000347) {
358                 bfin_write_USB_APHY_CNTRL(0x0);
359                 SSYNC();
360         }
361 
362         /* Configure PLL oscillator register */
363         bfin_write_USB_PLLOSC_CTRL(0x3080 |
364                         ((480/musb->config->clkin) << 1));
365         SSYNC();
366 
367         bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
368         SSYNC();
369 
370         bfin_write_USB_EP_NI0_RXMAXP(64);
371         SSYNC();
372 
373         bfin_write_USB_EP_NI0_TXMAXP(64);
374         SSYNC();
375 
376         /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
377         bfin_write_USB_GLOBINTR(0x7);
378         SSYNC();
379 
380         bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
381                                 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
382                                 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
383                                 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
384                                 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
385         SSYNC();
386 }
387 
388 static int bfin_musb_init(struct musb *musb)
389 {
390 
391         /*
392          * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
393          * and OTG HOST modes, while rev 1.1 and greater require PE7 to
394          * be low for DEVICE mode and high for HOST mode. We set it high
395          * here because we are in host mode
396          */
397 
398         if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
399                 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
400                         musb->config->gpio_vrsel);
401                 return -ENODEV;
402         }
403         gpio_direction_output(musb->config->gpio_vrsel, 0);
404 
405         musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
406         if (IS_ERR_OR_NULL(musb->xceiv)) {
407                 gpio_free(musb->config->gpio_vrsel);
408                 return -EPROBE_DEFER;
409         }
410 
411         bfin_musb_reg_init(musb);
412 
413         setup_timer(&musb_conn_timer, musb_conn_timer_handler,
414                         (unsigned long) musb);
415 
416         musb->xceiv->set_power = bfin_musb_set_power;
417 
418         musb->isr = blackfin_interrupt;
419         musb->double_buffer_not_ok = true;
420 
421         return 0;
422 }
423 
424 static int bfin_musb_exit(struct musb *musb)
425 {
426         gpio_free(musb->config->gpio_vrsel);
427         usb_put_phy(musb->xceiv);
428 
429         return 0;
430 }
431 
432 static const struct musb_platform_ops bfin_ops = {
433         .init           = bfin_musb_init,
434         .exit           = bfin_musb_exit,
435 
436         .enable         = bfin_musb_enable,
437         .disable        = bfin_musb_disable,
438 
439         .set_mode       = bfin_musb_set_mode,
440 
441         .vbus_status    = bfin_musb_vbus_status,
442         .set_vbus       = bfin_musb_set_vbus,
443 
444         .adjust_channel_params = bfin_musb_adjust_channel_params,
445 };
446 
447 static u64 bfin_dmamask = DMA_BIT_MASK(32);
448 
449 static int bfin_probe(struct platform_device *pdev)
450 {
451         struct resource musb_resources[2];
452         struct musb_hdrc_platform_data  *pdata = dev_get_platdata(&pdev->dev);
453         struct platform_device          *musb;
454         struct bfin_glue                *glue;
455 
456         int                             ret = -ENOMEM;
457 
458         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
459         if (!glue) {
460                 dev_err(&pdev->dev, "failed to allocate glue context\n");
461                 goto err0;
462         }
463 
464         musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
465         if (!musb) {
466                 dev_err(&pdev->dev, "failed to allocate musb device\n");
467                 goto err1;
468         }
469 
470         musb->dev.parent                = &pdev->dev;
471         musb->dev.dma_mask              = &bfin_dmamask;
472         musb->dev.coherent_dma_mask     = bfin_dmamask;
473 
474         glue->dev                       = &pdev->dev;
475         glue->musb                      = musb;
476 
477         pdata->platform_ops             = &bfin_ops;
478 
479         glue->phy = usb_phy_generic_register();
480         if (IS_ERR(glue->phy))
481                 goto err2;
482         platform_set_drvdata(pdev, glue);
483 
484         memset(musb_resources, 0x00, sizeof(*musb_resources) *
485                         ARRAY_SIZE(musb_resources));
486 
487         musb_resources[0].name = pdev->resource[0].name;
488         musb_resources[0].start = pdev->resource[0].start;
489         musb_resources[0].end = pdev->resource[0].end;
490         musb_resources[0].flags = pdev->resource[0].flags;
491 
492         musb_resources[1].name = pdev->resource[1].name;
493         musb_resources[1].start = pdev->resource[1].start;
494         musb_resources[1].end = pdev->resource[1].end;
495         musb_resources[1].flags = pdev->resource[1].flags;
496 
497         ret = platform_device_add_resources(musb, musb_resources,
498                         ARRAY_SIZE(musb_resources));
499         if (ret) {
500                 dev_err(&pdev->dev, "failed to add resources\n");
501                 goto err3;
502         }
503 
504         ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
505         if (ret) {
506                 dev_err(&pdev->dev, "failed to add platform_data\n");
507                 goto err3;
508         }
509 
510         ret = platform_device_add(musb);
511         if (ret) {
512                 dev_err(&pdev->dev, "failed to register musb device\n");
513                 goto err3;
514         }
515 
516         return 0;
517 
518 err3:
519         usb_phy_generic_unregister(glue->phy);
520 
521 err2:
522         platform_device_put(musb);
523 
524 err1:
525         kfree(glue);
526 
527 err0:
528         return ret;
529 }
530 
531 static int bfin_remove(struct platform_device *pdev)
532 {
533         struct bfin_glue                *glue = platform_get_drvdata(pdev);
534 
535         platform_device_unregister(glue->musb);
536         usb_phy_generic_unregister(glue->phy);
537         kfree(glue);
538 
539         return 0;
540 }
541 
542 #ifdef CONFIG_PM
543 static int bfin_suspend(struct device *dev)
544 {
545         struct bfin_glue        *glue = dev_get_drvdata(dev);
546         struct musb             *musb = glue_to_musb(glue);
547 
548         if (is_host_active(musb))
549                 /*
550                  * During hibernate gpio_vrsel will change from high to low
551                  * low which will generate wakeup event resume the system
552                  * immediately.  Set it to 0 before hibernate to avoid this
553                  * wakeup event.
554                  */
555                 gpio_set_value(musb->config->gpio_vrsel, 0);
556 
557         return 0;
558 }
559 
560 static int bfin_resume(struct device *dev)
561 {
562         struct bfin_glue        *glue = dev_get_drvdata(dev);
563         struct musb             *musb = glue_to_musb(glue);
564 
565         bfin_musb_reg_init(musb);
566 
567         return 0;
568 }
569 #endif
570 
571 static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);
572 
573 static struct platform_driver bfin_driver = {
574         .probe          = bfin_probe,
575         .remove         = __exit_p(bfin_remove),
576         .driver         = {
577                 .name   = "musb-blackfin",
578                 .pm     = &bfin_pm_ops,
579         },
580 };
581 
582 MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
583 MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
584 MODULE_LICENSE("GPL v2");
585 module_platform_driver(bfin_driver);
586 

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