Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/usb/musb/am35x.c

  1 /*
  2  * Texas Instruments AM35x "glue layer"
  3  *
  4  * Copyright (c) 2010, by Texas Instruments
  5  *
  6  * Based on the DA8xx "glue layer" code.
  7  * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
  8  *
  9  * This file is part of the Inventra Controller Driver for Linux.
 10  *
 11  * The Inventra Controller Driver for Linux is free software; you
 12  * can redistribute it and/or modify it under the terms of the GNU
 13  * General Public License version 2 as published by the Free Software
 14  * Foundation.
 15  *
 16  * The Inventra Controller Driver for Linux is distributed in
 17  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
 18  * without even the implied warranty of MERCHANTABILITY or
 19  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 20  * License for more details.
 21  *
 22  * You should have received a copy of the GNU General Public License
 23  * along with The Inventra Controller Driver for Linux ; if not,
 24  * write to the Free Software Foundation, Inc., 59 Temple Place,
 25  * Suite 330, Boston, MA  02111-1307  USA
 26  *
 27  */
 28 
 29 #include <linux/module.h>
 30 #include <linux/clk.h>
 31 #include <linux/err.h>
 32 #include <linux/io.h>
 33 #include <linux/platform_device.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/usb/usb_phy_generic.h>
 36 #include <linux/platform_data/usb-omap.h>
 37 
 38 #include "musb_core.h"
 39 
 40 /*
 41  * AM35x specific definitions
 42  */
 43 /* USB 2.0 OTG module registers */
 44 #define USB_REVISION_REG        0x00
 45 #define USB_CTRL_REG            0x04
 46 #define USB_STAT_REG            0x08
 47 #define USB_EMULATION_REG       0x0c
 48 /* 0x10 Reserved */
 49 #define USB_AUTOREQ_REG         0x14
 50 #define USB_SRP_FIX_TIME_REG    0x18
 51 #define USB_TEARDOWN_REG        0x1c
 52 #define EP_INTR_SRC_REG         0x20
 53 #define EP_INTR_SRC_SET_REG     0x24
 54 #define EP_INTR_SRC_CLEAR_REG   0x28
 55 #define EP_INTR_MASK_REG        0x2c
 56 #define EP_INTR_MASK_SET_REG    0x30
 57 #define EP_INTR_MASK_CLEAR_REG  0x34
 58 #define EP_INTR_SRC_MASKED_REG  0x38
 59 #define CORE_INTR_SRC_REG       0x40
 60 #define CORE_INTR_SRC_SET_REG   0x44
 61 #define CORE_INTR_SRC_CLEAR_REG 0x48
 62 #define CORE_INTR_MASK_REG      0x4c
 63 #define CORE_INTR_MASK_SET_REG  0x50
 64 #define CORE_INTR_MASK_CLEAR_REG 0x54
 65 #define CORE_INTR_SRC_MASKED_REG 0x58
 66 /* 0x5c Reserved */
 67 #define USB_END_OF_INTR_REG     0x60
 68 
 69 /* Control register bits */
 70 #define AM35X_SOFT_RESET_MASK   1
 71 
 72 /* USB interrupt register bits */
 73 #define AM35X_INTR_USB_SHIFT    16
 74 #define AM35X_INTR_USB_MASK     (0x1ff << AM35X_INTR_USB_SHIFT)
 75 #define AM35X_INTR_DRVVBUS      0x100
 76 #define AM35X_INTR_RX_SHIFT     16
 77 #define AM35X_INTR_TX_SHIFT     0
 78 #define AM35X_TX_EP_MASK        0xffff          /* EP0 + 15 Tx EPs */
 79 #define AM35X_RX_EP_MASK        0xfffe          /* 15 Rx EPs */
 80 #define AM35X_TX_INTR_MASK      (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
 81 #define AM35X_RX_INTR_MASK      (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
 82 
 83 #define USB_MENTOR_CORE_OFFSET  0x400
 84 
 85 struct am35x_glue {
 86         struct device           *dev;
 87         struct platform_device  *musb;
 88         struct platform_device  *phy;
 89         struct clk              *phy_clk;
 90         struct clk              *clk;
 91 };
 92 
 93 /*
 94  * am35x_musb_enable - enable interrupts
 95  */
 96 static void am35x_musb_enable(struct musb *musb)
 97 {
 98         void __iomem *reg_base = musb->ctrl_base;
 99         u32 epmask;
100 
101         /* Workaround: setup IRQs through both register sets. */
102         epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
103                ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
104 
105         musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
106         musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
107 
108         /* Force the DRVVBUS IRQ so we can start polling for ID change. */
109         musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
110                         AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
111 }
112 
113 /*
114  * am35x_musb_disable - disable HDRC and flush interrupts
115  */
116 static void am35x_musb_disable(struct musb *musb)
117 {
118         void __iomem *reg_base = musb->ctrl_base;
119 
120         musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
121         musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
122                          AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
123         musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
124         musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
125 }
126 
127 #define portstate(stmt)         stmt
128 
129 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
130 {
131         WARN_ON(is_on && is_peripheral_active(musb));
132 }
133 
134 #define POLL_SECONDS    2
135 
136 static struct timer_list otg_workaround;
137 
138 static void otg_timer(unsigned long _musb)
139 {
140         struct musb             *musb = (void *)_musb;
141         void __iomem            *mregs = musb->mregs;
142         u8                      devctl;
143         unsigned long           flags;
144 
145         /*
146          * We poll because AM35x's won't expose several OTG-critical
147          * status change events (from the transceiver) otherwise.
148          */
149         devctl = musb_readb(mregs, MUSB_DEVCTL);
150         dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
151                 usb_otg_state_string(musb->xceiv->state));
152 
153         spin_lock_irqsave(&musb->lock, flags);
154         switch (musb->xceiv->state) {
155         case OTG_STATE_A_WAIT_BCON:
156                 devctl &= ~MUSB_DEVCTL_SESSION;
157                 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
158 
159                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
160                 if (devctl & MUSB_DEVCTL_BDEVICE) {
161                         musb->xceiv->state = OTG_STATE_B_IDLE;
162                         MUSB_DEV_MODE(musb);
163                 } else {
164                         musb->xceiv->state = OTG_STATE_A_IDLE;
165                         MUSB_HST_MODE(musb);
166                 }
167                 break;
168         case OTG_STATE_A_WAIT_VFALL:
169                 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
170                 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
171                             MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
172                 break;
173         case OTG_STATE_B_IDLE:
174                 devctl = musb_readb(mregs, MUSB_DEVCTL);
175                 if (devctl & MUSB_DEVCTL_BDEVICE)
176                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
177                 else
178                         musb->xceiv->state = OTG_STATE_A_IDLE;
179                 break;
180         default:
181                 break;
182         }
183         spin_unlock_irqrestore(&musb->lock, flags);
184 }
185 
186 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
187 {
188         static unsigned long last_timer;
189 
190         if (timeout == 0)
191                 timeout = jiffies + msecs_to_jiffies(3);
192 
193         /* Never idle if active, or when VBUS timeout is not set as host */
194         if (musb->is_active || (musb->a_wait_bcon == 0 &&
195                                 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
196                 dev_dbg(musb->controller, "%s active, deleting timer\n",
197                         usb_otg_state_string(musb->xceiv->state));
198                 del_timer(&otg_workaround);
199                 last_timer = jiffies;
200                 return;
201         }
202 
203         if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
204                 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
205                 return;
206         }
207         last_timer = timeout;
208 
209         dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
210                 usb_otg_state_string(musb->xceiv->state),
211                 jiffies_to_msecs(timeout - jiffies));
212         mod_timer(&otg_workaround, timeout);
213 }
214 
215 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
216 {
217         struct musb  *musb = hci;
218         void __iomem *reg_base = musb->ctrl_base;
219         struct device *dev = musb->controller;
220         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
221         struct omap_musb_board_data *data = plat->board_data;
222         struct usb_otg *otg = musb->xceiv->otg;
223         unsigned long flags;
224         irqreturn_t ret = IRQ_NONE;
225         u32 epintr, usbintr;
226 
227         spin_lock_irqsave(&musb->lock, flags);
228 
229         /* Get endpoint interrupts */
230         epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
231 
232         if (epintr) {
233                 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
234 
235                 musb->int_rx =
236                         (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
237                 musb->int_tx =
238                         (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
239         }
240 
241         /* Get usb core interrupts */
242         usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
243         if (!usbintr && !epintr)
244                 goto eoi;
245 
246         if (usbintr) {
247                 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
248 
249                 musb->int_usb =
250                         (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
251         }
252         /*
253          * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
254          * AM35x's missing ID change IRQ.  We need an ID change IRQ to
255          * switch appropriately between halves of the OTG state machine.
256          * Managing DEVCTL.SESSION per Mentor docs requires that we know its
257          * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
258          * Also, DRVVBUS pulses for SRP (but not at 5V) ...
259          */
260         if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
261                 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
262                 void __iomem *mregs = musb->mregs;
263                 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
264                 int err;
265 
266                 err = musb->int_usb & MUSB_INTR_VBUSERROR;
267                 if (err) {
268                         /*
269                          * The Mentor core doesn't debounce VBUS as needed
270                          * to cope with device connect current spikes. This
271                          * means it's not uncommon for bus-powered devices
272                          * to get VBUS errors during enumeration.
273                          *
274                          * This is a workaround, but newer RTL from Mentor
275                          * seems to allow a better one: "re"-starting sessions
276                          * without waiting for VBUS to stop registering in
277                          * devctl.
278                          */
279                         musb->int_usb &= ~MUSB_INTR_VBUSERROR;
280                         musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
281                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
282                         WARNING("VBUS error workaround (delay coming)\n");
283                 } else if (drvvbus) {
284                         MUSB_HST_MODE(musb);
285                         otg->default_a = 1;
286                         musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
287                         portstate(musb->port1_status |= USB_PORT_STAT_POWER);
288                         del_timer(&otg_workaround);
289                 } else {
290                         musb->is_active = 0;
291                         MUSB_DEV_MODE(musb);
292                         otg->default_a = 0;
293                         musb->xceiv->state = OTG_STATE_B_IDLE;
294                         portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
295                 }
296 
297                 /* NOTE: this must complete power-on within 100 ms. */
298                 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
299                                 drvvbus ? "on" : "off",
300                                 usb_otg_state_string(musb->xceiv->state),
301                                 err ? " ERROR" : "",
302                                 devctl);
303                 ret = IRQ_HANDLED;
304         }
305 
306         /* Drop spurious RX and TX if device is disconnected */
307         if (musb->int_usb & MUSB_INTR_DISCONNECT) {
308                 musb->int_tx = 0;
309                 musb->int_rx = 0;
310         }
311 
312         if (musb->int_tx || musb->int_rx || musb->int_usb)
313                 ret |= musb_interrupt(musb);
314 
315 eoi:
316         /* EOI needs to be written for the IRQ to be re-asserted. */
317         if (ret == IRQ_HANDLED || epintr || usbintr) {
318                 /* clear level interrupt */
319                 if (data->clear_irq)
320                         data->clear_irq();
321                 /* write EOI */
322                 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
323         }
324 
325         /* Poll for ID change */
326         if (musb->xceiv->state == OTG_STATE_B_IDLE)
327                 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
328 
329         spin_unlock_irqrestore(&musb->lock, flags);
330 
331         return ret;
332 }
333 
334 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
335 {
336         struct device *dev = musb->controller;
337         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
338         struct omap_musb_board_data *data = plat->board_data;
339         int     retval = 0;
340 
341         if (data->set_mode)
342                 data->set_mode(musb_mode);
343         else
344                 retval = -EIO;
345 
346         return retval;
347 }
348 
349 static int am35x_musb_init(struct musb *musb)
350 {
351         struct device *dev = musb->controller;
352         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
353         struct omap_musb_board_data *data = plat->board_data;
354         void __iomem *reg_base = musb->ctrl_base;
355         u32 rev;
356 
357         musb->mregs += USB_MENTOR_CORE_OFFSET;
358 
359         /* Returns zero if e.g. not clocked */
360         rev = musb_readl(reg_base, USB_REVISION_REG);
361         if (!rev)
362                 return -ENODEV;
363 
364         musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
365         if (IS_ERR_OR_NULL(musb->xceiv))
366                 return -EPROBE_DEFER;
367 
368         setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
369 
370         /* Reset the musb */
371         if (data->reset)
372                 data->reset();
373 
374         /* Reset the controller */
375         musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
376 
377         /* Start the on-chip PHY and its PLL. */
378         if (data->set_phy_power)
379                 data->set_phy_power(1);
380 
381         msleep(5);
382 
383         musb->isr = am35x_musb_interrupt;
384 
385         /* clear level interrupt */
386         if (data->clear_irq)
387                 data->clear_irq();
388 
389         return 0;
390 }
391 
392 static int am35x_musb_exit(struct musb *musb)
393 {
394         struct device *dev = musb->controller;
395         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
396         struct omap_musb_board_data *data = plat->board_data;
397 
398         del_timer_sync(&otg_workaround);
399 
400         /* Shutdown the on-chip PHY and its PLL. */
401         if (data->set_phy_power)
402                 data->set_phy_power(0);
403 
404         usb_put_phy(musb->xceiv);
405 
406         return 0;
407 }
408 
409 /* AM35x supports only 32bit read operation */
410 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
411 {
412         void __iomem *fifo = hw_ep->fifo;
413         u32             val;
414         int             i;
415 
416         /* Read for 32bit-aligned destination address */
417         if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
418                 readsl(fifo, dst, len >> 2);
419                 dst += len & ~0x03;
420                 len &= 0x03;
421         }
422         /*
423          * Now read the remaining 1 to 3 byte or complete length if
424          * unaligned address.
425          */
426         if (len > 4) {
427                 for (i = 0; i < (len >> 2); i++) {
428                         *(u32 *) dst = musb_readl(fifo, 0);
429                         dst += 4;
430                 }
431                 len &= 0x03;
432         }
433         if (len > 0) {
434                 val = musb_readl(fifo, 0);
435                 memcpy(dst, &val, len);
436         }
437 }
438 
439 static const struct musb_platform_ops am35x_ops = {
440         .init           = am35x_musb_init,
441         .exit           = am35x_musb_exit,
442 
443         .enable         = am35x_musb_enable,
444         .disable        = am35x_musb_disable,
445 
446         .set_mode       = am35x_musb_set_mode,
447         .try_idle       = am35x_musb_try_idle,
448 
449         .set_vbus       = am35x_musb_set_vbus,
450 };
451 
452 static const struct platform_device_info am35x_dev_info = {
453         .name           = "musb-hdrc",
454         .id             = PLATFORM_DEVID_AUTO,
455         .dma_mask       = DMA_BIT_MASK(32),
456 };
457 
458 static int am35x_probe(struct platform_device *pdev)
459 {
460         struct musb_hdrc_platform_data  *pdata = dev_get_platdata(&pdev->dev);
461         struct platform_device          *musb;
462         struct am35x_glue               *glue;
463         struct platform_device_info     pinfo;
464         struct clk                      *phy_clk;
465         struct clk                      *clk;
466 
467         int                             ret = -ENOMEM;
468 
469         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
470         if (!glue) {
471                 dev_err(&pdev->dev, "failed to allocate glue context\n");
472                 goto err0;
473         }
474 
475         phy_clk = clk_get(&pdev->dev, "fck");
476         if (IS_ERR(phy_clk)) {
477                 dev_err(&pdev->dev, "failed to get PHY clock\n");
478                 ret = PTR_ERR(phy_clk);
479                 goto err3;
480         }
481 
482         clk = clk_get(&pdev->dev, "ick");
483         if (IS_ERR(clk)) {
484                 dev_err(&pdev->dev, "failed to get clock\n");
485                 ret = PTR_ERR(clk);
486                 goto err4;
487         }
488 
489         ret = clk_enable(phy_clk);
490         if (ret) {
491                 dev_err(&pdev->dev, "failed to enable PHY clock\n");
492                 goto err5;
493         }
494 
495         ret = clk_enable(clk);
496         if (ret) {
497                 dev_err(&pdev->dev, "failed to enable clock\n");
498                 goto err6;
499         }
500 
501         glue->dev                       = &pdev->dev;
502         glue->phy_clk                   = phy_clk;
503         glue->clk                       = clk;
504 
505         pdata->platform_ops             = &am35x_ops;
506 
507         glue->phy = usb_phy_generic_register();
508         if (IS_ERR(glue->phy))
509                 goto err7;
510         platform_set_drvdata(pdev, glue);
511 
512         pinfo = am35x_dev_info;
513         pinfo.parent = &pdev->dev;
514         pinfo.res = pdev->resource;
515         pinfo.num_res = pdev->num_resources;
516         pinfo.data = pdata;
517         pinfo.size_data = sizeof(*pdata);
518 
519         glue->musb = musb = platform_device_register_full(&pinfo);
520         if (IS_ERR(musb)) {
521                 ret = PTR_ERR(musb);
522                 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
523                 goto err8;
524         }
525 
526         return 0;
527 
528 err8:
529         usb_phy_generic_unregister(glue->phy);
530 
531 err7:
532         clk_disable(clk);
533 
534 err6:
535         clk_disable(phy_clk);
536 
537 err5:
538         clk_put(clk);
539 
540 err4:
541         clk_put(phy_clk);
542 
543 err3:
544         kfree(glue);
545 
546 err0:
547         return ret;
548 }
549 
550 static int am35x_remove(struct platform_device *pdev)
551 {
552         struct am35x_glue       *glue = platform_get_drvdata(pdev);
553 
554         platform_device_unregister(glue->musb);
555         usb_phy_generic_unregister(glue->phy);
556         clk_disable(glue->clk);
557         clk_disable(glue->phy_clk);
558         clk_put(glue->clk);
559         clk_put(glue->phy_clk);
560         kfree(glue);
561 
562         return 0;
563 }
564 
565 #ifdef CONFIG_PM
566 static int am35x_suspend(struct device *dev)
567 {
568         struct am35x_glue       *glue = dev_get_drvdata(dev);
569         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
570         struct omap_musb_board_data *data = plat->board_data;
571 
572         /* Shutdown the on-chip PHY and its PLL. */
573         if (data->set_phy_power)
574                 data->set_phy_power(0);
575 
576         clk_disable(glue->phy_clk);
577         clk_disable(glue->clk);
578 
579         return 0;
580 }
581 
582 static int am35x_resume(struct device *dev)
583 {
584         struct am35x_glue       *glue = dev_get_drvdata(dev);
585         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
586         struct omap_musb_board_data *data = plat->board_data;
587         int                     ret;
588 
589         /* Start the on-chip PHY and its PLL. */
590         if (data->set_phy_power)
591                 data->set_phy_power(1);
592 
593         ret = clk_enable(glue->phy_clk);
594         if (ret) {
595                 dev_err(dev, "failed to enable PHY clock\n");
596                 return ret;
597         }
598 
599         ret = clk_enable(glue->clk);
600         if (ret) {
601                 dev_err(dev, "failed to enable clock\n");
602                 return ret;
603         }
604 
605         return 0;
606 }
607 #endif
608 
609 static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume);
610 
611 static struct platform_driver am35x_driver = {
612         .probe          = am35x_probe,
613         .remove         = am35x_remove,
614         .driver         = {
615                 .name   = "musb-am35x",
616                 .pm     = &am35x_pm_ops,
617         },
618 };
619 
620 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
621 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
622 MODULE_LICENSE("GPL v2");
623 module_platform_driver(am35x_driver);
624 

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