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Linux/drivers/usb/host/xhci-pci.c

  1 /*
  2  * xHCI host controller driver PCI Bus Glue.
  3  *
  4  * Copyright (C) 2008 Intel Corp.
  5  *
  6  * Author: Sarah Sharp
  7  * Some code borrowed from the Linux EHCI driver.
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  *
 13  * This program is distributed in the hope that it will be useful, but
 14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 16  * for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program; if not, write to the Free Software Foundation,
 20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 21  */
 22 
 23 #include <linux/pci.h>
 24 #include <linux/slab.h>
 25 #include <linux/module.h>
 26 #include <linux/acpi.h>
 27 
 28 #include "xhci.h"
 29 #include "xhci-trace.h"
 30 
 31 #define SSIC_PORT_NUM           2
 32 #define SSIC_PORT_CFG2          0x880c
 33 #define SSIC_PORT_CFG2_OFFSET   0x30
 34 #define PROG_DONE               (1 << 30)
 35 #define SSIC_PORT_UNUSED        (1 << 31)
 36 
 37 /* Device for a quirk */
 38 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
 39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
 40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
 41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
 42 
 43 #define PCI_VENDOR_ID_ETRON             0x1b6f
 44 #define PCI_DEVICE_ID_EJ168             0x7023
 45 
 46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
 47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
 48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
 49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
 50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
 51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
 52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
 53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
 54 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
 55 
 56 static const char hcd_name[] = "xhci_hcd";
 57 
 58 static struct hc_driver __read_mostly xhci_pci_hc_driver;
 59 
 60 static int xhci_pci_setup(struct usb_hcd *hcd);
 61 
 62 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
 63         .reset = xhci_pci_setup,
 64 };
 65 
 66 /* called after powerup, by probe or system-pm "wakeup" */
 67 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
 68 {
 69         /*
 70          * TODO: Implement finding debug ports later.
 71          * TODO: see if there are any quirks that need to be added to handle
 72          * new extended capabilities.
 73          */
 74 
 75         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
 76         if (!pci_set_mwi(pdev))
 77                 xhci_dbg(xhci, "MWI active\n");
 78 
 79         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
 80         return 0;
 81 }
 82 
 83 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 84 {
 85         struct pci_dev          *pdev = to_pci_dev(dev);
 86 
 87         /* Look for vendor-specific quirks */
 88         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 89                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 90                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 91                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 92                                 pdev->revision == 0x0) {
 93                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 94                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 95                                 "QUIRK: Fresco Logic xHC needs configure"
 96                                 " endpoint cmd after reset endpoint");
 97                 }
 98                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 99                                 pdev->revision == 0x4) {
100                         xhci->quirks |= XHCI_SLOW_SUSPEND;
101                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
102                                 "QUIRK: Fresco Logic xHC revision %u"
103                                 "must be suspended extra slowly",
104                                 pdev->revision);
105                 }
106                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
107                         xhci->quirks |= XHCI_BROKEN_STREAMS;
108                 /* Fresco Logic confirms: all revisions of this chip do not
109                  * support MSI, even though some of them claim to in their PCI
110                  * capabilities.
111                  */
112                 xhci->quirks |= XHCI_BROKEN_MSI;
113                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
114                                 "QUIRK: Fresco Logic revision %u "
115                                 "has broken MSI implementation",
116                                 pdev->revision);
117                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
118         }
119 
120         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
121                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
122                 xhci->quirks |= XHCI_BROKEN_STREAMS;
123 
124         if (pdev->vendor == PCI_VENDOR_ID_NEC)
125                 xhci->quirks |= XHCI_NEC_HOST;
126 
127         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
128                 xhci->quirks |= XHCI_AMD_0x96_HOST;
129 
130         /* AMD PLL quirk */
131         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
132                 xhci->quirks |= XHCI_AMD_PLL_FIX;
133 
134         if (pdev->vendor == PCI_VENDOR_ID_AMD)
135                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
136 
137         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
138                 xhci->quirks |= XHCI_LPM_SUPPORT;
139                 xhci->quirks |= XHCI_INTEL_HOST;
140                 xhci->quirks |= XHCI_AVOID_BEI;
141         }
142         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
143                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
144                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
145                 xhci->limit_active_eps = 64;
146                 xhci->quirks |= XHCI_SW_BW_CHECKING;
147                 /*
148                  * PPT desktop boards DH77EB and DH77DF will power back on after
149                  * a few seconds of being shutdown.  The fix for this is to
150                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
151                  * DMI information to find those particular boards (since each
152                  * vendor will change the board name), so we have to key off all
153                  * PPT chipsets.
154                  */
155                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
156         }
157         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
158                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
159                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
160                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
161                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
162         }
163         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
164                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
165                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
166                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
167                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
168                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI)) {
169                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
170         }
171         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
172                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
173                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
174         }
175         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
176             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
177              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
178                 xhci->quirks |= XHCI_MISSING_CAS;
179 
180         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
181                         pdev->device == PCI_DEVICE_ID_EJ168) {
182                 xhci->quirks |= XHCI_RESET_ON_RESUME;
183                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
184                 xhci->quirks |= XHCI_BROKEN_STREAMS;
185         }
186         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
187                         pdev->device == 0x0015)
188                 xhci->quirks |= XHCI_RESET_ON_RESUME;
189         if (pdev->vendor == PCI_VENDOR_ID_VIA)
190                 xhci->quirks |= XHCI_RESET_ON_RESUME;
191 
192         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
193         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
194                         pdev->device == 0x3432)
195                 xhci->quirks |= XHCI_BROKEN_STREAMS;
196 
197         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
198                         pdev->device == 0x1042)
199                 xhci->quirks |= XHCI_BROKEN_STREAMS;
200 
201         if (xhci->quirks & XHCI_RESET_ON_RESUME)
202                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
203                                 "QUIRK: Resetting on resume");
204 }
205 
206 #ifdef CONFIG_ACPI
207 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
208 {
209         static const u8 intel_dsm_uuid[] = {
210                 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
211                 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
212         };
213         union acpi_object *obj;
214 
215         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
216                                 NULL);
217         ACPI_FREE(obj);
218 }
219 #else
220 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
221 #endif /* CONFIG_ACPI */
222 
223 /* called during probe() after chip reset completes */
224 static int xhci_pci_setup(struct usb_hcd *hcd)
225 {
226         struct xhci_hcd         *xhci;
227         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
228         int                     retval;
229 
230         xhci = hcd_to_xhci(hcd);
231         if (!xhci->sbrn)
232                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
233 
234         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
235         if (retval)
236                 return retval;
237 
238         if (!usb_hcd_is_primary_hcd(hcd))
239                 return 0;
240 
241         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
242 
243         /* Find any debug ports */
244         retval = xhci_pci_reinit(xhci, pdev);
245         if (!retval)
246                 return retval;
247 
248         return retval;
249 }
250 
251 /*
252  * We need to register our own PCI probe function (instead of the USB core's
253  * function) in order to create a second roothub under xHCI.
254  */
255 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
256 {
257         int retval;
258         struct xhci_hcd *xhci;
259         struct hc_driver *driver;
260         struct usb_hcd *hcd;
261 
262         driver = (struct hc_driver *)id->driver_data;
263 
264         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
265         pm_runtime_get_noresume(&dev->dev);
266 
267         /* Register the USB 2.0 roothub.
268          * FIXME: USB core must know to register the USB 2.0 roothub first.
269          * This is sort of silly, because we could just set the HCD driver flags
270          * to say USB 2.0, but I'm not sure what the implications would be in
271          * the other parts of the HCD code.
272          */
273         retval = usb_hcd_pci_probe(dev, id);
274 
275         if (retval)
276                 goto put_runtime_pm;
277 
278         /* USB 2.0 roothub is stored in the PCI device now. */
279         hcd = dev_get_drvdata(&dev->dev);
280         xhci = hcd_to_xhci(hcd);
281         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
282                                 pci_name(dev), hcd);
283         if (!xhci->shared_hcd) {
284                 retval = -ENOMEM;
285                 goto dealloc_usb2_hcd;
286         }
287 
288         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
289                         IRQF_SHARED);
290         if (retval)
291                 goto put_usb3_hcd;
292         /* Roothub already marked as USB 3.0 speed */
293 
294         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
295                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
296                 xhci->shared_hcd->can_do_streams = 1;
297 
298         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
299                 xhci_pme_acpi_rtd3_enable(dev);
300 
301         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
302         pm_runtime_put_noidle(&dev->dev);
303 
304         return 0;
305 
306 put_usb3_hcd:
307         usb_put_hcd(xhci->shared_hcd);
308 dealloc_usb2_hcd:
309         usb_hcd_pci_remove(dev);
310 put_runtime_pm:
311         pm_runtime_put_noidle(&dev->dev);
312         return retval;
313 }
314 
315 static void xhci_pci_remove(struct pci_dev *dev)
316 {
317         struct xhci_hcd *xhci;
318 
319         xhci = hcd_to_xhci(pci_get_drvdata(dev));
320         xhci->xhc_state |= XHCI_STATE_REMOVING;
321         if (xhci->shared_hcd) {
322                 usb_remove_hcd(xhci->shared_hcd);
323                 usb_put_hcd(xhci->shared_hcd);
324         }
325 
326         /* Workaround for spurious wakeups at shutdown with HSW */
327         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
328                 pci_set_power_state(dev, PCI_D3hot);
329 
330         usb_hcd_pci_remove(dev);
331 }
332 
333 #ifdef CONFIG_PM
334 /*
335  * In some Intel xHCI controllers, in order to get D3 working,
336  * through a vendor specific SSIC CONFIG register at offset 0x883c,
337  * SSIC PORT need to be marked as "unused" before putting xHCI
338  * into D3. After D3 exit, the SSIC port need to be marked as "used".
339  * Without this change, xHCI might not enter D3 state.
340  */
341 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
342 {
343         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
344         u32 val;
345         void __iomem *reg;
346         int i;
347 
348         for (i = 0; i < SSIC_PORT_NUM; i++) {
349                 reg = (void __iomem *) xhci->cap_regs +
350                                 SSIC_PORT_CFG2 +
351                                 i * SSIC_PORT_CFG2_OFFSET;
352 
353                 /* Notify SSIC that SSIC profile programming is not done. */
354                 val = readl(reg) & ~PROG_DONE;
355                 writel(val, reg);
356 
357                 /* Mark SSIC port as unused(suspend) or used(resume) */
358                 val = readl(reg);
359                 if (suspend)
360                         val |= SSIC_PORT_UNUSED;
361                 else
362                         val &= ~SSIC_PORT_UNUSED;
363                 writel(val, reg);
364 
365                 /* Notify SSIC that SSIC profile programming is done */
366                 val = readl(reg) | PROG_DONE;
367                 writel(val, reg);
368                 readl(reg);
369         }
370 }
371 
372 /*
373  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
374  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
375  */
376 static void xhci_pme_quirk(struct usb_hcd *hcd)
377 {
378         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
379         void __iomem *reg;
380         u32 val;
381 
382         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
383         val = readl(reg);
384         writel(val | BIT(28), reg);
385         readl(reg);
386 }
387 
388 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
389 {
390         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
391         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
392         int                     ret;
393 
394         /*
395          * Systems with the TI redriver that loses port status change events
396          * need to have the registers polled during D3, so avoid D3cold.
397          */
398         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
399                 pci_d3cold_disable(pdev);
400 
401         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
402                 xhci_pme_quirk(hcd);
403 
404         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
405                 xhci_ssic_port_unused_quirk(hcd, true);
406 
407         ret = xhci_suspend(xhci, do_wakeup);
408         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
409                 xhci_ssic_port_unused_quirk(hcd, false);
410 
411         return ret;
412 }
413 
414 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
415 {
416         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
417         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
418         int                     retval = 0;
419 
420         /* The BIOS on systems with the Intel Panther Point chipset may or may
421          * not support xHCI natively.  That means that during system resume, it
422          * may switch the ports back to EHCI so that users can use their
423          * keyboard to select a kernel from GRUB after resume from hibernate.
424          *
425          * The BIOS is supposed to remember whether the OS had xHCI ports
426          * enabled before resume, and switch the ports back to xHCI when the
427          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
428          * writers.
429          *
430          * Unconditionally switch the ports back to xHCI after a system resume.
431          * It should not matter whether the EHCI or xHCI controller is
432          * resumed first. It's enough to do the switchover in xHCI because
433          * USB core won't notice anything as the hub driver doesn't start
434          * running again until after all the devices (including both EHCI and
435          * xHCI host controllers) have been resumed.
436          */
437 
438         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
439                 usb_enable_intel_xhci_ports(pdev);
440 
441         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
442                 xhci_ssic_port_unused_quirk(hcd, false);
443 
444         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
445                 xhci_pme_quirk(hcd);
446 
447         retval = xhci_resume(xhci, hibernated);
448         return retval;
449 }
450 #endif /* CONFIG_PM */
451 
452 /*-------------------------------------------------------------------------*/
453 
454 /* PCI driver selection metadata; PCI hotplugging uses this */
455 static const struct pci_device_id pci_ids[] = { {
456         /* handle any USB 3.0 xHCI controller */
457         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
458         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
459         },
460         { /* end: all zeroes */ }
461 };
462 MODULE_DEVICE_TABLE(pci, pci_ids);
463 
464 /* pci driver glue; this is a "new style" PCI driver module */
465 static struct pci_driver xhci_pci_driver = {
466         .name =         (char *) hcd_name,
467         .id_table =     pci_ids,
468 
469         .probe =        xhci_pci_probe,
470         .remove =       xhci_pci_remove,
471         /* suspend and resume implemented later */
472 
473         .shutdown =     usb_hcd_pci_shutdown,
474 #ifdef CONFIG_PM
475         .driver = {
476                 .pm = &usb_hcd_pci_pm_ops
477         },
478 #endif
479 };
480 
481 static int __init xhci_pci_init(void)
482 {
483         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
484 #ifdef CONFIG_PM
485         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
486         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
487 #endif
488         return pci_register_driver(&xhci_pci_driver);
489 }
490 module_init(xhci_pci_init);
491 
492 static void __exit xhci_pci_exit(void)
493 {
494         pci_unregister_driver(&xhci_pci_driver);
495 }
496 module_exit(xhci_pci_exit);
497 
498 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
499 MODULE_LICENSE("GPL");
500 

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