Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/usb/host/ehci-tegra.c

  1 /*
  2  * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
  3  *
  4  * Copyright (C) 2010 Google, Inc.
  5  * Copyright (C) 2009 - 2013 NVIDIA Corporation
  6  *
  7  * This program is free software; you can redistribute it and/or modify it
  8  * under the terms of the GNU General Public License as published by the
  9  * Free Software Foundation; either version 2 of the License, or (at your
 10  * option) any later version.
 11  *
 12  * This program is distributed in the hope that it will be useful, but WITHOUT
 13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 15  * more details.
 16  *
 17  */
 18 
 19 #include <linux/clk.h>
 20 #include <linux/dma-mapping.h>
 21 #include <linux/err.h>
 22 #include <linux/gpio.h>
 23 #include <linux/io.h>
 24 #include <linux/irq.h>
 25 #include <linux/module.h>
 26 #include <linux/of.h>
 27 #include <linux/of_device.h>
 28 #include <linux/of_gpio.h>
 29 #include <linux/platform_device.h>
 30 #include <linux/pm_runtime.h>
 31 #include <linux/reset.h>
 32 #include <linux/slab.h>
 33 #include <linux/usb/ehci_def.h>
 34 #include <linux/usb/tegra_usb_phy.h>
 35 #include <linux/usb.h>
 36 #include <linux/usb/hcd.h>
 37 #include <linux/usb/otg.h>
 38 
 39 #include "ehci.h"
 40 
 41 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
 42 
 43 #define TEGRA_USB_DMA_ALIGN 32
 44 
 45 #define DRIVER_DESC "Tegra EHCI driver"
 46 #define DRV_NAME "tegra-ehci"
 47 
 48 static struct hc_driver __read_mostly tegra_ehci_hc_driver;
 49 static bool usb1_reset_attempted;
 50 
 51 struct tegra_ehci_soc_config {
 52         bool has_hostpc;
 53 };
 54 
 55 struct tegra_ehci_hcd {
 56         struct tegra_usb_phy *phy;
 57         struct clk *clk;
 58         struct reset_control *rst;
 59         int port_resuming;
 60         bool needs_double_reset;
 61         enum tegra_usb_phy_port_speed port_speed;
 62 };
 63 
 64 /*
 65  * The 1st USB controller contains some UTMI pad registers that are global for
 66  * all the controllers on the chip. Those registers are also cleared when
 67  * reset is asserted to the 1st controller. This means that the 1st controller
 68  * can only be reset when no other controlled has finished probing. So we'll
 69  * reset the 1st controller before doing any other setup on any of the
 70  * controllers, and then never again.
 71  *
 72  * Since this is a PHY issue, the Tegra PHY driver should probably be doing
 73  * the resetting of the USB controllers. But to keep compatibility with old
 74  * device trees that don't have reset phandles in the PHYs, do it here.
 75  * Those old DTs will be vulnerable to total USB breakage if the 1st EHCI
 76  * device isn't the first one to finish probing, so warn them.
 77  */
 78 static int tegra_reset_usb_controller(struct platform_device *pdev)
 79 {
 80         struct device_node *phy_np;
 81         struct usb_hcd *hcd = platform_get_drvdata(pdev);
 82         struct tegra_ehci_hcd *tegra =
 83                 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
 84 
 85         phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
 86         if (!phy_np)
 87                 return -ENOENT;
 88 
 89         if (!usb1_reset_attempted) {
 90                 struct reset_control *usb1_reset;
 91 
 92                 usb1_reset = of_reset_control_get(phy_np, "usb");
 93                 if (IS_ERR(usb1_reset)) {
 94                         dev_warn(&pdev->dev,
 95                                  "can't get utmi-pads reset from the PHY\n");
 96                         dev_warn(&pdev->dev,
 97                                  "continuing, but please update your DT\n");
 98                 } else {
 99                         reset_control_assert(usb1_reset);
100                         udelay(1);
101                         reset_control_deassert(usb1_reset);
102                 }
103 
104                 reset_control_put(usb1_reset);
105                 usb1_reset_attempted = true;
106         }
107 
108         if (!of_property_read_bool(phy_np, "nvidia,has-utmi-pad-registers")) {
109                 reset_control_assert(tegra->rst);
110                 udelay(1);
111                 reset_control_deassert(tegra->rst);
112         }
113 
114         of_node_put(phy_np);
115 
116         return 0;
117 }
118 
119 static int tegra_ehci_internal_port_reset(
120         struct ehci_hcd *ehci,
121         u32 __iomem     *portsc_reg
122 )
123 {
124         u32             temp;
125         unsigned long   flags;
126         int             retval = 0;
127         int             i, tries;
128         u32             saved_usbintr;
129 
130         spin_lock_irqsave(&ehci->lock, flags);
131         saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
132         /* disable USB interrupt */
133         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
134         spin_unlock_irqrestore(&ehci->lock, flags);
135 
136         /*
137          * Here we have to do Port Reset at most twice for
138          * Port Enable bit to be set.
139          */
140         for (i = 0; i < 2; i++) {
141                 temp = ehci_readl(ehci, portsc_reg);
142                 temp |= PORT_RESET;
143                 ehci_writel(ehci, temp, portsc_reg);
144                 mdelay(10);
145                 temp &= ~PORT_RESET;
146                 ehci_writel(ehci, temp, portsc_reg);
147                 mdelay(1);
148                 tries = 100;
149                 do {
150                         mdelay(1);
151                         /*
152                          * Up to this point, Port Enable bit is
153                          * expected to be set after 2 ms waiting.
154                          * USB1 usually takes extra 45 ms, for safety,
155                          * we take 100 ms as timeout.
156                          */
157                         temp = ehci_readl(ehci, portsc_reg);
158                 } while (!(temp & PORT_PE) && tries--);
159                 if (temp & PORT_PE)
160                         break;
161         }
162         if (i == 2)
163                 retval = -ETIMEDOUT;
164 
165         /*
166          * Clear Connect Status Change bit if it's set.
167          * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
168          */
169         if (temp & PORT_CSC)
170                 ehci_writel(ehci, PORT_CSC, portsc_reg);
171 
172         /*
173          * Write to clear any interrupt status bits that might be set
174          * during port reset.
175          */
176         temp = ehci_readl(ehci, &ehci->regs->status);
177         ehci_writel(ehci, temp, &ehci->regs->status);
178 
179         /* restore original interrupt enable bits */
180         ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
181         return retval;
182 }
183 
184 static int tegra_ehci_hub_control(
185         struct usb_hcd  *hcd,
186         u16             typeReq,
187         u16             wValue,
188         u16             wIndex,
189         char            *buf,
190         u16             wLength
191 )
192 {
193         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
194         struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
195         u32 __iomem     *status_reg;
196         u32             temp;
197         unsigned long   flags;
198         int             retval = 0;
199 
200         status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
201 
202         spin_lock_irqsave(&ehci->lock, flags);
203 
204         if (typeReq == GetPortStatus) {
205                 temp = ehci_readl(ehci, status_reg);
206                 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
207                         /* Resume completed, re-enable disconnect detection */
208                         tegra->port_resuming = 0;
209                         tegra_usb_phy_postresume(hcd->usb_phy);
210                 }
211         }
212 
213         else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
214                 temp = ehci_readl(ehci, status_reg);
215                 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
216                         retval = -EPIPE;
217                         goto done;
218                 }
219 
220                 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
221                 temp |= PORT_WKDISC_E | PORT_WKOC_E;
222                 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
223 
224                 /*
225                  * If a transaction is in progress, there may be a delay in
226                  * suspending the port. Poll until the port is suspended.
227                  */
228                 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
229                                                 PORT_SUSPEND, 5000))
230                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
231 
232                 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
233                 goto done;
234         }
235 
236         /* For USB1 port we need to issue Port Reset twice internally */
237         if (tegra->needs_double_reset &&
238            (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
239                 spin_unlock_irqrestore(&ehci->lock, flags);
240                 return tegra_ehci_internal_port_reset(ehci, status_reg);
241         }
242 
243         /*
244          * Tegra host controller will time the resume operation to clear the bit
245          * when the port control state switches to HS or FS Idle. This behavior
246          * is different from EHCI where the host controller driver is required
247          * to set this bit to a zero after the resume duration is timed in the
248          * driver.
249          */
250         else if (typeReq == ClearPortFeature &&
251                                         wValue == USB_PORT_FEAT_SUSPEND) {
252                 temp = ehci_readl(ehci, status_reg);
253                 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
254                         retval = -EPIPE;
255                         goto done;
256                 }
257 
258                 if (!(temp & PORT_SUSPEND))
259                         goto done;
260 
261                 /* Disable disconnect detection during port resume */
262                 tegra_usb_phy_preresume(hcd->usb_phy);
263 
264                 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
265 
266                 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
267                 /* start resume signalling */
268                 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
269                 set_bit(wIndex-1, &ehci->resuming_ports);
270 
271                 spin_unlock_irqrestore(&ehci->lock, flags);
272                 msleep(20);
273                 spin_lock_irqsave(&ehci->lock, flags);
274 
275                 /* Poll until the controller clears RESUME and SUSPEND */
276                 if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
277                         pr_err("%s: timeout waiting for RESUME\n", __func__);
278                 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
279                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
280 
281                 ehci->reset_done[wIndex-1] = 0;
282                 clear_bit(wIndex-1, &ehci->resuming_ports);
283 
284                 tegra->port_resuming = 1;
285                 goto done;
286         }
287 
288         spin_unlock_irqrestore(&ehci->lock, flags);
289 
290         /* Handle the hub control events here */
291         return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
292 
293 done:
294         spin_unlock_irqrestore(&ehci->lock, flags);
295         return retval;
296 }
297 
298 struct dma_aligned_buffer {
299         void *kmalloc_ptr;
300         void *old_xfer_buffer;
301         u8 data[0];
302 };
303 
304 static void free_dma_aligned_buffer(struct urb *urb)
305 {
306         struct dma_aligned_buffer *temp;
307 
308         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
309                 return;
310 
311         temp = container_of(urb->transfer_buffer,
312                 struct dma_aligned_buffer, data);
313 
314         if (usb_urb_dir_in(urb))
315                 memcpy(temp->old_xfer_buffer, temp->data,
316                        urb->transfer_buffer_length);
317         urb->transfer_buffer = temp->old_xfer_buffer;
318         kfree(temp->kmalloc_ptr);
319 
320         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
321 }
322 
323 static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
324 {
325         struct dma_aligned_buffer *temp, *kmalloc_ptr;
326         size_t kmalloc_size;
327 
328         if (urb->num_sgs || urb->sg ||
329             urb->transfer_buffer_length == 0 ||
330             !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
331                 return 0;
332 
333         /* Allocate a buffer with enough padding for alignment */
334         kmalloc_size = urb->transfer_buffer_length +
335                 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
336 
337         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
338         if (!kmalloc_ptr)
339                 return -ENOMEM;
340 
341         /* Position our struct dma_aligned_buffer such that data is aligned */
342         temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
343         temp->kmalloc_ptr = kmalloc_ptr;
344         temp->old_xfer_buffer = urb->transfer_buffer;
345         if (usb_urb_dir_out(urb))
346                 memcpy(temp->data, urb->transfer_buffer,
347                        urb->transfer_buffer_length);
348         urb->transfer_buffer = temp->data;
349 
350         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
351 
352         return 0;
353 }
354 
355 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
356                                       gfp_t mem_flags)
357 {
358         int ret;
359 
360         ret = alloc_dma_aligned_buffer(urb, mem_flags);
361         if (ret)
362                 return ret;
363 
364         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
365         if (ret)
366                 free_dma_aligned_buffer(urb);
367 
368         return ret;
369 }
370 
371 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
372 {
373         usb_hcd_unmap_urb_for_dma(hcd, urb);
374         free_dma_aligned_buffer(urb);
375 }
376 
377 static const struct tegra_ehci_soc_config tegra30_soc_config = {
378         .has_hostpc = true,
379 };
380 
381 static const struct tegra_ehci_soc_config tegra20_soc_config = {
382         .has_hostpc = false,
383 };
384 
385 static const struct of_device_id tegra_ehci_of_match[] = {
386         { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
387         { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
388         { },
389 };
390 
391 static int tegra_ehci_probe(struct platform_device *pdev)
392 {
393         const struct of_device_id *match;
394         const struct tegra_ehci_soc_config *soc_config;
395         struct resource *res;
396         struct usb_hcd *hcd;
397         struct ehci_hcd *ehci;
398         struct tegra_ehci_hcd *tegra;
399         int err = 0;
400         int irq;
401         struct usb_phy *u_phy;
402 
403         match = of_match_device(tegra_ehci_of_match, &pdev->dev);
404         if (!match) {
405                 dev_err(&pdev->dev, "Error: No device match found\n");
406                 return -ENODEV;
407         }
408         soc_config = match->data;
409 
410         /* Right now device-tree probed devices don't get dma_mask set.
411          * Since shared usb code relies on it, set it here for now.
412          * Once we have dma capability bindings this can go away.
413          */
414         err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
415         if (err)
416                 return err;
417 
418         hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
419                                         dev_name(&pdev->dev));
420         if (!hcd) {
421                 dev_err(&pdev->dev, "Unable to create HCD\n");
422                 return -ENOMEM;
423         }
424         platform_set_drvdata(pdev, hcd);
425         ehci = hcd_to_ehci(hcd);
426         tegra = (struct tegra_ehci_hcd *)ehci->priv;
427 
428         hcd->has_tt = 1;
429 
430         tegra->clk = devm_clk_get(&pdev->dev, NULL);
431         if (IS_ERR(tegra->clk)) {
432                 dev_err(&pdev->dev, "Can't get ehci clock\n");
433                 err = PTR_ERR(tegra->clk);
434                 goto cleanup_hcd_create;
435         }
436 
437         tegra->rst = devm_reset_control_get(&pdev->dev, "usb");
438         if (IS_ERR(tegra->rst)) {
439                 dev_err(&pdev->dev, "Can't get ehci reset\n");
440                 err = PTR_ERR(tegra->rst);
441                 goto cleanup_hcd_create;
442         }
443 
444         err = clk_prepare_enable(tegra->clk);
445         if (err)
446                 goto cleanup_hcd_create;
447 
448         err = tegra_reset_usb_controller(pdev);
449         if (err)
450                 goto cleanup_clk_en;
451 
452         u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
453         if (IS_ERR(u_phy)) {
454                 err = PTR_ERR(u_phy);
455                 goto cleanup_clk_en;
456         }
457         hcd->usb_phy = u_phy;
458 
459         tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
460                 "nvidia,needs-double-reset");
461 
462         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
463         if (!res) {
464                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
465                 err = -ENXIO;
466                 goto cleanup_clk_en;
467         }
468         hcd->rsrc_start = res->start;
469         hcd->rsrc_len = resource_size(res);
470         hcd->regs = devm_ioremap_resource(&pdev->dev, res);
471         if (IS_ERR(hcd->regs)) {
472                 err = PTR_ERR(hcd->regs);
473                 goto cleanup_clk_en;
474         }
475         ehci->caps = hcd->regs + 0x100;
476         ehci->has_hostpc = soc_config->has_hostpc;
477 
478         err = usb_phy_init(hcd->usb_phy);
479         if (err) {
480                 dev_err(&pdev->dev, "Failed to initialize phy\n");
481                 goto cleanup_clk_en;
482         }
483 
484         u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
485                              GFP_KERNEL);
486         if (!u_phy->otg) {
487                 dev_err(&pdev->dev, "Failed to alloc memory for otg\n");
488                 err = -ENOMEM;
489                 goto cleanup_phy;
490         }
491         u_phy->otg->host = hcd_to_bus(hcd);
492 
493         err = usb_phy_set_suspend(hcd->usb_phy, 0);
494         if (err) {
495                 dev_err(&pdev->dev, "Failed to power on the phy\n");
496                 goto cleanup_phy;
497         }
498 
499         irq = platform_get_irq(pdev, 0);
500         if (!irq) {
501                 dev_err(&pdev->dev, "Failed to get IRQ\n");
502                 err = -ENODEV;
503                 goto cleanup_phy;
504         }
505 
506         otg_set_host(u_phy->otg, &hcd->self);
507 
508         err = usb_add_hcd(hcd, irq, IRQF_SHARED);
509         if (err) {
510                 dev_err(&pdev->dev, "Failed to add USB HCD\n");
511                 goto cleanup_otg_set_host;
512         }
513         device_wakeup_enable(hcd->self.controller);
514 
515         return err;
516 
517 cleanup_otg_set_host:
518         otg_set_host(u_phy->otg, NULL);
519 cleanup_phy:
520         usb_phy_shutdown(hcd->usb_phy);
521 cleanup_clk_en:
522         clk_disable_unprepare(tegra->clk);
523 cleanup_hcd_create:
524         usb_put_hcd(hcd);
525         return err;
526 }
527 
528 static int tegra_ehci_remove(struct platform_device *pdev)
529 {
530         struct usb_hcd *hcd = platform_get_drvdata(pdev);
531         struct tegra_ehci_hcd *tegra =
532                 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
533 
534         otg_set_host(hcd->usb_phy->otg, NULL);
535 
536         usb_phy_shutdown(hcd->usb_phy);
537         usb_remove_hcd(hcd);
538 
539         clk_disable_unprepare(tegra->clk);
540 
541         usb_put_hcd(hcd);
542 
543         return 0;
544 }
545 
546 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
547 {
548         struct usb_hcd *hcd = platform_get_drvdata(pdev);
549 
550         if (hcd->driver->shutdown)
551                 hcd->driver->shutdown(hcd);
552 }
553 
554 static struct platform_driver tegra_ehci_driver = {
555         .probe          = tegra_ehci_probe,
556         .remove         = tegra_ehci_remove,
557         .shutdown       = tegra_ehci_hcd_shutdown,
558         .driver         = {
559                 .name   = DRV_NAME,
560                 .of_match_table = tegra_ehci_of_match,
561         }
562 };
563 
564 static int tegra_ehci_reset(struct usb_hcd *hcd)
565 {
566         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
567         int retval;
568         int txfifothresh;
569 
570         retval = ehci_setup(hcd);
571         if (retval)
572                 return retval;
573 
574         /*
575          * We should really pull this value out of tegra_ehci_soc_config, but
576          * to avoid needing access to it, make use of the fact that Tegra20 is
577          * the only one so far that needs a value of 10, and Tegra20 is the
578          * only one which doesn't set has_hostpc.
579          */
580         txfifothresh = ehci->has_hostpc ? 0x10 : 10;
581         ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
582 
583         return 0;
584 }
585 
586 static const struct ehci_driver_overrides tegra_overrides __initconst = {
587         .extra_priv_size        = sizeof(struct tegra_ehci_hcd),
588         .reset                  = tegra_ehci_reset,
589 };
590 
591 static int __init ehci_tegra_init(void)
592 {
593         if (usb_disabled())
594                 return -ENODEV;
595 
596         pr_info(DRV_NAME ": " DRIVER_DESC "\n");
597 
598         ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
599 
600         /*
601          * The Tegra HW has some unusual quirks, which require Tegra-specific
602          * workarounds. We override certain hc_driver functions here to
603          * achieve that. We explicitly do not enhance ehci_driver_overrides to
604          * allow this more easily, since this is an unusual case, and we don't
605          * want to encourage others to override these functions by making it
606          * too easy.
607          */
608 
609         tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
610         tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
611         tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
612 
613         return platform_driver_register(&tegra_ehci_driver);
614 }
615 module_init(ehci_tegra_init);
616 
617 static void __exit ehci_tegra_cleanup(void)
618 {
619         platform_driver_unregister(&tegra_ehci_driver);
620 }
621 module_exit(ehci_tegra_cleanup);
622 
623 MODULE_DESCRIPTION(DRIVER_DESC);
624 MODULE_LICENSE("GPL");
625 MODULE_ALIAS("platform:" DRV_NAME);
626 MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);
627 

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