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Linux/drivers/usb/gadget/s3c-hsotg.c

  1 /**
  2  * linux/drivers/usb/gadget/s3c-hsotg.c
  3  *
  4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  5  *              http://www.samsung.com
  6  *
  7  * Copyright 2008 Openmoko, Inc.
  8  * Copyright 2008 Simtec Electronics
  9  *      Ben Dooks <ben@simtec.co.uk>
 10  *      http://armlinux.simtec.co.uk/
 11  *
 12  * S3C USB2.0 High-speed / OtG driver
 13  *
 14  * This program is free software; you can redistribute it and/or modify
 15  * it under the terms of the GNU General Public License version 2 as
 16  * published by the Free Software Foundation.
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/module.h>
 21 #include <linux/spinlock.h>
 22 #include <linux/interrupt.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/dma-mapping.h>
 25 #include <linux/debugfs.h>
 26 #include <linux/seq_file.h>
 27 #include <linux/delay.h>
 28 #include <linux/io.h>
 29 #include <linux/slab.h>
 30 #include <linux/clk.h>
 31 #include <linux/regulator/consumer.h>
 32 #include <linux/of_platform.h>
 33 #include <linux/phy/phy.h>
 34 
 35 #include <linux/usb/ch9.h>
 36 #include <linux/usb/gadget.h>
 37 #include <linux/usb/phy.h>
 38 #include <linux/platform_data/s3c-hsotg.h>
 39 
 40 #include "s3c-hsotg.h"
 41 
 42 static const char * const s3c_hsotg_supply_names[] = {
 43         "vusb_d",               /* digital USB supply, 1.2V */
 44         "vusb_a",               /* analog USB supply, 1.1V */
 45 };
 46 
 47 /*
 48  * EP0_MPS_LIMIT
 49  *
 50  * Unfortunately there seems to be a limit of the amount of data that can
 51  * be transferred by IN transactions on EP0. This is either 127 bytes or 3
 52  * packets (which practically means 1 packet and 63 bytes of data) when the
 53  * MPS is set to 64.
 54  *
 55  * This means if we are wanting to move >127 bytes of data, we need to
 56  * split the transactions up, but just doing one packet at a time does
 57  * not work (this may be an implicit DATA0 PID on first packet of the
 58  * transaction) and doing 2 packets is outside the controller's limits.
 59  *
 60  * If we try to lower the MPS size for EP0, then no transfers work properly
 61  * for EP0, and the system will fail basic enumeration. As no cause for this
 62  * has currently been found, we cannot support any large IN transfers for
 63  * EP0.
 64  */
 65 #define EP0_MPS_LIMIT   64
 66 
 67 struct s3c_hsotg;
 68 struct s3c_hsotg_req;
 69 
 70 /**
 71  * struct s3c_hsotg_ep - driver endpoint definition.
 72  * @ep: The gadget layer representation of the endpoint.
 73  * @name: The driver generated name for the endpoint.
 74  * @queue: Queue of requests for this endpoint.
 75  * @parent: Reference back to the parent device structure.
 76  * @req: The current request that the endpoint is processing. This is
 77  *       used to indicate an request has been loaded onto the endpoint
 78  *       and has yet to be completed (maybe due to data move, or simply
 79  *       awaiting an ack from the core all the data has been completed).
 80  * @debugfs: File entry for debugfs file for this endpoint.
 81  * @lock: State lock to protect contents of endpoint.
 82  * @dir_in: Set to true if this endpoint is of the IN direction, which
 83  *          means that it is sending data to the Host.
 84  * @index: The index for the endpoint registers.
 85  * @mc: Multi Count - number of transactions per microframe
 86  * @interval - Interval for periodic endpoints
 87  * @name: The name array passed to the USB core.
 88  * @halted: Set if the endpoint has been halted.
 89  * @periodic: Set if this is a periodic ep, such as Interrupt
 90  * @isochronous: Set if this is a isochronous ep
 91  * @sent_zlp: Set if we've sent a zero-length packet.
 92  * @total_data: The total number of data bytes done.
 93  * @fifo_size: The size of the FIFO (for periodic IN endpoints)
 94  * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
 95  * @last_load: The offset of data for the last start of request.
 96  * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
 97  *
 98  * This is the driver's state for each registered enpoint, allowing it
 99  * to keep track of transactions that need doing. Each endpoint has a
100  * lock to protect the state, to try and avoid using an overall lock
101  * for the host controller as much as possible.
102  *
103  * For periodic IN endpoints, we have fifo_size and fifo_load to try
104  * and keep track of the amount of data in the periodic FIFO for each
105  * of these as we don't have a status register that tells us how much
106  * is in each of them. (note, this may actually be useless information
107  * as in shared-fifo mode periodic in acts like a single-frame packet
108  * buffer than a fifo)
109  */
110 struct s3c_hsotg_ep {
111         struct usb_ep           ep;
112         struct list_head        queue;
113         struct s3c_hsotg        *parent;
114         struct s3c_hsotg_req    *req;
115         struct dentry           *debugfs;
116 
117 
118         unsigned long           total_data;
119         unsigned int            size_loaded;
120         unsigned int            last_load;
121         unsigned int            fifo_load;
122         unsigned short          fifo_size;
123 
124         unsigned char           dir_in;
125         unsigned char           index;
126         unsigned char           mc;
127         unsigned char           interval;
128 
129         unsigned int            halted:1;
130         unsigned int            periodic:1;
131         unsigned int            isochronous:1;
132         unsigned int            sent_zlp:1;
133 
134         char                    name[10];
135 };
136 
137 /**
138  * struct s3c_hsotg - driver state.
139  * @dev: The parent device supplied to the probe function
140  * @driver: USB gadget driver
141  * @phy: The otg phy transceiver structure for phy control.
142  * @uphy: The otg phy transceiver structure for old USB phy control.
143  * @plat: The platform specific configuration data. This can be removed once
144  * all SoCs support usb transceiver.
145  * @regs: The memory area mapped for accessing registers.
146  * @irq: The IRQ number we are using
147  * @supplies: Definition of USB power supplies
148  * @phyif: PHY interface width
149  * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
150  * @num_of_eps: Number of available EPs (excluding EP0)
151  * @debug_root: root directrory for debugfs.
152  * @debug_file: main status file for debugfs.
153  * @debug_fifo: FIFO status file for debugfs.
154  * @ep0_reply: Request used for ep0 reply.
155  * @ep0_buff: Buffer for EP0 reply data, if needed.
156  * @ctrl_buff: Buffer for EP0 control requests.
157  * @ctrl_req: Request for EP0 control packets.
158  * @setup: NAK management for EP0 SETUP
159  * @last_rst: Time of last reset
160  * @eps: The endpoints being supplied to the gadget framework
161  */
162 struct s3c_hsotg {
163         struct device            *dev;
164         struct usb_gadget_driver *driver;
165         struct phy               *phy;
166         struct usb_phy           *uphy;
167         struct s3c_hsotg_plat    *plat;
168 
169         spinlock_t              lock;
170 
171         void __iomem            *regs;
172         int                     irq;
173         struct clk              *clk;
174 
175         struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
176 
177         u32                     phyif;
178         unsigned int            dedicated_fifos:1;
179         unsigned char           num_of_eps;
180 
181         struct dentry           *debug_root;
182         struct dentry           *debug_file;
183         struct dentry           *debug_fifo;
184 
185         struct usb_request      *ep0_reply;
186         struct usb_request      *ctrl_req;
187         u8                      ep0_buff[8];
188         u8                      ctrl_buff[8];
189 
190         struct usb_gadget       gadget;
191         unsigned int            setup;
192         unsigned long           last_rst;
193         struct s3c_hsotg_ep     *eps;
194 };
195 
196 /**
197  * struct s3c_hsotg_req - data transfer request
198  * @req: The USB gadget request
199  * @queue: The list of requests for the endpoint this is queued for.
200  * @in_progress: Has already had size/packets written to core
201  * @mapped: DMA buffer for this request has been mapped via dma_map_single().
202  */
203 struct s3c_hsotg_req {
204         struct usb_request      req;
205         struct list_head        queue;
206         unsigned char           in_progress;
207         unsigned char           mapped;
208 };
209 
210 /* conversion functions */
211 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
212 {
213         return container_of(req, struct s3c_hsotg_req, req);
214 }
215 
216 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
217 {
218         return container_of(ep, struct s3c_hsotg_ep, ep);
219 }
220 
221 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
222 {
223         return container_of(gadget, struct s3c_hsotg, gadget);
224 }
225 
226 static inline void __orr32(void __iomem *ptr, u32 val)
227 {
228         writel(readl(ptr) | val, ptr);
229 }
230 
231 static inline void __bic32(void __iomem *ptr, u32 val)
232 {
233         writel(readl(ptr) & ~val, ptr);
234 }
235 
236 /* forward decleration of functions */
237 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
238 
239 /**
240  * using_dma - return the DMA status of the driver.
241  * @hsotg: The driver state.
242  *
243  * Return true if we're using DMA.
244  *
245  * Currently, we have the DMA support code worked into everywhere
246  * that needs it, but the AMBA DMA implementation in the hardware can
247  * only DMA from 32bit aligned addresses. This means that gadgets such
248  * as the CDC Ethernet cannot work as they often pass packets which are
249  * not 32bit aligned.
250  *
251  * Unfortunately the choice to use DMA or not is global to the controller
252  * and seems to be only settable when the controller is being put through
253  * a core reset. This means we either need to fix the gadgets to take
254  * account of DMA alignment, or add bounce buffers (yuerk).
255  *
256  * Until this issue is sorted out, we always return 'false'.
257  */
258 static inline bool using_dma(struct s3c_hsotg *hsotg)
259 {
260         return false;   /* support is not complete */
261 }
262 
263 /**
264  * s3c_hsotg_en_gsint - enable one or more of the general interrupt
265  * @hsotg: The device state
266  * @ints: A bitmask of the interrupts to enable
267  */
268 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
269 {
270         u32 gsintmsk = readl(hsotg->regs + GINTMSK);
271         u32 new_gsintmsk;
272 
273         new_gsintmsk = gsintmsk | ints;
274 
275         if (new_gsintmsk != gsintmsk) {
276                 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
277                 writel(new_gsintmsk, hsotg->regs + GINTMSK);
278         }
279 }
280 
281 /**
282  * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
283  * @hsotg: The device state
284  * @ints: A bitmask of the interrupts to enable
285  */
286 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
287 {
288         u32 gsintmsk = readl(hsotg->regs + GINTMSK);
289         u32 new_gsintmsk;
290 
291         new_gsintmsk = gsintmsk & ~ints;
292 
293         if (new_gsintmsk != gsintmsk)
294                 writel(new_gsintmsk, hsotg->regs + GINTMSK);
295 }
296 
297 /**
298  * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
299  * @hsotg: The device state
300  * @ep: The endpoint index
301  * @dir_in: True if direction is in.
302  * @en: The enable value, true to enable
303  *
304  * Set or clear the mask for an individual endpoint's interrupt
305  * request.
306  */
307 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
308                                  unsigned int ep, unsigned int dir_in,
309                                  unsigned int en)
310 {
311         unsigned long flags;
312         u32 bit = 1 << ep;
313         u32 daint;
314 
315         if (!dir_in)
316                 bit <<= 16;
317 
318         local_irq_save(flags);
319         daint = readl(hsotg->regs + DAINTMSK);
320         if (en)
321                 daint |= bit;
322         else
323                 daint &= ~bit;
324         writel(daint, hsotg->regs + DAINTMSK);
325         local_irq_restore(flags);
326 }
327 
328 /**
329  * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
330  * @hsotg: The device instance.
331  */
332 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
333 {
334         unsigned int ep;
335         unsigned int addr;
336         unsigned int size;
337         int timeout;
338         u32 val;
339 
340         /* set FIFO sizes to 2048/1024 */
341 
342         writel(2048, hsotg->regs + GRXFSIZ);
343         writel(GNPTXFSIZ_NPTxFStAddr(2048) |
344                GNPTXFSIZ_NPTxFDep(1024),
345                hsotg->regs + GNPTXFSIZ);
346 
347         /*
348          * arange all the rest of the TX FIFOs, as some versions of this
349          * block have overlapping default addresses. This also ensures
350          * that if the settings have been changed, then they are set to
351          * known values.
352          */
353 
354         /* start at the end of the GNPTXFSIZ, rounded up */
355         addr = 2048 + 1024;
356         size = 768;
357 
358         /*
359          * currently we allocate TX FIFOs for all possible endpoints,
360          * and assume that they are all the same size.
361          */
362 
363         for (ep = 1; ep <= 15; ep++) {
364                 val = addr;
365                 val |= size << DPTXFSIZn_DPTxFSize_SHIFT;
366                 addr += size;
367 
368                 writel(val, hsotg->regs + DPTXFSIZn(ep));
369         }
370 
371         /*
372          * according to p428 of the design guide, we need to ensure that
373          * all fifos are flushed before continuing
374          */
375 
376         writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh |
377                GRSTCTL_RxFFlsh, hsotg->regs + GRSTCTL);
378 
379         /* wait until the fifos are both flushed */
380         timeout = 100;
381         while (1) {
382                 val = readl(hsotg->regs + GRSTCTL);
383 
384                 if ((val & (GRSTCTL_TxFFlsh | GRSTCTL_RxFFlsh)) == 0)
385                         break;
386 
387                 if (--timeout == 0) {
388                         dev_err(hsotg->dev,
389                                 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
390                                 __func__, val);
391                 }
392 
393                 udelay(1);
394         }
395 
396         dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
397 }
398 
399 /**
400  * @ep: USB endpoint to allocate request for.
401  * @flags: Allocation flags
402  *
403  * Allocate a new USB request structure appropriate for the specified endpoint
404  */
405 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
406                                                       gfp_t flags)
407 {
408         struct s3c_hsotg_req *req;
409 
410         req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
411         if (!req)
412                 return NULL;
413 
414         INIT_LIST_HEAD(&req->queue);
415 
416         return &req->req;
417 }
418 
419 /**
420  * is_ep_periodic - return true if the endpoint is in periodic mode.
421  * @hs_ep: The endpoint to query.
422  *
423  * Returns true if the endpoint is in periodic mode, meaning it is being
424  * used for an Interrupt or ISO transfer.
425  */
426 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
427 {
428         return hs_ep->periodic;
429 }
430 
431 /**
432  * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
433  * @hsotg: The device state.
434  * @hs_ep: The endpoint for the request
435  * @hs_req: The request being processed.
436  *
437  * This is the reverse of s3c_hsotg_map_dma(), called for the completion
438  * of a request to ensure the buffer is ready for access by the caller.
439  */
440 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
441                                 struct s3c_hsotg_ep *hs_ep,
442                                 struct s3c_hsotg_req *hs_req)
443 {
444         struct usb_request *req = &hs_req->req;
445 
446         /* ignore this if we're not moving any data */
447         if (hs_req->req.length == 0)
448                 return;
449 
450         usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
451 }
452 
453 /**
454  * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
455  * @hsotg: The controller state.
456  * @hs_ep: The endpoint we're going to write for.
457  * @hs_req: The request to write data for.
458  *
459  * This is called when the TxFIFO has some space in it to hold a new
460  * transmission and we have something to give it. The actual setup of
461  * the data size is done elsewhere, so all we have to do is to actually
462  * write the data.
463  *
464  * The return value is zero if there is more space (or nothing was done)
465  * otherwise -ENOSPC is returned if the FIFO space was used up.
466  *
467  * This routine is only needed for PIO
468  */
469 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
470                                 struct s3c_hsotg_ep *hs_ep,
471                                 struct s3c_hsotg_req *hs_req)
472 {
473         bool periodic = is_ep_periodic(hs_ep);
474         u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
475         int buf_pos = hs_req->req.actual;
476         int to_write = hs_ep->size_loaded;
477         void *data;
478         int can_write;
479         int pkt_round;
480         int max_transfer;
481 
482         to_write -= (buf_pos - hs_ep->last_load);
483 
484         /* if there's nothing to write, get out early */
485         if (to_write == 0)
486                 return 0;
487 
488         if (periodic && !hsotg->dedicated_fifos) {
489                 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
490                 int size_left;
491                 int size_done;
492 
493                 /*
494                  * work out how much data was loaded so we can calculate
495                  * how much data is left in the fifo.
496                  */
497 
498                 size_left = DxEPTSIZ_XferSize_GET(epsize);
499 
500                 /*
501                  * if shared fifo, we cannot write anything until the
502                  * previous data has been completely sent.
503                  */
504                 if (hs_ep->fifo_load != 0) {
505                         s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
506                         return -ENOSPC;
507                 }
508 
509                 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
510                         __func__, size_left,
511                         hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
512 
513                 /* how much of the data has moved */
514                 size_done = hs_ep->size_loaded - size_left;
515 
516                 /* how much data is left in the fifo */
517                 can_write = hs_ep->fifo_load - size_done;
518                 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
519                         __func__, can_write);
520 
521                 can_write = hs_ep->fifo_size - can_write;
522                 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
523                         __func__, can_write);
524 
525                 if (can_write <= 0) {
526                         s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
527                         return -ENOSPC;
528                 }
529         } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
530                 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
531 
532                 can_write &= 0xffff;
533                 can_write *= 4;
534         } else {
535                 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
536                         dev_dbg(hsotg->dev,
537                                 "%s: no queue slots available (0x%08x)\n",
538                                 __func__, gnptxsts);
539 
540                         s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTxFEmp);
541                         return -ENOSPC;
542                 }
543 
544                 can_write = GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
545                 can_write *= 4; /* fifo size is in 32bit quantities. */
546         }
547 
548         max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
549 
550         dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
551                  __func__, gnptxsts, can_write, to_write, max_transfer);
552 
553         /*
554          * limit to 512 bytes of data, it seems at least on the non-periodic
555          * FIFO, requests of >512 cause the endpoint to get stuck with a
556          * fragment of the end of the transfer in it.
557          */
558         if (can_write > 512 && !periodic)
559                 can_write = 512;
560 
561         /*
562          * limit the write to one max-packet size worth of data, but allow
563          * the transfer to return that it did not run out of fifo space
564          * doing it.
565          */
566         if (to_write > max_transfer) {
567                 to_write = max_transfer;
568 
569                 /* it's needed only when we do not use dedicated fifos */
570                 if (!hsotg->dedicated_fifos)
571                         s3c_hsotg_en_gsint(hsotg,
572                                            periodic ? GINTSTS_PTxFEmp :
573                                            GINTSTS_NPTxFEmp);
574         }
575 
576         /* see if we can write data */
577 
578         if (to_write > can_write) {
579                 to_write = can_write;
580                 pkt_round = to_write % max_transfer;
581 
582                 /*
583                  * Round the write down to an
584                  * exact number of packets.
585                  *
586                  * Note, we do not currently check to see if we can ever
587                  * write a full packet or not to the FIFO.
588                  */
589 
590                 if (pkt_round)
591                         to_write -= pkt_round;
592 
593                 /*
594                  * enable correct FIFO interrupt to alert us when there
595                  * is more room left.
596                  */
597 
598                 /* it's needed only when we do not use dedicated fifos */
599                 if (!hsotg->dedicated_fifos)
600                         s3c_hsotg_en_gsint(hsotg,
601                                            periodic ? GINTSTS_PTxFEmp :
602                                            GINTSTS_NPTxFEmp);
603         }
604 
605         dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
606                  to_write, hs_req->req.length, can_write, buf_pos);
607 
608         if (to_write <= 0)
609                 return -ENOSPC;
610 
611         hs_req->req.actual = buf_pos + to_write;
612         hs_ep->total_data += to_write;
613 
614         if (periodic)
615                 hs_ep->fifo_load += to_write;
616 
617         to_write = DIV_ROUND_UP(to_write, 4);
618         data = hs_req->req.buf + buf_pos;
619 
620         iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
621 
622         return (to_write >= can_write) ? -ENOSPC : 0;
623 }
624 
625 /**
626  * get_ep_limit - get the maximum data legnth for this endpoint
627  * @hs_ep: The endpoint
628  *
629  * Return the maximum data that can be queued in one go on a given endpoint
630  * so that transfers that are too long can be split.
631  */
632 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
633 {
634         int index = hs_ep->index;
635         unsigned maxsize;
636         unsigned maxpkt;
637 
638         if (index != 0) {
639                 maxsize = DxEPTSIZ_XferSize_LIMIT + 1;
640                 maxpkt = DxEPTSIZ_PktCnt_LIMIT + 1;
641         } else {
642                 maxsize = 64+64;
643                 if (hs_ep->dir_in)
644                         maxpkt = DIEPTSIZ0_PktCnt_LIMIT + 1;
645                 else
646                         maxpkt = 2;
647         }
648 
649         /* we made the constant loading easier above by using +1 */
650         maxpkt--;
651         maxsize--;
652 
653         /*
654          * constrain by packet count if maxpkts*pktsize is greater
655          * than the length register size.
656          */
657 
658         if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
659                 maxsize = maxpkt * hs_ep->ep.maxpacket;
660 
661         return maxsize;
662 }
663 
664 /**
665  * s3c_hsotg_start_req - start a USB request from an endpoint's queue
666  * @hsotg: The controller state.
667  * @hs_ep: The endpoint to process a request for
668  * @hs_req: The request to start.
669  * @continuing: True if we are doing more for the current request.
670  *
671  * Start the given request running by setting the endpoint registers
672  * appropriately, and writing any data to the FIFOs.
673  */
674 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
675                                 struct s3c_hsotg_ep *hs_ep,
676                                 struct s3c_hsotg_req *hs_req,
677                                 bool continuing)
678 {
679         struct usb_request *ureq = &hs_req->req;
680         int index = hs_ep->index;
681         int dir_in = hs_ep->dir_in;
682         u32 epctrl_reg;
683         u32 epsize_reg;
684         u32 epsize;
685         u32 ctrl;
686         unsigned length;
687         unsigned packets;
688         unsigned maxreq;
689 
690         if (index != 0) {
691                 if (hs_ep->req && !continuing) {
692                         dev_err(hsotg->dev, "%s: active request\n", __func__);
693                         WARN_ON(1);
694                         return;
695                 } else if (hs_ep->req != hs_req && continuing) {
696                         dev_err(hsotg->dev,
697                                 "%s: continue different req\n", __func__);
698                         WARN_ON(1);
699                         return;
700                 }
701         }
702 
703         epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
704         epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
705 
706         dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
707                 __func__, readl(hsotg->regs + epctrl_reg), index,
708                 hs_ep->dir_in ? "in" : "out");
709 
710         /* If endpoint is stalled, we will restart request later */
711         ctrl = readl(hsotg->regs + epctrl_reg);
712 
713         if (ctrl & DxEPCTL_Stall) {
714                 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
715                 return;
716         }
717 
718         length = ureq->length - ureq->actual;
719         dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
720                 ureq->length, ureq->actual);
721         if (0)
722                 dev_dbg(hsotg->dev,
723                         "REQ buf %p len %d dma 0x%pad noi=%d zp=%d snok=%d\n",
724                         ureq->buf, length, &ureq->dma,
725                         ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
726 
727         maxreq = get_ep_limit(hs_ep);
728         if (length > maxreq) {
729                 int round = maxreq % hs_ep->ep.maxpacket;
730 
731                 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
732                         __func__, length, maxreq, round);
733 
734                 /* round down to multiple of packets */
735                 if (round)
736                         maxreq -= round;
737 
738                 length = maxreq;
739         }
740 
741         if (length)
742                 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
743         else
744                 packets = 1;    /* send one packet if length is zero. */
745 
746         if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
747                 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
748                 return;
749         }
750 
751         if (dir_in && index != 0)
752                 if (hs_ep->isochronous)
753                         epsize = DxEPTSIZ_MC(packets);
754                 else
755                         epsize = DxEPTSIZ_MC(1);
756         else
757                 epsize = 0;
758 
759         if (index != 0 && ureq->zero) {
760                 /*
761                  * test for the packets being exactly right for the
762                  * transfer
763                  */
764 
765                 if (length == (packets * hs_ep->ep.maxpacket))
766                         packets++;
767         }
768 
769         epsize |= DxEPTSIZ_PktCnt(packets);
770         epsize |= DxEPTSIZ_XferSize(length);
771 
772         dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
773                 __func__, packets, length, ureq->length, epsize, epsize_reg);
774 
775         /* store the request as the current one we're doing */
776         hs_ep->req = hs_req;
777 
778         /* write size / packets */
779         writel(epsize, hsotg->regs + epsize_reg);
780 
781         if (using_dma(hsotg) && !continuing) {
782                 unsigned int dma_reg;
783 
784                 /*
785                  * write DMA address to control register, buffer already
786                  * synced by s3c_hsotg_ep_queue().
787                  */
788 
789                 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
790                 writel(ureq->dma, hsotg->regs + dma_reg);
791 
792                 dev_dbg(hsotg->dev, "%s: 0x%pad => 0x%08x\n",
793                         __func__, &ureq->dma, dma_reg);
794         }
795 
796         ctrl |= DxEPCTL_EPEna;  /* ensure ep enabled */
797         ctrl |= DxEPCTL_USBActEp;
798 
799         dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
800 
801         /* For Setup request do not clear NAK */
802         if (hsotg->setup && index == 0)
803                 hsotg->setup = 0;
804         else
805                 ctrl |= DxEPCTL_CNAK;   /* clear NAK set by core */
806 
807 
808         dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
809         writel(ctrl, hsotg->regs + epctrl_reg);
810 
811         /*
812          * set these, it seems that DMA support increments past the end
813          * of the packet buffer so we need to calculate the length from
814          * this information.
815          */
816         hs_ep->size_loaded = length;
817         hs_ep->last_load = ureq->actual;
818 
819         if (dir_in && !using_dma(hsotg)) {
820                 /* set these anyway, we may need them for non-periodic in */
821                 hs_ep->fifo_load = 0;
822 
823                 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
824         }
825 
826         /*
827          * clear the INTknTXFEmpMsk when we start request, more as a aide
828          * to debugging to see what is going on.
829          */
830         if (dir_in)
831                 writel(DIEPMSK_INTknTXFEmpMsk,
832                        hsotg->regs + DIEPINT(index));
833 
834         /*
835          * Note, trying to clear the NAK here causes problems with transmit
836          * on the S3C6400 ending up with the TXFIFO becoming full.
837          */
838 
839         /* check ep is enabled */
840         if (!(readl(hsotg->regs + epctrl_reg) & DxEPCTL_EPEna))
841                 dev_warn(hsotg->dev,
842                          "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
843                          index, readl(hsotg->regs + epctrl_reg));
844 
845         dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
846                 __func__, readl(hsotg->regs + epctrl_reg));
847 
848         /* enable ep interrupts */
849         s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
850 }
851 
852 /**
853  * s3c_hsotg_map_dma - map the DMA memory being used for the request
854  * @hsotg: The device state.
855  * @hs_ep: The endpoint the request is on.
856  * @req: The request being processed.
857  *
858  * We've been asked to queue a request, so ensure that the memory buffer
859  * is correctly setup for DMA. If we've been passed an extant DMA address
860  * then ensure the buffer has been synced to memory. If our buffer has no
861  * DMA memory, then we map the memory and mark our request to allow us to
862  * cleanup on completion.
863  */
864 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
865                              struct s3c_hsotg_ep *hs_ep,
866                              struct usb_request *req)
867 {
868         struct s3c_hsotg_req *hs_req = our_req(req);
869         int ret;
870 
871         /* if the length is zero, ignore the DMA data */
872         if (hs_req->req.length == 0)
873                 return 0;
874 
875         ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
876         if (ret)
877                 goto dma_error;
878 
879         return 0;
880 
881 dma_error:
882         dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
883                 __func__, req->buf, req->length);
884 
885         return -EIO;
886 }
887 
888 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
889                               gfp_t gfp_flags)
890 {
891         struct s3c_hsotg_req *hs_req = our_req(req);
892         struct s3c_hsotg_ep *hs_ep = our_ep(ep);
893         struct s3c_hsotg *hs = hs_ep->parent;
894         bool first;
895 
896         dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
897                 ep->name, req, req->length, req->buf, req->no_interrupt,
898                 req->zero, req->short_not_ok);
899 
900         /* initialise status of the request */
901         INIT_LIST_HEAD(&hs_req->queue);
902         req->actual = 0;
903         req->status = -EINPROGRESS;
904 
905         /* if we're using DMA, sync the buffers as necessary */
906         if (using_dma(hs)) {
907                 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
908                 if (ret)
909                         return ret;
910         }
911 
912         first = list_empty(&hs_ep->queue);
913         list_add_tail(&hs_req->queue, &hs_ep->queue);
914 
915         if (first)
916                 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
917 
918         return 0;
919 }
920 
921 static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
922                               gfp_t gfp_flags)
923 {
924         struct s3c_hsotg_ep *hs_ep = our_ep(ep);
925         struct s3c_hsotg *hs = hs_ep->parent;
926         unsigned long flags = 0;
927         int ret = 0;
928 
929         spin_lock_irqsave(&hs->lock, flags);
930         ret = s3c_hsotg_ep_queue(ep, req, gfp_flags);
931         spin_unlock_irqrestore(&hs->lock, flags);
932 
933         return ret;
934 }
935 
936 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
937                                       struct usb_request *req)
938 {
939         struct s3c_hsotg_req *hs_req = our_req(req);
940 
941         kfree(hs_req);
942 }
943 
944 /**
945  * s3c_hsotg_complete_oursetup - setup completion callback
946  * @ep: The endpoint the request was on.
947  * @req: The request completed.
948  *
949  * Called on completion of any requests the driver itself
950  * submitted that need cleaning up.
951  */
952 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
953                                         struct usb_request *req)
954 {
955         struct s3c_hsotg_ep *hs_ep = our_ep(ep);
956         struct s3c_hsotg *hsotg = hs_ep->parent;
957 
958         dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
959 
960         s3c_hsotg_ep_free_request(ep, req);
961 }
962 
963 /**
964  * ep_from_windex - convert control wIndex value to endpoint
965  * @hsotg: The driver state.
966  * @windex: The control request wIndex field (in host order).
967  *
968  * Convert the given wIndex into a pointer to an driver endpoint
969  * structure, or return NULL if it is not a valid endpoint.
970  */
971 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
972                                            u32 windex)
973 {
974         struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
975         int dir = (windex & USB_DIR_IN) ? 1 : 0;
976         int idx = windex & 0x7F;
977 
978         if (windex >= 0x100)
979                 return NULL;
980 
981         if (idx > hsotg->num_of_eps)
982                 return NULL;
983 
984         if (idx && ep->dir_in != dir)
985                 return NULL;
986 
987         return ep;
988 }
989 
990 /**
991  * s3c_hsotg_send_reply - send reply to control request
992  * @hsotg: The device state
993  * @ep: Endpoint 0
994  * @buff: Buffer for request
995  * @length: Length of reply.
996  *
997  * Create a request and queue it on the given endpoint. This is useful as
998  * an internal method of sending replies to certain control requests, etc.
999  */
1000 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
1001                                 struct s3c_hsotg_ep *ep,
1002                                 void *buff,
1003                                 int length)
1004 {
1005         struct usb_request *req;
1006         int ret;
1007 
1008         dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1009 
1010         req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1011         hsotg->ep0_reply = req;
1012         if (!req) {
1013                 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1014                 return -ENOMEM;
1015         }
1016 
1017         req->buf = hsotg->ep0_buff;
1018         req->length = length;
1019         req->zero = 1; /* always do zero-length final transfer */
1020         req->complete = s3c_hsotg_complete_oursetup;
1021 
1022         if (length)
1023                 memcpy(req->buf, buff, length);
1024         else
1025                 ep->sent_zlp = 1;
1026 
1027         ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1028         if (ret) {
1029                 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1030                 return ret;
1031         }
1032 
1033         return 0;
1034 }
1035 
1036 /**
1037  * s3c_hsotg_process_req_status - process request GET_STATUS
1038  * @hsotg: The device state
1039  * @ctrl: USB control request
1040  */
1041 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
1042                                         struct usb_ctrlrequest *ctrl)
1043 {
1044         struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1045         struct s3c_hsotg_ep *ep;
1046         __le16 reply;
1047         int ret;
1048 
1049         dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1050 
1051         if (!ep0->dir_in) {
1052                 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1053                 return -EINVAL;
1054         }
1055 
1056         switch (ctrl->bRequestType & USB_RECIP_MASK) {
1057         case USB_RECIP_DEVICE:
1058                 reply = cpu_to_le16(0); /* bit 0 => self powered,
1059                                          * bit 1 => remote wakeup */
1060                 break;
1061 
1062         case USB_RECIP_INTERFACE:
1063                 /* currently, the data result should be zero */
1064                 reply = cpu_to_le16(0);
1065                 break;
1066 
1067         case USB_RECIP_ENDPOINT:
1068                 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1069                 if (!ep)
1070                         return -ENOENT;
1071 
1072                 reply = cpu_to_le16(ep->halted ? 1 : 0);
1073                 break;
1074 
1075         default:
1076                 return 0;
1077         }
1078 
1079         if (le16_to_cpu(ctrl->wLength) != 2)
1080                 return -EINVAL;
1081 
1082         ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1083         if (ret) {
1084                 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1085                 return ret;
1086         }
1087 
1088         return 1;
1089 }
1090 
1091 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1092 
1093 /**
1094  * get_ep_head - return the first request on the endpoint
1095  * @hs_ep: The controller endpoint to get
1096  *
1097  * Get the first request on the endpoint.
1098  */
1099 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1100 {
1101         if (list_empty(&hs_ep->queue))
1102                 return NULL;
1103 
1104         return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1105 }
1106 
1107 /**
1108  * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1109  * @hsotg: The device state
1110  * @ctrl: USB control request
1111  */
1112 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1113                                          struct usb_ctrlrequest *ctrl)
1114 {
1115         struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1116         struct s3c_hsotg_req *hs_req;
1117         bool restart;
1118         bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1119         struct s3c_hsotg_ep *ep;
1120         int ret;
1121         bool halted;
1122 
1123         dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1124                 __func__, set ? "SET" : "CLEAR");
1125 
1126         if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1127                 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1128                 if (!ep) {
1129                         dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1130                                 __func__, le16_to_cpu(ctrl->wIndex));
1131                         return -ENOENT;
1132                 }
1133 
1134                 switch (le16_to_cpu(ctrl->wValue)) {
1135                 case USB_ENDPOINT_HALT:
1136                         halted = ep->halted;
1137 
1138                         s3c_hsotg_ep_sethalt(&ep->ep, set);
1139 
1140                         ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1141                         if (ret) {
1142                                 dev_err(hsotg->dev,
1143                                         "%s: failed to send reply\n", __func__);
1144                                 return ret;
1145                         }
1146 
1147                         /*
1148                          * we have to complete all requests for ep if it was
1149                          * halted, and the halt was cleared by CLEAR_FEATURE
1150                          */
1151 
1152                         if (!set && halted) {
1153                                 /*
1154                                  * If we have request in progress,
1155                                  * then complete it
1156                                  */
1157                                 if (ep->req) {
1158                                         hs_req = ep->req;
1159                                         ep->req = NULL;
1160                                         list_del_init(&hs_req->queue);
1161                                         hs_req->req.complete(&ep->ep,
1162                                                              &hs_req->req);
1163                                 }
1164 
1165                                 /* If we have pending request, then start it */
1166                                 restart = !list_empty(&ep->queue);
1167                                 if (restart) {
1168                                         hs_req = get_ep_head(ep);
1169                                         s3c_hsotg_start_req(hsotg, ep,
1170                                                             hs_req, false);
1171                                 }
1172                         }
1173 
1174                         break;
1175 
1176                 default:
1177                         return -ENOENT;
1178                 }
1179         } else
1180                 return -ENOENT;  /* currently only deal with endpoint */
1181 
1182         return 1;
1183 }
1184 
1185 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1186 static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg);
1187 
1188 /**
1189  * s3c_hsotg_stall_ep0 - stall ep0
1190  * @hsotg: The device state
1191  *
1192  * Set stall for ep0 as response for setup request.
1193  */
1194 static void s3c_hsotg_stall_ep0(struct s3c_hsotg *hsotg) {
1195         struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1196         u32 reg;
1197         u32 ctrl;
1198 
1199         dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1200         reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1201 
1202         /*
1203          * DxEPCTL_Stall will be cleared by EP once it has
1204          * taken effect, so no need to clear later.
1205          */
1206 
1207         ctrl = readl(hsotg->regs + reg);
1208         ctrl |= DxEPCTL_Stall;
1209         ctrl |= DxEPCTL_CNAK;
1210         writel(ctrl, hsotg->regs + reg);
1211 
1212         dev_dbg(hsotg->dev,
1213                 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1214                 ctrl, reg, readl(hsotg->regs + reg));
1215 
1216          /*
1217           * complete won't be called, so we enqueue
1218           * setup request here
1219           */
1220          s3c_hsotg_enqueue_setup(hsotg);
1221 }
1222 
1223 /**
1224  * s3c_hsotg_process_control - process a control request
1225  * @hsotg: The device state
1226  * @ctrl: The control request received
1227  *
1228  * The controller has received the SETUP phase of a control request, and
1229  * needs to work out what to do next (and whether to pass it on to the
1230  * gadget driver).
1231  */
1232 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1233                                       struct usb_ctrlrequest *ctrl)
1234 {
1235         struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1236         int ret = 0;
1237         u32 dcfg;
1238 
1239         ep0->sent_zlp = 0;
1240 
1241         dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1242                  ctrl->bRequest, ctrl->bRequestType,
1243                  ctrl->wValue, ctrl->wLength);
1244 
1245         /*
1246          * record the direction of the request, for later use when enquing
1247          * packets onto EP0.
1248          */
1249 
1250         ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1251         dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1252 
1253         /*
1254          * if we've no data with this request, then the last part of the
1255          * transaction is going to implicitly be IN.
1256          */
1257         if (ctrl->wLength == 0)
1258                 ep0->dir_in = 1;
1259 
1260         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1261                 switch (ctrl->bRequest) {
1262                 case USB_REQ_SET_ADDRESS:
1263                         s3c_hsotg_disconnect(hsotg);
1264                         dcfg = readl(hsotg->regs + DCFG);
1265                         dcfg &= ~DCFG_DevAddr_MASK;
1266                         dcfg |= ctrl->wValue << DCFG_DevAddr_SHIFT;
1267                         writel(dcfg, hsotg->regs + DCFG);
1268 
1269                         dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1270 
1271                         ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1272                         return;
1273 
1274                 case USB_REQ_GET_STATUS:
1275                         ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1276                         break;
1277 
1278                 case USB_REQ_CLEAR_FEATURE:
1279                 case USB_REQ_SET_FEATURE:
1280                         ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1281                         break;
1282                 }
1283         }
1284 
1285         /* as a fallback, try delivering it to the driver to deal with */
1286 
1287         if (ret == 0 && hsotg->driver) {
1288                 spin_unlock(&hsotg->lock);
1289                 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1290                 spin_lock(&hsotg->lock);
1291                 if (ret < 0)
1292                         dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1293         }
1294 
1295         /*
1296          * the request is either unhandlable, or is not formatted correctly
1297          * so respond with a STALL for the status stage to indicate failure.
1298          */
1299 
1300         if (ret < 0)
1301                 s3c_hsotg_stall_ep0(hsotg);
1302 }
1303 
1304 /**
1305  * s3c_hsotg_complete_setup - completion of a setup transfer
1306  * @ep: The endpoint the request was on.
1307  * @req: The request completed.
1308  *
1309  * Called on completion of any requests the driver itself submitted for
1310  * EP0 setup packets
1311  */
1312 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1313                                      struct usb_request *req)
1314 {
1315         struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1316         struct s3c_hsotg *hsotg = hs_ep->parent;
1317 
1318         if (req->status < 0) {
1319                 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1320                 return;
1321         }
1322 
1323         spin_lock(&hsotg->lock);
1324         if (req->actual == 0)
1325                 s3c_hsotg_enqueue_setup(hsotg);
1326         else
1327                 s3c_hsotg_process_control(hsotg, req->buf);
1328         spin_unlock(&hsotg->lock);
1329 }
1330 
1331 /**
1332  * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1333  * @hsotg: The device state.
1334  *
1335  * Enqueue a request on EP0 if necessary to received any SETUP packets
1336  * received from the host.
1337  */
1338 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1339 {
1340         struct usb_request *req = hsotg->ctrl_req;
1341         struct s3c_hsotg_req *hs_req = our_req(req);
1342         int ret;
1343 
1344         dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1345 
1346         req->zero = 0;
1347         req->length = 8;
1348         req->buf = hsotg->ctrl_buff;
1349         req->complete = s3c_hsotg_complete_setup;
1350 
1351         if (!list_empty(&hs_req->queue)) {
1352                 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1353                 return;
1354         }
1355 
1356         hsotg->eps[0].dir_in = 0;
1357 
1358         ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1359         if (ret < 0) {
1360                 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1361                 /*
1362                  * Don't think there's much we can do other than watch the
1363                  * driver fail.
1364                  */
1365         }
1366 }
1367 
1368 /**
1369  * s3c_hsotg_complete_request - complete a request given to us
1370  * @hsotg: The device state.
1371  * @hs_ep: The endpoint the request was on.
1372  * @hs_req: The request to complete.
1373  * @result: The result code (0 => Ok, otherwise errno)
1374  *
1375  * The given request has finished, so call the necessary completion
1376  * if it has one and then look to see if we can start a new request
1377  * on the endpoint.
1378  *
1379  * Note, expects the ep to already be locked as appropriate.
1380  */
1381 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1382                                        struct s3c_hsotg_ep *hs_ep,
1383                                        struct s3c_hsotg_req *hs_req,
1384                                        int result)
1385 {
1386         bool restart;
1387 
1388         if (!hs_req) {
1389                 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1390                 return;
1391         }
1392 
1393         dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1394                 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1395 
1396         /*
1397          * only replace the status if we've not already set an error
1398          * from a previous transaction
1399          */
1400 
1401         if (hs_req->req.status == -EINPROGRESS)
1402                 hs_req->req.status = result;
1403 
1404         hs_ep->req = NULL;
1405         list_del_init(&hs_req->queue);
1406 
1407         if (using_dma(hsotg))
1408                 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1409 
1410         /*
1411          * call the complete request with the locks off, just in case the
1412          * request tries to queue more work for this endpoint.
1413          */
1414 
1415         if (hs_req->req.complete) {
1416                 spin_unlock(&hsotg->lock);
1417                 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1418                 spin_lock(&hsotg->lock);
1419         }
1420 
1421         /*
1422          * Look to see if there is anything else to do. Note, the completion
1423          * of the previous request may have caused a new request to be started
1424          * so be careful when doing this.
1425          */
1426 
1427         if (!hs_ep->req && result >= 0) {
1428                 restart = !list_empty(&hs_ep->queue);
1429                 if (restart) {
1430                         hs_req = get_ep_head(hs_ep);
1431                         s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1432                 }
1433         }
1434 }
1435 
1436 /**
1437  * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1438  * @hsotg: The device state.
1439  * @ep_idx: The endpoint index for the data
1440  * @size: The size of data in the fifo, in bytes
1441  *
1442  * The FIFO status shows there is data to read from the FIFO for a given
1443  * endpoint, so sort out whether we need to read the data into a request
1444  * that has been made for that endpoint.
1445  */
1446 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1447 {
1448         struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1449         struct s3c_hsotg_req *hs_req = hs_ep->req;
1450         void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1451         int to_read;
1452         int max_req;
1453         int read_ptr;
1454 
1455 
1456         if (!hs_req) {
1457                 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1458                 int ptr;
1459 
1460                 dev_warn(hsotg->dev,
1461                          "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1462                          __func__, size, ep_idx, epctl);
1463 
1464                 /* dump the data from the FIFO, we've nothing we can do */
1465                 for (ptr = 0; ptr < size; ptr += 4)
1466                         (void)readl(fifo);
1467 
1468                 return;
1469         }
1470 
1471         to_read = size;
1472         read_ptr = hs_req->req.actual;
1473         max_req = hs_req->req.length - read_ptr;
1474 
1475         dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1476                 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1477 
1478         if (to_read > max_req) {
1479                 /*
1480                  * more data appeared than we where willing
1481                  * to deal with in this request.
1482                  */
1483 
1484                 /* currently we don't deal this */
1485                 WARN_ON_ONCE(1);
1486         }
1487 
1488         hs_ep->total_data += to_read;
1489         hs_req->req.actual += to_read;
1490         to_read = DIV_ROUND_UP(to_read, 4);
1491 
1492         /*
1493          * note, we might over-write the buffer end by 3 bytes depending on
1494          * alignment of the data.
1495          */
1496         ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1497 }
1498 
1499 /**
1500  * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1501  * @hsotg: The device instance
1502  * @req: The request currently on this endpoint
1503  *
1504  * Generate a zero-length IN packet request for terminating a SETUP
1505  * transaction.
1506  *
1507  * Note, since we don't write any data to the TxFIFO, then it is
1508  * currently believed that we do not need to wait for any space in
1509  * the TxFIFO.
1510  */
1511 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1512                                struct s3c_hsotg_req *req)
1513 {
1514         u32 ctrl;
1515 
1516         if (!req) {
1517                 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1518                 return;
1519         }
1520 
1521         if (req->req.length == 0) {
1522                 hsotg->eps[0].sent_zlp = 1;
1523                 s3c_hsotg_enqueue_setup(hsotg);
1524                 return;
1525         }
1526 
1527         hsotg->eps[0].dir_in = 1;
1528         hsotg->eps[0].sent_zlp = 1;
1529 
1530         dev_dbg(hsotg->dev, "sending zero-length packet\n");
1531 
1532         /* issue a zero-sized packet to terminate this */
1533         writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1534                DxEPTSIZ_XferSize(0), hsotg->regs + DIEPTSIZ(0));
1535 
1536         ctrl = readl(hsotg->regs + DIEPCTL0);
1537         ctrl |= DxEPCTL_CNAK;  /* clear NAK set by core */
1538         ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
1539         ctrl |= DxEPCTL_USBActEp;
1540         writel(ctrl, hsotg->regs + DIEPCTL0);
1541 }
1542 
1543 /**
1544  * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1545  * @hsotg: The device instance
1546  * @epnum: The endpoint received from
1547  * @was_setup: Set if processing a SetupDone event.
1548  *
1549  * The RXFIFO has delivered an OutDone event, which means that the data
1550  * transfer for an OUT endpoint has been completed, either by a short
1551  * packet or by the finish of a transfer.
1552  */
1553 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1554                                      int epnum, bool was_setup)
1555 {
1556         u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1557         struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1558         struct s3c_hsotg_req *hs_req = hs_ep->req;
1559         struct usb_request *req = &hs_req->req;
1560         unsigned size_left = DxEPTSIZ_XferSize_GET(epsize);
1561         int result = 0;
1562 
1563         if (!hs_req) {
1564                 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1565                 return;
1566         }
1567 
1568         if (using_dma(hsotg)) {
1569                 unsigned size_done;
1570 
1571                 /*
1572                  * Calculate the size of the transfer by checking how much
1573                  * is left in the endpoint size register and then working it
1574                  * out from the amount we loaded for the transfer.
1575                  *
1576                  * We need to do this as DMA pointers are always 32bit aligned
1577                  * so may overshoot/undershoot the transfer.
1578                  */
1579 
1580                 size_done = hs_ep->size_loaded - size_left;
1581                 size_done += hs_ep->last_load;
1582 
1583                 req->actual = size_done;
1584         }
1585 
1586         /* if there is more request to do, schedule new transfer */
1587         if (req->actual < req->length && size_left == 0) {
1588                 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1589                 return;
1590         } else if (epnum == 0) {
1591                 /*
1592                  * After was_setup = 1 =>
1593                  * set CNAK for non Setup requests
1594                  */
1595                 hsotg->setup = was_setup ? 0 : 1;
1596         }
1597 
1598         if (req->actual < req->length && req->short_not_ok) {
1599                 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1600                         __func__, req->actual, req->length);
1601 
1602                 /*
1603                  * todo - what should we return here? there's no one else
1604                  * even bothering to check the status.
1605                  */
1606         }
1607 
1608         if (epnum == 0) {
1609                 /*
1610                  * Condition req->complete != s3c_hsotg_complete_setup says:
1611                  * send ZLP when we have an asynchronous request from gadget
1612                  */
1613                 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1614                         s3c_hsotg_send_zlp(hsotg, hs_req);
1615         }
1616 
1617         s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1618 }
1619 
1620 /**
1621  * s3c_hsotg_read_frameno - read current frame number
1622  * @hsotg: The device instance
1623  *
1624  * Return the current frame number
1625  */
1626 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1627 {
1628         u32 dsts;
1629 
1630         dsts = readl(hsotg->regs + DSTS);
1631         dsts &= DSTS_SOFFN_MASK;
1632         dsts >>= DSTS_SOFFN_SHIFT;
1633 
1634         return dsts;
1635 }
1636 
1637 /**
1638  * s3c_hsotg_handle_rx - RX FIFO has data
1639  * @hsotg: The device instance
1640  *
1641  * The IRQ handler has detected that the RX FIFO has some data in it
1642  * that requires processing, so find out what is in there and do the
1643  * appropriate read.
1644  *
1645  * The RXFIFO is a true FIFO, the packets coming out are still in packet
1646  * chunks, so if you have x packets received on an endpoint you'll get x
1647  * FIFO events delivered, each with a packet's worth of data in it.
1648  *
1649  * When using DMA, we should not be processing events from the RXFIFO
1650  * as the actual data should be sent to the memory directly and we turn
1651  * on the completion interrupts to get notifications of transfer completion.
1652  */
1653 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1654 {
1655         u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1656         u32 epnum, status, size;
1657 
1658         WARN_ON(using_dma(hsotg));
1659 
1660         epnum = grxstsr & GRXSTS_EPNum_MASK;
1661         status = grxstsr & GRXSTS_PktSts_MASK;
1662 
1663         size = grxstsr & GRXSTS_ByteCnt_MASK;
1664         size >>= GRXSTS_ByteCnt_SHIFT;
1665 
1666         if (1)
1667                 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1668                         __func__, grxstsr, size, epnum);
1669 
1670 #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1671 
1672         switch (status >> GRXSTS_PktSts_SHIFT) {
1673         case __status(GRXSTS_PktSts_GlobalOutNAK):
1674                 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1675                 break;
1676 
1677         case __status(GRXSTS_PktSts_OutDone):
1678                 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1679                         s3c_hsotg_read_frameno(hsotg));
1680 
1681                 if (!using_dma(hsotg))
1682                         s3c_hsotg_handle_outdone(hsotg, epnum, false);
1683                 break;
1684 
1685         case __status(GRXSTS_PktSts_SetupDone):
1686                 dev_dbg(hsotg->dev,
1687                         "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1688                         s3c_hsotg_read_frameno(hsotg),
1689                         readl(hsotg->regs + DOEPCTL(0)));
1690 
1691                 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1692                 break;
1693 
1694         case __status(GRXSTS_PktSts_OutRX):
1695                 s3c_hsotg_rx_data(hsotg, epnum, size);
1696                 break;
1697 
1698         case __status(GRXSTS_PktSts_SetupRX):
1699                 dev_dbg(hsotg->dev,
1700                         "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1701                         s3c_hsotg_read_frameno(hsotg),
1702                         readl(hsotg->regs + DOEPCTL(0)));
1703 
1704                 s3c_hsotg_rx_data(hsotg, epnum, size);
1705                 break;
1706 
1707         default:
1708                 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1709                          __func__, grxstsr);
1710 
1711                 s3c_hsotg_dump(hsotg);
1712                 break;
1713         }
1714 }
1715 
1716 /**
1717  * s3c_hsotg_ep0_mps - turn max packet size into register setting
1718  * @mps: The maximum packet size in bytes.
1719  */
1720 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1721 {
1722         switch (mps) {
1723         case 64:
1724                 return D0EPCTL_MPS_64;
1725         case 32:
1726                 return D0EPCTL_MPS_32;
1727         case 16:
1728                 return D0EPCTL_MPS_16;
1729         case 8:
1730                 return D0EPCTL_MPS_8;
1731         }
1732 
1733         /* bad max packet size, warn and return invalid result */
1734         WARN_ON(1);
1735         return (u32)-1;
1736 }
1737 
1738 /**
1739  * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1740  * @hsotg: The driver state.
1741  * @ep: The index number of the endpoint
1742  * @mps: The maximum packet size in bytes
1743  *
1744  * Configure the maximum packet size for the given endpoint, updating
1745  * the hardware control registers to reflect this.
1746  */
1747 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1748                                        unsigned int ep, unsigned int mps)
1749 {
1750         struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1751         void __iomem *regs = hsotg->regs;
1752         u32 mpsval;
1753         u32 mcval;
1754         u32 reg;
1755 
1756         if (ep == 0) {
1757                 /* EP0 is a special case */
1758                 mpsval = s3c_hsotg_ep0_mps(mps);
1759                 if (mpsval > 3)
1760                         goto bad_mps;
1761                 hs_ep->ep.maxpacket = mps;
1762                 hs_ep->mc = 1;
1763         } else {
1764                 mpsval = mps & DxEPCTL_MPS_MASK;
1765                 if (mpsval > 1024)
1766                         goto bad_mps;
1767                 mcval = ((mps >> 11) & 0x3) + 1;
1768                 hs_ep->mc = mcval;
1769                 if (mcval > 3)
1770                         goto bad_mps;
1771                 hs_ep->ep.maxpacket = mpsval;
1772         }
1773 
1774         /*
1775          * update both the in and out endpoint controldir_ registers, even
1776          * if one of the directions may not be in use.
1777          */
1778 
1779         reg = readl(regs + DIEPCTL(ep));
1780         reg &= ~DxEPCTL_MPS_MASK;
1781         reg |= mpsval;
1782         writel(reg, regs + DIEPCTL(ep));
1783 
1784         if (ep) {
1785                 reg = readl(regs + DOEPCTL(ep));
1786                 reg &= ~DxEPCTL_MPS_MASK;
1787                 reg |= mpsval;
1788                 writel(reg, regs + DOEPCTL(ep));
1789         }
1790 
1791         return;
1792 
1793 bad_mps:
1794         dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1795 }
1796 
1797 /**
1798  * s3c_hsotg_txfifo_flush - flush Tx FIFO
1799  * @hsotg: The driver state
1800  * @idx: The index for the endpoint (0..15)
1801  */
1802 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1803 {
1804         int timeout;
1805         int val;
1806 
1807         writel(GRSTCTL_TxFNum(idx) | GRSTCTL_TxFFlsh,
1808                 hsotg->regs + GRSTCTL);
1809 
1810         /* wait until the fifo is flushed */
1811         timeout = 100;
1812 
1813         while (1) {
1814                 val = readl(hsotg->regs + GRSTCTL);
1815 
1816                 if ((val & (GRSTCTL_TxFFlsh)) == 0)
1817                         break;
1818 
1819                 if (--timeout == 0) {
1820                         dev_err(hsotg->dev,
1821                                 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1822                                 __func__, val);
1823                 }
1824 
1825                 udelay(1);
1826         }
1827 }
1828 
1829 /**
1830  * s3c_hsotg_trytx - check to see if anything needs transmitting
1831  * @hsotg: The driver state
1832  * @hs_ep: The driver endpoint to check.
1833  *
1834  * Check to see if there is a request that has data to send, and if so
1835  * make an attempt to write data into the FIFO.
1836  */
1837 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1838                            struct s3c_hsotg_ep *hs_ep)
1839 {
1840         struct s3c_hsotg_req *hs_req = hs_ep->req;
1841 
1842         if (!hs_ep->dir_in || !hs_req) {
1843                 /**
1844                  * if request is not enqueued, we disable interrupts
1845                  * for endpoints, excepting ep0
1846                  */
1847                 if (hs_ep->index != 0)
1848                         s3c_hsotg_ctrl_epint(hsotg, hs_ep->index,
1849                                              hs_ep->dir_in, 0);
1850                 return 0;
1851         }
1852 
1853         if (hs_req->req.actual < hs_req->req.length) {
1854                 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1855                         hs_ep->index);
1856                 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1857         }
1858 
1859         return 0;
1860 }
1861 
1862 /**
1863  * s3c_hsotg_complete_in - complete IN transfer
1864  * @hsotg: The device state.
1865  * @hs_ep: The endpoint that has just completed.
1866  *
1867  * An IN transfer has been completed, update the transfer's state and then
1868  * call the relevant completion routines.
1869  */
1870 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1871                                   struct s3c_hsotg_ep *hs_ep)
1872 {
1873         struct s3c_hsotg_req *hs_req = hs_ep->req;
1874         u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1875         int size_left, size_done;
1876 
1877         if (!hs_req) {
1878                 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1879                 return;
1880         }
1881 
1882         /* Finish ZLP handling for IN EP0 transactions */
1883         if (hsotg->eps[0].sent_zlp) {
1884                 dev_dbg(hsotg->dev, "zlp packet received\n");
1885                 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1886                 return;
1887         }
1888 
1889         /*
1890          * Calculate the size of the transfer by checking how much is left
1891          * in the endpoint size register and then working it out from
1892          * the amount we loaded for the transfer.
1893          *
1894          * We do this even for DMA, as the transfer may have incremented
1895          * past the end of the buffer (DMA transfers are always 32bit
1896          * aligned).
1897          */
1898 
1899         size_left = DxEPTSIZ_XferSize_GET(epsize);
1900 
1901         size_done = hs_ep->size_loaded - size_left;
1902         size_done += hs_ep->last_load;
1903 
1904         if (hs_req->req.actual != size_done)
1905                 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1906                         __func__, hs_req->req.actual, size_done);
1907 
1908         hs_req->req.actual = size_done;
1909         dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1910                 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1911 
1912         /*
1913          * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1914          * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1915          * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1916          * inform the host that no more data is available.
1917          * The state of req.zero member is checked to be sure that the value to
1918          * send is smaller than wValue expected from host.
1919          * Check req.length to NOT send another ZLP when the current one is
1920          * under completion (the one for which this completion has been called).
1921          */
1922         if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero &&
1923             hs_req->req.length == hs_req->req.actual &&
1924             !(hs_req->req.length % hs_ep->ep.maxpacket)) {
1925 
1926                 dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n");
1927                 s3c_hsotg_send_zlp(hsotg, hs_req);
1928 
1929                 return;
1930         }
1931 
1932         if (!size_left && hs_req->req.actual < hs_req->req.length) {
1933                 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1934                 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1935         } else
1936                 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1937 }
1938 
1939 /**
1940  * s3c_hsotg_epint - handle an in/out endpoint interrupt
1941  * @hsotg: The driver state
1942  * @idx: The index for the endpoint (0..15)
1943  * @dir_in: Set if this is an IN endpoint
1944  *
1945  * Process and clear any interrupt pending for an individual endpoint
1946  */
1947 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1948                             int dir_in)
1949 {
1950         struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1951         u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1952         u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1953         u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1954         u32 ints;
1955         u32 ctrl;
1956 
1957         ints = readl(hsotg->regs + epint_reg);
1958         ctrl = readl(hsotg->regs + epctl_reg);
1959 
1960         /* Clear endpoint interrupts */
1961         writel(ints, hsotg->regs + epint_reg);
1962 
1963         dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1964                 __func__, idx, dir_in ? "in" : "out", ints);
1965 
1966         if (ints & DxEPINT_XferCompl) {
1967                 if (hs_ep->isochronous && hs_ep->interval == 1) {
1968                         if (ctrl & DxEPCTL_EOFrNum)
1969                                 ctrl |= DxEPCTL_SetEvenFr;
1970                         else
1971                                 ctrl |= DxEPCTL_SetOddFr;
1972                         writel(ctrl, hsotg->regs + epctl_reg);
1973                 }
1974 
1975                 dev_dbg(hsotg->dev,
1976                         "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1977                         __func__, readl(hsotg->regs + epctl_reg),
1978                         readl(hsotg->regs + epsiz_reg));
1979 
1980                 /*
1981                  * we get OutDone from the FIFO, so we only need to look
1982                  * at completing IN requests here
1983                  */
1984                 if (dir_in) {
1985                         s3c_hsotg_complete_in(hsotg, hs_ep);
1986 
1987                         if (idx == 0 && !hs_ep->req)
1988                                 s3c_hsotg_enqueue_setup(hsotg);
1989                 } else if (using_dma(hsotg)) {
1990                         /*
1991                          * We're using DMA, we need to fire an OutDone here
1992                          * as we ignore the RXFIFO.
1993                          */
1994 
1995                         s3c_hsotg_handle_outdone(hsotg, idx, false);
1996                 }
1997         }
1998 
1999         if (ints & DxEPINT_EPDisbld) {
2000                 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2001 
2002                 if (dir_in) {
2003                         int epctl = readl(hsotg->regs + epctl_reg);
2004 
2005                         s3c_hsotg_txfifo_flush(hsotg, idx);
2006 
2007                         if ((epctl & DxEPCTL_Stall) &&
2008                                 (epctl & DxEPCTL_EPType_Bulk)) {
2009                                 int dctl = readl(hsotg->regs + DCTL);
2010 
2011                                 dctl |= DCTL_CGNPInNAK;
2012                                 writel(dctl, hsotg->regs + DCTL);
2013                         }
2014                 }
2015         }
2016 
2017         if (ints & DxEPINT_AHBErr)
2018                 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2019 
2020         if (ints & DxEPINT_Setup) {  /* Setup or Timeout */
2021                 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n",  __func__);
2022 
2023                 if (using_dma(hsotg) && idx == 0) {
2024                         /*
2025                          * this is the notification we've received a
2026                          * setup packet. In non-DMA mode we'd get this
2027                          * from the RXFIFO, instead we need to process
2028                          * the setup here.
2029                          */
2030 
2031                         if (dir_in)
2032                                 WARN_ON_ONCE(1);
2033                         else
2034                                 s3c_hsotg_handle_outdone(hsotg, 0, true);
2035                 }
2036         }
2037 
2038         if (ints & DxEPINT_Back2BackSetup)
2039                 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2040 
2041         if (dir_in && !hs_ep->isochronous) {
2042                 /* not sure if this is important, but we'll clear it anyway */
2043                 if (ints & DIEPMSK_INTknTXFEmpMsk) {
2044                         dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2045                                 __func__, idx);
2046                 }
2047 
2048                 /* this probably means something bad is happening */
2049                 if (ints & DIEPMSK_INTknEPMisMsk) {
2050                         dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2051                                  __func__, idx);
2052                 }
2053 
2054                 /* FIFO has space or is empty (see GAHBCFG) */
2055                 if (hsotg->dedicated_fifos &&
2056                     ints & DIEPMSK_TxFIFOEmpty) {
2057                         dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2058                                 __func__, idx);
2059                         if (!using_dma(hsotg))
2060                                 s3c_hsotg_trytx(hsotg, hs_ep);
2061                 }
2062         }
2063 }
2064 
2065 /**
2066  * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2067  * @hsotg: The device state.
2068  *
2069  * Handle updating the device settings after the enumeration phase has
2070  * been completed.
2071  */
2072 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
2073 {
2074         u32 dsts = readl(hsotg->regs + DSTS);
2075         int ep0_mps = 0, ep_mps;
2076 
2077         /*
2078          * This should signal the finish of the enumeration phase
2079          * of the USB handshaking, so we should now know what rate
2080          * we connected at.
2081          */
2082 
2083         dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2084 
2085         /*
2086          * note, since we're limited by the size of transfer on EP0, and
2087          * it seems IN transfers must be a even number of packets we do
2088          * not advertise a 64byte MPS on EP0.
2089          */
2090 
2091         /* catch both EnumSpd_FS and EnumSpd_FS48 */
2092         switch (dsts & DSTS_EnumSpd_MASK) {
2093         case DSTS_EnumSpd_FS:
2094         case DSTS_EnumSpd_FS48:
2095                 hsotg->gadget.speed = USB_SPEED_FULL;
2096                 ep0_mps = EP0_MPS_LIMIT;
2097                 ep_mps = 1023;
2098                 break;
2099 
2100         case DSTS_EnumSpd_HS:
2101                 hsotg->gadget.speed = USB_SPEED_HIGH;
2102                 ep0_mps = EP0_MPS_LIMIT;
2103                 ep_mps = 1024;
2104                 break;
2105 
2106         case DSTS_EnumSpd_LS:
2107                 hsotg->gadget.speed = USB_SPEED_LOW;
2108                 /*
2109                  * note, we don't actually support LS in this driver at the
2110                  * moment, and the documentation seems to imply that it isn't
2111                  * supported by the PHYs on some of the devices.
2112                  */
2113                 break;
2114         }
2115         dev_info(hsotg->dev, "new device is %s\n",
2116                  usb_speed_string(hsotg->gadget.speed));
2117 
2118         /*
2119          * we should now know the maximum packet size for an
2120          * endpoint, so set the endpoints to a default value.
2121          */
2122 
2123         if (ep0_mps) {
2124                 int i;
2125                 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
2126                 for (i = 1; i < hsotg->num_of_eps; i++)
2127                         s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
2128         }
2129 
2130         /* ensure after enumeration our EP0 is active */
2131 
2132         s3c_hsotg_enqueue_setup(hsotg);
2133 
2134         dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2135                 readl(hsotg->regs + DIEPCTL0),
2136                 readl(hsotg->regs + DOEPCTL0));
2137 }
2138 
2139 /**
2140  * kill_all_requests - remove all requests from the endpoint's queue
2141  * @hsotg: The device state.
2142  * @ep: The endpoint the requests may be on.
2143  * @result: The result code to use.
2144  * @force: Force removal of any current requests
2145  *
2146  * Go through the requests on the given endpoint and mark them
2147  * completed with the given result code.
2148  */
2149 static void kill_all_requests(struct s3c_hsotg *hsotg,
2150                               struct s3c_hsotg_ep *ep,
2151                               int result, bool force)
2152 {
2153         struct s3c_hsotg_req *req, *treq;
2154 
2155         list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2156                 /*
2157                  * currently, we can't do much about an already
2158                  * running request on an in endpoint
2159                  */
2160 
2161                 if (ep->req == req && ep->dir_in && !force)
2162                         continue;
2163 
2164                 s3c_hsotg_complete_request(hsotg, ep, req,
2165                                            result);
2166         }
2167         if(hsotg->dedicated_fifos)
2168                 if ((readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4 < 3072)
2169                         s3c_hsotg_txfifo_flush(hsotg, ep->index);
2170 }
2171 
2172 #define call_gadget(_hs, _entry) \
2173 do { \
2174         if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2175             (_hs)->driver && (_hs)->driver->_entry) { \
2176                 spin_unlock(&_hs->lock); \
2177                 (_hs)->driver->_entry(&(_hs)->gadget); \
2178                 spin_lock(&_hs->lock); \
2179         } \
2180 } while (0)
2181 
2182 /**
2183  * s3c_hsotg_disconnect - disconnect service
2184  * @hsotg: The device state.
2185  *
2186  * The device has been disconnected. Remove all current
2187  * transactions and signal the gadget driver that this
2188  * has happened.
2189  */
2190 static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg)
2191 {
2192         unsigned ep;
2193 
2194         for (ep = 0; ep < hsotg->num_of_eps; ep++)
2195                 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2196 
2197         call_gadget(hsotg, disconnect);
2198 }
2199 
2200 /**
2201  * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2202  * @hsotg: The device state:
2203  * @periodic: True if this is a periodic FIFO interrupt
2204  */
2205 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2206 {
2207         struct s3c_hsotg_ep *ep;
2208         int epno, ret;
2209 
2210         /* look through for any more data to transmit */
2211 
2212         for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2213                 ep = &hsotg->eps[epno];
2214 
2215                 if (!ep->dir_in)
2216                         continue;
2217 
2218                 if ((periodic && !ep->periodic) ||
2219                     (!periodic && ep->periodic))
2220                         continue;
2221 
2222                 ret = s3c_hsotg_trytx(hsotg, ep);
2223                 if (ret < 0)
2224                         break;
2225         }
2226 }
2227 
2228 /* IRQ flags which will trigger a retry around the IRQ loop */
2229 #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2230                         GINTSTS_PTxFEmp |  \
2231                         GINTSTS_RxFLvl)
2232 
2233 /**
2234  * s3c_hsotg_corereset - issue softreset to the core
2235  * @hsotg: The device state
2236  *
2237  * Issue a soft reset to the core, and await the core finishing it.
2238  */
2239 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2240 {
2241         int timeout;
2242         u32 grstctl;
2243 
2244         dev_dbg(hsotg->dev, "resetting core\n");
2245 
2246         /* issue soft reset */
2247         writel(GRSTCTL_CSftRst, hsotg->regs + GRSTCTL);
2248 
2249         timeout = 10000;
2250         do {
2251                 grstctl = readl(hsotg->regs + GRSTCTL);
2252         } while ((grstctl & GRSTCTL_CSftRst) && timeout-- > 0);
2253 
2254         if (grstctl & GRSTCTL_CSftRst) {
2255                 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2256                 return -EINVAL;
2257         }
2258 
2259         timeout = 10000;
2260 
2261         while (1) {
2262                 u32 grstctl = readl(hsotg->regs + GRSTCTL);
2263 
2264                 if (timeout-- < 0) {
2265                         dev_info(hsotg->dev,
2266                                  "%s: reset failed, GRSTCTL=%08x\n",
2267                                  __func__, grstctl);
2268                         return -ETIMEDOUT;
2269                 }
2270 
2271                 if (!(grstctl & GRSTCTL_AHBIdle))
2272                         continue;
2273 
2274                 break;          /* reset done */
2275         }
2276 
2277         dev_dbg(hsotg->dev, "reset successful\n");
2278         return 0;
2279 }
2280 
2281 /**
2282  * s3c_hsotg_core_init - issue softreset to the core
2283  * @hsotg: The device state
2284  *
2285  * Issue a soft reset to the core, and await the core finishing it.
2286  */
2287 static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2288 {
2289         s3c_hsotg_corereset(hsotg);
2290 
2291         /*
2292          * we must now enable ep0 ready for host detection and then
2293          * set configuration.
2294          */
2295 
2296         /* set the PLL on, remove the HNP/SRP and set the PHY */
2297         writel(hsotg->phyif | GUSBCFG_TOutCal(7) |
2298                (0x5 << 10), hsotg->regs + GUSBCFG);
2299 
2300         s3c_hsotg_init_fifo(hsotg);
2301 
2302         __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2303 
2304         writel(1 << 18 | DCFG_DevSpd_HS,  hsotg->regs + DCFG);
2305 
2306         /* Clear any pending OTG interrupts */
2307         writel(0xffffffff, hsotg->regs + GOTGINT);
2308 
2309         /* Clear any pending interrupts */
2310         writel(0xffffffff, hsotg->regs + GINTSTS);
2311 
2312         writel(GINTSTS_ErlySusp | GINTSTS_SessReqInt |
2313                GINTSTS_GOUTNakEff | GINTSTS_GINNakEff |
2314                GINTSTS_ConIDStsChng | GINTSTS_USBRst |
2315                GINTSTS_EnumDone | GINTSTS_OTGInt |
2316                GINTSTS_USBSusp | GINTSTS_WkUpInt,
2317                hsotg->regs + GINTMSK);
2318 
2319         if (using_dma(hsotg))
2320                 writel(GAHBCFG_GlblIntrEn | GAHBCFG_DMAEn |
2321                        GAHBCFG_HBstLen_Incr4,
2322                        hsotg->regs + GAHBCFG);
2323         else
2324                 writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NPTxFEmpLvl |
2325                                                     GAHBCFG_PTxFEmpLvl) : 0) |
2326                        GAHBCFG_GlblIntrEn,
2327                        hsotg->regs + GAHBCFG);
2328 
2329         /*
2330          * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2331          * when we have no data to transfer. Otherwise we get being flooded by
2332          * interrupts.
2333          */
2334 
2335         writel(((hsotg->dedicated_fifos) ? DIEPMSK_TxFIFOEmpty |
2336                DIEPMSK_INTknTXFEmpMsk : 0) |
2337                DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk |
2338                DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2339                DIEPMSK_INTknEPMisMsk,
2340                hsotg->regs + DIEPMSK);
2341 
2342         /*
2343          * don't need XferCompl, we get that from RXFIFO in slave mode. In
2344          * DMA mode we may need this.
2345          */
2346         writel((using_dma(hsotg) ? (DIEPMSK_XferComplMsk |
2347                                     DIEPMSK_TimeOUTMsk) : 0) |
2348                DOEPMSK_EPDisbldMsk | DOEPMSK_AHBErrMsk |
2349                DOEPMSK_SetupMsk,
2350                hsotg->regs + DOEPMSK);
2351 
2352         writel(0, hsotg->regs + DAINTMSK);
2353 
2354         dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2355                 readl(hsotg->regs + DIEPCTL0),
2356                 readl(hsotg->regs + DOEPCTL0));
2357 
2358         /* enable in and out endpoint interrupts */
2359         s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPInt | GINTSTS_IEPInt);
2360 
2361         /*
2362          * Enable the RXFIFO when in slave mode, as this is how we collect
2363          * the data. In DMA mode, we get events from the FIFO but also
2364          * things we cannot process, so do not use it.
2365          */
2366         if (!using_dma(hsotg))
2367                 s3c_hsotg_en_gsint(hsotg, GINTSTS_RxFLvl);
2368 
2369         /* Enable interrupts for EP0 in and out */
2370         s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2371         s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2372 
2373         __orr32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2374         udelay(10);  /* see openiboot */
2375         __bic32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2376 
2377         dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
2378 
2379         /*
2380          * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2381          * writing to the EPCTL register..
2382          */
2383 
2384         /* set to read 1 8byte packet */
2385         writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2386                DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2387 
2388         writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2389                DxEPCTL_CNAK | DxEPCTL_EPEna |
2390                DxEPCTL_USBActEp,
2391                hsotg->regs + DOEPCTL0);
2392 
2393         /* enable, but don't activate EP0in */
2394         writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2395                DxEPCTL_USBActEp, hsotg->regs + DIEPCTL0);
2396 
2397         s3c_hsotg_enqueue_setup(hsotg);
2398 
2399         dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2400                 readl(hsotg->regs + DIEPCTL0),
2401                 readl(hsotg->regs + DOEPCTL0));
2402 
2403         /* clear global NAKs */
2404         writel(DCTL_CGOUTNak | DCTL_CGNPInNAK,
2405                hsotg->regs + DCTL);
2406 
2407         /* must be at-least 3ms to allow bus to see disconnect */
2408         mdelay(3);
2409 
2410         /* remove the soft-disconnect and let's go */
2411         __bic32(hsotg->regs + DCTL, DCTL_SftDiscon);
2412 }
2413 
2414 /**
2415  * s3c_hsotg_irq - handle device interrupt
2416  * @irq: The IRQ number triggered
2417  * @pw: The pw value when registered the handler.
2418  */
2419 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2420 {
2421         struct s3c_hsotg *hsotg = pw;
2422         int retry_count = 8;
2423         u32 gintsts;
2424         u32 gintmsk;
2425 
2426         spin_lock(&hsotg->lock);
2427 irq_retry:
2428         gintsts = readl(hsotg->regs + GINTSTS);
2429         gintmsk = readl(hsotg->regs + GINTMSK);
2430 
2431         dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2432                 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2433 
2434         gintsts &= gintmsk;
2435 
2436         if (gintsts & GINTSTS_OTGInt) {
2437                 u32 otgint = readl(hsotg->regs + GOTGINT);
2438 
2439                 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2440 
2441                 writel(otgint, hsotg->regs + GOTGINT);
2442         }
2443 
2444         if (gintsts & GINTSTS_SessReqInt) {
2445                 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2446                 writel(GINTSTS_SessReqInt, hsotg->regs + GINTSTS);
2447         }
2448 
2449         if (gintsts & GINTSTS_EnumDone) {
2450                 writel(GINTSTS_EnumDone, hsotg->regs + GINTSTS);
2451 
2452                 s3c_hsotg_irq_enumdone(hsotg);
2453         }
2454 
2455         if (gintsts & GINTSTS_ConIDStsChng) {
2456                 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2457                         readl(hsotg->regs + DSTS),
2458                         readl(hsotg->regs + GOTGCTL));
2459 
2460                 writel(GINTSTS_ConIDStsChng, hsotg->regs + GINTSTS);
2461         }
2462 
2463         if (gintsts & (GINTSTS_OEPInt | GINTSTS_IEPInt)) {
2464                 u32 daint = readl(hsotg->regs + DAINT);
2465                 u32 daintmsk = readl(hsotg->regs + DAINTMSK);
2466                 u32 daint_out, daint_in;
2467                 int ep;
2468 
2469                 daint &= daintmsk;
2470                 daint_out = daint >> DAINT_OutEP_SHIFT;
2471                 daint_in = daint & ~(daint_out << DAINT_OutEP_SHIFT);
2472 
2473                 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2474 
2475                 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2476                         if (daint_out & 1)
2477                                 s3c_hsotg_epint(hsotg, ep, 0);
2478                 }
2479 
2480                 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2481                         if (daint_in & 1)
2482                                 s3c_hsotg_epint(hsotg, ep, 1);
2483                 }
2484         }
2485 
2486         if (gintsts & GINTSTS_USBRst) {
2487 
2488                 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2489 
2490                 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2491                 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2492                         readl(hsotg->regs + GNPTXSTS));
2493 
2494                 writel(GINTSTS_USBRst, hsotg->regs + GINTSTS);
2495 
2496                 if (usb_status & GOTGCTL_BSESVLD) {
2497                         if (time_after(jiffies, hsotg->last_rst +
2498                                        msecs_to_jiffies(200))) {
2499 
2500                                 kill_all_requests(hsotg, &hsotg->eps[0],
2501                                                           -ECONNRESET, true);
2502 
2503                                 s3c_hsotg_core_init(hsotg);
2504                                 hsotg->last_rst = jiffies;
2505                         }
2506                 }
2507         }
2508 
2509         /* check both FIFOs */
2510 
2511         if (gintsts & GINTSTS_NPTxFEmp) {
2512                 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2513 
2514                 /*
2515                  * Disable the interrupt to stop it happening again
2516                  * unless one of these endpoint routines decides that
2517                  * it needs re-enabling
2518                  */
2519 
2520                 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTxFEmp);
2521                 s3c_hsotg_irq_fifoempty(hsotg, false);
2522         }
2523 
2524         if (gintsts & GINTSTS_PTxFEmp) {
2525                 dev_dbg(hsotg->dev, "PTxFEmp\n");
2526 
2527                 /* See note in GINTSTS_NPTxFEmp */
2528 
2529                 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTxFEmp);
2530                 s3c_hsotg_irq_fifoempty(hsotg, true);
2531         }
2532 
2533         if (gintsts & GINTSTS_RxFLvl) {
2534                 /*
2535                  * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2536                  * we need to retry s3c_hsotg_handle_rx if this is still
2537                  * set.
2538                  */
2539 
2540                 s3c_hsotg_handle_rx(hsotg);
2541         }
2542 
2543         if (gintsts & GINTSTS_ModeMis) {
2544                 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2545                 writel(GINTSTS_ModeMis, hsotg->regs + GINTSTS);
2546         }
2547 
2548         if (gintsts & GINTSTS_USBSusp) {
2549                 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
2550                 writel(GINTSTS_USBSusp, hsotg->regs + GINTSTS);
2551 
2552                 call_gadget(hsotg, suspend);
2553         }
2554 
2555         if (gintsts & GINTSTS_WkUpInt) {
2556                 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
2557                 writel(GINTSTS_WkUpInt, hsotg->regs + GINTSTS);
2558 
2559                 call_gadget(hsotg, resume);
2560         }
2561 
2562         if (gintsts & GINTSTS_ErlySusp) {
2563                 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2564                 writel(GINTSTS_ErlySusp, hsotg->regs + GINTSTS);
2565         }
2566 
2567         /*
2568          * these next two seem to crop-up occasionally causing the core
2569          * to shutdown the USB transfer, so try clearing them and logging
2570          * the occurrence.
2571          */
2572 
2573         if (gintsts & GINTSTS_GOUTNakEff) {
2574                 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2575 
2576                 writel(DCTL_CGOUTNak, hsotg->regs + DCTL);
2577 
2578                 s3c_hsotg_dump(hsotg);
2579         }
2580 
2581         if (gintsts & GINTSTS_GINNakEff) {
2582                 dev_info(hsotg->dev, "GINNakEff triggered\n");
2583 
2584                 writel(DCTL_CGNPInNAK, hsotg->regs + DCTL);
2585 
2586                 s3c_hsotg_dump(hsotg);
2587         }
2588 
2589         /*
2590          * if we've had fifo events, we should try and go around the
2591          * loop again to see if there's any point in returning yet.
2592          */
2593 
2594         if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2595                         goto irq_retry;
2596 
2597         spin_unlock(&hsotg->lock);
2598 
2599         return IRQ_HANDLED;
2600 }
2601 
2602 /**
2603  * s3c_hsotg_ep_enable - enable the given endpoint
2604  * @ep: The USB endpint to configure
2605  * @desc: The USB endpoint descriptor to configure with.
2606  *
2607  * This is called from the USB gadget code's usb_ep_enable().
2608  */
2609 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2610                                const struct usb_endpoint_descriptor *desc)
2611 {
2612         struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2613         struct s3c_hsotg *hsotg = hs_ep->parent;
2614         unsigned long flags;
2615         int index = hs_ep->index;
2616         u32 epctrl_reg;
2617         u32 epctrl;
2618         u32 mps;
2619         int dir_in;
2620         int ret = 0;
2621 
2622         dev_dbg(hsotg->dev,
2623                 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2624                 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2625                 desc->wMaxPacketSize, desc->bInterval);
2626 
2627         /* not to be called for EP0 */
2628         WARN_ON(index == 0);
2629 
2630         dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2631         if (dir_in != hs_ep->dir_in) {
2632                 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2633                 return -EINVAL;
2634         }
2635 
2636         mps = usb_endpoint_maxp(desc);
2637 
2638         /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2639 
2640         epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2641         epctrl = readl(hsotg->regs + epctrl_reg);
2642 
2643         dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2644                 __func__, epctrl, epctrl_reg);
2645 
2646         spin_lock_irqsave(&hsotg->lock, flags);
2647 
2648         epctrl &= ~(DxEPCTL_EPType_MASK | DxEPCTL_MPS_MASK);
2649         epctrl |= DxEPCTL_MPS(mps);
2650 
2651         /*
2652          * mark the endpoint as active, otherwise the core may ignore
2653          * transactions entirely for this endpoint
2654          */
2655         epctrl |= DxEPCTL_USBActEp;
2656 
2657         /*
2658          * set the NAK status on the endpoint, otherwise we might try and
2659          * do something with data that we've yet got a request to process
2660          * since the RXFIFO will take data for an endpoint even if the
2661          * size register hasn't been set.
2662          */
2663 
2664         epctrl |= DxEPCTL_SNAK;
2665 
2666         /* update the endpoint state */
2667         s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps);
2668 
2669         /* default, set to non-periodic */
2670         hs_ep->isochronous = 0;
2671         hs_ep->periodic = 0;
2672         hs_ep->halted = 0;
2673         hs_ep->interval = desc->bInterval;
2674 
2675         if (hs_ep->interval > 1 && hs_ep->mc > 1)
2676                 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2677 
2678         switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2679         case USB_ENDPOINT_XFER_ISOC:
2680                 epctrl |= DxEPCTL_EPType_Iso;
2681                 epctrl |= DxEPCTL_SetEvenFr;
2682                 hs_ep->isochronous = 1;
2683                 if (dir_in)
2684                         hs_ep->periodic = 1;
2685                 break;
2686 
2687         case USB_ENDPOINT_XFER_BULK:
2688                 epctrl |= DxEPCTL_EPType_Bulk;
2689                 break;
2690 
2691         case USB_ENDPOINT_XFER_INT:
2692                 if (dir_in) {
2693                         /*
2694                          * Allocate our TxFNum by simply using the index
2695                          * of the endpoint for the moment. We could do
2696                          * something better if the host indicates how
2697                          * many FIFOs we are expecting to use.
2698                          */
2699 
2700                         hs_ep->periodic = 1;
2701                         epctrl |= DxEPCTL_TxFNum(index);
2702                 }
2703 
2704                 epctrl |= DxEPCTL_EPType_Intterupt;
2705                 break;
2706 
2707         case USB_ENDPOINT_XFER_CONTROL:
2708                 epctrl |= DxEPCTL_EPType_Control;
2709                 break;
2710         }
2711 
2712         /*
2713          * if the hardware has dedicated fifos, we must give each IN EP
2714          * a unique tx-fifo even if it is non-periodic.
2715          */
2716         if (dir_in && hsotg->dedicated_fifos)
2717                 epctrl |= DxEPCTL_TxFNum(index);
2718 
2719         /* for non control endpoints, set PID to D0 */
2720         if (index)
2721                 epctrl |= DxEPCTL_SetD0PID;
2722 
2723         dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2724                 __func__, epctrl);
2725 
2726         writel(epctrl, hsotg->regs + epctrl_reg);
2727         dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2728                 __func__, readl(hsotg->regs + epctrl_reg));
2729 
2730         /* enable the endpoint interrupt */
2731         s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2732 
2733         spin_unlock_irqrestore(&hsotg->lock, flags);
2734         return ret;
2735 }
2736 
2737 /**
2738  * s3c_hsotg_ep_disable - disable given endpoint
2739  * @ep: The endpoint to disable.
2740  */
2741 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2742 {
2743         struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2744         struct s3c_hsotg *hsotg = hs_ep->parent;
2745         int dir_in = hs_ep->dir_in;
2746         int index = hs_ep->index;
2747         unsigned long flags;
2748         u32 epctrl_reg;
2749         u32 ctrl;
2750 
2751         dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2752 
2753         if (ep == &hsotg->eps[0].ep) {
2754                 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2755                 return -EINVAL;
2756         }
2757 
2758         epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2759 
2760         spin_lock_irqsave(&hsotg->lock, flags);
2761         /* terminate all requests with shutdown */
2762         kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2763 
2764 
2765         ctrl = readl(hsotg->regs + epctrl_reg);
2766         ctrl &= ~DxEPCTL_EPEna;
2767         ctrl &= ~DxEPCTL_USBActEp;
2768         ctrl |= DxEPCTL_SNAK;
2769 
2770         dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2771         writel(ctrl, hsotg->regs + epctrl_reg);
2772 
2773         /* disable endpoint interrupts */
2774         s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2775 
2776         spin_unlock_irqrestore(&hsotg->lock, flags);
2777         return 0;
2778 }
2779 
2780 /**
2781  * on_list - check request is on the given endpoint
2782  * @ep: The endpoint to check.
2783  * @test: The request to test if it is on the endpoint.
2784  */
2785 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2786 {
2787         struct s3c_hsotg_req *req, *treq;
2788 
2789         list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2790                 if (req == test)
2791                         return true;
2792         }
2793 
2794         return false;
2795 }
2796 
2797 /**
2798  * s3c_hsotg_ep_dequeue - dequeue given endpoint
2799  * @ep: The endpoint to dequeue.
2800  * @req: The request to be removed from a queue.
2801  */
2802 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2803 {
2804         struct s3c_hsotg_req *hs_req = our_req(req);
2805         struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2806         struct s3c_hsotg *hs = hs_ep->parent;
2807         unsigned long flags;
2808 
2809         dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2810 
2811         spin_lock_irqsave(&hs->lock, flags);
2812 
2813         if (!on_list(hs_ep, hs_req)) {
2814                 spin_unlock_irqrestore(&hs->lock, flags);
2815                 return -EINVAL;
2816         }
2817 
2818         s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2819         spin_unlock_irqrestore(&hs->lock, flags);
2820 
2821         return 0;
2822 }
2823 
2824 /**
2825  * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2826  * @ep: The endpoint to set halt.
2827  * @value: Set or unset the halt.
2828  */
2829 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2830 {
2831         struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2832         struct s3c_hsotg *hs = hs_ep->parent;
2833         int index = hs_ep->index;
2834         u32 epreg;
2835         u32 epctl;
2836         u32 xfertype;
2837 
2838         dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2839 
2840         if (index == 0) {
2841                 if (value)
2842                         s3c_hsotg_stall_ep0(hs);
2843                 else
2844                         dev_warn(hs->dev,
2845                                  "%s: can't clear halt on ep0\n", __func__);
2846                 return 0;
2847         }
2848 
2849         /* write both IN and OUT control registers */
2850 
2851         epreg = DIEPCTL(index);
2852         epctl = readl(hs->regs + epreg);
2853 
2854         if (value) {
2855                 epctl |= DxEPCTL_Stall + DxEPCTL_SNAK;
2856                 if (epctl & DxEPCTL_EPEna)
2857                         epctl |= DxEPCTL_EPDis;
2858         } else {
2859                 epctl &= ~DxEPCTL_Stall;
2860                 xfertype = epctl & DxEPCTL_EPType_MASK;
2861                 if (xfertype == DxEPCTL_EPType_Bulk ||
2862                         xfertype == DxEPCTL_EPType_Intterupt)
2863                                 epctl |= DxEPCTL_SetD0PID;
2864         }
2865 
2866         writel(epctl, hs->regs + epreg);
2867 
2868         epreg = DOEPCTL(index);
2869         epctl = readl(hs->regs + epreg);
2870 
2871         if (value)
2872                 epctl |= DxEPCTL_Stall;
2873         else {
2874                 epctl &= ~DxEPCTL_Stall;
2875                 xfertype = epctl & DxEPCTL_EPType_MASK;
2876                 if (xfertype == DxEPCTL_EPType_Bulk ||
2877                         xfertype == DxEPCTL_EPType_Intterupt)
2878                                 epctl |= DxEPCTL_SetD0PID;
2879         }
2880 
2881         writel(epctl, hs->regs + epreg);
2882 
2883         hs_ep->halted = value;
2884 
2885         return 0;
2886 }
2887 
2888 /**
2889  * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2890  * @ep: The endpoint to set halt.
2891  * @value: Set or unset the halt.
2892  */
2893 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
2894 {
2895         struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2896         struct s3c_hsotg *hs = hs_ep->parent;
2897         unsigned long flags = 0;
2898         int ret = 0;
2899 
2900         spin_lock_irqsave(&hs->lock, flags);
2901         ret = s3c_hsotg_ep_sethalt(ep, value);
2902         spin_unlock_irqrestore(&hs->lock, flags);
2903 
2904         return ret;
2905 }
2906 
2907 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2908         .enable         = s3c_hsotg_ep_enable,
2909         .disable        = s3c_hsotg_ep_disable,
2910         .alloc_request  = s3c_hsotg_ep_alloc_request,
2911         .free_request   = s3c_hsotg_ep_free_request,
2912         .queue          = s3c_hsotg_ep_queue_lock,
2913         .dequeue        = s3c_hsotg_ep_dequeue,
2914         .set_halt       = s3c_hsotg_ep_sethalt_lock,
2915         /* note, don't believe we have any call for the fifo routines */
2916 };
2917 
2918 /**
2919  * s3c_hsotg_phy_enable - enable platform phy dev
2920  * @hsotg: The driver state
2921  *
2922  * A wrapper for platform code responsible for controlling
2923  * low-level USB code
2924  */
2925 static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
2926 {
2927         struct platform_device *pdev = to_platform_device(hsotg->dev);
2928 
2929         dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2930 
2931         if (hsotg->phy) {
2932                 phy_init(hsotg->phy);
2933                 phy_power_on(hsotg->phy);
2934         } else if (hsotg->uphy)
2935                 usb_phy_init(hsotg->uphy);
2936         else if (hsotg->plat->phy_init)
2937                 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2938 }
2939 
2940 /**
2941  * s3c_hsotg_phy_disable - disable platform phy dev
2942  * @hsotg: The driver state
2943  *
2944  * A wrapper for platform code responsible for controlling
2945  * low-level USB code
2946  */
2947 static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
2948 {
2949         struct platform_device *pdev = to_platform_device(hsotg->dev);
2950 
2951         if (hsotg->phy) {
2952                 phy_power_off(hsotg->phy);
2953                 phy_exit(hsotg->phy);
2954         } else if (hsotg->uphy)
2955                 usb_phy_shutdown(hsotg->uphy);
2956         else if (hsotg->plat->phy_exit)
2957                 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2958 }
2959 
2960 /**
2961  * s3c_hsotg_init - initalize the usb core
2962  * @hsotg: The driver state
2963  */
2964 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2965 {
2966         /* unmask subset of endpoint interrupts */
2967 
2968         writel(DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2969                DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk,
2970                hsotg->regs + DIEPMSK);
2971 
2972         writel(DOEPMSK_SetupMsk | DOEPMSK_AHBErrMsk |
2973                DOEPMSK_EPDisbldMsk | DOEPMSK_XferComplMsk,
2974                hsotg->regs + DOEPMSK);
2975 
2976         writel(0, hsotg->regs + DAINTMSK);
2977 
2978         /* Be in disconnected state until gadget is registered */
2979         __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2980 
2981         if (0) {
2982                 /* post global nak until we're ready */
2983                 writel(DCTL_SGNPInNAK | DCTL_SGOUTNak,
2984                        hsotg->regs + DCTL);
2985         }
2986 
2987         /* setup fifos */
2988 
2989         dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2990                 readl(hsotg->regs + GRXFSIZ),
2991                 readl(hsotg->regs + GNPTXFSIZ));
2992 
2993         s3c_hsotg_init_fifo(hsotg);
2994 
2995         /* set the PLL on, remove the HNP/SRP and set the PHY */
2996         writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) | (0x5 << 10),
2997                hsotg->regs + GUSBCFG);
2998 
2999         writel(using_dma(hsotg) ? GAHBCFG_DMAEn : 0x0,
3000                hsotg->regs + GAHBCFG);
3001 }
3002 
3003 /**
3004  * s3c_hsotg_udc_start - prepare the udc for work
3005  * @gadget: The usb gadget state
3006  * @driver: The usb gadget driver
3007  *
3008  * Perform initialization to prepare udc device and driver
3009  * to work.
3010  */
3011 static int s3c_hsotg_udc_start(struct usb_gadget *gadget,
3012                            struct usb_gadget_driver *driver)
3013 {
3014         struct s3c_hsotg *hsotg = to_hsotg(gadget);
3015         int ret;
3016 
3017         if (!hsotg) {
3018                 pr_err("%s: called with no device\n", __func__);
3019                 return -ENODEV;
3020         }
3021 
3022         if (!driver) {
3023                 dev_err(hsotg->dev, "%s: no driver\n", __func__);
3024                 return -EINVAL;
3025         }
3026 
3027         if (driver->max_speed < USB_SPEED_FULL)
3028                 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
3029 
3030         if (!driver->setup) {
3031                 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3032                 return -EINVAL;
3033         }
3034 
3035         WARN_ON(hsotg->driver);
3036 
3037         driver->driver.bus = NULL;
3038         hsotg->driver = driver;
3039         hsotg->gadget.dev.of_node = hsotg->dev->of_node;
3040         hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3041 
3042         ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3043                                     hsotg->supplies);
3044         if (ret) {
3045                 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3046                 goto err;
3047         }
3048 
3049         hsotg->last_rst = jiffies;
3050         dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
3051         return 0;
3052 
3053 err:
3054         hsotg->driver = NULL;
3055         return ret;
3056 }
3057 
3058 /**
3059  * s3c_hsotg_udc_stop - stop the udc
3060  * @gadget: The usb gadget state
3061  * @driver: The usb gadget driver
3062  *
3063  * Stop udc hw block and stay tunned for future transmissions
3064  */
3065 static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
3066                           struct usb_gadget_driver *driver)
3067 {
3068         struct s3c_hsotg *hsotg = to_hsotg(gadget);
3069         unsigned long flags = 0;
3070         int ep;
3071 
3072         if (!hsotg)
3073                 return -ENODEV;
3074 
3075         /* all endpoints should be shutdown */
3076         for (ep = 0; ep < hsotg->num_of_eps; ep++)
3077                 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
3078 
3079         spin_lock_irqsave(&hsotg->lock, flags);
3080 
3081         s3c_hsotg_phy_disable(hsotg);
3082 
3083         if (!driver)
3084                 hsotg->driver = NULL;
3085 
3086         hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3087 
3088         spin_unlock_irqrestore(&hsotg->lock, flags);
3089 
3090         regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
3091 
3092         return 0;
3093 }
3094 
3095 /**
3096  * s3c_hsotg_gadget_getframe - read the frame number
3097  * @gadget: The usb gadget state
3098  *
3099  * Read the {micro} frame number
3100  */
3101 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
3102 {
3103         return s3c_hsotg_read_frameno(to_hsotg(gadget));
3104 }
3105 
3106 /**
3107  * s3c_hsotg_pullup - connect/disconnect the USB PHY
3108  * @gadget: The usb gadget state
3109  * @is_on: Current state of the USB PHY
3110  *
3111  * Connect/Disconnect the USB PHY pullup
3112  */
3113 static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3114 {
3115         struct s3c_hsotg *hsotg = to_hsotg(gadget);
3116         unsigned long flags = 0;
3117 
3118         dev_dbg(hsotg->dev, "%s: is_in: %d\n", __func__, is_on);
3119 
3120         spin_lock_irqsave(&hsotg->lock, flags);
3121         if (is_on) {
3122                 s3c_hsotg_phy_enable(hsotg);
3123                 s3c_hsotg_core_init(hsotg);
3124         } else {
3125                 s3c_hsotg_disconnect(hsotg);
3126                 s3c_hsotg_phy_disable(hsotg);
3127         }
3128 
3129         hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3130         spin_unlock_irqrestore(&hsotg->lock, flags);
3131 
3132         return 0;
3133 }
3134 
3135 static const struct usb_gadget_ops s3c_hsotg_gadget_ops = {
3136         .get_frame      = s3c_hsotg_gadget_getframe,
3137         .udc_start              = s3c_hsotg_udc_start,
3138         .udc_stop               = s3c_hsotg_udc_stop,
3139         .pullup                 = s3c_hsotg_pullup,
3140 };
3141 
3142 /**
3143  * s3c_hsotg_initep - initialise a single endpoint
3144  * @hsotg: The device state.
3145  * @hs_ep: The endpoint to be initialised.
3146  * @epnum: The endpoint number
3147  *
3148  * Initialise the given endpoint (as part of the probe and device state
3149  * creation) to give to the gadget driver. Setup the endpoint name, any
3150  * direction information and other state that may be required.
3151  */
3152 static void s3c_hsotg_initep(struct s3c_hsotg *hsotg,
3153                                        struct s3c_hsotg_ep *hs_ep,
3154                                        int epnum)
3155 {
3156         u32 ptxfifo;
3157         char *dir;
3158 
3159         if (epnum == 0)
3160                 dir = "";
3161         else if ((epnum % 2) == 0) {
3162                 dir = "out";
3163         } else {
3164                 dir = "in";
3165                 hs_ep->dir_in = 1;
3166         }
3167 
3168         hs_ep->index = epnum;
3169 
3170         snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3171 
3172         INIT_LIST_HEAD(&hs_ep->queue);
3173         INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3174 
3175         /* add to the list of endpoints known by the gadget driver */
3176         if (epnum)
3177                 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3178 
3179         hs_ep->parent = hsotg;
3180         hs_ep->ep.name = hs_ep->name;
3181         usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3182         hs_ep->ep.ops = &s3c_hsotg_ep_ops;
3183 
3184         /*
3185          * Read the FIFO size for the Periodic TX FIFO, even if we're
3186          * an OUT endpoint, we may as well do this if in future the
3187          * code is changed to make each endpoint's direction changeable.
3188          */
3189 
3190         ptxfifo = readl(hsotg->regs + DPTXFSIZn(epnum));
3191         hs_ep->fifo_size = DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
3192 
3193         /*
3194          * if we're using dma, we need to set the next-endpoint pointer
3195          * to be something valid.
3196          */
3197 
3198         if (using_dma(hsotg)) {
3199                 u32 next = DxEPCTL_NextEp((epnum + 1) % 15);
3200                 writel(next, hsotg->regs + DIEPCTL(epnum));
3201                 writel(next, hsotg->regs + DOEPCTL(epnum));
3202         }
3203 }
3204 
3205 /**
3206  * s3c_hsotg_hw_cfg - read HW configuration registers
3207  * @param: The device state
3208  *
3209  * Read the USB core HW configuration registers
3210  */
3211 static void s3c_hsotg_hw_cfg(struct s3c_hsotg *hsotg)
3212 {
3213         u32 cfg2, cfg4;
3214         /* check hardware configuration */
3215 
3216         cfg2 = readl(hsotg->regs + 0x48);
3217         hsotg->num_of_eps = (cfg2 >> 10) & 0xF;
3218 
3219         dev_info(hsotg->dev, "EPs:%d\n", hsotg->num_of_eps);
3220 
3221         cfg4 = readl(hsotg->regs + 0x50);
3222         hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
3223 
3224         dev_info(hsotg->dev, "%s fifos\n",
3225                  hsotg->dedicated_fifos ? "dedicated" : "shared");
3226 }
3227 
3228 /**
3229  * s3c_hsotg_dump - dump state of the udc
3230  * @param: The device state
3231  */
3232 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
3233 {
3234 #ifdef DEBUG
3235         struct device *dev = hsotg->dev;
3236         void __iomem *regs = hsotg->regs;
3237         u32 val;
3238         int idx;
3239 
3240         dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3241                  readl(regs + DCFG), readl(regs + DCTL),
3242                  readl(regs + DIEPMSK));
3243 
3244         dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3245                  readl(regs + GAHBCFG), readl(regs + 0x44));
3246 
3247         dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3248                  readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
3249 
3250         /* show periodic fifo settings */
3251 
3252         for (idx = 1; idx <= 15; idx++) {
3253                 val = readl(regs + DPTXFSIZn(idx));
3254                 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3255                          val >> DPTXFSIZn_DPTxFSize_SHIFT,
3256                          val & DPTXFSIZn_DPTxFStAddr_MASK);
3257         }
3258 
3259         for (idx = 0; idx < 15; idx++) {
3260                 dev_info(dev,
3261                          "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3262                          readl(regs + DIEPCTL(idx)),
3263                          readl(regs + DIEPTSIZ(idx)),
3264                          readl(regs + DIEPDMA(idx)));
3265 
3266                 val = readl(regs + DOEPCTL(idx));
3267                 dev_info(dev,
3268                          "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3269                          idx, readl(regs + DOEPCTL(idx)),
3270                          readl(regs + DOEPTSIZ(idx)),
3271                          readl(regs + DOEPDMA(idx)));
3272 
3273         }
3274 
3275         dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3276                  readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
3277 #endif
3278 }
3279 
3280 /**
3281  * state_show - debugfs: show overall driver and device state.
3282  * @seq: The seq file to write to.
3283  * @v: Unused parameter.
3284  *
3285  * This debugfs entry shows the overall state of the hardware and
3286  * some general information about each of the endpoints available
3287  * to the system.
3288  */
3289 static int state_show(struct seq_file *seq, void *v)
3290 {
3291         struct s3c_hsotg *hsotg = seq->private;
3292         void __iomem *regs = hsotg->regs;
3293         int idx;
3294 
3295         seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3296                  readl(regs + DCFG),
3297                  readl(regs + DCTL),
3298                  readl(regs + DSTS));
3299 
3300         seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3301                    readl(regs + DIEPMSK), readl(regs + DOEPMSK));
3302 
3303         seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3304                    readl(regs + GINTMSK),
3305                    readl(regs + GINTSTS));
3306 
3307         seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3308                    readl(regs + DAINTMSK),
3309                    readl(regs + DAINT));
3310 
3311         seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3312                    readl(regs + GNPTXSTS),
3313                    readl(regs + GRXSTSR));
3314 
3315         seq_puts(seq, "\nEndpoint status:\n");
3316 
3317         for (idx = 0; idx < 15; idx++) {
3318                 u32 in, out;
3319 
3320                 in = readl(regs + DIEPCTL(idx));
3321                 out = readl(regs + DOEPCTL(idx));
3322 
3323                 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3324                            idx, in, out);
3325 
3326                 in = readl(regs + DIEPTSIZ(idx));
3327                 out = readl(regs + DOEPTSIZ(idx));
3328 
3329                 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3330                            in, out);
3331 
3332                 seq_puts(seq, "\n");
3333         }
3334 
3335         return 0;
3336 }
3337 
3338 static int state_open(struct inode *inode, struct file *file)
3339 {
3340         return single_open(file, state_show, inode->i_private);
3341 }
3342 
3343 static const struct file_operations state_fops = {
3344         .owner          = THIS_MODULE,
3345         .open           = state_open,
3346         .read           = seq_read,
3347         .llseek         = seq_lseek,
3348         .release        = single_release,
3349 };
3350 
3351 /**
3352  * fifo_show - debugfs: show the fifo information
3353  * @seq: The seq_file to write data to.
3354  * @v: Unused parameter.
3355  *
3356  * Show the FIFO information for the overall fifo and all the
3357  * periodic transmission FIFOs.
3358  */
3359 static int fifo_show(struct seq_file *seq, void *v)
3360 {
3361         struct s3c_hsotg *hsotg = seq->private;
3362         void __iomem *regs = hsotg->regs;
3363         u32 val;
3364         int idx;
3365 
3366         seq_puts(seq, "Non-periodic FIFOs:\n");
3367         seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
3368 
3369         val = readl(regs + GNPTXFSIZ);
3370         seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3371                    val >> GNPTXFSIZ_NPTxFDep_SHIFT,
3372                    val & GNPTXFSIZ_NPTxFStAddr_MASK);
3373 
3374         seq_puts(seq, "\nPeriodic TXFIFOs:\n");
3375 
3376         for (idx = 1; idx <= 15; idx++) {
3377                 val = readl(regs + DPTXFSIZn(idx));
3378 
3379                 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3380                            val >> DPTXFSIZn_DPTxFSize_SHIFT,
3381                            val & DPTXFSIZn_DPTxFStAddr_MASK);
3382         }
3383 
3384         return 0;
3385 }
3386 
3387 static int fifo_open(struct inode *inode, struct file *file)
3388 {
3389         return single_open(file, fifo_show, inode->i_private);
3390 }
3391 
3392 static const struct file_operations fifo_fops = {
3393         .owner          = THIS_MODULE,
3394         .open           = fifo_open,
3395         .read           = seq_read,
3396         .llseek         = seq_lseek,
3397         .release        = single_release,
3398 };
3399 
3400 
3401 static const char *decode_direction(int is_in)
3402 {
3403         return is_in ? "in" : "out";
3404 }
3405 
3406 /**
3407  * ep_show - debugfs: show the state of an endpoint.
3408  * @seq: The seq_file to write data to.
3409  * @v: Unused parameter.
3410  *
3411  * This debugfs entry shows the state of the given endpoint (one is
3412  * registered for each available).
3413  */
3414 static int ep_show(struct seq_file *seq, void *v)
3415 {
3416         struct s3c_hsotg_ep *ep = seq->private;
3417         struct s3c_hsotg *hsotg = ep->parent;
3418         struct s3c_hsotg_req *req;
3419         void __iomem *regs = hsotg->regs;
3420         int index = ep->index;
3421         int show_limit = 15;
3422         unsigned long flags;
3423 
3424         seq_printf(seq, "Endpoint index %d, named %s,  dir %s:\n",
3425                    ep->index, ep->ep.name, decode_direction(ep->dir_in));
3426 
3427         /* first show the register state */
3428 
3429         seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3430                    readl(regs + DIEPCTL(index)),
3431                    readl(regs + DOEPCTL(index)));
3432 
3433         seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3434                    readl(regs + DIEPDMA(index)),
3435                    readl(regs + DOEPDMA(index)));
3436 
3437         seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3438                    readl(regs + DIEPINT(index)),
3439                    readl(regs + DOEPINT(index)));
3440 
3441         seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3442                    readl(regs + DIEPTSIZ(index)),
3443                    readl(regs + DOEPTSIZ(index)));
3444 
3445         seq_puts(seq, "\n");
3446         seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3447         seq_printf(seq, "total_data=%ld\n", ep->total_data);
3448 
3449         seq_printf(seq, "request list (%p,%p):\n",
3450                    ep->queue.next, ep->queue.prev);
3451 
3452         spin_lock_irqsave(&hsotg->lock, flags);
3453 
3454         list_for_each_entry(req, &ep->queue, queue) {
3455                 if (--show_limit < 0) {
3456                         seq_puts(seq, "not showing more requests...\n");
3457                         break;
3458                 }
3459 
3460                 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3461                            req == ep->req ? '*' : ' ',
3462                            req, req->req.length, req->req.buf);
3463                 seq_printf(seq, "%d done, res %d\n",
3464                            req->req.actual, req->req.status);
3465         }
3466 
3467         spin_unlock_irqrestore(&hsotg->lock, flags);
3468 
3469         return 0;
3470 }
3471 
3472 static int ep_open(struct inode *inode, struct file *file)
3473 {
3474         return single_open(file, ep_show, inode->i_private);
3475 }
3476 
3477 static const struct file_operations ep_fops = {
3478         .owner          = THIS_MODULE,
3479         .open           = ep_open,
3480         .read           = seq_read,
3481         .llseek         = seq_lseek,
3482         .release        = single_release,
3483 };
3484 
3485 /**
3486  * s3c_hsotg_create_debug - create debugfs directory and files
3487  * @hsotg: The driver state
3488  *
3489  * Create the debugfs files to allow the user to get information
3490  * about the state of the system. The directory name is created
3491  * with the same name as the device itself, in case we end up
3492  * with multiple blocks in future systems.
3493  */
3494 static void s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3495 {
3496         struct dentry *root;
3497         unsigned epidx;
3498 
3499         root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3500         hsotg->debug_root = root;
3501         if (IS_ERR(root)) {
3502                 dev_err(hsotg->dev, "cannot create debug root\n");
3503                 return;
3504         }
3505 
3506         /* create general state file */
3507 
3508         hsotg->debug_file = debugfs_create_file("state", 0444, root,
3509                                                 hsotg, &state_fops);
3510 
3511         if (IS_ERR(hsotg->debug_file))
3512                 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3513 
3514         hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3515                                                 hsotg, &fifo_fops);
3516 
3517         if (IS_ERR(hsotg->debug_fifo))
3518                 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3519 
3520         /* create one file for each endpoint */
3521 
3522         for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3523                 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3524 
3525                 ep->debugfs = debugfs_create_file(ep->name, 0444,
3526                                                   root, ep, &ep_fops);
3527 
3528                 if (IS_ERR(ep->debugfs))
3529                         dev_err(hsotg->dev, "failed to create %s debug file\n",
3530                                 ep->name);
3531         }
3532 }
3533 
3534 /**
3535  * s3c_hsotg_delete_debug - cleanup debugfs entries
3536  * @hsotg: The driver state
3537  *
3538  * Cleanup (remove) the debugfs files for use on module exit.
3539  */
3540 static void s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3541 {
3542         unsigned epidx;
3543 
3544         for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3545                 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3546                 debugfs_remove(ep->debugfs);
3547         }
3548 
3549         debugfs_remove(hsotg->debug_file);
3550         debugfs_remove(hsotg->debug_fifo);
3551         debugfs_remove(hsotg->debug_root);
3552 }
3553 
3554 /**
3555  * s3c_hsotg_probe - probe function for hsotg driver
3556  * @pdev: The platform information for the driver
3557  */
3558 
3559 static int s3c_hsotg_probe(struct platform_device *pdev)
3560 {
3561         struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev);
3562         struct phy *phy;
3563         struct usb_phy *uphy;
3564         struct device *dev = &pdev->dev;
3565         struct s3c_hsotg_ep *eps;
3566         struct s3c_hsotg *hsotg;
3567         struct resource *res;
3568         int epnum;
3569         int ret;
3570         int i;
3571 
3572         hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
3573         if (!hsotg) {
3574                 dev_err(dev, "cannot get memory\n");
3575                 return -ENOMEM;
3576         }
3577 
3578         /*
3579          * Attempt to find a generic PHY, then look for an old style
3580          * USB PHY, finally fall back to pdata
3581          */
3582         phy = devm_phy_get(&pdev->dev, "usb2-phy");
3583         if (IS_ERR(phy)) {
3584                 uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
3585                 if (IS_ERR(uphy)) {
3586                         /* Fallback for pdata */
3587                         plat = dev_get_platdata(&pdev->dev);
3588                         if (!plat) {
3589                                 dev_err(&pdev->dev,
3590                                 "no platform data or transceiver defined\n");
3591                                 return -EPROBE_DEFER;
3592                         }
3593                         hsotg->plat = plat;
3594                 } else
3595                         hsotg->uphy = uphy;
3596         } else
3597                 hsotg->phy = phy;
3598 
3599         hsotg->dev = dev;
3600 
3601         hsotg->clk = devm_clk_get(&pdev->dev, "otg");
3602         if (IS_ERR(hsotg->clk)) {
3603                 dev_err(dev, "cannot get otg clock\n");
3604                 return PTR_ERR(hsotg->clk);
3605         }
3606 
3607         platform_set_drvdata(pdev, hsotg);
3608 
3609         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3610 
3611         hsotg->regs = devm_ioremap_resource(&pdev->dev, res);
3612         if (IS_ERR(hsotg->regs)) {
3613                 ret = PTR_ERR(hsotg->regs);
3614                 goto err_clk;
3615         }
3616 
3617         ret = platform_get_irq(pdev, 0);
3618         if (ret < 0) {
3619                 dev_err(dev, "cannot find IRQ\n");
3620                 goto err_clk;
3621         }
3622 
3623         spin_lock_init(&hsotg->lock);
3624 
3625         hsotg->irq = ret;
3626 
3627         ret = devm_request_irq(&pdev->dev, hsotg->irq, s3c_hsotg_irq, 0,
3628                                 dev_name(dev), hsotg);
3629         if (ret < 0) {
3630                 dev_err(dev, "cannot claim IRQ\n");
3631                 goto err_clk;
3632         }
3633 
3634         dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3635 
3636         hsotg->gadget.max_speed = USB_SPEED_HIGH;
3637         hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3638         hsotg->gadget.name = dev_name(dev);
3639 
3640         /* reset the system */
3641 
3642         clk_prepare_enable(hsotg->clk);
3643 
3644         /* regulators */
3645 
3646         for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3647                 hsotg->supplies[i].supply = s3c_hsotg_supply_names[i];
3648 
3649         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
3650                                  hsotg->supplies);
3651         if (ret) {
3652                 dev_err(dev, "failed to request supplies: %d\n", ret);
3653                 goto err_clk;
3654         }
3655 
3656         ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3657                                     hsotg->supplies);
3658 
3659         if (ret) {
3660                 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3661                 goto err_supplies;
3662         }
3663 
3664         /* Set default UTMI width */
3665         hsotg->phyif = GUSBCFG_PHYIf16;
3666 
3667         /*
3668          * If using the generic PHY framework, check if the PHY bus
3669          * width is 8-bit and set the phyif appropriately.
3670          */
3671         if (hsotg->phy && (phy_get_bus_width(phy) == 8))
3672                 hsotg->phyif = GUSBCFG_PHYIf8;
3673 
3674         if (hsotg->phy)
3675                 phy_init(hsotg->phy);
3676 
3677         /* usb phy enable */
3678         s3c_hsotg_phy_enable(hsotg);
3679 
3680         s3c_hsotg_corereset(hsotg);
3681         s3c_hsotg_init(hsotg);
3682         s3c_hsotg_hw_cfg(hsotg);
3683 
3684         /* hsotg->num_of_eps holds number of EPs other than ep0 */
3685 
3686         if (hsotg->num_of_eps == 0) {
3687                 dev_err(dev, "wrong number of EPs (zero)\n");
3688                 ret = -EINVAL;
3689                 goto err_supplies;
3690         }
3691 
3692         eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep),
3693                       GFP_KERNEL);
3694         if (!eps) {
3695                 dev_err(dev, "cannot get memory\n");
3696                 ret = -ENOMEM;
3697                 goto err_supplies;
3698         }
3699 
3700         hsotg->eps = eps;
3701 
3702         /* setup endpoint information */
3703 
3704         INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3705         hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3706 
3707         /* allocate EP0 request */
3708 
3709         hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3710                                                      GFP_KERNEL);
3711         if (!hsotg->ctrl_req) {
3712                 dev_err(dev, "failed to allocate ctrl req\n");
3713                 ret = -ENOMEM;
3714                 goto err_ep_mem;
3715         }
3716 
3717         /* initialise the endpoints now the core has been initialised */
3718         for (epnum = 0; epnum < hsotg->num_of_eps; epnum++)
3719                 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3720 
3721         /* disable power and clock */
3722 
3723         ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3724                                     hsotg->supplies);
3725         if (ret) {
3726                 dev_err(hsotg->dev, "failed to disable supplies: %d\n", ret);
3727                 goto err_ep_mem;
3728         }
3729 
3730         s3c_hsotg_phy_disable(hsotg);
3731 
3732         ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget);
3733         if (ret)
3734                 goto err_ep_mem;
3735 
3736         s3c_hsotg_create_debug(hsotg);
3737 
3738         s3c_hsotg_dump(hsotg);
3739 
3740         return 0;
3741 
3742 err_ep_mem:
3743         kfree(eps);
3744 err_supplies:
3745         s3c_hsotg_phy_disable(hsotg);
3746 err_clk:
3747         clk_disable_unprepare(hsotg->clk);
3748 
3749         return ret;
3750 }
3751 
3752 /**
3753  * s3c_hsotg_remove - remove function for hsotg driver
3754  * @pdev: The platform information for the driver
3755  */
3756 static int s3c_hsotg_remove(struct platform_device *pdev)
3757 {
3758         struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3759 
3760         usb_del_gadget_udc(&hsotg->gadget);
3761 
3762         s3c_hsotg_delete_debug(hsotg);
3763 
3764         if (hsotg->driver) {
3765                 /* should have been done already by driver model core */
3766                 usb_gadget_unregister_driver(hsotg->driver);
3767         }
3768 
3769         s3c_hsotg_phy_disable(hsotg);
3770         if (hsotg->phy)
3771                 phy_exit(hsotg->phy);
3772         clk_disable_unprepare(hsotg->clk);
3773 
3774         return 0;
3775 }
3776 
3777 static int s3c_hsotg_suspend(struct platform_device *pdev, pm_message_t state)
3778 {
3779         struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3780         unsigned long flags;
3781         int ret = 0;
3782 
3783         if (hsotg->driver)
3784                 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3785                          hsotg->driver->driver.name);
3786 
3787         spin_lock_irqsave(&hsotg->lock, flags);
3788         s3c_hsotg_disconnect(hsotg);
3789         s3c_hsotg_phy_disable(hsotg);
3790         hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3791         spin_unlock_irqrestore(&hsotg->lock, flags);
3792 
3793         if (hsotg->driver) {
3794                 int ep;
3795                 for (ep = 0; ep < hsotg->num_of_eps; ep++)
3796                         s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
3797 
3798                 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3799                                              hsotg->supplies);
3800         }
3801 
3802         return ret;
3803 }
3804 
3805 static int s3c_hsotg_resume(struct platform_device *pdev)
3806 {
3807         struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3808         unsigned long flags;
3809         int ret = 0;
3810 
3811         if (hsotg->driver) {
3812                 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3813                          hsotg->driver->driver.name);
3814                 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3815                                       hsotg->supplies);
3816         }
3817 
3818         spin_lock_irqsave(&hsotg->lock, flags);
3819         hsotg->last_rst = jiffies;
3820         s3c_hsotg_phy_enable(hsotg);
3821         s3c_hsotg_core_init(hsotg);
3822         spin_unlock_irqrestore(&hsotg->lock, flags);
3823 
3824         return ret;
3825 }
3826 
3827 #ifdef CONFIG_OF
3828 static const struct of_device_id s3c_hsotg_of_ids[] = {
3829         { .compatible = "samsung,s3c6400-hsotg", },
3830         { .compatible = "snps,dwc2", },
3831         { /* sentinel */ }
3832 };
3833 MODULE_DEVICE_TABLE(of, s3c_hsotg_of_ids);
3834 #endif
3835 
3836 static struct platform_driver s3c_hsotg_driver = {
3837         .driver         = {
3838                 .name   = "s3c-hsotg",
3839                 .owner  = THIS_MODULE,
3840                 .of_match_table = of_match_ptr(s3c_hsotg_of_ids),
3841         },
3842         .probe          = s3c_hsotg_probe,
3843         .remove         = s3c_hsotg_remove,
3844         .suspend        = s3c_hsotg_suspend,
3845         .resume         = s3c_hsotg_resume,
3846 };
3847 
3848 module_platform_driver(s3c_hsotg_driver);
3849 
3850 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3851 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3852 MODULE_LICENSE("GPL");
3853 MODULE_ALIAS("platform:s3c-hsotg");
3854 

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