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Linux/drivers/usb/gadget/fsl_udc_core.c

  1 /*
  2  * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
  3  * All rights reserved.
  4  *
  5  * Author: Li Yang <leoli@freescale.com>
  6  *         Jiang Bo <tanya.jiang@freescale.com>
  7  *
  8  * Description:
  9  * Freescale high-speed USB SOC DR module device controller driver.
 10  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
 11  * The driver is previously named as mpc_udc.  Based on bare board
 12  * code from Dave Liu and Shlomi Gridish.
 13  *
 14  * This program is free software; you can redistribute  it and/or modify it
 15  * under  the terms of  the GNU General  Public License as published by the
 16  * Free Software Foundation;  either version 2 of the  License, or (at your
 17  * option) any later version.
 18  */
 19 
 20 #undef VERBOSE
 21 
 22 #include <linux/module.h>
 23 #include <linux/kernel.h>
 24 #include <linux/ioport.h>
 25 #include <linux/types.h>
 26 #include <linux/errno.h>
 27 #include <linux/err.h>
 28 #include <linux/slab.h>
 29 #include <linux/init.h>
 30 #include <linux/list.h>
 31 #include <linux/interrupt.h>
 32 #include <linux/proc_fs.h>
 33 #include <linux/mm.h>
 34 #include <linux/moduleparam.h>
 35 #include <linux/device.h>
 36 #include <linux/usb/ch9.h>
 37 #include <linux/usb/gadget.h>
 38 #include <linux/usb/otg.h>
 39 #include <linux/dma-mapping.h>
 40 #include <linux/platform_device.h>
 41 #include <linux/fsl_devices.h>
 42 #include <linux/dmapool.h>
 43 #include <linux/delay.h>
 44 #include <linux/of_device.h>
 45 
 46 #include <asm/byteorder.h>
 47 #include <asm/io.h>
 48 #include <asm/unaligned.h>
 49 #include <asm/dma.h>
 50 
 51 #include "fsl_usb2_udc.h"
 52 
 53 #define DRIVER_DESC     "Freescale High-Speed USB SOC Device Controller driver"
 54 #define DRIVER_AUTHOR   "Li Yang/Jiang Bo"
 55 #define DRIVER_VERSION  "Apr 20, 2007"
 56 
 57 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
 58 
 59 static const char driver_name[] = "fsl-usb2-udc";
 60 static const char driver_desc[] = DRIVER_DESC;
 61 
 62 static struct usb_dr_device *dr_regs;
 63 
 64 static struct usb_sys_interface *usb_sys_regs;
 65 
 66 /* it is initialized in probe()  */
 67 static struct fsl_udc *udc_controller = NULL;
 68 
 69 static const struct usb_endpoint_descriptor
 70 fsl_ep0_desc = {
 71         .bLength =              USB_DT_ENDPOINT_SIZE,
 72         .bDescriptorType =      USB_DT_ENDPOINT,
 73         .bEndpointAddress =     0,
 74         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
 75         .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
 76 };
 77 
 78 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
 79 
 80 #ifdef CONFIG_PPC32
 81 /*
 82  * On some SoCs, the USB controller registers can be big or little endian,
 83  * depending on the version of the chip. In order to be able to run the
 84  * same kernel binary on 2 different versions of an SoC, the BE/LE decision
 85  * must be made at run time. _fsl_readl and fsl_writel are pointers to the
 86  * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
 87  * call through those pointers. Platform code for SoCs that have BE USB
 88  * registers should set pdata->big_endian_mmio flag.
 89  *
 90  * This also applies to controller-to-cpu accessors for the USB descriptors,
 91  * since their endianness is also SoC dependant. Platform code for SoCs that
 92  * have BE USB descriptors should set pdata->big_endian_desc flag.
 93  */
 94 static u32 _fsl_readl_be(const unsigned __iomem *p)
 95 {
 96         return in_be32(p);
 97 }
 98 
 99 static u32 _fsl_readl_le(const unsigned __iomem *p)
100 {
101         return in_le32(p);
102 }
103 
104 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
105 {
106         out_be32(p, v);
107 }
108 
109 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
110 {
111         out_le32(p, v);
112 }
113 
114 static u32 (*_fsl_readl)(const unsigned __iomem *p);
115 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
116 
117 #define fsl_readl(p)            (*_fsl_readl)((p))
118 #define fsl_writel(v, p)        (*_fsl_writel)((v), (p))
119 
120 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
121 {
122         if (pdata->big_endian_mmio) {
123                 _fsl_readl = _fsl_readl_be;
124                 _fsl_writel = _fsl_writel_be;
125         } else {
126                 _fsl_readl = _fsl_readl_le;
127                 _fsl_writel = _fsl_writel_le;
128         }
129 }
130 
131 static inline u32 cpu_to_hc32(const u32 x)
132 {
133         return udc_controller->pdata->big_endian_desc
134                 ? (__force u32)cpu_to_be32(x)
135                 : (__force u32)cpu_to_le32(x);
136 }
137 
138 static inline u32 hc32_to_cpu(const u32 x)
139 {
140         return udc_controller->pdata->big_endian_desc
141                 ? be32_to_cpu((__force __be32)x)
142                 : le32_to_cpu((__force __le32)x);
143 }
144 #else /* !CONFIG_PPC32 */
145 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
146 
147 #define fsl_readl(addr)         readl(addr)
148 #define fsl_writel(val32, addr) writel(val32, addr)
149 #define cpu_to_hc32(x)          cpu_to_le32(x)
150 #define hc32_to_cpu(x)          le32_to_cpu(x)
151 #endif /* CONFIG_PPC32 */
152 
153 /********************************************************************
154  *      Internal Used Function
155 ********************************************************************/
156 /*-----------------------------------------------------------------
157  * done() - retire a request; caller blocked irqs
158  * @status : request status to be set, only works when
159  *      request is still in progress.
160  *--------------------------------------------------------------*/
161 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
162 {
163         struct fsl_udc *udc = NULL;
164         unsigned char stopped = ep->stopped;
165         struct ep_td_struct *curr_td, *next_td;
166         int j;
167 
168         udc = (struct fsl_udc *)ep->udc;
169         /* Removed the req from fsl_ep->queue */
170         list_del_init(&req->queue);
171 
172         /* req.status should be set as -EINPROGRESS in ep_queue() */
173         if (req->req.status == -EINPROGRESS)
174                 req->req.status = status;
175         else
176                 status = req->req.status;
177 
178         /* Free dtd for the request */
179         next_td = req->head;
180         for (j = 0; j < req->dtd_count; j++) {
181                 curr_td = next_td;
182                 if (j != req->dtd_count - 1) {
183                         next_td = curr_td->next_td_virt;
184                 }
185                 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
186         }
187 
188         usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
189 
190         if (status && (status != -ESHUTDOWN))
191                 VDBG("complete %s req %p stat %d len %u/%u",
192                         ep->ep.name, &req->req, status,
193                         req->req.actual, req->req.length);
194 
195         ep->stopped = 1;
196 
197         spin_unlock(&ep->udc->lock);
198         /* complete() is from gadget layer,
199          * eg fsg->bulk_in_complete() */
200         if (req->req.complete)
201                 req->req.complete(&ep->ep, &req->req);
202 
203         spin_lock(&ep->udc->lock);
204         ep->stopped = stopped;
205 }
206 
207 /*-----------------------------------------------------------------
208  * nuke(): delete all requests related to this ep
209  * called with spinlock held
210  *--------------------------------------------------------------*/
211 static void nuke(struct fsl_ep *ep, int status)
212 {
213         ep->stopped = 1;
214 
215         /* Flush fifo */
216         fsl_ep_fifo_flush(&ep->ep);
217 
218         /* Whether this eq has request linked */
219         while (!list_empty(&ep->queue)) {
220                 struct fsl_req *req = NULL;
221 
222                 req = list_entry(ep->queue.next, struct fsl_req, queue);
223                 done(ep, req, status);
224         }
225 }
226 
227 /*------------------------------------------------------------------
228         Internal Hardware related function
229  ------------------------------------------------------------------*/
230 
231 static int dr_controller_setup(struct fsl_udc *udc)
232 {
233         unsigned int tmp, portctrl, ep_num;
234         unsigned int max_no_of_ep;
235         unsigned int ctrl;
236         unsigned long timeout;
237 
238 #define FSL_UDC_RESET_TIMEOUT 1000
239 
240         /* Config PHY interface */
241         portctrl = fsl_readl(&dr_regs->portsc1);
242         portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
243         switch (udc->phy_mode) {
244         case FSL_USB2_PHY_ULPI:
245                 if (udc->pdata->have_sysif_regs) {
246                         if (udc->pdata->controller_ver) {
247                                 /* controller version 1.6 or above */
248                                 ctrl = __raw_readl(&usb_sys_regs->control);
249                                 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
250                                 ctrl |= USB_CTRL_USB_EN;
251                                 __raw_writel(ctrl, &usb_sys_regs->control);
252                         }
253                 }
254                 portctrl |= PORTSCX_PTS_ULPI;
255                 break;
256         case FSL_USB2_PHY_UTMI_WIDE:
257                 portctrl |= PORTSCX_PTW_16BIT;
258                 /* fall through */
259         case FSL_USB2_PHY_UTMI:
260                 if (udc->pdata->have_sysif_regs) {
261                         if (udc->pdata->controller_ver) {
262                                 /* controller version 1.6 or above */
263                                 ctrl = __raw_readl(&usb_sys_regs->control);
264                                 ctrl |= (USB_CTRL_UTMI_PHY_EN |
265                                         USB_CTRL_USB_EN);
266                                 __raw_writel(ctrl, &usb_sys_regs->control);
267                                 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
268                                         PHY CLK to become stable - 10ms*/
269                         }
270                 }
271                 portctrl |= PORTSCX_PTS_UTMI;
272                 break;
273         case FSL_USB2_PHY_SERIAL:
274                 portctrl |= PORTSCX_PTS_FSLS;
275                 break;
276         default:
277                 return -EINVAL;
278         }
279         fsl_writel(portctrl, &dr_regs->portsc1);
280 
281         /* Stop and reset the usb controller */
282         tmp = fsl_readl(&dr_regs->usbcmd);
283         tmp &= ~USB_CMD_RUN_STOP;
284         fsl_writel(tmp, &dr_regs->usbcmd);
285 
286         tmp = fsl_readl(&dr_regs->usbcmd);
287         tmp |= USB_CMD_CTRL_RESET;
288         fsl_writel(tmp, &dr_regs->usbcmd);
289 
290         /* Wait for reset to complete */
291         timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
292         while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
293                 if (time_after(jiffies, timeout)) {
294                         ERR("udc reset timeout!\n");
295                         return -ETIMEDOUT;
296                 }
297                 cpu_relax();
298         }
299 
300         /* Set the controller as device mode */
301         tmp = fsl_readl(&dr_regs->usbmode);
302         tmp &= ~USB_MODE_CTRL_MODE_MASK;        /* clear mode bits */
303         tmp |= USB_MODE_CTRL_MODE_DEVICE;
304         /* Disable Setup Lockout */
305         tmp |= USB_MODE_SETUP_LOCK_OFF;
306         if (udc->pdata->es)
307                 tmp |= USB_MODE_ES;
308         fsl_writel(tmp, &dr_regs->usbmode);
309 
310         /* Clear the setup status */
311         fsl_writel(0, &dr_regs->usbsts);
312 
313         tmp = udc->ep_qh_dma;
314         tmp &= USB_EP_LIST_ADDRESS_MASK;
315         fsl_writel(tmp, &dr_regs->endpointlistaddr);
316 
317         VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
318                 udc->ep_qh, (int)tmp,
319                 fsl_readl(&dr_regs->endpointlistaddr));
320 
321         max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
322         for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
323                 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
324                 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
325                 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
326                 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
327                 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
328         }
329         /* Config control enable i/o output, cpu endian register */
330 #ifndef CONFIG_ARCH_MXC
331         if (udc->pdata->have_sysif_regs) {
332                 ctrl = __raw_readl(&usb_sys_regs->control);
333                 ctrl |= USB_CTRL_IOENB;
334                 __raw_writel(ctrl, &usb_sys_regs->control);
335         }
336 #endif
337 
338 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
339         /* Turn on cache snooping hardware, since some PowerPC platforms
340          * wholly rely on hardware to deal with cache coherent. */
341 
342         if (udc->pdata->have_sysif_regs) {
343                 /* Setup Snooping for all the 4GB space */
344                 tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
345                 __raw_writel(tmp, &usb_sys_regs->snoop1);
346                 tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
347                 __raw_writel(tmp, &usb_sys_regs->snoop2);
348         }
349 #endif
350 
351         return 0;
352 }
353 
354 /* Enable DR irq and set controller to run state */
355 static void dr_controller_run(struct fsl_udc *udc)
356 {
357         u32 temp;
358 
359         /* Enable DR irq reg */
360         temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
361                 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
362                 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
363 
364         fsl_writel(temp, &dr_regs->usbintr);
365 
366         /* Clear stopped bit */
367         udc->stopped = 0;
368 
369         /* Set the controller as device mode */
370         temp = fsl_readl(&dr_regs->usbmode);
371         temp |= USB_MODE_CTRL_MODE_DEVICE;
372         fsl_writel(temp, &dr_regs->usbmode);
373 
374         /* Set controller to Run */
375         temp = fsl_readl(&dr_regs->usbcmd);
376         temp |= USB_CMD_RUN_STOP;
377         fsl_writel(temp, &dr_regs->usbcmd);
378 }
379 
380 static void dr_controller_stop(struct fsl_udc *udc)
381 {
382         unsigned int tmp;
383 
384         pr_debug("%s\n", __func__);
385 
386         /* if we're in OTG mode, and the Host is currently using the port,
387          * stop now and don't rip the controller out from under the
388          * ehci driver
389          */
390         if (udc->gadget.is_otg) {
391                 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
392                         pr_debug("udc: Leaving early\n");
393                         return;
394                 }
395         }
396 
397         /* disable all INTR */
398         fsl_writel(0, &dr_regs->usbintr);
399 
400         /* Set stopped bit for isr */
401         udc->stopped = 1;
402 
403         /* disable IO output */
404 /*      usb_sys_regs->control = 0; */
405 
406         /* set controller to Stop */
407         tmp = fsl_readl(&dr_regs->usbcmd);
408         tmp &= ~USB_CMD_RUN_STOP;
409         fsl_writel(tmp, &dr_regs->usbcmd);
410 }
411 
412 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
413                         unsigned char ep_type)
414 {
415         unsigned int tmp_epctrl = 0;
416 
417         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
418         if (dir) {
419                 if (ep_num)
420                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
421                 tmp_epctrl |= EPCTRL_TX_ENABLE;
422                 tmp_epctrl &= ~EPCTRL_TX_TYPE;
423                 tmp_epctrl |= ((unsigned int)(ep_type)
424                                 << EPCTRL_TX_EP_TYPE_SHIFT);
425         } else {
426                 if (ep_num)
427                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
428                 tmp_epctrl |= EPCTRL_RX_ENABLE;
429                 tmp_epctrl &= ~EPCTRL_RX_TYPE;
430                 tmp_epctrl |= ((unsigned int)(ep_type)
431                                 << EPCTRL_RX_EP_TYPE_SHIFT);
432         }
433 
434         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
435 }
436 
437 static void
438 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
439 {
440         u32 tmp_epctrl = 0;
441 
442         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
443 
444         if (value) {
445                 /* set the stall bit */
446                 if (dir)
447                         tmp_epctrl |= EPCTRL_TX_EP_STALL;
448                 else
449                         tmp_epctrl |= EPCTRL_RX_EP_STALL;
450         } else {
451                 /* clear the stall bit and reset data toggle */
452                 if (dir) {
453                         tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
454                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
455                 } else {
456                         tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
457                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
458                 }
459         }
460         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
461 }
462 
463 /* Get stall status of a specific ep
464    Return: 0: not stalled; 1:stalled */
465 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
466 {
467         u32 epctrl;
468 
469         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
470         if (dir)
471                 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
472         else
473                 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
474 }
475 
476 /********************************************************************
477         Internal Structure Build up functions
478 ********************************************************************/
479 
480 /*------------------------------------------------------------------
481 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
482  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
483  * @mult: Mult field
484  ------------------------------------------------------------------*/
485 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
486                 unsigned char dir, unsigned char ep_type,
487                 unsigned int max_pkt_len,
488                 unsigned int zlt, unsigned char mult)
489 {
490         struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
491         unsigned int tmp = 0;
492 
493         /* set the Endpoint Capabilites in QH */
494         switch (ep_type) {
495         case USB_ENDPOINT_XFER_CONTROL:
496                 /* Interrupt On Setup (IOS). for control ep  */
497                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
498                         | EP_QUEUE_HEAD_IOS;
499                 break;
500         case USB_ENDPOINT_XFER_ISOC:
501                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
502                         | (mult << EP_QUEUE_HEAD_MULT_POS);
503                 break;
504         case USB_ENDPOINT_XFER_BULK:
505         case USB_ENDPOINT_XFER_INT:
506                 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
507                 break;
508         default:
509                 VDBG("error ep type is %d", ep_type);
510                 return;
511         }
512         if (zlt)
513                 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
514 
515         p_QH->max_pkt_length = cpu_to_hc32(tmp);
516         p_QH->next_dtd_ptr = 1;
517         p_QH->size_ioc_int_sts = 0;
518 }
519 
520 /* Setup qh structure and ep register for ep0. */
521 static void ep0_setup(struct fsl_udc *udc)
522 {
523         /* the intialization of an ep includes: fields in QH, Regs,
524          * fsl_ep struct */
525         struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
526                         USB_MAX_CTRL_PAYLOAD, 0, 0);
527         struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
528                         USB_MAX_CTRL_PAYLOAD, 0, 0);
529         dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
530         dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
531 
532         return;
533 
534 }
535 
536 /***********************************************************************
537                 Endpoint Management Functions
538 ***********************************************************************/
539 
540 /*-------------------------------------------------------------------------
541  * when configurations are set, or when interface settings change
542  * for example the do_set_interface() in gadget layer,
543  * the driver will enable or disable the relevant endpoints
544  * ep0 doesn't use this routine. It is always enabled.
545 -------------------------------------------------------------------------*/
546 static int fsl_ep_enable(struct usb_ep *_ep,
547                 const struct usb_endpoint_descriptor *desc)
548 {
549         struct fsl_udc *udc = NULL;
550         struct fsl_ep *ep = NULL;
551         unsigned short max = 0;
552         unsigned char mult = 0, zlt;
553         int retval = -EINVAL;
554         unsigned long flags = 0;
555 
556         ep = container_of(_ep, struct fsl_ep, ep);
557 
558         /* catch various bogus parameters */
559         if (!_ep || !desc
560                         || (desc->bDescriptorType != USB_DT_ENDPOINT))
561                 return -EINVAL;
562 
563         udc = ep->udc;
564 
565         if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
566                 return -ESHUTDOWN;
567 
568         max = usb_endpoint_maxp(desc);
569 
570         /* Disable automatic zlp generation.  Driver is responsible to indicate
571          * explicitly through req->req.zero.  This is needed to enable multi-td
572          * request. */
573         zlt = 1;
574 
575         /* Assume the max packet size from gadget is always correct */
576         switch (desc->bmAttributes & 0x03) {
577         case USB_ENDPOINT_XFER_CONTROL:
578         case USB_ENDPOINT_XFER_BULK:
579         case USB_ENDPOINT_XFER_INT:
580                 /* mult = 0.  Execute N Transactions as demonstrated by
581                  * the USB variable length packet protocol where N is
582                  * computed using the Maximum Packet Length (dQH) and
583                  * the Total Bytes field (dTD) */
584                 mult = 0;
585                 break;
586         case USB_ENDPOINT_XFER_ISOC:
587                 /* Calculate transactions needed for high bandwidth iso */
588                 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
589                 max = max & 0x7ff;      /* bit 0~10 */
590                 /* 3 transactions at most */
591                 if (mult > 3)
592                         goto en_done;
593                 break;
594         default:
595                 goto en_done;
596         }
597 
598         spin_lock_irqsave(&udc->lock, flags);
599         ep->ep.maxpacket = max;
600         ep->ep.desc = desc;
601         ep->stopped = 0;
602 
603         /* Controller related setup */
604         /* Init EPx Queue Head (Ep Capabilites field in QH
605          * according to max, zlt, mult) */
606         struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
607                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
608                                         ?  USB_SEND : USB_RECV),
609                         (unsigned char) (desc->bmAttributes
610                                         & USB_ENDPOINT_XFERTYPE_MASK),
611                         max, zlt, mult);
612 
613         /* Init endpoint ctrl register */
614         dr_ep_setup((unsigned char) ep_index(ep),
615                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
616                                         ? USB_SEND : USB_RECV),
617                         (unsigned char) (desc->bmAttributes
618                                         & USB_ENDPOINT_XFERTYPE_MASK));
619 
620         spin_unlock_irqrestore(&udc->lock, flags);
621         retval = 0;
622 
623         VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
624                         ep->ep.desc->bEndpointAddress & 0x0f,
625                         (desc->bEndpointAddress & USB_DIR_IN)
626                                 ? "in" : "out", max);
627 en_done:
628         return retval;
629 }
630 
631 /*---------------------------------------------------------------------
632  * @ep : the ep being unconfigured. May not be ep0
633  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
634 *---------------------------------------------------------------------*/
635 static int fsl_ep_disable(struct usb_ep *_ep)
636 {
637         struct fsl_udc *udc = NULL;
638         struct fsl_ep *ep = NULL;
639         unsigned long flags = 0;
640         u32 epctrl;
641         int ep_num;
642 
643         ep = container_of(_ep, struct fsl_ep, ep);
644         if (!_ep || !ep->ep.desc) {
645                 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
646                 return -EINVAL;
647         }
648 
649         /* disable ep on controller */
650         ep_num = ep_index(ep);
651         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
652         if (ep_is_in(ep)) {
653                 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
654                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
655         } else {
656                 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
657                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
658         }
659         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
660 
661         udc = (struct fsl_udc *)ep->udc;
662         spin_lock_irqsave(&udc->lock, flags);
663 
664         /* nuke all pending requests (does flush) */
665         nuke(ep, -ESHUTDOWN);
666 
667         ep->ep.desc = NULL;
668         ep->stopped = 1;
669         spin_unlock_irqrestore(&udc->lock, flags);
670 
671         VDBG("disabled %s OK", _ep->name);
672         return 0;
673 }
674 
675 /*---------------------------------------------------------------------
676  * allocate a request object used by this endpoint
677  * the main operation is to insert the req->queue to the eq->queue
678  * Returns the request, or null if one could not be allocated
679 *---------------------------------------------------------------------*/
680 static struct usb_request *
681 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
682 {
683         struct fsl_req *req = NULL;
684 
685         req = kzalloc(sizeof *req, gfp_flags);
686         if (!req)
687                 return NULL;
688 
689         req->req.dma = DMA_ADDR_INVALID;
690         INIT_LIST_HEAD(&req->queue);
691 
692         return &req->req;
693 }
694 
695 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
696 {
697         struct fsl_req *req = NULL;
698 
699         req = container_of(_req, struct fsl_req, req);
700 
701         if (_req)
702                 kfree(req);
703 }
704 
705 /* Actually add a dTD chain to an empty dQH and let go */
706 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
707 {
708         struct ep_queue_head *qh = get_qh_by_ep(ep);
709 
710         /* Write dQH next pointer and terminate bit to 0 */
711         qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
712                         & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
713 
714         /* Clear active and halt bit */
715         qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
716                                         | EP_QUEUE_HEAD_STATUS_HALT));
717 
718         /* Ensure that updates to the QH will occur before priming. */
719         wmb();
720 
721         /* Prime endpoint by writing correct bit to ENDPTPRIME */
722         fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
723                         : (1 << (ep_index(ep))), &dr_regs->endpointprime);
724 }
725 
726 /* Add dTD chain to the dQH of an EP */
727 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
728 {
729         u32 temp, bitmask, tmp_stat;
730 
731         /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
732         VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
733 
734         bitmask = ep_is_in(ep)
735                 ? (1 << (ep_index(ep) + 16))
736                 : (1 << (ep_index(ep)));
737 
738         /* check if the pipe is empty */
739         if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
740                 /* Add td to the end */
741                 struct fsl_req *lastreq;
742                 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
743                 lastreq->tail->next_td_ptr =
744                         cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
745                 /* Ensure dTD's next dtd pointer to be updated */
746                 wmb();
747                 /* Read prime bit, if 1 goto done */
748                 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
749                         return;
750 
751                 do {
752                         /* Set ATDTW bit in USBCMD */
753                         temp = fsl_readl(&dr_regs->usbcmd);
754                         fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
755 
756                         /* Read correct status bit */
757                         tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
758 
759                 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
760 
761                 /* Write ATDTW bit to 0 */
762                 temp = fsl_readl(&dr_regs->usbcmd);
763                 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
764 
765                 if (tmp_stat)
766                         return;
767         }
768 
769         fsl_prime_ep(ep, req->head);
770 }
771 
772 /* Fill in the dTD structure
773  * @req: request that the transfer belongs to
774  * @length: return actually data length of the dTD
775  * @dma: return dma address of the dTD
776  * @is_last: return flag if it is the last dTD of the request
777  * return: pointer to the built dTD */
778 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
779                 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
780 {
781         u32 swap_temp;
782         struct ep_td_struct *dtd;
783 
784         /* how big will this transfer be? */
785         *length = min(req->req.length - req->req.actual,
786                         (unsigned)EP_MAX_LENGTH_TRANSFER);
787 
788         dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
789         if (dtd == NULL)
790                 return dtd;
791 
792         dtd->td_dma = *dma;
793         /* Clear reserved field */
794         swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
795         swap_temp &= ~DTD_RESERVED_FIELDS;
796         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
797 
798         /* Init all of buffer page pointers */
799         swap_temp = (u32) (req->req.dma + req->req.actual);
800         dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
801         dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
802         dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
803         dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
804         dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
805 
806         req->req.actual += *length;
807 
808         /* zlp is needed if req->req.zero is set */
809         if (req->req.zero) {
810                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
811                         *is_last = 1;
812                 else
813                         *is_last = 0;
814         } else if (req->req.length == req->req.actual)
815                 *is_last = 1;
816         else
817                 *is_last = 0;
818 
819         if ((*is_last) == 0)
820                 VDBG("multi-dtd request!");
821         /* Fill in the transfer size; set active bit */
822         swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
823 
824         /* Enable interrupt for the last dtd of a request */
825         if (*is_last && !req->req.no_interrupt)
826                 swap_temp |= DTD_IOC;
827 
828         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
829 
830         mb();
831 
832         VDBG("length = %d address= 0x%x", *length, (int)*dma);
833 
834         return dtd;
835 }
836 
837 /* Generate dtd chain for a request */
838 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
839 {
840         unsigned        count;
841         int             is_last;
842         int             is_first =1;
843         struct ep_td_struct     *last_dtd = NULL, *dtd;
844         dma_addr_t dma;
845 
846         do {
847                 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
848                 if (dtd == NULL)
849                         return -ENOMEM;
850 
851                 if (is_first) {
852                         is_first = 0;
853                         req->head = dtd;
854                 } else {
855                         last_dtd->next_td_ptr = cpu_to_hc32(dma);
856                         last_dtd->next_td_virt = dtd;
857                 }
858                 last_dtd = dtd;
859 
860                 req->dtd_count++;
861         } while (!is_last);
862 
863         dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
864 
865         req->tail = dtd;
866 
867         return 0;
868 }
869 
870 /* queues (submits) an I/O request to an endpoint */
871 static int
872 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
873 {
874         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
875         struct fsl_req *req = container_of(_req, struct fsl_req, req);
876         struct fsl_udc *udc;
877         unsigned long flags;
878         int ret;
879 
880         /* catch various bogus parameters */
881         if (!_req || !req->req.complete || !req->req.buf
882                         || !list_empty(&req->queue)) {
883                 VDBG("%s, bad params", __func__);
884                 return -EINVAL;
885         }
886         if (unlikely(!_ep || !ep->ep.desc)) {
887                 VDBG("%s, bad ep", __func__);
888                 return -EINVAL;
889         }
890         if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
891                 if (req->req.length > ep->ep.maxpacket)
892                         return -EMSGSIZE;
893         }
894 
895         udc = ep->udc;
896         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
897                 return -ESHUTDOWN;
898 
899         req->ep = ep;
900 
901         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
902         if (ret)
903                 return ret;
904 
905         req->req.status = -EINPROGRESS;
906         req->req.actual = 0;
907         req->dtd_count = 0;
908 
909         /* build dtds and push them to device queue */
910         if (!fsl_req_to_dtd(req, gfp_flags)) {
911                 spin_lock_irqsave(&udc->lock, flags);
912                 fsl_queue_td(ep, req);
913         } else {
914                 return -ENOMEM;
915         }
916 
917         /* irq handler advances the queue */
918         if (req != NULL)
919                 list_add_tail(&req->queue, &ep->queue);
920         spin_unlock_irqrestore(&udc->lock, flags);
921 
922         return 0;
923 }
924 
925 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
926 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
927 {
928         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
929         struct fsl_req *req;
930         unsigned long flags;
931         int ep_num, stopped, ret = 0;
932         u32 epctrl;
933 
934         if (!_ep || !_req)
935                 return -EINVAL;
936 
937         spin_lock_irqsave(&ep->udc->lock, flags);
938         stopped = ep->stopped;
939 
940         /* Stop the ep before we deal with the queue */
941         ep->stopped = 1;
942         ep_num = ep_index(ep);
943         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
944         if (ep_is_in(ep))
945                 epctrl &= ~EPCTRL_TX_ENABLE;
946         else
947                 epctrl &= ~EPCTRL_RX_ENABLE;
948         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
949 
950         /* make sure it's actually queued on this endpoint */
951         list_for_each_entry(req, &ep->queue, queue) {
952                 if (&req->req == _req)
953                         break;
954         }
955         if (&req->req != _req) {
956                 ret = -EINVAL;
957                 goto out;
958         }
959 
960         /* The request is in progress, or completed but not dequeued */
961         if (ep->queue.next == &req->queue) {
962                 _req->status = -ECONNRESET;
963                 fsl_ep_fifo_flush(_ep); /* flush current transfer */
964 
965                 /* The request isn't the last request in this ep queue */
966                 if (req->queue.next != &ep->queue) {
967                         struct fsl_req *next_req;
968 
969                         next_req = list_entry(req->queue.next, struct fsl_req,
970                                         queue);
971 
972                         /* prime with dTD of next request */
973                         fsl_prime_ep(ep, next_req->head);
974                 }
975         /* The request hasn't been processed, patch up the TD chain */
976         } else {
977                 struct fsl_req *prev_req;
978 
979                 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
980                 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
981         }
982 
983         done(ep, req, -ECONNRESET);
984 
985         /* Enable EP */
986 out:    epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
987         if (ep_is_in(ep))
988                 epctrl |= EPCTRL_TX_ENABLE;
989         else
990                 epctrl |= EPCTRL_RX_ENABLE;
991         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
992         ep->stopped = stopped;
993 
994         spin_unlock_irqrestore(&ep->udc->lock, flags);
995         return ret;
996 }
997 
998 /*-------------------------------------------------------------------------*/
999 
1000 /*-----------------------------------------------------------------
1001  * modify the endpoint halt feature
1002  * @ep: the non-isochronous endpoint being stalled
1003  * @value: 1--set halt  0--clear halt
1004  * Returns zero, or a negative error code.
1005 *----------------------------------------------------------------*/
1006 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1007 {
1008         struct fsl_ep *ep = NULL;
1009         unsigned long flags = 0;
1010         int status = -EOPNOTSUPP;       /* operation not supported */
1011         unsigned char ep_dir = 0, ep_num = 0;
1012         struct fsl_udc *udc = NULL;
1013 
1014         ep = container_of(_ep, struct fsl_ep, ep);
1015         udc = ep->udc;
1016         if (!_ep || !ep->ep.desc) {
1017                 status = -EINVAL;
1018                 goto out;
1019         }
1020 
1021         if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
1022                 status = -EOPNOTSUPP;
1023                 goto out;
1024         }
1025 
1026         /* Attempt to halt IN ep will fail if any transfer requests
1027          * are still queue */
1028         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1029                 status = -EAGAIN;
1030                 goto out;
1031         }
1032 
1033         status = 0;
1034         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1035         ep_num = (unsigned char)(ep_index(ep));
1036         spin_lock_irqsave(&ep->udc->lock, flags);
1037         dr_ep_change_stall(ep_num, ep_dir, value);
1038         spin_unlock_irqrestore(&ep->udc->lock, flags);
1039 
1040         if (ep_index(ep) == 0) {
1041                 udc->ep0_state = WAIT_FOR_SETUP;
1042                 udc->ep0_dir = 0;
1043         }
1044 out:
1045         VDBG(" %s %s halt stat %d", ep->ep.name,
1046                         value ?  "set" : "clear", status);
1047 
1048         return status;
1049 }
1050 
1051 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1052 {
1053         struct fsl_ep *ep;
1054         struct fsl_udc *udc;
1055         int size = 0;
1056         u32 bitmask;
1057         struct ep_queue_head *qh;
1058 
1059         ep = container_of(_ep, struct fsl_ep, ep);
1060         if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
1061                 return -ENODEV;
1062 
1063         udc = (struct fsl_udc *)ep->udc;
1064 
1065         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1066                 return -ESHUTDOWN;
1067 
1068         qh = get_qh_by_ep(ep);
1069 
1070         bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1071             (1 << (ep_index(ep)));
1072 
1073         if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1074                 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1075                     >> DTD_LENGTH_BIT_POS;
1076 
1077         pr_debug("%s %u\n", __func__, size);
1078         return size;
1079 }
1080 
1081 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1082 {
1083         struct fsl_ep *ep;
1084         int ep_num, ep_dir;
1085         u32 bits;
1086         unsigned long timeout;
1087 #define FSL_UDC_FLUSH_TIMEOUT 1000
1088 
1089         if (!_ep) {
1090                 return;
1091         } else {
1092                 ep = container_of(_ep, struct fsl_ep, ep);
1093                 if (!ep->ep.desc)
1094                         return;
1095         }
1096         ep_num = ep_index(ep);
1097         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1098 
1099         if (ep_num == 0)
1100                 bits = (1 << 16) | 1;
1101         else if (ep_dir == USB_SEND)
1102                 bits = 1 << (16 + ep_num);
1103         else
1104                 bits = 1 << ep_num;
1105 
1106         timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1107         do {
1108                 fsl_writel(bits, &dr_regs->endptflush);
1109 
1110                 /* Wait until flush complete */
1111                 while (fsl_readl(&dr_regs->endptflush)) {
1112                         if (time_after(jiffies, timeout)) {
1113                                 ERR("ep flush timeout\n");
1114                                 return;
1115                         }
1116                         cpu_relax();
1117                 }
1118                 /* See if we need to flush again */
1119         } while (fsl_readl(&dr_regs->endptstatus) & bits);
1120 }
1121 
1122 static struct usb_ep_ops fsl_ep_ops = {
1123         .enable = fsl_ep_enable,
1124         .disable = fsl_ep_disable,
1125 
1126         .alloc_request = fsl_alloc_request,
1127         .free_request = fsl_free_request,
1128 
1129         .queue = fsl_ep_queue,
1130         .dequeue = fsl_ep_dequeue,
1131 
1132         .set_halt = fsl_ep_set_halt,
1133         .fifo_status = fsl_ep_fifo_status,
1134         .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
1135 };
1136 
1137 /*-------------------------------------------------------------------------
1138                 Gadget Driver Layer Operations
1139 -------------------------------------------------------------------------*/
1140 
1141 /*----------------------------------------------------------------------
1142  * Get the current frame number (from DR frame_index Reg )
1143  *----------------------------------------------------------------------*/
1144 static int fsl_get_frame(struct usb_gadget *gadget)
1145 {
1146         return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1147 }
1148 
1149 /*-----------------------------------------------------------------------
1150  * Tries to wake up the host connected to this gadget
1151  -----------------------------------------------------------------------*/
1152 static int fsl_wakeup(struct usb_gadget *gadget)
1153 {
1154         struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1155         u32 portsc;
1156 
1157         /* Remote wakeup feature not enabled by host */
1158         if (!udc->remote_wakeup)
1159                 return -ENOTSUPP;
1160 
1161         portsc = fsl_readl(&dr_regs->portsc1);
1162         /* not suspended? */
1163         if (!(portsc & PORTSCX_PORT_SUSPEND))
1164                 return 0;
1165         /* trigger force resume */
1166         portsc |= PORTSCX_PORT_FORCE_RESUME;
1167         fsl_writel(portsc, &dr_regs->portsc1);
1168         return 0;
1169 }
1170 
1171 static int can_pullup(struct fsl_udc *udc)
1172 {
1173         return udc->driver && udc->softconnect && udc->vbus_active;
1174 }
1175 
1176 /* Notify controller that VBUS is powered, Called by whatever
1177    detects VBUS sessions */
1178 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1179 {
1180         struct fsl_udc  *udc;
1181         unsigned long   flags;
1182 
1183         udc = container_of(gadget, struct fsl_udc, gadget);
1184         spin_lock_irqsave(&udc->lock, flags);
1185         VDBG("VBUS %s", is_active ? "on" : "off");
1186         udc->vbus_active = (is_active != 0);
1187         if (can_pullup(udc))
1188                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1189                                 &dr_regs->usbcmd);
1190         else
1191                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1192                                 &dr_regs->usbcmd);
1193         spin_unlock_irqrestore(&udc->lock, flags);
1194         return 0;
1195 }
1196 
1197 /* constrain controller's VBUS power usage
1198  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1199  * reporting how much power the device may consume.  For example, this
1200  * could affect how quickly batteries are recharged.
1201  *
1202  * Returns zero on success, else negative errno.
1203  */
1204 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1205 {
1206         struct fsl_udc *udc;
1207 
1208         udc = container_of(gadget, struct fsl_udc, gadget);
1209         if (!IS_ERR_OR_NULL(udc->transceiver))
1210                 return usb_phy_set_power(udc->transceiver, mA);
1211         return -ENOTSUPP;
1212 }
1213 
1214 /* Change Data+ pullup status
1215  * this func is used by usb_gadget_connect/disconnet
1216  */
1217 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1218 {
1219         struct fsl_udc *udc;
1220 
1221         udc = container_of(gadget, struct fsl_udc, gadget);
1222 
1223         if (!udc->vbus_active)
1224                 return -EOPNOTSUPP;
1225 
1226         udc->softconnect = (is_on != 0);
1227         if (can_pullup(udc))
1228                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1229                                 &dr_regs->usbcmd);
1230         else
1231                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1232                                 &dr_regs->usbcmd);
1233 
1234         return 0;
1235 }
1236 
1237 static int fsl_udc_start(struct usb_gadget *g,
1238                 struct usb_gadget_driver *driver);
1239 static int fsl_udc_stop(struct usb_gadget *g,
1240                 struct usb_gadget_driver *driver);
1241 /* defined in gadget.h */
1242 static const struct usb_gadget_ops fsl_gadget_ops = {
1243         .get_frame = fsl_get_frame,
1244         .wakeup = fsl_wakeup,
1245 /*      .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1246         .vbus_session = fsl_vbus_session,
1247         .vbus_draw = fsl_vbus_draw,
1248         .pullup = fsl_pullup,
1249         .udc_start = fsl_udc_start,
1250         .udc_stop = fsl_udc_stop,
1251 };
1252 
1253 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1254    on new transaction */
1255 static void ep0stall(struct fsl_udc *udc)
1256 {
1257         u32 tmp;
1258 
1259         /* must set tx and rx to stall at the same time */
1260         tmp = fsl_readl(&dr_regs->endptctrl[0]);
1261         tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1262         fsl_writel(tmp, &dr_regs->endptctrl[0]);
1263         udc->ep0_state = WAIT_FOR_SETUP;
1264         udc->ep0_dir = 0;
1265 }
1266 
1267 /* Prime a status phase for ep0 */
1268 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1269 {
1270         struct fsl_req *req = udc->status_req;
1271         struct fsl_ep *ep;
1272         int ret;
1273 
1274         if (direction == EP_DIR_IN)
1275                 udc->ep0_dir = USB_DIR_IN;
1276         else
1277                 udc->ep0_dir = USB_DIR_OUT;
1278 
1279         ep = &udc->eps[0];
1280         if (udc->ep0_state != DATA_STATE_XMIT)
1281                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1282 
1283         req->ep = ep;
1284         req->req.length = 0;
1285         req->req.status = -EINPROGRESS;
1286         req->req.actual = 0;
1287         req->req.complete = NULL;
1288         req->dtd_count = 0;
1289 
1290         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1291         if (ret)
1292                 return ret;
1293 
1294         if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1295                 fsl_queue_td(ep, req);
1296         else
1297                 return -ENOMEM;
1298 
1299         list_add_tail(&req->queue, &ep->queue);
1300 
1301         return 0;
1302 }
1303 
1304 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1305 {
1306         struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1307 
1308         if (ep->name)
1309                 nuke(ep, -ESHUTDOWN);
1310 }
1311 
1312 /*
1313  * ch9 Set address
1314  */
1315 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1316 {
1317         /* Save the new address to device struct */
1318         udc->device_address = (u8) value;
1319         /* Update usb state */
1320         udc->usb_state = USB_STATE_ADDRESS;
1321         /* Status phase */
1322         if (ep0_prime_status(udc, EP_DIR_IN))
1323                 ep0stall(udc);
1324 }
1325 
1326 /*
1327  * ch9 Get status
1328  */
1329 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1330                 u16 index, u16 length)
1331 {
1332         u16 tmp = 0;            /* Status, cpu endian */
1333         struct fsl_req *req;
1334         struct fsl_ep *ep;
1335         int ret;
1336 
1337         ep = &udc->eps[0];
1338 
1339         if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1340                 /* Get device status */
1341                 tmp = 1 << USB_DEVICE_SELF_POWERED;
1342                 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1343         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1344                 /* Get interface status */
1345                 /* We don't have interface information in udc driver */
1346                 tmp = 0;
1347         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1348                 /* Get endpoint status */
1349                 struct fsl_ep *target_ep;
1350 
1351                 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1352 
1353                 /* stall if endpoint doesn't exist */
1354                 if (!target_ep->ep.desc)
1355                         goto stall;
1356                 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1357                                 << USB_ENDPOINT_HALT;
1358         }
1359 
1360         udc->ep0_dir = USB_DIR_IN;
1361         /* Borrow the per device status_req */
1362         req = udc->status_req;
1363         /* Fill in the reqest structure */
1364         *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1365 
1366         req->ep = ep;
1367         req->req.length = 2;
1368         req->req.status = -EINPROGRESS;
1369         req->req.actual = 0;
1370         req->req.complete = NULL;
1371         req->dtd_count = 0;
1372 
1373         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1374         if (ret)
1375                 goto stall;
1376 
1377         /* prime the data phase */
1378         if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1379                 fsl_queue_td(ep, req);
1380         else                    /* no mem */
1381                 goto stall;
1382 
1383         list_add_tail(&req->queue, &ep->queue);
1384         udc->ep0_state = DATA_STATE_XMIT;
1385         if (ep0_prime_status(udc, EP_DIR_OUT))
1386                 ep0stall(udc);
1387 
1388         return;
1389 stall:
1390         ep0stall(udc);
1391 }
1392 
1393 static void setup_received_irq(struct fsl_udc *udc,
1394                 struct usb_ctrlrequest *setup)
1395 {
1396         u16 wValue = le16_to_cpu(setup->wValue);
1397         u16 wIndex = le16_to_cpu(setup->wIndex);
1398         u16 wLength = le16_to_cpu(setup->wLength);
1399 
1400         udc_reset_ep_queue(udc, 0);
1401 
1402         /* We process some stardard setup requests here */
1403         switch (setup->bRequest) {
1404         case USB_REQ_GET_STATUS:
1405                 /* Data+Status phase from udc */
1406                 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1407                                         != (USB_DIR_IN | USB_TYPE_STANDARD))
1408                         break;
1409                 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1410                 return;
1411 
1412         case USB_REQ_SET_ADDRESS:
1413                 /* Status phase from udc */
1414                 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1415                                                 | USB_RECIP_DEVICE))
1416                         break;
1417                 ch9setaddress(udc, wValue, wIndex, wLength);
1418                 return;
1419 
1420         case USB_REQ_CLEAR_FEATURE:
1421         case USB_REQ_SET_FEATURE:
1422                 /* Status phase from udc */
1423         {
1424                 int rc = -EOPNOTSUPP;
1425                 u16 ptc = 0;
1426 
1427                 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1428                                 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1429                         int pipe = get_pipe_by_windex(wIndex);
1430                         struct fsl_ep *ep;
1431 
1432                         if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1433                                 break;
1434                         ep = get_ep_by_pipe(udc, pipe);
1435 
1436                         spin_unlock(&udc->lock);
1437                         rc = fsl_ep_set_halt(&ep->ep,
1438                                         (setup->bRequest == USB_REQ_SET_FEATURE)
1439                                                 ? 1 : 0);
1440                         spin_lock(&udc->lock);
1441 
1442                 } else if ((setup->bRequestType & (USB_RECIP_MASK
1443                                 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1444                                 | USB_TYPE_STANDARD)) {
1445                         /* Note: The driver has not include OTG support yet.
1446                          * This will be set when OTG support is added */
1447                         if (wValue == USB_DEVICE_TEST_MODE)
1448                                 ptc = wIndex >> 8;
1449                         else if (gadget_is_otg(&udc->gadget)) {
1450                                 if (setup->bRequest ==
1451                                     USB_DEVICE_B_HNP_ENABLE)
1452                                         udc->gadget.b_hnp_enable = 1;
1453                                 else if (setup->bRequest ==
1454                                          USB_DEVICE_A_HNP_SUPPORT)
1455                                         udc->gadget.a_hnp_support = 1;
1456                                 else if (setup->bRequest ==
1457                                          USB_DEVICE_A_ALT_HNP_SUPPORT)
1458                                         udc->gadget.a_alt_hnp_support = 1;
1459                         }
1460                         rc = 0;
1461                 } else
1462                         break;
1463 
1464                 if (rc == 0) {
1465                         if (ep0_prime_status(udc, EP_DIR_IN))
1466                                 ep0stall(udc);
1467                 }
1468                 if (ptc) {
1469                         u32 tmp;
1470 
1471                         mdelay(10);
1472                         tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1473                         fsl_writel(tmp, &dr_regs->portsc1);
1474                         printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1475                 }
1476 
1477                 return;
1478         }
1479 
1480         default:
1481                 break;
1482         }
1483 
1484         /* Requests handled by gadget */
1485         if (wLength) {
1486                 /* Data phase from gadget, status phase from udc */
1487                 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1488                                 ?  USB_DIR_IN : USB_DIR_OUT;
1489                 spin_unlock(&udc->lock);
1490                 if (udc->driver->setup(&udc->gadget,
1491                                 &udc->local_setup_buff) < 0)
1492                         ep0stall(udc);
1493                 spin_lock(&udc->lock);
1494                 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1495                                 ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1496                 /*
1497                  * If the data stage is IN, send status prime immediately.
1498                  * See 2.0 Spec chapter 8.5.3.3 for detail.
1499                  */
1500                 if (udc->ep0_state == DATA_STATE_XMIT)
1501                         if (ep0_prime_status(udc, EP_DIR_OUT))
1502                                 ep0stall(udc);
1503 
1504         } else {
1505                 /* No data phase, IN status from gadget */
1506                 udc->ep0_dir = USB_DIR_IN;
1507                 spin_unlock(&udc->lock);
1508                 if (udc->driver->setup(&udc->gadget,
1509                                 &udc->local_setup_buff) < 0)
1510                         ep0stall(udc);
1511                 spin_lock(&udc->lock);
1512                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1513         }
1514 }
1515 
1516 /* Process request for Data or Status phase of ep0
1517  * prime status phase if needed */
1518 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1519                 struct fsl_req *req)
1520 {
1521         if (udc->usb_state == USB_STATE_ADDRESS) {
1522                 /* Set the new address */
1523                 u32 new_address = (u32) udc->device_address;
1524                 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1525                                 &dr_regs->deviceaddr);
1526         }
1527 
1528         done(ep0, req, 0);
1529 
1530         switch (udc->ep0_state) {
1531         case DATA_STATE_XMIT:
1532                 /* already primed at setup_received_irq */
1533                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1534                 break;
1535         case DATA_STATE_RECV:
1536                 /* send status phase */
1537                 if (ep0_prime_status(udc, EP_DIR_IN))
1538                         ep0stall(udc);
1539                 break;
1540         case WAIT_FOR_OUT_STATUS:
1541                 udc->ep0_state = WAIT_FOR_SETUP;
1542                 break;
1543         case WAIT_FOR_SETUP:
1544                 ERR("Unexpect ep0 packets\n");
1545                 break;
1546         default:
1547                 ep0stall(udc);
1548                 break;
1549         }
1550 }
1551 
1552 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1553  * being corrupted by another incoming setup packet */
1554 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1555 {
1556         u32 temp;
1557         struct ep_queue_head *qh;
1558         struct fsl_usb2_platform_data *pdata = udc->pdata;
1559 
1560         qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1561 
1562         /* Clear bit in ENDPTSETUPSTAT */
1563         temp = fsl_readl(&dr_regs->endptsetupstat);
1564         fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1565 
1566         /* while a hazard exists when setup package arrives */
1567         do {
1568                 /* Set Setup Tripwire */
1569                 temp = fsl_readl(&dr_regs->usbcmd);
1570                 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1571 
1572                 /* Copy the setup packet to local buffer */
1573                 if (pdata->le_setup_buf) {
1574                         u32 *p = (u32 *)buffer_ptr;
1575                         u32 *s = (u32 *)qh->setup_buffer;
1576 
1577                         /* Convert little endian setup buffer to CPU endian */
1578                         *p++ = le32_to_cpu(*s++);
1579                         *p = le32_to_cpu(*s);
1580                 } else {
1581                         memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1582                 }
1583         } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1584 
1585         /* Clear Setup Tripwire */
1586         temp = fsl_readl(&dr_regs->usbcmd);
1587         fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1588 }
1589 
1590 /* process-ep_req(): free the completed Tds for this req */
1591 static int process_ep_req(struct fsl_udc *udc, int pipe,
1592                 struct fsl_req *curr_req)
1593 {
1594         struct ep_td_struct *curr_td;
1595         int     td_complete, actual, remaining_length, j, tmp;
1596         int     status = 0;
1597         int     errors = 0;
1598         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1599         int direction = pipe % 2;
1600 
1601         curr_td = curr_req->head;
1602         td_complete = 0;
1603         actual = curr_req->req.length;
1604 
1605         for (j = 0; j < curr_req->dtd_count; j++) {
1606                 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1607                                         & DTD_PACKET_SIZE)
1608                                 >> DTD_LENGTH_BIT_POS;
1609                 actual -= remaining_length;
1610 
1611                 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1612                 if (errors & DTD_ERROR_MASK) {
1613                         if (errors & DTD_STATUS_HALTED) {
1614                                 ERR("dTD error %08x QH=%d\n", errors, pipe);
1615                                 /* Clear the errors and Halt condition */
1616                                 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1617                                 tmp &= ~errors;
1618                                 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1619                                 status = -EPIPE;
1620                                 /* FIXME: continue with next queued TD? */
1621 
1622                                 break;
1623                         }
1624                         if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1625                                 VDBG("Transfer overflow");
1626                                 status = -EPROTO;
1627                                 break;
1628                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1629                                 VDBG("ISO error");
1630                                 status = -EILSEQ;
1631                                 break;
1632                         } else
1633                                 ERR("Unknown error has occurred (0x%x)!\n",
1634                                         errors);
1635 
1636                 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1637                                 & DTD_STATUS_ACTIVE) {
1638                         VDBG("Request not complete");
1639                         status = REQ_UNCOMPLETE;
1640                         return status;
1641                 } else if (remaining_length) {
1642                         if (direction) {
1643                                 VDBG("Transmit dTD remaining length not zero");
1644                                 status = -EPROTO;
1645                                 break;
1646                         } else {
1647                                 td_complete++;
1648                                 break;
1649                         }
1650                 } else {
1651                         td_complete++;
1652                         VDBG("dTD transmitted successful");
1653                 }
1654 
1655                 if (j != curr_req->dtd_count - 1)
1656                         curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1657         }
1658 
1659         if (status)
1660                 return status;
1661 
1662         curr_req->req.actual = actual;
1663 
1664         return 0;
1665 }
1666 
1667 /* Process a DTD completion interrupt */
1668 static void dtd_complete_irq(struct fsl_udc *udc)
1669 {
1670         u32 bit_pos;
1671         int i, ep_num, direction, bit_mask, status;
1672         struct fsl_ep *curr_ep;
1673         struct fsl_req *curr_req, *temp_req;
1674 
1675         /* Clear the bits in the register */
1676         bit_pos = fsl_readl(&dr_regs->endptcomplete);
1677         fsl_writel(bit_pos, &dr_regs->endptcomplete);
1678 
1679         if (!bit_pos)
1680                 return;
1681 
1682         for (i = 0; i < udc->max_ep; i++) {
1683                 ep_num = i >> 1;
1684                 direction = i % 2;
1685 
1686                 bit_mask = 1 << (ep_num + 16 * direction);
1687 
1688                 if (!(bit_pos & bit_mask))
1689                         continue;
1690 
1691                 curr_ep = get_ep_by_pipe(udc, i);
1692 
1693                 /* If the ep is configured */
1694                 if (curr_ep->name == NULL) {
1695                         WARNING("Invalid EP?");
1696                         continue;
1697                 }
1698 
1699                 /* process the req queue until an uncomplete request */
1700                 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1701                                 queue) {
1702                         status = process_ep_req(udc, i, curr_req);
1703 
1704                         VDBG("status of process_ep_req= %d, ep = %d",
1705                                         status, ep_num);
1706                         if (status == REQ_UNCOMPLETE)
1707                                 break;
1708                         /* write back status to req */
1709                         curr_req->req.status = status;
1710 
1711                         if (ep_num == 0) {
1712                                 ep0_req_complete(udc, curr_ep, curr_req);
1713                                 break;
1714                         } else
1715                                 done(curr_ep, curr_req, status);
1716                 }
1717         }
1718 }
1719 
1720 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1721 {
1722         switch (reg & PORTSCX_PORT_SPEED_MASK) {
1723         case PORTSCX_PORT_SPEED_HIGH:
1724                 return USB_SPEED_HIGH;
1725         case PORTSCX_PORT_SPEED_FULL:
1726                 return USB_SPEED_FULL;
1727         case PORTSCX_PORT_SPEED_LOW:
1728                 return USB_SPEED_LOW;
1729         default:
1730                 return USB_SPEED_UNKNOWN;
1731         }
1732 }
1733 
1734 /* Process a port change interrupt */
1735 static void port_change_irq(struct fsl_udc *udc)
1736 {
1737         if (udc->bus_reset)
1738                 udc->bus_reset = 0;
1739 
1740         /* Bus resetting is finished */
1741         if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1742                 /* Get the speed */
1743                 udc->gadget.speed =
1744                         portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1745 
1746         /* Update USB state */
1747         if (!udc->resume_state)
1748                 udc->usb_state = USB_STATE_DEFAULT;
1749 }
1750 
1751 /* Process suspend interrupt */
1752 static void suspend_irq(struct fsl_udc *udc)
1753 {
1754         udc->resume_state = udc->usb_state;
1755         udc->usb_state = USB_STATE_SUSPENDED;
1756 
1757         /* report suspend to the driver, serial.c does not support this */
1758         if (udc->driver->suspend)
1759                 udc->driver->suspend(&udc->gadget);
1760 }
1761 
1762 static void bus_resume(struct fsl_udc *udc)
1763 {
1764         udc->usb_state = udc->resume_state;
1765         udc->resume_state = 0;
1766 
1767         /* report resume to the driver, serial.c does not support this */
1768         if (udc->driver->resume)
1769                 udc->driver->resume(&udc->gadget);
1770 }
1771 
1772 /* Clear up all ep queues */
1773 static int reset_queues(struct fsl_udc *udc)
1774 {
1775         u8 pipe;
1776 
1777         for (pipe = 0; pipe < udc->max_pipes; pipe++)
1778                 udc_reset_ep_queue(udc, pipe);
1779 
1780         /* report disconnect; the driver is already quiesced */
1781         spin_unlock(&udc->lock);
1782         udc->driver->disconnect(&udc->gadget);
1783         spin_lock(&udc->lock);
1784 
1785         return 0;
1786 }
1787 
1788 /* Process reset interrupt */
1789 static void reset_irq(struct fsl_udc *udc)
1790 {
1791         u32 temp;
1792         unsigned long timeout;
1793 
1794         /* Clear the device address */
1795         temp = fsl_readl(&dr_regs->deviceaddr);
1796         fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1797 
1798         udc->device_address = 0;
1799 
1800         /* Clear usb state */
1801         udc->resume_state = 0;
1802         udc->ep0_dir = 0;
1803         udc->ep0_state = WAIT_FOR_SETUP;
1804         udc->remote_wakeup = 0; /* default to 0 on reset */
1805         udc->gadget.b_hnp_enable = 0;
1806         udc->gadget.a_hnp_support = 0;
1807         udc->gadget.a_alt_hnp_support = 0;
1808 
1809         /* Clear all the setup token semaphores */
1810         temp = fsl_readl(&dr_regs->endptsetupstat);
1811         fsl_writel(temp, &dr_regs->endptsetupstat);
1812 
1813         /* Clear all the endpoint complete status bits */
1814         temp = fsl_readl(&dr_regs->endptcomplete);
1815         fsl_writel(temp, &dr_regs->endptcomplete);
1816 
1817         timeout = jiffies + 100;
1818         while (fsl_readl(&dr_regs->endpointprime)) {
1819                 /* Wait until all endptprime bits cleared */
1820                 if (time_after(jiffies, timeout)) {
1821                         ERR("Timeout for reset\n");
1822                         break;
1823                 }
1824                 cpu_relax();
1825         }
1826 
1827         /* Write 1s to the flush register */
1828         fsl_writel(0xffffffff, &dr_regs->endptflush);
1829 
1830         if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1831                 VDBG("Bus reset");
1832                 /* Bus is reseting */
1833                 udc->bus_reset = 1;
1834                 /* Reset all the queues, include XD, dTD, EP queue
1835                  * head and TR Queue */
1836                 reset_queues(udc);
1837                 udc->usb_state = USB_STATE_DEFAULT;
1838         } else {
1839                 VDBG("Controller reset");
1840                 /* initialize usb hw reg except for regs for EP, not
1841                  * touch usbintr reg */
1842                 dr_controller_setup(udc);
1843 
1844                 /* Reset all internal used Queues */
1845                 reset_queues(udc);
1846 
1847                 ep0_setup(udc);
1848 
1849                 /* Enable DR IRQ reg, Set Run bit, change udc state */
1850                 dr_controller_run(udc);
1851                 udc->usb_state = USB_STATE_ATTACHED;
1852         }
1853 }
1854 
1855 /*
1856  * USB device controller interrupt handler
1857  */
1858 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1859 {
1860         struct fsl_udc *udc = _udc;
1861         u32 irq_src;
1862         irqreturn_t status = IRQ_NONE;
1863         unsigned long flags;
1864 
1865         /* Disable ISR for OTG host mode */
1866         if (udc->stopped)
1867                 return IRQ_NONE;
1868         spin_lock_irqsave(&udc->lock, flags);
1869         irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1870         /* Clear notification bits */
1871         fsl_writel(irq_src, &dr_regs->usbsts);
1872 
1873         /* VDBG("irq_src [0x%8x]", irq_src); */
1874 
1875         /* Need to resume? */
1876         if (udc->usb_state == USB_STATE_SUSPENDED)
1877                 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1878                         bus_resume(udc);
1879 
1880         /* USB Interrupt */
1881         if (irq_src & USB_STS_INT) {
1882                 VDBG("Packet int");
1883                 /* Setup package, we only support ep0 as control ep */
1884                 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1885                         tripwire_handler(udc, 0,
1886                                         (u8 *) (&udc->local_setup_buff));
1887                         setup_received_irq(udc, &udc->local_setup_buff);
1888                         status = IRQ_HANDLED;
1889                 }
1890 
1891                 /* completion of dtd */
1892                 if (fsl_readl(&dr_regs->endptcomplete)) {
1893                         dtd_complete_irq(udc);
1894                         status = IRQ_HANDLED;
1895                 }
1896         }
1897 
1898         /* SOF (for ISO transfer) */
1899         if (irq_src & USB_STS_SOF) {
1900                 status = IRQ_HANDLED;
1901         }
1902 
1903         /* Port Change */
1904         if (irq_src & USB_STS_PORT_CHANGE) {
1905                 port_change_irq(udc);
1906                 status = IRQ_HANDLED;
1907         }
1908 
1909         /* Reset Received */
1910         if (irq_src & USB_STS_RESET) {
1911                 VDBG("reset int");
1912                 reset_irq(udc);
1913                 status = IRQ_HANDLED;
1914         }
1915 
1916         /* Sleep Enable (Suspend) */
1917         if (irq_src & USB_STS_SUSPEND) {
1918                 suspend_irq(udc);
1919                 status = IRQ_HANDLED;
1920         }
1921 
1922         if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1923                 VDBG("Error IRQ %x", irq_src);
1924         }
1925 
1926         spin_unlock_irqrestore(&udc->lock, flags);
1927         return status;
1928 }
1929 
1930 /*----------------------------------------------------------------*
1931  * Hook to gadget drivers
1932  * Called by initialization code of gadget drivers
1933 *----------------------------------------------------------------*/
1934 static int fsl_udc_start(struct usb_gadget *g,
1935                 struct usb_gadget_driver *driver)
1936 {
1937         int retval = 0;
1938         unsigned long flags = 0;
1939 
1940         /* lock is needed but whether should use this lock or another */
1941         spin_lock_irqsave(&udc_controller->lock, flags);
1942 
1943         driver->driver.bus = NULL;
1944         /* hook up the driver */
1945         udc_controller->driver = driver;
1946         spin_unlock_irqrestore(&udc_controller->lock, flags);
1947 
1948         if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1949                 /* Suspend the controller until OTG enable it */
1950                 udc_controller->stopped = 1;
1951                 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1952 
1953                 /* connect to bus through transceiver */
1954                 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1955                         retval = otg_set_peripheral(
1956                                         udc_controller->transceiver->otg,
1957                                                     &udc_controller->gadget);
1958                         if (retval < 0) {
1959                                 ERR("can't bind to transceiver\n");
1960                                 driver->unbind(&udc_controller->gadget);
1961                                 udc_controller->driver = 0;
1962                                 return retval;
1963                         }
1964                 }
1965         } else {
1966                 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1967                 dr_controller_run(udc_controller);
1968                 udc_controller->usb_state = USB_STATE_ATTACHED;
1969                 udc_controller->ep0_state = WAIT_FOR_SETUP;
1970                 udc_controller->ep0_dir = 0;
1971         }
1972 
1973         return retval;
1974 }
1975 
1976 /* Disconnect from gadget driver */
1977 static int fsl_udc_stop(struct usb_gadget *g,
1978                 struct usb_gadget_driver *driver)
1979 {
1980         struct fsl_ep *loop_ep;
1981         unsigned long flags;
1982 
1983         if (!IS_ERR_OR_NULL(udc_controller->transceiver))
1984                 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
1985 
1986         /* stop DR, disable intr */
1987         dr_controller_stop(udc_controller);
1988 
1989         /* in fact, no needed */
1990         udc_controller->usb_state = USB_STATE_ATTACHED;
1991         udc_controller->ep0_state = WAIT_FOR_SETUP;
1992         udc_controller->ep0_dir = 0;
1993 
1994         /* stand operation */
1995         spin_lock_irqsave(&udc_controller->lock, flags);
1996         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
1997         nuke(&udc_controller->eps[0], -ESHUTDOWN);
1998         list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
1999                         ep.ep_list)
2000                 nuke(loop_ep, -ESHUTDOWN);
2001         spin_unlock_irqrestore(&udc_controller->lock, flags);
2002 
2003         udc_controller->driver = NULL;
2004 
2005         return 0;
2006 }
2007 
2008 /*-------------------------------------------------------------------------
2009                 PROC File System Support
2010 -------------------------------------------------------------------------*/
2011 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2012 
2013 #include <linux/seq_file.h>
2014 
2015 static const char proc_filename[] = "driver/fsl_usb2_udc";
2016 
2017 static int fsl_proc_read(struct seq_file *m, void *v)
2018 {
2019         unsigned long flags;
2020         int i;
2021         u32 tmp_reg;
2022         struct fsl_ep *ep = NULL;
2023         struct fsl_req *req;
2024 
2025         struct fsl_udc *udc = udc_controller;
2026 
2027         spin_lock_irqsave(&udc->lock, flags);
2028 
2029         /* ------basic driver information ---- */
2030         seq_printf(m,
2031                         DRIVER_DESC "\n"
2032                         "%s version: %s\n"
2033                         "Gadget driver: %s\n\n",
2034                         driver_name, DRIVER_VERSION,
2035                         udc->driver ? udc->driver->driver.name : "(none)");
2036 
2037         /* ------ DR Registers ----- */
2038         tmp_reg = fsl_readl(&dr_regs->usbcmd);
2039         seq_printf(m,
2040                         "USBCMD reg:\n"
2041                         "SetupTW: %d\n"
2042                         "Run/Stop: %s\n\n",
2043                         (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2044                         (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2045 
2046         tmp_reg = fsl_readl(&dr_regs->usbsts);
2047         seq_printf(m,
2048                         "USB Status Reg:\n"
2049                         "Dr Suspend: %d Reset Received: %d System Error: %s "
2050                         "USB Error Interrupt: %s\n\n",
2051                         (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2052                         (tmp_reg & USB_STS_RESET) ? 1 : 0,
2053                         (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2054                         (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2055 
2056         tmp_reg = fsl_readl(&dr_regs->usbintr);
2057         seq_printf(m,
2058                         "USB Interrupt Enable Reg:\n"
2059                         "Sleep Enable: %d SOF Received Enable: %d "
2060                         "Reset Enable: %d\n"
2061                         "System Error Enable: %d "
2062                         "Port Change Dectected Enable: %d\n"
2063                         "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2064                         (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2065                         (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2066                         (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2067                         (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2068                         (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2069                         (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2070                         (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2071 
2072         tmp_reg = fsl_readl(&dr_regs->frindex);
2073         seq_printf(m,
2074                         "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2075                         (tmp_reg & USB_FRINDEX_MASKS));
2076 
2077         tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2078         seq_printf(m,
2079                         "USB Device Address Reg: Device Addr is 0x%x\n\n",
2080                         (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2081 
2082         tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2083         seq_printf(m,
2084                         "USB Endpoint List Address Reg: "
2085                         "Device Addr is 0x%x\n\n",
2086                         (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2087 
2088         tmp_reg = fsl_readl(&dr_regs->portsc1);
2089         seq_printf(m,
2090                 "USB Port Status&Control Reg:\n"
2091                 "Port Transceiver Type : %s Port Speed: %s\n"
2092                 "PHY Low Power Suspend: %s Port Reset: %s "
2093                 "Port Suspend Mode: %s\n"
2094                 "Over-current Change: %s "
2095                 "Port Enable/Disable Change: %s\n"
2096                 "Port Enabled/Disabled: %s "
2097                 "Current Connect Status: %s\n\n", ( {
2098                         const char *s;
2099                         switch (tmp_reg & PORTSCX_PTS_FSLS) {
2100                         case PORTSCX_PTS_UTMI:
2101                                 s = "UTMI"; break;
2102                         case PORTSCX_PTS_ULPI:
2103                                 s = "ULPI "; break;
2104                         case PORTSCX_PTS_FSLS:
2105                                 s = "FS/LS Serial"; break;
2106                         default:
2107                                 s = "None"; break;
2108                         }
2109                         s;} ),
2110                 usb_speed_string(portscx_device_speed(tmp_reg)),
2111                 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2112                 "Normal PHY mode" : "Low power mode",
2113                 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2114                 "Not in Reset",
2115                 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2116                 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2117                 "No",
2118                 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2119                 "Not change",
2120                 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2121                 "Not correct",
2122                 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2123                 "Attached" : "Not-Att");
2124 
2125         tmp_reg = fsl_readl(&dr_regs->usbmode);
2126         seq_printf(m,
2127                         "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2128                                 const char *s;
2129                                 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2130                                 case USB_MODE_CTRL_MODE_IDLE:
2131                                         s = "Idle"; break;
2132                                 case USB_MODE_CTRL_MODE_DEVICE:
2133                                         s = "Device Controller"; break;
2134                                 case USB_MODE_CTRL_MODE_HOST:
2135                                         s = "Host Controller"; break;
2136                                 default:
2137                                         s = "None"; break;
2138                                 }
2139                                 s;
2140                         } ));
2141 
2142         tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2143         seq_printf(m,
2144                         "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2145                         (tmp_reg & EP_SETUP_STATUS_MASK));
2146 
2147         for (i = 0; i < udc->max_ep / 2; i++) {
2148                 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2149                 seq_printf(m, "EP Ctrl Reg [0x%x]: = [0x%x]\n", i, tmp_reg);
2150         }
2151         tmp_reg = fsl_readl(&dr_regs->endpointprime);
2152         seq_printf(m, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2153 
2154 #ifndef CONFIG_ARCH_MXC
2155         if (udc->pdata->have_sysif_regs) {
2156                 tmp_reg = usb_sys_regs->snoop1;
2157                 seq_printf(m, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2158 
2159                 tmp_reg = usb_sys_regs->control;
2160                 seq_printf(m, "General Control Reg : = [0x%x]\n\n", tmp_reg);
2161         }
2162 #endif
2163 
2164         /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2165         ep = &udc->eps[0];
2166         seq_printf(m, "For %s Maxpkt is 0x%x index is 0x%x\n",
2167                         ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2168 
2169         if (list_empty(&ep->queue)) {
2170                 seq_puts(m, "its req queue is empty\n\n");
2171         } else {
2172                 list_for_each_entry(req, &ep->queue, queue) {
2173                         seq_printf(m,
2174                                 "req %p actual 0x%x length 0x%x buf %p\n",
2175                                 &req->req, req->req.actual,
2176                                 req->req.length, req->req.buf);
2177                 }
2178         }
2179         /* other gadget->eplist ep */
2180         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2181                 if (ep->ep.desc) {
2182                         seq_printf(m,
2183                                         "\nFor %s Maxpkt is 0x%x "
2184                                         "index is 0x%x\n",
2185                                         ep->ep.name, ep_maxpacket(ep),
2186                                         ep_index(ep));
2187 
2188                         if (list_empty(&ep->queue)) {
2189                                 seq_puts(m, "its req queue is empty\n\n");
2190                         } else {
2191                                 list_for_each_entry(req, &ep->queue, queue) {
2192                                         seq_printf(m,
2193                                                 "req %p actual 0x%x length "
2194                                                 "0x%x  buf %p\n",
2195                                                 &req->req, req->req.actual,
2196                                                 req->req.length, req->req.buf);
2197                                 }       /* end for each_entry of ep req */
2198                         }       /* end for else */
2199                 }       /* end for if(ep->queue) */
2200         }       /* end (ep->desc) */
2201 
2202         spin_unlock_irqrestore(&udc->lock, flags);
2203         return 0;
2204 }
2205 
2206 /*
2207  * seq_file wrappers for procfile show routines.
2208  */
2209 static int fsl_proc_open(struct inode *inode, struct file *file)
2210 {
2211         return single_open(file, fsl_proc_read, NULL);
2212 }
2213 
2214 static const struct file_operations fsl_proc_fops = {
2215         .open           = fsl_proc_open,
2216         .read           = seq_read,
2217         .llseek         = seq_lseek,
2218         .release        = single_release,
2219 };
2220 
2221 #define create_proc_file()      proc_create(proc_filename, 0, NULL, &fsl_proc_fops)
2222 #define remove_proc_file()      remove_proc_entry(proc_filename, NULL)
2223 
2224 #else                           /* !CONFIG_USB_GADGET_DEBUG_FILES */
2225 
2226 #define create_proc_file()      do {} while (0)
2227 #define remove_proc_file()      do {} while (0)
2228 
2229 #endif                          /* CONFIG_USB_GADGET_DEBUG_FILES */
2230 
2231 /*-------------------------------------------------------------------------*/
2232 
2233 /* Release udc structures */
2234 static void fsl_udc_release(struct device *dev)
2235 {
2236         complete(udc_controller->done);
2237         dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2238                         udc_controller->ep_qh, udc_controller->ep_qh_dma);
2239         kfree(udc_controller);
2240 }
2241 
2242 /******************************************************************
2243         Internal structure setup functions
2244 *******************************************************************/
2245 /*------------------------------------------------------------------
2246  * init resource for globle controller
2247  * Return the udc handle on success or NULL on failure
2248  ------------------------------------------------------------------*/
2249 static int __init struct_udc_setup(struct fsl_udc *udc,
2250                 struct platform_device *pdev)
2251 {
2252         struct fsl_usb2_platform_data *pdata;
2253         size_t size;
2254 
2255         pdata = dev_get_platdata(&pdev->dev);
2256         udc->phy_mode = pdata->phy_mode;
2257 
2258         udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2259         if (!udc->eps)
2260                 return -1;
2261 
2262         /* initialized QHs, take care of alignment */
2263         size = udc->max_ep * sizeof(struct ep_queue_head);
2264         if (size < QH_ALIGNMENT)
2265                 size = QH_ALIGNMENT;
2266         else if ((size % QH_ALIGNMENT) != 0) {
2267                 size += QH_ALIGNMENT + 1;
2268                 size &= ~(QH_ALIGNMENT - 1);
2269         }
2270         udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2271                                         &udc->ep_qh_dma, GFP_KERNEL);
2272         if (!udc->ep_qh) {
2273                 ERR("malloc QHs for udc failed\n");
2274                 kfree(udc->eps);
2275                 return -1;
2276         }
2277 
2278         udc->ep_qh_size = size;
2279 
2280         /* Initialize ep0 status request structure */
2281         /* FIXME: fsl_alloc_request() ignores ep argument */
2282         udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2283                         struct fsl_req, req);
2284         /* allocate a small amount of memory to get valid address */
2285         udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2286 
2287         udc->resume_state = USB_STATE_NOTATTACHED;
2288         udc->usb_state = USB_STATE_POWERED;
2289         udc->ep0_dir = 0;
2290         udc->remote_wakeup = 0; /* default to 0 on reset */
2291 
2292         return 0;
2293 }
2294 
2295 /*----------------------------------------------------------------
2296  * Setup the fsl_ep struct for eps
2297  * Link fsl_ep->ep to gadget->ep_list
2298  * ep0out is not used so do nothing here
2299  * ep0in should be taken care
2300  *--------------------------------------------------------------*/
2301 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2302                 char *name, int link)
2303 {
2304         struct fsl_ep *ep = &udc->eps[index];
2305 
2306         ep->udc = udc;
2307         strcpy(ep->name, name);
2308         ep->ep.name = ep->name;
2309 
2310         ep->ep.ops = &fsl_ep_ops;
2311         ep->stopped = 0;
2312 
2313         /* for ep0: maxP defined in desc
2314          * for other eps, maxP is set by epautoconfig() called by gadget layer
2315          */
2316         usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
2317 
2318         /* the queue lists any req for this ep */
2319         INIT_LIST_HEAD(&ep->queue);
2320 
2321         /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2322         if (link)
2323                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2324         ep->gadget = &udc->gadget;
2325         ep->qh = &udc->ep_qh[index];
2326 
2327         return 0;
2328 }
2329 
2330 /* Driver probe function
2331  * all intialization operations implemented here except enabling usb_intr reg
2332  * board setup should have been done in the platform code
2333  */
2334 static int __init fsl_udc_probe(struct platform_device *pdev)
2335 {
2336         struct fsl_usb2_platform_data *pdata;
2337         struct resource *res;
2338         int ret = -ENODEV;
2339         unsigned int i;
2340         u32 dccparams;
2341 
2342         udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2343         if (udc_controller == NULL)
2344                 return -ENOMEM;
2345 
2346         pdata = dev_get_platdata(&pdev->dev);
2347         udc_controller->pdata = pdata;
2348         spin_lock_init(&udc_controller->lock);
2349         udc_controller->stopped = 1;
2350 
2351 #ifdef CONFIG_USB_OTG
2352         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2353                 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2354                 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2355                         ERR("Can't find OTG driver!\n");
2356                         ret = -ENODEV;
2357                         goto err_kfree;
2358                 }
2359         }
2360 #endif
2361 
2362         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2363         if (!res) {
2364                 ret = -ENXIO;
2365                 goto err_kfree;
2366         }
2367 
2368         if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2369                 if (!request_mem_region(res->start, resource_size(res),
2370                                         driver_name)) {
2371                         ERR("request mem region for %s failed\n", pdev->name);
2372                         ret = -EBUSY;
2373                         goto err_kfree;
2374                 }
2375         }
2376 
2377         dr_regs = ioremap(res->start, resource_size(res));
2378         if (!dr_regs) {
2379                 ret = -ENOMEM;
2380                 goto err_release_mem_region;
2381         }
2382 
2383         pdata->regs = (void *)dr_regs;
2384 
2385         /*
2386          * do platform specific init: check the clock, grab/config pins, etc.
2387          */
2388         if (pdata->init && pdata->init(pdev)) {
2389                 ret = -ENODEV;
2390                 goto err_iounmap_noclk;
2391         }
2392 
2393         /* Set accessors only after pdata->init() ! */
2394         fsl_set_accessors(pdata);
2395 
2396 #ifndef CONFIG_ARCH_MXC
2397         if (pdata->have_sysif_regs)
2398                 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2399 #endif
2400 
2401         /* Initialize USB clocks */
2402         ret = fsl_udc_clk_init(pdev);
2403         if (ret < 0)
2404                 goto err_iounmap_noclk;
2405 
2406         /* Read Device Controller Capability Parameters register */
2407         dccparams = fsl_readl(&dr_regs->dccparams);
2408         if (!(dccparams & DCCPARAMS_DC)) {
2409                 ERR("This SOC doesn't support device role\n");
2410                 ret = -ENODEV;
2411                 goto err_iounmap;
2412         }
2413         /* Get max device endpoints */
2414         /* DEN is bidirectional ep number, max_ep doubles the number */
2415         udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2416 
2417         udc_controller->irq = platform_get_irq(pdev, 0);
2418         if (!udc_controller->irq) {
2419                 ret = -ENODEV;
2420                 goto err_iounmap;
2421         }
2422 
2423         ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2424                         driver_name, udc_controller);
2425         if (ret != 0) {
2426                 ERR("cannot request irq %d err %d\n",
2427                                 udc_controller->irq, ret);
2428                 goto err_iounmap;
2429         }
2430 
2431         /* Initialize the udc structure including QH member and other member */
2432         if (struct_udc_setup(udc_controller, pdev)) {
2433                 ERR("Can't initialize udc data structure\n");
2434                 ret = -ENOMEM;
2435                 goto err_free_irq;
2436         }
2437 
2438         if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2439                 /* initialize usb hw reg except for regs for EP,
2440                  * leave usbintr reg untouched */
2441                 dr_controller_setup(udc_controller);
2442         }
2443 
2444         ret = fsl_udc_clk_finalize(pdev);
2445         if (ret)
2446                 goto err_free_irq;
2447 
2448         /* Setup gadget structure */
2449         udc_controller->gadget.ops = &fsl_gadget_ops;
2450         udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2451         udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2452         INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2453         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2454         udc_controller->gadget.name = driver_name;
2455 
2456         /* Setup gadget.dev and register with kernel */
2457         dev_set_name(&udc_controller->gadget.dev, "gadget");
2458         udc_controller->gadget.dev.of_node = pdev->dev.of_node;
2459 
2460         if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2461                 udc_controller->gadget.is_otg = 1;
2462 
2463         /* setup QH and epctrl for ep0 */
2464         ep0_setup(udc_controller);
2465 
2466         /* setup udc->eps[] for ep0 */
2467         struct_ep_setup(udc_controller, 0, "ep0", 0);
2468         /* for ep0: the desc defined here;
2469          * for other eps, gadget layer called ep_enable with defined desc
2470          */
2471         udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
2472         usb_ep_set_maxpacket_limit(&udc_controller->eps[0].ep,
2473                                    USB_MAX_CTRL_PAYLOAD);
2474 
2475         /* setup the udc->eps[] for non-control endpoints and link
2476          * to gadget.ep_list */
2477         for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2478                 char name[14];
2479 
2480                 sprintf(name, "ep%dout", i);
2481                 struct_ep_setup(udc_controller, i * 2, name, 1);
2482                 sprintf(name, "ep%din", i);
2483                 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2484         }
2485 
2486         /* use dma_pool for TD management */
2487         udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2488                         sizeof(struct ep_td_struct),
2489                         DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2490         if (udc_controller->td_pool == NULL) {
2491                 ret = -ENOMEM;
2492                 goto err_free_irq;
2493         }
2494 
2495         ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
2496                         fsl_udc_release);
2497         if (ret)
2498                 goto err_del_udc;
2499 
2500         create_proc_file();
2501         return 0;
2502 
2503 err_del_udc:
2504         dma_pool_destroy(udc_controller->td_pool);
2505 err_free_irq:
2506         free_irq(udc_controller->irq, udc_controller);
2507 err_iounmap:
2508         if (pdata->exit)
2509                 pdata->exit(pdev);
2510         fsl_udc_clk_release();
2511 err_iounmap_noclk:
2512         iounmap(dr_regs);
2513 err_release_mem_region:
2514         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2515                 release_mem_region(res->start, resource_size(res));
2516 err_kfree:
2517         kfree(udc_controller);
2518         udc_controller = NULL;
2519         return ret;
2520 }
2521 
2522 /* Driver removal function
2523  * Free resources and finish pending transactions
2524  */
2525 static int __exit fsl_udc_remove(struct platform_device *pdev)
2526 {
2527         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2528         struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
2529 
2530         DECLARE_COMPLETION(done);
2531 
2532         if (!udc_controller)
2533                 return -ENODEV;
2534 
2535         udc_controller->done = &done;
2536         usb_del_gadget_udc(&udc_controller->gadget);
2537 
2538         fsl_udc_clk_release();
2539 
2540         /* DR has been stopped in usb_gadget_unregister_driver() */
2541         remove_proc_file();
2542 
2543         /* Free allocated memory */
2544         kfree(udc_controller->status_req->req.buf);
2545         kfree(udc_controller->status_req);
2546         kfree(udc_controller->eps);
2547 
2548         dma_pool_destroy(udc_controller->td_pool);
2549         free_irq(udc_controller->irq, udc_controller);
2550         iounmap(dr_regs);
2551         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2552                 release_mem_region(res->start, resource_size(res));
2553 
2554         /* free udc --wait for the release() finished */
2555         wait_for_completion(&done);
2556 
2557         /*
2558          * do platform specific un-initialization:
2559          * release iomux pins, etc.
2560          */
2561         if (pdata->exit)
2562                 pdata->exit(pdev);
2563 
2564         return 0;
2565 }
2566 
2567 /*-----------------------------------------------------------------
2568  * Modify Power management attributes
2569  * Used by OTG statemachine to disable gadget temporarily
2570  -----------------------------------------------------------------*/
2571 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2572 {
2573         dr_controller_stop(udc_controller);
2574         return 0;
2575 }
2576 
2577 /*-----------------------------------------------------------------
2578  * Invoked on USB resume. May be called in_interrupt.
2579  * Here we start the DR controller and enable the irq
2580  *-----------------------------------------------------------------*/
2581 static int fsl_udc_resume(struct platform_device *pdev)
2582 {
2583         /* Enable DR irq reg and set controller Run */
2584         if (udc_controller->stopped) {
2585                 dr_controller_setup(udc_controller);
2586                 dr_controller_run(udc_controller);
2587         }
2588         udc_controller->usb_state = USB_STATE_ATTACHED;
2589         udc_controller->ep0_state = WAIT_FOR_SETUP;
2590         udc_controller->ep0_dir = 0;
2591         return 0;
2592 }
2593 
2594 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2595 {
2596         struct fsl_udc *udc = udc_controller;
2597         u32 mode, usbcmd;
2598 
2599         mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2600 
2601         pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2602 
2603         /*
2604          * If the controller is already stopped, then this must be a
2605          * PM suspend.  Remember this fact, so that we will leave the
2606          * controller stopped at PM resume time.
2607          */
2608         if (udc->stopped) {
2609                 pr_debug("gadget already stopped, leaving early\n");
2610                 udc->already_stopped = 1;
2611                 return 0;
2612         }
2613 
2614         if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2615                 pr_debug("gadget not in device mode, leaving early\n");
2616                 return 0;
2617         }
2618 
2619         /* stop the controller */
2620         usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2621         fsl_writel(usbcmd, &dr_regs->usbcmd);
2622 
2623         udc->stopped = 1;
2624 
2625         pr_info("USB Gadget suspended\n");
2626 
2627         return 0;
2628 }
2629 
2630 static int fsl_udc_otg_resume(struct device *dev)
2631 {
2632         pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
2633                  udc_controller->stopped, udc_controller->already_stopped);
2634 
2635         /*
2636          * If the controller was stopped at suspend time, then
2637          * don't resume it now.
2638          */
2639         if (udc_controller->already_stopped) {
2640                 udc_controller->already_stopped = 0;
2641                 pr_debug("gadget was already stopped, leaving early\n");
2642                 return 0;
2643         }
2644 
2645         pr_info("USB Gadget resume\n");
2646 
2647         return fsl_udc_resume(NULL);
2648 }
2649 /*-------------------------------------------------------------------------
2650         Register entry point for the peripheral controller driver
2651 --------------------------------------------------------------------------*/
2652 static const struct platform_device_id fsl_udc_devtype[] = {
2653         {
2654                 .name = "imx-udc-mx27",
2655         }, {
2656                 .name = "imx-udc-mx51",
2657         }, {
2658                 /* sentinel */
2659         }
2660 };
2661 MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
2662 static struct platform_driver udc_driver = {
2663         .remove         = __exit_p(fsl_udc_remove),
2664         /* Just for FSL i.mx SoC currently */
2665         .id_table       = fsl_udc_devtype,
2666         /* these suspend and resume are not usb suspend and resume */
2667         .suspend        = fsl_udc_suspend,
2668         .resume         = fsl_udc_resume,
2669         .driver         = {
2670                         .name = driver_name,
2671                         .owner = THIS_MODULE,
2672                         /* udc suspend/resume called from OTG driver */
2673                         .suspend = fsl_udc_otg_suspend,
2674                         .resume  = fsl_udc_otg_resume,
2675         },
2676 };
2677 
2678 module_platform_driver_probe(udc_driver, fsl_udc_probe);
2679 
2680 MODULE_DESCRIPTION(DRIVER_DESC);
2681 MODULE_AUTHOR(DRIVER_AUTHOR);
2682 MODULE_LICENSE("GPL");
2683 MODULE_ALIAS("platform:fsl-usb2-udc");
2684 

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