Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/usb/gadget/amd5536udc.c

  1 /*
  2  * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
  3  *
  4  * Copyright (C) 2005-2007 AMD (http://www.amd.com)
  5  * Author: Thomas Dahlmann
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  */
 12 
 13 /*
 14  * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
 15  * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
 16  * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
 17  *
 18  * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
 19  * be used as host port) and UOC bits PAD_EN and APU are set (should be done
 20  * by BIOS init).
 21  *
 22  * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
 23  * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
 24  * can be used with gadget ether.
 25  */
 26 
 27 /* debug control */
 28 /* #define UDC_VERBOSE */
 29 
 30 /* Driver strings */
 31 #define UDC_MOD_DESCRIPTION             "AMD 5536 UDC - USB Device Controller"
 32 #define UDC_DRIVER_VERSION_STRING       "01.00.0206"
 33 
 34 /* system */
 35 #include <linux/module.h>
 36 #include <linux/pci.h>
 37 #include <linux/kernel.h>
 38 #include <linux/delay.h>
 39 #include <linux/ioport.h>
 40 #include <linux/sched.h>
 41 #include <linux/slab.h>
 42 #include <linux/errno.h>
 43 #include <linux/timer.h>
 44 #include <linux/list.h>
 45 #include <linux/interrupt.h>
 46 #include <linux/ioctl.h>
 47 #include <linux/fs.h>
 48 #include <linux/dmapool.h>
 49 #include <linux/moduleparam.h>
 50 #include <linux/device.h>
 51 #include <linux/io.h>
 52 #include <linux/irq.h>
 53 #include <linux/prefetch.h>
 54 
 55 #include <asm/byteorder.h>
 56 #include <asm/unaligned.h>
 57 
 58 /* gadget stack */
 59 #include <linux/usb/ch9.h>
 60 #include <linux/usb/gadget.h>
 61 
 62 /* udc specific */
 63 #include "amd5536udc.h"
 64 
 65 
 66 static void udc_tasklet_disconnect(unsigned long);
 67 static void empty_req_queue(struct udc_ep *);
 68 static int udc_probe(struct udc *dev);
 69 static void udc_basic_init(struct udc *dev);
 70 static void udc_setup_endpoints(struct udc *dev);
 71 static void udc_soft_reset(struct udc *dev);
 72 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
 73 static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
 74 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req);
 75 static int udc_create_dma_chain(struct udc_ep *ep, struct udc_request *req,
 76                                 unsigned long buf_len, gfp_t gfp_flags);
 77 static int udc_remote_wakeup(struct udc *dev);
 78 static int udc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
 79 static void udc_pci_remove(struct pci_dev *pdev);
 80 
 81 /* description */
 82 static const char mod_desc[] = UDC_MOD_DESCRIPTION;
 83 static const char name[] = "amd5536udc";
 84 
 85 /* structure to hold endpoint function pointers */
 86 static const struct usb_ep_ops udc_ep_ops;
 87 
 88 /* received setup data */
 89 static union udc_setup_data setup_data;
 90 
 91 /* pointer to device object */
 92 static struct udc *udc;
 93 
 94 /* irq spin lock for soft reset */
 95 static DEFINE_SPINLOCK(udc_irq_spinlock);
 96 /* stall spin lock */
 97 static DEFINE_SPINLOCK(udc_stall_spinlock);
 98 
 99 /*
100 * slave mode: pending bytes in rx fifo after nyet,
101 * used if EPIN irq came but no req was available
102 */
103 static unsigned int udc_rxfifo_pending;
104 
105 /* count soft resets after suspend to avoid loop */
106 static int soft_reset_occured;
107 static int soft_reset_after_usbreset_occured;
108 
109 /* timer */
110 static struct timer_list udc_timer;
111 static int stop_timer;
112 
113 /* set_rde -- Is used to control enabling of RX DMA. Problem is
114  * that UDC has only one bit (RDE) to enable/disable RX DMA for
115  * all OUT endpoints. So we have to handle race conditions like
116  * when OUT data reaches the fifo but no request was queued yet.
117  * This cannot be solved by letting the RX DMA disabled until a
118  * request gets queued because there may be other OUT packets
119  * in the FIFO (important for not blocking control traffic).
120  * The value of set_rde controls the correspondig timer.
121  *
122  * set_rde -1 == not used, means it is alloed to be set to 0 or 1
123  * set_rde  0 == do not touch RDE, do no start the RDE timer
124  * set_rde  1 == timer function will look whether FIFO has data
125  * set_rde  2 == set by timer function to enable RX DMA on next call
126  */
127 static int set_rde = -1;
128 
129 static DECLARE_COMPLETION(on_exit);
130 static struct timer_list udc_pollstall_timer;
131 static int stop_pollstall_timer;
132 static DECLARE_COMPLETION(on_pollstall_exit);
133 
134 /* tasklet for usb disconnect */
135 static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
136                 (unsigned long) &udc);
137 
138 
139 /* endpoint names used for print */
140 static const char ep0_string[] = "ep0in";
141 static const char *const ep_string[] = {
142         ep0_string,
143         "ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk",
144         "ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk",
145         "ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk",
146         "ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk",
147         "ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk",
148         "ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk",
149         "ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk"
150 };
151 
152 /* DMA usage flag */
153 static bool use_dma = 1;
154 /* packet per buffer dma */
155 static bool use_dma_ppb = 1;
156 /* with per descr. update */
157 static bool use_dma_ppb_du;
158 /* buffer fill mode */
159 static int use_dma_bufferfill_mode;
160 /* full speed only mode */
161 static bool use_fullspeed;
162 /* tx buffer size for high speed */
163 static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
164 
165 /* module parameters */
166 module_param(use_dma, bool, S_IRUGO);
167 MODULE_PARM_DESC(use_dma, "true for DMA");
168 module_param(use_dma_ppb, bool, S_IRUGO);
169 MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
170 module_param(use_dma_ppb_du, bool, S_IRUGO);
171 MODULE_PARM_DESC(use_dma_ppb_du,
172         "true for DMA in packet per buffer mode with descriptor update");
173 module_param(use_fullspeed, bool, S_IRUGO);
174 MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
175 
176 /*---------------------------------------------------------------------------*/
177 /* Prints UDC device registers and endpoint irq registers */
178 static void print_regs(struct udc *dev)
179 {
180         DBG(dev, "------- Device registers -------\n");
181         DBG(dev, "dev config     = %08x\n", readl(&dev->regs->cfg));
182         DBG(dev, "dev control    = %08x\n", readl(&dev->regs->ctl));
183         DBG(dev, "dev status     = %08x\n", readl(&dev->regs->sts));
184         DBG(dev, "\n");
185         DBG(dev, "dev int's      = %08x\n", readl(&dev->regs->irqsts));
186         DBG(dev, "dev intmask    = %08x\n", readl(&dev->regs->irqmsk));
187         DBG(dev, "\n");
188         DBG(dev, "dev ep int's   = %08x\n", readl(&dev->regs->ep_irqsts));
189         DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
190         DBG(dev, "\n");
191         DBG(dev, "USE DMA        = %d\n", use_dma);
192         if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
193                 DBG(dev, "DMA mode       = PPBNDU (packet per buffer "
194                         "WITHOUT desc. update)\n");
195                 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBNDU");
196         } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
197                 DBG(dev, "DMA mode       = PPBDU (packet per buffer "
198                         "WITH desc. update)\n");
199                 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBDU");
200         }
201         if (use_dma && use_dma_bufferfill_mode) {
202                 DBG(dev, "DMA mode       = BF (buffer fill mode)\n");
203                 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "BF");
204         }
205         if (!use_dma)
206                 dev_info(&dev->pdev->dev, "FIFO mode\n");
207         DBG(dev, "-------------------------------------------------------\n");
208 }
209 
210 /* Masks unused interrupts */
211 static int udc_mask_unused_interrupts(struct udc *dev)
212 {
213         u32 tmp;
214 
215         /* mask all dev interrupts */
216         tmp =   AMD_BIT(UDC_DEVINT_SVC) |
217                 AMD_BIT(UDC_DEVINT_ENUM) |
218                 AMD_BIT(UDC_DEVINT_US) |
219                 AMD_BIT(UDC_DEVINT_UR) |
220                 AMD_BIT(UDC_DEVINT_ES) |
221                 AMD_BIT(UDC_DEVINT_SI) |
222                 AMD_BIT(UDC_DEVINT_SOF)|
223                 AMD_BIT(UDC_DEVINT_SC);
224         writel(tmp, &dev->regs->irqmsk);
225 
226         /* mask all ep interrupts */
227         writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
228 
229         return 0;
230 }
231 
232 /* Enables endpoint 0 interrupts */
233 static int udc_enable_ep0_interrupts(struct udc *dev)
234 {
235         u32 tmp;
236 
237         DBG(dev, "udc_enable_ep0_interrupts()\n");
238 
239         /* read irq mask */
240         tmp = readl(&dev->regs->ep_irqmsk);
241         /* enable ep0 irq's */
242         tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
243                 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
244         writel(tmp, &dev->regs->ep_irqmsk);
245 
246         return 0;
247 }
248 
249 /* Enables device interrupts for SET_INTF and SET_CONFIG */
250 static int udc_enable_dev_setup_interrupts(struct udc *dev)
251 {
252         u32 tmp;
253 
254         DBG(dev, "enable device interrupts for setup data\n");
255 
256         /* read irq mask */
257         tmp = readl(&dev->regs->irqmsk);
258 
259         /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
260         tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
261                 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
262                 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
263                 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
264                 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
265         writel(tmp, &dev->regs->irqmsk);
266 
267         return 0;
268 }
269 
270 /* Calculates fifo start of endpoint based on preceding endpoints */
271 static int udc_set_txfifo_addr(struct udc_ep *ep)
272 {
273         struct udc      *dev;
274         u32 tmp;
275         int i;
276 
277         if (!ep || !(ep->in))
278                 return -EINVAL;
279 
280         dev = ep->dev;
281         ep->txfifo = dev->txfifo;
282 
283         /* traverse ep's */
284         for (i = 0; i < ep->num; i++) {
285                 if (dev->ep[i].regs) {
286                         /* read fifo size */
287                         tmp = readl(&dev->ep[i].regs->bufin_framenum);
288                         tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
289                         ep->txfifo += tmp;
290                 }
291         }
292         return 0;
293 }
294 
295 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
296 static u32 cnak_pending;
297 
298 static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
299 {
300         if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
301                 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
302                 cnak_pending |= 1 << (num);
303                 ep->naking = 1;
304         } else
305                 cnak_pending = cnak_pending & (~(1 << (num)));
306 }
307 
308 
309 /* Enables endpoint, is called by gadget driver */
310 static int
311 udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
312 {
313         struct udc_ep           *ep;
314         struct udc              *dev;
315         u32                     tmp;
316         unsigned long           iflags;
317         u8 udc_csr_epix;
318         unsigned                maxpacket;
319 
320         if (!usbep
321                         || usbep->name == ep0_string
322                         || !desc
323                         || desc->bDescriptorType != USB_DT_ENDPOINT)
324                 return -EINVAL;
325 
326         ep = container_of(usbep, struct udc_ep, ep);
327         dev = ep->dev;
328 
329         DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
330 
331         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
332                 return -ESHUTDOWN;
333 
334         spin_lock_irqsave(&dev->lock, iflags);
335         ep->ep.desc = desc;
336 
337         ep->halted = 0;
338 
339         /* set traffic type */
340         tmp = readl(&dev->ep[ep->num].regs->ctl);
341         tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
342         writel(tmp, &dev->ep[ep->num].regs->ctl);
343 
344         /* set max packet size */
345         maxpacket = usb_endpoint_maxp(desc);
346         tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
347         tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
348         ep->ep.maxpacket = maxpacket;
349         writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
350 
351         /* IN ep */
352         if (ep->in) {
353 
354                 /* ep ix in UDC CSR register space */
355                 udc_csr_epix = ep->num;
356 
357                 /* set buffer size (tx fifo entries) */
358                 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
359                 /* double buffering: fifo size = 2 x max packet size */
360                 tmp = AMD_ADDBITS(
361                                 tmp,
362                                 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
363                                           / UDC_DWORD_BYTES,
364                                 UDC_EPIN_BUFF_SIZE);
365                 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
366 
367                 /* calc. tx fifo base addr */
368                 udc_set_txfifo_addr(ep);
369 
370                 /* flush fifo */
371                 tmp = readl(&ep->regs->ctl);
372                 tmp |= AMD_BIT(UDC_EPCTL_F);
373                 writel(tmp, &ep->regs->ctl);
374 
375         /* OUT ep */
376         } else {
377                 /* ep ix in UDC CSR register space */
378                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
379 
380                 /* set max packet size UDC CSR  */
381                 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
382                 tmp = AMD_ADDBITS(tmp, maxpacket,
383                                         UDC_CSR_NE_MAX_PKT);
384                 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
385 
386                 if (use_dma && !ep->in) {
387                         /* alloc and init BNA dummy request */
388                         ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
389                         ep->bna_occurred = 0;
390                 }
391 
392                 if (ep->num != UDC_EP0OUT_IX)
393                         dev->data_ep_enabled = 1;
394         }
395 
396         /* set ep values */
397         tmp = readl(&dev->csr->ne[udc_csr_epix]);
398         /* max packet */
399         tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
400         /* ep number */
401         tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
402         /* ep direction */
403         tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
404         /* ep type */
405         tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
406         /* ep config */
407         tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
408         /* ep interface */
409         tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
410         /* ep alt */
411         tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
412         /* write reg */
413         writel(tmp, &dev->csr->ne[udc_csr_epix]);
414 
415         /* enable ep irq */
416         tmp = readl(&dev->regs->ep_irqmsk);
417         tmp &= AMD_UNMASK_BIT(ep->num);
418         writel(tmp, &dev->regs->ep_irqmsk);
419 
420         /*
421          * clear NAK by writing CNAK
422          * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
423          */
424         if (!use_dma || ep->in) {
425                 tmp = readl(&ep->regs->ctl);
426                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
427                 writel(tmp, &ep->regs->ctl);
428                 ep->naking = 0;
429                 UDC_QUEUE_CNAK(ep, ep->num);
430         }
431         tmp = desc->bEndpointAddress;
432         DBG(dev, "%s enabled\n", usbep->name);
433 
434         spin_unlock_irqrestore(&dev->lock, iflags);
435         return 0;
436 }
437 
438 /* Resets endpoint */
439 static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
440 {
441         u32             tmp;
442 
443         VDBG(ep->dev, "ep-%d reset\n", ep->num);
444         ep->ep.desc = NULL;
445         ep->ep.ops = &udc_ep_ops;
446         INIT_LIST_HEAD(&ep->queue);
447 
448         usb_ep_set_maxpacket_limit(&ep->ep,(u16) ~0);
449         /* set NAK */
450         tmp = readl(&ep->regs->ctl);
451         tmp |= AMD_BIT(UDC_EPCTL_SNAK);
452         writel(tmp, &ep->regs->ctl);
453         ep->naking = 1;
454 
455         /* disable interrupt */
456         tmp = readl(&regs->ep_irqmsk);
457         tmp |= AMD_BIT(ep->num);
458         writel(tmp, &regs->ep_irqmsk);
459 
460         if (ep->in) {
461                 /* unset P and IN bit of potential former DMA */
462                 tmp = readl(&ep->regs->ctl);
463                 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
464                 writel(tmp, &ep->regs->ctl);
465 
466                 tmp = readl(&ep->regs->sts);
467                 tmp |= AMD_BIT(UDC_EPSTS_IN);
468                 writel(tmp, &ep->regs->sts);
469 
470                 /* flush the fifo */
471                 tmp = readl(&ep->regs->ctl);
472                 tmp |= AMD_BIT(UDC_EPCTL_F);
473                 writel(tmp, &ep->regs->ctl);
474 
475         }
476         /* reset desc pointer */
477         writel(0, &ep->regs->desptr);
478 }
479 
480 /* Disables endpoint, is called by gadget driver */
481 static int udc_ep_disable(struct usb_ep *usbep)
482 {
483         struct udc_ep   *ep = NULL;
484         unsigned long   iflags;
485 
486         if (!usbep)
487                 return -EINVAL;
488 
489         ep = container_of(usbep, struct udc_ep, ep);
490         if (usbep->name == ep0_string || !ep->ep.desc)
491                 return -EINVAL;
492 
493         DBG(ep->dev, "Disable ep-%d\n", ep->num);
494 
495         spin_lock_irqsave(&ep->dev->lock, iflags);
496         udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
497         empty_req_queue(ep);
498         ep_init(ep->dev->regs, ep);
499         spin_unlock_irqrestore(&ep->dev->lock, iflags);
500 
501         return 0;
502 }
503 
504 /* Allocates request packet, called by gadget driver */
505 static struct usb_request *
506 udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
507 {
508         struct udc_request      *req;
509         struct udc_data_dma     *dma_desc;
510         struct udc_ep   *ep;
511 
512         if (!usbep)
513                 return NULL;
514 
515         ep = container_of(usbep, struct udc_ep, ep);
516 
517         VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
518         req = kzalloc(sizeof(struct udc_request), gfp);
519         if (!req)
520                 return NULL;
521 
522         req->req.dma = DMA_DONT_USE;
523         INIT_LIST_HEAD(&req->queue);
524 
525         if (ep->dma) {
526                 /* ep0 in requests are allocated from data pool here */
527                 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
528                                                 &req->td_phys);
529                 if (!dma_desc) {
530                         kfree(req);
531                         return NULL;
532                 }
533 
534                 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
535                                 "td_phys = %lx\n",
536                                 req, dma_desc,
537                                 (unsigned long)req->td_phys);
538                 /* prevent from using desc. - set HOST BUSY */
539                 dma_desc->status = AMD_ADDBITS(dma_desc->status,
540                                                 UDC_DMA_STP_STS_BS_HOST_BUSY,
541                                                 UDC_DMA_STP_STS_BS);
542                 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
543                 req->td_data = dma_desc;
544                 req->td_data_last = NULL;
545                 req->chain_len = 1;
546         }
547 
548         return &req->req;
549 }
550 
551 /* Frees request packet, called by gadget driver */
552 static void
553 udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
554 {
555         struct udc_ep   *ep;
556         struct udc_request      *req;
557 
558         if (!usbep || !usbreq)
559                 return;
560 
561         ep = container_of(usbep, struct udc_ep, ep);
562         req = container_of(usbreq, struct udc_request, req);
563         VDBG(ep->dev, "free_req req=%p\n", req);
564         BUG_ON(!list_empty(&req->queue));
565         if (req->td_data) {
566                 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
567 
568                 /* free dma chain if created */
569                 if (req->chain_len > 1)
570                         udc_free_dma_chain(ep->dev, req);
571 
572                 pci_pool_free(ep->dev->data_requests, req->td_data,
573                                                         req->td_phys);
574         }
575         kfree(req);
576 }
577 
578 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
579 static void udc_init_bna_dummy(struct udc_request *req)
580 {
581         if (req) {
582                 /* set last bit */
583                 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
584                 /* set next pointer to itself */
585                 req->td_data->next = req->td_phys;
586                 /* set HOST BUSY */
587                 req->td_data->status
588                         = AMD_ADDBITS(req->td_data->status,
589                                         UDC_DMA_STP_STS_BS_DMA_DONE,
590                                         UDC_DMA_STP_STS_BS);
591 #ifdef UDC_VERBOSE
592                 pr_debug("bna desc = %p, sts = %08x\n",
593                         req->td_data, req->td_data->status);
594 #endif
595         }
596 }
597 
598 /* Allocate BNA dummy descriptor */
599 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
600 {
601         struct udc_request *req = NULL;
602         struct usb_request *_req = NULL;
603 
604         /* alloc the dummy request */
605         _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
606         if (_req) {
607                 req = container_of(_req, struct udc_request, req);
608                 ep->bna_dummy_req = req;
609                 udc_init_bna_dummy(req);
610         }
611         return req;
612 }
613 
614 /* Write data to TX fifo for IN packets */
615 static void
616 udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
617 {
618         u8                      *req_buf;
619         u32                     *buf;
620         int                     i, j;
621         unsigned                bytes = 0;
622         unsigned                remaining = 0;
623 
624         if (!req || !ep)
625                 return;
626 
627         req_buf = req->buf + req->actual;
628         prefetch(req_buf);
629         remaining = req->length - req->actual;
630 
631         buf = (u32 *) req_buf;
632 
633         bytes = ep->ep.maxpacket;
634         if (bytes > remaining)
635                 bytes = remaining;
636 
637         /* dwords first */
638         for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
639                 writel(*(buf + i), ep->txfifo);
640 
641         /* remaining bytes must be written by byte access */
642         for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
643                 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
644                                                         ep->txfifo);
645         }
646 
647         /* dummy write confirm */
648         writel(0, &ep->regs->confirm);
649 }
650 
651 /* Read dwords from RX fifo for OUT transfers */
652 static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
653 {
654         int i;
655 
656         VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
657 
658         for (i = 0; i < dwords; i++)
659                 *(buf + i) = readl(dev->rxfifo);
660         return 0;
661 }
662 
663 /* Read bytes from RX fifo for OUT transfers */
664 static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
665 {
666         int i, j;
667         u32 tmp;
668 
669         VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
670 
671         /* dwords first */
672         for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
673                 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
674 
675         /* remaining bytes must be read by byte access */
676         if (bytes % UDC_DWORD_BYTES) {
677                 tmp = readl(dev->rxfifo);
678                 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
679                         *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
680                         tmp = tmp >> UDC_BITS_PER_BYTE;
681                 }
682         }
683 
684         return 0;
685 }
686 
687 /* Read data from RX fifo for OUT transfers */
688 static int
689 udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
690 {
691         u8 *buf;
692         unsigned buf_space;
693         unsigned bytes = 0;
694         unsigned finished = 0;
695 
696         /* received number bytes */
697         bytes = readl(&ep->regs->sts);
698         bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
699 
700         buf_space = req->req.length - req->req.actual;
701         buf = req->req.buf + req->req.actual;
702         if (bytes > buf_space) {
703                 if ((buf_space % ep->ep.maxpacket) != 0) {
704                         DBG(ep->dev,
705                                 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
706                                 ep->ep.name, bytes, buf_space);
707                         req->req.status = -EOVERFLOW;
708                 }
709                 bytes = buf_space;
710         }
711         req->req.actual += bytes;
712 
713         /* last packet ? */
714         if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
715                 || ((req->req.actual == req->req.length) && !req->req.zero))
716                 finished = 1;
717 
718         /* read rx fifo bytes */
719         VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
720         udc_rxfifo_read_bytes(ep->dev, buf, bytes);
721 
722         return finished;
723 }
724 
725 /* create/re-init a DMA descriptor or a DMA descriptor chain */
726 static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
727 {
728         int     retval = 0;
729         u32     tmp;
730 
731         VDBG(ep->dev, "prep_dma\n");
732         VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
733                         ep->num, req->td_data);
734 
735         /* set buffer pointer */
736         req->td_data->bufptr = req->req.dma;
737 
738         /* set last bit */
739         req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
740 
741         /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
742         if (use_dma_ppb) {
743 
744                 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
745                 if (retval != 0) {
746                         if (retval == -ENOMEM)
747                                 DBG(ep->dev, "Out of DMA memory\n");
748                         return retval;
749                 }
750                 if (ep->in) {
751                         if (req->req.length == ep->ep.maxpacket) {
752                                 /* write tx bytes */
753                                 req->td_data->status =
754                                         AMD_ADDBITS(req->td_data->status,
755                                                 ep->ep.maxpacket,
756                                                 UDC_DMA_IN_STS_TXBYTES);
757 
758                         }
759                 }
760 
761         }
762 
763         if (ep->in) {
764                 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
765                                 "maxpacket=%d ep%d\n",
766                                 use_dma_ppb, req->req.length,
767                                 ep->ep.maxpacket, ep->num);
768                 /*
769                  * if bytes < max packet then tx bytes must
770                  * be written in packet per buffer mode
771                  */
772                 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
773                                 || ep->num == UDC_EP0OUT_IX
774                                 || ep->num == UDC_EP0IN_IX) {
775                         /* write tx bytes */
776                         req->td_data->status =
777                                 AMD_ADDBITS(req->td_data->status,
778                                                 req->req.length,
779                                                 UDC_DMA_IN_STS_TXBYTES);
780                         /* reset frame num */
781                         req->td_data->status =
782                                 AMD_ADDBITS(req->td_data->status,
783                                                 0,
784                                                 UDC_DMA_IN_STS_FRAMENUM);
785                 }
786                 /* set HOST BUSY */
787                 req->td_data->status =
788                         AMD_ADDBITS(req->td_data->status,
789                                 UDC_DMA_STP_STS_BS_HOST_BUSY,
790                                 UDC_DMA_STP_STS_BS);
791         } else {
792                 VDBG(ep->dev, "OUT set host ready\n");
793                 /* set HOST READY */
794                 req->td_data->status =
795                         AMD_ADDBITS(req->td_data->status,
796                                 UDC_DMA_STP_STS_BS_HOST_READY,
797                                 UDC_DMA_STP_STS_BS);
798 
799 
800                         /* clear NAK by writing CNAK */
801                         if (ep->naking) {
802                                 tmp = readl(&ep->regs->ctl);
803                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
804                                 writel(tmp, &ep->regs->ctl);
805                                 ep->naking = 0;
806                                 UDC_QUEUE_CNAK(ep, ep->num);
807                         }
808 
809         }
810 
811         return retval;
812 }
813 
814 /* Completes request packet ... caller MUST hold lock */
815 static void
816 complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
817 __releases(ep->dev->lock)
818 __acquires(ep->dev->lock)
819 {
820         struct udc              *dev;
821         unsigned                halted;
822 
823         VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
824 
825         dev = ep->dev;
826         /* unmap DMA */
827         if (ep->dma)
828                 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in);
829 
830         halted = ep->halted;
831         ep->halted = 1;
832 
833         /* set new status if pending */
834         if (req->req.status == -EINPROGRESS)
835                 req->req.status = sts;
836 
837         /* remove from ep queue */
838         list_del_init(&req->queue);
839 
840         VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
841                 &req->req, req->req.length, ep->ep.name, sts);
842 
843         spin_unlock(&dev->lock);
844         req->req.complete(&ep->ep, &req->req);
845         spin_lock(&dev->lock);
846         ep->halted = halted;
847 }
848 
849 /* frees pci pool descriptors of a DMA chain */
850 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req)
851 {
852 
853         int ret_val = 0;
854         struct udc_data_dma     *td;
855         struct udc_data_dma     *td_last = NULL;
856         unsigned int i;
857 
858         DBG(dev, "free chain req = %p\n", req);
859 
860         /* do not free first desc., will be done by free for request */
861         td_last = req->td_data;
862         td = phys_to_virt(td_last->next);
863 
864         for (i = 1; i < req->chain_len; i++) {
865 
866                 pci_pool_free(dev->data_requests, td,
867                                 (dma_addr_t) td_last->next);
868                 td_last = td;
869                 td = phys_to_virt(td_last->next);
870         }
871 
872         return ret_val;
873 }
874 
875 /* Iterates to the end of a DMA chain and returns last descriptor */
876 static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
877 {
878         struct udc_data_dma     *td;
879 
880         td = req->td_data;
881         while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L)))
882                 td = phys_to_virt(td->next);
883 
884         return td;
885 
886 }
887 
888 /* Iterates to the end of a DMA chain and counts bytes received */
889 static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
890 {
891         struct udc_data_dma     *td;
892         u32 count;
893 
894         td = req->td_data;
895         /* received number bytes */
896         count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
897 
898         while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
899                 td = phys_to_virt(td->next);
900                 /* received number bytes */
901                 if (td) {
902                         count += AMD_GETBITS(td->status,
903                                 UDC_DMA_OUT_STS_RXBYTES);
904                 }
905         }
906 
907         return count;
908 
909 }
910 
911 /* Creates or re-inits a DMA chain */
912 static int udc_create_dma_chain(
913         struct udc_ep *ep,
914         struct udc_request *req,
915         unsigned long buf_len, gfp_t gfp_flags
916 )
917 {
918         unsigned long bytes = req->req.length;
919         unsigned int i;
920         dma_addr_t dma_addr;
921         struct udc_data_dma     *td = NULL;
922         struct udc_data_dma     *last = NULL;
923         unsigned long txbytes;
924         unsigned create_new_chain = 0;
925         unsigned len;
926 
927         VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
928                         bytes, buf_len);
929         dma_addr = DMA_DONT_USE;
930 
931         /* unset L bit in first desc for OUT */
932         if (!ep->in)
933                 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
934 
935         /* alloc only new desc's if not already available */
936         len = req->req.length / ep->ep.maxpacket;
937         if (req->req.length % ep->ep.maxpacket)
938                 len++;
939 
940         if (len > req->chain_len) {
941                 /* shorter chain already allocated before */
942                 if (req->chain_len > 1)
943                         udc_free_dma_chain(ep->dev, req);
944                 req->chain_len = len;
945                 create_new_chain = 1;
946         }
947 
948         td = req->td_data;
949         /* gen. required number of descriptors and buffers */
950         for (i = buf_len; i < bytes; i += buf_len) {
951                 /* create or determine next desc. */
952                 if (create_new_chain) {
953 
954                         td = pci_pool_alloc(ep->dev->data_requests,
955                                         gfp_flags, &dma_addr);
956                         if (!td)
957                                 return -ENOMEM;
958 
959                         td->status = 0;
960                 } else if (i == buf_len) {
961                         /* first td */
962                         td = (struct udc_data_dma *) phys_to_virt(
963                                                 req->td_data->next);
964                         td->status = 0;
965                 } else {
966                         td = (struct udc_data_dma *) phys_to_virt(last->next);
967                         td->status = 0;
968                 }
969 
970 
971                 if (td)
972                         td->bufptr = req->req.dma + i; /* assign buffer */
973                 else
974                         break;
975 
976                 /* short packet ? */
977                 if ((bytes - i) >= buf_len) {
978                         txbytes = buf_len;
979                 } else {
980                         /* short packet */
981                         txbytes = bytes - i;
982                 }
983 
984                 /* link td and assign tx bytes */
985                 if (i == buf_len) {
986                         if (create_new_chain)
987                                 req->td_data->next = dma_addr;
988                         /*
989                         else
990                                 req->td_data->next = virt_to_phys(td);
991                         */
992                         /* write tx bytes */
993                         if (ep->in) {
994                                 /* first desc */
995                                 req->td_data->status =
996                                         AMD_ADDBITS(req->td_data->status,
997                                                         ep->ep.maxpacket,
998                                                         UDC_DMA_IN_STS_TXBYTES);
999                                 /* second desc */
1000                                 td->status = AMD_ADDBITS(td->status,
1001                                                         txbytes,
1002                                                         UDC_DMA_IN_STS_TXBYTES);
1003                         }
1004                 } else {
1005                         if (create_new_chain)
1006                                 last->next = dma_addr;
1007                         /*
1008                         else
1009                                 last->next = virt_to_phys(td);
1010                         */
1011                         if (ep->in) {
1012                                 /* write tx bytes */
1013                                 td->status = AMD_ADDBITS(td->status,
1014                                                         txbytes,
1015                                                         UDC_DMA_IN_STS_TXBYTES);
1016                         }
1017                 }
1018                 last = td;
1019         }
1020         /* set last bit */
1021         if (td) {
1022                 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
1023                 /* last desc. points to itself */
1024                 req->td_data_last = td;
1025         }
1026 
1027         return 0;
1028 }
1029 
1030 /* Enabling RX DMA */
1031 static void udc_set_rde(struct udc *dev)
1032 {
1033         u32 tmp;
1034 
1035         VDBG(dev, "udc_set_rde()\n");
1036         /* stop RDE timer */
1037         if (timer_pending(&udc_timer)) {
1038                 set_rde = 0;
1039                 mod_timer(&udc_timer, jiffies - 1);
1040         }
1041         /* set RDE */
1042         tmp = readl(&dev->regs->ctl);
1043         tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1044         writel(tmp, &dev->regs->ctl);
1045 }
1046 
1047 /* Queues a request packet, called by gadget driver */
1048 static int
1049 udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1050 {
1051         int                     retval = 0;
1052         u8                      open_rxfifo = 0;
1053         unsigned long           iflags;
1054         struct udc_ep           *ep;
1055         struct udc_request      *req;
1056         struct udc              *dev;
1057         u32                     tmp;
1058 
1059         /* check the inputs */
1060         req = container_of(usbreq, struct udc_request, req);
1061 
1062         if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1063                         || !list_empty(&req->queue))
1064                 return -EINVAL;
1065 
1066         ep = container_of(usbep, struct udc_ep, ep);
1067         if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1068                 return -EINVAL;
1069 
1070         VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1071         dev = ep->dev;
1072 
1073         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1074                 return -ESHUTDOWN;
1075 
1076         /* map dma (usually done before) */
1077         if (ep->dma) {
1078                 VDBG(dev, "DMA map req %p\n", req);
1079                 retval = usb_gadget_map_request(&udc->gadget, usbreq, ep->in);
1080                 if (retval)
1081                         return retval;
1082         }
1083 
1084         VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1085                         usbep->name, usbreq, usbreq->length,
1086                         req->td_data, usbreq->buf);
1087 
1088         spin_lock_irqsave(&dev->lock, iflags);
1089         usbreq->actual = 0;
1090         usbreq->status = -EINPROGRESS;
1091         req->dma_done = 0;
1092 
1093         /* on empty queue just do first transfer */
1094         if (list_empty(&ep->queue)) {
1095                 /* zlp */
1096                 if (usbreq->length == 0) {
1097                         /* IN zlp's are handled by hardware */
1098                         complete_req(ep, req, 0);
1099                         VDBG(dev, "%s: zlp\n", ep->ep.name);
1100                         /*
1101                          * if set_config or set_intf is waiting for ack by zlp
1102                          * then set CSR_DONE
1103                          */
1104                         if (dev->set_cfg_not_acked) {
1105                                 tmp = readl(&dev->regs->ctl);
1106                                 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1107                                 writel(tmp, &dev->regs->ctl);
1108                                 dev->set_cfg_not_acked = 0;
1109                         }
1110                         /* setup command is ACK'ed now by zlp */
1111                         if (dev->waiting_zlp_ack_ep0in) {
1112                                 /* clear NAK by writing CNAK in EP0_IN */
1113                                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1114                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1115                                 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1116                                 dev->ep[UDC_EP0IN_IX].naking = 0;
1117                                 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1118                                                         UDC_EP0IN_IX);
1119                                 dev->waiting_zlp_ack_ep0in = 0;
1120                         }
1121                         goto finished;
1122                 }
1123                 if (ep->dma) {
1124                         retval = prep_dma(ep, req, GFP_ATOMIC);
1125                         if (retval != 0)
1126                                 goto finished;
1127                         /* write desc pointer to enable DMA */
1128                         if (ep->in) {
1129                                 /* set HOST READY */
1130                                 req->td_data->status =
1131                                         AMD_ADDBITS(req->td_data->status,
1132                                                 UDC_DMA_IN_STS_BS_HOST_READY,
1133                                                 UDC_DMA_IN_STS_BS);
1134                         }
1135 
1136                         /* disabled rx dma while descriptor update */
1137                         if (!ep->in) {
1138                                 /* stop RDE timer */
1139                                 if (timer_pending(&udc_timer)) {
1140                                         set_rde = 0;
1141                                         mod_timer(&udc_timer, jiffies - 1);
1142                                 }
1143                                 /* clear RDE */
1144                                 tmp = readl(&dev->regs->ctl);
1145                                 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1146                                 writel(tmp, &dev->regs->ctl);
1147                                 open_rxfifo = 1;
1148 
1149                                 /*
1150                                  * if BNA occurred then let BNA dummy desc.
1151                                  * point to current desc.
1152                                  */
1153                                 if (ep->bna_occurred) {
1154                                         VDBG(dev, "copy to BNA dummy desc.\n");
1155                                         memcpy(ep->bna_dummy_req->td_data,
1156                                                 req->td_data,
1157                                                 sizeof(struct udc_data_dma));
1158                                 }
1159                         }
1160                         /* write desc pointer */
1161                         writel(req->td_phys, &ep->regs->desptr);
1162 
1163                         /* clear NAK by writing CNAK */
1164                         if (ep->naking) {
1165                                 tmp = readl(&ep->regs->ctl);
1166                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1167                                 writel(tmp, &ep->regs->ctl);
1168                                 ep->naking = 0;
1169                                 UDC_QUEUE_CNAK(ep, ep->num);
1170                         }
1171 
1172                         if (ep->in) {
1173                                 /* enable ep irq */
1174                                 tmp = readl(&dev->regs->ep_irqmsk);
1175                                 tmp &= AMD_UNMASK_BIT(ep->num);
1176                                 writel(tmp, &dev->regs->ep_irqmsk);
1177                         }
1178                 } else if (ep->in) {
1179                                 /* enable ep irq */
1180                                 tmp = readl(&dev->regs->ep_irqmsk);
1181                                 tmp &= AMD_UNMASK_BIT(ep->num);
1182                                 writel(tmp, &dev->regs->ep_irqmsk);
1183                         }
1184 
1185         } else if (ep->dma) {
1186 
1187                 /*
1188                  * prep_dma not used for OUT ep's, this is not possible
1189                  * for PPB modes, because of chain creation reasons
1190                  */
1191                 if (ep->in) {
1192                         retval = prep_dma(ep, req, GFP_ATOMIC);
1193                         if (retval != 0)
1194                                 goto finished;
1195                 }
1196         }
1197         VDBG(dev, "list_add\n");
1198         /* add request to ep queue */
1199         if (req) {
1200 
1201                 list_add_tail(&req->queue, &ep->queue);
1202 
1203                 /* open rxfifo if out data queued */
1204                 if (open_rxfifo) {
1205                         /* enable DMA */
1206                         req->dma_going = 1;
1207                         udc_set_rde(dev);
1208                         if (ep->num != UDC_EP0OUT_IX)
1209                                 dev->data_ep_queued = 1;
1210                 }
1211                 /* stop OUT naking */
1212                 if (!ep->in) {
1213                         if (!use_dma && udc_rxfifo_pending) {
1214                                 DBG(dev, "udc_queue(): pending bytes in "
1215                                         "rxfifo after nyet\n");
1216                                 /*
1217                                  * read pending bytes afer nyet:
1218                                  * referring to isr
1219                                  */
1220                                 if (udc_rxfifo_read(ep, req)) {
1221                                         /* finish */
1222                                         complete_req(ep, req, 0);
1223                                 }
1224                                 udc_rxfifo_pending = 0;
1225 
1226                         }
1227                 }
1228         }
1229 
1230 finished:
1231         spin_unlock_irqrestore(&dev->lock, iflags);
1232         return retval;
1233 }
1234 
1235 /* Empty request queue of an endpoint; caller holds spinlock */
1236 static void empty_req_queue(struct udc_ep *ep)
1237 {
1238         struct udc_request      *req;
1239 
1240         ep->halted = 1;
1241         while (!list_empty(&ep->queue)) {
1242                 req = list_entry(ep->queue.next,
1243                         struct udc_request,
1244                         queue);
1245                 complete_req(ep, req, -ESHUTDOWN);
1246         }
1247 }
1248 
1249 /* Dequeues a request packet, called by gadget driver */
1250 static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1251 {
1252         struct udc_ep           *ep;
1253         struct udc_request      *req;
1254         unsigned                halted;
1255         unsigned long           iflags;
1256 
1257         ep = container_of(usbep, struct udc_ep, ep);
1258         if (!usbep || !usbreq || (!ep->ep.desc && (ep->num != 0
1259                                 && ep->num != UDC_EP0OUT_IX)))
1260                 return -EINVAL;
1261 
1262         req = container_of(usbreq, struct udc_request, req);
1263 
1264         spin_lock_irqsave(&ep->dev->lock, iflags);
1265         halted = ep->halted;
1266         ep->halted = 1;
1267         /* request in processing or next one */
1268         if (ep->queue.next == &req->queue) {
1269                 if (ep->dma && req->dma_going) {
1270                         if (ep->in)
1271                                 ep->cancel_transfer = 1;
1272                         else {
1273                                 u32 tmp;
1274                                 u32 dma_sts;
1275                                 /* stop potential receive DMA */
1276                                 tmp = readl(&udc->regs->ctl);
1277                                 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1278                                                         &udc->regs->ctl);
1279                                 /*
1280                                  * Cancel transfer later in ISR
1281                                  * if descriptor was touched.
1282                                  */
1283                                 dma_sts = AMD_GETBITS(req->td_data->status,
1284                                                         UDC_DMA_OUT_STS_BS);
1285                                 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1286                                         ep->cancel_transfer = 1;
1287                                 else {
1288                                         udc_init_bna_dummy(ep->req);
1289                                         writel(ep->bna_dummy_req->td_phys,
1290                                                 &ep->regs->desptr);
1291                                 }
1292                                 writel(tmp, &udc->regs->ctl);
1293                         }
1294                 }
1295         }
1296         complete_req(ep, req, -ECONNRESET);
1297         ep->halted = halted;
1298 
1299         spin_unlock_irqrestore(&ep->dev->lock, iflags);
1300         return 0;
1301 }
1302 
1303 /* Halt or clear halt of endpoint */
1304 static int
1305 udc_set_halt(struct usb_ep *usbep, int halt)
1306 {
1307         struct udc_ep   *ep;
1308         u32 tmp;
1309         unsigned long iflags;
1310         int retval = 0;
1311 
1312         if (!usbep)
1313                 return -EINVAL;
1314 
1315         pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1316 
1317         ep = container_of(usbep, struct udc_ep, ep);
1318         if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1319                 return -EINVAL;
1320         if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1321                 return -ESHUTDOWN;
1322 
1323         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1324         /* halt or clear halt */
1325         if (halt) {
1326                 if (ep->num == 0)
1327                         ep->dev->stall_ep0in = 1;
1328                 else {
1329                         /*
1330                          * set STALL
1331                          * rxfifo empty not taken into acount
1332                          */
1333                         tmp = readl(&ep->regs->ctl);
1334                         tmp |= AMD_BIT(UDC_EPCTL_S);
1335                         writel(tmp, &ep->regs->ctl);
1336                         ep->halted = 1;
1337 
1338                         /* setup poll timer */
1339                         if (!timer_pending(&udc_pollstall_timer)) {
1340                                 udc_pollstall_timer.expires = jiffies +
1341                                         HZ * UDC_POLLSTALL_TIMER_USECONDS
1342                                         / (1000 * 1000);
1343                                 if (!stop_pollstall_timer) {
1344                                         DBG(ep->dev, "start polltimer\n");
1345                                         add_timer(&udc_pollstall_timer);
1346                                 }
1347                         }
1348                 }
1349         } else {
1350                 /* ep is halted by set_halt() before */
1351                 if (ep->halted) {
1352                         tmp = readl(&ep->regs->ctl);
1353                         /* clear stall bit */
1354                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1355                         /* clear NAK by writing CNAK */
1356                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1357                         writel(tmp, &ep->regs->ctl);
1358                         ep->halted = 0;
1359                         UDC_QUEUE_CNAK(ep, ep->num);
1360                 }
1361         }
1362         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1363         return retval;
1364 }
1365 
1366 /* gadget interface */
1367 static const struct usb_ep_ops udc_ep_ops = {
1368         .enable         = udc_ep_enable,
1369         .disable        = udc_ep_disable,
1370 
1371         .alloc_request  = udc_alloc_request,
1372         .free_request   = udc_free_request,
1373 
1374         .queue          = udc_queue,
1375         .dequeue        = udc_dequeue,
1376 
1377         .set_halt       = udc_set_halt,
1378         /* fifo ops not implemented */
1379 };
1380 
1381 /*-------------------------------------------------------------------------*/
1382 
1383 /* Get frame counter (not implemented) */
1384 static int udc_get_frame(struct usb_gadget *gadget)
1385 {
1386         return -EOPNOTSUPP;
1387 }
1388 
1389 /* Remote wakeup gadget interface */
1390 static int udc_wakeup(struct usb_gadget *gadget)
1391 {
1392         struct udc              *dev;
1393 
1394         if (!gadget)
1395                 return -EINVAL;
1396         dev = container_of(gadget, struct udc, gadget);
1397         udc_remote_wakeup(dev);
1398 
1399         return 0;
1400 }
1401 
1402 static int amd5536_udc_start(struct usb_gadget *g,
1403                 struct usb_gadget_driver *driver);
1404 static int amd5536_udc_stop(struct usb_gadget *g,
1405                 struct usb_gadget_driver *driver);
1406 /* gadget operations */
1407 static const struct usb_gadget_ops udc_ops = {
1408         .wakeup         = udc_wakeup,
1409         .get_frame      = udc_get_frame,
1410         .udc_start      = amd5536_udc_start,
1411         .udc_stop       = amd5536_udc_stop,
1412 };
1413 
1414 /* Setups endpoint parameters, adds endpoints to linked list */
1415 static void make_ep_lists(struct udc *dev)
1416 {
1417         /* make gadget ep lists */
1418         INIT_LIST_HEAD(&dev->gadget.ep_list);
1419         list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1420                                                 &dev->gadget.ep_list);
1421         list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1422                                                 &dev->gadget.ep_list);
1423         list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1424                                                 &dev->gadget.ep_list);
1425 
1426         /* fifo config */
1427         dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1428         if (dev->gadget.speed == USB_SPEED_FULL)
1429                 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1430         else if (dev->gadget.speed == USB_SPEED_HIGH)
1431                 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1432         dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1433 }
1434 
1435 /* init registers at driver load time */
1436 static int startup_registers(struct udc *dev)
1437 {
1438         u32 tmp;
1439 
1440         /* init controller by soft reset */
1441         udc_soft_reset(dev);
1442 
1443         /* mask not needed interrupts */
1444         udc_mask_unused_interrupts(dev);
1445 
1446         /* put into initial config */
1447         udc_basic_init(dev);
1448         /* link up all endpoints */
1449         udc_setup_endpoints(dev);
1450 
1451         /* program speed */
1452         tmp = readl(&dev->regs->cfg);
1453         if (use_fullspeed)
1454                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1455         else
1456                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1457         writel(tmp, &dev->regs->cfg);
1458 
1459         return 0;
1460 }
1461 
1462 /* Inits UDC context */
1463 static void udc_basic_init(struct udc *dev)
1464 {
1465         u32     tmp;
1466 
1467         DBG(dev, "udc_basic_init()\n");
1468 
1469         dev->gadget.speed = USB_SPEED_UNKNOWN;
1470 
1471         /* stop RDE timer */
1472         if (timer_pending(&udc_timer)) {
1473                 set_rde = 0;
1474                 mod_timer(&udc_timer, jiffies - 1);
1475         }
1476         /* stop poll stall timer */
1477         if (timer_pending(&udc_pollstall_timer))
1478                 mod_timer(&udc_pollstall_timer, jiffies - 1);
1479         /* disable DMA */
1480         tmp = readl(&dev->regs->ctl);
1481         tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1482         tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1483         writel(tmp, &dev->regs->ctl);
1484 
1485         /* enable dynamic CSR programming */
1486         tmp = readl(&dev->regs->cfg);
1487         tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1488         /* set self powered */
1489         tmp |= AMD_BIT(UDC_DEVCFG_SP);
1490         /* set remote wakeupable */
1491         tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1492         writel(tmp, &dev->regs->cfg);
1493 
1494         make_ep_lists(dev);
1495 
1496         dev->data_ep_enabled = 0;
1497         dev->data_ep_queued = 0;
1498 }
1499 
1500 /* Sets initial endpoint parameters */
1501 static void udc_setup_endpoints(struct udc *dev)
1502 {
1503         struct udc_ep   *ep;
1504         u32     tmp;
1505         u32     reg;
1506 
1507         DBG(dev, "udc_setup_endpoints()\n");
1508 
1509         /* read enum speed */
1510         tmp = readl(&dev->regs->sts);
1511         tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1512         if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
1513                 dev->gadget.speed = USB_SPEED_HIGH;
1514         else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
1515                 dev->gadget.speed = USB_SPEED_FULL;
1516 
1517         /* set basic ep parameters */
1518         for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1519                 ep = &dev->ep[tmp];
1520                 ep->dev = dev;
1521                 ep->ep.name = ep_string[tmp];
1522                 ep->num = tmp;
1523                 /* txfifo size is calculated at enable time */
1524                 ep->txfifo = dev->txfifo;
1525 
1526                 /* fifo size */
1527                 if (tmp < UDC_EPIN_NUM) {
1528                         ep->fifo_depth = UDC_TXFIFO_SIZE;
1529                         ep->in = 1;
1530                 } else {
1531                         ep->fifo_depth = UDC_RXFIFO_SIZE;
1532                         ep->in = 0;
1533 
1534                 }
1535                 ep->regs = &dev->ep_regs[tmp];
1536                 /*
1537                  * ep will be reset only if ep was not enabled before to avoid
1538                  * disabling ep interrupts when ENUM interrupt occurs but ep is
1539                  * not enabled by gadget driver
1540                  */
1541                 if (!ep->ep.desc)
1542                         ep_init(dev->regs, ep);
1543 
1544                 if (use_dma) {
1545                         /*
1546                          * ep->dma is not really used, just to indicate that
1547                          * DMA is active: remove this
1548                          * dma regs = dev control regs
1549                          */
1550                         ep->dma = &dev->regs->ctl;
1551 
1552                         /* nak OUT endpoints until enable - not for ep0 */
1553                         if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1554                                                 && tmp > UDC_EPIN_NUM) {
1555                                 /* set NAK */
1556                                 reg = readl(&dev->ep[tmp].regs->ctl);
1557                                 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1558                                 writel(reg, &dev->ep[tmp].regs->ctl);
1559                                 dev->ep[tmp].naking = 1;
1560 
1561                         }
1562                 }
1563         }
1564         /* EP0 max packet */
1565         if (dev->gadget.speed == USB_SPEED_FULL) {
1566                 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1567                                            UDC_FS_EP0IN_MAX_PKT_SIZE);
1568                 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1569                                            UDC_FS_EP0OUT_MAX_PKT_SIZE);
1570         } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1571                 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1572                                            UDC_EP0IN_MAX_PKT_SIZE);
1573                 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1574                                            UDC_EP0OUT_MAX_PKT_SIZE);
1575         }
1576 
1577         /*
1578          * with suspend bug workaround, ep0 params for gadget driver
1579          * are set at gadget driver bind() call
1580          */
1581         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1582         dev->ep[UDC_EP0IN_IX].halted = 0;
1583         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1584 
1585         /* init cfg/alt/int */
1586         dev->cur_config = 0;
1587         dev->cur_intf = 0;
1588         dev->cur_alt = 0;
1589 }
1590 
1591 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1592 static void usb_connect(struct udc *dev)
1593 {
1594 
1595         dev_info(&dev->pdev->dev, "USB Connect\n");
1596 
1597         dev->connected = 1;
1598 
1599         /* put into initial config */
1600         udc_basic_init(dev);
1601 
1602         /* enable device setup interrupts */
1603         udc_enable_dev_setup_interrupts(dev);
1604 }
1605 
1606 /*
1607  * Calls gadget with disconnect event and resets the UDC and makes
1608  * initial bringup to be ready for ep0 events
1609  */
1610 static void usb_disconnect(struct udc *dev)
1611 {
1612 
1613         dev_info(&dev->pdev->dev, "USB Disconnect\n");
1614 
1615         dev->connected = 0;
1616 
1617         /* mask interrupts */
1618         udc_mask_unused_interrupts(dev);
1619 
1620         /* REVISIT there doesn't seem to be a point to having this
1621          * talk to a tasklet ... do it directly, we already hold
1622          * the spinlock needed to process the disconnect.
1623          */
1624 
1625         tasklet_schedule(&disconnect_tasklet);
1626 }
1627 
1628 /* Tasklet for disconnect to be outside of interrupt context */
1629 static void udc_tasklet_disconnect(unsigned long par)
1630 {
1631         struct udc *dev = (struct udc *)(*((struct udc **) par));
1632         u32 tmp;
1633 
1634         DBG(dev, "Tasklet disconnect\n");
1635         spin_lock_irq(&dev->lock);
1636 
1637         if (dev->driver) {
1638                 spin_unlock(&dev->lock);
1639                 dev->driver->disconnect(&dev->gadget);
1640                 spin_lock(&dev->lock);
1641 
1642                 /* empty queues */
1643                 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1644                         empty_req_queue(&dev->ep[tmp]);
1645 
1646         }
1647 
1648         /* disable ep0 */
1649         ep_init(dev->regs,
1650                         &dev->ep[UDC_EP0IN_IX]);
1651 
1652 
1653         if (!soft_reset_occured) {
1654                 /* init controller by soft reset */
1655                 udc_soft_reset(dev);
1656                 soft_reset_occured++;
1657         }
1658 
1659         /* re-enable dev interrupts */
1660         udc_enable_dev_setup_interrupts(dev);
1661         /* back to full speed ? */
1662         if (use_fullspeed) {
1663                 tmp = readl(&dev->regs->cfg);
1664                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1665                 writel(tmp, &dev->regs->cfg);
1666         }
1667 
1668         spin_unlock_irq(&dev->lock);
1669 }
1670 
1671 /* Reset the UDC core */
1672 static void udc_soft_reset(struct udc *dev)
1673 {
1674         unsigned long   flags;
1675 
1676         DBG(dev, "Soft reset\n");
1677         /*
1678          * reset possible waiting interrupts, because int.
1679          * status is lost after soft reset,
1680          * ep int. status reset
1681          */
1682         writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1683         /* device int. status reset */
1684         writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1685 
1686         spin_lock_irqsave(&udc_irq_spinlock, flags);
1687         writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1688         readl(&dev->regs->cfg);
1689         spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1690 
1691 }
1692 
1693 /* RDE timer callback to set RDE bit */
1694 static void udc_timer_function(unsigned long v)
1695 {
1696         u32 tmp;
1697 
1698         spin_lock_irq(&udc_irq_spinlock);
1699 
1700         if (set_rde > 0) {
1701                 /*
1702                  * open the fifo if fifo was filled on last timer call
1703                  * conditionally
1704                  */
1705                 if (set_rde > 1) {
1706                         /* set RDE to receive setup data */
1707                         tmp = readl(&udc->regs->ctl);
1708                         tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1709                         writel(tmp, &udc->regs->ctl);
1710                         set_rde = -1;
1711                 } else if (readl(&udc->regs->sts)
1712                                 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1713                         /*
1714                          * if fifo empty setup polling, do not just
1715                          * open the fifo
1716                          */
1717                         udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1718                         if (!stop_timer)
1719                                 add_timer(&udc_timer);
1720                 } else {
1721                         /*
1722                          * fifo contains data now, setup timer for opening
1723                          * the fifo when timer expires to be able to receive
1724                          * setup packets, when data packets gets queued by
1725                          * gadget layer then timer will forced to expire with
1726                          * set_rde=0 (RDE is set in udc_queue())
1727                          */
1728                         set_rde++;
1729                         /* debug: lhadmot_timer_start = 221070 */
1730                         udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1731                         if (!stop_timer)
1732                                 add_timer(&udc_timer);
1733                 }
1734 
1735         } else
1736                 set_rde = -1; /* RDE was set by udc_queue() */
1737         spin_unlock_irq(&udc_irq_spinlock);
1738         if (stop_timer)
1739                 complete(&on_exit);
1740 
1741 }
1742 
1743 /* Handle halt state, used in stall poll timer */
1744 static void udc_handle_halt_state(struct udc_ep *ep)
1745 {
1746         u32 tmp;
1747         /* set stall as long not halted */
1748         if (ep->halted == 1) {
1749                 tmp = readl(&ep->regs->ctl);
1750                 /* STALL cleared ? */
1751                 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1752                         /*
1753                          * FIXME: MSC spec requires that stall remains
1754                          * even on receivng of CLEAR_FEATURE HALT. So
1755                          * we would set STALL again here to be compliant.
1756                          * But with current mass storage drivers this does
1757                          * not work (would produce endless host retries).
1758                          * So we clear halt on CLEAR_FEATURE.
1759                          *
1760                         DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1761                         tmp |= AMD_BIT(UDC_EPCTL_S);
1762                         writel(tmp, &ep->regs->ctl);*/
1763 
1764                         /* clear NAK by writing CNAK */
1765                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1766                         writel(tmp, &ep->regs->ctl);
1767                         ep->halted = 0;
1768                         UDC_QUEUE_CNAK(ep, ep->num);
1769                 }
1770         }
1771 }
1772 
1773 /* Stall timer callback to poll S bit and set it again after */
1774 static void udc_pollstall_timer_function(unsigned long v)
1775 {
1776         struct udc_ep *ep;
1777         int halted = 0;
1778 
1779         spin_lock_irq(&udc_stall_spinlock);
1780         /*
1781          * only one IN and OUT endpoints are handled
1782          * IN poll stall
1783          */
1784         ep = &udc->ep[UDC_EPIN_IX];
1785         udc_handle_halt_state(ep);
1786         if (ep->halted)
1787                 halted = 1;
1788         /* OUT poll stall */
1789         ep = &udc->ep[UDC_EPOUT_IX];
1790         udc_handle_halt_state(ep);
1791         if (ep->halted)
1792                 halted = 1;
1793 
1794         /* setup timer again when still halted */
1795         if (!stop_pollstall_timer && halted) {
1796                 udc_pollstall_timer.expires = jiffies +
1797                                         HZ * UDC_POLLSTALL_TIMER_USECONDS
1798                                         / (1000 * 1000);
1799                 add_timer(&udc_pollstall_timer);
1800         }
1801         spin_unlock_irq(&udc_stall_spinlock);
1802 
1803         if (stop_pollstall_timer)
1804                 complete(&on_pollstall_exit);
1805 }
1806 
1807 /* Inits endpoint 0 so that SETUP packets are processed */
1808 static void activate_control_endpoints(struct udc *dev)
1809 {
1810         u32 tmp;
1811 
1812         DBG(dev, "activate_control_endpoints\n");
1813 
1814         /* flush fifo */
1815         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1816         tmp |= AMD_BIT(UDC_EPCTL_F);
1817         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1818 
1819         /* set ep0 directions */
1820         dev->ep[UDC_EP0IN_IX].in = 1;
1821         dev->ep[UDC_EP0OUT_IX].in = 0;
1822 
1823         /* set buffer size (tx fifo entries) of EP0_IN */
1824         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1825         if (dev->gadget.speed == USB_SPEED_FULL)
1826                 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1827                                         UDC_EPIN_BUFF_SIZE);
1828         else if (dev->gadget.speed == USB_SPEED_HIGH)
1829                 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1830                                         UDC_EPIN_BUFF_SIZE);
1831         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1832 
1833         /* set max packet size of EP0_IN */
1834         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1835         if (dev->gadget.speed == USB_SPEED_FULL)
1836                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1837                                         UDC_EP_MAX_PKT_SIZE);
1838         else if (dev->gadget.speed == USB_SPEED_HIGH)
1839                 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1840                                 UDC_EP_MAX_PKT_SIZE);
1841         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1842 
1843         /* set max packet size of EP0_OUT */
1844         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1845         if (dev->gadget.speed == USB_SPEED_FULL)
1846                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1847                                         UDC_EP_MAX_PKT_SIZE);
1848         else if (dev->gadget.speed == USB_SPEED_HIGH)
1849                 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1850                                         UDC_EP_MAX_PKT_SIZE);
1851         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1852 
1853         /* set max packet size of EP0 in UDC CSR */
1854         tmp = readl(&dev->csr->ne[0]);
1855         if (dev->gadget.speed == USB_SPEED_FULL)
1856                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1857                                         UDC_CSR_NE_MAX_PKT);
1858         else if (dev->gadget.speed == USB_SPEED_HIGH)
1859                 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1860                                         UDC_CSR_NE_MAX_PKT);
1861         writel(tmp, &dev->csr->ne[0]);
1862 
1863         if (use_dma) {
1864                 dev->ep[UDC_EP0OUT_IX].td->status |=
1865                         AMD_BIT(UDC_DMA_OUT_STS_L);
1866                 /* write dma desc address */
1867                 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1868                         &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1869                 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1870                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1871                 /* stop RDE timer */
1872                 if (timer_pending(&udc_timer)) {
1873                         set_rde = 0;
1874                         mod_timer(&udc_timer, jiffies - 1);
1875                 }
1876                 /* stop pollstall timer */
1877                 if (timer_pending(&udc_pollstall_timer))
1878                         mod_timer(&udc_pollstall_timer, jiffies - 1);
1879                 /* enable DMA */
1880                 tmp = readl(&dev->regs->ctl);
1881                 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1882                                 | AMD_BIT(UDC_DEVCTL_RDE)
1883                                 | AMD_BIT(UDC_DEVCTL_TDE);
1884                 if (use_dma_bufferfill_mode)
1885                         tmp |= AMD_BIT(UDC_DEVCTL_BF);
1886                 else if (use_dma_ppb_du)
1887                         tmp |= AMD_BIT(UDC_DEVCTL_DU);
1888                 writel(tmp, &dev->regs->ctl);
1889         }
1890 
1891         /* clear NAK by writing CNAK for EP0IN */
1892         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1893         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1894         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1895         dev->ep[UDC_EP0IN_IX].naking = 0;
1896         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1897 
1898         /* clear NAK by writing CNAK for EP0OUT */
1899         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1900         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1901         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1902         dev->ep[UDC_EP0OUT_IX].naking = 0;
1903         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1904 }
1905 
1906 /* Make endpoint 0 ready for control traffic */
1907 static int setup_ep0(struct udc *dev)
1908 {
1909         activate_control_endpoints(dev);
1910         /* enable ep0 interrupts */
1911         udc_enable_ep0_interrupts(dev);
1912         /* enable device setup interrupts */
1913         udc_enable_dev_setup_interrupts(dev);
1914 
1915         return 0;
1916 }
1917 
1918 /* Called by gadget driver to register itself */
1919 static int amd5536_udc_start(struct usb_gadget *g,
1920                 struct usb_gadget_driver *driver)
1921 {
1922         struct udc *dev = to_amd5536_udc(g);
1923         u32 tmp;
1924 
1925         driver->driver.bus = NULL;
1926         dev->driver = driver;
1927 
1928         /* Some gadget drivers use both ep0 directions.
1929          * NOTE: to gadget driver, ep0 is just one endpoint...
1930          */
1931         dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1932                 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1933 
1934         /* get ready for ep0 traffic */
1935         setup_ep0(dev);
1936 
1937         /* clear SD */
1938         tmp = readl(&dev->regs->ctl);
1939         tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1940         writel(tmp, &dev->regs->ctl);
1941 
1942         usb_connect(dev);
1943 
1944         return 0;
1945 }
1946 
1947 /* shutdown requests and disconnect from gadget */
1948 static void
1949 shutdown(struct udc *dev, struct usb_gadget_driver *driver)
1950 __releases(dev->lock)
1951 __acquires(dev->lock)
1952 {
1953         int tmp;
1954 
1955         /* empty queues and init hardware */
1956         udc_basic_init(dev);
1957 
1958         for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1959                 empty_req_queue(&dev->ep[tmp]);
1960 
1961         udc_setup_endpoints(dev);
1962 }
1963 
1964 /* Called by gadget driver to unregister itself */
1965 static int amd5536_udc_stop(struct usb_gadget *g,
1966                 struct usb_gadget_driver *driver)
1967 {
1968         struct udc *dev = to_amd5536_udc(g);
1969         unsigned long flags;
1970         u32 tmp;
1971 
1972         spin_lock_irqsave(&dev->lock, flags);
1973         udc_mask_unused_interrupts(dev);
1974         shutdown(dev, driver);
1975         spin_unlock_irqrestore(&dev->lock, flags);
1976 
1977         dev->driver = NULL;
1978 
1979         /* set SD */
1980         tmp = readl(&dev->regs->ctl);
1981         tmp |= AMD_BIT(UDC_DEVCTL_SD);
1982         writel(tmp, &dev->regs->ctl);
1983 
1984         return 0;
1985 }
1986 
1987 /* Clear pending NAK bits */
1988 static void udc_process_cnak_queue(struct udc *dev)
1989 {
1990         u32 tmp;
1991         u32 reg;
1992 
1993         /* check epin's */
1994         DBG(dev, "CNAK pending queue processing\n");
1995         for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
1996                 if (cnak_pending & (1 << tmp)) {
1997                         DBG(dev, "CNAK pending for ep%d\n", tmp);
1998                         /* clear NAK by writing CNAK */
1999                         reg = readl(&dev->ep[tmp].regs->ctl);
2000                         reg |= AMD_BIT(UDC_EPCTL_CNAK);
2001                         writel(reg, &dev->ep[tmp].regs->ctl);
2002                         dev->ep[tmp].naking = 0;
2003                         UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2004                 }
2005         }
2006         /* ...  and ep0out */
2007         if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2008                 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2009                 /* clear NAK by writing CNAK */
2010                 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2011                 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2012                 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2013                 dev->ep[UDC_EP0OUT_IX].naking = 0;
2014                 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2015                                 dev->ep[UDC_EP0OUT_IX].num);
2016         }
2017 }
2018 
2019 /* Enabling RX DMA after setup packet */
2020 static void udc_ep0_set_rde(struct udc *dev)
2021 {
2022         if (use_dma) {
2023                 /*
2024                  * only enable RXDMA when no data endpoint enabled
2025                  * or data is queued
2026                  */
2027                 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2028                         udc_set_rde(dev);
2029                 } else {
2030                         /*
2031                          * setup timer for enabling RDE (to not enable
2032                          * RXFIFO DMA for data endpoints to early)
2033                          */
2034                         if (set_rde != 0 && !timer_pending(&udc_timer)) {
2035                                 udc_timer.expires =
2036                                         jiffies + HZ/UDC_RDE_TIMER_DIV;
2037                                 set_rde = 1;
2038                                 if (!stop_timer)
2039                                         add_timer(&udc_timer);
2040                         }
2041                 }
2042         }
2043 }
2044 
2045 
2046 /* Interrupt handler for data OUT traffic */
2047 static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2048 {
2049         irqreturn_t             ret_val = IRQ_NONE;
2050         u32                     tmp;
2051         struct udc_ep           *ep;
2052         struct udc_request      *req;
2053         unsigned int            count;
2054         struct udc_data_dma     *td = NULL;
2055         unsigned                dma_done;
2056 
2057         VDBG(dev, "ep%d irq\n", ep_ix);
2058         ep = &dev->ep[ep_ix];
2059 
2060         tmp = readl(&ep->regs->sts);
2061         if (use_dma) {
2062                 /* BNA event ? */
2063                 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2064                         DBG(dev, "BNA ep%dout occurred - DESPTR = %x\n",
2065                                         ep->num, readl(&ep->regs->desptr));
2066                         /* clear BNA */
2067                         writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2068                         if (!ep->cancel_transfer)
2069                                 ep->bna_occurred = 1;
2070                         else
2071                                 ep->cancel_transfer = 0;
2072                         ret_val = IRQ_HANDLED;
2073                         goto finished;
2074                 }
2075         }
2076         /* HE event ? */
2077         if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2078                 dev_err(&dev->pdev->dev, "HE ep%dout occurred\n", ep->num);
2079 
2080                 /* clear HE */
2081                 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2082                 ret_val = IRQ_HANDLED;
2083                 goto finished;
2084         }
2085 
2086         if (!list_empty(&ep->queue)) {
2087 
2088                 /* next request */
2089                 req = list_entry(ep->queue.next,
2090                         struct udc_request, queue);
2091         } else {
2092                 req = NULL;
2093                 udc_rxfifo_pending = 1;
2094         }
2095         VDBG(dev, "req = %p\n", req);
2096         /* fifo mode */
2097         if (!use_dma) {
2098 
2099                 /* read fifo */
2100                 if (req && udc_rxfifo_read(ep, req)) {
2101                         ret_val = IRQ_HANDLED;
2102 
2103                         /* finish */
2104                         complete_req(ep, req, 0);
2105                         /* next request */
2106                         if (!list_empty(&ep->queue) && !ep->halted) {
2107                                 req = list_entry(ep->queue.next,
2108                                         struct udc_request, queue);
2109                         } else
2110                                 req = NULL;
2111                 }
2112 
2113         /* DMA */
2114         } else if (!ep->cancel_transfer && req != NULL) {
2115                 ret_val = IRQ_HANDLED;
2116 
2117                 /* check for DMA done */
2118                 if (!use_dma_ppb) {
2119                         dma_done = AMD_GETBITS(req->td_data->status,
2120                                                 UDC_DMA_OUT_STS_BS);
2121                 /* packet per buffer mode - rx bytes */
2122                 } else {
2123                         /*
2124                          * if BNA occurred then recover desc. from
2125                          * BNA dummy desc.
2126                          */
2127                         if (ep->bna_occurred) {
2128                                 VDBG(dev, "Recover desc. from BNA dummy\n");
2129                                 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2130                                                 sizeof(struct udc_data_dma));
2131                                 ep->bna_occurred = 0;
2132                                 udc_init_bna_dummy(ep->req);
2133                         }
2134                         td = udc_get_last_dma_desc(req);
2135                         dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2136                 }
2137                 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2138                         /* buffer fill mode - rx bytes */
2139                         if (!use_dma_ppb) {
2140                                 /* received number bytes */
2141                                 count = AMD_GETBITS(req->td_data->status,
2142                                                 UDC_DMA_OUT_STS_RXBYTES);
2143                                 VDBG(dev, "rx bytes=%u\n", count);
2144                         /* packet per buffer mode - rx bytes */
2145                         } else {
2146                                 VDBG(dev, "req->td_data=%p\n", req->td_data);
2147                                 VDBG(dev, "last desc = %p\n", td);
2148                                 /* received number bytes */
2149                                 if (use_dma_ppb_du) {
2150                                         /* every desc. counts bytes */
2151                                         count = udc_get_ppbdu_rxbytes(req);
2152                                 } else {
2153                                         /* last desc. counts bytes */
2154                                         count = AMD_GETBITS(td->status,
2155                                                 UDC_DMA_OUT_STS_RXBYTES);
2156                                         if (!count && req->req.length
2157                                                 == UDC_DMA_MAXPACKET) {
2158                                                 /*
2159                                                  * on 64k packets the RXBYTES
2160                                                  * field is zero
2161                                                  */
2162                                                 count = UDC_DMA_MAXPACKET;
2163                                         }
2164                                 }
2165                                 VDBG(dev, "last desc rx bytes=%u\n", count);
2166                         }
2167 
2168                         tmp = req->req.length - req->req.actual;
2169                         if (count > tmp) {
2170                                 if ((tmp % ep->ep.maxpacket) != 0) {
2171                                         DBG(dev, "%s: rx %db, space=%db\n",
2172                                                 ep->ep.name, count, tmp);
2173                                         req->req.status = -EOVERFLOW;
2174                                 }
2175                                 count = tmp;
2176                         }
2177                         req->req.actual += count;
2178                         req->dma_going = 0;
2179                         /* complete request */
2180                         complete_req(ep, req, 0);
2181 
2182                         /* next request */
2183                         if (!list_empty(&ep->queue) && !ep->halted) {
2184                                 req = list_entry(ep->queue.next,
2185                                         struct udc_request,
2186                                         queue);
2187                                 /*
2188                                  * DMA may be already started by udc_queue()
2189                                  * called by gadget drivers completion
2190                                  * routine. This happens when queue
2191                                  * holds one request only.
2192                                  */
2193                                 if (req->dma_going == 0) {
2194                                         /* next dma */
2195                                         if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2196                                                 goto finished;
2197                                         /* write desc pointer */
2198                                         writel(req->td_phys,
2199                                                 &ep->regs->desptr);
2200                                         req->dma_going = 1;
2201                                         /* enable DMA */
2202                                         udc_set_rde(dev);
2203                                 }
2204                         } else {
2205                                 /*
2206                                  * implant BNA dummy descriptor to allow
2207                                  * RXFIFO opening by RDE
2208                                  */
2209                                 if (ep->bna_dummy_req) {
2210                                         /* write desc pointer */
2211                                         writel(ep->bna_dummy_req->td_phys,
2212                                                 &ep->regs->desptr);
2213                                         ep->bna_occurred = 0;
2214                                 }
2215 
2216                                 /*
2217                                  * schedule timer for setting RDE if queue
2218                                  * remains empty to allow ep0 packets pass
2219                                  * through
2220                                  */
2221                                 if (set_rde != 0
2222                                                 && !timer_pending(&udc_timer)) {
2223                                         udc_timer.expires =
2224                                                 jiffies
2225                                                 + HZ*UDC_RDE_TIMER_SECONDS;
2226                                         set_rde = 1;
2227                                         if (!stop_timer)
2228                                                 add_timer(&udc_timer);
2229                                 }
2230                                 if (ep->num != UDC_EP0OUT_IX)
2231                                         dev->data_ep_queued = 0;
2232                         }
2233 
2234                 } else {
2235                         /*
2236                         * RX DMA must be reenabled for each desc in PPBDU mode
2237                         * and must be enabled for PPBNDU mode in case of BNA
2238                         */
2239                         udc_set_rde(dev);
2240                 }
2241 
2242         } else if (ep->cancel_transfer) {
2243                 ret_val = IRQ_HANDLED;
2244                 ep->cancel_transfer = 0;
2245         }
2246 
2247         /* check pending CNAKS */
2248         if (cnak_pending) {
2249                 /* CNAk processing when rxfifo empty only */
2250                 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2251                         udc_process_cnak_queue(dev);
2252         }
2253 
2254         /* clear OUT bits in ep status */
2255         writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2256 finished:
2257         return ret_val;
2258 }
2259 
2260 /* Interrupt handler for data IN traffic */
2261 static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2262 {
2263         irqreturn_t ret_val = IRQ_NONE;
2264         u32 tmp;
2265         u32 epsts;
2266         struct udc_ep *ep;
2267         struct udc_request *req;
2268         struct udc_data_dma *td;
2269         unsigned dma_done;
2270         unsigned len;
2271 
2272         ep = &dev->ep[ep_ix];
2273 
2274         epsts = readl(&ep->regs->sts);
2275         if (use_dma) {
2276                 /* BNA ? */
2277                 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2278                         dev_err(&dev->pdev->dev,
2279                                 "BNA ep%din occurred - DESPTR = %08lx\n",
2280                                 ep->num,
2281                                 (unsigned long) readl(&ep->regs->desptr));
2282 
2283                         /* clear BNA */
2284                         writel(epsts, &ep->regs->sts);
2285                         ret_val = IRQ_HANDLED;
2286                         goto finished;
2287                 }
2288         }
2289         /* HE event ? */
2290         if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2291                 dev_err(&dev->pdev->dev,
2292                         "HE ep%dn occurred - DESPTR = %08lx\n",
2293                         ep->num, (unsigned long) readl(&ep->regs->desptr));
2294 
2295                 /* clear HE */
2296                 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2297                 ret_val = IRQ_HANDLED;
2298                 goto finished;
2299         }
2300 
2301         /* DMA completion */
2302         if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2303                 VDBG(dev, "TDC set- completion\n");
2304                 ret_val = IRQ_HANDLED;
2305                 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2306                         req = list_entry(ep->queue.next,
2307                                         struct udc_request, queue);
2308                         /*
2309                          * length bytes transferred
2310                          * check dma done of last desc. in PPBDU mode
2311                          */
2312                         if (use_dma_ppb_du) {
2313                                 td = udc_get_last_dma_desc(req);
2314                                 if (td) {
2315                                         dma_done =
2316                                                 AMD_GETBITS(td->status,
2317                                                 UDC_DMA_IN_STS_BS);
2318                                         /* don't care DMA done */
2319                                         req->req.actual = req->req.length;
2320                                 }
2321                         } else {
2322                                 /* assume all bytes transferred */
2323                                 req->req.actual = req->req.length;
2324                         }
2325 
2326                         if (req->req.actual == req->req.length) {
2327                                 /* complete req */
2328                                 complete_req(ep, req, 0);
2329                                 req->dma_going = 0;
2330                                 /* further request available ? */
2331                                 if (list_empty(&ep->queue)) {
2332                                         /* disable interrupt */
2333                                         tmp = readl(&dev->regs->ep_irqmsk);
2334                                         tmp |= AMD_BIT(ep->num);
2335                                         writel(tmp, &dev->regs->ep_irqmsk);
2336                                 }
2337                         }
2338                 }
2339                 ep->cancel_transfer = 0;
2340 
2341         }
2342         /*
2343          * status reg has IN bit set and TDC not set (if TDC was handled,
2344          * IN must not be handled (UDC defect) ?
2345          */
2346         if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2347                         && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2348                 ret_val = IRQ_HANDLED;
2349                 if (!list_empty(&ep->queue)) {
2350                         /* next request */
2351                         req = list_entry(ep->queue.next,
2352                                         struct udc_request, queue);
2353                         /* FIFO mode */
2354                         if (!use_dma) {
2355                                 /* write fifo */
2356                                 udc_txfifo_write(ep, &req->req);
2357                                 len = req->req.length - req->req.actual;
2358                                 if (len > ep->ep.maxpacket)
2359                                         len = ep->ep.maxpacket;
2360                                 req->req.actual += len;
2361                                 if (req->req.actual == req->req.length
2362                                         || (len != ep->ep.maxpacket)) {
2363                                         /* complete req */
2364                                         complete_req(ep, req, 0);
2365                                 }
2366                         /* DMA */
2367                         } else if (req && !req->dma_going) {
2368                                 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2369                                         req, req->td_data);
2370                                 if (req->td_data) {
2371 
2372                                         req->dma_going = 1;
2373 
2374                                         /*
2375                                          * unset L bit of first desc.
2376                                          * for chain
2377                                          */
2378                                         if (use_dma_ppb && req->req.length >
2379                                                         ep->ep.maxpacket) {
2380                                                 req->td_data->status &=
2381                                                         AMD_CLEAR_BIT(
2382                                                         UDC_DMA_IN_STS_L);
2383                                         }
2384 
2385                                         /* write desc pointer */
2386                                         writel(req->td_phys, &ep->regs->desptr);
2387 
2388                                         /* set HOST READY */
2389                                         req->td_data->status =
2390                                                 AMD_ADDBITS(
2391                                                 req->td_data->status,
2392                                                 UDC_DMA_IN_STS_BS_HOST_READY,
2393                                                 UDC_DMA_IN_STS_BS);
2394 
2395                                         /* set poll demand bit */
2396                                         tmp = readl(&ep->regs->ctl);
2397                                         tmp |= AMD_BIT(UDC_EPCTL_P);
2398                                         writel(tmp, &ep->regs->ctl);
2399                                 }
2400                         }
2401 
2402                 } else if (!use_dma && ep->in) {
2403                         /* disable interrupt */
2404                         tmp = readl(
2405                                 &dev->regs->ep_irqmsk);
2406                         tmp |= AMD_BIT(ep->num);
2407                         writel(tmp,
2408                                 &dev->regs->ep_irqmsk);
2409                 }
2410         }
2411         /* clear status bits */
2412         writel(epsts, &ep->regs->sts);
2413 
2414 finished:
2415         return ret_val;
2416 
2417 }
2418 
2419 /* Interrupt handler for Control OUT traffic */
2420 static irqreturn_t udc_control_out_isr(struct udc *dev)
2421 __releases(dev->lock)
2422 __acquires(dev->lock)
2423 {
2424         irqreturn_t ret_val = IRQ_NONE;
2425         u32 tmp;
2426         int setup_supported;
2427         u32 count;
2428         int set = 0;
2429         struct udc_ep   *ep;
2430         struct udc_ep   *ep_tmp;
2431 
2432         ep = &dev->ep[UDC_EP0OUT_IX];
2433 
2434         /* clear irq */
2435         writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2436 
2437         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2438         /* check BNA and clear if set */
2439         if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2440                 VDBG(dev, "ep0: BNA set\n");
2441                 writel(AMD_BIT(UDC_EPSTS_BNA),
2442                         &dev->ep[UDC_EP0OUT_IX].regs->sts);
2443                 ep->bna_occurred = 1;
2444                 ret_val = IRQ_HANDLED;
2445                 goto finished;
2446         }
2447 
2448         /* type of data: SETUP or DATA 0 bytes */
2449         tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2450         VDBG(dev, "data_typ = %x\n", tmp);
2451 
2452         /* setup data */
2453         if (tmp == UDC_EPSTS_OUT_SETUP) {
2454                 ret_val = IRQ_HANDLED;
2455 
2456                 ep->dev->stall_ep0in = 0;
2457                 dev->waiting_zlp_ack_ep0in = 0;
2458 
2459                 /* set NAK for EP0_IN */
2460                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2461                 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2462                 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2463                 dev->ep[UDC_EP0IN_IX].naking = 1;
2464                 /* get setup data */
2465                 if (use_dma) {
2466 
2467                         /* clear OUT bits in ep status */
2468                         writel(UDC_EPSTS_OUT_CLEAR,
2469                                 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2470 
2471                         setup_data.data[0] =
2472                                 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2473                         setup_data.data[1] =
2474                                 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2475                         /* set HOST READY */
2476                         dev->ep[UDC_EP0OUT_IX].td_stp->status =
2477                                         UDC_DMA_STP_STS_BS_HOST_READY;
2478                 } else {
2479                         /* read fifo */
2480                         udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2481                 }
2482 
2483                 /* determine direction of control data */
2484                 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2485                         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2486                         /* enable RDE */
2487                         udc_ep0_set_rde(dev);
2488                         set = 0;
2489                 } else {
2490                         dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2491                         /*
2492                          * implant BNA dummy descriptor to allow RXFIFO opening
2493                          * by RDE
2494                          */
2495                         if (ep->bna_dummy_req) {
2496                                 /* write desc pointer */
2497                                 writel(ep->bna_dummy_req->td_phys,
2498                                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2499                                 ep->bna_occurred = 0;
2500                         }
2501 
2502                         set = 1;
2503                         dev->ep[UDC_EP0OUT_IX].naking = 1;
2504                         /*
2505                          * setup timer for enabling RDE (to not enable
2506                          * RXFIFO DMA for data to early)
2507                          */
2508                         set_rde = 1;
2509                         if (!timer_pending(&udc_timer)) {
2510                                 udc_timer.expires = jiffies +
2511                                                         HZ/UDC_RDE_TIMER_DIV;
2512                                 if (!stop_timer)
2513                                         add_timer(&udc_timer);
2514                         }
2515                 }
2516 
2517                 /*
2518                  * mass storage reset must be processed here because
2519                  * next packet may be a CLEAR_FEATURE HALT which would not
2520                  * clear the stall bit when no STALL handshake was received
2521                  * before (autostall can cause this)
2522                  */
2523                 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2524                                 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2525                         DBG(dev, "MSC Reset\n");
2526                         /*
2527                          * clear stall bits
2528                          * only one IN and OUT endpoints are handled
2529                          */
2530                         ep_tmp = &udc->ep[UDC_EPIN_IX];
2531                         udc_set_halt(&ep_tmp->ep, 0);
2532                         ep_tmp = &udc->ep[UDC_EPOUT_IX];
2533                         udc_set_halt(&ep_tmp->ep, 0);
2534                 }
2535 
2536                 /* call gadget with setup data received */
2537                 spin_unlock(&dev->lock);
2538                 setup_supported = dev->driver->setup(&dev->gadget,
2539                                                 &setup_data.request);
2540                 spin_lock(&dev->lock);
2541 
2542                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2543                 /* ep0 in returns data (not zlp) on IN phase */
2544                 if (setup_supported >= 0 && setup_supported <
2545                                 UDC_EP0IN_MAXPACKET) {
2546                         /* clear NAK by writing CNAK in EP0_IN */
2547                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2548                         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2549                         dev->ep[UDC_EP0IN_IX].naking = 0;
2550                         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2551 
2552                 /* if unsupported request then stall */
2553                 } else if (setup_supported < 0) {
2554                         tmp |= AMD_BIT(UDC_EPCTL_S);
2555                         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2556                 } else
2557                         dev->waiting_zlp_ack_ep0in = 1;
2558 
2559 
2560                 /* clear NAK by writing CNAK in EP0_OUT */
2561                 if (!set) {
2562                         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2563                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2564                         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2565                         dev->ep[UDC_EP0OUT_IX].naking = 0;
2566                         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2567                 }
2568 
2569                 if (!use_dma) {
2570                         /* clear OUT bits in ep status */
2571                         writel(UDC_EPSTS_OUT_CLEAR,
2572                                 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2573                 }
2574 
2575         /* data packet 0 bytes */
2576         } else if (tmp == UDC_EPSTS_OUT_DATA) {
2577                 /* clear OUT bits in ep status */
2578                 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2579 
2580                 /* get setup data: only 0 packet */
2581                 if (use_dma) {
2582                         /* no req if 0 packet, just reactivate */
2583                         if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2584                                 VDBG(dev, "ZLP\n");
2585 
2586                                 /* set HOST READY */
2587                                 dev->ep[UDC_EP0OUT_IX].td->status =
2588                                         AMD_ADDBITS(
2589                                         dev->ep[UDC_EP0OUT_IX].td->status,
2590                                         UDC_DMA_OUT_STS_BS_HOST_READY,
2591                                         UDC_DMA_OUT_STS_BS);
2592                                 /* enable RDE */
2593                                 udc_ep0_set_rde(dev);
2594                                 ret_val = IRQ_HANDLED;
2595 
2596                         } else {
2597                                 /* control write */
2598                                 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2599                                 /* re-program desc. pointer for possible ZLPs */
2600                                 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2601                                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2602                                 /* enable RDE */
2603                                 udc_ep0_set_rde(dev);
2604                         }
2605                 } else {
2606 
2607                         /* received number bytes */
2608                         count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2609                         count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2610                         /* out data for fifo mode not working */
2611                         count = 0;
2612 
2613                         /* 0 packet or real data ? */
2614                         if (count != 0) {
2615                                 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2616                         } else {
2617                                 /* dummy read confirm */
2618                                 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2619                                 ret_val = IRQ_HANDLED;
2620                         }
2621                 }
2622         }
2623 
2624         /* check pending CNAKS */
2625         if (cnak_pending) {
2626                 /* CNAk processing when rxfifo empty only */
2627                 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2628                         udc_process_cnak_queue(dev);
2629         }
2630 
2631 finished:
2632         return ret_val;
2633 }
2634 
2635 /* Interrupt handler for Control IN traffic */
2636 static irqreturn_t udc_control_in_isr(struct udc *dev)
2637 {
2638         irqreturn_t ret_val = IRQ_NONE;
2639         u32 tmp;
2640         struct udc_ep *ep;
2641         struct udc_request *req;
2642         unsigned len;
2643 
2644         ep = &dev->ep[UDC_EP0IN_IX];
2645 
2646         /* clear irq */
2647         writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2648 
2649         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2650         /* DMA completion */
2651         if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2652                 VDBG(dev, "isr: TDC clear\n");
2653                 ret_val = IRQ_HANDLED;
2654 
2655                 /* clear TDC bit */
2656                 writel(AMD_BIT(UDC_EPSTS_TDC),
2657                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2658 
2659         /* status reg has IN bit set ? */
2660         } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2661                 ret_val = IRQ_HANDLED;
2662 
2663                 if (ep->dma) {
2664                         /* clear IN bit */
2665                         writel(AMD_BIT(UDC_EPSTS_IN),
2666                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2667                 }
2668                 if (dev->stall_ep0in) {
2669                         DBG(dev, "stall ep0in\n");
2670                         /* halt ep0in */
2671                         tmp = readl(&ep->regs->ctl);
2672                         tmp |= AMD_BIT(UDC_EPCTL_S);
2673                         writel(tmp, &ep->regs->ctl);
2674                 } else {
2675                         if (!list_empty(&ep->queue)) {
2676                                 /* next request */
2677                                 req = list_entry(ep->queue.next,
2678                                                 struct udc_request, queue);
2679 
2680                                 if (ep->dma) {
2681                                         /* write desc pointer */
2682                                         writel(req->td_phys, &ep->regs->desptr);
2683                                         /* set HOST READY */
2684                                         req->td_data->status =
2685                                                 AMD_ADDBITS(
2686                                                 req->td_data->status,
2687                                                 UDC_DMA_STP_STS_BS_HOST_READY,
2688                                                 UDC_DMA_STP_STS_BS);
2689 
2690                                         /* set poll demand bit */
2691                                         tmp =
2692                                         readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2693                                         tmp |= AMD_BIT(UDC_EPCTL_P);
2694                                         writel(tmp,
2695                                         &dev->ep[UDC_EP0IN_IX].regs->ctl);
2696 
2697                                         /* all bytes will be transferred */
2698                                         req->req.actual = req->req.length;
2699 
2700                                         /* complete req */
2701                                         complete_req(ep, req, 0);
2702 
2703                                 } else {
2704                                         /* write fifo */
2705                                         udc_txfifo_write(ep, &req->req);
2706 
2707                                         /* lengh bytes transferred */
2708                                         len = req->req.length - req->req.actual;
2709                                         if (len > ep->ep.maxpacket)
2710                                                 len = ep->ep.maxpacket;
2711 
2712                                         req->req.actual += len;
2713                                         if (req->req.actual == req->req.length
2714                                                 || (len != ep->ep.maxpacket)) {
2715                                                 /* complete req */
2716                                                 complete_req(ep, req, 0);
2717                                         }
2718                                 }
2719 
2720                         }
2721                 }
2722                 ep->halted = 0;
2723                 dev->stall_ep0in = 0;
2724                 if (!ep->dma) {
2725                         /* clear IN bit */
2726                         writel(AMD_BIT(UDC_EPSTS_IN),
2727                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2728                 }
2729         }
2730 
2731         return ret_val;
2732 }
2733 
2734 
2735 /* Interrupt handler for global device events */
2736 static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2737 __releases(dev->lock)
2738 __acquires(dev->lock)
2739 {
2740         irqreturn_t ret_val = IRQ_NONE;
2741         u32 tmp;
2742         u32 cfg;
2743         struct udc_ep *ep;
2744         u16 i;
2745         u8 udc_csr_epix;
2746 
2747         /* SET_CONFIG irq ? */
2748         if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2749                 ret_val = IRQ_HANDLED;
2750 
2751                 /* read config value */
2752                 tmp = readl(&dev->regs->sts);
2753                 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2754                 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2755                 dev->cur_config = cfg;
2756                 dev->set_cfg_not_acked = 1;
2757 
2758                 /* make usb request for gadget driver */
2759                 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2760                 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2761                 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2762 
2763                 /* programm the NE registers */
2764                 for (i = 0; i < UDC_EP_NUM; i++) {
2765                         ep = &dev->ep[i];
2766                         if (ep->in) {
2767 
2768                                 /* ep ix in UDC CSR register space */
2769                                 udc_csr_epix = ep->num;
2770 
2771 
2772                         /* OUT ep */
2773                         } else {
2774                                 /* ep ix in UDC CSR register space */
2775                                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2776                         }
2777 
2778                         tmp = readl(&dev->csr->ne[udc_csr_epix]);
2779                         /* ep cfg */
2780                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2781                                                 UDC_CSR_NE_CFG);
2782                         /* write reg */
2783                         writel(tmp, &dev->csr->ne[udc_csr_epix]);
2784 
2785                         /* clear stall bits */
2786                         ep->halted = 0;
2787                         tmp = readl(&ep->regs->ctl);
2788                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2789                         writel(tmp, &ep->regs->ctl);
2790                 }
2791                 /* call gadget zero with setup data received */
2792                 spin_unlock(&dev->lock);
2793                 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2794                 spin_lock(&dev->lock);
2795 
2796         } /* SET_INTERFACE ? */
2797         if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2798                 ret_val = IRQ_HANDLED;
2799 
2800                 dev->set_cfg_not_acked = 1;
2801                 /* read interface and alt setting values */
2802                 tmp = readl(&dev->regs->sts);
2803                 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2804                 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2805 
2806                 /* make usb request for gadget driver */
2807                 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2808                 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2809                 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2810                 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2811                 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2812 
2813                 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2814                                 dev->cur_alt, dev->cur_intf);
2815 
2816                 /* programm the NE registers */
2817                 for (i = 0; i < UDC_EP_NUM; i++) {
2818                         ep = &dev->ep[i];
2819                         if (ep->in) {
2820 
2821                                 /* ep ix in UDC CSR register space */
2822                                 udc_csr_epix = ep->num;
2823 
2824 
2825                         /* OUT ep */
2826                         } else {
2827                                 /* ep ix in UDC CSR register space */
2828                                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2829                         }
2830 
2831                         /* UDC CSR reg */
2832                         /* set ep values */
2833                         tmp = readl(&dev->csr->ne[udc_csr_epix]);
2834                         /* ep interface */
2835                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2836                                                 UDC_CSR_NE_INTF);
2837                         /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2838                         /* ep alt */
2839                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2840                                                 UDC_CSR_NE_ALT);
2841                         /* write reg */
2842                         writel(tmp, &dev->csr->ne[udc_csr_epix]);
2843 
2844                         /* clear stall bits */
2845                         ep->halted = 0;
2846                         tmp = readl(&ep->regs->ctl);
2847                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2848                         writel(tmp, &ep->regs->ctl);
2849                 }
2850 
2851                 /* call gadget zero with setup data received */
2852                 spin_unlock(&dev->lock);
2853                 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2854                 spin_lock(&dev->lock);
2855 
2856         } /* USB reset */
2857         if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2858                 DBG(dev, "USB Reset interrupt\n");
2859                 ret_val = IRQ_HANDLED;
2860 
2861                 /* allow soft reset when suspend occurs */
2862                 soft_reset_occured = 0;
2863 
2864                 dev->waiting_zlp_ack_ep0in = 0;
2865                 dev->set_cfg_not_acked = 0;
2866 
2867                 /* mask not needed interrupts */
2868                 udc_mask_unused_interrupts(dev);
2869 
2870                 /* call gadget to resume and reset configs etc. */
2871                 spin_unlock(&dev->lock);
2872                 if (dev->sys_suspended && dev->driver->resume) {
2873                         dev->driver->resume(&dev->gadget);
2874                         dev->sys_suspended = 0;
2875                 }
2876                 dev->driver->disconnect(&dev->gadget);
2877                 spin_lock(&dev->lock);
2878 
2879                 /* disable ep0 to empty req queue */
2880                 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2881                 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2882 
2883                 /* soft reset when rxfifo not empty */
2884                 tmp = readl(&dev->regs->sts);
2885                 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2886                                 && !soft_reset_after_usbreset_occured) {
2887                         udc_soft_reset(dev);
2888                         soft_reset_after_usbreset_occured++;
2889                 }
2890 
2891                 /*
2892                  * DMA reset to kill potential old DMA hw hang,
2893                  * POLL bit is already reset by ep_init() through
2894                  * disconnect()
2895                  */
2896                 DBG(dev, "DMA machine reset\n");
2897                 tmp = readl(&dev->regs->cfg);
2898                 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2899                 writel(tmp, &dev->regs->cfg);
2900 
2901                 /* put into initial config */
2902                 udc_basic_init(dev);
2903 
2904                 /* enable device setup interrupts */
2905                 udc_enable_dev_setup_interrupts(dev);
2906 
2907                 /* enable suspend interrupt */
2908                 tmp = readl(&dev->regs->irqmsk);
2909                 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2910                 writel(tmp, &dev->regs->irqmsk);
2911 
2912         } /* USB suspend */
2913         if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2914                 DBG(dev, "USB Suspend interrupt\n");
2915                 ret_val = IRQ_HANDLED;
2916                 if (dev->driver->suspend) {
2917                         spin_unlock(&dev->lock);
2918                         dev->sys_suspended = 1;
2919                         dev->driver->suspend(&dev->gadget);
2920                         spin_lock(&dev->lock);
2921                 }
2922         } /* new speed ? */
2923         if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2924                 DBG(dev, "ENUM interrupt\n");
2925                 ret_val = IRQ_HANDLED;
2926                 soft_reset_after_usbreset_occured = 0;
2927 
2928                 /* disable ep0 to empty req queue */
2929                 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2930                 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2931 
2932                 /* link up all endpoints */
2933                 udc_setup_endpoints(dev);
2934                 dev_info(&dev->pdev->dev, "Connect: %s\n",
2935                          usb_speed_string(dev->gadget.speed));
2936 
2937                 /* init ep 0 */
2938                 activate_control_endpoints(dev);
2939 
2940                 /* enable ep0 interrupts */
2941                 udc_enable_ep0_interrupts(dev);
2942         }
2943         /* session valid change interrupt */
2944         if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
2945                 DBG(dev, "USB SVC interrupt\n");
2946                 ret_val = IRQ_HANDLED;
2947 
2948                 /* check that session is not valid to detect disconnect */
2949                 tmp = readl(&dev->regs->sts);
2950                 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
2951                         /* disable suspend interrupt */
2952                         tmp = readl(&dev->regs->irqmsk);
2953                         tmp |= AMD_BIT(UDC_DEVINT_US);
2954                         writel(tmp, &dev->regs->irqmsk);
2955                         DBG(dev, "USB Disconnect (session valid low)\n");
2956                         /* cleanup on disconnect */
2957                         usb_disconnect(udc);
2958                 }
2959 
2960         }
2961 
2962         return ret_val;
2963 }
2964 
2965 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
2966 static irqreturn_t udc_irq(int irq, void *pdev)
2967 {
2968         struct udc *dev = pdev;
2969         u32 reg;
2970         u16 i;
2971         u32 ep_irq;
2972         irqreturn_t ret_val = IRQ_NONE;
2973 
2974         spin_lock(&dev->lock);
2975 
2976         /* check for ep irq */
2977         reg = readl(&dev->regs->ep_irqsts);
2978         if (reg) {
2979                 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
2980                         ret_val |= udc_control_out_isr(dev);
2981                 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
2982                         ret_val |= udc_control_in_isr(dev);
2983 
2984                 /*
2985                  * data endpoint
2986                  * iterate ep's
2987                  */
2988                 for (i = 1; i < UDC_EP_NUM; i++) {
2989                         ep_irq = 1 << i;
2990                         if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
2991                                 continue;
2992 
2993                         /* clear irq status */
2994                         writel(ep_irq, &dev->regs->ep_irqsts);
2995 
2996                         /* irq for out ep ? */
2997                         if (i > UDC_EPIN_NUM)
2998                                 ret_val |= udc_data_out_isr(dev, i);
2999                         else
3000                                 ret_val |= udc_data_in_isr(dev, i);
3001                 }
3002 
3003         }
3004 
3005 
3006         /* check for dev irq */
3007         reg = readl(&dev->regs->irqsts);
3008         if (reg) {
3009                 /* clear irq */
3010                 writel(reg, &dev->regs->irqsts);
3011                 ret_val |= udc_dev_isr(dev, reg);
3012         }
3013 
3014 
3015         spin_unlock(&dev->lock);
3016         return ret_val;
3017 }
3018 
3019 /* Tears down device */
3020 static void gadget_release(struct device *pdev)
3021 {
3022         struct amd5536udc *dev = dev_get_drvdata(pdev);
3023         kfree(dev);
3024 }
3025 
3026 /* Cleanup on device remove */
3027 static void udc_remove(struct udc *dev)
3028 {
3029         /* remove timer */
3030         stop_timer++;
3031         if (timer_pending(&udc_timer))
3032                 wait_for_completion(&on_exit);
3033         if (udc_timer.data)
3034                 del_timer_sync(&udc_timer);
3035         /* remove pollstall timer */
3036         stop_pollstall_timer++;
3037         if (timer_pending(&udc_pollstall_timer))
3038                 wait_for_completion(&on_pollstall_exit);
3039         if (udc_pollstall_timer.data)
3040                 del_timer_sync(&udc_pollstall_timer);
3041         udc = NULL;
3042 }
3043 
3044 /* Reset all pci context */
3045 static void udc_pci_remove(struct pci_dev *pdev)
3046 {
3047         struct udc              *dev;
3048 
3049         dev = pci_get_drvdata(pdev);
3050 
3051         usb_del_gadget_udc(&udc->gadget);
3052         /* gadget driver must not be registered */
3053         BUG_ON(dev->driver != NULL);
3054 
3055         /* dma pool cleanup */
3056         if (dev->data_requests)
3057                 pci_pool_destroy(dev->data_requests);
3058 
3059         if (dev->stp_requests) {
3060                 /* cleanup DMA desc's for ep0in */
3061                 pci_pool_free(dev->stp_requests,
3062                         dev->ep[UDC_EP0OUT_IX].td_stp,
3063                         dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3064                 pci_pool_free(dev->stp_requests,
3065                         dev->ep[UDC_EP0OUT_IX].td,
3066                         dev->ep[UDC_EP0OUT_IX].td_phys);
3067 
3068                 pci_pool_destroy(dev->stp_requests);
3069         }
3070 
3071         /* reset controller */
3072         writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
3073         if (dev->irq_registered)
3074                 free_irq(pdev->irq, dev);
3075         if (dev->regs)
3076                 iounmap(dev->regs);
3077         if (dev->mem_region)
3078                 release_mem_region(pci_resource_start(pdev, 0),
3079                                 pci_resource_len(pdev, 0));
3080         if (dev->active)
3081                 pci_disable_device(pdev);
3082 
3083         udc_remove(dev);
3084 }
3085 
3086 /* create dma pools on init */
3087 static int init_dma_pools(struct udc *dev)
3088 {
3089         struct udc_stp_dma      *td_stp;
3090         struct udc_data_dma     *td_data;
3091         int retval;
3092 
3093         /* consistent DMA mode setting ? */
3094         if (use_dma_ppb) {
3095                 use_dma_bufferfill_mode = 0;
3096         } else {
3097                 use_dma_ppb_du = 0;
3098                 use_dma_bufferfill_mode = 1;
3099         }
3100 
3101         /* DMA setup */
3102         dev->data_requests = dma_pool_create("data_requests", NULL,
3103                 sizeof(struct udc_data_dma), 0, 0);
3104         if (!dev->data_requests) {
3105                 DBG(dev, "can't get request data pool\n");
3106                 retval = -ENOMEM;
3107                 goto finished;
3108         }
3109 
3110         /* EP0 in dma regs = dev control regs */
3111         dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3112 
3113         /* dma desc for setup data */
3114         dev->stp_requests = dma_pool_create("setup requests", NULL,
3115                 sizeof(struct udc_stp_dma), 0, 0);
3116         if (!dev->stp_requests) {
3117                 DBG(dev, "can't get stp request pool\n");
3118                 retval = -ENOMEM;
3119                 goto finished;
3120         }
3121         /* setup */
3122         td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3123                                 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3124         if (td_stp == NULL) {
3125                 retval = -ENOMEM;
3126                 goto finished;
3127         }
3128         dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3129 
3130         /* data: 0 packets !? */
3131         td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3132                                 &dev->ep[UDC_EP0OUT_IX].td_phys);
3133         if (td_data == NULL) {
3134                 retval = -ENOMEM;
3135                 goto finished;
3136         }
3137         dev->ep[UDC_EP0OUT_IX].td = td_data;
3138         return 0;
3139 
3140 finished:
3141         return retval;
3142 }
3143 
3144 /* Called by pci bus driver to init pci context */
3145 static int udc_pci_probe(
3146         struct pci_dev *pdev,
3147         const struct pci_device_id *id
3148 )
3149 {
3150         struct udc              *dev;
3151         unsigned long           resource;
3152         unsigned long           len;
3153         int                     retval = 0;
3154 
3155         /* one udc only */
3156         if (udc) {
3157                 dev_dbg(&pdev->dev, "already probed\n");
3158                 return -EBUSY;
3159         }
3160 
3161         /* init */
3162         dev = kzalloc(sizeof(struct udc), GFP_KERNEL);
3163         if (!dev) {
3164                 retval = -ENOMEM;
3165                 goto finished;
3166         }
3167 
3168         /* pci setup */
3169         if (pci_enable_device(pdev) < 0) {
3170                 kfree(dev);
3171                 dev = NULL;
3172                 retval = -ENODEV;
3173                 goto finished;
3174         }
3175         dev->active = 1;
3176 
3177         /* PCI resource allocation */
3178         resource = pci_resource_start(pdev, 0);
3179         len = pci_resource_len(pdev, 0);
3180 
3181         if (!request_mem_region(resource, len, name)) {
3182                 dev_dbg(&pdev->dev, "pci device used already\n");
3183                 kfree(dev);
3184                 dev = NULL;
3185                 retval = -EBUSY;
3186                 goto finished;
3187         }
3188         dev->mem_region = 1;
3189 
3190         dev->virt_addr = ioremap_nocache(resource, len);
3191         if (dev->virt_addr == NULL) {
3192                 dev_dbg(&pdev->dev, "start address cannot be mapped\n");
3193                 kfree(dev);
3194                 dev = NULL;
3195                 retval = -EFAULT;
3196                 goto finished;
3197         }
3198 
3199         if (!pdev->irq) {
3200                 dev_err(&pdev->dev, "irq not set\n");
3201                 kfree(dev);
3202                 dev = NULL;
3203                 retval = -ENODEV;
3204                 goto finished;
3205         }
3206 
3207         spin_lock_init(&dev->lock);
3208         /* udc csr registers base */
3209         dev->csr = dev->virt_addr + UDC_CSR_ADDR;
3210         /* dev registers base */
3211         dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
3212         /* ep registers base */
3213         dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
3214         /* fifo's base */
3215         dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
3216         dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
3217 
3218         if (request_irq(pdev->irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
3219                 dev_dbg(&pdev->dev, "request_irq(%d) fail\n", pdev->irq);
3220                 kfree(dev);
3221                 dev = NULL;
3222                 retval = -EBUSY;
3223                 goto finished;
3224         }
3225         dev->irq_registered = 1;
3226 
3227         pci_set_drvdata(pdev, dev);
3228 
3229         /* chip revision for Hs AMD5536 */
3230         dev->chiprev = pdev->revision;
3231 
3232         pci_set_master(pdev);
3233         pci_try_set_mwi(pdev);
3234 
3235         /* init dma pools */
3236         if (use_dma) {
3237                 retval = init_dma_pools(dev);
3238                 if (retval != 0)
3239                         goto finished;
3240         }
3241 
3242         dev->phys_addr = resource;
3243         dev->irq = pdev->irq;
3244         dev->pdev = pdev;
3245 
3246         /* general probing */
3247         if (udc_probe(dev) == 0)
3248                 return 0;
3249 
3250 finished:
3251         if (dev)
3252                 udc_pci_remove(pdev);
3253         return retval;
3254 }
3255 
3256 /* general probe */
3257 static int udc_probe(struct udc *dev)
3258 {
3259         char            tmp[128];
3260         u32             reg;
3261         int             retval;
3262 
3263         /* mark timer as not initialized */
3264         udc_timer.data = 0;
3265         udc_pollstall_timer.data = 0;
3266 
3267         /* device struct setup */
3268         dev->gadget.ops = &udc_ops;
3269 
3270         dev_set_name(&dev->gadget.dev, "gadget");
3271         dev->gadget.name = name;
3272         dev->gadget.max_speed = USB_SPEED_HIGH;
3273 
3274         /* init registers, interrupts, ... */
3275         startup_registers(dev);
3276 
3277         dev_info(&dev->pdev->dev, "%s\n", mod_desc);
3278 
3279         snprintf(tmp, sizeof tmp, "%d", dev->irq);
3280         dev_info(&dev->pdev->dev,
3281                 "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3282                 tmp, dev->phys_addr, dev->chiprev,
3283                 (dev->chiprev == UDC_HSA0_REV) ? "A0" : "B1");
3284         strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3285         if (dev->chiprev == UDC_HSA0_REV) {
3286                 dev_err(&dev->pdev->dev, "chip revision is A0; too old\n");
3287                 retval = -ENODEV;
3288                 goto finished;
3289         }
3290         dev_info(&dev->pdev->dev,
3291                 "driver version: %s(for Geode5536 B1)\n", tmp);
3292         udc = dev;
3293 
3294         retval = usb_add_gadget_udc_release(&udc->pdev->dev, &dev->gadget,
3295                         gadget_release);
3296         if (retval)
3297                 goto finished;
3298 
3299         /* timer init */
3300         init_timer(&udc_timer);
3301         udc_timer.function = udc_timer_function;
3302         udc_timer.data = 1;
3303         /* timer pollstall init */
3304         init_timer(&udc_pollstall_timer);
3305         udc_pollstall_timer.function = udc_pollstall_timer_function;
3306         udc_pollstall_timer.data = 1;
3307 
3308         /* set SD */
3309         reg = readl(&dev->regs->ctl);
3310         reg |= AMD_BIT(UDC_DEVCTL_SD);
3311         writel(reg, &dev->regs->ctl);
3312 
3313         /* print dev register info */
3314         print_regs(dev);
3315 
3316         return 0;
3317 
3318 finished:
3319         return retval;
3320 }
3321 
3322 /* Initiates a remote wakeup */
3323 static int udc_remote_wakeup(struct udc *dev)
3324 {
3325         unsigned long flags;
3326         u32 tmp;
3327 
3328         DBG(dev, "UDC initiates remote wakeup\n");
3329 
3330         spin_lock_irqsave(&dev->lock, flags);
3331 
3332         tmp = readl(&dev->regs->ctl);
3333         tmp |= AMD_BIT(UDC_DEVCTL_RES);
3334         writel(tmp, &dev->regs->ctl);
3335         tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
3336         writel(tmp, &dev->regs->ctl);
3337 
3338         spin_unlock_irqrestore(&dev->lock, flags);
3339         return 0;
3340 }
3341 
3342 /* PCI device parameters */
3343 static const struct pci_device_id pci_id[] = {
3344         {
3345                 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x2096),
3346                 .class =        (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3347                 .class_mask =   0xffffffff,
3348         },
3349         {},
3350 };
3351 MODULE_DEVICE_TABLE(pci, pci_id);
3352 
3353 /* PCI functions */
3354 static struct pci_driver udc_pci_driver = {
3355         .name =         (char *) name,
3356         .id_table =     pci_id,
3357         .probe =        udc_pci_probe,
3358         .remove =       udc_pci_remove,
3359 };
3360 
3361 module_pci_driver(udc_pci_driver);
3362 
3363 MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3364 MODULE_AUTHOR("Thomas Dahlmann");
3365 MODULE_LICENSE("GPL");
3366 
3367 

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