Version:  2.0.40 2.2.26 2.4.37 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7

Linux/drivers/usb/dwc3/core.c

  1 /**
  2  * core.c - DesignWare USB3 DRD Controller Core file
  3  *
  4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5  *
  6  * Authors: Felipe Balbi <balbi@ti.com>,
  7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8  *
  9  * This program is free software: you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2  of
 11  * the License as published by the Free Software Foundation.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 20  */
 21 
 22 #include <linux/version.h>
 23 #include <linux/module.h>
 24 #include <linux/kernel.h>
 25 #include <linux/slab.h>
 26 #include <linux/spinlock.h>
 27 #include <linux/platform_device.h>
 28 #include <linux/pm_runtime.h>
 29 #include <linux/interrupt.h>
 30 #include <linux/ioport.h>
 31 #include <linux/io.h>
 32 #include <linux/list.h>
 33 #include <linux/delay.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/of.h>
 36 #include <linux/acpi.h>
 37 #include <linux/pinctrl/consumer.h>
 38 
 39 #include <linux/usb/ch9.h>
 40 #include <linux/usb/gadget.h>
 41 #include <linux/usb/of.h>
 42 #include <linux/usb/otg.h>
 43 
 44 #include "platform_data.h"
 45 #include "core.h"
 46 #include "gadget.h"
 47 #include "io.h"
 48 
 49 #include "debug.h"
 50 
 51 /* -------------------------------------------------------------------------- */
 52 
 53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 54 {
 55         u32 reg;
 56 
 57         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 58         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 59         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 60         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 61 }
 62 
 63 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 64 {
 65         struct dwc3             *dwc = dep->dwc;
 66         u32                     reg;
 67 
 68         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 69                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 70                         DWC3_GDBGFIFOSPACE_TYPE(type));
 71 
 72         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 73 
 74         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 75 }
 76 
 77 /**
 78  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 79  * @dwc: pointer to our context structure
 80  */
 81 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 82 {
 83         u32             reg;
 84         int             retries = 1000;
 85         int             ret;
 86 
 87         usb_phy_init(dwc->usb2_phy);
 88         usb_phy_init(dwc->usb3_phy);
 89         ret = phy_init(dwc->usb2_generic_phy);
 90         if (ret < 0)
 91                 return ret;
 92 
 93         ret = phy_init(dwc->usb3_generic_phy);
 94         if (ret < 0) {
 95                 phy_exit(dwc->usb2_generic_phy);
 96                 return ret;
 97         }
 98 
 99         /*
100          * We're resetting only the device side because, if we're in host mode,
101          * XHCI driver will reset the host block. If dwc3 was configured for
102          * host-only mode, then we can return early.
103          */
104         if (dwc->dr_mode == USB_DR_MODE_HOST)
105                 return 0;
106 
107         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
108         reg |= DWC3_DCTL_CSFTRST;
109         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
110 
111         do {
112                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
113                 if (!(reg & DWC3_DCTL_CSFTRST))
114                         return 0;
115 
116                 udelay(1);
117         } while (--retries);
118 
119         return -ETIMEDOUT;
120 }
121 
122 /**
123  * dwc3_soft_reset - Issue soft reset
124  * @dwc: Pointer to our controller context structure
125  */
126 static int dwc3_soft_reset(struct dwc3 *dwc)
127 {
128         unsigned long timeout;
129         u32 reg;
130 
131         timeout = jiffies + msecs_to_jiffies(500);
132         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
133         do {
134                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
135                 if (!(reg & DWC3_DCTL_CSFTRST))
136                         break;
137 
138                 if (time_after(jiffies, timeout)) {
139                         dev_err(dwc->dev, "Reset Timed Out\n");
140                         return -ETIMEDOUT;
141                 }
142 
143                 cpu_relax();
144         } while (true);
145 
146         return 0;
147 }
148 
149 /*
150  * dwc3_frame_length_adjustment - Adjusts frame length if required
151  * @dwc3: Pointer to our controller context structure
152  * @fladj: Value of GFLADJ_30MHZ to adjust frame length
153  */
154 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
155 {
156         u32 reg;
157         u32 dft;
158 
159         if (dwc->revision < DWC3_REVISION_250A)
160                 return;
161 
162         if (fladj == 0)
163                 return;
164 
165         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
166         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
167         if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
168             "request value same as default, ignoring\n")) {
169                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
170                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
171                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
172         }
173 }
174 
175 /**
176  * dwc3_free_one_event_buffer - Frees one event buffer
177  * @dwc: Pointer to our controller context structure
178  * @evt: Pointer to event buffer to be freed
179  */
180 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
181                 struct dwc3_event_buffer *evt)
182 {
183         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
184 }
185 
186 /**
187  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
188  * @dwc: Pointer to our controller context structure
189  * @length: size of the event buffer
190  *
191  * Returns a pointer to the allocated event buffer structure on success
192  * otherwise ERR_PTR(errno).
193  */
194 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
195                 unsigned length)
196 {
197         struct dwc3_event_buffer        *evt;
198 
199         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
200         if (!evt)
201                 return ERR_PTR(-ENOMEM);
202 
203         evt->dwc        = dwc;
204         evt->length     = length;
205         evt->buf        = dma_alloc_coherent(dwc->dev, length,
206                         &evt->dma, GFP_KERNEL);
207         if (!evt->buf)
208                 return ERR_PTR(-ENOMEM);
209 
210         return evt;
211 }
212 
213 /**
214  * dwc3_free_event_buffers - frees all allocated event buffers
215  * @dwc: Pointer to our controller context structure
216  */
217 static void dwc3_free_event_buffers(struct dwc3 *dwc)
218 {
219         struct dwc3_event_buffer        *evt;
220 
221         evt = dwc->ev_buf;
222         if (evt)
223                 dwc3_free_one_event_buffer(dwc, evt);
224 }
225 
226 /**
227  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
228  * @dwc: pointer to our controller context structure
229  * @length: size of event buffer
230  *
231  * Returns 0 on success otherwise negative errno. In the error case, dwc
232  * may contain some buffers allocated but not all which were requested.
233  */
234 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
235 {
236         struct dwc3_event_buffer *evt;
237 
238         evt = dwc3_alloc_one_event_buffer(dwc, length);
239         if (IS_ERR(evt)) {
240                 dev_err(dwc->dev, "can't allocate event buffer\n");
241                 return PTR_ERR(evt);
242         }
243         dwc->ev_buf = evt;
244 
245         return 0;
246 }
247 
248 /**
249  * dwc3_event_buffers_setup - setup our allocated event buffers
250  * @dwc: pointer to our controller context structure
251  *
252  * Returns 0 on success otherwise negative errno.
253  */
254 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
255 {
256         struct dwc3_event_buffer        *evt;
257 
258         evt = dwc->ev_buf;
259         dwc3_trace(trace_dwc3_core,
260                         "Event buf %p dma %08llx length %d\n",
261                         evt->buf, (unsigned long long) evt->dma,
262                         evt->length);
263 
264         evt->lpos = 0;
265 
266         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
267                         lower_32_bits(evt->dma));
268         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
269                         upper_32_bits(evt->dma));
270         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
271                         DWC3_GEVNTSIZ_SIZE(evt->length));
272         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
273 
274         return 0;
275 }
276 
277 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
278 {
279         struct dwc3_event_buffer        *evt;
280 
281         evt = dwc->ev_buf;
282 
283         evt->lpos = 0;
284 
285         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
286         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
287         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
288                         | DWC3_GEVNTSIZ_SIZE(0));
289         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
290 }
291 
292 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
293 {
294         if (!dwc->has_hibernation)
295                 return 0;
296 
297         if (!dwc->nr_scratch)
298                 return 0;
299 
300         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
301                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
302         if (!dwc->scratchbuf)
303                 return -ENOMEM;
304 
305         return 0;
306 }
307 
308 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
309 {
310         dma_addr_t scratch_addr;
311         u32 param;
312         int ret;
313 
314         if (!dwc->has_hibernation)
315                 return 0;
316 
317         if (!dwc->nr_scratch)
318                 return 0;
319 
320          /* should never fall here */
321         if (!WARN_ON(dwc->scratchbuf))
322                 return 0;
323 
324         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
325                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
326                         DMA_BIDIRECTIONAL);
327         if (dma_mapping_error(dwc->dev, scratch_addr)) {
328                 dev_err(dwc->dev, "failed to map scratch buffer\n");
329                 ret = -EFAULT;
330                 goto err0;
331         }
332 
333         dwc->scratch_addr = scratch_addr;
334 
335         param = lower_32_bits(scratch_addr);
336 
337         ret = dwc3_send_gadget_generic_command(dwc,
338                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
339         if (ret < 0)
340                 goto err1;
341 
342         param = upper_32_bits(scratch_addr);
343 
344         ret = dwc3_send_gadget_generic_command(dwc,
345                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
346         if (ret < 0)
347                 goto err1;
348 
349         return 0;
350 
351 err1:
352         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
353                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
354 
355 err0:
356         return ret;
357 }
358 
359 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
360 {
361         if (!dwc->has_hibernation)
362                 return;
363 
364         if (!dwc->nr_scratch)
365                 return;
366 
367          /* should never fall here */
368         if (!WARN_ON(dwc->scratchbuf))
369                 return;
370 
371         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
372                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
373         kfree(dwc->scratchbuf);
374 }
375 
376 static void dwc3_core_num_eps(struct dwc3 *dwc)
377 {
378         struct dwc3_hwparams    *parms = &dwc->hwparams;
379 
380         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
381         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
382 
383         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
384                         dwc->num_in_eps, dwc->num_out_eps);
385 }
386 
387 static void dwc3_cache_hwparams(struct dwc3 *dwc)
388 {
389         struct dwc3_hwparams    *parms = &dwc->hwparams;
390 
391         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
392         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
393         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
394         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
395         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
396         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
397         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
398         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
399         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
400 }
401 
402 /**
403  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
404  * @dwc: Pointer to our controller context structure
405  *
406  * Returns 0 on success. The USB PHY interfaces are configured but not
407  * initialized. The PHY interfaces and the PHYs get initialized together with
408  * the core in dwc3_core_init.
409  */
410 static int dwc3_phy_setup(struct dwc3 *dwc)
411 {
412         u32 reg;
413         int ret;
414 
415         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
416 
417         /*
418          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
419          * to '' during coreConsultant configuration. So default value
420          * will be '' when the core is reset. Application needs to set it
421          * to '1' after the core initialization is completed.
422          */
423         if (dwc->revision > DWC3_REVISION_194A)
424                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
425 
426         if (dwc->u2ss_inp3_quirk)
427                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
428 
429         if (dwc->dis_rxdet_inp3_quirk)
430                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
431 
432         if (dwc->req_p1p2p3_quirk)
433                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
434 
435         if (dwc->del_p1p2p3_quirk)
436                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
437 
438         if (dwc->del_phy_power_chg_quirk)
439                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
440 
441         if (dwc->lfps_filter_quirk)
442                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
443 
444         if (dwc->rx_detect_poll_quirk)
445                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
446 
447         if (dwc->tx_de_emphasis_quirk)
448                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
449 
450         if (dwc->dis_u3_susphy_quirk)
451                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
452 
453         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
454 
455         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
456 
457         /* Select the HS PHY interface */
458         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
459         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
460                 if (dwc->hsphy_interface &&
461                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
462                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
463                         break;
464                 } else if (dwc->hsphy_interface &&
465                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
466                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
467                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
468                 } else {
469                         /* Relying on default value. */
470                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
471                                 break;
472                 }
473                 /* FALLTHROUGH */
474         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
475                 /* Making sure the interface and PHY are operational */
476                 ret = dwc3_soft_reset(dwc);
477                 if (ret)
478                         return ret;
479 
480                 udelay(1);
481 
482                 ret = dwc3_ulpi_init(dwc);
483                 if (ret)
484                         return ret;
485                 /* FALLTHROUGH */
486         default:
487                 break;
488         }
489 
490         /*
491          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
492          * '' during coreConsultant configuration. So default value will
493          * be '' when the core is reset. Application needs to set it to
494          * '1' after the core initialization is completed.
495          */
496         if (dwc->revision > DWC3_REVISION_194A)
497                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
498 
499         if (dwc->dis_u2_susphy_quirk)
500                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
501 
502         if (dwc->dis_enblslpm_quirk)
503                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
504 
505         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
506 
507         return 0;
508 }
509 
510 /**
511  * dwc3_core_init - Low-level initialization of DWC3 Core
512  * @dwc: Pointer to our controller context structure
513  *
514  * Returns 0 on success otherwise negative errno.
515  */
516 static int dwc3_core_init(struct dwc3 *dwc)
517 {
518         u32                     hwparams4 = dwc->hwparams.hwparams4;
519         u32                     reg;
520         int                     ret;
521 
522         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
523         /* This should read as U3 followed by revision number */
524         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
525                 /* Detected DWC_usb3 IP */
526                 dwc->revision = reg;
527         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
528                 /* Detected DWC_usb31 IP */
529                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
530                 dwc->revision |= DWC3_REVISION_IS_DWC31;
531         } else {
532                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
533                 ret = -ENODEV;
534                 goto err0;
535         }
536 
537         /*
538          * Write Linux Version Code to our GUID register so it's easy to figure
539          * out which kernel version a bug was found.
540          */
541         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
542 
543         /* Handle USB2.0-only core configuration */
544         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
545                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
546                 if (dwc->maximum_speed == USB_SPEED_SUPER)
547                         dwc->maximum_speed = USB_SPEED_HIGH;
548         }
549 
550         /* issue device SoftReset too */
551         ret = dwc3_soft_reset(dwc);
552         if (ret)
553                 goto err0;
554 
555         ret = dwc3_core_soft_reset(dwc);
556         if (ret)
557                 goto err0;
558 
559         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
560         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
561 
562         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
563         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
564                 /**
565                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
566                  * issue which would cause xHCI compliance tests to fail.
567                  *
568                  * Because of that we cannot enable clock gating on such
569                  * configurations.
570                  *
571                  * Refers to:
572                  *
573                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
574                  * SOF/ITP Mode Used
575                  */
576                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
577                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
578                                 (dwc->revision >= DWC3_REVISION_210A &&
579                                 dwc->revision <= DWC3_REVISION_250A))
580                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
581                 else
582                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
583                 break;
584         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
585                 /* enable hibernation here */
586                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
587 
588                 /*
589                  * REVISIT Enabling this bit so that host-mode hibernation
590                  * will work. Device-mode hibernation is not yet implemented.
591                  */
592                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
593                 break;
594         default:
595                 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
596         }
597 
598         /* check if current dwc3 is on simulation board */
599         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
600                 dwc3_trace(trace_dwc3_core,
601                                 "running on FPGA platform\n");
602                 dwc->is_fpga = true;
603         }
604 
605         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
606                         "disable_scramble cannot be used on non-FPGA builds\n");
607 
608         if (dwc->disable_scramble_quirk && dwc->is_fpga)
609                 reg |= DWC3_GCTL_DISSCRAMBLE;
610         else
611                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
612 
613         if (dwc->u2exit_lfps_quirk)
614                 reg |= DWC3_GCTL_U2EXIT_LFPS;
615 
616         /*
617          * WORKAROUND: DWC3 revisions <1.90a have a bug
618          * where the device can fail to connect at SuperSpeed
619          * and falls back to high-speed mode which causes
620          * the device to enter a Connect/Disconnect loop
621          */
622         if (dwc->revision < DWC3_REVISION_190A)
623                 reg |= DWC3_GCTL_U2RSTECN;
624 
625         dwc3_core_num_eps(dwc);
626 
627         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
628 
629         ret = dwc3_alloc_scratch_buffers(dwc);
630         if (ret)
631                 goto err1;
632 
633         ret = dwc3_setup_scratch_buffers(dwc);
634         if (ret)
635                 goto err2;
636 
637         return 0;
638 
639 err2:
640         dwc3_free_scratch_buffers(dwc);
641 
642 err1:
643         usb_phy_shutdown(dwc->usb2_phy);
644         usb_phy_shutdown(dwc->usb3_phy);
645         phy_exit(dwc->usb2_generic_phy);
646         phy_exit(dwc->usb3_generic_phy);
647 
648 err0:
649         return ret;
650 }
651 
652 static void dwc3_core_exit(struct dwc3 *dwc)
653 {
654         dwc3_free_scratch_buffers(dwc);
655         usb_phy_shutdown(dwc->usb2_phy);
656         usb_phy_shutdown(dwc->usb3_phy);
657         phy_exit(dwc->usb2_generic_phy);
658         phy_exit(dwc->usb3_generic_phy);
659 }
660 
661 static int dwc3_core_get_phy(struct dwc3 *dwc)
662 {
663         struct device           *dev = dwc->dev;
664         struct device_node      *node = dev->of_node;
665         int ret;
666 
667         if (node) {
668                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
669                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
670         } else {
671                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
672                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
673         }
674 
675         if (IS_ERR(dwc->usb2_phy)) {
676                 ret = PTR_ERR(dwc->usb2_phy);
677                 if (ret == -ENXIO || ret == -ENODEV) {
678                         dwc->usb2_phy = NULL;
679                 } else if (ret == -EPROBE_DEFER) {
680                         return ret;
681                 } else {
682                         dev_err(dev, "no usb2 phy configured\n");
683                         return ret;
684                 }
685         }
686 
687         if (IS_ERR(dwc->usb3_phy)) {
688                 ret = PTR_ERR(dwc->usb3_phy);
689                 if (ret == -ENXIO || ret == -ENODEV) {
690                         dwc->usb3_phy = NULL;
691                 } else if (ret == -EPROBE_DEFER) {
692                         return ret;
693                 } else {
694                         dev_err(dev, "no usb3 phy configured\n");
695                         return ret;
696                 }
697         }
698 
699         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
700         if (IS_ERR(dwc->usb2_generic_phy)) {
701                 ret = PTR_ERR(dwc->usb2_generic_phy);
702                 if (ret == -ENOSYS || ret == -ENODEV) {
703                         dwc->usb2_generic_phy = NULL;
704                 } else if (ret == -EPROBE_DEFER) {
705                         return ret;
706                 } else {
707                         dev_err(dev, "no usb2 phy configured\n");
708                         return ret;
709                 }
710         }
711 
712         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
713         if (IS_ERR(dwc->usb3_generic_phy)) {
714                 ret = PTR_ERR(dwc->usb3_generic_phy);
715                 if (ret == -ENOSYS || ret == -ENODEV) {
716                         dwc->usb3_generic_phy = NULL;
717                 } else if (ret == -EPROBE_DEFER) {
718                         return ret;
719                 } else {
720                         dev_err(dev, "no usb3 phy configured\n");
721                         return ret;
722                 }
723         }
724 
725         return 0;
726 }
727 
728 static int dwc3_core_init_mode(struct dwc3 *dwc)
729 {
730         struct device *dev = dwc->dev;
731         int ret;
732 
733         switch (dwc->dr_mode) {
734         case USB_DR_MODE_PERIPHERAL:
735                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
736                 ret = dwc3_gadget_init(dwc);
737                 if (ret) {
738                         dev_err(dev, "failed to initialize gadget\n");
739                         return ret;
740                 }
741                 break;
742         case USB_DR_MODE_HOST:
743                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
744                 ret = dwc3_host_init(dwc);
745                 if (ret) {
746                         dev_err(dev, "failed to initialize host\n");
747                         return ret;
748                 }
749                 break;
750         case USB_DR_MODE_OTG:
751                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
752                 ret = dwc3_host_init(dwc);
753                 if (ret) {
754                         dev_err(dev, "failed to initialize host\n");
755                         return ret;
756                 }
757 
758                 ret = dwc3_gadget_init(dwc);
759                 if (ret) {
760                         dev_err(dev, "failed to initialize gadget\n");
761                         return ret;
762                 }
763                 break;
764         default:
765                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
766                 return -EINVAL;
767         }
768 
769         return 0;
770 }
771 
772 static void dwc3_core_exit_mode(struct dwc3 *dwc)
773 {
774         switch (dwc->dr_mode) {
775         case USB_DR_MODE_PERIPHERAL:
776                 dwc3_gadget_exit(dwc);
777                 break;
778         case USB_DR_MODE_HOST:
779                 dwc3_host_exit(dwc);
780                 break;
781         case USB_DR_MODE_OTG:
782                 dwc3_host_exit(dwc);
783                 dwc3_gadget_exit(dwc);
784                 break;
785         default:
786                 /* do nothing */
787                 break;
788         }
789 }
790 
791 #define DWC3_ALIGN_MASK         (16 - 1)
792 
793 static int dwc3_probe(struct platform_device *pdev)
794 {
795         struct device           *dev = &pdev->dev;
796         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
797         struct resource         *res;
798         struct dwc3             *dwc;
799         u8                      lpm_nyet_threshold;
800         u8                      tx_de_emphasis;
801         u8                      hird_threshold;
802         u32                     fladj = 0;
803 
804         int                     ret;
805 
806         void __iomem            *regs;
807         void                    *mem;
808 
809         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
810         if (!mem)
811                 return -ENOMEM;
812 
813         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
814         dwc->mem = mem;
815         dwc->dev = dev;
816 
817         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
818         if (!res) {
819                 dev_err(dev, "missing IRQ\n");
820                 return -ENODEV;
821         }
822         dwc->xhci_resources[1].start = res->start;
823         dwc->xhci_resources[1].end = res->end;
824         dwc->xhci_resources[1].flags = res->flags;
825         dwc->xhci_resources[1].name = res->name;
826 
827         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
828         if (!res) {
829                 dev_err(dev, "missing memory resource\n");
830                 return -ENODEV;
831         }
832 
833         dwc->xhci_resources[0].start = res->start;
834         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
835                                         DWC3_XHCI_REGS_END;
836         dwc->xhci_resources[0].flags = res->flags;
837         dwc->xhci_resources[0].name = res->name;
838 
839         res->start += DWC3_GLOBALS_REGS_START;
840 
841         /*
842          * Request memory region but exclude xHCI regs,
843          * since it will be requested by the xhci-plat driver.
844          */
845         regs = devm_ioremap_resource(dev, res);
846         if (IS_ERR(regs)) {
847                 ret = PTR_ERR(regs);
848                 goto err0;
849         }
850 
851         dwc->regs       = regs;
852         dwc->regs_size  = resource_size(res);
853 
854         /* default to highest possible threshold */
855         lpm_nyet_threshold = 0xff;
856 
857         /* default to -3.5dB de-emphasis */
858         tx_de_emphasis = 1;
859 
860         /*
861          * default to assert utmi_sleep_n and use maximum allowed HIRD
862          * threshold value of 0b1100
863          */
864         hird_threshold = 12;
865 
866         dwc->maximum_speed = usb_get_maximum_speed(dev);
867         dwc->dr_mode = usb_get_dr_mode(dev);
868 
869         dwc->has_lpm_erratum = device_property_read_bool(dev,
870                                 "snps,has-lpm-erratum");
871         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
872                                 &lpm_nyet_threshold);
873         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
874                                 "snps,is-utmi-l1-suspend");
875         device_property_read_u8(dev, "snps,hird-threshold",
876                                 &hird_threshold);
877         dwc->usb3_lpm_capable = device_property_read_bool(dev,
878                                 "snps,usb3_lpm_capable");
879 
880         dwc->disable_scramble_quirk = device_property_read_bool(dev,
881                                 "snps,disable_scramble_quirk");
882         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
883                                 "snps,u2exit_lfps_quirk");
884         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
885                                 "snps,u2ss_inp3_quirk");
886         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
887                                 "snps,req_p1p2p3_quirk");
888         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
889                                 "snps,del_p1p2p3_quirk");
890         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
891                                 "snps,del_phy_power_chg_quirk");
892         dwc->lfps_filter_quirk = device_property_read_bool(dev,
893                                 "snps,lfps_filter_quirk");
894         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
895                                 "snps,rx_detect_poll_quirk");
896         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
897                                 "snps,dis_u3_susphy_quirk");
898         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
899                                 "snps,dis_u2_susphy_quirk");
900         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
901                                 "snps,dis_enblslpm_quirk");
902         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
903                                 "snps,dis_rxdet_inp3_quirk");
904 
905         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
906                                 "snps,tx_de_emphasis_quirk");
907         device_property_read_u8(dev, "snps,tx_de_emphasis",
908                                 &tx_de_emphasis);
909         device_property_read_string(dev, "snps,hsphy_interface",
910                                     &dwc->hsphy_interface);
911         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
912                                  &fladj);
913 
914         if (pdata) {
915                 dwc->maximum_speed = pdata->maximum_speed;
916                 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
917                 if (pdata->lpm_nyet_threshold)
918                         lpm_nyet_threshold = pdata->lpm_nyet_threshold;
919                 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
920                 if (pdata->hird_threshold)
921                         hird_threshold = pdata->hird_threshold;
922 
923                 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
924                 dwc->dr_mode = pdata->dr_mode;
925 
926                 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
927                 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
928                 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
929                 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
930                 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
931                 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
932                 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
933                 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
934                 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
935                 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
936                 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
937                 dwc->dis_rxdet_inp3_quirk = pdata->dis_rxdet_inp3_quirk;
938 
939                 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
940                 if (pdata->tx_de_emphasis)
941                         tx_de_emphasis = pdata->tx_de_emphasis;
942 
943                 dwc->hsphy_interface = pdata->hsphy_interface;
944                 fladj = pdata->fladj_value;
945         }
946 
947         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
948         dwc->tx_de_emphasis = tx_de_emphasis;
949 
950         dwc->hird_threshold = hird_threshold
951                 | (dwc->is_utmi_l1_suspend << 4);
952 
953         platform_set_drvdata(pdev, dwc);
954         dwc3_cache_hwparams(dwc);
955 
956         ret = dwc3_phy_setup(dwc);
957         if (ret)
958                 goto err0;
959 
960         ret = dwc3_core_get_phy(dwc);
961         if (ret)
962                 goto err0;
963 
964         spin_lock_init(&dwc->lock);
965 
966         if (!dev->dma_mask) {
967                 dev->dma_mask = dev->parent->dma_mask;
968                 dev->dma_parms = dev->parent->dma_parms;
969                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
970         }
971 
972         pm_runtime_enable(dev);
973         pm_runtime_get_sync(dev);
974         pm_runtime_forbid(dev);
975 
976         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
977         if (ret) {
978                 dev_err(dwc->dev, "failed to allocate event buffers\n");
979                 ret = -ENOMEM;
980                 goto err1;
981         }
982 
983         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
984                 dwc->dr_mode = USB_DR_MODE_HOST;
985         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
986                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
987 
988         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
989                 dwc->dr_mode = USB_DR_MODE_OTG;
990 
991         ret = dwc3_core_init(dwc);
992         if (ret) {
993                 dev_err(dev, "failed to initialize core\n");
994                 goto err1;
995         }
996 
997         /* Check the maximum_speed parameter */
998         switch (dwc->maximum_speed) {
999         case USB_SPEED_LOW:
1000         case USB_SPEED_FULL:
1001         case USB_SPEED_HIGH:
1002         case USB_SPEED_SUPER:
1003         case USB_SPEED_SUPER_PLUS:
1004                 break;
1005         default:
1006                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1007                         dwc->maximum_speed);
1008                 /* fall through */
1009         case USB_SPEED_UNKNOWN:
1010                 /* default to superspeed */
1011                 dwc->maximum_speed = USB_SPEED_SUPER;
1012 
1013                 /*
1014                  * default to superspeed plus if we are capable.
1015                  */
1016                 if (dwc3_is_usb31(dwc) &&
1017                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1018                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1019                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1020 
1021                 break;
1022         }
1023 
1024         /* Adjust Frame Length */
1025         dwc3_frame_length_adjustment(dwc, fladj);
1026 
1027         usb_phy_set_suspend(dwc->usb2_phy, 0);
1028         usb_phy_set_suspend(dwc->usb3_phy, 0);
1029         ret = phy_power_on(dwc->usb2_generic_phy);
1030         if (ret < 0)
1031                 goto err2;
1032 
1033         ret = phy_power_on(dwc->usb3_generic_phy);
1034         if (ret < 0)
1035                 goto err3;
1036 
1037         ret = dwc3_event_buffers_setup(dwc);
1038         if (ret) {
1039                 dev_err(dwc->dev, "failed to setup event buffers\n");
1040                 goto err4;
1041         }
1042 
1043         ret = dwc3_core_init_mode(dwc);
1044         if (ret)
1045                 goto err5;
1046 
1047         dwc3_debugfs_init(dwc);
1048         pm_runtime_allow(dev);
1049 
1050         return 0;
1051 
1052 err5:
1053         dwc3_event_buffers_cleanup(dwc);
1054 
1055 err4:
1056         phy_power_off(dwc->usb3_generic_phy);
1057 
1058 err3:
1059         phy_power_off(dwc->usb2_generic_phy);
1060 
1061 err2:
1062         usb_phy_set_suspend(dwc->usb2_phy, 1);
1063         usb_phy_set_suspend(dwc->usb3_phy, 1);
1064         dwc3_core_exit(dwc);
1065 
1066 err1:
1067         dwc3_free_event_buffers(dwc);
1068         dwc3_ulpi_exit(dwc);
1069 
1070 err0:
1071         /*
1072          * restore res->start back to its original value so that, in case the
1073          * probe is deferred, we don't end up getting error in request the
1074          * memory region the next time probe is called.
1075          */
1076         res->start -= DWC3_GLOBALS_REGS_START;
1077 
1078         return ret;
1079 }
1080 
1081 static int dwc3_remove(struct platform_device *pdev)
1082 {
1083         struct dwc3     *dwc = platform_get_drvdata(pdev);
1084         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1085 
1086         /*
1087          * restore res->start back to its original value so that, in case the
1088          * probe is deferred, we don't end up getting error in request the
1089          * memory region the next time probe is called.
1090          */
1091         res->start -= DWC3_GLOBALS_REGS_START;
1092 
1093         dwc3_debugfs_exit(dwc);
1094         dwc3_core_exit_mode(dwc);
1095         dwc3_event_buffers_cleanup(dwc);
1096         dwc3_free_event_buffers(dwc);
1097 
1098         usb_phy_set_suspend(dwc->usb2_phy, 1);
1099         usb_phy_set_suspend(dwc->usb3_phy, 1);
1100         phy_power_off(dwc->usb2_generic_phy);
1101         phy_power_off(dwc->usb3_generic_phy);
1102 
1103         dwc3_core_exit(dwc);
1104         dwc3_ulpi_exit(dwc);
1105 
1106         pm_runtime_put_sync(&pdev->dev);
1107         pm_runtime_disable(&pdev->dev);
1108 
1109         return 0;
1110 }
1111 
1112 #ifdef CONFIG_PM_SLEEP
1113 static int dwc3_suspend(struct device *dev)
1114 {
1115         struct dwc3     *dwc = dev_get_drvdata(dev);
1116         unsigned long   flags;
1117 
1118         spin_lock_irqsave(&dwc->lock, flags);
1119 
1120         switch (dwc->dr_mode) {
1121         case USB_DR_MODE_PERIPHERAL:
1122         case USB_DR_MODE_OTG:
1123                 dwc3_gadget_suspend(dwc);
1124                 /* FALLTHROUGH */
1125         case USB_DR_MODE_HOST:
1126         default:
1127                 dwc3_event_buffers_cleanup(dwc);
1128                 break;
1129         }
1130 
1131         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1132         spin_unlock_irqrestore(&dwc->lock, flags);
1133 
1134         usb_phy_shutdown(dwc->usb3_phy);
1135         usb_phy_shutdown(dwc->usb2_phy);
1136         phy_exit(dwc->usb2_generic_phy);
1137         phy_exit(dwc->usb3_generic_phy);
1138 
1139         usb_phy_set_suspend(dwc->usb2_phy, 1);
1140         usb_phy_set_suspend(dwc->usb3_phy, 1);
1141         WARN_ON(phy_power_off(dwc->usb2_generic_phy) < 0);
1142         WARN_ON(phy_power_off(dwc->usb3_generic_phy) < 0);
1143 
1144         pinctrl_pm_select_sleep_state(dev);
1145 
1146         return 0;
1147 }
1148 
1149 static int dwc3_resume(struct device *dev)
1150 {
1151         struct dwc3     *dwc = dev_get_drvdata(dev);
1152         unsigned long   flags;
1153         int             ret;
1154 
1155         pinctrl_pm_select_default_state(dev);
1156 
1157         usb_phy_set_suspend(dwc->usb2_phy, 0);
1158         usb_phy_set_suspend(dwc->usb3_phy, 0);
1159         ret = phy_power_on(dwc->usb2_generic_phy);
1160         if (ret < 0)
1161                 return ret;
1162 
1163         ret = phy_power_on(dwc->usb3_generic_phy);
1164         if (ret < 0)
1165                 goto err_usb2phy_power;
1166 
1167         usb_phy_init(dwc->usb3_phy);
1168         usb_phy_init(dwc->usb2_phy);
1169         ret = phy_init(dwc->usb2_generic_phy);
1170         if (ret < 0)
1171                 goto err_usb3phy_power;
1172 
1173         ret = phy_init(dwc->usb3_generic_phy);
1174         if (ret < 0)
1175                 goto err_usb2phy_init;
1176 
1177         spin_lock_irqsave(&dwc->lock, flags);
1178 
1179         dwc3_event_buffers_setup(dwc);
1180         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1181 
1182         switch (dwc->dr_mode) {
1183         case USB_DR_MODE_PERIPHERAL:
1184         case USB_DR_MODE_OTG:
1185                 dwc3_gadget_resume(dwc);
1186                 /* FALLTHROUGH */
1187         case USB_DR_MODE_HOST:
1188         default:
1189                 /* do nothing */
1190                 break;
1191         }
1192 
1193         spin_unlock_irqrestore(&dwc->lock, flags);
1194 
1195         pm_runtime_disable(dev);
1196         pm_runtime_set_active(dev);
1197         pm_runtime_enable(dev);
1198 
1199         return 0;
1200 
1201 err_usb2phy_init:
1202         phy_exit(dwc->usb2_generic_phy);
1203 
1204 err_usb3phy_power:
1205         phy_power_off(dwc->usb3_generic_phy);
1206 
1207 err_usb2phy_power:
1208         phy_power_off(dwc->usb2_generic_phy);
1209 
1210         return ret;
1211 }
1212 
1213 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1214         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1215 };
1216 
1217 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
1218 #else
1219 #define DWC3_PM_OPS     NULL
1220 #endif
1221 
1222 #ifdef CONFIG_OF
1223 static const struct of_device_id of_dwc3_match[] = {
1224         {
1225                 .compatible = "snps,dwc3"
1226         },
1227         {
1228                 .compatible = "synopsys,dwc3"
1229         },
1230         { },
1231 };
1232 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1233 #endif
1234 
1235 #ifdef CONFIG_ACPI
1236 
1237 #define ACPI_ID_INTEL_BSW       "808622B7"
1238 
1239 static const struct acpi_device_id dwc3_acpi_match[] = {
1240         { ACPI_ID_INTEL_BSW, 0 },
1241         { },
1242 };
1243 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1244 #endif
1245 
1246 static struct platform_driver dwc3_driver = {
1247         .probe          = dwc3_probe,
1248         .remove         = dwc3_remove,
1249         .driver         = {
1250                 .name   = "dwc3",
1251                 .of_match_table = of_match_ptr(of_dwc3_match),
1252                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1253                 .pm     = DWC3_PM_OPS,
1254         },
1255 };
1256 
1257 module_platform_driver(dwc3_driver);
1258 
1259 MODULE_ALIAS("platform:dwc3");
1260 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1261 MODULE_LICENSE("GPL v2");
1262 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
1263 

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