Version:  2.0.40 2.2.26 2.4.37 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Linux/drivers/usb/dwc3/core.c

  1 /**
  2  * core.c - DesignWare USB3 DRD Controller Core file
  3  *
  4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5  *
  6  * Authors: Felipe Balbi <balbi@ti.com>,
  7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8  *
  9  * This program is free software: you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2  of
 11  * the License as published by the Free Software Foundation.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 20  */
 21 
 22 #include <linux/version.h>
 23 #include <linux/module.h>
 24 #include <linux/kernel.h>
 25 #include <linux/slab.h>
 26 #include <linux/spinlock.h>
 27 #include <linux/platform_device.h>
 28 #include <linux/pm_runtime.h>
 29 #include <linux/interrupt.h>
 30 #include <linux/ioport.h>
 31 #include <linux/io.h>
 32 #include <linux/list.h>
 33 #include <linux/delay.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/of.h>
 36 #include <linux/acpi.h>
 37 
 38 #include <linux/usb/ch9.h>
 39 #include <linux/usb/gadget.h>
 40 #include <linux/usb/of.h>
 41 #include <linux/usb/otg.h>
 42 
 43 #include "platform_data.h"
 44 #include "core.h"
 45 #include "gadget.h"
 46 #include "io.h"
 47 
 48 #include "debug.h"
 49 
 50 /* -------------------------------------------------------------------------- */
 51 
 52 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 53 {
 54         u32 reg;
 55 
 56         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 57         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 58         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 59         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 60 }
 61 
 62 /**
 63  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 64  * @dwc: pointer to our context structure
 65  */
 66 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 67 {
 68         u32             reg;
 69         int             ret;
 70 
 71         /* Before Resetting PHY, put Core in Reset */
 72         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 73         reg |= DWC3_GCTL_CORESOFTRESET;
 74         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 75 
 76         /* Assert USB3 PHY reset */
 77         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 78         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
 79         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 80 
 81         /* Assert USB2 PHY reset */
 82         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 83         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
 84         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 85 
 86         usb_phy_init(dwc->usb2_phy);
 87         usb_phy_init(dwc->usb3_phy);
 88         ret = phy_init(dwc->usb2_generic_phy);
 89         if (ret < 0)
 90                 return ret;
 91 
 92         ret = phy_init(dwc->usb3_generic_phy);
 93         if (ret < 0) {
 94                 phy_exit(dwc->usb2_generic_phy);
 95                 return ret;
 96         }
 97         mdelay(100);
 98 
 99         /* Clear USB3 PHY reset */
100         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
101         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
102         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
103 
104         /* Clear USB2 PHY reset */
105         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
106         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
107         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
108 
109         mdelay(100);
110 
111         /* After PHYs are stable we can take Core out of reset state */
112         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
113         reg &= ~DWC3_GCTL_CORESOFTRESET;
114         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
115 
116         return 0;
117 }
118 
119 /**
120  * dwc3_free_one_event_buffer - Frees one event buffer
121  * @dwc: Pointer to our controller context structure
122  * @evt: Pointer to event buffer to be freed
123  */
124 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
125                 struct dwc3_event_buffer *evt)
126 {
127         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
128 }
129 
130 /**
131  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
132  * @dwc: Pointer to our controller context structure
133  * @length: size of the event buffer
134  *
135  * Returns a pointer to the allocated event buffer structure on success
136  * otherwise ERR_PTR(errno).
137  */
138 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
139                 unsigned length)
140 {
141         struct dwc3_event_buffer        *evt;
142 
143         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
144         if (!evt)
145                 return ERR_PTR(-ENOMEM);
146 
147         evt->dwc        = dwc;
148         evt->length     = length;
149         evt->buf        = dma_alloc_coherent(dwc->dev, length,
150                         &evt->dma, GFP_KERNEL);
151         if (!evt->buf)
152                 return ERR_PTR(-ENOMEM);
153 
154         return evt;
155 }
156 
157 /**
158  * dwc3_free_event_buffers - frees all allocated event buffers
159  * @dwc: Pointer to our controller context structure
160  */
161 static void dwc3_free_event_buffers(struct dwc3 *dwc)
162 {
163         struct dwc3_event_buffer        *evt;
164         int i;
165 
166         for (i = 0; i < dwc->num_event_buffers; i++) {
167                 evt = dwc->ev_buffs[i];
168                 if (evt)
169                         dwc3_free_one_event_buffer(dwc, evt);
170         }
171 }
172 
173 /**
174  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
175  * @dwc: pointer to our controller context structure
176  * @length: size of event buffer
177  *
178  * Returns 0 on success otherwise negative errno. In the error case, dwc
179  * may contain some buffers allocated but not all which were requested.
180  */
181 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
182 {
183         int                     num;
184         int                     i;
185 
186         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
187         dwc->num_event_buffers = num;
188 
189         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
190                         GFP_KERNEL);
191         if (!dwc->ev_buffs)
192                 return -ENOMEM;
193 
194         for (i = 0; i < num; i++) {
195                 struct dwc3_event_buffer        *evt;
196 
197                 evt = dwc3_alloc_one_event_buffer(dwc, length);
198                 if (IS_ERR(evt)) {
199                         dev_err(dwc->dev, "can't allocate event buffer\n");
200                         return PTR_ERR(evt);
201                 }
202                 dwc->ev_buffs[i] = evt;
203         }
204 
205         return 0;
206 }
207 
208 /**
209  * dwc3_event_buffers_setup - setup our allocated event buffers
210  * @dwc: pointer to our controller context structure
211  *
212  * Returns 0 on success otherwise negative errno.
213  */
214 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
215 {
216         struct dwc3_event_buffer        *evt;
217         int                             n;
218 
219         for (n = 0; n < dwc->num_event_buffers; n++) {
220                 evt = dwc->ev_buffs[n];
221                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
222                                 evt->buf, (unsigned long long) evt->dma,
223                                 evt->length);
224 
225                 evt->lpos = 0;
226 
227                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
228                                 lower_32_bits(evt->dma));
229                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
230                                 upper_32_bits(evt->dma));
231                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
232                                 DWC3_GEVNTSIZ_SIZE(evt->length));
233                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
234         }
235 
236         return 0;
237 }
238 
239 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
240 {
241         struct dwc3_event_buffer        *evt;
242         int                             n;
243 
244         for (n = 0; n < dwc->num_event_buffers; n++) {
245                 evt = dwc->ev_buffs[n];
246 
247                 evt->lpos = 0;
248 
249                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
250                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
251                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
252                                 | DWC3_GEVNTSIZ_SIZE(0));
253                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
254         }
255 }
256 
257 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
258 {
259         if (!dwc->has_hibernation)
260                 return 0;
261 
262         if (!dwc->nr_scratch)
263                 return 0;
264 
265         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
266                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
267         if (!dwc->scratchbuf)
268                 return -ENOMEM;
269 
270         return 0;
271 }
272 
273 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
274 {
275         dma_addr_t scratch_addr;
276         u32 param;
277         int ret;
278 
279         if (!dwc->has_hibernation)
280                 return 0;
281 
282         if (!dwc->nr_scratch)
283                 return 0;
284 
285          /* should never fall here */
286         if (!WARN_ON(dwc->scratchbuf))
287                 return 0;
288 
289         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
290                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
291                         DMA_BIDIRECTIONAL);
292         if (dma_mapping_error(dwc->dev, scratch_addr)) {
293                 dev_err(dwc->dev, "failed to map scratch buffer\n");
294                 ret = -EFAULT;
295                 goto err0;
296         }
297 
298         dwc->scratch_addr = scratch_addr;
299 
300         param = lower_32_bits(scratch_addr);
301 
302         ret = dwc3_send_gadget_generic_command(dwc,
303                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
304         if (ret < 0)
305                 goto err1;
306 
307         param = upper_32_bits(scratch_addr);
308 
309         ret = dwc3_send_gadget_generic_command(dwc,
310                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
311         if (ret < 0)
312                 goto err1;
313 
314         return 0;
315 
316 err1:
317         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
318                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
319 
320 err0:
321         return ret;
322 }
323 
324 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
325 {
326         if (!dwc->has_hibernation)
327                 return;
328 
329         if (!dwc->nr_scratch)
330                 return;
331 
332          /* should never fall here */
333         if (!WARN_ON(dwc->scratchbuf))
334                 return;
335 
336         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
337                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
338         kfree(dwc->scratchbuf);
339 }
340 
341 static void dwc3_core_num_eps(struct dwc3 *dwc)
342 {
343         struct dwc3_hwparams    *parms = &dwc->hwparams;
344 
345         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
346         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
347 
348         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
349                         dwc->num_in_eps, dwc->num_out_eps);
350 }
351 
352 static void dwc3_cache_hwparams(struct dwc3 *dwc)
353 {
354         struct dwc3_hwparams    *parms = &dwc->hwparams;
355 
356         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
357         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
358         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
359         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
360         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
361         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
362         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
363         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
364         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
365 }
366 
367 /**
368  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
369  * @dwc: Pointer to our controller context structure
370  */
371 static void dwc3_phy_setup(struct dwc3 *dwc)
372 {
373         u32 reg;
374 
375         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
376 
377         /*
378          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
379          * to '' during coreConsultant configuration. So default value
380          * will be '' when the core is reset. Application needs to set it
381          * to '1' after the core initialization is completed.
382          */
383         if (dwc->revision > DWC3_REVISION_194A)
384                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
385 
386         if (dwc->u2ss_inp3_quirk)
387                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
388 
389         if (dwc->req_p1p2p3_quirk)
390                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
391 
392         if (dwc->del_p1p2p3_quirk)
393                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
394 
395         if (dwc->del_phy_power_chg_quirk)
396                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
397 
398         if (dwc->lfps_filter_quirk)
399                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
400 
401         if (dwc->rx_detect_poll_quirk)
402                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
403 
404         if (dwc->tx_de_emphasis_quirk)
405                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
406 
407         if (dwc->dis_u3_susphy_quirk)
408                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
409 
410         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
411 
412         mdelay(100);
413 
414         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
415 
416         /*
417          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
418          * '' during coreConsultant configuration. So default value will
419          * be '' when the core is reset. Application needs to set it to
420          * '1' after the core initialization is completed.
421          */
422         if (dwc->revision > DWC3_REVISION_194A)
423                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
424 
425         if (dwc->dis_u2_susphy_quirk)
426                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
427 
428         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
429 
430         mdelay(100);
431 }
432 
433 /**
434  * dwc3_core_init - Low-level initialization of DWC3 Core
435  * @dwc: Pointer to our controller context structure
436  *
437  * Returns 0 on success otherwise negative errno.
438  */
439 static int dwc3_core_init(struct dwc3 *dwc)
440 {
441         unsigned long           timeout;
442         u32                     hwparams4 = dwc->hwparams.hwparams4;
443         u32                     reg;
444         int                     ret;
445 
446         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
447         /* This should read as U3 followed by revision number */
448         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
449                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
450                 ret = -ENODEV;
451                 goto err0;
452         }
453         dwc->revision = reg;
454 
455         /*
456          * Write Linux Version Code to our GUID register so it's easy to figure
457          * out which kernel version a bug was found.
458          */
459         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
460 
461         /* Handle USB2.0-only core configuration */
462         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
463                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
464                 if (dwc->maximum_speed == USB_SPEED_SUPER)
465                         dwc->maximum_speed = USB_SPEED_HIGH;
466         }
467 
468         /* issue device SoftReset too */
469         timeout = jiffies + msecs_to_jiffies(500);
470         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
471         do {
472                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
473                 if (!(reg & DWC3_DCTL_CSFTRST))
474                         break;
475 
476                 if (time_after(jiffies, timeout)) {
477                         dev_err(dwc->dev, "Reset Timed Out\n");
478                         ret = -ETIMEDOUT;
479                         goto err0;
480                 }
481 
482                 cpu_relax();
483         } while (true);
484 
485         ret = dwc3_core_soft_reset(dwc);
486         if (ret)
487                 goto err0;
488 
489         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
490         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
491 
492         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
493         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
494                 /**
495                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
496                  * issue which would cause xHCI compliance tests to fail.
497                  *
498                  * Because of that we cannot enable clock gating on such
499                  * configurations.
500                  *
501                  * Refers to:
502                  *
503                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
504                  * SOF/ITP Mode Used
505                  */
506                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
507                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
508                                 (dwc->revision >= DWC3_REVISION_210A &&
509                                 dwc->revision <= DWC3_REVISION_250A))
510                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
511                 else
512                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
513                 break;
514         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
515                 /* enable hibernation here */
516                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
517 
518                 /*
519                  * REVISIT Enabling this bit so that host-mode hibernation
520                  * will work. Device-mode hibernation is not yet implemented.
521                  */
522                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
523                 break;
524         default:
525                 dev_dbg(dwc->dev, "No power optimization available\n");
526         }
527 
528         /* check if current dwc3 is on simulation board */
529         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
530                 dev_dbg(dwc->dev, "it is on FPGA board\n");
531                 dwc->is_fpga = true;
532         }
533 
534         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
535                         "disable_scramble cannot be used on non-FPGA builds\n");
536 
537         if (dwc->disable_scramble_quirk && dwc->is_fpga)
538                 reg |= DWC3_GCTL_DISSCRAMBLE;
539         else
540                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
541 
542         if (dwc->u2exit_lfps_quirk)
543                 reg |= DWC3_GCTL_U2EXIT_LFPS;
544 
545         /*
546          * WORKAROUND: DWC3 revisions <1.90a have a bug
547          * where the device can fail to connect at SuperSpeed
548          * and falls back to high-speed mode which causes
549          * the device to enter a Connect/Disconnect loop
550          */
551         if (dwc->revision < DWC3_REVISION_190A)
552                 reg |= DWC3_GCTL_U2RSTECN;
553 
554         dwc3_core_num_eps(dwc);
555 
556         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
557 
558         dwc3_phy_setup(dwc);
559 
560         ret = dwc3_alloc_scratch_buffers(dwc);
561         if (ret)
562                 goto err1;
563 
564         ret = dwc3_setup_scratch_buffers(dwc);
565         if (ret)
566                 goto err2;
567 
568         return 0;
569 
570 err2:
571         dwc3_free_scratch_buffers(dwc);
572 
573 err1:
574         usb_phy_shutdown(dwc->usb2_phy);
575         usb_phy_shutdown(dwc->usb3_phy);
576         phy_exit(dwc->usb2_generic_phy);
577         phy_exit(dwc->usb3_generic_phy);
578 
579 err0:
580         return ret;
581 }
582 
583 static void dwc3_core_exit(struct dwc3 *dwc)
584 {
585         dwc3_free_scratch_buffers(dwc);
586         usb_phy_shutdown(dwc->usb2_phy);
587         usb_phy_shutdown(dwc->usb3_phy);
588         phy_exit(dwc->usb2_generic_phy);
589         phy_exit(dwc->usb3_generic_phy);
590 }
591 
592 static int dwc3_core_get_phy(struct dwc3 *dwc)
593 {
594         struct device           *dev = dwc->dev;
595         struct device_node      *node = dev->of_node;
596         int ret;
597 
598         if (node) {
599                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
600                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
601         } else {
602                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
603                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
604         }
605 
606         if (IS_ERR(dwc->usb2_phy)) {
607                 ret = PTR_ERR(dwc->usb2_phy);
608                 if (ret == -ENXIO || ret == -ENODEV) {
609                         dwc->usb2_phy = NULL;
610                 } else if (ret == -EPROBE_DEFER) {
611                         return ret;
612                 } else {
613                         dev_err(dev, "no usb2 phy configured\n");
614                         return ret;
615                 }
616         }
617 
618         if (IS_ERR(dwc->usb3_phy)) {
619                 ret = PTR_ERR(dwc->usb3_phy);
620                 if (ret == -ENXIO || ret == -ENODEV) {
621                         dwc->usb3_phy = NULL;
622                 } else if (ret == -EPROBE_DEFER) {
623                         return ret;
624                 } else {
625                         dev_err(dev, "no usb3 phy configured\n");
626                         return ret;
627                 }
628         }
629 
630         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
631         if (IS_ERR(dwc->usb2_generic_phy)) {
632                 ret = PTR_ERR(dwc->usb2_generic_phy);
633                 if (ret == -ENOSYS || ret == -ENODEV) {
634                         dwc->usb2_generic_phy = NULL;
635                 } else if (ret == -EPROBE_DEFER) {
636                         return ret;
637                 } else {
638                         dev_err(dev, "no usb2 phy configured\n");
639                         return ret;
640                 }
641         }
642 
643         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
644         if (IS_ERR(dwc->usb3_generic_phy)) {
645                 ret = PTR_ERR(dwc->usb3_generic_phy);
646                 if (ret == -ENOSYS || ret == -ENODEV) {
647                         dwc->usb3_generic_phy = NULL;
648                 } else if (ret == -EPROBE_DEFER) {
649                         return ret;
650                 } else {
651                         dev_err(dev, "no usb3 phy configured\n");
652                         return ret;
653                 }
654         }
655 
656         return 0;
657 }
658 
659 static int dwc3_core_init_mode(struct dwc3 *dwc)
660 {
661         struct device *dev = dwc->dev;
662         int ret;
663 
664         switch (dwc->dr_mode) {
665         case USB_DR_MODE_PERIPHERAL:
666                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
667                 ret = dwc3_gadget_init(dwc);
668                 if (ret) {
669                         dev_err(dev, "failed to initialize gadget\n");
670                         return ret;
671                 }
672                 break;
673         case USB_DR_MODE_HOST:
674                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
675                 ret = dwc3_host_init(dwc);
676                 if (ret) {
677                         dev_err(dev, "failed to initialize host\n");
678                         return ret;
679                 }
680                 break;
681         case USB_DR_MODE_OTG:
682                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
683                 ret = dwc3_host_init(dwc);
684                 if (ret) {
685                         dev_err(dev, "failed to initialize host\n");
686                         return ret;
687                 }
688 
689                 ret = dwc3_gadget_init(dwc);
690                 if (ret) {
691                         dev_err(dev, "failed to initialize gadget\n");
692                         return ret;
693                 }
694                 break;
695         default:
696                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
697                 return -EINVAL;
698         }
699 
700         return 0;
701 }
702 
703 static void dwc3_core_exit_mode(struct dwc3 *dwc)
704 {
705         switch (dwc->dr_mode) {
706         case USB_DR_MODE_PERIPHERAL:
707                 dwc3_gadget_exit(dwc);
708                 break;
709         case USB_DR_MODE_HOST:
710                 dwc3_host_exit(dwc);
711                 break;
712         case USB_DR_MODE_OTG:
713                 dwc3_host_exit(dwc);
714                 dwc3_gadget_exit(dwc);
715                 break;
716         default:
717                 /* do nothing */
718                 break;
719         }
720 }
721 
722 #define DWC3_ALIGN_MASK         (16 - 1)
723 
724 static int dwc3_probe(struct platform_device *pdev)
725 {
726         struct device           *dev = &pdev->dev;
727         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
728         struct device_node      *node = dev->of_node;
729         struct resource         *res;
730         struct dwc3             *dwc;
731         u8                      lpm_nyet_threshold;
732         u8                      tx_de_emphasis;
733         u8                      hird_threshold;
734 
735         int                     ret;
736 
737         void __iomem            *regs;
738         void                    *mem;
739 
740         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
741         if (!mem)
742                 return -ENOMEM;
743 
744         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
745         dwc->mem = mem;
746         dwc->dev = dev;
747 
748         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
749         if (!res) {
750                 dev_err(dev, "missing IRQ\n");
751                 return -ENODEV;
752         }
753         dwc->xhci_resources[1].start = res->start;
754         dwc->xhci_resources[1].end = res->end;
755         dwc->xhci_resources[1].flags = res->flags;
756         dwc->xhci_resources[1].name = res->name;
757 
758         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
759         if (!res) {
760                 dev_err(dev, "missing memory resource\n");
761                 return -ENODEV;
762         }
763 
764         dwc->xhci_resources[0].start = res->start;
765         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
766                                         DWC3_XHCI_REGS_END;
767         dwc->xhci_resources[0].flags = res->flags;
768         dwc->xhci_resources[0].name = res->name;
769 
770         res->start += DWC3_GLOBALS_REGS_START;
771 
772         /*
773          * Request memory region but exclude xHCI regs,
774          * since it will be requested by the xhci-plat driver.
775          */
776         regs = devm_ioremap_resource(dev, res);
777         if (IS_ERR(regs))
778                 return PTR_ERR(regs);
779 
780         dwc->regs       = regs;
781         dwc->regs_size  = resource_size(res);
782         /*
783          * restore res->start back to its original value so that,
784          * in case the probe is deferred, we don't end up getting error in
785          * request the memory region the next time probe is called.
786          */
787         res->start -= DWC3_GLOBALS_REGS_START;
788 
789         /* default to highest possible threshold */
790         lpm_nyet_threshold = 0xff;
791 
792         /* default to -3.5dB de-emphasis */
793         tx_de_emphasis = 1;
794 
795         /*
796          * default to assert utmi_sleep_n and use maximum allowed HIRD
797          * threshold value of 0b1100
798          */
799         hird_threshold = 12;
800 
801         if (node) {
802                 dwc->maximum_speed = of_usb_get_maximum_speed(node);
803                 dwc->has_lpm_erratum = of_property_read_bool(node,
804                                 "snps,has-lpm-erratum");
805                 of_property_read_u8(node, "snps,lpm-nyet-threshold",
806                                 &lpm_nyet_threshold);
807                 dwc->is_utmi_l1_suspend = of_property_read_bool(node,
808                                 "snps,is-utmi-l1-suspend");
809                 of_property_read_u8(node, "snps,hird-threshold",
810                                 &hird_threshold);
811 
812                 dwc->needs_fifo_resize = of_property_read_bool(node,
813                                 "tx-fifo-resize");
814                 dwc->dr_mode = of_usb_get_dr_mode(node);
815 
816                 dwc->disable_scramble_quirk = of_property_read_bool(node,
817                                 "snps,disable_scramble_quirk");
818                 dwc->u2exit_lfps_quirk = of_property_read_bool(node,
819                                 "snps,u2exit_lfps_quirk");
820                 dwc->u2ss_inp3_quirk = of_property_read_bool(node,
821                                 "snps,u2ss_inp3_quirk");
822                 dwc->req_p1p2p3_quirk = of_property_read_bool(node,
823                                 "snps,req_p1p2p3_quirk");
824                 dwc->del_p1p2p3_quirk = of_property_read_bool(node,
825                                 "snps,del_p1p2p3_quirk");
826                 dwc->del_phy_power_chg_quirk = of_property_read_bool(node,
827                                 "snps,del_phy_power_chg_quirk");
828                 dwc->lfps_filter_quirk = of_property_read_bool(node,
829                                 "snps,lfps_filter_quirk");
830                 dwc->rx_detect_poll_quirk = of_property_read_bool(node,
831                                 "snps,rx_detect_poll_quirk");
832                 dwc->dis_u3_susphy_quirk = of_property_read_bool(node,
833                                 "snps,dis_u3_susphy_quirk");
834                 dwc->dis_u2_susphy_quirk = of_property_read_bool(node,
835                                 "snps,dis_u2_susphy_quirk");
836 
837                 dwc->tx_de_emphasis_quirk = of_property_read_bool(node,
838                                 "snps,tx_de_emphasis_quirk");
839                 of_property_read_u8(node, "snps,tx_de_emphasis",
840                                 &tx_de_emphasis);
841         } else if (pdata) {
842                 dwc->maximum_speed = pdata->maximum_speed;
843                 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
844                 if (pdata->lpm_nyet_threshold)
845                         lpm_nyet_threshold = pdata->lpm_nyet_threshold;
846                 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
847                 if (pdata->hird_threshold)
848                         hird_threshold = pdata->hird_threshold;
849 
850                 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
851                 dwc->dr_mode = pdata->dr_mode;
852 
853                 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
854                 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
855                 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
856                 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
857                 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
858                 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
859                 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
860                 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
861                 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
862                 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
863 
864                 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
865                 if (pdata->tx_de_emphasis)
866                         tx_de_emphasis = pdata->tx_de_emphasis;
867         }
868 
869         /* default to superspeed if no maximum_speed passed */
870         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
871                 dwc->maximum_speed = USB_SPEED_SUPER;
872 
873         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
874         dwc->tx_de_emphasis = tx_de_emphasis;
875 
876         dwc->hird_threshold = hird_threshold
877                 | (dwc->is_utmi_l1_suspend << 4);
878 
879         ret = dwc3_core_get_phy(dwc);
880         if (ret)
881                 return ret;
882 
883         spin_lock_init(&dwc->lock);
884         platform_set_drvdata(pdev, dwc);
885 
886         if (!dev->dma_mask) {
887                 dev->dma_mask = dev->parent->dma_mask;
888                 dev->dma_parms = dev->parent->dma_parms;
889                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
890         }
891 
892         pm_runtime_enable(dev);
893         pm_runtime_get_sync(dev);
894         pm_runtime_forbid(dev);
895 
896         dwc3_cache_hwparams(dwc);
897 
898         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
899         if (ret) {
900                 dev_err(dwc->dev, "failed to allocate event buffers\n");
901                 ret = -ENOMEM;
902                 goto err0;
903         }
904 
905         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
906                 dwc->dr_mode = USB_DR_MODE_HOST;
907         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
908                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
909 
910         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
911                 dwc->dr_mode = USB_DR_MODE_OTG;
912 
913         ret = dwc3_core_init(dwc);
914         if (ret) {
915                 dev_err(dev, "failed to initialize core\n");
916                 goto err0;
917         }
918 
919         usb_phy_set_suspend(dwc->usb2_phy, 0);
920         usb_phy_set_suspend(dwc->usb3_phy, 0);
921         ret = phy_power_on(dwc->usb2_generic_phy);
922         if (ret < 0)
923                 goto err1;
924 
925         ret = phy_power_on(dwc->usb3_generic_phy);
926         if (ret < 0)
927                 goto err_usb2phy_power;
928 
929         ret = dwc3_event_buffers_setup(dwc);
930         if (ret) {
931                 dev_err(dwc->dev, "failed to setup event buffers\n");
932                 goto err_usb3phy_power;
933         }
934 
935         ret = dwc3_core_init_mode(dwc);
936         if (ret)
937                 goto err2;
938 
939         ret = dwc3_debugfs_init(dwc);
940         if (ret) {
941                 dev_err(dev, "failed to initialize debugfs\n");
942                 goto err3;
943         }
944 
945         pm_runtime_allow(dev);
946 
947         return 0;
948 
949 err3:
950         dwc3_core_exit_mode(dwc);
951 
952 err2:
953         dwc3_event_buffers_cleanup(dwc);
954 
955 err_usb3phy_power:
956         phy_power_off(dwc->usb3_generic_phy);
957 
958 err_usb2phy_power:
959         phy_power_off(dwc->usb2_generic_phy);
960 
961 err1:
962         usb_phy_set_suspend(dwc->usb2_phy, 1);
963         usb_phy_set_suspend(dwc->usb3_phy, 1);
964         dwc3_core_exit(dwc);
965 
966 err0:
967         dwc3_free_event_buffers(dwc);
968 
969         return ret;
970 }
971 
972 static int dwc3_remove(struct platform_device *pdev)
973 {
974         struct dwc3     *dwc = platform_get_drvdata(pdev);
975 
976         dwc3_debugfs_exit(dwc);
977         dwc3_core_exit_mode(dwc);
978         dwc3_event_buffers_cleanup(dwc);
979         dwc3_free_event_buffers(dwc);
980 
981         usb_phy_set_suspend(dwc->usb2_phy, 1);
982         usb_phy_set_suspend(dwc->usb3_phy, 1);
983         phy_power_off(dwc->usb2_generic_phy);
984         phy_power_off(dwc->usb3_generic_phy);
985 
986         dwc3_core_exit(dwc);
987 
988         pm_runtime_put_sync(&pdev->dev);
989         pm_runtime_disable(&pdev->dev);
990 
991         return 0;
992 }
993 
994 #ifdef CONFIG_PM_SLEEP
995 static int dwc3_suspend(struct device *dev)
996 {
997         struct dwc3     *dwc = dev_get_drvdata(dev);
998         unsigned long   flags;
999 
1000         spin_lock_irqsave(&dwc->lock, flags);
1001 
1002         switch (dwc->dr_mode) {
1003         case USB_DR_MODE_PERIPHERAL:
1004         case USB_DR_MODE_OTG:
1005                 dwc3_gadget_suspend(dwc);
1006                 /* FALLTHROUGH */
1007         case USB_DR_MODE_HOST:
1008         default:
1009                 dwc3_event_buffers_cleanup(dwc);
1010                 break;
1011         }
1012 
1013         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1014         spin_unlock_irqrestore(&dwc->lock, flags);
1015 
1016         usb_phy_shutdown(dwc->usb3_phy);
1017         usb_phy_shutdown(dwc->usb2_phy);
1018         phy_exit(dwc->usb2_generic_phy);
1019         phy_exit(dwc->usb3_generic_phy);
1020 
1021         return 0;
1022 }
1023 
1024 static int dwc3_resume(struct device *dev)
1025 {
1026         struct dwc3     *dwc = dev_get_drvdata(dev);
1027         unsigned long   flags;
1028         int             ret;
1029 
1030         usb_phy_init(dwc->usb3_phy);
1031         usb_phy_init(dwc->usb2_phy);
1032         ret = phy_init(dwc->usb2_generic_phy);
1033         if (ret < 0)
1034                 return ret;
1035 
1036         ret = phy_init(dwc->usb3_generic_phy);
1037         if (ret < 0)
1038                 goto err_usb2phy_init;
1039 
1040         spin_lock_irqsave(&dwc->lock, flags);
1041 
1042         dwc3_event_buffers_setup(dwc);
1043         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1044 
1045         switch (dwc->dr_mode) {
1046         case USB_DR_MODE_PERIPHERAL:
1047         case USB_DR_MODE_OTG:
1048                 dwc3_gadget_resume(dwc);
1049                 /* FALLTHROUGH */
1050         case USB_DR_MODE_HOST:
1051         default:
1052                 /* do nothing */
1053                 break;
1054         }
1055 
1056         spin_unlock_irqrestore(&dwc->lock, flags);
1057 
1058         pm_runtime_disable(dev);
1059         pm_runtime_set_active(dev);
1060         pm_runtime_enable(dev);
1061 
1062         return 0;
1063 
1064 err_usb2phy_init:
1065         phy_exit(dwc->usb2_generic_phy);
1066 
1067         return ret;
1068 }
1069 
1070 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1071         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1072 };
1073 
1074 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
1075 #else
1076 #define DWC3_PM_OPS     NULL
1077 #endif
1078 
1079 #ifdef CONFIG_OF
1080 static const struct of_device_id of_dwc3_match[] = {
1081         {
1082                 .compatible = "snps,dwc3"
1083         },
1084         {
1085                 .compatible = "synopsys,dwc3"
1086         },
1087         { },
1088 };
1089 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1090 #endif
1091 
1092 #ifdef CONFIG_ACPI
1093 
1094 #define ACPI_ID_INTEL_BSW       "808622B7"
1095 
1096 static const struct acpi_device_id dwc3_acpi_match[] = {
1097         { ACPI_ID_INTEL_BSW, 0 },
1098         { },
1099 };
1100 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1101 #endif
1102 
1103 static struct platform_driver dwc3_driver = {
1104         .probe          = dwc3_probe,
1105         .remove         = dwc3_remove,
1106         .driver         = {
1107                 .name   = "dwc3",
1108                 .of_match_table = of_match_ptr(of_dwc3_match),
1109                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1110                 .pm     = DWC3_PM_OPS,
1111         },
1112 };
1113 
1114 module_platform_driver(dwc3_driver);
1115 
1116 MODULE_ALIAS("platform:dwc3");
1117 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1118 MODULE_LICENSE("GPL v2");
1119 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
1120 

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