Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/usb/dwc3/core.c

  1 /**
  2  * core.c - DesignWare USB3 DRD Controller Core file
  3  *
  4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5  *
  6  * Authors: Felipe Balbi <balbi@ti.com>,
  7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8  *
  9  * This program is free software: you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2  of
 11  * the License as published by the Free Software Foundation.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 20  */
 21 
 22 #include <linux/version.h>
 23 #include <linux/module.h>
 24 #include <linux/kernel.h>
 25 #include <linux/slab.h>
 26 #include <linux/spinlock.h>
 27 #include <linux/platform_device.h>
 28 #include <linux/pm_runtime.h>
 29 #include <linux/interrupt.h>
 30 #include <linux/ioport.h>
 31 #include <linux/io.h>
 32 #include <linux/list.h>
 33 #include <linux/delay.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/of.h>
 36 #include <linux/acpi.h>
 37 #include <linux/pinctrl/consumer.h>
 38 
 39 #include <linux/usb/ch9.h>
 40 #include <linux/usb/gadget.h>
 41 #include <linux/usb/of.h>
 42 #include <linux/usb/otg.h>
 43 
 44 #include "platform_data.h"
 45 #include "core.h"
 46 #include "gadget.h"
 47 #include "io.h"
 48 
 49 #include "debug.h"
 50 
 51 /* -------------------------------------------------------------------------- */
 52 
 53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 54 {
 55         u32 reg;
 56 
 57         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 58         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 59         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 60         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 61 }
 62 
 63 /**
 64  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 65  * @dwc: pointer to our context structure
 66  */
 67 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 68 {
 69         u32             reg;
 70         int             retries = 1000;
 71         int             ret;
 72 
 73         usb_phy_init(dwc->usb2_phy);
 74         usb_phy_init(dwc->usb3_phy);
 75         ret = phy_init(dwc->usb2_generic_phy);
 76         if (ret < 0)
 77                 return ret;
 78 
 79         ret = phy_init(dwc->usb3_generic_phy);
 80         if (ret < 0) {
 81                 phy_exit(dwc->usb2_generic_phy);
 82                 return ret;
 83         }
 84 
 85         /*
 86          * We're resetting only the device side because, if we're in host mode,
 87          * XHCI driver will reset the host block. If dwc3 was configured for
 88          * host-only mode, then we can return early.
 89          */
 90         if (dwc->dr_mode == USB_DR_MODE_HOST)
 91                 return 0;
 92 
 93         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 94         reg |= DWC3_DCTL_CSFTRST;
 95         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 96 
 97         do {
 98                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 99                 if (!(reg & DWC3_DCTL_CSFTRST))
100                         return 0;
101 
102                 udelay(1);
103         } while (--retries);
104 
105         return -ETIMEDOUT;
106 }
107 
108 /**
109  * dwc3_soft_reset - Issue soft reset
110  * @dwc: Pointer to our controller context structure
111  */
112 static int dwc3_soft_reset(struct dwc3 *dwc)
113 {
114         unsigned long timeout;
115         u32 reg;
116 
117         timeout = jiffies + msecs_to_jiffies(500);
118         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
119         do {
120                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121                 if (!(reg & DWC3_DCTL_CSFTRST))
122                         break;
123 
124                 if (time_after(jiffies, timeout)) {
125                         dev_err(dwc->dev, "Reset Timed Out\n");
126                         return -ETIMEDOUT;
127                 }
128 
129                 cpu_relax();
130         } while (true);
131 
132         return 0;
133 }
134 
135 /*
136  * dwc3_frame_length_adjustment - Adjusts frame length if required
137  * @dwc3: Pointer to our controller context structure
138  * @fladj: Value of GFLADJ_30MHZ to adjust frame length
139  */
140 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
141 {
142         u32 reg;
143         u32 dft;
144 
145         if (dwc->revision < DWC3_REVISION_250A)
146                 return;
147 
148         if (fladj == 0)
149                 return;
150 
151         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
152         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
153         if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
154             "request value same as default, ignoring\n")) {
155                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
156                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
157                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
158         }
159 }
160 
161 /**
162  * dwc3_free_one_event_buffer - Frees one event buffer
163  * @dwc: Pointer to our controller context structure
164  * @evt: Pointer to event buffer to be freed
165  */
166 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
167                 struct dwc3_event_buffer *evt)
168 {
169         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
170 }
171 
172 /**
173  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
174  * @dwc: Pointer to our controller context structure
175  * @length: size of the event buffer
176  *
177  * Returns a pointer to the allocated event buffer structure on success
178  * otherwise ERR_PTR(errno).
179  */
180 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
181                 unsigned length)
182 {
183         struct dwc3_event_buffer        *evt;
184 
185         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
186         if (!evt)
187                 return ERR_PTR(-ENOMEM);
188 
189         evt->dwc        = dwc;
190         evt->length     = length;
191         evt->buf        = dma_alloc_coherent(dwc->dev, length,
192                         &evt->dma, GFP_KERNEL);
193         if (!evt->buf)
194                 return ERR_PTR(-ENOMEM);
195 
196         return evt;
197 }
198 
199 /**
200  * dwc3_free_event_buffers - frees all allocated event buffers
201  * @dwc: Pointer to our controller context structure
202  */
203 static void dwc3_free_event_buffers(struct dwc3 *dwc)
204 {
205         struct dwc3_event_buffer        *evt;
206         int i;
207 
208         for (i = 0; i < dwc->num_event_buffers; i++) {
209                 evt = dwc->ev_buffs[i];
210                 if (evt)
211                         dwc3_free_one_event_buffer(dwc, evt);
212         }
213 }
214 
215 /**
216  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
217  * @dwc: pointer to our controller context structure
218  * @length: size of event buffer
219  *
220  * Returns 0 on success otherwise negative errno. In the error case, dwc
221  * may contain some buffers allocated but not all which were requested.
222  */
223 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
224 {
225         int                     num;
226         int                     i;
227 
228         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
229         dwc->num_event_buffers = num;
230 
231         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
232                         GFP_KERNEL);
233         if (!dwc->ev_buffs)
234                 return -ENOMEM;
235 
236         for (i = 0; i < num; i++) {
237                 struct dwc3_event_buffer        *evt;
238 
239                 evt = dwc3_alloc_one_event_buffer(dwc, length);
240                 if (IS_ERR(evt)) {
241                         dev_err(dwc->dev, "can't allocate event buffer\n");
242                         return PTR_ERR(evt);
243                 }
244                 dwc->ev_buffs[i] = evt;
245         }
246 
247         return 0;
248 }
249 
250 /**
251  * dwc3_event_buffers_setup - setup our allocated event buffers
252  * @dwc: pointer to our controller context structure
253  *
254  * Returns 0 on success otherwise negative errno.
255  */
256 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
257 {
258         struct dwc3_event_buffer        *evt;
259         int                             n;
260 
261         for (n = 0; n < dwc->num_event_buffers; n++) {
262                 evt = dwc->ev_buffs[n];
263                 dwc3_trace(trace_dwc3_core,
264                                 "Event buf %p dma %08llx length %d\n",
265                                 evt->buf, (unsigned long long) evt->dma,
266                                 evt->length);
267 
268                 evt->lpos = 0;
269 
270                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
271                                 lower_32_bits(evt->dma));
272                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
273                                 upper_32_bits(evt->dma));
274                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
275                                 DWC3_GEVNTSIZ_SIZE(evt->length));
276                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
277         }
278 
279         return 0;
280 }
281 
282 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
283 {
284         struct dwc3_event_buffer        *evt;
285         int                             n;
286 
287         for (n = 0; n < dwc->num_event_buffers; n++) {
288                 evt = dwc->ev_buffs[n];
289 
290                 evt->lpos = 0;
291 
292                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
293                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
294                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
295                                 | DWC3_GEVNTSIZ_SIZE(0));
296                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
297         }
298 }
299 
300 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
301 {
302         if (!dwc->has_hibernation)
303                 return 0;
304 
305         if (!dwc->nr_scratch)
306                 return 0;
307 
308         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
309                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
310         if (!dwc->scratchbuf)
311                 return -ENOMEM;
312 
313         return 0;
314 }
315 
316 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
317 {
318         dma_addr_t scratch_addr;
319         u32 param;
320         int ret;
321 
322         if (!dwc->has_hibernation)
323                 return 0;
324 
325         if (!dwc->nr_scratch)
326                 return 0;
327 
328          /* should never fall here */
329         if (!WARN_ON(dwc->scratchbuf))
330                 return 0;
331 
332         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
333                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
334                         DMA_BIDIRECTIONAL);
335         if (dma_mapping_error(dwc->dev, scratch_addr)) {
336                 dev_err(dwc->dev, "failed to map scratch buffer\n");
337                 ret = -EFAULT;
338                 goto err0;
339         }
340 
341         dwc->scratch_addr = scratch_addr;
342 
343         param = lower_32_bits(scratch_addr);
344 
345         ret = dwc3_send_gadget_generic_command(dwc,
346                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
347         if (ret < 0)
348                 goto err1;
349 
350         param = upper_32_bits(scratch_addr);
351 
352         ret = dwc3_send_gadget_generic_command(dwc,
353                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
354         if (ret < 0)
355                 goto err1;
356 
357         return 0;
358 
359 err1:
360         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
361                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
362 
363 err0:
364         return ret;
365 }
366 
367 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
368 {
369         if (!dwc->has_hibernation)
370                 return;
371 
372         if (!dwc->nr_scratch)
373                 return;
374 
375          /* should never fall here */
376         if (!WARN_ON(dwc->scratchbuf))
377                 return;
378 
379         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
380                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
381         kfree(dwc->scratchbuf);
382 }
383 
384 static void dwc3_core_num_eps(struct dwc3 *dwc)
385 {
386         struct dwc3_hwparams    *parms = &dwc->hwparams;
387 
388         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
389         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
390 
391         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
392                         dwc->num_in_eps, dwc->num_out_eps);
393 }
394 
395 static void dwc3_cache_hwparams(struct dwc3 *dwc)
396 {
397         struct dwc3_hwparams    *parms = &dwc->hwparams;
398 
399         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
400         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
401         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
402         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
403         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
404         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
405         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
406         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
407         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
408 }
409 
410 /**
411  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
412  * @dwc: Pointer to our controller context structure
413  *
414  * Returns 0 on success. The USB PHY interfaces are configured but not
415  * initialized. The PHY interfaces and the PHYs get initialized together with
416  * the core in dwc3_core_init.
417  */
418 static int dwc3_phy_setup(struct dwc3 *dwc)
419 {
420         u32 reg;
421         int ret;
422 
423         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
424 
425         /*
426          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
427          * to '' during coreConsultant configuration. So default value
428          * will be '' when the core is reset. Application needs to set it
429          * to '1' after the core initialization is completed.
430          */
431         if (dwc->revision > DWC3_REVISION_194A)
432                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
433 
434         if (dwc->u2ss_inp3_quirk)
435                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
436 
437         if (dwc->req_p1p2p3_quirk)
438                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
439 
440         if (dwc->del_p1p2p3_quirk)
441                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
442 
443         if (dwc->del_phy_power_chg_quirk)
444                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
445 
446         if (dwc->lfps_filter_quirk)
447                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
448 
449         if (dwc->rx_detect_poll_quirk)
450                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
451 
452         if (dwc->tx_de_emphasis_quirk)
453                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
454 
455         if (dwc->dis_u3_susphy_quirk)
456                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
457 
458         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
459 
460         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
461 
462         /* Select the HS PHY interface */
463         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
464         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
465                 if (dwc->hsphy_interface &&
466                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
467                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
468                         break;
469                 } else if (dwc->hsphy_interface &&
470                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
471                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
472                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
473                 } else {
474                         /* Relying on default value. */
475                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
476                                 break;
477                 }
478                 /* FALLTHROUGH */
479         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
480                 /* Making sure the interface and PHY are operational */
481                 ret = dwc3_soft_reset(dwc);
482                 if (ret)
483                         return ret;
484 
485                 udelay(1);
486 
487                 ret = dwc3_ulpi_init(dwc);
488                 if (ret)
489                         return ret;
490                 /* FALLTHROUGH */
491         default:
492                 break;
493         }
494 
495         /*
496          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
497          * '' during coreConsultant configuration. So default value will
498          * be '' when the core is reset. Application needs to set it to
499          * '1' after the core initialization is completed.
500          */
501         if (dwc->revision > DWC3_REVISION_194A)
502                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
503 
504         if (dwc->dis_u2_susphy_quirk)
505                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
506 
507         if (dwc->dis_enblslpm_quirk)
508                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
509 
510         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
511 
512         return 0;
513 }
514 
515 /**
516  * dwc3_core_init - Low-level initialization of DWC3 Core
517  * @dwc: Pointer to our controller context structure
518  *
519  * Returns 0 on success otherwise negative errno.
520  */
521 static int dwc3_core_init(struct dwc3 *dwc)
522 {
523         u32                     hwparams4 = dwc->hwparams.hwparams4;
524         u32                     reg;
525         int                     ret;
526 
527         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
528         /* This should read as U3 followed by revision number */
529         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
530                 /* Detected DWC_usb3 IP */
531                 dwc->revision = reg;
532         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
533                 /* Detected DWC_usb31 IP */
534                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
535                 dwc->revision |= DWC3_REVISION_IS_DWC31;
536         } else {
537                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
538                 ret = -ENODEV;
539                 goto err0;
540         }
541 
542         /*
543          * Write Linux Version Code to our GUID register so it's easy to figure
544          * out which kernel version a bug was found.
545          */
546         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
547 
548         /* Handle USB2.0-only core configuration */
549         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
550                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
551                 if (dwc->maximum_speed == USB_SPEED_SUPER)
552                         dwc->maximum_speed = USB_SPEED_HIGH;
553         }
554 
555         /* issue device SoftReset too */
556         ret = dwc3_soft_reset(dwc);
557         if (ret)
558                 goto err0;
559 
560         ret = dwc3_core_soft_reset(dwc);
561         if (ret)
562                 goto err0;
563 
564         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
565         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
566 
567         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
568         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
569                 /**
570                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
571                  * issue which would cause xHCI compliance tests to fail.
572                  *
573                  * Because of that we cannot enable clock gating on such
574                  * configurations.
575                  *
576                  * Refers to:
577                  *
578                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
579                  * SOF/ITP Mode Used
580                  */
581                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
582                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
583                                 (dwc->revision >= DWC3_REVISION_210A &&
584                                 dwc->revision <= DWC3_REVISION_250A))
585                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
586                 else
587                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
588                 break;
589         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
590                 /* enable hibernation here */
591                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
592 
593                 /*
594                  * REVISIT Enabling this bit so that host-mode hibernation
595                  * will work. Device-mode hibernation is not yet implemented.
596                  */
597                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
598                 break;
599         default:
600                 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
601         }
602 
603         /* check if current dwc3 is on simulation board */
604         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
605                 dwc3_trace(trace_dwc3_core,
606                                 "running on FPGA platform\n");
607                 dwc->is_fpga = true;
608         }
609 
610         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
611                         "disable_scramble cannot be used on non-FPGA builds\n");
612 
613         if (dwc->disable_scramble_quirk && dwc->is_fpga)
614                 reg |= DWC3_GCTL_DISSCRAMBLE;
615         else
616                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
617 
618         if (dwc->u2exit_lfps_quirk)
619                 reg |= DWC3_GCTL_U2EXIT_LFPS;
620 
621         /*
622          * WORKAROUND: DWC3 revisions <1.90a have a bug
623          * where the device can fail to connect at SuperSpeed
624          * and falls back to high-speed mode which causes
625          * the device to enter a Connect/Disconnect loop
626          */
627         if (dwc->revision < DWC3_REVISION_190A)
628                 reg |= DWC3_GCTL_U2RSTECN;
629 
630         dwc3_core_num_eps(dwc);
631 
632         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
633 
634         ret = dwc3_alloc_scratch_buffers(dwc);
635         if (ret)
636                 goto err1;
637 
638         ret = dwc3_setup_scratch_buffers(dwc);
639         if (ret)
640                 goto err2;
641 
642         return 0;
643 
644 err2:
645         dwc3_free_scratch_buffers(dwc);
646 
647 err1:
648         usb_phy_shutdown(dwc->usb2_phy);
649         usb_phy_shutdown(dwc->usb3_phy);
650         phy_exit(dwc->usb2_generic_phy);
651         phy_exit(dwc->usb3_generic_phy);
652 
653 err0:
654         return ret;
655 }
656 
657 static void dwc3_core_exit(struct dwc3 *dwc)
658 {
659         dwc3_free_scratch_buffers(dwc);
660         usb_phy_shutdown(dwc->usb2_phy);
661         usb_phy_shutdown(dwc->usb3_phy);
662         phy_exit(dwc->usb2_generic_phy);
663         phy_exit(dwc->usb3_generic_phy);
664 }
665 
666 static int dwc3_core_get_phy(struct dwc3 *dwc)
667 {
668         struct device           *dev = dwc->dev;
669         struct device_node      *node = dev->of_node;
670         int ret;
671 
672         if (node) {
673                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
674                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
675         } else {
676                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
677                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
678         }
679 
680         if (IS_ERR(dwc->usb2_phy)) {
681                 ret = PTR_ERR(dwc->usb2_phy);
682                 if (ret == -ENXIO || ret == -ENODEV) {
683                         dwc->usb2_phy = NULL;
684                 } else if (ret == -EPROBE_DEFER) {
685                         return ret;
686                 } else {
687                         dev_err(dev, "no usb2 phy configured\n");
688                         return ret;
689                 }
690         }
691 
692         if (IS_ERR(dwc->usb3_phy)) {
693                 ret = PTR_ERR(dwc->usb3_phy);
694                 if (ret == -ENXIO || ret == -ENODEV) {
695                         dwc->usb3_phy = NULL;
696                 } else if (ret == -EPROBE_DEFER) {
697                         return ret;
698                 } else {
699                         dev_err(dev, "no usb3 phy configured\n");
700                         return ret;
701                 }
702         }
703 
704         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
705         if (IS_ERR(dwc->usb2_generic_phy)) {
706                 ret = PTR_ERR(dwc->usb2_generic_phy);
707                 if (ret == -ENOSYS || ret == -ENODEV) {
708                         dwc->usb2_generic_phy = NULL;
709                 } else if (ret == -EPROBE_DEFER) {
710                         return ret;
711                 } else {
712                         dev_err(dev, "no usb2 phy configured\n");
713                         return ret;
714                 }
715         }
716 
717         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
718         if (IS_ERR(dwc->usb3_generic_phy)) {
719                 ret = PTR_ERR(dwc->usb3_generic_phy);
720                 if (ret == -ENOSYS || ret == -ENODEV) {
721                         dwc->usb3_generic_phy = NULL;
722                 } else if (ret == -EPROBE_DEFER) {
723                         return ret;
724                 } else {
725                         dev_err(dev, "no usb3 phy configured\n");
726                         return ret;
727                 }
728         }
729 
730         return 0;
731 }
732 
733 static int dwc3_core_init_mode(struct dwc3 *dwc)
734 {
735         struct device *dev = dwc->dev;
736         int ret;
737 
738         switch (dwc->dr_mode) {
739         case USB_DR_MODE_PERIPHERAL:
740                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
741                 ret = dwc3_gadget_init(dwc);
742                 if (ret) {
743                         dev_err(dev, "failed to initialize gadget\n");
744                         return ret;
745                 }
746                 break;
747         case USB_DR_MODE_HOST:
748                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
749                 ret = dwc3_host_init(dwc);
750                 if (ret) {
751                         dev_err(dev, "failed to initialize host\n");
752                         return ret;
753                 }
754                 break;
755         case USB_DR_MODE_OTG:
756                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
757                 ret = dwc3_host_init(dwc);
758                 if (ret) {
759                         dev_err(dev, "failed to initialize host\n");
760                         return ret;
761                 }
762 
763                 ret = dwc3_gadget_init(dwc);
764                 if (ret) {
765                         dev_err(dev, "failed to initialize gadget\n");
766                         return ret;
767                 }
768                 break;
769         default:
770                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
771                 return -EINVAL;
772         }
773 
774         return 0;
775 }
776 
777 static void dwc3_core_exit_mode(struct dwc3 *dwc)
778 {
779         switch (dwc->dr_mode) {
780         case USB_DR_MODE_PERIPHERAL:
781                 dwc3_gadget_exit(dwc);
782                 break;
783         case USB_DR_MODE_HOST:
784                 dwc3_host_exit(dwc);
785                 break;
786         case USB_DR_MODE_OTG:
787                 dwc3_host_exit(dwc);
788                 dwc3_gadget_exit(dwc);
789                 break;
790         default:
791                 /* do nothing */
792                 break;
793         }
794 }
795 
796 #define DWC3_ALIGN_MASK         (16 - 1)
797 
798 static int dwc3_probe(struct platform_device *pdev)
799 {
800         struct device           *dev = &pdev->dev;
801         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
802         struct resource         *res;
803         struct dwc3             *dwc;
804         u8                      lpm_nyet_threshold;
805         u8                      tx_de_emphasis;
806         u8                      hird_threshold;
807         u32                     fladj = 0;
808 
809         int                     ret;
810 
811         void __iomem            *regs;
812         void                    *mem;
813 
814         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
815         if (!mem)
816                 return -ENOMEM;
817 
818         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
819         dwc->mem = mem;
820         dwc->dev = dev;
821 
822         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
823         if (!res) {
824                 dev_err(dev, "missing IRQ\n");
825                 return -ENODEV;
826         }
827         dwc->xhci_resources[1].start = res->start;
828         dwc->xhci_resources[1].end = res->end;
829         dwc->xhci_resources[1].flags = res->flags;
830         dwc->xhci_resources[1].name = res->name;
831 
832         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
833         if (!res) {
834                 dev_err(dev, "missing memory resource\n");
835                 return -ENODEV;
836         }
837 
838         dwc->xhci_resources[0].start = res->start;
839         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
840                                         DWC3_XHCI_REGS_END;
841         dwc->xhci_resources[0].flags = res->flags;
842         dwc->xhci_resources[0].name = res->name;
843 
844         res->start += DWC3_GLOBALS_REGS_START;
845 
846         /*
847          * Request memory region but exclude xHCI regs,
848          * since it will be requested by the xhci-plat driver.
849          */
850         regs = devm_ioremap_resource(dev, res);
851         if (IS_ERR(regs)) {
852                 ret = PTR_ERR(regs);
853                 goto err0;
854         }
855 
856         dwc->regs       = regs;
857         dwc->regs_size  = resource_size(res);
858 
859         /* default to highest possible threshold */
860         lpm_nyet_threshold = 0xff;
861 
862         /* default to -3.5dB de-emphasis */
863         tx_de_emphasis = 1;
864 
865         /*
866          * default to assert utmi_sleep_n and use maximum allowed HIRD
867          * threshold value of 0b1100
868          */
869         hird_threshold = 12;
870 
871         dwc->maximum_speed = usb_get_maximum_speed(dev);
872         dwc->dr_mode = usb_get_dr_mode(dev);
873 
874         dwc->has_lpm_erratum = device_property_read_bool(dev,
875                                 "snps,has-lpm-erratum");
876         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
877                                 &lpm_nyet_threshold);
878         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
879                                 "snps,is-utmi-l1-suspend");
880         device_property_read_u8(dev, "snps,hird-threshold",
881                                 &hird_threshold);
882         dwc->usb3_lpm_capable = device_property_read_bool(dev,
883                                 "snps,usb3_lpm_capable");
884 
885         dwc->needs_fifo_resize = device_property_read_bool(dev,
886                                 "tx-fifo-resize");
887 
888         dwc->disable_scramble_quirk = device_property_read_bool(dev,
889                                 "snps,disable_scramble_quirk");
890         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
891                                 "snps,u2exit_lfps_quirk");
892         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
893                                 "snps,u2ss_inp3_quirk");
894         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
895                                 "snps,req_p1p2p3_quirk");
896         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
897                                 "snps,del_p1p2p3_quirk");
898         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
899                                 "snps,del_phy_power_chg_quirk");
900         dwc->lfps_filter_quirk = device_property_read_bool(dev,
901                                 "snps,lfps_filter_quirk");
902         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
903                                 "snps,rx_detect_poll_quirk");
904         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
905                                 "snps,dis_u3_susphy_quirk");
906         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
907                                 "snps,dis_u2_susphy_quirk");
908         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
909                                 "snps,dis_enblslpm_quirk");
910 
911         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
912                                 "snps,tx_de_emphasis_quirk");
913         device_property_read_u8(dev, "snps,tx_de_emphasis",
914                                 &tx_de_emphasis);
915         device_property_read_string(dev, "snps,hsphy_interface",
916                                     &dwc->hsphy_interface);
917         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
918                                  &fladj);
919 
920         if (pdata) {
921                 dwc->maximum_speed = pdata->maximum_speed;
922                 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
923                 if (pdata->lpm_nyet_threshold)
924                         lpm_nyet_threshold = pdata->lpm_nyet_threshold;
925                 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
926                 if (pdata->hird_threshold)
927                         hird_threshold = pdata->hird_threshold;
928 
929                 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
930                 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
931                 dwc->dr_mode = pdata->dr_mode;
932 
933                 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
934                 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
935                 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
936                 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
937                 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
938                 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
939                 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
940                 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
941                 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
942                 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
943                 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
944 
945                 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
946                 if (pdata->tx_de_emphasis)
947                         tx_de_emphasis = pdata->tx_de_emphasis;
948 
949                 dwc->hsphy_interface = pdata->hsphy_interface;
950                 fladj = pdata->fladj_value;
951         }
952 
953         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
954         dwc->tx_de_emphasis = tx_de_emphasis;
955 
956         dwc->hird_threshold = hird_threshold
957                 | (dwc->is_utmi_l1_suspend << 4);
958 
959         platform_set_drvdata(pdev, dwc);
960         dwc3_cache_hwparams(dwc);
961 
962         ret = dwc3_phy_setup(dwc);
963         if (ret)
964                 goto err0;
965 
966         ret = dwc3_core_get_phy(dwc);
967         if (ret)
968                 goto err0;
969 
970         spin_lock_init(&dwc->lock);
971 
972         if (!dev->dma_mask) {
973                 dev->dma_mask = dev->parent->dma_mask;
974                 dev->dma_parms = dev->parent->dma_parms;
975                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
976         }
977 
978         pm_runtime_enable(dev);
979         pm_runtime_get_sync(dev);
980         pm_runtime_forbid(dev);
981 
982         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
983         if (ret) {
984                 dev_err(dwc->dev, "failed to allocate event buffers\n");
985                 ret = -ENOMEM;
986                 goto err1;
987         }
988 
989         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
990                 dwc->dr_mode = USB_DR_MODE_HOST;
991         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
992                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
993 
994         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
995                 dwc->dr_mode = USB_DR_MODE_OTG;
996 
997         ret = dwc3_core_init(dwc);
998         if (ret) {
999                 dev_err(dev, "failed to initialize core\n");
1000                 goto err1;
1001         }
1002 
1003         /* Check the maximum_speed parameter */
1004         switch (dwc->maximum_speed) {
1005         case USB_SPEED_LOW:
1006         case USB_SPEED_FULL:
1007         case USB_SPEED_HIGH:
1008         case USB_SPEED_SUPER:
1009         case USB_SPEED_SUPER_PLUS:
1010                 break;
1011         default:
1012                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1013                         dwc->maximum_speed);
1014                 /* fall through */
1015         case USB_SPEED_UNKNOWN:
1016                 /* default to superspeed */
1017                 dwc->maximum_speed = USB_SPEED_SUPER;
1018 
1019                 /*
1020                  * default to superspeed plus if we are capable.
1021                  */
1022                 if (dwc3_is_usb31(dwc) &&
1023                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1024                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1025                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1026 
1027                 break;
1028         }
1029 
1030         /* Adjust Frame Length */
1031         dwc3_frame_length_adjustment(dwc, fladj);
1032 
1033         usb_phy_set_suspend(dwc->usb2_phy, 0);
1034         usb_phy_set_suspend(dwc->usb3_phy, 0);
1035         ret = phy_power_on(dwc->usb2_generic_phy);
1036         if (ret < 0)
1037                 goto err2;
1038 
1039         ret = phy_power_on(dwc->usb3_generic_phy);
1040         if (ret < 0)
1041                 goto err3;
1042 
1043         ret = dwc3_event_buffers_setup(dwc);
1044         if (ret) {
1045                 dev_err(dwc->dev, "failed to setup event buffers\n");
1046                 goto err4;
1047         }
1048 
1049         ret = dwc3_core_init_mode(dwc);
1050         if (ret)
1051                 goto err5;
1052 
1053         ret = dwc3_debugfs_init(dwc);
1054         if (ret) {
1055                 dev_err(dev, "failed to initialize debugfs\n");
1056                 goto err6;
1057         }
1058 
1059         pm_runtime_allow(dev);
1060 
1061         return 0;
1062 
1063 err6:
1064         dwc3_core_exit_mode(dwc);
1065 
1066 err5:
1067         dwc3_event_buffers_cleanup(dwc);
1068 
1069 err4:
1070         phy_power_off(dwc->usb3_generic_phy);
1071 
1072 err3:
1073         phy_power_off(dwc->usb2_generic_phy);
1074 
1075 err2:
1076         usb_phy_set_suspend(dwc->usb2_phy, 1);
1077         usb_phy_set_suspend(dwc->usb3_phy, 1);
1078         dwc3_core_exit(dwc);
1079 
1080 err1:
1081         dwc3_free_event_buffers(dwc);
1082         dwc3_ulpi_exit(dwc);
1083 
1084 err0:
1085         /*
1086          * restore res->start back to its original value so that, in case the
1087          * probe is deferred, we don't end up getting error in request the
1088          * memory region the next time probe is called.
1089          */
1090         res->start -= DWC3_GLOBALS_REGS_START;
1091 
1092         return ret;
1093 }
1094 
1095 static int dwc3_remove(struct platform_device *pdev)
1096 {
1097         struct dwc3     *dwc = platform_get_drvdata(pdev);
1098         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1099 
1100         /*
1101          * restore res->start back to its original value so that, in case the
1102          * probe is deferred, we don't end up getting error in request the
1103          * memory region the next time probe is called.
1104          */
1105         res->start -= DWC3_GLOBALS_REGS_START;
1106 
1107         dwc3_debugfs_exit(dwc);
1108         dwc3_core_exit_mode(dwc);
1109         dwc3_event_buffers_cleanup(dwc);
1110         dwc3_free_event_buffers(dwc);
1111 
1112         usb_phy_set_suspend(dwc->usb2_phy, 1);
1113         usb_phy_set_suspend(dwc->usb3_phy, 1);
1114         phy_power_off(dwc->usb2_generic_phy);
1115         phy_power_off(dwc->usb3_generic_phy);
1116 
1117         dwc3_core_exit(dwc);
1118         dwc3_ulpi_exit(dwc);
1119 
1120         pm_runtime_put_sync(&pdev->dev);
1121         pm_runtime_disable(&pdev->dev);
1122 
1123         return 0;
1124 }
1125 
1126 #ifdef CONFIG_PM_SLEEP
1127 static int dwc3_suspend(struct device *dev)
1128 {
1129         struct dwc3     *dwc = dev_get_drvdata(dev);
1130         unsigned long   flags;
1131 
1132         spin_lock_irqsave(&dwc->lock, flags);
1133 
1134         switch (dwc->dr_mode) {
1135         case USB_DR_MODE_PERIPHERAL:
1136         case USB_DR_MODE_OTG:
1137                 dwc3_gadget_suspend(dwc);
1138                 /* FALLTHROUGH */
1139         case USB_DR_MODE_HOST:
1140         default:
1141                 dwc3_event_buffers_cleanup(dwc);
1142                 break;
1143         }
1144 
1145         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1146         spin_unlock_irqrestore(&dwc->lock, flags);
1147 
1148         usb_phy_shutdown(dwc->usb3_phy);
1149         usb_phy_shutdown(dwc->usb2_phy);
1150         phy_exit(dwc->usb2_generic_phy);
1151         phy_exit(dwc->usb3_generic_phy);
1152 
1153         usb_phy_set_suspend(dwc->usb2_phy, 1);
1154         usb_phy_set_suspend(dwc->usb3_phy, 1);
1155         WARN_ON(phy_power_off(dwc->usb2_generic_phy) < 0);
1156         WARN_ON(phy_power_off(dwc->usb3_generic_phy) < 0);
1157 
1158         pinctrl_pm_select_sleep_state(dev);
1159 
1160         return 0;
1161 }
1162 
1163 static int dwc3_resume(struct device *dev)
1164 {
1165         struct dwc3     *dwc = dev_get_drvdata(dev);
1166         unsigned long   flags;
1167         int             ret;
1168 
1169         pinctrl_pm_select_default_state(dev);
1170 
1171         usb_phy_set_suspend(dwc->usb2_phy, 0);
1172         usb_phy_set_suspend(dwc->usb3_phy, 0);
1173         ret = phy_power_on(dwc->usb2_generic_phy);
1174         if (ret < 0)
1175                 return ret;
1176 
1177         ret = phy_power_on(dwc->usb3_generic_phy);
1178         if (ret < 0)
1179                 goto err_usb2phy_power;
1180 
1181         usb_phy_init(dwc->usb3_phy);
1182         usb_phy_init(dwc->usb2_phy);
1183         ret = phy_init(dwc->usb2_generic_phy);
1184         if (ret < 0)
1185                 goto err_usb3phy_power;
1186 
1187         ret = phy_init(dwc->usb3_generic_phy);
1188         if (ret < 0)
1189                 goto err_usb2phy_init;
1190 
1191         spin_lock_irqsave(&dwc->lock, flags);
1192 
1193         dwc3_event_buffers_setup(dwc);
1194         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1195 
1196         switch (dwc->dr_mode) {
1197         case USB_DR_MODE_PERIPHERAL:
1198         case USB_DR_MODE_OTG:
1199                 dwc3_gadget_resume(dwc);
1200                 /* FALLTHROUGH */
1201         case USB_DR_MODE_HOST:
1202         default:
1203                 /* do nothing */
1204                 break;
1205         }
1206 
1207         spin_unlock_irqrestore(&dwc->lock, flags);
1208 
1209         pm_runtime_disable(dev);
1210         pm_runtime_set_active(dev);
1211         pm_runtime_enable(dev);
1212 
1213         return 0;
1214 
1215 err_usb2phy_init:
1216         phy_exit(dwc->usb2_generic_phy);
1217 
1218 err_usb3phy_power:
1219         phy_power_off(dwc->usb3_generic_phy);
1220 
1221 err_usb2phy_power:
1222         phy_power_off(dwc->usb2_generic_phy);
1223 
1224         return ret;
1225 }
1226 
1227 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1228         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1229 };
1230 
1231 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
1232 #else
1233 #define DWC3_PM_OPS     NULL
1234 #endif
1235 
1236 #ifdef CONFIG_OF
1237 static const struct of_device_id of_dwc3_match[] = {
1238         {
1239                 .compatible = "snps,dwc3"
1240         },
1241         {
1242                 .compatible = "synopsys,dwc3"
1243         },
1244         { },
1245 };
1246 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1247 #endif
1248 
1249 #ifdef CONFIG_ACPI
1250 
1251 #define ACPI_ID_INTEL_BSW       "808622B7"
1252 
1253 static const struct acpi_device_id dwc3_acpi_match[] = {
1254         { ACPI_ID_INTEL_BSW, 0 },
1255         { },
1256 };
1257 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1258 #endif
1259 
1260 static struct platform_driver dwc3_driver = {
1261         .probe          = dwc3_probe,
1262         .remove         = dwc3_remove,
1263         .driver         = {
1264                 .name   = "dwc3",
1265                 .of_match_table = of_match_ptr(of_dwc3_match),
1266                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1267                 .pm     = DWC3_PM_OPS,
1268         },
1269 };
1270 
1271 module_platform_driver(dwc3_driver);
1272 
1273 MODULE_ALIAS("platform:dwc3");
1274 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1275 MODULE_LICENSE("GPL v2");
1276 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
1277 

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