Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/usb/dwc3/core.c

  1 /**
  2  * core.c - DesignWare USB3 DRD Controller Core file
  3  *
  4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5  *
  6  * Authors: Felipe Balbi <balbi@ti.com>,
  7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8  *
  9  * This program is free software: you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2  of
 11  * the License as published by the Free Software Foundation.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 20  */
 21 
 22 #include <linux/version.h>
 23 #include <linux/module.h>
 24 #include <linux/kernel.h>
 25 #include <linux/slab.h>
 26 #include <linux/spinlock.h>
 27 #include <linux/platform_device.h>
 28 #include <linux/pm_runtime.h>
 29 #include <linux/interrupt.h>
 30 #include <linux/ioport.h>
 31 #include <linux/io.h>
 32 #include <linux/list.h>
 33 #include <linux/delay.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/of.h>
 36 #include <linux/acpi.h>
 37 #include <linux/pinctrl/consumer.h>
 38 
 39 #include <linux/usb/ch9.h>
 40 #include <linux/usb/gadget.h>
 41 #include <linux/usb/of.h>
 42 #include <linux/usb/otg.h>
 43 
 44 #include "core.h"
 45 #include "gadget.h"
 46 #include "io.h"
 47 
 48 #include "debug.h"
 49 
 50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
 51 
 52 /**
 53  * dwc3_get_dr_mode - Validates and sets dr_mode
 54  * @dwc: pointer to our context structure
 55  */
 56 static int dwc3_get_dr_mode(struct dwc3 *dwc)
 57 {
 58         enum usb_dr_mode mode;
 59         struct device *dev = dwc->dev;
 60         unsigned int hw_mode;
 61 
 62         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
 63                 dwc->dr_mode = USB_DR_MODE_OTG;
 64 
 65         mode = dwc->dr_mode;
 66         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 67 
 68         switch (hw_mode) {
 69         case DWC3_GHWPARAMS0_MODE_GADGET:
 70                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
 71                         dev_err(dev,
 72                                 "Controller does not support host mode.\n");
 73                         return -EINVAL;
 74                 }
 75                 mode = USB_DR_MODE_PERIPHERAL;
 76                 break;
 77         case DWC3_GHWPARAMS0_MODE_HOST:
 78                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
 79                         dev_err(dev,
 80                                 "Controller does not support device mode.\n");
 81                         return -EINVAL;
 82                 }
 83                 mode = USB_DR_MODE_HOST;
 84                 break;
 85         default:
 86                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
 87                         mode = USB_DR_MODE_HOST;
 88                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 89                         mode = USB_DR_MODE_PERIPHERAL;
 90         }
 91 
 92         if (mode != dwc->dr_mode) {
 93                 dev_warn(dev,
 94                          "Configuration mismatch. dr_mode forced to %s\n",
 95                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
 96 
 97                 dwc->dr_mode = mode;
 98         }
 99 
100         return 0;
101 }
102 
103 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
104 {
105         u32 reg;
106 
107         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
108         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
109         reg |= DWC3_GCTL_PRTCAPDIR(mode);
110         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
111 }
112 
113 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
114 {
115         struct dwc3             *dwc = dep->dwc;
116         u32                     reg;
117 
118         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
119                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
120                         DWC3_GDBGFIFOSPACE_TYPE(type));
121 
122         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
123 
124         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
125 }
126 
127 /**
128  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
129  * @dwc: pointer to our context structure
130  */
131 static int dwc3_core_soft_reset(struct dwc3 *dwc)
132 {
133         u32             reg;
134         int             retries = 1000;
135         int             ret;
136 
137         usb_phy_init(dwc->usb2_phy);
138         usb_phy_init(dwc->usb3_phy);
139         ret = phy_init(dwc->usb2_generic_phy);
140         if (ret < 0)
141                 return ret;
142 
143         ret = phy_init(dwc->usb3_generic_phy);
144         if (ret < 0) {
145                 phy_exit(dwc->usb2_generic_phy);
146                 return ret;
147         }
148 
149         /*
150          * We're resetting only the device side because, if we're in host mode,
151          * XHCI driver will reset the host block. If dwc3 was configured for
152          * host-only mode, then we can return early.
153          */
154         if (dwc->dr_mode == USB_DR_MODE_HOST)
155                 return 0;
156 
157         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
158         reg |= DWC3_DCTL_CSFTRST;
159         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
160 
161         do {
162                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
163                 if (!(reg & DWC3_DCTL_CSFTRST))
164                         return 0;
165 
166                 udelay(1);
167         } while (--retries);
168 
169         return -ETIMEDOUT;
170 }
171 
172 /*
173  * dwc3_frame_length_adjustment - Adjusts frame length if required
174  * @dwc3: Pointer to our controller context structure
175  */
176 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
177 {
178         u32 reg;
179         u32 dft;
180 
181         if (dwc->revision < DWC3_REVISION_250A)
182                 return;
183 
184         if (dwc->fladj == 0)
185                 return;
186 
187         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
188         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
189         if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
190             "request value same as default, ignoring\n")) {
191                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
192                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
193                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
194         }
195 }
196 
197 /**
198  * dwc3_free_one_event_buffer - Frees one event buffer
199  * @dwc: Pointer to our controller context structure
200  * @evt: Pointer to event buffer to be freed
201  */
202 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
203                 struct dwc3_event_buffer *evt)
204 {
205         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
206 }
207 
208 /**
209  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
210  * @dwc: Pointer to our controller context structure
211  * @length: size of the event buffer
212  *
213  * Returns a pointer to the allocated event buffer structure on success
214  * otherwise ERR_PTR(errno).
215  */
216 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
217                 unsigned length)
218 {
219         struct dwc3_event_buffer        *evt;
220 
221         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
222         if (!evt)
223                 return ERR_PTR(-ENOMEM);
224 
225         evt->dwc        = dwc;
226         evt->length     = length;
227         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
228         if (!evt->cache)
229                 return ERR_PTR(-ENOMEM);
230 
231         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
232                         &evt->dma, GFP_KERNEL);
233         if (!evt->buf)
234                 return ERR_PTR(-ENOMEM);
235 
236         return evt;
237 }
238 
239 /**
240  * dwc3_free_event_buffers - frees all allocated event buffers
241  * @dwc: Pointer to our controller context structure
242  */
243 static void dwc3_free_event_buffers(struct dwc3 *dwc)
244 {
245         struct dwc3_event_buffer        *evt;
246 
247         evt = dwc->ev_buf;
248         if (evt)
249                 dwc3_free_one_event_buffer(dwc, evt);
250 }
251 
252 /**
253  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
254  * @dwc: pointer to our controller context structure
255  * @length: size of event buffer
256  *
257  * Returns 0 on success otherwise negative errno. In the error case, dwc
258  * may contain some buffers allocated but not all which were requested.
259  */
260 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
261 {
262         struct dwc3_event_buffer *evt;
263 
264         evt = dwc3_alloc_one_event_buffer(dwc, length);
265         if (IS_ERR(evt)) {
266                 dev_err(dwc->dev, "can't allocate event buffer\n");
267                 return PTR_ERR(evt);
268         }
269         dwc->ev_buf = evt;
270 
271         return 0;
272 }
273 
274 /**
275  * dwc3_event_buffers_setup - setup our allocated event buffers
276  * @dwc: pointer to our controller context structure
277  *
278  * Returns 0 on success otherwise negative errno.
279  */
280 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
281 {
282         struct dwc3_event_buffer        *evt;
283 
284         evt = dwc->ev_buf;
285         evt->lpos = 0;
286         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
287                         lower_32_bits(evt->dma));
288         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
289                         upper_32_bits(evt->dma));
290         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
291                         DWC3_GEVNTSIZ_SIZE(evt->length));
292         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
293 
294         return 0;
295 }
296 
297 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
298 {
299         struct dwc3_event_buffer        *evt;
300 
301         evt = dwc->ev_buf;
302 
303         evt->lpos = 0;
304 
305         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
306         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
307         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
308                         | DWC3_GEVNTSIZ_SIZE(0));
309         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
310 }
311 
312 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
313 {
314         if (!dwc->has_hibernation)
315                 return 0;
316 
317         if (!dwc->nr_scratch)
318                 return 0;
319 
320         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
321                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
322         if (!dwc->scratchbuf)
323                 return -ENOMEM;
324 
325         return 0;
326 }
327 
328 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
329 {
330         dma_addr_t scratch_addr;
331         u32 param;
332         int ret;
333 
334         if (!dwc->has_hibernation)
335                 return 0;
336 
337         if (!dwc->nr_scratch)
338                 return 0;
339 
340          /* should never fall here */
341         if (!WARN_ON(dwc->scratchbuf))
342                 return 0;
343 
344         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
345                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
346                         DMA_BIDIRECTIONAL);
347         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
348                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
349                 ret = -EFAULT;
350                 goto err0;
351         }
352 
353         dwc->scratch_addr = scratch_addr;
354 
355         param = lower_32_bits(scratch_addr);
356 
357         ret = dwc3_send_gadget_generic_command(dwc,
358                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
359         if (ret < 0)
360                 goto err1;
361 
362         param = upper_32_bits(scratch_addr);
363 
364         ret = dwc3_send_gadget_generic_command(dwc,
365                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
366         if (ret < 0)
367                 goto err1;
368 
369         return 0;
370 
371 err1:
372         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
373                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
374 
375 err0:
376         return ret;
377 }
378 
379 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
380 {
381         if (!dwc->has_hibernation)
382                 return;
383 
384         if (!dwc->nr_scratch)
385                 return;
386 
387          /* should never fall here */
388         if (!WARN_ON(dwc->scratchbuf))
389                 return;
390 
391         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
392                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
393         kfree(dwc->scratchbuf);
394 }
395 
396 static void dwc3_core_num_eps(struct dwc3 *dwc)
397 {
398         struct dwc3_hwparams    *parms = &dwc->hwparams;
399 
400         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
401         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
402 }
403 
404 static void dwc3_cache_hwparams(struct dwc3 *dwc)
405 {
406         struct dwc3_hwparams    *parms = &dwc->hwparams;
407 
408         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
409         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
410         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
411         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
412         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
413         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
414         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
415         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
416         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
417 }
418 
419 /**
420  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
421  * @dwc: Pointer to our controller context structure
422  *
423  * Returns 0 on success. The USB PHY interfaces are configured but not
424  * initialized. The PHY interfaces and the PHYs get initialized together with
425  * the core in dwc3_core_init.
426  */
427 static int dwc3_phy_setup(struct dwc3 *dwc)
428 {
429         u32 reg;
430         int ret;
431 
432         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
433 
434         /*
435          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
436          * to '' during coreConsultant configuration. So default value
437          * will be '' when the core is reset. Application needs to set it
438          * to '1' after the core initialization is completed.
439          */
440         if (dwc->revision > DWC3_REVISION_194A)
441                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
442 
443         if (dwc->u2ss_inp3_quirk)
444                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
445 
446         if (dwc->dis_rxdet_inp3_quirk)
447                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
448 
449         if (dwc->req_p1p2p3_quirk)
450                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
451 
452         if (dwc->del_p1p2p3_quirk)
453                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
454 
455         if (dwc->del_phy_power_chg_quirk)
456                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
457 
458         if (dwc->lfps_filter_quirk)
459                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
460 
461         if (dwc->rx_detect_poll_quirk)
462                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
463 
464         if (dwc->tx_de_emphasis_quirk)
465                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
466 
467         if (dwc->dis_u3_susphy_quirk)
468                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
469 
470         if (dwc->dis_del_phy_power_chg_quirk)
471                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
472 
473         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
474 
475         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
476 
477         /* Select the HS PHY interface */
478         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
479         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
480                 if (dwc->hsphy_interface &&
481                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
482                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
483                         break;
484                 } else if (dwc->hsphy_interface &&
485                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
486                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
487                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
488                 } else {
489                         /* Relying on default value. */
490                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
491                                 break;
492                 }
493                 /* FALLTHROUGH */
494         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
495                 ret = dwc3_ulpi_init(dwc);
496                 if (ret)
497                         return ret;
498                 /* FALLTHROUGH */
499         default:
500                 break;
501         }
502 
503         switch (dwc->hsphy_mode) {
504         case USBPHY_INTERFACE_MODE_UTMI:
505                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
506                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
507                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
508                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
509                 break;
510         case USBPHY_INTERFACE_MODE_UTMIW:
511                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
512                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
513                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
514                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
515                 break;
516         default:
517                 break;
518         }
519 
520         /*
521          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
522          * '' during coreConsultant configuration. So default value will
523          * be '' when the core is reset. Application needs to set it to
524          * '1' after the core initialization is completed.
525          */
526         if (dwc->revision > DWC3_REVISION_194A)
527                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
528 
529         if (dwc->dis_u2_susphy_quirk)
530                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
531 
532         if (dwc->dis_enblslpm_quirk)
533                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
534 
535         if (dwc->dis_u2_freeclk_exists_quirk)
536                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
537 
538         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
539 
540         return 0;
541 }
542 
543 static void dwc3_core_exit(struct dwc3 *dwc)
544 {
545         dwc3_event_buffers_cleanup(dwc);
546 
547         usb_phy_shutdown(dwc->usb2_phy);
548         usb_phy_shutdown(dwc->usb3_phy);
549         phy_exit(dwc->usb2_generic_phy);
550         phy_exit(dwc->usb3_generic_phy);
551 
552         usb_phy_set_suspend(dwc->usb2_phy, 1);
553         usb_phy_set_suspend(dwc->usb3_phy, 1);
554         phy_power_off(dwc->usb2_generic_phy);
555         phy_power_off(dwc->usb3_generic_phy);
556 }
557 
558 static bool dwc3_core_is_valid(struct dwc3 *dwc)
559 {
560         u32 reg;
561 
562         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
563 
564         /* This should read as U3 followed by revision number */
565         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
566                 /* Detected DWC_usb3 IP */
567                 dwc->revision = reg;
568         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
569                 /* Detected DWC_usb31 IP */
570                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
571                 dwc->revision |= DWC3_REVISION_IS_DWC31;
572         } else {
573                 return false;
574         }
575 
576         return true;
577 }
578 
579 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
580 {
581         u32 hwparams4 = dwc->hwparams.hwparams4;
582         u32 reg;
583 
584         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
585         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
586 
587         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
588         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
589                 /**
590                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
591                  * issue which would cause xHCI compliance tests to fail.
592                  *
593                  * Because of that we cannot enable clock gating on such
594                  * configurations.
595                  *
596                  * Refers to:
597                  *
598                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
599                  * SOF/ITP Mode Used
600                  */
601                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
602                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
603                                 (dwc->revision >= DWC3_REVISION_210A &&
604                                 dwc->revision <= DWC3_REVISION_250A))
605                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
606                 else
607                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
608                 break;
609         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
610                 /* enable hibernation here */
611                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
612 
613                 /*
614                  * REVISIT Enabling this bit so that host-mode hibernation
615                  * will work. Device-mode hibernation is not yet implemented.
616                  */
617                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
618                 break;
619         default:
620                 /* nothing */
621                 break;
622         }
623 
624         /* check if current dwc3 is on simulation board */
625         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
626                 dev_info(dwc->dev, "Running with FPGA optmizations\n");
627                 dwc->is_fpga = true;
628         }
629 
630         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
631                         "disable_scramble cannot be used on non-FPGA builds\n");
632 
633         if (dwc->disable_scramble_quirk && dwc->is_fpga)
634                 reg |= DWC3_GCTL_DISSCRAMBLE;
635         else
636                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
637 
638         if (dwc->u2exit_lfps_quirk)
639                 reg |= DWC3_GCTL_U2EXIT_LFPS;
640 
641         /*
642          * WORKAROUND: DWC3 revisions <1.90a have a bug
643          * where the device can fail to connect at SuperSpeed
644          * and falls back to high-speed mode which causes
645          * the device to enter a Connect/Disconnect loop
646          */
647         if (dwc->revision < DWC3_REVISION_190A)
648                 reg |= DWC3_GCTL_U2RSTECN;
649 
650         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
651 }
652 
653 /**
654  * dwc3_core_init - Low-level initialization of DWC3 Core
655  * @dwc: Pointer to our controller context structure
656  *
657  * Returns 0 on success otherwise negative errno.
658  */
659 static int dwc3_core_init(struct dwc3 *dwc)
660 {
661         u32                     reg;
662         int                     ret;
663 
664         if (!dwc3_core_is_valid(dwc)) {
665                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
666                 ret = -ENODEV;
667                 goto err0;
668         }
669 
670         /*
671          * Write Linux Version Code to our GUID register so it's easy to figure
672          * out which kernel version a bug was found.
673          */
674         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
675 
676         /* Handle USB2.0-only core configuration */
677         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
678                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
679                 if (dwc->maximum_speed == USB_SPEED_SUPER)
680                         dwc->maximum_speed = USB_SPEED_HIGH;
681         }
682 
683         ret = dwc3_core_soft_reset(dwc);
684         if (ret)
685                 goto err0;
686 
687         ret = dwc3_phy_setup(dwc);
688         if (ret)
689                 goto err0;
690 
691         dwc3_core_setup_global_control(dwc);
692         dwc3_core_num_eps(dwc);
693 
694         ret = dwc3_setup_scratch_buffers(dwc);
695         if (ret)
696                 goto err1;
697 
698         /* Adjust Frame Length */
699         dwc3_frame_length_adjustment(dwc);
700 
701         usb_phy_set_suspend(dwc->usb2_phy, 0);
702         usb_phy_set_suspend(dwc->usb3_phy, 0);
703         ret = phy_power_on(dwc->usb2_generic_phy);
704         if (ret < 0)
705                 goto err2;
706 
707         ret = phy_power_on(dwc->usb3_generic_phy);
708         if (ret < 0)
709                 goto err3;
710 
711         ret = dwc3_event_buffers_setup(dwc);
712         if (ret) {
713                 dev_err(dwc->dev, "failed to setup event buffers\n");
714                 goto err4;
715         }
716 
717         switch (dwc->dr_mode) {
718         case USB_DR_MODE_PERIPHERAL:
719                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
720                 break;
721         case USB_DR_MODE_HOST:
722                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
723                 break;
724         case USB_DR_MODE_OTG:
725                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
726                 break;
727         default:
728                 dev_warn(dwc->dev, "Unsupported mode %d\n", dwc->dr_mode);
729                 break;
730         }
731 
732         /*
733          * ENDXFER polling is available on version 3.10a and later of
734          * the DWC_usb3 controller. It is NOT available in the
735          * DWC_usb31 controller.
736          */
737         if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
738                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
739                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
740                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
741         }
742 
743         /*
744          * Enable hardware control of sending remote wakeup in HS when
745          * the device is in the L1 state.
746          */
747         if (dwc->revision >= DWC3_REVISION_290A) {
748                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
749                 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
750                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
751         }
752 
753         return 0;
754 
755 err4:
756         phy_power_off(dwc->usb3_generic_phy);
757 
758 err3:
759         phy_power_off(dwc->usb2_generic_phy);
760 
761 err2:
762         usb_phy_set_suspend(dwc->usb2_phy, 1);
763         usb_phy_set_suspend(dwc->usb3_phy, 1);
764 
765 err1:
766         usb_phy_shutdown(dwc->usb2_phy);
767         usb_phy_shutdown(dwc->usb3_phy);
768         phy_exit(dwc->usb2_generic_phy);
769         phy_exit(dwc->usb3_generic_phy);
770 
771 err0:
772         return ret;
773 }
774 
775 static int dwc3_core_get_phy(struct dwc3 *dwc)
776 {
777         struct device           *dev = dwc->dev;
778         struct device_node      *node = dev->of_node;
779         int ret;
780 
781         if (node) {
782                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
783                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
784         } else {
785                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
786                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
787         }
788 
789         if (IS_ERR(dwc->usb2_phy)) {
790                 ret = PTR_ERR(dwc->usb2_phy);
791                 if (ret == -ENXIO || ret == -ENODEV) {
792                         dwc->usb2_phy = NULL;
793                 } else if (ret == -EPROBE_DEFER) {
794                         return ret;
795                 } else {
796                         dev_err(dev, "no usb2 phy configured\n");
797                         return ret;
798                 }
799         }
800 
801         if (IS_ERR(dwc->usb3_phy)) {
802                 ret = PTR_ERR(dwc->usb3_phy);
803                 if (ret == -ENXIO || ret == -ENODEV) {
804                         dwc->usb3_phy = NULL;
805                 } else if (ret == -EPROBE_DEFER) {
806                         return ret;
807                 } else {
808                         dev_err(dev, "no usb3 phy configured\n");
809                         return ret;
810                 }
811         }
812 
813         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
814         if (IS_ERR(dwc->usb2_generic_phy)) {
815                 ret = PTR_ERR(dwc->usb2_generic_phy);
816                 if (ret == -ENOSYS || ret == -ENODEV) {
817                         dwc->usb2_generic_phy = NULL;
818                 } else if (ret == -EPROBE_DEFER) {
819                         return ret;
820                 } else {
821                         dev_err(dev, "no usb2 phy configured\n");
822                         return ret;
823                 }
824         }
825 
826         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
827         if (IS_ERR(dwc->usb3_generic_phy)) {
828                 ret = PTR_ERR(dwc->usb3_generic_phy);
829                 if (ret == -ENOSYS || ret == -ENODEV) {
830                         dwc->usb3_generic_phy = NULL;
831                 } else if (ret == -EPROBE_DEFER) {
832                         return ret;
833                 } else {
834                         dev_err(dev, "no usb3 phy configured\n");
835                         return ret;
836                 }
837         }
838 
839         return 0;
840 }
841 
842 static int dwc3_core_init_mode(struct dwc3 *dwc)
843 {
844         struct device *dev = dwc->dev;
845         int ret;
846 
847         switch (dwc->dr_mode) {
848         case USB_DR_MODE_PERIPHERAL:
849                 ret = dwc3_gadget_init(dwc);
850                 if (ret) {
851                         if (ret != -EPROBE_DEFER)
852                                 dev_err(dev, "failed to initialize gadget\n");
853                         return ret;
854                 }
855                 break;
856         case USB_DR_MODE_HOST:
857                 ret = dwc3_host_init(dwc);
858                 if (ret) {
859                         if (ret != -EPROBE_DEFER)
860                                 dev_err(dev, "failed to initialize host\n");
861                         return ret;
862                 }
863                 break;
864         case USB_DR_MODE_OTG:
865                 ret = dwc3_host_init(dwc);
866                 if (ret) {
867                         if (ret != -EPROBE_DEFER)
868                                 dev_err(dev, "failed to initialize host\n");
869                         return ret;
870                 }
871 
872                 ret = dwc3_gadget_init(dwc);
873                 if (ret) {
874                         if (ret != -EPROBE_DEFER)
875                                 dev_err(dev, "failed to initialize gadget\n");
876                         return ret;
877                 }
878                 break;
879         default:
880                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
881                 return -EINVAL;
882         }
883 
884         return 0;
885 }
886 
887 static void dwc3_core_exit_mode(struct dwc3 *dwc)
888 {
889         switch (dwc->dr_mode) {
890         case USB_DR_MODE_PERIPHERAL:
891                 dwc3_gadget_exit(dwc);
892                 break;
893         case USB_DR_MODE_HOST:
894                 dwc3_host_exit(dwc);
895                 break;
896         case USB_DR_MODE_OTG:
897                 dwc3_host_exit(dwc);
898                 dwc3_gadget_exit(dwc);
899                 break;
900         default:
901                 /* do nothing */
902                 break;
903         }
904 }
905 
906 static void dwc3_get_properties(struct dwc3 *dwc)
907 {
908         struct device           *dev = dwc->dev;
909         u8                      lpm_nyet_threshold;
910         u8                      tx_de_emphasis;
911         u8                      hird_threshold;
912 
913         /* default to highest possible threshold */
914         lpm_nyet_threshold = 0xff;
915 
916         /* default to -3.5dB de-emphasis */
917         tx_de_emphasis = 1;
918 
919         /*
920          * default to assert utmi_sleep_n and use maximum allowed HIRD
921          * threshold value of 0b1100
922          */
923         hird_threshold = 12;
924 
925         dwc->maximum_speed = usb_get_maximum_speed(dev);
926         dwc->dr_mode = usb_get_dr_mode(dev);
927         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
928 
929         dwc->sysdev_is_parent = device_property_read_bool(dev,
930                                 "linux,sysdev_is_parent");
931         if (dwc->sysdev_is_parent)
932                 dwc->sysdev = dwc->dev->parent;
933         else
934                 dwc->sysdev = dwc->dev;
935 
936         dwc->has_lpm_erratum = device_property_read_bool(dev,
937                                 "snps,has-lpm-erratum");
938         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
939                                 &lpm_nyet_threshold);
940         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
941                                 "snps,is-utmi-l1-suspend");
942         device_property_read_u8(dev, "snps,hird-threshold",
943                                 &hird_threshold);
944         dwc->usb3_lpm_capable = device_property_read_bool(dev,
945                                 "snps,usb3_lpm_capable");
946 
947         dwc->disable_scramble_quirk = device_property_read_bool(dev,
948                                 "snps,disable_scramble_quirk");
949         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
950                                 "snps,u2exit_lfps_quirk");
951         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
952                                 "snps,u2ss_inp3_quirk");
953         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
954                                 "snps,req_p1p2p3_quirk");
955         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
956                                 "snps,del_p1p2p3_quirk");
957         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
958                                 "snps,del_phy_power_chg_quirk");
959         dwc->lfps_filter_quirk = device_property_read_bool(dev,
960                                 "snps,lfps_filter_quirk");
961         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
962                                 "snps,rx_detect_poll_quirk");
963         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
964                                 "snps,dis_u3_susphy_quirk");
965         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
966                                 "snps,dis_u2_susphy_quirk");
967         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
968                                 "snps,dis_enblslpm_quirk");
969         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
970                                 "snps,dis_rxdet_inp3_quirk");
971         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
972                                 "snps,dis-u2-freeclk-exists-quirk");
973         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
974                                 "snps,dis-del-phy-power-chg-quirk");
975 
976         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
977                                 "snps,tx_de_emphasis_quirk");
978         device_property_read_u8(dev, "snps,tx_de_emphasis",
979                                 &tx_de_emphasis);
980         device_property_read_string(dev, "snps,hsphy_interface",
981                                     &dwc->hsphy_interface);
982         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
983                                  &dwc->fladj);
984 
985         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
986         dwc->tx_de_emphasis = tx_de_emphasis;
987 
988         dwc->hird_threshold = hird_threshold
989                 | (dwc->is_utmi_l1_suspend << 4);
990 
991         dwc->imod_interval = 0;
992 }
993 
994 /* check whether the core supports IMOD */
995 bool dwc3_has_imod(struct dwc3 *dwc)
996 {
997         return ((dwc3_is_usb3(dwc) &&
998                  dwc->revision >= DWC3_REVISION_300A) ||
999                 (dwc3_is_usb31(dwc) &&
1000                  dwc->revision >= DWC3_USB31_REVISION_120A));
1001 }
1002 
1003 static void dwc3_check_params(struct dwc3 *dwc)
1004 {
1005         struct device *dev = dwc->dev;
1006 
1007         /* Check for proper value of imod_interval */
1008         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1009                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1010                 dwc->imod_interval = 0;
1011         }
1012 
1013         /*
1014          * Workaround for STAR 9000961433 which affects only version
1015          * 3.00a of the DWC_usb3 core. This prevents the controller
1016          * interrupt from being masked while handling events. IMOD
1017          * allows us to work around this issue. Enable it for the
1018          * affected version.
1019          */
1020         if (!dwc->imod_interval &&
1021             (dwc->revision == DWC3_REVISION_300A))
1022                 dwc->imod_interval = 1;
1023 
1024         /* Check the maximum_speed parameter */
1025         switch (dwc->maximum_speed) {
1026         case USB_SPEED_LOW:
1027         case USB_SPEED_FULL:
1028         case USB_SPEED_HIGH:
1029         case USB_SPEED_SUPER:
1030         case USB_SPEED_SUPER_PLUS:
1031                 break;
1032         default:
1033                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1034                         dwc->maximum_speed);
1035                 /* fall through */
1036         case USB_SPEED_UNKNOWN:
1037                 /* default to superspeed */
1038                 dwc->maximum_speed = USB_SPEED_SUPER;
1039 
1040                 /*
1041                  * default to superspeed plus if we are capable.
1042                  */
1043                 if (dwc3_is_usb31(dwc) &&
1044                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1045                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1046                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1047 
1048                 break;
1049         }
1050 }
1051 
1052 static int dwc3_probe(struct platform_device *pdev)
1053 {
1054         struct device           *dev = &pdev->dev;
1055         struct resource         *res;
1056         struct dwc3             *dwc;
1057 
1058         int                     ret;
1059 
1060         void __iomem            *regs;
1061 
1062         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1063         if (!dwc)
1064                 return -ENOMEM;
1065 
1066         dwc->dev = dev;
1067 
1068         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1069         if (!res) {
1070                 dev_err(dev, "missing memory resource\n");
1071                 return -ENODEV;
1072         }
1073 
1074         dwc->xhci_resources[0].start = res->start;
1075         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1076                                         DWC3_XHCI_REGS_END;
1077         dwc->xhci_resources[0].flags = res->flags;
1078         dwc->xhci_resources[0].name = res->name;
1079 
1080         res->start += DWC3_GLOBALS_REGS_START;
1081 
1082         /*
1083          * Request memory region but exclude xHCI regs,
1084          * since it will be requested by the xhci-plat driver.
1085          */
1086         regs = devm_ioremap_resource(dev, res);
1087         if (IS_ERR(regs)) {
1088                 ret = PTR_ERR(regs);
1089                 goto err0;
1090         }
1091 
1092         dwc->regs       = regs;
1093         dwc->regs_size  = resource_size(res);
1094 
1095         dwc3_get_properties(dwc);
1096 
1097         platform_set_drvdata(pdev, dwc);
1098         dwc3_cache_hwparams(dwc);
1099 
1100         ret = dwc3_core_get_phy(dwc);
1101         if (ret)
1102                 goto err0;
1103 
1104         spin_lock_init(&dwc->lock);
1105 
1106         pm_runtime_set_active(dev);
1107         pm_runtime_use_autosuspend(dev);
1108         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1109         pm_runtime_enable(dev);
1110         ret = pm_runtime_get_sync(dev);
1111         if (ret < 0)
1112                 goto err1;
1113 
1114         pm_runtime_forbid(dev);
1115 
1116         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1117         if (ret) {
1118                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1119                 ret = -ENOMEM;
1120                 goto err2;
1121         }
1122 
1123         ret = dwc3_get_dr_mode(dwc);
1124         if (ret)
1125                 goto err3;
1126 
1127         ret = dwc3_alloc_scratch_buffers(dwc);
1128         if (ret)
1129                 goto err3;
1130 
1131         ret = dwc3_core_init(dwc);
1132         if (ret) {
1133                 dev_err(dev, "failed to initialize core\n");
1134                 goto err4;
1135         }
1136 
1137         dwc3_check_params(dwc);
1138 
1139         ret = dwc3_core_init_mode(dwc);
1140         if (ret)
1141                 goto err5;
1142 
1143         dwc3_debugfs_init(dwc);
1144         pm_runtime_put(dev);
1145 
1146         return 0;
1147 
1148 err5:
1149         dwc3_event_buffers_cleanup(dwc);
1150 
1151 err4:
1152         dwc3_free_scratch_buffers(dwc);
1153 
1154 err3:
1155         dwc3_free_event_buffers(dwc);
1156         dwc3_ulpi_exit(dwc);
1157 
1158 err2:
1159         pm_runtime_allow(&pdev->dev);
1160 
1161 err1:
1162         pm_runtime_put_sync(&pdev->dev);
1163         pm_runtime_disable(&pdev->dev);
1164 
1165 err0:
1166         /*
1167          * restore res->start back to its original value so that, in case the
1168          * probe is deferred, we don't end up getting error in request the
1169          * memory region the next time probe is called.
1170          */
1171         res->start -= DWC3_GLOBALS_REGS_START;
1172 
1173         return ret;
1174 }
1175 
1176 static int dwc3_remove(struct platform_device *pdev)
1177 {
1178         struct dwc3     *dwc = platform_get_drvdata(pdev);
1179         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1180 
1181         pm_runtime_get_sync(&pdev->dev);
1182         /*
1183          * restore res->start back to its original value so that, in case the
1184          * probe is deferred, we don't end up getting error in request the
1185          * memory region the next time probe is called.
1186          */
1187         res->start -= DWC3_GLOBALS_REGS_START;
1188 
1189         dwc3_debugfs_exit(dwc);
1190         dwc3_core_exit_mode(dwc);
1191 
1192         dwc3_core_exit(dwc);
1193         dwc3_ulpi_exit(dwc);
1194 
1195         pm_runtime_put_sync(&pdev->dev);
1196         pm_runtime_allow(&pdev->dev);
1197         pm_runtime_disable(&pdev->dev);
1198 
1199         dwc3_free_event_buffers(dwc);
1200         dwc3_free_scratch_buffers(dwc);
1201 
1202         return 0;
1203 }
1204 
1205 #ifdef CONFIG_PM
1206 static int dwc3_suspend_common(struct dwc3 *dwc)
1207 {
1208         unsigned long   flags;
1209 
1210         switch (dwc->dr_mode) {
1211         case USB_DR_MODE_PERIPHERAL:
1212         case USB_DR_MODE_OTG:
1213                 spin_lock_irqsave(&dwc->lock, flags);
1214                 dwc3_gadget_suspend(dwc);
1215                 spin_unlock_irqrestore(&dwc->lock, flags);
1216                 break;
1217         case USB_DR_MODE_HOST:
1218         default:
1219                 /* do nothing */
1220                 break;
1221         }
1222 
1223         dwc3_core_exit(dwc);
1224 
1225         return 0;
1226 }
1227 
1228 static int dwc3_resume_common(struct dwc3 *dwc)
1229 {
1230         unsigned long   flags;
1231         int             ret;
1232 
1233         ret = dwc3_core_init(dwc);
1234         if (ret)
1235                 return ret;
1236 
1237         switch (dwc->dr_mode) {
1238         case USB_DR_MODE_PERIPHERAL:
1239         case USB_DR_MODE_OTG:
1240                 spin_lock_irqsave(&dwc->lock, flags);
1241                 dwc3_gadget_resume(dwc);
1242                 spin_unlock_irqrestore(&dwc->lock, flags);
1243                 /* FALLTHROUGH */
1244         case USB_DR_MODE_HOST:
1245         default:
1246                 /* do nothing */
1247                 break;
1248         }
1249 
1250         return 0;
1251 }
1252 
1253 static int dwc3_runtime_checks(struct dwc3 *dwc)
1254 {
1255         switch (dwc->dr_mode) {
1256         case USB_DR_MODE_PERIPHERAL:
1257         case USB_DR_MODE_OTG:
1258                 if (dwc->connected)
1259                         return -EBUSY;
1260                 break;
1261         case USB_DR_MODE_HOST:
1262         default:
1263                 /* do nothing */
1264                 break;
1265         }
1266 
1267         return 0;
1268 }
1269 
1270 static int dwc3_runtime_suspend(struct device *dev)
1271 {
1272         struct dwc3     *dwc = dev_get_drvdata(dev);
1273         int             ret;
1274 
1275         if (dwc3_runtime_checks(dwc))
1276                 return -EBUSY;
1277 
1278         ret = dwc3_suspend_common(dwc);
1279         if (ret)
1280                 return ret;
1281 
1282         device_init_wakeup(dev, true);
1283 
1284         return 0;
1285 }
1286 
1287 static int dwc3_runtime_resume(struct device *dev)
1288 {
1289         struct dwc3     *dwc = dev_get_drvdata(dev);
1290         int             ret;
1291 
1292         device_init_wakeup(dev, false);
1293 
1294         ret = dwc3_resume_common(dwc);
1295         if (ret)
1296                 return ret;
1297 
1298         switch (dwc->dr_mode) {
1299         case USB_DR_MODE_PERIPHERAL:
1300         case USB_DR_MODE_OTG:
1301                 dwc3_gadget_process_pending_events(dwc);
1302                 break;
1303         case USB_DR_MODE_HOST:
1304         default:
1305                 /* do nothing */
1306                 break;
1307         }
1308 
1309         pm_runtime_mark_last_busy(dev);
1310         pm_runtime_put(dev);
1311 
1312         return 0;
1313 }
1314 
1315 static int dwc3_runtime_idle(struct device *dev)
1316 {
1317         struct dwc3     *dwc = dev_get_drvdata(dev);
1318 
1319         switch (dwc->dr_mode) {
1320         case USB_DR_MODE_PERIPHERAL:
1321         case USB_DR_MODE_OTG:
1322                 if (dwc3_runtime_checks(dwc))
1323                         return -EBUSY;
1324                 break;
1325         case USB_DR_MODE_HOST:
1326         default:
1327                 /* do nothing */
1328                 break;
1329         }
1330 
1331         pm_runtime_mark_last_busy(dev);
1332         pm_runtime_autosuspend(dev);
1333 
1334         return 0;
1335 }
1336 #endif /* CONFIG_PM */
1337 
1338 #ifdef CONFIG_PM_SLEEP
1339 static int dwc3_suspend(struct device *dev)
1340 {
1341         struct dwc3     *dwc = dev_get_drvdata(dev);
1342         int             ret;
1343 
1344         ret = dwc3_suspend_common(dwc);
1345         if (ret)
1346                 return ret;
1347 
1348         pinctrl_pm_select_sleep_state(dev);
1349 
1350         return 0;
1351 }
1352 
1353 static int dwc3_resume(struct device *dev)
1354 {
1355         struct dwc3     *dwc = dev_get_drvdata(dev);
1356         int             ret;
1357 
1358         pinctrl_pm_select_default_state(dev);
1359 
1360         ret = dwc3_resume_common(dwc);
1361         if (ret)
1362                 return ret;
1363 
1364         pm_runtime_disable(dev);
1365         pm_runtime_set_active(dev);
1366         pm_runtime_enable(dev);
1367 
1368         return 0;
1369 }
1370 #endif /* CONFIG_PM_SLEEP */
1371 
1372 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1373         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1374         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1375                         dwc3_runtime_idle)
1376 };
1377 
1378 #ifdef CONFIG_OF
1379 static const struct of_device_id of_dwc3_match[] = {
1380         {
1381                 .compatible = "snps,dwc3"
1382         },
1383         {
1384                 .compatible = "synopsys,dwc3"
1385         },
1386         { },
1387 };
1388 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1389 #endif
1390 
1391 #ifdef CONFIG_ACPI
1392 
1393 #define ACPI_ID_INTEL_BSW       "808622B7"
1394 
1395 static const struct acpi_device_id dwc3_acpi_match[] = {
1396         { ACPI_ID_INTEL_BSW, 0 },
1397         { },
1398 };
1399 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1400 #endif
1401 
1402 static struct platform_driver dwc3_driver = {
1403         .probe          = dwc3_probe,
1404         .remove         = dwc3_remove,
1405         .driver         = {
1406                 .name   = "dwc3",
1407                 .of_match_table = of_match_ptr(of_dwc3_match),
1408                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1409                 .pm     = &dwc3_dev_pm_ops,
1410         },
1411 };
1412 
1413 module_platform_driver(dwc3_driver);
1414 
1415 MODULE_ALIAS("platform:dwc3");
1416 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1417 MODULE_LICENSE("GPL v2");
1418 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
1419 

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