Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/usb/dwc3/core.c

  1 /**
  2  * core.c - DesignWare USB3 DRD Controller Core file
  3  *
  4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5  *
  6  * Authors: Felipe Balbi <balbi@ti.com>,
  7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8  *
  9  * This program is free software: you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2  of
 11  * the License as published by the Free Software Foundation.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 20  */
 21 
 22 #include <linux/module.h>
 23 #include <linux/kernel.h>
 24 #include <linux/slab.h>
 25 #include <linux/spinlock.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/pm_runtime.h>
 28 #include <linux/interrupt.h>
 29 #include <linux/ioport.h>
 30 #include <linux/io.h>
 31 #include <linux/list.h>
 32 #include <linux/delay.h>
 33 #include <linux/dma-mapping.h>
 34 #include <linux/of.h>
 35 
 36 #include <linux/usb/ch9.h>
 37 #include <linux/usb/gadget.h>
 38 #include <linux/usb/of.h>
 39 #include <linux/usb/otg.h>
 40 
 41 #include "platform_data.h"
 42 #include "core.h"
 43 #include "gadget.h"
 44 #include "io.h"
 45 
 46 #include "debug.h"
 47 
 48 /* -------------------------------------------------------------------------- */
 49 
 50 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 51 {
 52         u32 reg;
 53 
 54         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 55         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 56         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 57         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 58 }
 59 
 60 /**
 61  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 62  * @dwc: pointer to our context structure
 63  */
 64 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 65 {
 66         u32             reg;
 67         int             ret;
 68 
 69         /* Before Resetting PHY, put Core in Reset */
 70         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 71         reg |= DWC3_GCTL_CORESOFTRESET;
 72         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 73 
 74         /* Assert USB3 PHY reset */
 75         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 76         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
 77         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 78 
 79         /* Assert USB2 PHY reset */
 80         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 81         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
 82         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 83 
 84         usb_phy_init(dwc->usb2_phy);
 85         usb_phy_init(dwc->usb3_phy);
 86         ret = phy_init(dwc->usb2_generic_phy);
 87         if (ret < 0)
 88                 return ret;
 89 
 90         ret = phy_init(dwc->usb3_generic_phy);
 91         if (ret < 0) {
 92                 phy_exit(dwc->usb2_generic_phy);
 93                 return ret;
 94         }
 95         mdelay(100);
 96 
 97         /* Clear USB3 PHY reset */
 98         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 99         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
100         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
101 
102         /* Clear USB2 PHY reset */
103         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
104         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
105         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
106 
107         mdelay(100);
108 
109         /* After PHYs are stable we can take Core out of reset state */
110         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
111         reg &= ~DWC3_GCTL_CORESOFTRESET;
112         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
113 
114         return 0;
115 }
116 
117 /**
118  * dwc3_free_one_event_buffer - Frees one event buffer
119  * @dwc: Pointer to our controller context structure
120  * @evt: Pointer to event buffer to be freed
121  */
122 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
123                 struct dwc3_event_buffer *evt)
124 {
125         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
126 }
127 
128 /**
129  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
130  * @dwc: Pointer to our controller context structure
131  * @length: size of the event buffer
132  *
133  * Returns a pointer to the allocated event buffer structure on success
134  * otherwise ERR_PTR(errno).
135  */
136 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
137                 unsigned length)
138 {
139         struct dwc3_event_buffer        *evt;
140 
141         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
142         if (!evt)
143                 return ERR_PTR(-ENOMEM);
144 
145         evt->dwc        = dwc;
146         evt->length     = length;
147         evt->buf        = dma_alloc_coherent(dwc->dev, length,
148                         &evt->dma, GFP_KERNEL);
149         if (!evt->buf)
150                 return ERR_PTR(-ENOMEM);
151 
152         return evt;
153 }
154 
155 /**
156  * dwc3_free_event_buffers - frees all allocated event buffers
157  * @dwc: Pointer to our controller context structure
158  */
159 static void dwc3_free_event_buffers(struct dwc3 *dwc)
160 {
161         struct dwc3_event_buffer        *evt;
162         int i;
163 
164         for (i = 0; i < dwc->num_event_buffers; i++) {
165                 evt = dwc->ev_buffs[i];
166                 if (evt)
167                         dwc3_free_one_event_buffer(dwc, evt);
168         }
169 }
170 
171 /**
172  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
173  * @dwc: pointer to our controller context structure
174  * @length: size of event buffer
175  *
176  * Returns 0 on success otherwise negative errno. In the error case, dwc
177  * may contain some buffers allocated but not all which were requested.
178  */
179 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
180 {
181         int                     num;
182         int                     i;
183 
184         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
185         dwc->num_event_buffers = num;
186 
187         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
188                         GFP_KERNEL);
189         if (!dwc->ev_buffs) {
190                 dev_err(dwc->dev, "can't allocate event buffers array\n");
191                 return -ENOMEM;
192         }
193 
194         for (i = 0; i < num; i++) {
195                 struct dwc3_event_buffer        *evt;
196 
197                 evt = dwc3_alloc_one_event_buffer(dwc, length);
198                 if (IS_ERR(evt)) {
199                         dev_err(dwc->dev, "can't allocate event buffer\n");
200                         return PTR_ERR(evt);
201                 }
202                 dwc->ev_buffs[i] = evt;
203         }
204 
205         return 0;
206 }
207 
208 /**
209  * dwc3_event_buffers_setup - setup our allocated event buffers
210  * @dwc: pointer to our controller context structure
211  *
212  * Returns 0 on success otherwise negative errno.
213  */
214 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
215 {
216         struct dwc3_event_buffer        *evt;
217         int                             n;
218 
219         for (n = 0; n < dwc->num_event_buffers; n++) {
220                 evt = dwc->ev_buffs[n];
221                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
222                                 evt->buf, (unsigned long long) evt->dma,
223                                 evt->length);
224 
225                 evt->lpos = 0;
226 
227                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
228                                 lower_32_bits(evt->dma));
229                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
230                                 upper_32_bits(evt->dma));
231                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
232                                 DWC3_GEVNTSIZ_SIZE(evt->length));
233                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
234         }
235 
236         return 0;
237 }
238 
239 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
240 {
241         struct dwc3_event_buffer        *evt;
242         int                             n;
243 
244         for (n = 0; n < dwc->num_event_buffers; n++) {
245                 evt = dwc->ev_buffs[n];
246 
247                 evt->lpos = 0;
248 
249                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
250                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
251                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
252                                 | DWC3_GEVNTSIZ_SIZE(0));
253                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
254         }
255 }
256 
257 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
258 {
259         if (!dwc->has_hibernation)
260                 return 0;
261 
262         if (!dwc->nr_scratch)
263                 return 0;
264 
265         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
266                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
267         if (!dwc->scratchbuf)
268                 return -ENOMEM;
269 
270         return 0;
271 }
272 
273 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
274 {
275         dma_addr_t scratch_addr;
276         u32 param;
277         int ret;
278 
279         if (!dwc->has_hibernation)
280                 return 0;
281 
282         if (!dwc->nr_scratch)
283                 return 0;
284 
285          /* should never fall here */
286         if (!WARN_ON(dwc->scratchbuf))
287                 return 0;
288 
289         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
290                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
291                         DMA_BIDIRECTIONAL);
292         if (dma_mapping_error(dwc->dev, scratch_addr)) {
293                 dev_err(dwc->dev, "failed to map scratch buffer\n");
294                 ret = -EFAULT;
295                 goto err0;
296         }
297 
298         dwc->scratch_addr = scratch_addr;
299 
300         param = lower_32_bits(scratch_addr);
301 
302         ret = dwc3_send_gadget_generic_command(dwc,
303                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
304         if (ret < 0)
305                 goto err1;
306 
307         param = upper_32_bits(scratch_addr);
308 
309         ret = dwc3_send_gadget_generic_command(dwc,
310                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
311         if (ret < 0)
312                 goto err1;
313 
314         return 0;
315 
316 err1:
317         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
318                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
319 
320 err0:
321         return ret;
322 }
323 
324 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
325 {
326         if (!dwc->has_hibernation)
327                 return;
328 
329         if (!dwc->nr_scratch)
330                 return;
331 
332          /* should never fall here */
333         if (!WARN_ON(dwc->scratchbuf))
334                 return;
335 
336         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
337                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
338         kfree(dwc->scratchbuf);
339 }
340 
341 static void dwc3_core_num_eps(struct dwc3 *dwc)
342 {
343         struct dwc3_hwparams    *parms = &dwc->hwparams;
344 
345         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
346         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
347 
348         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
349                         dwc->num_in_eps, dwc->num_out_eps);
350 }
351 
352 static void dwc3_cache_hwparams(struct dwc3 *dwc)
353 {
354         struct dwc3_hwparams    *parms = &dwc->hwparams;
355 
356         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
357         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
358         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
359         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
360         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
361         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
362         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
363         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
364         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
365 }
366 
367 /**
368  * dwc3_core_init - Low-level initialization of DWC3 Core
369  * @dwc: Pointer to our controller context structure
370  *
371  * Returns 0 on success otherwise negative errno.
372  */
373 static int dwc3_core_init(struct dwc3 *dwc)
374 {
375         unsigned long           timeout;
376         u32                     hwparams4 = dwc->hwparams.hwparams4;
377         u32                     reg;
378         int                     ret;
379 
380         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
381         /* This should read as U3 followed by revision number */
382         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
383                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
384                 ret = -ENODEV;
385                 goto err0;
386         }
387         dwc->revision = reg;
388 
389         /* Handle USB2.0-only core configuration */
390         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
391                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
392                 if (dwc->maximum_speed == USB_SPEED_SUPER)
393                         dwc->maximum_speed = USB_SPEED_HIGH;
394         }
395 
396         /* issue device SoftReset too */
397         timeout = jiffies + msecs_to_jiffies(500);
398         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
399         do {
400                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
401                 if (!(reg & DWC3_DCTL_CSFTRST))
402                         break;
403 
404                 if (time_after(jiffies, timeout)) {
405                         dev_err(dwc->dev, "Reset Timed Out\n");
406                         ret = -ETIMEDOUT;
407                         goto err0;
408                 }
409 
410                 cpu_relax();
411         } while (true);
412 
413         ret = dwc3_core_soft_reset(dwc);
414         if (ret)
415                 goto err0;
416 
417         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
418         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
419         reg &= ~DWC3_GCTL_DISSCRAMBLE;
420 
421         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
422         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
423                 /**
424                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
425                  * issue which would cause xHCI compliance tests to fail.
426                  *
427                  * Because of that we cannot enable clock gating on such
428                  * configurations.
429                  *
430                  * Refers to:
431                  *
432                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
433                  * SOF/ITP Mode Used
434                  */
435                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
436                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
437                                 (dwc->revision >= DWC3_REVISION_210A &&
438                                 dwc->revision <= DWC3_REVISION_250A))
439                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
440                 else
441                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
442                 break;
443         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
444                 /* enable hibernation here */
445                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
446                 break;
447         default:
448                 dev_dbg(dwc->dev, "No power optimization available\n");
449         }
450 
451         /*
452          * WORKAROUND: DWC3 revisions <1.90a have a bug
453          * where the device can fail to connect at SuperSpeed
454          * and falls back to high-speed mode which causes
455          * the device to enter a Connect/Disconnect loop
456          */
457         if (dwc->revision < DWC3_REVISION_190A)
458                 reg |= DWC3_GCTL_U2RSTECN;
459 
460         dwc3_core_num_eps(dwc);
461 
462         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
463 
464         ret = dwc3_alloc_scratch_buffers(dwc);
465         if (ret)
466                 goto err1;
467 
468         ret = dwc3_setup_scratch_buffers(dwc);
469         if (ret)
470                 goto err2;
471 
472         return 0;
473 
474 err2:
475         dwc3_free_scratch_buffers(dwc);
476 
477 err1:
478         usb_phy_shutdown(dwc->usb2_phy);
479         usb_phy_shutdown(dwc->usb3_phy);
480         phy_exit(dwc->usb2_generic_phy);
481         phy_exit(dwc->usb3_generic_phy);
482 
483 err0:
484         return ret;
485 }
486 
487 static void dwc3_core_exit(struct dwc3 *dwc)
488 {
489         dwc3_free_scratch_buffers(dwc);
490         usb_phy_shutdown(dwc->usb2_phy);
491         usb_phy_shutdown(dwc->usb3_phy);
492         phy_exit(dwc->usb2_generic_phy);
493         phy_exit(dwc->usb3_generic_phy);
494 }
495 
496 static int dwc3_core_get_phy(struct dwc3 *dwc)
497 {
498         struct device           *dev = dwc->dev;
499         struct device_node      *node = dev->of_node;
500         int ret;
501 
502         if (node) {
503                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
504                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
505         } else {
506                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
507                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
508         }
509 
510         if (IS_ERR(dwc->usb2_phy)) {
511                 ret = PTR_ERR(dwc->usb2_phy);
512                 if (ret == -ENXIO || ret == -ENODEV) {
513                         dwc->usb2_phy = NULL;
514                 } else if (ret == -EPROBE_DEFER) {
515                         return ret;
516                 } else {
517                         dev_err(dev, "no usb2 phy configured\n");
518                         return ret;
519                 }
520         }
521 
522         if (IS_ERR(dwc->usb3_phy)) {
523                 ret = PTR_ERR(dwc->usb3_phy);
524                 if (ret == -ENXIO || ret == -ENODEV) {
525                         dwc->usb3_phy = NULL;
526                 } else if (ret == -EPROBE_DEFER) {
527                         return ret;
528                 } else {
529                         dev_err(dev, "no usb3 phy configured\n");
530                         return ret;
531                 }
532         }
533 
534         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
535         if (IS_ERR(dwc->usb2_generic_phy)) {
536                 ret = PTR_ERR(dwc->usb2_generic_phy);
537                 if (ret == -ENOSYS || ret == -ENODEV) {
538                         dwc->usb2_generic_phy = NULL;
539                 } else if (ret == -EPROBE_DEFER) {
540                         return ret;
541                 } else {
542                         dev_err(dev, "no usb2 phy configured\n");
543                         return ret;
544                 }
545         }
546 
547         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
548         if (IS_ERR(dwc->usb3_generic_phy)) {
549                 ret = PTR_ERR(dwc->usb3_generic_phy);
550                 if (ret == -ENOSYS || ret == -ENODEV) {
551                         dwc->usb3_generic_phy = NULL;
552                 } else if (ret == -EPROBE_DEFER) {
553                         return ret;
554                 } else {
555                         dev_err(dev, "no usb3 phy configured\n");
556                         return ret;
557                 }
558         }
559 
560         return 0;
561 }
562 
563 static int dwc3_core_init_mode(struct dwc3 *dwc)
564 {
565         struct device *dev = dwc->dev;
566         int ret;
567 
568         switch (dwc->dr_mode) {
569         case USB_DR_MODE_PERIPHERAL:
570                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
571                 ret = dwc3_gadget_init(dwc);
572                 if (ret) {
573                         dev_err(dev, "failed to initialize gadget\n");
574                         return ret;
575                 }
576                 break;
577         case USB_DR_MODE_HOST:
578                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
579                 ret = dwc3_host_init(dwc);
580                 if (ret) {
581                         dev_err(dev, "failed to initialize host\n");
582                         return ret;
583                 }
584                 break;
585         case USB_DR_MODE_OTG:
586                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
587                 ret = dwc3_host_init(dwc);
588                 if (ret) {
589                         dev_err(dev, "failed to initialize host\n");
590                         return ret;
591                 }
592 
593                 ret = dwc3_gadget_init(dwc);
594                 if (ret) {
595                         dev_err(dev, "failed to initialize gadget\n");
596                         return ret;
597                 }
598                 break;
599         default:
600                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
601                 return -EINVAL;
602         }
603 
604         return 0;
605 }
606 
607 static void dwc3_core_exit_mode(struct dwc3 *dwc)
608 {
609         switch (dwc->dr_mode) {
610         case USB_DR_MODE_PERIPHERAL:
611                 dwc3_gadget_exit(dwc);
612                 break;
613         case USB_DR_MODE_HOST:
614                 dwc3_host_exit(dwc);
615                 break;
616         case USB_DR_MODE_OTG:
617                 dwc3_host_exit(dwc);
618                 dwc3_gadget_exit(dwc);
619                 break;
620         default:
621                 /* do nothing */
622                 break;
623         }
624 }
625 
626 #define DWC3_ALIGN_MASK         (16 - 1)
627 
628 static int dwc3_probe(struct platform_device *pdev)
629 {
630         struct device           *dev = &pdev->dev;
631         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
632         struct device_node      *node = dev->of_node;
633         struct resource         *res;
634         struct dwc3             *dwc;
635 
636         int                     ret;
637 
638         void __iomem            *regs;
639         void                    *mem;
640 
641         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
642         if (!mem) {
643                 dev_err(dev, "not enough memory\n");
644                 return -ENOMEM;
645         }
646         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
647         dwc->mem = mem;
648         dwc->dev = dev;
649 
650         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
651         if (!res) {
652                 dev_err(dev, "missing IRQ\n");
653                 return -ENODEV;
654         }
655         dwc->xhci_resources[1].start = res->start;
656         dwc->xhci_resources[1].end = res->end;
657         dwc->xhci_resources[1].flags = res->flags;
658         dwc->xhci_resources[1].name = res->name;
659 
660         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
661         if (!res) {
662                 dev_err(dev, "missing memory resource\n");
663                 return -ENODEV;
664         }
665 
666         dwc->xhci_resources[0].start = res->start;
667         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
668                                         DWC3_XHCI_REGS_END;
669         dwc->xhci_resources[0].flags = res->flags;
670         dwc->xhci_resources[0].name = res->name;
671 
672         res->start += DWC3_GLOBALS_REGS_START;
673 
674         /*
675          * Request memory region but exclude xHCI regs,
676          * since it will be requested by the xhci-plat driver.
677          */
678         regs = devm_ioremap_resource(dev, res);
679         if (IS_ERR(regs))
680                 return PTR_ERR(regs);
681 
682         dwc->regs       = regs;
683         dwc->regs_size  = resource_size(res);
684         /*
685          * restore res->start back to its original value so that,
686          * in case the probe is deferred, we don't end up getting error in
687          * request the memory region the next time probe is called.
688          */
689         res->start -= DWC3_GLOBALS_REGS_START;
690 
691         if (node) {
692                 dwc->maximum_speed = of_usb_get_maximum_speed(node);
693 
694                 dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
695                 dwc->dr_mode = of_usb_get_dr_mode(node);
696         } else if (pdata) {
697                 dwc->maximum_speed = pdata->maximum_speed;
698 
699                 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
700                 dwc->dr_mode = pdata->dr_mode;
701         }
702 
703         /* default to superspeed if no maximum_speed passed */
704         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
705                 dwc->maximum_speed = USB_SPEED_SUPER;
706 
707         ret = dwc3_core_get_phy(dwc);
708         if (ret)
709                 return ret;
710 
711         spin_lock_init(&dwc->lock);
712         platform_set_drvdata(pdev, dwc);
713 
714         dev->dma_mask   = dev->parent->dma_mask;
715         dev->dma_parms  = dev->parent->dma_parms;
716         dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
717 
718         pm_runtime_enable(dev);
719         pm_runtime_get_sync(dev);
720         pm_runtime_forbid(dev);
721 
722         dwc3_cache_hwparams(dwc);
723 
724         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
725         if (ret) {
726                 dev_err(dwc->dev, "failed to allocate event buffers\n");
727                 ret = -ENOMEM;
728                 goto err0;
729         }
730 
731         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
732                 dwc->dr_mode = USB_DR_MODE_HOST;
733         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
734                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
735 
736         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
737                 dwc->dr_mode = USB_DR_MODE_OTG;
738 
739         ret = dwc3_core_init(dwc);
740         if (ret) {
741                 dev_err(dev, "failed to initialize core\n");
742                 goto err0;
743         }
744 
745         usb_phy_set_suspend(dwc->usb2_phy, 0);
746         usb_phy_set_suspend(dwc->usb3_phy, 0);
747         ret = phy_power_on(dwc->usb2_generic_phy);
748         if (ret < 0)
749                 goto err1;
750 
751         ret = phy_power_on(dwc->usb3_generic_phy);
752         if (ret < 0)
753                 goto err_usb2phy_power;
754 
755         ret = dwc3_event_buffers_setup(dwc);
756         if (ret) {
757                 dev_err(dwc->dev, "failed to setup event buffers\n");
758                 goto err_usb3phy_power;
759         }
760 
761         ret = dwc3_core_init_mode(dwc);
762         if (ret)
763                 goto err2;
764 
765         ret = dwc3_debugfs_init(dwc);
766         if (ret) {
767                 dev_err(dev, "failed to initialize debugfs\n");
768                 goto err3;
769         }
770 
771         pm_runtime_allow(dev);
772 
773         return 0;
774 
775 err3:
776         dwc3_core_exit_mode(dwc);
777 
778 err2:
779         dwc3_event_buffers_cleanup(dwc);
780 
781 err_usb3phy_power:
782         phy_power_off(dwc->usb3_generic_phy);
783 
784 err_usb2phy_power:
785         phy_power_off(dwc->usb2_generic_phy);
786 
787 err1:
788         usb_phy_set_suspend(dwc->usb2_phy, 1);
789         usb_phy_set_suspend(dwc->usb3_phy, 1);
790         dwc3_core_exit(dwc);
791 
792 err0:
793         dwc3_free_event_buffers(dwc);
794 
795         return ret;
796 }
797 
798 static int dwc3_remove(struct platform_device *pdev)
799 {
800         struct dwc3     *dwc = platform_get_drvdata(pdev);
801 
802         dwc3_debugfs_exit(dwc);
803         dwc3_core_exit_mode(dwc);
804         dwc3_event_buffers_cleanup(dwc);
805         dwc3_free_event_buffers(dwc);
806 
807         usb_phy_set_suspend(dwc->usb2_phy, 1);
808         usb_phy_set_suspend(dwc->usb3_phy, 1);
809         phy_power_off(dwc->usb2_generic_phy);
810         phy_power_off(dwc->usb3_generic_phy);
811 
812         dwc3_core_exit(dwc);
813 
814         pm_runtime_put_sync(&pdev->dev);
815         pm_runtime_disable(&pdev->dev);
816 
817         return 0;
818 }
819 
820 #ifdef CONFIG_PM_SLEEP
821 static int dwc3_prepare(struct device *dev)
822 {
823         struct dwc3     *dwc = dev_get_drvdata(dev);
824         unsigned long   flags;
825 
826         spin_lock_irqsave(&dwc->lock, flags);
827 
828         switch (dwc->dr_mode) {
829         case USB_DR_MODE_PERIPHERAL:
830         case USB_DR_MODE_OTG:
831                 dwc3_gadget_prepare(dwc);
832                 /* FALLTHROUGH */
833         case USB_DR_MODE_HOST:
834         default:
835                 dwc3_event_buffers_cleanup(dwc);
836                 break;
837         }
838 
839         spin_unlock_irqrestore(&dwc->lock, flags);
840 
841         return 0;
842 }
843 
844 static void dwc3_complete(struct device *dev)
845 {
846         struct dwc3     *dwc = dev_get_drvdata(dev);
847         unsigned long   flags;
848 
849         spin_lock_irqsave(&dwc->lock, flags);
850 
851         dwc3_event_buffers_setup(dwc);
852         switch (dwc->dr_mode) {
853         case USB_DR_MODE_PERIPHERAL:
854         case USB_DR_MODE_OTG:
855                 dwc3_gadget_complete(dwc);
856                 /* FALLTHROUGH */
857         case USB_DR_MODE_HOST:
858         default:
859                 break;
860         }
861 
862         spin_unlock_irqrestore(&dwc->lock, flags);
863 }
864 
865 static int dwc3_suspend(struct device *dev)
866 {
867         struct dwc3     *dwc = dev_get_drvdata(dev);
868         unsigned long   flags;
869 
870         spin_lock_irqsave(&dwc->lock, flags);
871 
872         switch (dwc->dr_mode) {
873         case USB_DR_MODE_PERIPHERAL:
874         case USB_DR_MODE_OTG:
875                 dwc3_gadget_suspend(dwc);
876                 /* FALLTHROUGH */
877         case USB_DR_MODE_HOST:
878         default:
879                 /* do nothing */
880                 break;
881         }
882 
883         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
884         spin_unlock_irqrestore(&dwc->lock, flags);
885 
886         usb_phy_shutdown(dwc->usb3_phy);
887         usb_phy_shutdown(dwc->usb2_phy);
888         phy_exit(dwc->usb2_generic_phy);
889         phy_exit(dwc->usb3_generic_phy);
890 
891         return 0;
892 }
893 
894 static int dwc3_resume(struct device *dev)
895 {
896         struct dwc3     *dwc = dev_get_drvdata(dev);
897         unsigned long   flags;
898         int             ret;
899 
900         usb_phy_init(dwc->usb3_phy);
901         usb_phy_init(dwc->usb2_phy);
902         ret = phy_init(dwc->usb2_generic_phy);
903         if (ret < 0)
904                 return ret;
905 
906         ret = phy_init(dwc->usb3_generic_phy);
907         if (ret < 0)
908                 goto err_usb2phy_init;
909 
910         spin_lock_irqsave(&dwc->lock, flags);
911 
912         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
913 
914         switch (dwc->dr_mode) {
915         case USB_DR_MODE_PERIPHERAL:
916         case USB_DR_MODE_OTG:
917                 dwc3_gadget_resume(dwc);
918                 /* FALLTHROUGH */
919         case USB_DR_MODE_HOST:
920         default:
921                 /* do nothing */
922                 break;
923         }
924 
925         spin_unlock_irqrestore(&dwc->lock, flags);
926 
927         pm_runtime_disable(dev);
928         pm_runtime_set_active(dev);
929         pm_runtime_enable(dev);
930 
931         return 0;
932 
933 err_usb2phy_init:
934         phy_exit(dwc->usb2_generic_phy);
935 
936         return ret;
937 }
938 
939 static const struct dev_pm_ops dwc3_dev_pm_ops = {
940         .prepare        = dwc3_prepare,
941         .complete       = dwc3_complete,
942 
943         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
944 };
945 
946 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
947 #else
948 #define DWC3_PM_OPS     NULL
949 #endif
950 
951 #ifdef CONFIG_OF
952 static const struct of_device_id of_dwc3_match[] = {
953         {
954                 .compatible = "snps,dwc3"
955         },
956         {
957                 .compatible = "synopsys,dwc3"
958         },
959         { },
960 };
961 MODULE_DEVICE_TABLE(of, of_dwc3_match);
962 #endif
963 
964 static struct platform_driver dwc3_driver = {
965         .probe          = dwc3_probe,
966         .remove         = dwc3_remove,
967         .driver         = {
968                 .name   = "dwc3",
969                 .of_match_table = of_match_ptr(of_dwc3_match),
970                 .pm     = DWC3_PM_OPS,
971         },
972 };
973 
974 module_platform_driver(dwc3_driver);
975 
976 MODULE_ALIAS("platform:dwc3");
977 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
978 MODULE_LICENSE("GPL v2");
979 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
980 

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