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Linux/drivers/usb/dwc2/platform.c

  1 /*
  2  * platform.c - DesignWare HS OTG Controller platform driver
  3  *
  4  * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
  5  *
  6  * Redistribution and use in source and binary forms, with or without
  7  * modification, are permitted provided that the following conditions
  8  * are met:
  9  * 1. Redistributions of source code must retain the above copyright
 10  *    notice, this list of conditions, and the following disclaimer,
 11  *    without modification.
 12  * 2. Redistributions in binary form must reproduce the above copyright
 13  *    notice, this list of conditions and the following disclaimer in the
 14  *    documentation and/or other materials provided with the distribution.
 15  * 3. The names of the above-listed copyright holders may not be used
 16  *    to endorse or promote products derived from this software without
 17  *    specific prior written permission.
 18  *
 19  * ALTERNATIVELY, this software may be distributed under the terms of the
 20  * GNU General Public License ("GPL") as published by the Free Software
 21  * Foundation; either version 2 of the License, or (at your option) any
 22  * later version.
 23  *
 24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 35  */
 36 
 37 #include <linux/kernel.h>
 38 #include <linux/module.h>
 39 #include <linux/slab.h>
 40 #include <linux/clk.h>
 41 #include <linux/device.h>
 42 #include <linux/dma-mapping.h>
 43 #include <linux/of_device.h>
 44 #include <linux/mutex.h>
 45 #include <linux/platform_device.h>
 46 #include <linux/phy/phy.h>
 47 #include <linux/platform_data/s3c-hsotg.h>
 48 #include <linux/reset.h>
 49 
 50 #include <linux/usb/of.h>
 51 
 52 #include "core.h"
 53 #include "hcd.h"
 54 #include "debug.h"
 55 
 56 static const char dwc2_driver_name[] = "dwc2";
 57 
 58 static const struct dwc2_core_params params_hi6220 = {
 59         .otg_cap                        = 2,    /* No HNP/SRP capable */
 60         .otg_ver                        = 0,    /* 1.3 */
 61         .dma_enable                     = 1,
 62         .dma_desc_enable                = 0,
 63         .dma_desc_fs_enable             = 0,
 64         .speed                          = 0,    /* High Speed */
 65         .enable_dynamic_fifo            = 1,
 66         .en_multiple_tx_fifo            = 1,
 67         .host_rx_fifo_size              = 512,
 68         .host_nperio_tx_fifo_size       = 512,
 69         .host_perio_tx_fifo_size        = 512,
 70         .max_transfer_size              = 65535,
 71         .max_packet_count               = 511,
 72         .host_channels                  = 16,
 73         .phy_type                       = 1,    /* UTMI */
 74         .phy_utmi_width                 = 8,
 75         .phy_ulpi_ddr                   = 0,    /* Single */
 76         .phy_ulpi_ext_vbus              = 0,
 77         .i2c_enable                     = 0,
 78         .ulpi_fs_ls                     = 0,
 79         .host_support_fs_ls_low_power   = 0,
 80         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
 81         .ts_dline                       = 0,
 82         .reload_ctl                     = 0,
 83         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 84                                           GAHBCFG_HBSTLEN_SHIFT,
 85         .uframe_sched                   = 0,
 86         .external_id_pin_ctl            = -1,
 87         .hibernation                    = -1,
 88 };
 89 
 90 static const struct dwc2_core_params params_bcm2835 = {
 91         .otg_cap                        = 0,    /* HNP/SRP capable */
 92         .otg_ver                        = 0,    /* 1.3 */
 93         .dma_enable                     = 1,
 94         .dma_desc_enable                = 0,
 95         .dma_desc_fs_enable             = 0,
 96         .speed                          = 0,    /* High Speed */
 97         .enable_dynamic_fifo            = 1,
 98         .en_multiple_tx_fifo            = 1,
 99         .host_rx_fifo_size              = 774,  /* 774 DWORDs */
100         .host_nperio_tx_fifo_size       = 256,  /* 256 DWORDs */
101         .host_perio_tx_fifo_size        = 512,  /* 512 DWORDs */
102         .max_transfer_size              = 65535,
103         .max_packet_count               = 511,
104         .host_channels                  = 8,
105         .phy_type                       = 1,    /* UTMI */
106         .phy_utmi_width                 = 8,    /* 8 bits */
107         .phy_ulpi_ddr                   = 0,    /* Single */
108         .phy_ulpi_ext_vbus              = 0,
109         .i2c_enable                     = 0,
110         .ulpi_fs_ls                     = 0,
111         .host_support_fs_ls_low_power   = 0,
112         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
113         .ts_dline                       = 0,
114         .reload_ctl                     = 0,
115         .ahbcfg                         = 0x10,
116         .uframe_sched                   = 0,
117         .external_id_pin_ctl            = -1,
118         .hibernation                    = -1,
119 };
120 
121 static const struct dwc2_core_params params_rk3066 = {
122         .otg_cap                        = 2,    /* non-HNP/non-SRP */
123         .otg_ver                        = -1,
124         .dma_enable                     = -1,
125         .dma_desc_enable                = 0,
126         .dma_desc_fs_enable             = 0,
127         .speed                          = -1,
128         .enable_dynamic_fifo            = 1,
129         .en_multiple_tx_fifo            = -1,
130         .host_rx_fifo_size              = 525,  /* 525 DWORDs */
131         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
132         .host_perio_tx_fifo_size        = 256,  /* 256 DWORDs */
133         .max_transfer_size              = -1,
134         .max_packet_count               = -1,
135         .host_channels                  = -1,
136         .phy_type                       = -1,
137         .phy_utmi_width                 = -1,
138         .phy_ulpi_ddr                   = -1,
139         .phy_ulpi_ext_vbus              = -1,
140         .i2c_enable                     = -1,
141         .ulpi_fs_ls                     = -1,
142         .host_support_fs_ls_low_power   = -1,
143         .host_ls_low_power_phy_clk      = -1,
144         .ts_dline                       = -1,
145         .reload_ctl                     = -1,
146         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
147                                           GAHBCFG_HBSTLEN_SHIFT,
148         .uframe_sched                   = -1,
149         .external_id_pin_ctl            = -1,
150         .hibernation                    = -1,
151 };
152 
153 static const struct dwc2_core_params params_ltq = {
154         .otg_cap                        = 2,    /* non-HNP/non-SRP */
155         .otg_ver                        = -1,
156         .dma_enable                     = -1,
157         .dma_desc_enable                = -1,
158         .dma_desc_fs_enable             = -1,
159         .speed                          = -1,
160         .enable_dynamic_fifo            = -1,
161         .en_multiple_tx_fifo            = -1,
162         .host_rx_fifo_size              = 288,  /* 288 DWORDs */
163         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
164         .host_perio_tx_fifo_size        = 96,   /* 96 DWORDs */
165         .max_transfer_size              = 65535,
166         .max_packet_count               = 511,
167         .host_channels                  = -1,
168         .phy_type                       = -1,
169         .phy_utmi_width                 = -1,
170         .phy_ulpi_ddr                   = -1,
171         .phy_ulpi_ext_vbus              = -1,
172         .i2c_enable                     = -1,
173         .ulpi_fs_ls                     = -1,
174         .host_support_fs_ls_low_power   = -1,
175         .host_ls_low_power_phy_clk      = -1,
176         .ts_dline                       = -1,
177         .reload_ctl                     = -1,
178         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
179                                           GAHBCFG_HBSTLEN_SHIFT,
180         .uframe_sched                   = -1,
181         .external_id_pin_ctl            = -1,
182         .hibernation                    = -1,
183 };
184 
185 /*
186  * Check the dr_mode against the module configuration and hardware
187  * capabilities.
188  *
189  * The hardware, module, and dr_mode, can each be set to host, device,
190  * or otg. Check that all these values are compatible and adjust the
191  * value of dr_mode if possible.
192  *
193  *                      actual
194  *    HW  MOD dr_mode   dr_mode
195  *  ------------------------------
196  *   HST  HST  any    :  HST
197  *   HST  DEV  any    :  ---
198  *   HST  OTG  any    :  HST
199  *
200  *   DEV  HST  any    :  ---
201  *   DEV  DEV  any    :  DEV
202  *   DEV  OTG  any    :  DEV
203  *
204  *   OTG  HST  any    :  HST
205  *   OTG  DEV  any    :  DEV
206  *   OTG  OTG  any    :  dr_mode
207  */
208 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
209 {
210         enum usb_dr_mode mode;
211 
212         hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
213         if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
214                 hsotg->dr_mode = USB_DR_MODE_OTG;
215 
216         mode = hsotg->dr_mode;
217 
218         if (dwc2_hw_is_device(hsotg)) {
219                 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
220                         dev_err(hsotg->dev,
221                                 "Controller does not support host mode.\n");
222                         return -EINVAL;
223                 }
224                 mode = USB_DR_MODE_PERIPHERAL;
225         } else if (dwc2_hw_is_host(hsotg)) {
226                 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
227                         dev_err(hsotg->dev,
228                                 "Controller does not support device mode.\n");
229                         return -EINVAL;
230                 }
231                 mode = USB_DR_MODE_HOST;
232         } else {
233                 if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
234                         mode = USB_DR_MODE_HOST;
235                 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
236                         mode = USB_DR_MODE_PERIPHERAL;
237         }
238 
239         if (mode != hsotg->dr_mode) {
240                 dev_warn(hsotg->dev,
241                         "Configuration mismatch. dr_mode forced to %s\n",
242                         mode == USB_DR_MODE_HOST ? "host" : "device");
243 
244                 hsotg->dr_mode = mode;
245         }
246 
247         return 0;
248 }
249 
250 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
251 {
252         struct platform_device *pdev = to_platform_device(hsotg->dev);
253         int ret;
254 
255         ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
256                                     hsotg->supplies);
257         if (ret)
258                 return ret;
259 
260         if (hsotg->clk) {
261                 ret = clk_prepare_enable(hsotg->clk);
262                 if (ret)
263                         return ret;
264         }
265 
266         if (hsotg->uphy)
267                 ret = usb_phy_init(hsotg->uphy);
268         else if (hsotg->plat && hsotg->plat->phy_init)
269                 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
270         else {
271                 ret = phy_power_on(hsotg->phy);
272                 if (ret == 0)
273                         ret = phy_init(hsotg->phy);
274         }
275 
276         return ret;
277 }
278 
279 /**
280  * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
281  * @hsotg: The driver state
282  *
283  * A wrapper for platform code responsible for controlling
284  * low-level USB platform resources (phy, clock, regulators)
285  */
286 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
287 {
288         int ret = __dwc2_lowlevel_hw_enable(hsotg);
289 
290         if (ret == 0)
291                 hsotg->ll_hw_enabled = true;
292         return ret;
293 }
294 
295 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
296 {
297         struct platform_device *pdev = to_platform_device(hsotg->dev);
298         int ret = 0;
299 
300         if (hsotg->uphy)
301                 usb_phy_shutdown(hsotg->uphy);
302         else if (hsotg->plat && hsotg->plat->phy_exit)
303                 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
304         else {
305                 ret = phy_exit(hsotg->phy);
306                 if (ret == 0)
307                         ret = phy_power_off(hsotg->phy);
308         }
309         if (ret)
310                 return ret;
311 
312         if (hsotg->clk)
313                 clk_disable_unprepare(hsotg->clk);
314 
315         ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
316                                      hsotg->supplies);
317 
318         return ret;
319 }
320 
321 /**
322  * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
323  * @hsotg: The driver state
324  *
325  * A wrapper for platform code responsible for controlling
326  * low-level USB platform resources (phy, clock, regulators)
327  */
328 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
329 {
330         int ret = __dwc2_lowlevel_hw_disable(hsotg);
331 
332         if (ret == 0)
333                 hsotg->ll_hw_enabled = false;
334         return ret;
335 }
336 
337 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
338 {
339         int i, ret;
340 
341         hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
342         if (IS_ERR(hsotg->reset)) {
343                 ret = PTR_ERR(hsotg->reset);
344                 switch (ret) {
345                 case -ENOENT:
346                 case -ENOTSUPP:
347                         hsotg->reset = NULL;
348                         break;
349                 default:
350                         dev_err(hsotg->dev, "error getting reset control %d\n",
351                                 ret);
352                         return ret;
353                 }
354         }
355 
356         if (hsotg->reset)
357                 reset_control_deassert(hsotg->reset);
358 
359         /* Set default UTMI width */
360         hsotg->phyif = GUSBCFG_PHYIF16;
361 
362         /*
363          * Attempt to find a generic PHY, then look for an old style
364          * USB PHY and then fall back to pdata
365          */
366         hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
367         if (IS_ERR(hsotg->phy)) {
368                 ret = PTR_ERR(hsotg->phy);
369                 switch (ret) {
370                 case -ENODEV:
371                 case -ENOSYS:
372                         hsotg->phy = NULL;
373                         break;
374                 case -EPROBE_DEFER:
375                         return ret;
376                 default:
377                         dev_err(hsotg->dev, "error getting phy %d\n", ret);
378                         return ret;
379                 }
380         }
381 
382         if (!hsotg->phy) {
383                 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
384                 if (IS_ERR(hsotg->uphy)) {
385                         ret = PTR_ERR(hsotg->uphy);
386                         switch (ret) {
387                         case -ENODEV:
388                         case -ENXIO:
389                                 hsotg->uphy = NULL;
390                                 break;
391                         case -EPROBE_DEFER:
392                                 return ret;
393                         default:
394                                 dev_err(hsotg->dev, "error getting usb phy %d\n",
395                                         ret);
396                                 return ret;
397                         }
398                 }
399         }
400 
401         hsotg->plat = dev_get_platdata(hsotg->dev);
402 
403         if (hsotg->phy) {
404                 /*
405                  * If using the generic PHY framework, check if the PHY bus
406                  * width is 8-bit and set the phyif appropriately.
407                  */
408                 if (phy_get_bus_width(hsotg->phy) == 8)
409                         hsotg->phyif = GUSBCFG_PHYIF8;
410         }
411 
412         /* Clock */
413         hsotg->clk = devm_clk_get(hsotg->dev, "otg");
414         if (IS_ERR(hsotg->clk)) {
415                 hsotg->clk = NULL;
416                 dev_dbg(hsotg->dev, "cannot get otg clock\n");
417         }
418 
419         /* Regulators */
420         for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
421                 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
422 
423         ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
424                                       hsotg->supplies);
425         if (ret) {
426                 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
427                 return ret;
428         }
429         return 0;
430 }
431 
432 /**
433  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
434  * DWC_otg driver
435  *
436  * @dev: Platform device
437  *
438  * This routine is called, for example, when the rmmod command is executed. The
439  * device may or may not be electrically present. If it is present, the driver
440  * stops device processing. Any resources used on behalf of this device are
441  * freed.
442  */
443 static int dwc2_driver_remove(struct platform_device *dev)
444 {
445         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
446 
447         dwc2_debugfs_exit(hsotg);
448         if (hsotg->hcd_enabled)
449                 dwc2_hcd_remove(hsotg);
450         if (hsotg->gadget_enabled)
451                 dwc2_hsotg_remove(hsotg);
452 
453         if (hsotg->ll_hw_enabled)
454                 dwc2_lowlevel_hw_disable(hsotg);
455 
456         if (hsotg->reset)
457                 reset_control_assert(hsotg->reset);
458 
459         return 0;
460 }
461 
462 /**
463  * dwc2_driver_shutdown() - Called on device shutdown
464  *
465  * @dev: Platform device
466  *
467  * In specific conditions (involving usb hubs) dwc2 devices can create a
468  * lot of interrupts, even to the point of overwhelming devices running
469  * at low frequencies. Some devices need to do special clock handling
470  * at shutdown-time which may bring the system clock below the threshold
471  * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
472  * prevents reboots/poweroffs from getting stuck in such cases.
473  */
474 static void dwc2_driver_shutdown(struct platform_device *dev)
475 {
476         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
477 
478         disable_irq(hsotg->irq);
479 }
480 
481 static const struct of_device_id dwc2_of_match_table[] = {
482         { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
483         { .compatible = "hisilicon,hi6220-usb", .data = &params_hi6220 },
484         { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
485         { .compatible = "lantiq,arx100-usb", .data = &params_ltq },
486         { .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
487         { .compatible = "snps,dwc2", .data = NULL },
488         { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
489         {},
490 };
491 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
492 
493 /**
494  * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
495  * driver
496  *
497  * @dev: Platform device
498  *
499  * This routine creates the driver components required to control the device
500  * (core, HCD, and PCD) and initializes the device. The driver components are
501  * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
502  * in the device private data. This allows the driver to access the dwc2_hsotg
503  * structure on subsequent calls to driver methods for this device.
504  */
505 static int dwc2_driver_probe(struct platform_device *dev)
506 {
507         const struct of_device_id *match;
508         const struct dwc2_core_params *params;
509         struct dwc2_core_params defparams;
510         struct dwc2_hsotg *hsotg;
511         struct resource *res;
512         int retval;
513 
514         match = of_match_device(dwc2_of_match_table, &dev->dev);
515         if (match && match->data) {
516                 params = match->data;
517         } else {
518                 /* Default all params to autodetect */
519                 dwc2_set_all_params(&defparams, -1);
520                 params = &defparams;
521 
522                 /*
523                  * Disable descriptor dma mode by default as the HW can support
524                  * it, but does not support it for SPLIT transactions.
525                  * Disable it for FS devices as well.
526                  */
527                 defparams.dma_desc_enable = 0;
528                 defparams.dma_desc_fs_enable = 0;
529         }
530 
531         hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
532         if (!hsotg)
533                 return -ENOMEM;
534 
535         hsotg->dev = &dev->dev;
536 
537         /*
538          * Use reasonable defaults so platforms don't have to provide these.
539          */
540         if (!dev->dev.dma_mask)
541                 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
542         retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
543         if (retval)
544                 return retval;
545 
546         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
547         hsotg->regs = devm_ioremap_resource(&dev->dev, res);
548         if (IS_ERR(hsotg->regs))
549                 return PTR_ERR(hsotg->regs);
550 
551         dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
552                 (unsigned long)res->start, hsotg->regs);
553 
554         retval = dwc2_lowlevel_hw_init(hsotg);
555         if (retval)
556                 return retval;
557 
558         spin_lock_init(&hsotg->lock);
559 
560         hsotg->core_params = devm_kzalloc(&dev->dev,
561                                 sizeof(*hsotg->core_params), GFP_KERNEL);
562         if (!hsotg->core_params)
563                 return -ENOMEM;
564 
565         dwc2_set_all_params(hsotg->core_params, -1);
566 
567         hsotg->irq = platform_get_irq(dev, 0);
568         if (hsotg->irq < 0) {
569                 dev_err(&dev->dev, "missing IRQ resource\n");
570                 return hsotg->irq;
571         }
572 
573         dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
574                 hsotg->irq);
575         retval = devm_request_irq(hsotg->dev, hsotg->irq,
576                                   dwc2_handle_common_intr, IRQF_SHARED,
577                                   dev_name(hsotg->dev), hsotg);
578         if (retval)
579                 return retval;
580 
581         retval = dwc2_lowlevel_hw_enable(hsotg);
582         if (retval)
583                 return retval;
584 
585         retval = dwc2_get_dr_mode(hsotg);
586         if (retval)
587                 goto error;
588 
589         /*
590          * Reset before dwc2_get_hwparams() then it could get power-on real
591          * reset value form registers.
592          */
593         dwc2_core_reset_and_force_dr_mode(hsotg);
594 
595         /* Detect config values from hardware */
596         retval = dwc2_get_hwparams(hsotg);
597         if (retval)
598                 goto error;
599 
600         /* Validate parameter values */
601         dwc2_set_parameters(hsotg, params);
602 
603         dwc2_force_dr_mode(hsotg);
604 
605         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
606                 retval = dwc2_gadget_init(hsotg, hsotg->irq);
607                 if (retval)
608                         goto error;
609                 hsotg->gadget_enabled = 1;
610         }
611 
612         if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
613                 retval = dwc2_hcd_init(hsotg, hsotg->irq);
614                 if (retval) {
615                         if (hsotg->gadget_enabled)
616                                 dwc2_hsotg_remove(hsotg);
617                         goto error;
618                 }
619                 hsotg->hcd_enabled = 1;
620         }
621 
622         platform_set_drvdata(dev, hsotg);
623 
624         dwc2_debugfs_init(hsotg);
625 
626         /* Gadget code manages lowlevel hw on its own */
627         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
628                 dwc2_lowlevel_hw_disable(hsotg);
629 
630         return 0;
631 
632 error:
633         dwc2_lowlevel_hw_disable(hsotg);
634         return retval;
635 }
636 
637 static int __maybe_unused dwc2_suspend(struct device *dev)
638 {
639         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
640         int ret = 0;
641 
642         if (dwc2_is_device_mode(dwc2))
643                 dwc2_hsotg_suspend(dwc2);
644 
645         if (dwc2->ll_hw_enabled)
646                 ret = __dwc2_lowlevel_hw_disable(dwc2);
647 
648         return ret;
649 }
650 
651 static int __maybe_unused dwc2_resume(struct device *dev)
652 {
653         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
654         int ret = 0;
655 
656         if (dwc2->ll_hw_enabled) {
657                 ret = __dwc2_lowlevel_hw_enable(dwc2);
658                 if (ret)
659                         return ret;
660         }
661 
662         if (dwc2_is_device_mode(dwc2))
663                 ret = dwc2_hsotg_resume(dwc2);
664 
665         return ret;
666 }
667 
668 static const struct dev_pm_ops dwc2_dev_pm_ops = {
669         SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
670 };
671 
672 static struct platform_driver dwc2_platform_driver = {
673         .driver = {
674                 .name = dwc2_driver_name,
675                 .of_match_table = dwc2_of_match_table,
676                 .pm = &dwc2_dev_pm_ops,
677         },
678         .probe = dwc2_driver_probe,
679         .remove = dwc2_driver_remove,
680         .shutdown = dwc2_driver_shutdown,
681 };
682 
683 module_platform_driver(dwc2_platform_driver);
684 
685 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
686 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
687 MODULE_LICENSE("Dual BSD/GPL");
688 

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