Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/usb/chipidea/core.c

  1 /*
  2  * core.c - ChipIdea USB IP core family device controller
  3  *
  4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5  *
  6  * Author: David Lopo
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  */
 12 
 13 /*
 14  * Description: ChipIdea USB IP core family device controller
 15  *
 16  * This driver is composed of several blocks:
 17  * - HW:     hardware interface
 18  * - DBG:    debug facilities (optional)
 19  * - UTIL:   utilities
 20  * - ISR:    interrupts handling
 21  * - ENDPT:  endpoint operations (Gadget API)
 22  * - GADGET: gadget operations (Gadget API)
 23  * - BUS:    bus glue code, bus abstraction layer
 24  *
 25  * Compile Options
 26  * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
 27  * - STALL_IN:  non-empty bulk-in pipes cannot be halted
 28  *              if defined mass storage compliance succeeds but with warnings
 29  *              => case 4: Hi >  Dn
 30  *              => case 5: Hi >  Di
 31  *              => case 8: Hi <> Do
 32  *              if undefined usbtest 13 fails
 33  * - TRACE:     enable function tracing (depends on DEBUG)
 34  *
 35  * Main Features
 36  * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
 37  * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
 38  * - Normal & LPM support
 39  *
 40  * USBTEST Report
 41  * - OK: 0-12, 13 (STALL_IN defined) & 14
 42  * - Not Supported: 15 & 16 (ISO)
 43  *
 44  * TODO List
 45  * - OTG
 46  * - Interrupt Traffic
 47  * - GET_STATUS(device) - always reports 0
 48  * - Gadget API (majority of optional features)
 49  * - Suspend & Remote Wakeup
 50  */
 51 #include <linux/delay.h>
 52 #include <linux/device.h>
 53 #include <linux/dma-mapping.h>
 54 #include <linux/platform_device.h>
 55 #include <linux/module.h>
 56 #include <linux/idr.h>
 57 #include <linux/interrupt.h>
 58 #include <linux/io.h>
 59 #include <linux/kernel.h>
 60 #include <linux/slab.h>
 61 #include <linux/pm_runtime.h>
 62 #include <linux/usb/ch9.h>
 63 #include <linux/usb/gadget.h>
 64 #include <linux/usb/otg.h>
 65 #include <linux/usb/chipidea.h>
 66 #include <linux/usb/of.h>
 67 #include <linux/of.h>
 68 #include <linux/phy.h>
 69 #include <linux/regulator/consumer.h>
 70 
 71 #include "ci.h"
 72 #include "udc.h"
 73 #include "bits.h"
 74 #include "host.h"
 75 #include "debug.h"
 76 #include "otg.h"
 77 
 78 /* Controller register map */
 79 static const u8 ci_regs_nolpm[] = {
 80         [CAP_CAPLENGTH]         = 0x00U,
 81         [CAP_HCCPARAMS]         = 0x08U,
 82         [CAP_DCCPARAMS]         = 0x24U,
 83         [CAP_TESTMODE]          = 0x38U,
 84         [OP_USBCMD]             = 0x00U,
 85         [OP_USBSTS]             = 0x04U,
 86         [OP_USBINTR]            = 0x08U,
 87         [OP_DEVICEADDR]         = 0x14U,
 88         [OP_ENDPTLISTADDR]      = 0x18U,
 89         [OP_PORTSC]             = 0x44U,
 90         [OP_DEVLC]              = 0x84U,
 91         [OP_OTGSC]              = 0x64U,
 92         [OP_USBMODE]            = 0x68U,
 93         [OP_ENDPTSETUPSTAT]     = 0x6CU,
 94         [OP_ENDPTPRIME]         = 0x70U,
 95         [OP_ENDPTFLUSH]         = 0x74U,
 96         [OP_ENDPTSTAT]          = 0x78U,
 97         [OP_ENDPTCOMPLETE]      = 0x7CU,
 98         [OP_ENDPTCTRL]          = 0x80U,
 99 };
100 
101 static const u8 ci_regs_lpm[] = {
102         [CAP_CAPLENGTH]         = 0x00U,
103         [CAP_HCCPARAMS]         = 0x08U,
104         [CAP_DCCPARAMS]         = 0x24U,
105         [CAP_TESTMODE]          = 0xFCU,
106         [OP_USBCMD]             = 0x00U,
107         [OP_USBSTS]             = 0x04U,
108         [OP_USBINTR]            = 0x08U,
109         [OP_DEVICEADDR]         = 0x14U,
110         [OP_ENDPTLISTADDR]      = 0x18U,
111         [OP_PORTSC]             = 0x44U,
112         [OP_DEVLC]              = 0x84U,
113         [OP_OTGSC]              = 0xC4U,
114         [OP_USBMODE]            = 0xC8U,
115         [OP_ENDPTSETUPSTAT]     = 0xD8U,
116         [OP_ENDPTPRIME]         = 0xDCU,
117         [OP_ENDPTFLUSH]         = 0xE0U,
118         [OP_ENDPTSTAT]          = 0xE4U,
119         [OP_ENDPTCOMPLETE]      = 0xE8U,
120         [OP_ENDPTCTRL]          = 0xECU,
121 };
122 
123 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
124 {
125         int i;
126 
127         for (i = 0; i < OP_ENDPTCTRL; i++)
128                 ci->hw_bank.regmap[i] =
129                         (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
130                         (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
131 
132         for (; i <= OP_LAST; i++)
133                 ci->hw_bank.regmap[i] = ci->hw_bank.op +
134                         4 * (i - OP_ENDPTCTRL) +
135                         (is_lpm
136                          ? ci_regs_lpm[OP_ENDPTCTRL]
137                          : ci_regs_nolpm[OP_ENDPTCTRL]);
138 
139         return 0;
140 }
141 
142 /**
143  * hw_port_test_set: writes port test mode (execute without interruption)
144  * @mode: new value
145  *
146  * This function returns an error code
147  */
148 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
149 {
150         const u8 TEST_MODE_MAX = 7;
151 
152         if (mode > TEST_MODE_MAX)
153                 return -EINVAL;
154 
155         hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
156         return 0;
157 }
158 
159 /**
160  * hw_port_test_get: reads port test mode value
161  *
162  * This function returns port test mode value
163  */
164 u8 hw_port_test_get(struct ci_hdrc *ci)
165 {
166         return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
167 }
168 
169 /* The PHY enters/leaves low power mode */
170 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
171 {
172         enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
173         bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
174 
175         if (enable && !lpm) {
176                 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
177                                 PORTSC_PHCD(ci->hw_bank.lpm));
178         } else  if (!enable && lpm) {
179                 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
180                                 0);
181                 /* 
182                  * The controller needs at least 1ms to reflect
183                  * PHY's status, the PHY also needs some time (less
184                  * than 1ms) to leave low power mode.
185                  */
186                 usleep_range(1500, 2000);
187         }
188 }
189 
190 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
191 {
192         u32 reg;
193 
194         /* bank is a module variable */
195         ci->hw_bank.abs = base;
196 
197         ci->hw_bank.cap = ci->hw_bank.abs;
198         ci->hw_bank.cap += ci->platdata->capoffset;
199         ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
200 
201         hw_alloc_regmap(ci, false);
202         reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
203                 __ffs(HCCPARAMS_LEN);
204         ci->hw_bank.lpm  = reg;
205         if (reg)
206                 hw_alloc_regmap(ci, !!reg);
207         ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
208         ci->hw_bank.size += OP_LAST;
209         ci->hw_bank.size /= sizeof(u32);
210 
211         reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
212                 __ffs(DCCPARAMS_DEN);
213         ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */
214 
215         if (ci->hw_ep_max > ENDPT_MAX)
216                 return -ENODEV;
217 
218         ci_hdrc_enter_lpm(ci, false);
219 
220         /* Disable all interrupts bits */
221         hw_write(ci, OP_USBINTR, 0xffffffff, 0);
222 
223         /* Clear all interrupts status bits*/
224         hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
225 
226         dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
227                 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
228 
229         /* setup lock mode ? */
230 
231         /* ENDPTSETUPSTAT is '' by default */
232 
233         /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
234 
235         return 0;
236 }
237 
238 static void hw_phymode_configure(struct ci_hdrc *ci)
239 {
240         u32 portsc, lpm, sts = 0;
241 
242         switch (ci->platdata->phy_mode) {
243         case USBPHY_INTERFACE_MODE_UTMI:
244                 portsc = PORTSC_PTS(PTS_UTMI);
245                 lpm = DEVLC_PTS(PTS_UTMI);
246                 break;
247         case USBPHY_INTERFACE_MODE_UTMIW:
248                 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
249                 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
250                 break;
251         case USBPHY_INTERFACE_MODE_ULPI:
252                 portsc = PORTSC_PTS(PTS_ULPI);
253                 lpm = DEVLC_PTS(PTS_ULPI);
254                 break;
255         case USBPHY_INTERFACE_MODE_SERIAL:
256                 portsc = PORTSC_PTS(PTS_SERIAL);
257                 lpm = DEVLC_PTS(PTS_SERIAL);
258                 sts = 1;
259                 break;
260         case USBPHY_INTERFACE_MODE_HSIC:
261                 portsc = PORTSC_PTS(PTS_HSIC);
262                 lpm = DEVLC_PTS(PTS_HSIC);
263                 break;
264         default:
265                 return;
266         }
267 
268         if (ci->hw_bank.lpm) {
269                 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
270                 if (sts)
271                         hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
272         } else {
273                 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
274                 if (sts)
275                         hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
276         }
277 }
278 
279 /**
280  * ci_usb_phy_init: initialize phy according to different phy type
281  * @ci: the controller
282   *
283  * This function returns an error code if usb_phy_init has failed
284  */
285 static int ci_usb_phy_init(struct ci_hdrc *ci)
286 {
287         int ret;
288 
289         switch (ci->platdata->phy_mode) {
290         case USBPHY_INTERFACE_MODE_UTMI:
291         case USBPHY_INTERFACE_MODE_UTMIW:
292         case USBPHY_INTERFACE_MODE_HSIC:
293                 ret = usb_phy_init(ci->transceiver);
294                 if (ret)
295                         return ret;
296                 hw_phymode_configure(ci);
297                 break;
298         case USBPHY_INTERFACE_MODE_ULPI:
299         case USBPHY_INTERFACE_MODE_SERIAL:
300                 hw_phymode_configure(ci);
301                 ret = usb_phy_init(ci->transceiver);
302                 if (ret)
303                         return ret;
304                 break;
305         default:
306                 ret = usb_phy_init(ci->transceiver);
307         }
308 
309         return ret;
310 }
311 
312 /**
313  * hw_device_reset: resets chip (execute without interruption)
314  * @ci: the controller
315   *
316  * This function returns an error code
317  */
318 int hw_device_reset(struct ci_hdrc *ci, u32 mode)
319 {
320         /* should flush & stop before reset */
321         hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
322         hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
323 
324         hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
325         while (hw_read(ci, OP_USBCMD, USBCMD_RST))
326                 udelay(10);             /* not RTOS friendly */
327 
328         if (ci->platdata->notify_event)
329                 ci->platdata->notify_event(ci,
330                         CI_HDRC_CONTROLLER_RESET_EVENT);
331 
332         if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
333                 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
334 
335         if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
336                 if (ci->hw_bank.lpm)
337                         hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
338                 else
339                         hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
340         }
341 
342         /* USBMODE should be configured step by step */
343         hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
344         hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
345         /* HW >= 2.3 */
346         hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
347 
348         if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
349                 pr_err("cannot enter in %s mode", ci_role(ci)->name);
350                 pr_err("lpm = %i", ci->hw_bank.lpm);
351                 return -ENODEV;
352         }
353 
354         return 0;
355 }
356 
357 /**
358  * hw_wait_reg: wait the register value
359  *
360  * Sometimes, it needs to wait register value before going on.
361  * Eg, when switch to device mode, the vbus value should be lower
362  * than OTGSC_BSV before connects to host.
363  *
364  * @ci: the controller
365  * @reg: register index
366  * @mask: mast bit
367  * @value: the bit value to wait
368  * @timeout_ms: timeout in millisecond
369  *
370  * This function returns an error code if timeout
371  */
372 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
373                                 u32 value, unsigned int timeout_ms)
374 {
375         unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
376 
377         while (hw_read(ci, reg, mask) != value) {
378                 if (time_after(jiffies, elapse)) {
379                         dev_err(ci->dev, "timeout waiting for %08x in %d\n",
380                                         mask, reg);
381                         return -ETIMEDOUT;
382                 }
383                 msleep(20);
384         }
385 
386         return 0;
387 }
388 
389 static irqreturn_t ci_irq(int irq, void *data)
390 {
391         struct ci_hdrc *ci = data;
392         irqreturn_t ret = IRQ_NONE;
393         u32 otgsc = 0;
394 
395         if (ci->is_otg)
396                 otgsc = hw_read(ci, OP_OTGSC, ~0);
397 
398         /*
399          * Handle id change interrupt, it indicates device/host function
400          * switch.
401          */
402         if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
403                 ci->id_event = true;
404                 ci_clear_otg_interrupt(ci, OTGSC_IDIS);
405                 disable_irq_nosync(ci->irq);
406                 queue_work(ci->wq, &ci->work);
407                 return IRQ_HANDLED;
408         }
409 
410         /*
411          * Handle vbus change interrupt, it indicates device connection
412          * and disconnection events.
413          */
414         if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
415                 ci->b_sess_valid_event = true;
416                 ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
417                 disable_irq_nosync(ci->irq);
418                 queue_work(ci->wq, &ci->work);
419                 return IRQ_HANDLED;
420         }
421 
422         /* Handle device/host interrupt */
423         if (ci->role != CI_ROLE_END)
424                 ret = ci_role(ci)->irq(ci);
425 
426         return ret;
427 }
428 
429 static int ci_get_platdata(struct device *dev,
430                 struct ci_hdrc_platform_data *platdata)
431 {
432         if (!platdata->phy_mode)
433                 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
434 
435         if (!platdata->dr_mode)
436                 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
437 
438         if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
439                 platdata->dr_mode = USB_DR_MODE_OTG;
440 
441         if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
442                 /* Get the vbus regulator */
443                 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
444                 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
445                         return -EPROBE_DEFER;
446                 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
447                         /* no vbus regualator is needed */
448                         platdata->reg_vbus = NULL;
449                 } else if (IS_ERR(platdata->reg_vbus)) {
450                         dev_err(dev, "Getting regulator error: %ld\n",
451                                 PTR_ERR(platdata->reg_vbus));
452                         return PTR_ERR(platdata->reg_vbus);
453                 }
454         }
455 
456         if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
457                 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
458 
459         return 0;
460 }
461 
462 static DEFINE_IDA(ci_ida);
463 
464 struct platform_device *ci_hdrc_add_device(struct device *dev,
465                         struct resource *res, int nres,
466                         struct ci_hdrc_platform_data *platdata)
467 {
468         struct platform_device *pdev;
469         int id, ret;
470 
471         ret = ci_get_platdata(dev, platdata);
472         if (ret)
473                 return ERR_PTR(ret);
474 
475         id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
476         if (id < 0)
477                 return ERR_PTR(id);
478 
479         pdev = platform_device_alloc("ci_hdrc", id);
480         if (!pdev) {
481                 ret = -ENOMEM;
482                 goto put_id;
483         }
484 
485         pdev->dev.parent = dev;
486         pdev->dev.dma_mask = dev->dma_mask;
487         pdev->dev.dma_parms = dev->dma_parms;
488         dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
489 
490         ret = platform_device_add_resources(pdev, res, nres);
491         if (ret)
492                 goto err;
493 
494         ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
495         if (ret)
496                 goto err;
497 
498         ret = platform_device_add(pdev);
499         if (ret)
500                 goto err;
501 
502         return pdev;
503 
504 err:
505         platform_device_put(pdev);
506 put_id:
507         ida_simple_remove(&ci_ida, id);
508         return ERR_PTR(ret);
509 }
510 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
511 
512 void ci_hdrc_remove_device(struct platform_device *pdev)
513 {
514         int id = pdev->id;
515         platform_device_unregister(pdev);
516         ida_simple_remove(&ci_ida, id);
517 }
518 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
519 
520 static inline void ci_role_destroy(struct ci_hdrc *ci)
521 {
522         ci_hdrc_gadget_destroy(ci);
523         ci_hdrc_host_destroy(ci);
524         if (ci->is_otg)
525                 ci_hdrc_otg_destroy(ci);
526 }
527 
528 static void ci_get_otg_capable(struct ci_hdrc *ci)
529 {
530         if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
531                 ci->is_otg = false;
532         else
533                 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
534                                 DCCPARAMS_DC | DCCPARAMS_HC)
535                                         == (DCCPARAMS_DC | DCCPARAMS_HC));
536         if (ci->is_otg) {
537                 dev_dbg(ci->dev, "It is OTG capable controller\n");
538                 ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
539                 ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
540         }
541 }
542 
543 static int ci_hdrc_probe(struct platform_device *pdev)
544 {
545         struct device   *dev = &pdev->dev;
546         struct ci_hdrc  *ci;
547         struct resource *res;
548         void __iomem    *base;
549         int             ret;
550         enum usb_dr_mode dr_mode;
551 
552         if (!dev_get_platdata(dev)) {
553                 dev_err(dev, "platform data missing\n");
554                 return -ENODEV;
555         }
556 
557         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
558         base = devm_ioremap_resource(dev, res);
559         if (IS_ERR(base))
560                 return PTR_ERR(base);
561 
562         ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
563         if (!ci) {
564                 dev_err(dev, "can't allocate device\n");
565                 return -ENOMEM;
566         }
567 
568         ci->dev = dev;
569         ci->platdata = dev_get_platdata(dev);
570         ci->imx28_write_fix = !!(ci->platdata->flags &
571                 CI_HDRC_IMX28_WRITE_FIX);
572 
573         ret = hw_device_init(ci, base);
574         if (ret < 0) {
575                 dev_err(dev, "can't initialize hardware\n");
576                 return -ENODEV;
577         }
578 
579         if (ci->platdata->phy)
580                 ci->transceiver = ci->platdata->phy;
581         else
582                 ci->transceiver = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
583 
584         if (IS_ERR(ci->transceiver)) {
585                 ret = PTR_ERR(ci->transceiver);
586                 /*
587                  * if -ENXIO is returned, it means PHY layer wasn't
588                  * enabled, so it makes no sense to return -EPROBE_DEFER
589                  * in that case, since no PHY driver will ever probe.
590                  */
591                 if (ret == -ENXIO)
592                         return ret;
593 
594                 dev_err(dev, "no usb2 phy configured\n");
595                 return -EPROBE_DEFER;
596         }
597 
598         ret = ci_usb_phy_init(ci);
599         if (ret) {
600                 dev_err(dev, "unable to init phy: %d\n", ret);
601                 return ret;
602         }
603 
604         ci->hw_bank.phys = res->start;
605 
606         ci->irq = platform_get_irq(pdev, 0);
607         if (ci->irq < 0) {
608                 dev_err(dev, "missing IRQ\n");
609                 ret = ci->irq;
610                 goto deinit_phy;
611         }
612 
613         ci_get_otg_capable(ci);
614 
615         dr_mode = ci->platdata->dr_mode;
616         /* initialize role(s) before the interrupt is requested */
617         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
618                 ret = ci_hdrc_host_init(ci);
619                 if (ret)
620                         dev_info(dev, "doesn't support host\n");
621         }
622 
623         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
624                 ret = ci_hdrc_gadget_init(ci);
625                 if (ret)
626                         dev_info(dev, "doesn't support gadget\n");
627         }
628 
629         if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
630                 dev_err(dev, "no supported roles\n");
631                 ret = -ENODEV;
632                 goto deinit_phy;
633         }
634 
635         if (ci->is_otg) {
636                 ret = ci_hdrc_otg_init(ci);
637                 if (ret) {
638                         dev_err(dev, "init otg fails, ret = %d\n", ret);
639                         goto stop;
640                 }
641         }
642 
643         if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
644                 if (ci->is_otg) {
645                         /*
646                          * ID pin needs 1ms debouce time,
647                          * we delay 2ms for safe.
648                          */
649                         mdelay(2);
650                         ci->role = ci_otg_role(ci);
651                         ci_enable_otg_interrupt(ci, OTGSC_IDIE);
652                 } else {
653                         /*
654                          * If the controller is not OTG capable, but support
655                          * role switch, the defalt role is gadget, and the
656                          * user can switch it through debugfs.
657                          */
658                         ci->role = CI_ROLE_GADGET;
659                 }
660         } else {
661                 ci->role = ci->roles[CI_ROLE_HOST]
662                         ? CI_ROLE_HOST
663                         : CI_ROLE_GADGET;
664         }
665 
666         /* only update vbus status for peripheral */
667         if (ci->role == CI_ROLE_GADGET)
668                 ci_handle_vbus_change(ci);
669 
670         ret = ci_role_start(ci, ci->role);
671         if (ret) {
672                 dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
673                 goto stop;
674         }
675 
676         platform_set_drvdata(pdev, ci);
677         ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
678                           ci);
679         if (ret)
680                 goto stop;
681 
682         ret = dbg_create_files(ci);
683         if (!ret)
684                 return 0;
685 
686         free_irq(ci->irq, ci);
687 stop:
688         ci_role_destroy(ci);
689 deinit_phy:
690         usb_phy_shutdown(ci->transceiver);
691 
692         return ret;
693 }
694 
695 static int ci_hdrc_remove(struct platform_device *pdev)
696 {
697         struct ci_hdrc *ci = platform_get_drvdata(pdev);
698 
699         dbg_remove_files(ci);
700         free_irq(ci->irq, ci);
701         ci_role_destroy(ci);
702         ci_hdrc_enter_lpm(ci, true);
703         usb_phy_shutdown(ci->transceiver);
704         kfree(ci->hw_bank.regmap);
705 
706         return 0;
707 }
708 
709 static struct platform_driver ci_hdrc_driver = {
710         .probe  = ci_hdrc_probe,
711         .remove = ci_hdrc_remove,
712         .driver = {
713                 .name   = "ci_hdrc",
714         },
715 };
716 
717 module_platform_driver(ci_hdrc_driver);
718 
719 MODULE_ALIAS("platform:ci_hdrc");
720 MODULE_LICENSE("GPL v2");
721 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
722 MODULE_DESCRIPTION("ChipIdea HDRC Driver");
723 

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