Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/usb/chipidea/core.c

  1 /*
  2  * core.c - ChipIdea USB IP core family device controller
  3  *
  4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5  *
  6  * Author: David Lopo
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  */
 12 
 13 /*
 14  * Description: ChipIdea USB IP core family device controller
 15  *
 16  * This driver is composed of several blocks:
 17  * - HW:     hardware interface
 18  * - DBG:    debug facilities (optional)
 19  * - UTIL:   utilities
 20  * - ISR:    interrupts handling
 21  * - ENDPT:  endpoint operations (Gadget API)
 22  * - GADGET: gadget operations (Gadget API)
 23  * - BUS:    bus glue code, bus abstraction layer
 24  *
 25  * Compile Options
 26  * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities
 27  * - STALL_IN:  non-empty bulk-in pipes cannot be halted
 28  *              if defined mass storage compliance succeeds but with warnings
 29  *              => case 4: Hi >  Dn
 30  *              => case 5: Hi >  Di
 31  *              => case 8: Hi <> Do
 32  *              if undefined usbtest 13 fails
 33  * - TRACE:     enable function tracing (depends on DEBUG)
 34  *
 35  * Main Features
 36  * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
 37  * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
 38  * - Normal & LPM support
 39  *
 40  * USBTEST Report
 41  * - OK: 0-12, 13 (STALL_IN defined) & 14
 42  * - Not Supported: 15 & 16 (ISO)
 43  *
 44  * TODO List
 45  * - Suspend & Remote Wakeup
 46  */
 47 #include <linux/delay.h>
 48 #include <linux/device.h>
 49 #include <linux/dma-mapping.h>
 50 #include <linux/platform_device.h>
 51 #include <linux/module.h>
 52 #include <linux/idr.h>
 53 #include <linux/interrupt.h>
 54 #include <linux/io.h>
 55 #include <linux/kernel.h>
 56 #include <linux/slab.h>
 57 #include <linux/pm_runtime.h>
 58 #include <linux/usb/ch9.h>
 59 #include <linux/usb/gadget.h>
 60 #include <linux/usb/otg.h>
 61 #include <linux/usb/chipidea.h>
 62 #include <linux/usb/of.h>
 63 #include <linux/of.h>
 64 #include <linux/phy.h>
 65 #include <linux/regulator/consumer.h>
 66 
 67 #include "ci.h"
 68 #include "udc.h"
 69 #include "bits.h"
 70 #include "host.h"
 71 #include "debug.h"
 72 #include "otg.h"
 73 #include "otg_fsm.h"
 74 
 75 /* Controller register map */
 76 static const u8 ci_regs_nolpm[] = {
 77         [CAP_CAPLENGTH]         = 0x00U,
 78         [CAP_HCCPARAMS]         = 0x08U,
 79         [CAP_DCCPARAMS]         = 0x24U,
 80         [CAP_TESTMODE]          = 0x38U,
 81         [OP_USBCMD]             = 0x00U,
 82         [OP_USBSTS]             = 0x04U,
 83         [OP_USBINTR]            = 0x08U,
 84         [OP_DEVICEADDR]         = 0x14U,
 85         [OP_ENDPTLISTADDR]      = 0x18U,
 86         [OP_PORTSC]             = 0x44U,
 87         [OP_DEVLC]              = 0x84U,
 88         [OP_OTGSC]              = 0x64U,
 89         [OP_USBMODE]            = 0x68U,
 90         [OP_ENDPTSETUPSTAT]     = 0x6CU,
 91         [OP_ENDPTPRIME]         = 0x70U,
 92         [OP_ENDPTFLUSH]         = 0x74U,
 93         [OP_ENDPTSTAT]          = 0x78U,
 94         [OP_ENDPTCOMPLETE]      = 0x7CU,
 95         [OP_ENDPTCTRL]          = 0x80U,
 96 };
 97 
 98 static const u8 ci_regs_lpm[] = {
 99         [CAP_CAPLENGTH]         = 0x00U,
100         [CAP_HCCPARAMS]         = 0x08U,
101         [CAP_DCCPARAMS]         = 0x24U,
102         [CAP_TESTMODE]          = 0xFCU,
103         [OP_USBCMD]             = 0x00U,
104         [OP_USBSTS]             = 0x04U,
105         [OP_USBINTR]            = 0x08U,
106         [OP_DEVICEADDR]         = 0x14U,
107         [OP_ENDPTLISTADDR]      = 0x18U,
108         [OP_PORTSC]             = 0x44U,
109         [OP_DEVLC]              = 0x84U,
110         [OP_OTGSC]              = 0xC4U,
111         [OP_USBMODE]            = 0xC8U,
112         [OP_ENDPTSETUPSTAT]     = 0xD8U,
113         [OP_ENDPTPRIME]         = 0xDCU,
114         [OP_ENDPTFLUSH]         = 0xE0U,
115         [OP_ENDPTSTAT]          = 0xE4U,
116         [OP_ENDPTCOMPLETE]      = 0xE8U,
117         [OP_ENDPTCTRL]          = 0xECU,
118 };
119 
120 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
121 {
122         int i;
123 
124         for (i = 0; i < OP_ENDPTCTRL; i++)
125                 ci->hw_bank.regmap[i] =
126                         (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
127                         (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
128 
129         for (; i <= OP_LAST; i++)
130                 ci->hw_bank.regmap[i] = ci->hw_bank.op +
131                         4 * (i - OP_ENDPTCTRL) +
132                         (is_lpm
133                          ? ci_regs_lpm[OP_ENDPTCTRL]
134                          : ci_regs_nolpm[OP_ENDPTCTRL]);
135 
136         return 0;
137 }
138 
139 /**
140  * hw_read_intr_enable: returns interrupt enable register
141  *
142  * This function returns register data
143  */
144 u32 hw_read_intr_enable(struct ci_hdrc *ci)
145 {
146         return hw_read(ci, OP_USBINTR, ~0);
147 }
148 
149 /**
150  * hw_read_intr_status: returns interrupt status register
151  *
152  * This function returns register data
153  */
154 u32 hw_read_intr_status(struct ci_hdrc *ci)
155 {
156         return hw_read(ci, OP_USBSTS, ~0);
157 }
158 
159 /**
160  * hw_port_test_set: writes port test mode (execute without interruption)
161  * @mode: new value
162  *
163  * This function returns an error code
164  */
165 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
166 {
167         const u8 TEST_MODE_MAX = 7;
168 
169         if (mode > TEST_MODE_MAX)
170                 return -EINVAL;
171 
172         hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
173         return 0;
174 }
175 
176 /**
177  * hw_port_test_get: reads port test mode value
178  *
179  * This function returns port test mode value
180  */
181 u8 hw_port_test_get(struct ci_hdrc *ci)
182 {
183         return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
184 }
185 
186 /* The PHY enters/leaves low power mode */
187 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
188 {
189         enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
190         bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
191 
192         if (enable && !lpm) {
193                 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
194                                 PORTSC_PHCD(ci->hw_bank.lpm));
195         } else  if (!enable && lpm) {
196                 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
197                                 0);
198                 /* 
199                  * the PHY needs some time (less
200                  * than 1ms) to leave low power mode.
201                  */
202                 usleep_range(1000, 1100);
203         }
204 }
205 
206 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
207 {
208         u32 reg;
209 
210         /* bank is a module variable */
211         ci->hw_bank.abs = base;
212 
213         ci->hw_bank.cap = ci->hw_bank.abs;
214         ci->hw_bank.cap += ci->platdata->capoffset;
215         ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
216 
217         hw_alloc_regmap(ci, false);
218         reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
219                 __ffs(HCCPARAMS_LEN);
220         ci->hw_bank.lpm  = reg;
221         if (reg)
222                 hw_alloc_regmap(ci, !!reg);
223         ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
224         ci->hw_bank.size += OP_LAST;
225         ci->hw_bank.size /= sizeof(u32);
226 
227         reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
228                 __ffs(DCCPARAMS_DEN);
229         ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */
230 
231         if (ci->hw_ep_max > ENDPT_MAX)
232                 return -ENODEV;
233 
234         ci_hdrc_enter_lpm(ci, false);
235 
236         /* Disable all interrupts bits */
237         hw_write(ci, OP_USBINTR, 0xffffffff, 0);
238 
239         /* Clear all interrupts status bits*/
240         hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
241 
242         dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
243                 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
244 
245         /* setup lock mode ? */
246 
247         /* ENDPTSETUPSTAT is '' by default */
248 
249         /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
250 
251         return 0;
252 }
253 
254 static void hw_phymode_configure(struct ci_hdrc *ci)
255 {
256         u32 portsc, lpm, sts = 0;
257 
258         switch (ci->platdata->phy_mode) {
259         case USBPHY_INTERFACE_MODE_UTMI:
260                 portsc = PORTSC_PTS(PTS_UTMI);
261                 lpm = DEVLC_PTS(PTS_UTMI);
262                 break;
263         case USBPHY_INTERFACE_MODE_UTMIW:
264                 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
265                 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
266                 break;
267         case USBPHY_INTERFACE_MODE_ULPI:
268                 portsc = PORTSC_PTS(PTS_ULPI);
269                 lpm = DEVLC_PTS(PTS_ULPI);
270                 break;
271         case USBPHY_INTERFACE_MODE_SERIAL:
272                 portsc = PORTSC_PTS(PTS_SERIAL);
273                 lpm = DEVLC_PTS(PTS_SERIAL);
274                 sts = 1;
275                 break;
276         case USBPHY_INTERFACE_MODE_HSIC:
277                 portsc = PORTSC_PTS(PTS_HSIC);
278                 lpm = DEVLC_PTS(PTS_HSIC);
279                 break;
280         default:
281                 return;
282         }
283 
284         if (ci->hw_bank.lpm) {
285                 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
286                 if (sts)
287                         hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
288         } else {
289                 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
290                 if (sts)
291                         hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
292         }
293 }
294 
295 /**
296  * ci_usb_phy_init: initialize phy according to different phy type
297  * @ci: the controller
298   *
299  * This function returns an error code if usb_phy_init has failed
300  */
301 static int ci_usb_phy_init(struct ci_hdrc *ci)
302 {
303         int ret;
304 
305         switch (ci->platdata->phy_mode) {
306         case USBPHY_INTERFACE_MODE_UTMI:
307         case USBPHY_INTERFACE_MODE_UTMIW:
308         case USBPHY_INTERFACE_MODE_HSIC:
309                 ret = usb_phy_init(ci->transceiver);
310                 if (ret)
311                         return ret;
312                 hw_phymode_configure(ci);
313                 break;
314         case USBPHY_INTERFACE_MODE_ULPI:
315         case USBPHY_INTERFACE_MODE_SERIAL:
316                 hw_phymode_configure(ci);
317                 ret = usb_phy_init(ci->transceiver);
318                 if (ret)
319                         return ret;
320                 break;
321         default:
322                 ret = usb_phy_init(ci->transceiver);
323         }
324 
325         return ret;
326 }
327 
328 /**
329  * hw_device_reset: resets chip (execute without interruption)
330  * @ci: the controller
331   *
332  * This function returns an error code
333  */
334 int hw_device_reset(struct ci_hdrc *ci, u32 mode)
335 {
336         /* should flush & stop before reset */
337         hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
338         hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
339 
340         hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
341         while (hw_read(ci, OP_USBCMD, USBCMD_RST))
342                 udelay(10);             /* not RTOS friendly */
343 
344         if (ci->platdata->notify_event)
345                 ci->platdata->notify_event(ci,
346                         CI_HDRC_CONTROLLER_RESET_EVENT);
347 
348         if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
349                 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
350 
351         if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
352                 if (ci->hw_bank.lpm)
353                         hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
354                 else
355                         hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
356         }
357 
358         /* USBMODE should be configured step by step */
359         hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
360         hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
361         /* HW >= 2.3 */
362         hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
363 
364         if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
365                 pr_err("cannot enter in %s mode", ci_role(ci)->name);
366                 pr_err("lpm = %i", ci->hw_bank.lpm);
367                 return -ENODEV;
368         }
369 
370         return 0;
371 }
372 
373 /**
374  * hw_wait_reg: wait the register value
375  *
376  * Sometimes, it needs to wait register value before going on.
377  * Eg, when switch to device mode, the vbus value should be lower
378  * than OTGSC_BSV before connects to host.
379  *
380  * @ci: the controller
381  * @reg: register index
382  * @mask: mast bit
383  * @value: the bit value to wait
384  * @timeout_ms: timeout in millisecond
385  *
386  * This function returns an error code if timeout
387  */
388 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
389                                 u32 value, unsigned int timeout_ms)
390 {
391         unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
392 
393         while (hw_read(ci, reg, mask) != value) {
394                 if (time_after(jiffies, elapse)) {
395                         dev_err(ci->dev, "timeout waiting for %08x in %d\n",
396                                         mask, reg);
397                         return -ETIMEDOUT;
398                 }
399                 msleep(20);
400         }
401 
402         return 0;
403 }
404 
405 static irqreturn_t ci_irq(int irq, void *data)
406 {
407         struct ci_hdrc *ci = data;
408         irqreturn_t ret = IRQ_NONE;
409         u32 otgsc = 0;
410 
411         if (ci->is_otg) {
412                 otgsc = hw_read_otgsc(ci, ~0);
413                 if (ci_otg_is_fsm_mode(ci)) {
414                         ret = ci_otg_fsm_irq(ci);
415                         if (ret == IRQ_HANDLED)
416                                 return ret;
417                 }
418         }
419 
420         /*
421          * Handle id change interrupt, it indicates device/host function
422          * switch.
423          */
424         if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
425                 ci->id_event = true;
426                 /* Clear ID change irq status */
427                 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
428                 ci_otg_queue_work(ci);
429                 return IRQ_HANDLED;
430         }
431 
432         /*
433          * Handle vbus change interrupt, it indicates device connection
434          * and disconnection events.
435          */
436         if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
437                 ci->b_sess_valid_event = true;
438                 /* Clear BSV irq */
439                 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
440                 ci_otg_queue_work(ci);
441                 return IRQ_HANDLED;
442         }
443 
444         /* Handle device/host interrupt */
445         if (ci->role != CI_ROLE_END)
446                 ret = ci_role(ci)->irq(ci);
447 
448         return ret;
449 }
450 
451 static int ci_get_platdata(struct device *dev,
452                 struct ci_hdrc_platform_data *platdata)
453 {
454         if (!platdata->phy_mode)
455                 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
456 
457         if (!platdata->dr_mode)
458                 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
459 
460         if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
461                 platdata->dr_mode = USB_DR_MODE_OTG;
462 
463         if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
464                 /* Get the vbus regulator */
465                 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
466                 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
467                         return -EPROBE_DEFER;
468                 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
469                         /* no vbus regualator is needed */
470                         platdata->reg_vbus = NULL;
471                 } else if (IS_ERR(platdata->reg_vbus)) {
472                         dev_err(dev, "Getting regulator error: %ld\n",
473                                 PTR_ERR(platdata->reg_vbus));
474                         return PTR_ERR(platdata->reg_vbus);
475                 }
476         }
477 
478         if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
479                 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
480 
481         return 0;
482 }
483 
484 static DEFINE_IDA(ci_ida);
485 
486 struct platform_device *ci_hdrc_add_device(struct device *dev,
487                         struct resource *res, int nres,
488                         struct ci_hdrc_platform_data *platdata)
489 {
490         struct platform_device *pdev;
491         int id, ret;
492 
493         ret = ci_get_platdata(dev, platdata);
494         if (ret)
495                 return ERR_PTR(ret);
496 
497         id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
498         if (id < 0)
499                 return ERR_PTR(id);
500 
501         pdev = platform_device_alloc("ci_hdrc", id);
502         if (!pdev) {
503                 ret = -ENOMEM;
504                 goto put_id;
505         }
506 
507         pdev->dev.parent = dev;
508         pdev->dev.dma_mask = dev->dma_mask;
509         pdev->dev.dma_parms = dev->dma_parms;
510         dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
511 
512         ret = platform_device_add_resources(pdev, res, nres);
513         if (ret)
514                 goto err;
515 
516         ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
517         if (ret)
518                 goto err;
519 
520         ret = platform_device_add(pdev);
521         if (ret)
522                 goto err;
523 
524         return pdev;
525 
526 err:
527         platform_device_put(pdev);
528 put_id:
529         ida_simple_remove(&ci_ida, id);
530         return ERR_PTR(ret);
531 }
532 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
533 
534 void ci_hdrc_remove_device(struct platform_device *pdev)
535 {
536         int id = pdev->id;
537         platform_device_unregister(pdev);
538         ida_simple_remove(&ci_ida, id);
539 }
540 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
541 
542 static inline void ci_role_destroy(struct ci_hdrc *ci)
543 {
544         ci_hdrc_gadget_destroy(ci);
545         ci_hdrc_host_destroy(ci);
546         if (ci->is_otg)
547                 ci_hdrc_otg_destroy(ci);
548 }
549 
550 static void ci_get_otg_capable(struct ci_hdrc *ci)
551 {
552         if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
553                 ci->is_otg = false;
554         else
555                 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
556                                 DCCPARAMS_DC | DCCPARAMS_HC)
557                                         == (DCCPARAMS_DC | DCCPARAMS_HC));
558         if (ci->is_otg)
559                 dev_dbg(ci->dev, "It is OTG capable controller\n");
560 }
561 
562 static int ci_hdrc_probe(struct platform_device *pdev)
563 {
564         struct device   *dev = &pdev->dev;
565         struct ci_hdrc  *ci;
566         struct resource *res;
567         void __iomem    *base;
568         int             ret;
569         enum usb_dr_mode dr_mode;
570 
571         if (!dev_get_platdata(dev)) {
572                 dev_err(dev, "platform data missing\n");
573                 return -ENODEV;
574         }
575 
576         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
577         base = devm_ioremap_resource(dev, res);
578         if (IS_ERR(base))
579                 return PTR_ERR(base);
580 
581         ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
582         if (!ci) {
583                 dev_err(dev, "can't allocate device\n");
584                 return -ENOMEM;
585         }
586 
587         ci->dev = dev;
588         ci->platdata = dev_get_platdata(dev);
589         ci->imx28_write_fix = !!(ci->platdata->flags &
590                 CI_HDRC_IMX28_WRITE_FIX);
591 
592         ret = hw_device_init(ci, base);
593         if (ret < 0) {
594                 dev_err(dev, "can't initialize hardware\n");
595                 return -ENODEV;
596         }
597 
598         if (ci->platdata->phy)
599                 ci->transceiver = ci->platdata->phy;
600         else
601                 ci->transceiver = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
602 
603         if (IS_ERR(ci->transceiver)) {
604                 ret = PTR_ERR(ci->transceiver);
605                 /*
606                  * if -ENXIO is returned, it means PHY layer wasn't
607                  * enabled, so it makes no sense to return -EPROBE_DEFER
608                  * in that case, since no PHY driver will ever probe.
609                  */
610                 if (ret == -ENXIO)
611                         return ret;
612 
613                 dev_err(dev, "no usb2 phy configured\n");
614                 return -EPROBE_DEFER;
615         }
616 
617         ret = ci_usb_phy_init(ci);
618         if (ret) {
619                 dev_err(dev, "unable to init phy: %d\n", ret);
620                 return ret;
621         } else {
622                 /* 
623                  * The delay to sync PHY's status, the maximum delay is
624                  * 2ms since the otgsc uses 1ms timer to debounce the
625                  * PHY's input
626                  */
627                 usleep_range(2000, 2500);
628         }
629 
630         ci->hw_bank.phys = res->start;
631 
632         ci->irq = platform_get_irq(pdev, 0);
633         if (ci->irq < 0) {
634                 dev_err(dev, "missing IRQ\n");
635                 ret = ci->irq;
636                 goto deinit_phy;
637         }
638 
639         ci_get_otg_capable(ci);
640 
641         dr_mode = ci->platdata->dr_mode;
642         /* initialize role(s) before the interrupt is requested */
643         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
644                 ret = ci_hdrc_host_init(ci);
645                 if (ret)
646                         dev_info(dev, "doesn't support host\n");
647         }
648 
649         if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
650                 ret = ci_hdrc_gadget_init(ci);
651                 if (ret)
652                         dev_info(dev, "doesn't support gadget\n");
653         }
654 
655         if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
656                 dev_err(dev, "no supported roles\n");
657                 ret = -ENODEV;
658                 goto deinit_phy;
659         }
660 
661         if (ci->is_otg) {
662                 /* Disable and clear all OTG irq */
663                 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
664                                                         OTGSC_INT_STATUS_BITS);
665                 ret = ci_hdrc_otg_init(ci);
666                 if (ret) {
667                         dev_err(dev, "init otg fails, ret = %d\n", ret);
668                         goto stop;
669                 }
670         }
671 
672         if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
673                 if (ci->is_otg) {
674                         ci->role = ci_otg_role(ci);
675                         /* Enable ID change irq */
676                         hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
677                 } else {
678                         /*
679                          * If the controller is not OTG capable, but support
680                          * role switch, the defalt role is gadget, and the
681                          * user can switch it through debugfs.
682                          */
683                         ci->role = CI_ROLE_GADGET;
684                 }
685         } else {
686                 ci->role = ci->roles[CI_ROLE_HOST]
687                         ? CI_ROLE_HOST
688                         : CI_ROLE_GADGET;
689         }
690 
691         /* only update vbus status for peripheral */
692         if (ci->role == CI_ROLE_GADGET)
693                 ci_handle_vbus_change(ci);
694 
695         if (!ci_otg_is_fsm_mode(ci)) {
696                 ret = ci_role_start(ci, ci->role);
697                 if (ret) {
698                         dev_err(dev, "can't start %s role\n",
699                                                 ci_role(ci)->name);
700                         goto stop;
701                 }
702         }
703 
704         platform_set_drvdata(pdev, ci);
705         ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
706                           ci);
707         if (ret)
708                 goto stop;
709 
710         if (ci_otg_is_fsm_mode(ci))
711                 ci_hdrc_otg_fsm_start(ci);
712 
713         ret = dbg_create_files(ci);
714         if (!ret)
715                 return 0;
716 
717         free_irq(ci->irq, ci);
718 stop:
719         ci_role_destroy(ci);
720 deinit_phy:
721         usb_phy_shutdown(ci->transceiver);
722 
723         return ret;
724 }
725 
726 static int ci_hdrc_remove(struct platform_device *pdev)
727 {
728         struct ci_hdrc *ci = platform_get_drvdata(pdev);
729 
730         dbg_remove_files(ci);
731         free_irq(ci->irq, ci);
732         ci_role_destroy(ci);
733         ci_hdrc_enter_lpm(ci, true);
734         usb_phy_shutdown(ci->transceiver);
735         kfree(ci->hw_bank.regmap);
736 
737         return 0;
738 }
739 
740 static struct platform_driver ci_hdrc_driver = {
741         .probe  = ci_hdrc_probe,
742         .remove = ci_hdrc_remove,
743         .driver = {
744                 .name   = "ci_hdrc",
745                 .owner  = THIS_MODULE,
746         },
747 };
748 
749 module_platform_driver(ci_hdrc_driver);
750 
751 MODULE_ALIAS("platform:ci_hdrc");
752 MODULE_LICENSE("GPL v2");
753 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
754 MODULE_DESCRIPTION("ChipIdea HDRC Driver");
755 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us