Version:  2.0.40 2.2.26 2.4.37 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2

Linux/drivers/tty/synclinkmp.c

  1 /*
  2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
  3  *
  4  * Device driver for Microgate SyncLink Multiport
  5  * high speed multiprotocol serial adapter.
  6  *
  7  * written by Paul Fulghum for Microgate Corporation
  8  * paulkf@microgate.com
  9  *
 10  * Microgate and SyncLink are trademarks of Microgate Corporation
 11  *
 12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
 13  * This code is released under the GNU General Public License (GPL)
 14  *
 15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
 19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
 25  * OF THE POSSIBILITY OF SUCH DAMAGE.
 26  */
 27 
 28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
 29 #if defined(__i386__)
 30 #  define BREAKPOINT() asm("   int $3");
 31 #else
 32 #  define BREAKPOINT() { }
 33 #endif
 34 
 35 #define MAX_DEVICES 12
 36 
 37 #include <linux/module.h>
 38 #include <linux/errno.h>
 39 #include <linux/signal.h>
 40 #include <linux/sched.h>
 41 #include <linux/timer.h>
 42 #include <linux/interrupt.h>
 43 #include <linux/pci.h>
 44 #include <linux/tty.h>
 45 #include <linux/tty_flip.h>
 46 #include <linux/serial.h>
 47 #include <linux/major.h>
 48 #include <linux/string.h>
 49 #include <linux/fcntl.h>
 50 #include <linux/ptrace.h>
 51 #include <linux/ioport.h>
 52 #include <linux/mm.h>
 53 #include <linux/seq_file.h>
 54 #include <linux/slab.h>
 55 #include <linux/netdevice.h>
 56 #include <linux/vmalloc.h>
 57 #include <linux/init.h>
 58 #include <linux/delay.h>
 59 #include <linux/ioctl.h>
 60 
 61 #include <asm/io.h>
 62 #include <asm/irq.h>
 63 #include <asm/dma.h>
 64 #include <linux/bitops.h>
 65 #include <asm/types.h>
 66 #include <linux/termios.h>
 67 #include <linux/workqueue.h>
 68 #include <linux/hdlc.h>
 69 #include <linux/synclink.h>
 70 
 71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
 72 #define SYNCLINK_GENERIC_HDLC 1
 73 #else
 74 #define SYNCLINK_GENERIC_HDLC 0
 75 #endif
 76 
 77 #define GET_USER(error,value,addr) error = get_user(value,addr)
 78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
 79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
 80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
 81 
 82 #include <asm/uaccess.h>
 83 
 84 static MGSL_PARAMS default_params = {
 85         MGSL_MODE_HDLC,                 /* unsigned long mode */
 86         0,                              /* unsigned char loopback; */
 87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
 88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
 89         0,                              /* unsigned long clock_speed; */
 90         0xff,                           /* unsigned char addr_filter; */
 91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
 92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
 93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
 94         9600,                           /* unsigned long data_rate; */
 95         8,                              /* unsigned char data_bits; */
 96         1,                              /* unsigned char stop_bits; */
 97         ASYNC_PARITY_NONE               /* unsigned char parity; */
 98 };
 99 
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE      1024
102 #define SCA_MEM_SIZE    0x40000
103 #define SCA_BASE_SIZE   512
104 #define SCA_REG_SIZE    16
105 #define SCA_MAX_PORTS   4
106 #define SCAMAXDESC      128
107 
108 #define BUFFERLISTSIZE  4096
109 
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
112 {
113         u16     next;           /* lower l6 bits of next descriptor addr */
114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
115         u8      buf_base;       /* upper 8 bits of buffer addr */
116         u8      pad1;
117         u16     length;         /* length of buffer */
118         u8      status;         /* status of buffer */
119         u8      pad2;
120 } SCADESC, *PSCADESC;
121 
122 typedef struct _SCADESC_EX
123 {
124         /* device driver bookkeeping section */
125         char    *virt_addr;     /* virtual address of data buffer */
126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
128 
129 /* The queue of BH actions to be performed */
130 
131 #define BH_RECEIVE  1
132 #define BH_TRANSMIT 2
133 #define BH_STATUS   4
134 
135 #define IO_PIN_SHUTDOWN_LIMIT 100
136 
137 struct  _input_signal_events {
138         int     ri_up;
139         int     ri_down;
140         int     dsr_up;
141         int     dsr_down;
142         int     dcd_up;
143         int     dcd_down;
144         int     cts_up;
145         int     cts_down;
146 };
147 
148 /*
149  * Device instance data structure
150  */
151 typedef struct _synclinkmp_info {
152         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
153         int                     magic;
154         struct tty_port         port;
155         int                     line;
156         unsigned short          close_delay;
157         unsigned short          closing_wait;   /* time to wait before closing */
158 
159         struct mgsl_icount      icount;
160 
161         int                     timeout;
162         int                     x_char;         /* xon/xoff character */
163         u16                     read_status_mask1;  /* break detection (SR1 indications) */
164         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
165         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
166         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
167         unsigned char           *tx_buf;
168         int                     tx_put;
169         int                     tx_get;
170         int                     tx_count;
171 
172         wait_queue_head_t       status_event_wait_q;
173         wait_queue_head_t       event_wait_q;
174         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
175         struct _synclinkmp_info *next_device;   /* device list link */
176         struct timer_list       status_timer;   /* input signal status check timer */
177 
178         spinlock_t lock;                /* spinlock for synchronizing with ISR */
179         struct work_struct task;                        /* task structure for scheduling bh */
180 
181         u32 max_frame_size;                     /* as set by device config */
182 
183         u32 pending_bh;
184 
185         bool bh_running;                                /* Protection from multiple */
186         int isr_overflow;
187         bool bh_requested;
188 
189         int dcd_chkcount;                       /* check counts to prevent */
190         int cts_chkcount;                       /* too many IRQs if a signal */
191         int dsr_chkcount;                       /* is floating */
192         int ri_chkcount;
193 
194         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
195         unsigned long buffer_list_phys;
196 
197         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
198         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
199         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200         unsigned int current_rx_buf;
201 
202         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
203         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
204         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205         unsigned int last_tx_buf;
206 
207         unsigned char *tmp_rx_buf;
208         unsigned int tmp_rx_buf_count;
209 
210         bool rx_enabled;
211         bool rx_overflow;
212 
213         bool tx_enabled;
214         bool tx_active;
215         u32 idle_mode;
216 
217         unsigned char ie0_value;
218         unsigned char ie1_value;
219         unsigned char ie2_value;
220         unsigned char ctrlreg_value;
221         unsigned char old_signals;
222 
223         char device_name[25];                   /* device instance name */
224 
225         int port_count;
226         int adapter_num;
227         int port_num;
228 
229         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230 
231         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
232 
233         unsigned int irq_level;                 /* interrupt level */
234         unsigned long irq_flags;
235         bool irq_requested;                     /* true if IRQ requested */
236 
237         MGSL_PARAMS params;                     /* communications parameters */
238 
239         unsigned char serial_signals;           /* current serial signal states */
240 
241         bool irq_occurred;                      /* for diagnostics use */
242         unsigned int init_error;                /* Initialization startup error */
243 
244         u32 last_mem_alloc;
245         unsigned char* memory_base;             /* shared memory address (PCI only) */
246         u32 phys_memory_base;
247         int shared_mem_requested;
248 
249         unsigned char* sca_base;                /* HD64570 SCA Memory address */
250         u32 phys_sca_base;
251         u32 sca_offset;
252         bool sca_base_requested;
253 
254         unsigned char* lcr_base;                /* local config registers (PCI only) */
255         u32 phys_lcr_base;
256         u32 lcr_offset;
257         int lcr_mem_requested;
258 
259         unsigned char* statctrl_base;           /* status/control register memory */
260         u32 phys_statctrl_base;
261         u32 statctrl_offset;
262         bool sca_statctrl_requested;
263 
264         u32 misc_ctrl_value;
265         char *flag_buf;
266         bool drop_rts_on_tx_done;
267 
268         struct  _input_signal_events    input_signal_events;
269 
270         /* SPPP/Cisco HDLC device parts */
271         int netcount;
272         spinlock_t netlock;
273 
274 #if SYNCLINK_GENERIC_HDLC
275         struct net_device *netdev;
276 #endif
277 
278 } SLMP_INFO;
279 
280 #define MGSL_MAGIC 0x5401
281 
282 /*
283  * define serial signal status change macros
284  */
285 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
286 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
287 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
288 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
289 
290 /* Common Register macros */
291 #define LPR     0x00
292 #define PABR0   0x02
293 #define PABR1   0x03
294 #define WCRL    0x04
295 #define WCRM    0x05
296 #define WCRH    0x06
297 #define DPCR    0x08
298 #define DMER    0x09
299 #define ISR0    0x10
300 #define ISR1    0x11
301 #define ISR2    0x12
302 #define IER0    0x14
303 #define IER1    0x15
304 #define IER2    0x16
305 #define ITCR    0x18
306 #define INTVR   0x1a
307 #define IMVR    0x1c
308 
309 /* MSCI Register macros */
310 #define TRB     0x20
311 #define TRBL    0x20
312 #define TRBH    0x21
313 #define SR0     0x22
314 #define SR1     0x23
315 #define SR2     0x24
316 #define SR3     0x25
317 #define FST     0x26
318 #define IE0     0x28
319 #define IE1     0x29
320 #define IE2     0x2a
321 #define FIE     0x2b
322 #define CMD     0x2c
323 #define MD0     0x2e
324 #define MD1     0x2f
325 #define MD2     0x30
326 #define CTL     0x31
327 #define SA0     0x32
328 #define SA1     0x33
329 #define IDL     0x34
330 #define TMC     0x35
331 #define RXS     0x36
332 #define TXS     0x37
333 #define TRC0    0x38
334 #define TRC1    0x39
335 #define RRC     0x3a
336 #define CST0    0x3c
337 #define CST1    0x3d
338 
339 /* Timer Register Macros */
340 #define TCNT    0x60
341 #define TCNTL   0x60
342 #define TCNTH   0x61
343 #define TCONR   0x62
344 #define TCONRL  0x62
345 #define TCONRH  0x63
346 #define TMCS    0x64
347 #define TEPR    0x65
348 
349 /* DMA Controller Register macros */
350 #define DARL    0x80
351 #define DARH    0x81
352 #define DARB    0x82
353 #define BAR     0x80
354 #define BARL    0x80
355 #define BARH    0x81
356 #define BARB    0x82
357 #define SAR     0x84
358 #define SARL    0x84
359 #define SARH    0x85
360 #define SARB    0x86
361 #define CPB     0x86
362 #define CDA     0x88
363 #define CDAL    0x88
364 #define CDAH    0x89
365 #define EDA     0x8a
366 #define EDAL    0x8a
367 #define EDAH    0x8b
368 #define BFL     0x8c
369 #define BFLL    0x8c
370 #define BFLH    0x8d
371 #define BCR     0x8e
372 #define BCRL    0x8e
373 #define BCRH    0x8f
374 #define DSR     0x90
375 #define DMR     0x91
376 #define FCT     0x93
377 #define DIR     0x94
378 #define DCMD    0x95
379 
380 /* combine with timer or DMA register address */
381 #define TIMER0  0x00
382 #define TIMER1  0x08
383 #define TIMER2  0x10
384 #define TIMER3  0x18
385 #define RXDMA   0x00
386 #define TXDMA   0x20
387 
388 /* SCA Command Codes */
389 #define NOOP            0x00
390 #define TXRESET         0x01
391 #define TXENABLE        0x02
392 #define TXDISABLE       0x03
393 #define TXCRCINIT       0x04
394 #define TXCRCEXCL       0x05
395 #define TXEOM           0x06
396 #define TXABORT         0x07
397 #define MPON            0x08
398 #define TXBUFCLR        0x09
399 #define RXRESET         0x11
400 #define RXENABLE        0x12
401 #define RXDISABLE       0x13
402 #define RXCRCINIT       0x14
403 #define RXREJECT        0x15
404 #define SEARCHMP        0x16
405 #define RXCRCEXCL       0x17
406 #define RXCRCCALC       0x18
407 #define CHRESET         0x21
408 #define HUNT            0x31
409 
410 /* DMA command codes */
411 #define SWABORT         0x01
412 #define FEICLEAR        0x02
413 
414 /* IE0 */
415 #define TXINTE          BIT7
416 #define RXINTE          BIT6
417 #define TXRDYE          BIT1
418 #define RXRDYE          BIT0
419 
420 /* IE1 & SR1 */
421 #define UDRN    BIT7
422 #define IDLE    BIT6
423 #define SYNCD   BIT4
424 #define FLGD    BIT4
425 #define CCTS    BIT3
426 #define CDCD    BIT2
427 #define BRKD    BIT1
428 #define ABTD    BIT1
429 #define GAPD    BIT1
430 #define BRKE    BIT0
431 #define IDLD    BIT0
432 
433 /* IE2 & SR2 */
434 #define EOM     BIT7
435 #define PMP     BIT6
436 #define SHRT    BIT6
437 #define PE      BIT5
438 #define ABT     BIT5
439 #define FRME    BIT4
440 #define RBIT    BIT4
441 #define OVRN    BIT3
442 #define CRCE    BIT2
443 
444 
445 /*
446  * Global linked list of SyncLink devices
447  */
448 static SLMP_INFO *synclinkmp_device_list = NULL;
449 static int synclinkmp_adapter_count = -1;
450 static int synclinkmp_device_count = 0;
451 
452 /*
453  * Set this param to non-zero to load eax with the
454  * .text section address and breakpoint on module load.
455  * This is useful for use with gdb and add-symbol-file command.
456  */
457 static bool break_on_load = 0;
458 
459 /*
460  * Driver major number, defaults to zero to get auto
461  * assigned major number. May be forced as module parameter.
462  */
463 static int ttymajor = 0;
464 
465 /*
466  * Array of user specified options for ISA adapters.
467  */
468 static int debug_level = 0;
469 static int maxframe[MAX_DEVICES] = {0,};
470 
471 module_param(break_on_load, bool, 0);
472 module_param(ttymajor, int, 0);
473 module_param(debug_level, int, 0);
474 module_param_array(maxframe, int, NULL, 0);
475 
476 static char *driver_name = "SyncLink MultiPort driver";
477 static char *driver_version = "$Revision: 4.38 $";
478 
479 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
480 static void synclinkmp_remove_one(struct pci_dev *dev);
481 
482 static struct pci_device_id synclinkmp_pci_tbl[] = {
483         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
484         { 0, }, /* terminate list */
485 };
486 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
487 
488 MODULE_LICENSE("GPL");
489 
490 static struct pci_driver synclinkmp_pci_driver = {
491         .name           = "synclinkmp",
492         .id_table       = synclinkmp_pci_tbl,
493         .probe          = synclinkmp_init_one,
494         .remove         = synclinkmp_remove_one,
495 };
496 
497 
498 static struct tty_driver *serial_driver;
499 
500 /* number of characters left in xmit buffer before we ask for more */
501 #define WAKEUP_CHARS 256
502 
503 
504 /* tty callbacks */
505 
506 static int  open(struct tty_struct *tty, struct file * filp);
507 static void close(struct tty_struct *tty, struct file * filp);
508 static void hangup(struct tty_struct *tty);
509 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
510 
511 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
512 static int put_char(struct tty_struct *tty, unsigned char ch);
513 static void send_xchar(struct tty_struct *tty, char ch);
514 static void wait_until_sent(struct tty_struct *tty, int timeout);
515 static int  write_room(struct tty_struct *tty);
516 static void flush_chars(struct tty_struct *tty);
517 static void flush_buffer(struct tty_struct *tty);
518 static void tx_hold(struct tty_struct *tty);
519 static void tx_release(struct tty_struct *tty);
520 
521 static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
522 static int  chars_in_buffer(struct tty_struct *tty);
523 static void throttle(struct tty_struct * tty);
524 static void unthrottle(struct tty_struct * tty);
525 static int set_break(struct tty_struct *tty, int break_state);
526 
527 #if SYNCLINK_GENERIC_HDLC
528 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
529 static void hdlcdev_tx_done(SLMP_INFO *info);
530 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
531 static int  hdlcdev_init(SLMP_INFO *info);
532 static void hdlcdev_exit(SLMP_INFO *info);
533 #endif
534 
535 /* ioctl handlers */
536 
537 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
538 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
539 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
541 static int  set_txidle(SLMP_INFO *info, int idle_mode);
542 static int  tx_enable(SLMP_INFO *info, int enable);
543 static int  tx_abort(SLMP_INFO *info);
544 static int  rx_enable(SLMP_INFO *info, int enable);
545 static int  modem_input_wait(SLMP_INFO *info,int arg);
546 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
547 static int  tiocmget(struct tty_struct *tty);
548 static int  tiocmset(struct tty_struct *tty,
549                         unsigned int set, unsigned int clear);
550 static int  set_break(struct tty_struct *tty, int break_state);
551 
552 static void add_device(SLMP_INFO *info);
553 static void device_init(int adapter_num, struct pci_dev *pdev);
554 static int  claim_resources(SLMP_INFO *info);
555 static void release_resources(SLMP_INFO *info);
556 
557 static int  startup(SLMP_INFO *info);
558 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
559 static int carrier_raised(struct tty_port *port);
560 static void shutdown(SLMP_INFO *info);
561 static void program_hw(SLMP_INFO *info);
562 static void change_params(SLMP_INFO *info);
563 
564 static bool init_adapter(SLMP_INFO *info);
565 static bool register_test(SLMP_INFO *info);
566 static bool irq_test(SLMP_INFO *info);
567 static bool loopback_test(SLMP_INFO *info);
568 static int  adapter_test(SLMP_INFO *info);
569 static bool memory_test(SLMP_INFO *info);
570 
571 static void reset_adapter(SLMP_INFO *info);
572 static void reset_port(SLMP_INFO *info);
573 static void async_mode(SLMP_INFO *info);
574 static void hdlc_mode(SLMP_INFO *info);
575 
576 static void rx_stop(SLMP_INFO *info);
577 static void rx_start(SLMP_INFO *info);
578 static void rx_reset_buffers(SLMP_INFO *info);
579 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
580 static bool rx_get_frame(SLMP_INFO *info);
581 
582 static void tx_start(SLMP_INFO *info);
583 static void tx_stop(SLMP_INFO *info);
584 static void tx_load_fifo(SLMP_INFO *info);
585 static void tx_set_idle(SLMP_INFO *info);
586 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
587 
588 static void get_signals(SLMP_INFO *info);
589 static void set_signals(SLMP_INFO *info);
590 static void enable_loopback(SLMP_INFO *info, int enable);
591 static void set_rate(SLMP_INFO *info, u32 data_rate);
592 
593 static int  bh_action(SLMP_INFO *info);
594 static void bh_handler(struct work_struct *work);
595 static void bh_receive(SLMP_INFO *info);
596 static void bh_transmit(SLMP_INFO *info);
597 static void bh_status(SLMP_INFO *info);
598 static void isr_timer(SLMP_INFO *info);
599 static void isr_rxint(SLMP_INFO *info);
600 static void isr_rxrdy(SLMP_INFO *info);
601 static void isr_txint(SLMP_INFO *info);
602 static void isr_txrdy(SLMP_INFO *info);
603 static void isr_rxdmaok(SLMP_INFO *info);
604 static void isr_rxdmaerror(SLMP_INFO *info);
605 static void isr_txdmaok(SLMP_INFO *info);
606 static void isr_txdmaerror(SLMP_INFO *info);
607 static void isr_io_pin(SLMP_INFO *info, u16 status);
608 
609 static int  alloc_dma_bufs(SLMP_INFO *info);
610 static void free_dma_bufs(SLMP_INFO *info);
611 static int  alloc_buf_list(SLMP_INFO *info);
612 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
613 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
614 static void free_tmp_rx_buf(SLMP_INFO *info);
615 
616 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
617 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
618 static void tx_timeout(unsigned long context);
619 static void status_timeout(unsigned long context);
620 
621 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
623 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
624 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
625 static unsigned char read_status_reg(SLMP_INFO * info);
626 static void write_control_reg(SLMP_INFO * info);
627 
628 
629 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
630 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
631 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
632 
633 static u32 misc_ctrl_value = 0x007e4040;
634 static u32 lcr1_brdr_value = 0x00800028;
635 
636 static u32 read_ahead_count = 8;
637 
638 /* DPCR, DMA Priority Control
639  *
640  * 07..05  Not used, must be 0
641  * 04      BRC, bus release condition: 0=all transfers complete
642  *              1=release after 1 xfer on all channels
643  * 03      CCC, channel change condition: 0=every cycle
644  *              1=after each channel completes all xfers
645  * 02..00  PR<2..0>, priority 100=round robin
646  *
647  * 00000100 = 0x00
648  */
649 static unsigned char dma_priority = 0x04;
650 
651 // Number of bytes that can be written to shared RAM
652 // in a single write operation
653 static u32 sca_pci_load_interval = 64;
654 
655 /*
656  * 1st function defined in .text section. Calling this function in
657  * init_module() followed by a breakpoint allows a remote debugger
658  * (gdb) to get the .text address for the add-symbol-file command.
659  * This allows remote debugging of dynamically loadable modules.
660  */
661 static void* synclinkmp_get_text_ptr(void);
662 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
663 
664 static inline int sanity_check(SLMP_INFO *info,
665                                char *name, const char *routine)
666 {
667 #ifdef SANITY_CHECK
668         static const char *badmagic =
669                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
670         static const char *badinfo =
671                 "Warning: null synclinkmp_struct for (%s) in %s\n";
672 
673         if (!info) {
674                 printk(badinfo, name, routine);
675                 return 1;
676         }
677         if (info->magic != MGSL_MAGIC) {
678                 printk(badmagic, name, routine);
679                 return 1;
680         }
681 #else
682         if (!info)
683                 return 1;
684 #endif
685         return 0;
686 }
687 
688 /**
689  * line discipline callback wrappers
690  *
691  * The wrappers maintain line discipline references
692  * while calling into the line discipline.
693  *
694  * ldisc_receive_buf  - pass receive data to line discipline
695  */
696 
697 static void ldisc_receive_buf(struct tty_struct *tty,
698                               const __u8 *data, char *flags, int count)
699 {
700         struct tty_ldisc *ld;
701         if (!tty)
702                 return;
703         ld = tty_ldisc_ref(tty);
704         if (ld) {
705                 if (ld->ops->receive_buf)
706                         ld->ops->receive_buf(tty, data, flags, count);
707                 tty_ldisc_deref(ld);
708         }
709 }
710 
711 /* tty callbacks */
712 
713 static int install(struct tty_driver *driver, struct tty_struct *tty)
714 {
715         SLMP_INFO *info;
716         int line = tty->index;
717 
718         if (line >= synclinkmp_device_count) {
719                 printk("%s(%d): open with invalid line #%d.\n",
720                         __FILE__,__LINE__,line);
721                 return -ENODEV;
722         }
723 
724         info = synclinkmp_device_list;
725         while (info && info->line != line)
726                 info = info->next_device;
727         if (sanity_check(info, tty->name, "open"))
728                 return -ENODEV;
729         if (info->init_error) {
730                 printk("%s(%d):%s device is not allocated, init error=%d\n",
731                         __FILE__, __LINE__, info->device_name,
732                         info->init_error);
733                 return -ENODEV;
734         }
735 
736         tty->driver_data = info;
737 
738         return tty_port_install(&info->port, driver, tty);
739 }
740 
741 /* Called when a port is opened.  Init and enable port.
742  */
743 static int open(struct tty_struct *tty, struct file *filp)
744 {
745         SLMP_INFO *info = tty->driver_data;
746         unsigned long flags;
747         int retval;
748 
749         info->port.tty = tty;
750 
751         if (debug_level >= DEBUG_LEVEL_INFO)
752                 printk("%s(%d):%s open(), old ref count = %d\n",
753                          __FILE__,__LINE__,tty->driver->name, info->port.count);
754 
755         /* If port is closing, signal caller to try again */
756         if (info->port.flags & ASYNC_CLOSING){
757                 wait_event_interruptible_tty(tty, info->port.close_wait,
758                                              !(info->port.flags & ASYNC_CLOSING));
759                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
760                         -EAGAIN : -ERESTARTSYS);
761                 goto cleanup;
762         }
763 
764         info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
765 
766         spin_lock_irqsave(&info->netlock, flags);
767         if (info->netcount) {
768                 retval = -EBUSY;
769                 spin_unlock_irqrestore(&info->netlock, flags);
770                 goto cleanup;
771         }
772         info->port.count++;
773         spin_unlock_irqrestore(&info->netlock, flags);
774 
775         if (info->port.count == 1) {
776                 /* 1st open on this device, init hardware */
777                 retval = startup(info);
778                 if (retval < 0)
779                         goto cleanup;
780         }
781 
782         retval = block_til_ready(tty, filp, info);
783         if (retval) {
784                 if (debug_level >= DEBUG_LEVEL_INFO)
785                         printk("%s(%d):%s block_til_ready() returned %d\n",
786                                  __FILE__,__LINE__, info->device_name, retval);
787                 goto cleanup;
788         }
789 
790         if (debug_level >= DEBUG_LEVEL_INFO)
791                 printk("%s(%d):%s open() success\n",
792                          __FILE__,__LINE__, info->device_name);
793         retval = 0;
794 
795 cleanup:
796         if (retval) {
797                 if (tty->count == 1)
798                         info->port.tty = NULL; /* tty layer will release tty struct */
799                 if(info->port.count)
800                         info->port.count--;
801         }
802 
803         return retval;
804 }
805 
806 /* Called when port is closed. Wait for remaining data to be
807  * sent. Disable port and free resources.
808  */
809 static void close(struct tty_struct *tty, struct file *filp)
810 {
811         SLMP_INFO * info = tty->driver_data;
812 
813         if (sanity_check(info, tty->name, "close"))
814                 return;
815 
816         if (debug_level >= DEBUG_LEVEL_INFO)
817                 printk("%s(%d):%s close() entry, count=%d\n",
818                          __FILE__,__LINE__, info->device_name, info->port.count);
819 
820         if (tty_port_close_start(&info->port, tty, filp) == 0)
821                 goto cleanup;
822 
823         mutex_lock(&info->port.mutex);
824         if (info->port.flags & ASYNC_INITIALIZED)
825                 wait_until_sent(tty, info->timeout);
826 
827         flush_buffer(tty);
828         tty_ldisc_flush(tty);
829         shutdown(info);
830         mutex_unlock(&info->port.mutex);
831 
832         tty_port_close_end(&info->port, tty);
833         info->port.tty = NULL;
834 cleanup:
835         if (debug_level >= DEBUG_LEVEL_INFO)
836                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
837                         tty->driver->name, info->port.count);
838 }
839 
840 /* Called by tty_hangup() when a hangup is signaled.
841  * This is the same as closing all open descriptors for the port.
842  */
843 static void hangup(struct tty_struct *tty)
844 {
845         SLMP_INFO *info = tty->driver_data;
846         unsigned long flags;
847 
848         if (debug_level >= DEBUG_LEVEL_INFO)
849                 printk("%s(%d):%s hangup()\n",
850                          __FILE__,__LINE__, info->device_name );
851 
852         if (sanity_check(info, tty->name, "hangup"))
853                 return;
854 
855         mutex_lock(&info->port.mutex);
856         flush_buffer(tty);
857         shutdown(info);
858 
859         spin_lock_irqsave(&info->port.lock, flags);
860         info->port.count = 0;
861         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
862         info->port.tty = NULL;
863         spin_unlock_irqrestore(&info->port.lock, flags);
864         mutex_unlock(&info->port.mutex);
865 
866         wake_up_interruptible(&info->port.open_wait);
867 }
868 
869 /* Set new termios settings
870  */
871 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
872 {
873         SLMP_INFO *info = tty->driver_data;
874         unsigned long flags;
875 
876         if (debug_level >= DEBUG_LEVEL_INFO)
877                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
878                         tty->driver->name );
879 
880         change_params(info);
881 
882         /* Handle transition to B0 status */
883         if (old_termios->c_cflag & CBAUD &&
884             !(tty->termios.c_cflag & CBAUD)) {
885                 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
886                 spin_lock_irqsave(&info->lock,flags);
887                 set_signals(info);
888                 spin_unlock_irqrestore(&info->lock,flags);
889         }
890 
891         /* Handle transition away from B0 status */
892         if (!(old_termios->c_cflag & CBAUD) &&
893             tty->termios.c_cflag & CBAUD) {
894                 info->serial_signals |= SerialSignal_DTR;
895                 if (!(tty->termios.c_cflag & CRTSCTS) ||
896                     !test_bit(TTY_THROTTLED, &tty->flags)) {
897                         info->serial_signals |= SerialSignal_RTS;
898                 }
899                 spin_lock_irqsave(&info->lock,flags);
900                 set_signals(info);
901                 spin_unlock_irqrestore(&info->lock,flags);
902         }
903 
904         /* Handle turning off CRTSCTS */
905         if (old_termios->c_cflag & CRTSCTS &&
906             !(tty->termios.c_cflag & CRTSCTS)) {
907                 tty->hw_stopped = 0;
908                 tx_release(tty);
909         }
910 }
911 
912 /* Send a block of data
913  *
914  * Arguments:
915  *
916  *      tty             pointer to tty information structure
917  *      buf             pointer to buffer containing send data
918  *      count           size of send data in bytes
919  *
920  * Return Value:        number of characters written
921  */
922 static int write(struct tty_struct *tty,
923                  const unsigned char *buf, int count)
924 {
925         int     c, ret = 0;
926         SLMP_INFO *info = tty->driver_data;
927         unsigned long flags;
928 
929         if (debug_level >= DEBUG_LEVEL_INFO)
930                 printk("%s(%d):%s write() count=%d\n",
931                        __FILE__,__LINE__,info->device_name,count);
932 
933         if (sanity_check(info, tty->name, "write"))
934                 goto cleanup;
935 
936         if (!info->tx_buf)
937                 goto cleanup;
938 
939         if (info->params.mode == MGSL_MODE_HDLC) {
940                 if (count > info->max_frame_size) {
941                         ret = -EIO;
942                         goto cleanup;
943                 }
944                 if (info->tx_active)
945                         goto cleanup;
946                 if (info->tx_count) {
947                         /* send accumulated data from send_char() calls */
948                         /* as frame and wait before accepting more data. */
949                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
950                         goto start;
951                 }
952                 ret = info->tx_count = count;
953                 tx_load_dma_buffer(info, buf, count);
954                 goto start;
955         }
956 
957         for (;;) {
958                 c = min_t(int, count,
959                         min(info->max_frame_size - info->tx_count - 1,
960                             info->max_frame_size - info->tx_put));
961                 if (c <= 0)
962                         break;
963                         
964                 memcpy(info->tx_buf + info->tx_put, buf, c);
965 
966                 spin_lock_irqsave(&info->lock,flags);
967                 info->tx_put += c;
968                 if (info->tx_put >= info->max_frame_size)
969                         info->tx_put -= info->max_frame_size;
970                 info->tx_count += c;
971                 spin_unlock_irqrestore(&info->lock,flags);
972 
973                 buf += c;
974                 count -= c;
975                 ret += c;
976         }
977 
978         if (info->params.mode == MGSL_MODE_HDLC) {
979                 if (count) {
980                         ret = info->tx_count = 0;
981                         goto cleanup;
982                 }
983                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
984         }
985 start:
986         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
987                 spin_lock_irqsave(&info->lock,flags);
988                 if (!info->tx_active)
989                         tx_start(info);
990                 spin_unlock_irqrestore(&info->lock,flags);
991         }
992 
993 cleanup:
994         if (debug_level >= DEBUG_LEVEL_INFO)
995                 printk( "%s(%d):%s write() returning=%d\n",
996                         __FILE__,__LINE__,info->device_name,ret);
997         return ret;
998 }
999 
1000 /* Add a character to the transmit buffer.
1001  */
1002 static int put_char(struct tty_struct *tty, unsigned char ch)
1003 {
1004         SLMP_INFO *info = tty->driver_data;
1005         unsigned long flags;
1006         int ret = 0;
1007 
1008         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1009                 printk( "%s(%d):%s put_char(%d)\n",
1010                         __FILE__,__LINE__,info->device_name,ch);
1011         }
1012 
1013         if (sanity_check(info, tty->name, "put_char"))
1014                 return 0;
1015 
1016         if (!info->tx_buf)
1017                 return 0;
1018 
1019         spin_lock_irqsave(&info->lock,flags);
1020 
1021         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1022              !info->tx_active ) {
1023 
1024                 if (info->tx_count < info->max_frame_size - 1) {
1025                         info->tx_buf[info->tx_put++] = ch;
1026                         if (info->tx_put >= info->max_frame_size)
1027                                 info->tx_put -= info->max_frame_size;
1028                         info->tx_count++;
1029                         ret = 1;
1030                 }
1031         }
1032 
1033         spin_unlock_irqrestore(&info->lock,flags);
1034         return ret;
1035 }
1036 
1037 /* Send a high-priority XON/XOFF character
1038  */
1039 static void send_xchar(struct tty_struct *tty, char ch)
1040 {
1041         SLMP_INFO *info = tty->driver_data;
1042         unsigned long flags;
1043 
1044         if (debug_level >= DEBUG_LEVEL_INFO)
1045                 printk("%s(%d):%s send_xchar(%d)\n",
1046                          __FILE__,__LINE__, info->device_name, ch );
1047 
1048         if (sanity_check(info, tty->name, "send_xchar"))
1049                 return;
1050 
1051         info->x_char = ch;
1052         if (ch) {
1053                 /* Make sure transmit interrupts are on */
1054                 spin_lock_irqsave(&info->lock,flags);
1055                 if (!info->tx_enabled)
1056                         tx_start(info);
1057                 spin_unlock_irqrestore(&info->lock,flags);
1058         }
1059 }
1060 
1061 /* Wait until the transmitter is empty.
1062  */
1063 static void wait_until_sent(struct tty_struct *tty, int timeout)
1064 {
1065         SLMP_INFO * info = tty->driver_data;
1066         unsigned long orig_jiffies, char_time;
1067 
1068         if (!info )
1069                 return;
1070 
1071         if (debug_level >= DEBUG_LEVEL_INFO)
1072                 printk("%s(%d):%s wait_until_sent() entry\n",
1073                          __FILE__,__LINE__, info->device_name );
1074 
1075         if (sanity_check(info, tty->name, "wait_until_sent"))
1076                 return;
1077 
1078         if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags))
1079                 goto exit;
1080 
1081         orig_jiffies = jiffies;
1082 
1083         /* Set check interval to 1/5 of estimated time to
1084          * send a character, and make it at least 1. The check
1085          * interval should also be less than the timeout.
1086          * Note: use tight timings here to satisfy the NIST-PCTS.
1087          */
1088 
1089         if ( info->params.data_rate ) {
1090                 char_time = info->timeout/(32 * 5);
1091                 if (!char_time)
1092                         char_time++;
1093         } else
1094                 char_time = 1;
1095 
1096         if (timeout)
1097                 char_time = min_t(unsigned long, char_time, timeout);
1098 
1099         if ( info->params.mode == MGSL_MODE_HDLC ) {
1100                 while (info->tx_active) {
1101                         msleep_interruptible(jiffies_to_msecs(char_time));
1102                         if (signal_pending(current))
1103                                 break;
1104                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1105                                 break;
1106                 }
1107         } else {
1108                 /*
1109                  * TODO: determine if there is something similar to USC16C32
1110                  *       TXSTATUS_ALL_SENT status
1111                  */
1112                 while ( info->tx_active && info->tx_enabled) {
1113                         msleep_interruptible(jiffies_to_msecs(char_time));
1114                         if (signal_pending(current))
1115                                 break;
1116                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1117                                 break;
1118                 }
1119         }
1120 
1121 exit:
1122         if (debug_level >= DEBUG_LEVEL_INFO)
1123                 printk("%s(%d):%s wait_until_sent() exit\n",
1124                          __FILE__,__LINE__, info->device_name );
1125 }
1126 
1127 /* Return the count of free bytes in transmit buffer
1128  */
1129 static int write_room(struct tty_struct *tty)
1130 {
1131         SLMP_INFO *info = tty->driver_data;
1132         int ret;
1133 
1134         if (sanity_check(info, tty->name, "write_room"))
1135                 return 0;
1136 
1137         if (info->params.mode == MGSL_MODE_HDLC) {
1138                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1139         } else {
1140                 ret = info->max_frame_size - info->tx_count - 1;
1141                 if (ret < 0)
1142                         ret = 0;
1143         }
1144 
1145         if (debug_level >= DEBUG_LEVEL_INFO)
1146                 printk("%s(%d):%s write_room()=%d\n",
1147                        __FILE__, __LINE__, info->device_name, ret);
1148 
1149         return ret;
1150 }
1151 
1152 /* enable transmitter and send remaining buffered characters
1153  */
1154 static void flush_chars(struct tty_struct *tty)
1155 {
1156         SLMP_INFO *info = tty->driver_data;
1157         unsigned long flags;
1158 
1159         if ( debug_level >= DEBUG_LEVEL_INFO )
1160                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1161                         __FILE__,__LINE__,info->device_name,info->tx_count);
1162 
1163         if (sanity_check(info, tty->name, "flush_chars"))
1164                 return;
1165 
1166         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1167             !info->tx_buf)
1168                 return;
1169 
1170         if ( debug_level >= DEBUG_LEVEL_INFO )
1171                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1172                         __FILE__,__LINE__,info->device_name );
1173 
1174         spin_lock_irqsave(&info->lock,flags);
1175 
1176         if (!info->tx_active) {
1177                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1178                         info->tx_count ) {
1179                         /* operating in synchronous (frame oriented) mode */
1180                         /* copy data from circular tx_buf to */
1181                         /* transmit DMA buffer. */
1182                         tx_load_dma_buffer(info,
1183                                  info->tx_buf,info->tx_count);
1184                 }
1185                 tx_start(info);
1186         }
1187 
1188         spin_unlock_irqrestore(&info->lock,flags);
1189 }
1190 
1191 /* Discard all data in the send buffer
1192  */
1193 static void flush_buffer(struct tty_struct *tty)
1194 {
1195         SLMP_INFO *info = tty->driver_data;
1196         unsigned long flags;
1197 
1198         if (debug_level >= DEBUG_LEVEL_INFO)
1199                 printk("%s(%d):%s flush_buffer() entry\n",
1200                          __FILE__,__LINE__, info->device_name );
1201 
1202         if (sanity_check(info, tty->name, "flush_buffer"))
1203                 return;
1204 
1205         spin_lock_irqsave(&info->lock,flags);
1206         info->tx_count = info->tx_put = info->tx_get = 0;
1207         del_timer(&info->tx_timer);
1208         spin_unlock_irqrestore(&info->lock,flags);
1209 
1210         tty_wakeup(tty);
1211 }
1212 
1213 /* throttle (stop) transmitter
1214  */
1215 static void tx_hold(struct tty_struct *tty)
1216 {
1217         SLMP_INFO *info = tty->driver_data;
1218         unsigned long flags;
1219 
1220         if (sanity_check(info, tty->name, "tx_hold"))
1221                 return;
1222 
1223         if ( debug_level >= DEBUG_LEVEL_INFO )
1224                 printk("%s(%d):%s tx_hold()\n",
1225                         __FILE__,__LINE__,info->device_name);
1226 
1227         spin_lock_irqsave(&info->lock,flags);
1228         if (info->tx_enabled)
1229                 tx_stop(info);
1230         spin_unlock_irqrestore(&info->lock,flags);
1231 }
1232 
1233 /* release (start) transmitter
1234  */
1235 static void tx_release(struct tty_struct *tty)
1236 {
1237         SLMP_INFO *info = tty->driver_data;
1238         unsigned long flags;
1239 
1240         if (sanity_check(info, tty->name, "tx_release"))
1241                 return;
1242 
1243         if ( debug_level >= DEBUG_LEVEL_INFO )
1244                 printk("%s(%d):%s tx_release()\n",
1245                         __FILE__,__LINE__,info->device_name);
1246 
1247         spin_lock_irqsave(&info->lock,flags);
1248         if (!info->tx_enabled)
1249                 tx_start(info);
1250         spin_unlock_irqrestore(&info->lock,flags);
1251 }
1252 
1253 /* Service an IOCTL request
1254  *
1255  * Arguments:
1256  *
1257  *      tty     pointer to tty instance data
1258  *      cmd     IOCTL command code
1259  *      arg     command argument/context
1260  *
1261  * Return Value:        0 if success, otherwise error code
1262  */
1263 static int ioctl(struct tty_struct *tty,
1264                  unsigned int cmd, unsigned long arg)
1265 {
1266         SLMP_INFO *info = tty->driver_data;
1267         void __user *argp = (void __user *)arg;
1268 
1269         if (debug_level >= DEBUG_LEVEL_INFO)
1270                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1271                         info->device_name, cmd );
1272 
1273         if (sanity_check(info, tty->name, "ioctl"))
1274                 return -ENODEV;
1275 
1276         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1277             (cmd != TIOCMIWAIT)) {
1278                 if (tty->flags & (1 << TTY_IO_ERROR))
1279                     return -EIO;
1280         }
1281 
1282         switch (cmd) {
1283         case MGSL_IOCGPARAMS:
1284                 return get_params(info, argp);
1285         case MGSL_IOCSPARAMS:
1286                 return set_params(info, argp);
1287         case MGSL_IOCGTXIDLE:
1288                 return get_txidle(info, argp);
1289         case MGSL_IOCSTXIDLE:
1290                 return set_txidle(info, (int)arg);
1291         case MGSL_IOCTXENABLE:
1292                 return tx_enable(info, (int)arg);
1293         case MGSL_IOCRXENABLE:
1294                 return rx_enable(info, (int)arg);
1295         case MGSL_IOCTXABORT:
1296                 return tx_abort(info);
1297         case MGSL_IOCGSTATS:
1298                 return get_stats(info, argp);
1299         case MGSL_IOCWAITEVENT:
1300                 return wait_mgsl_event(info, argp);
1301         case MGSL_IOCLOOPTXDONE:
1302                 return 0; // TODO: Not supported, need to document
1303                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1304                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1305                  */
1306         case TIOCMIWAIT:
1307                 return modem_input_wait(info,(int)arg);
1308                 
1309                 /*
1310                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1311                  * Return: write counters to the user passed counter struct
1312                  * NB: both 1->0 and 0->1 transitions are counted except for
1313                  *     RI where only 0->1 is counted.
1314                  */
1315         default:
1316                 return -ENOIOCTLCMD;
1317         }
1318         return 0;
1319 }
1320 
1321 static int get_icount(struct tty_struct *tty,
1322                                 struct serial_icounter_struct *icount)
1323 {
1324         SLMP_INFO *info = tty->driver_data;
1325         struct mgsl_icount cnow;        /* kernel counter temps */
1326         unsigned long flags;
1327 
1328         spin_lock_irqsave(&info->lock,flags);
1329         cnow = info->icount;
1330         spin_unlock_irqrestore(&info->lock,flags);
1331 
1332         icount->cts = cnow.cts;
1333         icount->dsr = cnow.dsr;
1334         icount->rng = cnow.rng;
1335         icount->dcd = cnow.dcd;
1336         icount->rx = cnow.rx;
1337         icount->tx = cnow.tx;
1338         icount->frame = cnow.frame;
1339         icount->overrun = cnow.overrun;
1340         icount->parity = cnow.parity;
1341         icount->brk = cnow.brk;
1342         icount->buf_overrun = cnow.buf_overrun;
1343 
1344         return 0;
1345 }
1346 
1347 /*
1348  * /proc fs routines....
1349  */
1350 
1351 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1352 {
1353         char    stat_buf[30];
1354         unsigned long flags;
1355 
1356         seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1357                        "\tIRQ=%d MaxFrameSize=%u\n",
1358                 info->device_name,
1359                 info->phys_sca_base,
1360                 info->phys_memory_base,
1361                 info->phys_statctrl_base,
1362                 info->phys_lcr_base,
1363                 info->irq_level,
1364                 info->max_frame_size );
1365 
1366         /* output current serial signal states */
1367         spin_lock_irqsave(&info->lock,flags);
1368         get_signals(info);
1369         spin_unlock_irqrestore(&info->lock,flags);
1370 
1371         stat_buf[0] = 0;
1372         stat_buf[1] = 0;
1373         if (info->serial_signals & SerialSignal_RTS)
1374                 strcat(stat_buf, "|RTS");
1375         if (info->serial_signals & SerialSignal_CTS)
1376                 strcat(stat_buf, "|CTS");
1377         if (info->serial_signals & SerialSignal_DTR)
1378                 strcat(stat_buf, "|DTR");
1379         if (info->serial_signals & SerialSignal_DSR)
1380                 strcat(stat_buf, "|DSR");
1381         if (info->serial_signals & SerialSignal_DCD)
1382                 strcat(stat_buf, "|CD");
1383         if (info->serial_signals & SerialSignal_RI)
1384                 strcat(stat_buf, "|RI");
1385 
1386         if (info->params.mode == MGSL_MODE_HDLC) {
1387                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1388                               info->icount.txok, info->icount.rxok);
1389                 if (info->icount.txunder)
1390                         seq_printf(m, " txunder:%d", info->icount.txunder);
1391                 if (info->icount.txabort)
1392                         seq_printf(m, " txabort:%d", info->icount.txabort);
1393                 if (info->icount.rxshort)
1394                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1395                 if (info->icount.rxlong)
1396                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1397                 if (info->icount.rxover)
1398                         seq_printf(m, " rxover:%d", info->icount.rxover);
1399                 if (info->icount.rxcrc)
1400                         seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1401         } else {
1402                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1403                               info->icount.tx, info->icount.rx);
1404                 if (info->icount.frame)
1405                         seq_printf(m, " fe:%d", info->icount.frame);
1406                 if (info->icount.parity)
1407                         seq_printf(m, " pe:%d", info->icount.parity);
1408                 if (info->icount.brk)
1409                         seq_printf(m, " brk:%d", info->icount.brk);
1410                 if (info->icount.overrun)
1411                         seq_printf(m, " oe:%d", info->icount.overrun);
1412         }
1413 
1414         /* Append serial signal status to end */
1415         seq_printf(m, " %s\n", stat_buf+1);
1416 
1417         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1418          info->tx_active,info->bh_requested,info->bh_running,
1419          info->pending_bh);
1420 }
1421 
1422 /* Called to print information about devices
1423  */
1424 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1425 {
1426         SLMP_INFO *info;
1427 
1428         seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1429 
1430         info = synclinkmp_device_list;
1431         while( info ) {
1432                 line_info(m, info);
1433                 info = info->next_device;
1434         }
1435         return 0;
1436 }
1437 
1438 static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1439 {
1440         return single_open(file, synclinkmp_proc_show, NULL);
1441 }
1442 
1443 static const struct file_operations synclinkmp_proc_fops = {
1444         .owner          = THIS_MODULE,
1445         .open           = synclinkmp_proc_open,
1446         .read           = seq_read,
1447         .llseek         = seq_lseek,
1448         .release        = single_release,
1449 };
1450 
1451 /* Return the count of bytes in transmit buffer
1452  */
1453 static int chars_in_buffer(struct tty_struct *tty)
1454 {
1455         SLMP_INFO *info = tty->driver_data;
1456 
1457         if (sanity_check(info, tty->name, "chars_in_buffer"))
1458                 return 0;
1459 
1460         if (debug_level >= DEBUG_LEVEL_INFO)
1461                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1462                        __FILE__, __LINE__, info->device_name, info->tx_count);
1463 
1464         return info->tx_count;
1465 }
1466 
1467 /* Signal remote device to throttle send data (our receive data)
1468  */
1469 static void throttle(struct tty_struct * tty)
1470 {
1471         SLMP_INFO *info = tty->driver_data;
1472         unsigned long flags;
1473 
1474         if (debug_level >= DEBUG_LEVEL_INFO)
1475                 printk("%s(%d):%s throttle() entry\n",
1476                          __FILE__,__LINE__, info->device_name );
1477 
1478         if (sanity_check(info, tty->name, "throttle"))
1479                 return;
1480 
1481         if (I_IXOFF(tty))
1482                 send_xchar(tty, STOP_CHAR(tty));
1483 
1484         if (tty->termios.c_cflag & CRTSCTS) {
1485                 spin_lock_irqsave(&info->lock,flags);
1486                 info->serial_signals &= ~SerialSignal_RTS;
1487                 set_signals(info);
1488                 spin_unlock_irqrestore(&info->lock,flags);
1489         }
1490 }
1491 
1492 /* Signal remote device to stop throttling send data (our receive data)
1493  */
1494 static void unthrottle(struct tty_struct * tty)
1495 {
1496         SLMP_INFO *info = tty->driver_data;
1497         unsigned long flags;
1498 
1499         if (debug_level >= DEBUG_LEVEL_INFO)
1500                 printk("%s(%d):%s unthrottle() entry\n",
1501                          __FILE__,__LINE__, info->device_name );
1502 
1503         if (sanity_check(info, tty->name, "unthrottle"))
1504                 return;
1505 
1506         if (I_IXOFF(tty)) {
1507                 if (info->x_char)
1508                         info->x_char = 0;
1509                 else
1510                         send_xchar(tty, START_CHAR(tty));
1511         }
1512 
1513         if (tty->termios.c_cflag & CRTSCTS) {
1514                 spin_lock_irqsave(&info->lock,flags);
1515                 info->serial_signals |= SerialSignal_RTS;
1516                 set_signals(info);
1517                 spin_unlock_irqrestore(&info->lock,flags);
1518         }
1519 }
1520 
1521 /* set or clear transmit break condition
1522  * break_state  -1=set break condition, 0=clear
1523  */
1524 static int set_break(struct tty_struct *tty, int break_state)
1525 {
1526         unsigned char RegValue;
1527         SLMP_INFO * info = tty->driver_data;
1528         unsigned long flags;
1529 
1530         if (debug_level >= DEBUG_LEVEL_INFO)
1531                 printk("%s(%d):%s set_break(%d)\n",
1532                          __FILE__,__LINE__, info->device_name, break_state);
1533 
1534         if (sanity_check(info, tty->name, "set_break"))
1535                 return -EINVAL;
1536 
1537         spin_lock_irqsave(&info->lock,flags);
1538         RegValue = read_reg(info, CTL);
1539         if (break_state == -1)
1540                 RegValue |= BIT3;
1541         else
1542                 RegValue &= ~BIT3;
1543         write_reg(info, CTL, RegValue);
1544         spin_unlock_irqrestore(&info->lock,flags);
1545         return 0;
1546 }
1547 
1548 #if SYNCLINK_GENERIC_HDLC
1549 
1550 /**
1551  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1552  * set encoding and frame check sequence (FCS) options
1553  *
1554  * dev       pointer to network device structure
1555  * encoding  serial encoding setting
1556  * parity    FCS setting
1557  *
1558  * returns 0 if success, otherwise error code
1559  */
1560 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1561                           unsigned short parity)
1562 {
1563         SLMP_INFO *info = dev_to_port(dev);
1564         unsigned char  new_encoding;
1565         unsigned short new_crctype;
1566 
1567         /* return error if TTY interface open */
1568         if (info->port.count)
1569                 return -EBUSY;
1570 
1571         switch (encoding)
1572         {
1573         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1574         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1575         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1576         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1577         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1578         default: return -EINVAL;
1579         }
1580 
1581         switch (parity)
1582         {
1583         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1584         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1585         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1586         default: return -EINVAL;
1587         }
1588 
1589         info->params.encoding = new_encoding;
1590         info->params.crc_type = new_crctype;
1591 
1592         /* if network interface up, reprogram hardware */
1593         if (info->netcount)
1594                 program_hw(info);
1595 
1596         return 0;
1597 }
1598 
1599 /**
1600  * called by generic HDLC layer to send frame
1601  *
1602  * skb  socket buffer containing HDLC frame
1603  * dev  pointer to network device structure
1604  */
1605 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1606                                       struct net_device *dev)
1607 {
1608         SLMP_INFO *info = dev_to_port(dev);
1609         unsigned long flags;
1610 
1611         if (debug_level >= DEBUG_LEVEL_INFO)
1612                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1613 
1614         /* stop sending until this frame completes */
1615         netif_stop_queue(dev);
1616 
1617         /* copy data to device buffers */
1618         info->tx_count = skb->len;
1619         tx_load_dma_buffer(info, skb->data, skb->len);
1620 
1621         /* update network statistics */
1622         dev->stats.tx_packets++;
1623         dev->stats.tx_bytes += skb->len;
1624 
1625         /* done with socket buffer, so free it */
1626         dev_kfree_skb(skb);
1627 
1628         /* save start time for transmit timeout detection */
1629         dev->trans_start = jiffies;
1630 
1631         /* start hardware transmitter if necessary */
1632         spin_lock_irqsave(&info->lock,flags);
1633         if (!info->tx_active)
1634                 tx_start(info);
1635         spin_unlock_irqrestore(&info->lock,flags);
1636 
1637         return NETDEV_TX_OK;
1638 }
1639 
1640 /**
1641  * called by network layer when interface enabled
1642  * claim resources and initialize hardware
1643  *
1644  * dev  pointer to network device structure
1645  *
1646  * returns 0 if success, otherwise error code
1647  */
1648 static int hdlcdev_open(struct net_device *dev)
1649 {
1650         SLMP_INFO *info = dev_to_port(dev);
1651         int rc;
1652         unsigned long flags;
1653 
1654         if (debug_level >= DEBUG_LEVEL_INFO)
1655                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1656 
1657         /* generic HDLC layer open processing */
1658         rc = hdlc_open(dev);
1659         if (rc)
1660                 return rc;
1661 
1662         /* arbitrate between network and tty opens */
1663         spin_lock_irqsave(&info->netlock, flags);
1664         if (info->port.count != 0 || info->netcount != 0) {
1665                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1666                 spin_unlock_irqrestore(&info->netlock, flags);
1667                 return -EBUSY;
1668         }
1669         info->netcount=1;
1670         spin_unlock_irqrestore(&info->netlock, flags);
1671 
1672         /* claim resources and init adapter */
1673         if ((rc = startup(info)) != 0) {
1674                 spin_lock_irqsave(&info->netlock, flags);
1675                 info->netcount=0;
1676                 spin_unlock_irqrestore(&info->netlock, flags);
1677                 return rc;
1678         }
1679 
1680         /* assert RTS and DTR, apply hardware settings */
1681         info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1682         program_hw(info);
1683 
1684         /* enable network layer transmit */
1685         dev->trans_start = jiffies;
1686         netif_start_queue(dev);
1687 
1688         /* inform generic HDLC layer of current DCD status */
1689         spin_lock_irqsave(&info->lock, flags);
1690         get_signals(info);
1691         spin_unlock_irqrestore(&info->lock, flags);
1692         if (info->serial_signals & SerialSignal_DCD)
1693                 netif_carrier_on(dev);
1694         else
1695                 netif_carrier_off(dev);
1696         return 0;
1697 }
1698 
1699 /**
1700  * called by network layer when interface is disabled
1701  * shutdown hardware and release resources
1702  *
1703  * dev  pointer to network device structure
1704  *
1705  * returns 0 if success, otherwise error code
1706  */
1707 static int hdlcdev_close(struct net_device *dev)
1708 {
1709         SLMP_INFO *info = dev_to_port(dev);
1710         unsigned long flags;
1711 
1712         if (debug_level >= DEBUG_LEVEL_INFO)
1713                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1714 
1715         netif_stop_queue(dev);
1716 
1717         /* shutdown adapter and release resources */
1718         shutdown(info);
1719 
1720         hdlc_close(dev);
1721 
1722         spin_lock_irqsave(&info->netlock, flags);
1723         info->netcount=0;
1724         spin_unlock_irqrestore(&info->netlock, flags);
1725 
1726         return 0;
1727 }
1728 
1729 /**
1730  * called by network layer to process IOCTL call to network device
1731  *
1732  * dev  pointer to network device structure
1733  * ifr  pointer to network interface request structure
1734  * cmd  IOCTL command code
1735  *
1736  * returns 0 if success, otherwise error code
1737  */
1738 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1739 {
1740         const size_t size = sizeof(sync_serial_settings);
1741         sync_serial_settings new_line;
1742         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1743         SLMP_INFO *info = dev_to_port(dev);
1744         unsigned int flags;
1745 
1746         if (debug_level >= DEBUG_LEVEL_INFO)
1747                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1748 
1749         /* return error if TTY interface open */
1750         if (info->port.count)
1751                 return -EBUSY;
1752 
1753         if (cmd != SIOCWANDEV)
1754                 return hdlc_ioctl(dev, ifr, cmd);
1755 
1756         switch(ifr->ifr_settings.type) {
1757         case IF_GET_IFACE: /* return current sync_serial_settings */
1758 
1759                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1760                 if (ifr->ifr_settings.size < size) {
1761                         ifr->ifr_settings.size = size; /* data size wanted */
1762                         return -ENOBUFS;
1763                 }
1764 
1765                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1766                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1767                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1768                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1769 
1770                 memset(&new_line, 0, sizeof(new_line));
1771                 switch (flags){
1772                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1773                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1774                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1775                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1776                 default: new_line.clock_type = CLOCK_DEFAULT;
1777                 }
1778 
1779                 new_line.clock_rate = info->params.clock_speed;
1780                 new_line.loopback   = info->params.loopback ? 1:0;
1781 
1782                 if (copy_to_user(line, &new_line, size))
1783                         return -EFAULT;
1784                 return 0;
1785 
1786         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1787 
1788                 if(!capable(CAP_NET_ADMIN))
1789                         return -EPERM;
1790                 if (copy_from_user(&new_line, line, size))
1791                         return -EFAULT;
1792 
1793                 switch (new_line.clock_type)
1794                 {
1795                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1796                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1797                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1798                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1799                 case CLOCK_DEFAULT:  flags = info->params.flags &
1800                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1801                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1802                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1803                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1804                 default: return -EINVAL;
1805                 }
1806 
1807                 if (new_line.loopback != 0 && new_line.loopback != 1)
1808                         return -EINVAL;
1809 
1810                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1811                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1812                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1813                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1814                 info->params.flags |= flags;
1815 
1816                 info->params.loopback = new_line.loopback;
1817 
1818                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1819                         info->params.clock_speed = new_line.clock_rate;
1820                 else
1821                         info->params.clock_speed = 0;
1822 
1823                 /* if network interface up, reprogram hardware */
1824                 if (info->netcount)
1825                         program_hw(info);
1826                 return 0;
1827 
1828         default:
1829                 return hdlc_ioctl(dev, ifr, cmd);
1830         }
1831 }
1832 
1833 /**
1834  * called by network layer when transmit timeout is detected
1835  *
1836  * dev  pointer to network device structure
1837  */
1838 static void hdlcdev_tx_timeout(struct net_device *dev)
1839 {
1840         SLMP_INFO *info = dev_to_port(dev);
1841         unsigned long flags;
1842 
1843         if (debug_level >= DEBUG_LEVEL_INFO)
1844                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1845 
1846         dev->stats.tx_errors++;
1847         dev->stats.tx_aborted_errors++;
1848 
1849         spin_lock_irqsave(&info->lock,flags);
1850         tx_stop(info);
1851         spin_unlock_irqrestore(&info->lock,flags);
1852 
1853         netif_wake_queue(dev);
1854 }
1855 
1856 /**
1857  * called by device driver when transmit completes
1858  * reenable network layer transmit if stopped
1859  *
1860  * info  pointer to device instance information
1861  */
1862 static void hdlcdev_tx_done(SLMP_INFO *info)
1863 {
1864         if (netif_queue_stopped(info->netdev))
1865                 netif_wake_queue(info->netdev);
1866 }
1867 
1868 /**
1869  * called by device driver when frame received
1870  * pass frame to network layer
1871  *
1872  * info  pointer to device instance information
1873  * buf   pointer to buffer contianing frame data
1874  * size  count of data bytes in buf
1875  */
1876 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1877 {
1878         struct sk_buff *skb = dev_alloc_skb(size);
1879         struct net_device *dev = info->netdev;
1880 
1881         if (debug_level >= DEBUG_LEVEL_INFO)
1882                 printk("hdlcdev_rx(%s)\n",dev->name);
1883 
1884         if (skb == NULL) {
1885                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1886                        dev->name);
1887                 dev->stats.rx_dropped++;
1888                 return;
1889         }
1890 
1891         memcpy(skb_put(skb, size), buf, size);
1892 
1893         skb->protocol = hdlc_type_trans(skb, dev);
1894 
1895         dev->stats.rx_packets++;
1896         dev->stats.rx_bytes += size;
1897 
1898         netif_rx(skb);
1899 }
1900 
1901 static const struct net_device_ops hdlcdev_ops = {
1902         .ndo_open       = hdlcdev_open,
1903         .ndo_stop       = hdlcdev_close,
1904         .ndo_change_mtu = hdlc_change_mtu,
1905         .ndo_start_xmit = hdlc_start_xmit,
1906         .ndo_do_ioctl   = hdlcdev_ioctl,
1907         .ndo_tx_timeout = hdlcdev_tx_timeout,
1908 };
1909 
1910 /**
1911  * called by device driver when adding device instance
1912  * do generic HDLC initialization
1913  *
1914  * info  pointer to device instance information
1915  *
1916  * returns 0 if success, otherwise error code
1917  */
1918 static int hdlcdev_init(SLMP_INFO *info)
1919 {
1920         int rc;
1921         struct net_device *dev;
1922         hdlc_device *hdlc;
1923 
1924         /* allocate and initialize network and HDLC layer objects */
1925 
1926         dev = alloc_hdlcdev(info);
1927         if (!dev) {
1928                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1929                 return -ENOMEM;
1930         }
1931 
1932         /* for network layer reporting purposes only */
1933         dev->mem_start = info->phys_sca_base;
1934         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1935         dev->irq       = info->irq_level;
1936 
1937         /* network layer callbacks and settings */
1938         dev->netdev_ops     = &hdlcdev_ops;
1939         dev->watchdog_timeo = 10 * HZ;
1940         dev->tx_queue_len   = 50;
1941 
1942         /* generic HDLC layer callbacks and settings */
1943         hdlc         = dev_to_hdlc(dev);
1944         hdlc->attach = hdlcdev_attach;
1945         hdlc->xmit   = hdlcdev_xmit;
1946 
1947         /* register objects with HDLC layer */
1948         rc = register_hdlc_device(dev);
1949         if (rc) {
1950                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1951                 free_netdev(dev);
1952                 return rc;
1953         }
1954 
1955         info->netdev = dev;
1956         return 0;
1957 }
1958 
1959 /**
1960  * called by device driver when removing device instance
1961  * do generic HDLC cleanup
1962  *
1963  * info  pointer to device instance information
1964  */
1965 static void hdlcdev_exit(SLMP_INFO *info)
1966 {
1967         unregister_hdlc_device(info->netdev);
1968         free_netdev(info->netdev);
1969         info->netdev = NULL;
1970 }
1971 
1972 #endif /* CONFIG_HDLC */
1973 
1974 
1975 /* Return next bottom half action to perform.
1976  * Return Value:        BH action code or 0 if nothing to do.
1977  */
1978 static int bh_action(SLMP_INFO *info)
1979 {
1980         unsigned long flags;
1981         int rc = 0;
1982 
1983         spin_lock_irqsave(&info->lock,flags);
1984 
1985         if (info->pending_bh & BH_RECEIVE) {
1986                 info->pending_bh &= ~BH_RECEIVE;
1987                 rc = BH_RECEIVE;
1988         } else if (info->pending_bh & BH_TRANSMIT) {
1989                 info->pending_bh &= ~BH_TRANSMIT;
1990                 rc = BH_TRANSMIT;
1991         } else if (info->pending_bh & BH_STATUS) {
1992                 info->pending_bh &= ~BH_STATUS;
1993                 rc = BH_STATUS;
1994         }
1995 
1996         if (!rc) {
1997                 /* Mark BH routine as complete */
1998                 info->bh_running = false;
1999                 info->bh_requested = false;
2000         }
2001 
2002         spin_unlock_irqrestore(&info->lock,flags);
2003 
2004         return rc;
2005 }
2006 
2007 /* Perform bottom half processing of work items queued by ISR.
2008  */
2009 static void bh_handler(struct work_struct *work)
2010 {
2011         SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2012         int action;
2013 
2014         if ( debug_level >= DEBUG_LEVEL_BH )
2015                 printk( "%s(%d):%s bh_handler() entry\n",
2016                         __FILE__,__LINE__,info->device_name);
2017 
2018         info->bh_running = true;
2019 
2020         while((action = bh_action(info)) != 0) {
2021 
2022                 /* Process work item */
2023                 if ( debug_level >= DEBUG_LEVEL_BH )
2024                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2025                                 __FILE__,__LINE__,info->device_name, action);
2026 
2027                 switch (action) {
2028 
2029                 case BH_RECEIVE:
2030                         bh_receive(info);
2031                         break;
2032                 case BH_TRANSMIT:
2033                         bh_transmit(info);
2034                         break;
2035                 case BH_STATUS:
2036                         bh_status(info);
2037                         break;
2038                 default:
2039                         /* unknown work item ID */
2040                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2041                                 __FILE__,__LINE__,info->device_name,action);
2042                         break;
2043                 }
2044         }
2045 
2046         if ( debug_level >= DEBUG_LEVEL_BH )
2047                 printk( "%s(%d):%s bh_handler() exit\n",
2048                         __FILE__,__LINE__,info->device_name);
2049 }
2050 
2051 static void bh_receive(SLMP_INFO *info)
2052 {
2053         if ( debug_level >= DEBUG_LEVEL_BH )
2054                 printk( "%s(%d):%s bh_receive()\n",
2055                         __FILE__,__LINE__,info->device_name);
2056 
2057         while( rx_get_frame(info) );
2058 }
2059 
2060 static void bh_transmit(SLMP_INFO *info)
2061 {
2062         struct tty_struct *tty = info->port.tty;
2063 
2064         if ( debug_level >= DEBUG_LEVEL_BH )
2065                 printk( "%s(%d):%s bh_transmit() entry\n",
2066                         __FILE__,__LINE__,info->device_name);
2067 
2068         if (tty)
2069                 tty_wakeup(tty);
2070 }
2071 
2072 static void bh_status(SLMP_INFO *info)
2073 {
2074         if ( debug_level >= DEBUG_LEVEL_BH )
2075                 printk( "%s(%d):%s bh_status() entry\n",
2076                         __FILE__,__LINE__,info->device_name);
2077 
2078         info->ri_chkcount = 0;
2079         info->dsr_chkcount = 0;
2080         info->dcd_chkcount = 0;
2081         info->cts_chkcount = 0;
2082 }
2083 
2084 static void isr_timer(SLMP_INFO * info)
2085 {
2086         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2087 
2088         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2089         write_reg(info, IER2, 0);
2090 
2091         /* TMCS, Timer Control/Status Register
2092          *
2093          * 07      CMF, Compare match flag (read only) 1=match
2094          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2095          * 05      Reserved, must be 0
2096          * 04      TME, Timer Enable
2097          * 03..00  Reserved, must be 0
2098          *
2099          * 0000 0000
2100          */
2101         write_reg(info, (unsigned char)(timer + TMCS), 0);
2102 
2103         info->irq_occurred = true;
2104 
2105         if ( debug_level >= DEBUG_LEVEL_ISR )
2106                 printk("%s(%d):%s isr_timer()\n",
2107                         __FILE__,__LINE__,info->device_name);
2108 }
2109 
2110 static void isr_rxint(SLMP_INFO * info)
2111 {
2112         struct tty_struct *tty = info->port.tty;
2113         struct  mgsl_icount *icount = &info->icount;
2114         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2115         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2116 
2117         /* clear status bits */
2118         if (status)
2119                 write_reg(info, SR1, status);
2120 
2121         if (status2)
2122                 write_reg(info, SR2, status2);
2123         
2124         if ( debug_level >= DEBUG_LEVEL_ISR )
2125                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2126                         __FILE__,__LINE__,info->device_name,status,status2);
2127 
2128         if (info->params.mode == MGSL_MODE_ASYNC) {
2129                 if (status & BRKD) {
2130                         icount->brk++;
2131 
2132                         /* process break detection if tty control
2133                          * is not set to ignore it
2134                          */
2135                         if (!(status & info->ignore_status_mask1)) {
2136                                 if (info->read_status_mask1 & BRKD) {
2137                                         tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2138                                         if (tty && (info->port.flags & ASYNC_SAK))
2139                                                 do_SAK(tty);
2140                                 }
2141                         }
2142                 }
2143         }
2144         else {
2145                 if (status & (FLGD|IDLD)) {
2146                         if (status & FLGD)
2147                                 info->icount.exithunt++;
2148                         else if (status & IDLD)
2149                                 info->icount.rxidle++;
2150                         wake_up_interruptible(&info->event_wait_q);
2151                 }
2152         }
2153 
2154         if (status & CDCD) {
2155                 /* simulate a common modem status change interrupt
2156                  * for our handler
2157                  */
2158                 get_signals( info );
2159                 isr_io_pin(info,
2160                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2161         }
2162 }
2163 
2164 /*
2165  * handle async rx data interrupts
2166  */
2167 static void isr_rxrdy(SLMP_INFO * info)
2168 {
2169         u16 status;
2170         unsigned char DataByte;
2171         struct  mgsl_icount *icount = &info->icount;
2172 
2173         if ( debug_level >= DEBUG_LEVEL_ISR )
2174                 printk("%s(%d):%s isr_rxrdy\n",
2175                         __FILE__,__LINE__,info->device_name);
2176 
2177         while((status = read_reg(info,CST0)) & BIT0)
2178         {
2179                 int flag = 0;
2180                 bool over = false;
2181                 DataByte = read_reg(info,TRB);
2182 
2183                 icount->rx++;
2184 
2185                 if ( status & (PE + FRME + OVRN) ) {
2186                         printk("%s(%d):%s rxerr=%04X\n",
2187                                 __FILE__,__LINE__,info->device_name,status);
2188 
2189                         /* update error statistics */
2190                         if (status & PE)
2191                                 icount->parity++;
2192                         else if (status & FRME)
2193                                 icount->frame++;
2194                         else if (status & OVRN)
2195                                 icount->overrun++;
2196 
2197                         /* discard char if tty control flags say so */
2198                         if (status & info->ignore_status_mask2)
2199                                 continue;
2200 
2201                         status &= info->read_status_mask2;
2202 
2203                         if (status & PE)
2204                                 flag = TTY_PARITY;
2205                         else if (status & FRME)
2206                                 flag = TTY_FRAME;
2207                         if (status & OVRN) {
2208                                 /* Overrun is special, since it's
2209                                  * reported immediately, and doesn't
2210                                  * affect the current character
2211                                  */
2212                                 over = true;
2213                         }
2214                 }       /* end of if (error) */
2215 
2216                 tty_insert_flip_char(&info->port, DataByte, flag);
2217                 if (over)
2218                         tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2219         }
2220 
2221         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2222                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2223                         __FILE__,__LINE__,info->device_name,
2224                         icount->rx,icount->brk,icount->parity,
2225                         icount->frame,icount->overrun);
2226         }
2227 
2228         tty_flip_buffer_push(&info->port);
2229 }
2230 
2231 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2232 {
2233         if ( debug_level >= DEBUG_LEVEL_ISR )
2234                 printk("%s(%d):%s isr_txeom status=%02x\n",
2235                         __FILE__,__LINE__,info->device_name,status);
2236 
2237         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2238         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2239         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2240 
2241         if (status & UDRN) {
2242                 write_reg(info, CMD, TXRESET);
2243                 write_reg(info, CMD, TXENABLE);
2244         } else
2245                 write_reg(info, CMD, TXBUFCLR);
2246 
2247         /* disable and clear tx interrupts */
2248         info->ie0_value &= ~TXRDYE;
2249         info->ie1_value &= ~(IDLE + UDRN);
2250         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2251         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2252 
2253         if ( info->tx_active ) {
2254                 if (info->params.mode != MGSL_MODE_ASYNC) {
2255                         if (status & UDRN)
2256                                 info->icount.txunder++;
2257                         else if (status & IDLE)
2258                                 info->icount.txok++;
2259                 }
2260 
2261                 info->tx_active = false;
2262                 info->tx_count = info->tx_put = info->tx_get = 0;
2263 
2264                 del_timer(&info->tx_timer);
2265 
2266                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2267                         info->serial_signals &= ~SerialSignal_RTS;
2268                         info->drop_rts_on_tx_done = false;
2269                         set_signals(info);
2270                 }
2271 
2272 #if SYNCLINK_GENERIC_HDLC
2273                 if (info->netcount)
2274                         hdlcdev_tx_done(info);
2275                 else
2276 #endif
2277                 {
2278                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2279                                 tx_stop(info);
2280                                 return;
2281                         }
2282                         info->pending_bh |= BH_TRANSMIT;
2283                 }
2284         }
2285 }
2286 
2287 
2288 /*
2289  * handle tx status interrupts
2290  */
2291 static void isr_txint(SLMP_INFO * info)
2292 {
2293         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2294 
2295         /* clear status bits */
2296         write_reg(info, SR1, status);
2297 
2298         if ( debug_level >= DEBUG_LEVEL_ISR )
2299                 printk("%s(%d):%s isr_txint status=%02x\n",
2300                         __FILE__,__LINE__,info->device_name,status);
2301 
2302         if (status & (UDRN + IDLE))
2303                 isr_txeom(info, status);
2304 
2305         if (status & CCTS) {
2306                 /* simulate a common modem status change interrupt
2307                  * for our handler
2308                  */
2309                 get_signals( info );
2310                 isr_io_pin(info,
2311                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2312 
2313         }
2314 }
2315 
2316 /*
2317  * handle async tx data interrupts
2318  */
2319 static void isr_txrdy(SLMP_INFO * info)
2320 {
2321         if ( debug_level >= DEBUG_LEVEL_ISR )
2322                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2323                         __FILE__,__LINE__,info->device_name,info->tx_count);
2324 
2325         if (info->params.mode != MGSL_MODE_ASYNC) {
2326                 /* disable TXRDY IRQ, enable IDLE IRQ */
2327                 info->ie0_value &= ~TXRDYE;
2328                 info->ie1_value |= IDLE;
2329                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2330                 return;
2331         }
2332 
2333         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2334                 tx_stop(info);
2335                 return;
2336         }
2337 
2338         if ( info->tx_count )
2339                 tx_load_fifo( info );
2340         else {
2341                 info->tx_active = false;
2342                 info->ie0_value &= ~TXRDYE;
2343                 write_reg(info, IE0, info->ie0_value);
2344         }
2345 
2346         if (info->tx_count < WAKEUP_CHARS)
2347                 info->pending_bh |= BH_TRANSMIT;
2348 }
2349 
2350 static void isr_rxdmaok(SLMP_INFO * info)
2351 {
2352         /* BIT7 = EOT (end of transfer)
2353          * BIT6 = EOM (end of message/frame)
2354          */
2355         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2356 
2357         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2358         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2359 
2360         if ( debug_level >= DEBUG_LEVEL_ISR )
2361                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2362                         __FILE__,__LINE__,info->device_name,status);
2363 
2364         info->pending_bh |= BH_RECEIVE;
2365 }
2366 
2367 static void isr_rxdmaerror(SLMP_INFO * info)
2368 {
2369         /* BIT5 = BOF (buffer overflow)
2370          * BIT4 = COF (counter overflow)
2371          */
2372         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2373 
2374         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2375         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2376 
2377         if ( debug_level >= DEBUG_LEVEL_ISR )
2378                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2379                         __FILE__,__LINE__,info->device_name,status);
2380 
2381         info->rx_overflow = true;
2382         info->pending_bh |= BH_RECEIVE;
2383 }
2384 
2385 static void isr_txdmaok(SLMP_INFO * info)
2386 {
2387         unsigned char status_reg1 = read_reg(info, SR1);
2388 
2389         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2390         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2391         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2392 
2393         if ( debug_level >= DEBUG_LEVEL_ISR )
2394                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2395                         __FILE__,__LINE__,info->device_name,status_reg1);
2396 
2397         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2398         write_reg16(info, TRC0, 0);
2399         info->ie0_value |= TXRDYE;
2400         write_reg(info, IE0, info->ie0_value);
2401 }
2402 
2403 static void isr_txdmaerror(SLMP_INFO * info)
2404 {
2405         /* BIT5 = BOF (buffer overflow)
2406          * BIT4 = COF (counter overflow)
2407          */
2408         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2409 
2410         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2411         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2412 
2413         if ( debug_level >= DEBUG_LEVEL_ISR )
2414                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2415                         __FILE__,__LINE__,info->device_name,status);
2416 }
2417 
2418 /* handle input serial signal changes
2419  */
2420 static void isr_io_pin( SLMP_INFO *info, u16 status )
2421 {
2422         struct  mgsl_icount *icount;
2423 
2424         if ( debug_level >= DEBUG_LEVEL_ISR )
2425                 printk("%s(%d):isr_io_pin status=%04X\n",
2426                         __FILE__,__LINE__,status);
2427 
2428         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2429                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2430                 icount = &info->icount;
2431                 /* update input line counters */
2432                 if (status & MISCSTATUS_RI_LATCHED) {
2433                         icount->rng++;
2434                         if ( status & SerialSignal_RI )
2435                                 info->input_signal_events.ri_up++;
2436                         else
2437                                 info->input_signal_events.ri_down++;
2438                 }
2439                 if (status & MISCSTATUS_DSR_LATCHED) {
2440                         icount->dsr++;
2441                         if ( status & SerialSignal_DSR )
2442                                 info->input_signal_events.dsr_up++;
2443                         else
2444                                 info->input_signal_events.dsr_down++;
2445                 }
2446                 if (status & MISCSTATUS_DCD_LATCHED) {
2447                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2448                                 info->ie1_value &= ~CDCD;
2449                                 write_reg(info, IE1, info->ie1_value);
2450                         }
2451                         icount->dcd++;
2452                         if (status & SerialSignal_DCD) {
2453                                 info->input_signal_events.dcd_up++;
2454                         } else
2455                                 info->input_signal_events.dcd_down++;
2456 #if SYNCLINK_GENERIC_HDLC
2457                         if (info->netcount) {
2458                                 if (status & SerialSignal_DCD)
2459                                         netif_carrier_on(info->netdev);
2460                                 else
2461                                         netif_carrier_off(info->netdev);
2462                         }
2463 #endif
2464                 }
2465                 if (status & MISCSTATUS_CTS_LATCHED)
2466                 {
2467                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2468                                 info->ie1_value &= ~CCTS;
2469                                 write_reg(info, IE1, info->ie1_value);
2470                         }
2471                         icount->cts++;
2472                         if ( status & SerialSignal_CTS )
2473                                 info->input_signal_events.cts_up++;
2474                         else
2475                                 info->input_signal_events.cts_down++;
2476                 }
2477                 wake_up_interruptible(&info->status_event_wait_q);
2478                 wake_up_interruptible(&info->event_wait_q);
2479 
2480                 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2481                      (status & MISCSTATUS_DCD_LATCHED) ) {
2482                         if ( debug_level >= DEBUG_LEVEL_ISR )
2483                                 printk("%s CD now %s...", info->device_name,
2484                                        (status & SerialSignal_DCD) ? "on" : "off");
2485                         if (status & SerialSignal_DCD)
2486                                 wake_up_interruptible(&info->port.open_wait);
2487                         else {
2488                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2489                                         printk("doing serial hangup...");
2490                                 if (info->port.tty)
2491                                         tty_hangup(info->port.tty);
2492                         }
2493                 }
2494 
2495                 if (tty_port_cts_enabled(&info->port) &&
2496                      (status & MISCSTATUS_CTS_LATCHED) ) {
2497                         if ( info->port.tty ) {
2498                                 if (info->port.tty->hw_stopped) {
2499                                         if (status & SerialSignal_CTS) {
2500                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2501                                                         printk("CTS tx start...");
2502                                                 info->port.tty->hw_stopped = 0;
2503                                                 tx_start(info);
2504                                                 info->pending_bh |= BH_TRANSMIT;
2505                                                 return;
2506                                         }
2507                                 } else {
2508                                         if (!(status & SerialSignal_CTS)) {
2509                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2510                                                         printk("CTS tx stop...");
2511                                                 info->port.tty->hw_stopped = 1;
2512                                                 tx_stop(info);
2513                                         }
2514                                 }
2515                         }
2516                 }
2517         }
2518 
2519         info->pending_bh |= BH_STATUS;
2520 }
2521 
2522 /* Interrupt service routine entry point.
2523  *
2524  * Arguments:
2525  *      irq             interrupt number that caused interrupt
2526  *      dev_id          device ID supplied during interrupt registration
2527  *      regs            interrupted processor context
2528  */
2529 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2530 {
2531         SLMP_INFO *info = dev_id;
2532         unsigned char status, status0, status1=0;
2533         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2534         unsigned char timerstatus0, timerstatus1=0;
2535         unsigned char shift;
2536         unsigned int i;
2537         unsigned short tmp;
2538 
2539         if ( debug_level >= DEBUG_LEVEL_ISR )
2540                 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2541                         __FILE__, __LINE__, info->irq_level);
2542 
2543         spin_lock(&info->lock);
2544 
2545         for(;;) {
2546 
2547                 /* get status for SCA0 (ports 0-1) */
2548                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2549                 status0 = (unsigned char)tmp;
2550                 dmastatus0 = (unsigned char)(tmp>>8);
2551                 timerstatus0 = read_reg(info, ISR2);
2552 
2553                 if ( debug_level >= DEBUG_LEVEL_ISR )
2554                         printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2555                                 __FILE__, __LINE__, info->device_name,
2556                                 status0, dmastatus0, timerstatus0);
2557 
2558                 if (info->port_count == 4) {
2559                         /* get status for SCA1 (ports 2-3) */
2560                         tmp = read_reg16(info->port_array[2], ISR0);
2561                         status1 = (unsigned char)tmp;
2562                         dmastatus1 = (unsigned char)(tmp>>8);
2563                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2564 
2565                         if ( debug_level >= DEBUG_LEVEL_ISR )
2566                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2567                                         __FILE__,__LINE__,info->device_name,
2568                                         status1,dmastatus1,timerstatus1);
2569                 }
2570 
2571                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2572                          !status1 && !dmastatus1 && !timerstatus1)
2573                         break;
2574 
2575                 for(i=0; i < info->port_count ; i++) {
2576                         if (info->port_array[i] == NULL)
2577                                 continue;
2578                         if (i < 2) {
2579                                 status = status0;
2580                                 dmastatus = dmastatus0;
2581                         } else {
2582                                 status = status1;
2583                                 dmastatus = dmastatus1;
2584                         }
2585 
2586                         shift = i & 1 ? 4 :0;
2587 
2588                         if (status & BIT0 << shift)
2589                                 isr_rxrdy(info->port_array[i]);
2590                         if (status & BIT1 << shift)
2591                                 isr_txrdy(info->port_array[i]);
2592                         if (status & BIT2 << shift)
2593                                 isr_rxint(info->port_array[i]);
2594                         if (status & BIT3 << shift)
2595                                 isr_txint(info->port_array[i]);
2596 
2597                         if (dmastatus & BIT0 << shift)
2598                                 isr_rxdmaerror(info->port_array[i]);
2599                         if (dmastatus & BIT1 << shift)
2600                                 isr_rxdmaok(info->port_array[i]);
2601                         if (dmastatus & BIT2 << shift)
2602                                 isr_txdmaerror(info->port_array[i]);
2603                         if (dmastatus & BIT3 << shift)
2604                                 isr_txdmaok(info->port_array[i]);
2605                 }
2606 
2607                 if (timerstatus0 & (BIT5 | BIT4))
2608                         isr_timer(info->port_array[0]);
2609                 if (timerstatus0 & (BIT7 | BIT6))
2610                         isr_timer(info->port_array[1]);
2611                 if (timerstatus1 & (BIT5 | BIT4))
2612                         isr_timer(info->port_array[2]);
2613                 if (timerstatus1 & (BIT7 | BIT6))
2614                         isr_timer(info->port_array[3]);
2615         }
2616 
2617         for(i=0; i < info->port_count ; i++) {
2618                 SLMP_INFO * port = info->port_array[i];
2619 
2620                 /* Request bottom half processing if there's something
2621                  * for it to do and the bh is not already running.
2622                  *
2623                  * Note: startup adapter diags require interrupts.
2624                  * do not request bottom half processing if the
2625                  * device is not open in a normal mode.
2626                  */
2627                 if ( port && (port->port.count || port->netcount) &&
2628                      port->pending_bh && !port->bh_running &&
2629                      !port->bh_requested ) {
2630                         if ( debug_level >= DEBUG_LEVEL_ISR )
2631                                 printk("%s(%d):%s queueing bh task.\n",
2632                                         __FILE__,__LINE__,port->device_name);
2633                         schedule_work(&port->task);
2634                         port->bh_requested = true;
2635                 }
2636         }
2637 
2638         spin_unlock(&info->lock);
2639 
2640         if ( debug_level >= DEBUG_LEVEL_ISR )
2641                 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2642                         __FILE__, __LINE__, info->irq_level);
2643         return IRQ_HANDLED;
2644 }
2645 
2646 /* Initialize and start device.
2647  */
2648 static int startup(SLMP_INFO * info)
2649 {
2650         if ( debug_level >= DEBUG_LEVEL_INFO )
2651                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2652 
2653         if (info->port.flags & ASYNC_INITIALIZED)
2654                 return 0;
2655 
2656         if (!info->tx_buf) {
2657                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2658                 if (!info->tx_buf) {
2659                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2660                                 __FILE__,__LINE__,info->device_name);
2661                         return -ENOMEM;
2662                 }
2663         }
2664 
2665         info->pending_bh = 0;
2666 
2667         memset(&info->icount, 0, sizeof(info->icount));
2668 
2669         /* program hardware for current parameters */
2670         reset_port(info);
2671 
2672         change_params(info);
2673 
2674         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2675 
2676         if (info->port.tty)
2677                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2678 
2679         info->port.flags |= ASYNC_INITIALIZED;
2680 
2681         return 0;
2682 }
2683 
2684 /* Called by close() and hangup() to shutdown hardware
2685  */
2686 static void shutdown(SLMP_INFO * info)
2687 {
2688         unsigned long flags;
2689 
2690         if (!(info->port.flags & ASYNC_INITIALIZED))
2691                 return;
2692 
2693         if (debug_level >= DEBUG_LEVEL_INFO)
2694                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2695                          __FILE__,__LINE__, info->device_name );
2696 
2697         /* clear status wait queue because status changes */
2698         /* can't happen after shutting down the hardware */
2699         wake_up_interruptible(&info->status_event_wait_q);
2700         wake_up_interruptible(&info->event_wait_q);
2701 
2702         del_timer(&info->tx_timer);
2703         del_timer(&info->status_timer);
2704 
2705         kfree(info->tx_buf);
2706         info->tx_buf = NULL;
2707 
2708         spin_lock_irqsave(&info->lock,flags);
2709 
2710         reset_port(info);
2711 
2712         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2713                 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2714                 set_signals(info);
2715         }
2716 
2717         spin_unlock_irqrestore(&info->lock,flags);
2718 
2719         if (info->port.tty)
2720                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2721 
2722         info->port.flags &= ~ASYNC_INITIALIZED;
2723 }
2724 
2725 static void program_hw(SLMP_INFO *info)
2726 {
2727         unsigned long flags;
2728 
2729         spin_lock_irqsave(&info->lock,flags);
2730 
2731         rx_stop(info);
2732         tx_stop(info);
2733 
2734         info->tx_count = info->tx_put = info->tx_get = 0;
2735 
2736         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2737                 hdlc_mode(info);
2738         else
2739                 async_mode(info);
2740 
2741         set_signals(info);
2742 
2743         info->dcd_chkcount = 0;
2744         info->cts_chkcount = 0;
2745         info->ri_chkcount = 0;
2746         info->dsr_chkcount = 0;
2747 
2748         info->ie1_value |= (CDCD|CCTS);
2749         write_reg(info, IE1, info->ie1_value);
2750 
2751         get_signals(info);
2752 
2753         if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2754                 rx_start(info);
2755 
2756         spin_unlock_irqrestore(&info->lock,flags);
2757 }
2758 
2759 /* Reconfigure adapter based on new parameters
2760  */
2761 static void change_params(SLMP_INFO *info)
2762 {
2763         unsigned cflag;
2764         int bits_per_char;
2765 
2766         if (!info->port.tty)
2767                 return;
2768 
2769         if (debug_level >= DEBUG_LEVEL_INFO)
2770                 printk("%s(%d):%s change_params()\n",
2771                          __FILE__,__LINE__, info->device_name );
2772 
2773         cflag = info->port.tty->termios.c_cflag;
2774 
2775         /* if B0 rate (hangup) specified then negate RTS and DTR */
2776         /* otherwise assert RTS and DTR */
2777         if (cflag & CBAUD)
2778                 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
2779         else
2780                 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2781 
2782         /* byte size and parity */
2783 
2784         switch (cflag & CSIZE) {
2785               case CS5: info->params.data_bits = 5; break;
2786               case CS6: info->params.data_bits = 6; break;
2787               case CS7: info->params.data_bits = 7; break;
2788               case CS8: info->params.data_bits = 8; break;
2789               /* Never happens, but GCC is too dumb to figure it out */
2790               default:  info->params.data_bits = 7; break;
2791               }
2792 
2793         if (cflag & CSTOPB)
2794                 info->params.stop_bits = 2;
2795         else
2796                 info->params.stop_bits = 1;
2797 
2798         info->params.parity = ASYNC_PARITY_NONE;
2799         if (cflag & PARENB) {
2800                 if (cflag & PARODD)
2801                         info->params.parity = ASYNC_PARITY_ODD;
2802                 else
2803                         info->params.parity = ASYNC_PARITY_EVEN;
2804 #ifdef CMSPAR
2805                 if (cflag & CMSPAR)
2806                         info->params.parity = ASYNC_PARITY_SPACE;
2807 #endif
2808         }
2809 
2810         /* calculate number of jiffies to transmit a full
2811          * FIFO (32 bytes) at specified data rate
2812          */
2813         bits_per_char = info->params.data_bits +
2814                         info->params.stop_bits + 1;
2815 
2816         /* if port data rate is set to 460800 or less then
2817          * allow tty settings to override, otherwise keep the
2818          * current data rate.
2819          */
2820         if (info->params.data_rate <= 460800) {
2821                 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2822         }
2823 
2824         if ( info->params.data_rate ) {
2825                 info->timeout = (32*HZ*bits_per_char) /
2826                                 info->params.data_rate;
2827         }
2828         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2829 
2830         if (cflag & CRTSCTS)
2831                 info->port.flags |= ASYNC_CTS_FLOW;
2832         else
2833                 info->port.flags &= ~ASYNC_CTS_FLOW;
2834 
2835         if (cflag & CLOCAL)
2836                 info->port.flags &= ~ASYNC_CHECK_CD;
2837         else
2838                 info->port.flags |= ASYNC_CHECK_CD;
2839 
2840         /* process tty input control flags */
2841 
2842         info->read_status_mask2 = OVRN;
2843         if (I_INPCK(info->port.tty))
2844                 info->read_status_mask2 |= PE | FRME;
2845         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2846                 info->read_status_mask1 |= BRKD;
2847         if (I_IGNPAR(info->port.tty))
2848                 info->ignore_status_mask2 |= PE | FRME;
2849         if (I_IGNBRK(info->port.tty)) {
2850                 info->ignore_status_mask1 |= BRKD;
2851                 /* If ignoring parity and break indicators, ignore
2852                  * overruns too.  (For real raw support).
2853                  */
2854                 if (I_IGNPAR(info->port.tty))
2855                         info->ignore_status_mask2 |= OVRN;
2856         }
2857 
2858         program_hw(info);
2859 }
2860 
2861 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2862 {
2863         int err;
2864 
2865         if (debug_level >= DEBUG_LEVEL_INFO)
2866                 printk("%s(%d):%s get_params()\n",
2867                          __FILE__,__LINE__, info->device_name);
2868 
2869         if (!user_icount) {
2870                 memset(&info->icount, 0, sizeof(info->icount));
2871         } else {
2872                 mutex_lock(&info->port.mutex);
2873                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2874                 mutex_unlock(&info->port.mutex);
2875                 if (err)
2876                         return -EFAULT;
2877         }
2878 
2879         return 0;
2880 }
2881 
2882 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2883 {
2884         int err;
2885         if (debug_level >= DEBUG_LEVEL_INFO)
2886                 printk("%s(%d):%s get_params()\n",
2887                          __FILE__,__LINE__, info->device_name);
2888 
2889         mutex_lock(&info->port.mutex);
2890         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2891         mutex_unlock(&info->port.mutex);
2892         if (err) {
2893                 if ( debug_level >= DEBUG_LEVEL_INFO )
2894                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2895                                 __FILE__,__LINE__,info->device_name);
2896                 return -EFAULT;
2897         }
2898 
2899         return 0;
2900 }
2901 
2902 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2903 {
2904         unsigned long flags;
2905         MGSL_PARAMS tmp_params;
2906         int err;
2907 
2908         if (debug_level >= DEBUG_LEVEL_INFO)
2909                 printk("%s(%d):%s set_params\n",
2910                         __FILE__,__LINE__,info->device_name );
2911         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2912         if (err) {
2913                 if ( debug_level >= DEBUG_LEVEL_INFO )
2914                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2915                                 __FILE__,__LINE__,info->device_name);
2916                 return -EFAULT;
2917         }
2918 
2919         mutex_lock(&info->port.mutex);
2920         spin_lock_irqsave(&info->lock,flags);
2921         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2922         spin_unlock_irqrestore(&info->lock,flags);
2923 
2924         change_params(info);
2925         mutex_unlock(&info->port.mutex);
2926 
2927         return 0;
2928 }
2929 
2930 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2931 {
2932         int err;
2933 
2934         if (debug_level >= DEBUG_LEVEL_INFO)
2935                 printk("%s(%d):%s get_txidle()=%d\n",
2936                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2937 
2938         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2939         if (err) {
2940                 if ( debug_level >= DEBUG_LEVEL_INFO )
2941                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2942                                 __FILE__,__LINE__,info->device_name);
2943                 return -EFAULT;
2944         }
2945 
2946         return 0;
2947 }
2948 
2949 static int set_txidle(SLMP_INFO * info, int idle_mode)
2950 {
2951         unsigned long flags;
2952 
2953         if (debug_level >= DEBUG_LEVEL_INFO)
2954                 printk("%s(%d):%s set_txidle(%d)\n",
2955                         __FILE__,__LINE__,info->device_name, idle_mode );
2956 
2957         spin_lock_irqsave(&info->lock,flags);
2958         info->idle_mode = idle_mode;
2959         tx_set_idle( info );
2960         spin_unlock_irqrestore(&info->lock,flags);
2961         return 0;
2962 }
2963 
2964 static int tx_enable(SLMP_INFO * info, int enable)
2965 {
2966         unsigned long flags;
2967 
2968         if (debug_level >= DEBUG_LEVEL_INFO)
2969                 printk("%s(%d):%s tx_enable(%d)\n",
2970                         __FILE__,__LINE__,info->device_name, enable);
2971 
2972         spin_lock_irqsave(&info->lock,flags);
2973         if ( enable ) {
2974                 if ( !info->tx_enabled ) {
2975                         tx_start(info);
2976                 }
2977         } else {
2978                 if ( info->tx_enabled )
2979                         tx_stop(info);
2980         }
2981         spin_unlock_irqrestore(&info->lock,flags);
2982         return 0;
2983 }
2984 
2985 /* abort send HDLC frame
2986  */
2987 static int tx_abort(SLMP_INFO * info)
2988 {
2989         unsigned long flags;
2990 
2991         if (debug_level >= DEBUG_LEVEL_INFO)
2992                 printk("%s(%d):%s tx_abort()\n",
2993                         __FILE__,__LINE__,info->device_name);
2994 
2995         spin_lock_irqsave(&info->lock,flags);
2996         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2997                 info->ie1_value &= ~UDRN;
2998                 info->ie1_value |= IDLE;
2999                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3000                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3001 
3002                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3003                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3004 
3005                 write_reg(info, CMD, TXABORT);
3006         }
3007         spin_unlock_irqrestore(&info->lock,flags);
3008         return 0;
3009 }
3010 
3011 static int rx_enable(SLMP_INFO * info, int enable)
3012 {
3013         unsigned long flags;
3014 
3015         if (debug_level >= DEBUG_LEVEL_INFO)
3016                 printk("%s(%d):%s rx_enable(%d)\n",
3017                         __FILE__,__LINE__,info->device_name,enable);
3018 
3019         spin_lock_irqsave(&info->lock,flags);
3020         if ( enable ) {
3021                 if ( !info->rx_enabled )
3022                         rx_start(info);
3023         } else {
3024                 if ( info->rx_enabled )
3025                         rx_stop(info);
3026         }
3027         spin_unlock_irqrestore(&info->lock,flags);
3028         return 0;
3029 }
3030 
3031 /* wait for specified event to occur
3032  */
3033 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3034 {
3035         unsigned long flags;
3036         int s;
3037         int rc=0;
3038         struct mgsl_icount cprev, cnow;
3039         int events;
3040         int mask;
3041         struct  _input_signal_events oldsigs, newsigs;
3042         DECLARE_WAITQUEUE(wait, current);
3043 
3044         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3045         if (rc) {
3046                 return  -EFAULT;
3047         }
3048 
3049         if (debug_level >= DEBUG_LEVEL_INFO)
3050                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3051                         __FILE__,__LINE__,info->device_name,mask);
3052 
3053         spin_lock_irqsave(&info->lock,flags);
3054 
3055         /* return immediately if state matches requested events */
3056         get_signals(info);
3057         s = info->serial_signals;
3058 
3059         events = mask &
3060                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3061                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3062                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3063                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3064         if (events) {
3065                 spin_unlock_irqrestore(&info->lock,flags);
3066                 goto exit;
3067         }
3068 
3069         /* save current irq counts */
3070         cprev = info->icount;
3071         oldsigs = info->input_signal_events;
3072 
3073         /* enable hunt and idle irqs if needed */
3074         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3075                 unsigned char oldval = info->ie1_value;
3076                 unsigned char newval = oldval +
3077                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3078                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3079                 if ( oldval != newval ) {
3080                         info->ie1_value = newval;
3081                         write_reg(info, IE1, info->ie1_value);
3082                 }
3083         }
3084 
3085         set_current_state(TASK_INTERRUPTIBLE);
3086         add_wait_queue(&info->event_wait_q, &wait);
3087 
3088         spin_unlock_irqrestore(&info->lock,flags);
3089 
3090         for(;;) {
3091                 schedule();
3092                 if (signal_pending(current)) {
3093                         rc = -ERESTARTSYS;
3094                         break;
3095                 }
3096 
3097                 /* get current irq counts */
3098                 spin_lock_irqsave(&info->lock,flags);
3099                 cnow = info->icount;
3100                 newsigs = info->input_signal_events;
3101                 set_current_state(TASK_INTERRUPTIBLE);
3102                 spin_unlock_irqrestore(&info->lock,flags);
3103 
3104                 /* if no change, wait aborted for some reason */
3105                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3106                     newsigs.dsr_down == oldsigs.dsr_down &&
3107                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3108                     newsigs.dcd_down == oldsigs.dcd_down &&
3109                     newsigs.cts_up   == oldsigs.cts_up   &&
3110                     newsigs.cts_down == oldsigs.cts_down &&
3111                     newsigs.ri_up    == oldsigs.ri_up    &&
3112                     newsigs.ri_down  == oldsigs.ri_down  &&
3113                     cnow.exithunt    == cprev.exithunt   &&
3114                     cnow.rxidle      == cprev.rxidle) {
3115                         rc = -EIO;
3116                         break;
3117                 }
3118 
3119                 events = mask &
3120                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3121                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3122                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3123                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3124                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3125                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3126                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3127                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3128                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3129                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3130                 if (events)
3131                         break;
3132 
3133                 cprev = cnow;
3134                 oldsigs = newsigs;
3135         }
3136 
3137         remove_wait_queue(&info->event_wait_q, &wait);
3138         set_current_state(TASK_RUNNING);
3139 
3140 
3141         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3142                 spin_lock_irqsave(&info->lock,flags);
3143                 if (!waitqueue_active(&info->event_wait_q)) {
3144                         /* disable enable exit hunt mode/idle rcvd IRQs */
3145                         info->ie1_value &= ~(FLGD|IDLD);
3146                         write_reg(info, IE1, info->ie1_value);
3147                 }
3148                 spin_unlock_irqrestore(&info->lock,flags);
3149         }
3150 exit:
3151         if ( rc == 0 )
3152                 PUT_USER(rc, events, mask_ptr);
3153 
3154         return rc;
3155 }
3156 
3157 static int modem_input_wait(SLMP_INFO *info,int arg)
3158 {
3159         unsigned long flags;
3160         int rc;
3161         struct mgsl_icount cprev, cnow;
3162         DECLARE_WAITQUEUE(wait, current);
3163 
3164         /* save current irq counts */
3165         spin_lock_irqsave(&info->lock,flags);
3166         cprev = info->icount;
3167         add_wait_queue(&info->status_event_wait_q, &wait);
3168         set_current_state(TASK_INTERRUPTIBLE);
3169         spin_unlock_irqrestore(&info->lock,flags);
3170 
3171         for(;;) {
3172                 schedule();
3173                 if (signal_pending(current)) {
3174                         rc = -ERESTARTSYS;
3175                         break;
3176                 }
3177 
3178                 /* get new irq counts */
3179                 spin_lock_irqsave(&info->lock,flags);
3180                 cnow = info->icount;
3181                 set_current_state(TASK_INTERRUPTIBLE);
3182                 spin_unlock_irqrestore(&info->lock,flags);
3183 
3184                 /* if no change, wait aborted for some reason */
3185                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3186                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3187                         rc = -EIO;
3188                         break;
3189                 }
3190 
3191                 /* check for change in caller specified modem input */
3192                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3193                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3194                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3195                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3196                         rc = 0;
3197                         break;
3198                 }
3199 
3200                 cprev = cnow;
3201         }
3202         remove_wait_queue(&info->status_event_wait_q, &wait);
3203         set_current_state(TASK_RUNNING);
3204         return rc;
3205 }
3206 
3207 /* return the state of the serial control and status signals
3208  */
3209 static int tiocmget(struct tty_struct *tty)
3210 {
3211         SLMP_INFO *info = tty->driver_data;
3212         unsigned int result;
3213         unsigned long flags;
3214 
3215         spin_lock_irqsave(&info->lock,flags);
3216         get_signals(info);
3217         spin_unlock_irqrestore(&info->lock,flags);
3218 
3219         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3220                  ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3221                  ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3222                  ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG : 0) |
3223                  ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3224                  ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
3225 
3226         if (debug_level >= DEBUG_LEVEL_INFO)
3227                 printk("%s(%d):%s tiocmget() value=%08X\n",
3228                          __FILE__,__LINE__, info->device_name, result );
3229         return result;
3230 }
3231 
3232 /* set modem control signals (DTR/RTS)
3233  */
3234 static int tiocmset(struct tty_struct *tty,
3235                                         unsigned int set, unsigned int clear)
3236 {
3237         SLMP_INFO *info = tty->driver_data;
3238         unsigned long flags;
3239 
3240         if (debug_level >= DEBUG_LEVEL_INFO)
3241                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3242                         __FILE__,__LINE__,info->device_name, set, clear);
3243 
3244         if (set & TIOCM_RTS)
3245                 info->serial_signals |= SerialSignal_RTS;
3246         if (set & TIOCM_DTR)
3247                 info->serial_signals |= SerialSignal_DTR;
3248         if (clear & TIOCM_RTS)
3249                 info->serial_signals &= ~SerialSignal_RTS;
3250         if (clear & TIOCM_DTR)
3251                 info->serial_signals &= ~SerialSignal_DTR;
3252 
3253         spin_lock_irqsave(&info->lock,flags);
3254         set_signals(info);
3255         spin_unlock_irqrestore(&info->lock,flags);
3256 
3257         return 0;
3258 }
3259 
3260 static int carrier_raised(struct tty_port *port)
3261 {
3262         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3263         unsigned long flags;
3264 
3265         spin_lock_irqsave(&info->lock,flags);
3266         get_signals(info);
3267         spin_unlock_irqrestore(&info->lock,flags);
3268 
3269         return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3270 }
3271 
3272 static void dtr_rts(struct tty_port *port, int on)
3273 {
3274         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3275         unsigned long flags;
3276 
3277         spin_lock_irqsave(&info->lock,flags);
3278         if (on)
3279                 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3280         else
3281                 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3282         set_signals(info);
3283         spin_unlock_irqrestore(&info->lock,flags);
3284 }
3285 
3286 /* Block the current process until the specified port is ready to open.
3287  */
3288 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3289                            SLMP_INFO *info)
3290 {
3291         DECLARE_WAITQUEUE(wait, current);
3292         int             retval;
3293         bool            do_clocal = false;
3294         unsigned long   flags;
3295         int             cd;
3296         struct tty_port *port = &info->port;
3297 
3298         if (debug_level >= DEBUG_LEVEL_INFO)
3299                 printk("%s(%d):%s block_til_ready()\n",
3300                          __FILE__,__LINE__, tty->driver->name );
3301 
3302         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3303                 /* nonblock mode is set or port is not enabled */
3304                 /* just verify that callout device is not active */
3305                 port->flags |= ASYNC_NORMAL_ACTIVE;
3306                 return 0;
3307         }
3308 
3309         if (tty->termios.c_cflag & CLOCAL)
3310                 do_clocal = true;
3311 
3312         /* Wait for carrier detect and the line to become
3313          * free (i.e., not in use by the callout).  While we are in
3314          * this loop, port->count is dropped by one, so that
3315          * close() knows when to free things.  We restore it upon
3316          * exit, either normal or abnormal.
3317          */
3318 
3319         retval = 0;
3320         add_wait_queue(&port->open_wait, &wait);
3321 
3322         if (debug_level >= DEBUG_LEVEL_INFO)
3323                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3324                          __FILE__,__LINE__, tty->driver->name, port->count );
3325 
3326         spin_lock_irqsave(&info->lock, flags);
3327         port->count--;
3328         spin_unlock_irqrestore(&info->lock, flags);
3329         port->blocked_open++;
3330 
3331         while (1) {
3332                 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3333                         tty_port_raise_dtr_rts(port);
3334 
3335                 set_current_state(TASK_INTERRUPTIBLE);
3336 
3337                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3338                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3339                                         -EAGAIN : -ERESTARTSYS;
3340                         break;
3341                 }
3342 
3343                 cd = tty_port_carrier_raised(port);
3344 
3345                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3346                         break;
3347 
3348                 if (signal_pending(current)) {
3349                         retval = -ERESTARTSYS;
3350                         break;
3351                 }
3352 
3353                 if (debug_level >= DEBUG_LEVEL_INFO)
3354                         printk("%s(%d):%s block_til_ready() count=%d\n",
3355                                  __FILE__,__LINE__, tty->driver->name, port->count );
3356 
3357                 tty_unlock(tty);
3358                 schedule();
3359                 tty_lock(tty);
3360         }
3361 
3362         set_current_state(TASK_RUNNING);
3363         remove_wait_queue(&port->open_wait, &wait);
3364         if (!tty_hung_up_p(filp))
3365                 port->count++;
3366         port->blocked_open--;
3367 
3368         if (debug_level >= DEBUG_LEVEL_INFO)
3369                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3370                          __FILE__,__LINE__, tty->driver->name, port->count );
3371 
3372         if (!retval)
3373                 port->flags |= ASYNC_NORMAL_ACTIVE;
3374 
3375         return retval;
3376 }
3377 
3378 static int alloc_dma_bufs(SLMP_INFO *info)
3379 {
3380         unsigned short BuffersPerFrame;
3381         unsigned short BufferCount;
3382 
3383         // Force allocation to start at 64K boundary for each port.
3384         // This is necessary because *all* buffer descriptors for a port
3385         // *must* be in the same 64K block. All descriptors on a port
3386         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3387         // into the CBP register.
3388         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3389 
3390         /* Calculate the number of DMA buffers necessary to hold the */
3391         /* largest allowable frame size. Note: If the max frame size is */
3392         /* not an even multiple of the DMA buffer size then we need to */
3393         /* round the buffer count per frame up one. */
3394 
3395         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3396         if ( info->max_frame_size % SCABUFSIZE )
3397                 BuffersPerFrame++;
3398 
3399         /* calculate total number of data buffers (SCABUFSIZE) possible
3400          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3401          * for the descriptor list (BUFFERLISTSIZE).
3402          */
3403         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3404 
3405         /* limit number of buffers to maximum amount of descriptors */
3406         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3407                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3408 
3409         /* use enough buffers to transmit one max size frame */
3410         info->tx_buf_count = BuffersPerFrame + 1;
3411 
3412         /* never use more than half the available buffers for transmit */
3413         if (info->tx_buf_count > (BufferCount/2))
3414                 info->tx_buf_count = BufferCount/2;
3415 
3416         if (info->tx_buf_count > SCAMAXDESC)
3417                 info->tx_buf_count = SCAMAXDESC;
3418 
3419         /* use remaining buffers for receive */
3420         info->rx_buf_count = BufferCount - info->tx_buf_count;
3421 
3422         if (info->rx_buf_count > SCAMAXDESC)
3423                 info->rx_buf_count = SCAMAXDESC;
3424 
3425         if ( debug_level >= DEBUG_LEVEL_INFO )
3426                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3427                         __FILE__,__LINE__, info->device_name,
3428                         info->tx_buf_count,info->rx_buf_count);
3429 
3430         if ( alloc_buf_list( info ) < 0 ||
3431                 alloc_frame_bufs(info,
3432                                         info->rx_buf_list,
3433                                         info->rx_buf_list_ex,
3434                                         info->rx_buf_count) < 0 ||
3435                 alloc_frame_bufs(info,
3436                                         info->tx_buf_list,
3437                                         info->tx_buf_list_ex,
3438                                         info->tx_buf_count) < 0 ||
3439                 alloc_tmp_rx_buf(info) < 0 ) {
3440                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3441                         __FILE__,__LINE__, info->device_name);
3442                 return -ENOMEM;
3443         }
3444 
3445         rx_reset_buffers( info );
3446 
3447         return 0;
3448 }
3449 
3450 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3451  */
3452 static int alloc_buf_list(SLMP_INFO *info)
3453 {
3454         unsigned int i;
3455 
3456         /* build list in adapter shared memory */
3457         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3458         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3459         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3460 
3461         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3462 
3463         /* Save virtual address pointers to the receive and */
3464         /* transmit buffer lists. (Receive 1st). These pointers will */
3465         /* be used by the processor to access the lists. */
3466         info->rx_buf_list = (SCADESC *)info->buffer_list;
3467 
3468         info->tx_buf_list = (SCADESC *)info->buffer_list;
3469         info->tx_buf_list += info->rx_buf_count;
3470 
3471         /* Build links for circular buffer entry lists (tx and rx)
3472          *
3473          * Note: links are physical addresses read by the SCA device
3474          * to determine the next buffer entry to use.
3475          */
3476 
3477         for ( i = 0; i < info->rx_buf_count; i++ ) {
3478                 /* calculate and store physical address of this buffer entry */
3479                 info->rx_buf_list_ex[i].phys_entry =
3480                         info->buffer_list_phys + (i * SCABUFSIZE);
3481 
3482                 /* calculate and store physical address of */
3483                 /* next entry in cirular list of entries */
3484                 info->rx_buf_list[i].next = info->buffer_list_phys;
3485                 if ( i < info->rx_buf_count - 1 )
3486                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3487 
3488                 info->rx_buf_list[i].length = SCABUFSIZE;
3489         }
3490 
3491         for ( i = 0; i < info->tx_buf_count; i++ ) {
3492                 /* calculate and store physical address of this buffer entry */
3493                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3494                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3495 
3496                 /* calculate and store physical address of */
3497                 /* next entry in cirular list of entries */
3498 
3499                 info->tx_buf_list[i].next = info->buffer_list_phys +
3500                         info->rx_buf_count * sizeof(SCADESC);
3501 
3502                 if ( i < info->tx_buf_count - 1 )
3503                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3504         }
3505 
3506         return 0;
3507 }
3508 
3509 /* Allocate the frame DMA buffers used by the specified buffer list.
3510  */
3511 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3512 {
3513         int i;
3514         unsigned long phys_addr;
3515 
3516         for ( i = 0; i < count; i++ ) {
3517                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3518                 phys_addr = info->port_array[0]->last_mem_alloc;
3519                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3520 
3521                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3522                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3523         }
3524 
3525         return 0;
3526 }
3527 
3528 static void free_dma_bufs(SLMP_INFO *info)
3529 {
3530         info->buffer_list = NULL;
3531         info->rx_buf_list = NULL;
3532         info->tx_buf_list = NULL;
3533 }
3534 
3535 /* allocate buffer large enough to hold max_frame_size.
3536  * This buffer is used to pass an assembled frame to the line discipline.
3537  */
3538 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3539 {
3540         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3541         if (info->tmp_rx_buf == NULL)
3542                 return -ENOMEM;
3543         /* unused flag buffer to satisfy receive_buf calling interface */
3544         info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3545         if (!info->flag_buf) {
3546                 kfree(info->tmp_rx_buf);
3547                 info->tmp_rx_buf = NULL;
3548                 return -ENOMEM;
3549         }
3550         return 0;
3551 }
3552 
3553 static void free_tmp_rx_buf(SLMP_INFO *info)
3554 {
3555         kfree(info->tmp_rx_buf);
3556         info->tmp_rx_buf = NULL;
3557         kfree(info->flag_buf);
3558         info->flag_buf = NULL;
3559 }
3560 
3561 static int claim_resources(SLMP_INFO *info)
3562 {
3563         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3564                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3565                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3566                 info->init_error = DiagStatus_AddressConflict;
3567                 goto errout;
3568         }
3569         else
3570                 info->shared_mem_requested = true;
3571 
3572         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3573                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3574                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3575                 info->init_error = DiagStatus_AddressConflict;
3576                 goto errout;
3577         }
3578         else
3579                 info->lcr_mem_requested = true;
3580 
3581         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3582                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3583                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3584                 info->init_error = DiagStatus_AddressConflict;
3585                 goto errout;
3586         }
3587         else
3588                 info->sca_base_requested = true;
3589 
3590         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3591                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3592                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3593                 info->init_error = DiagStatus_AddressConflict;
3594                 goto errout;
3595         }
3596         else
3597                 info->sca_statctrl_requested = true;
3598 
3599         info->memory_base = ioremap_nocache(info->phys_memory_base,
3600                                                                 SCA_MEM_SIZE);
3601         if (!info->memory_base) {
3602                 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3603                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3604                 info->init_error = DiagStatus_CantAssignPciResources;
3605                 goto errout;
3606         }
3607 
3608         info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3609         if (!info->lcr_base) {
3610                 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3611                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3612                 info->init_error = DiagStatus_CantAssignPciResources;
3613                 goto errout;
3614         }
3615         info->lcr_base += info->lcr_offset;
3616 
3617         info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3618         if (!info->sca_base) {
3619                 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3620                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3621                 info->init_error = DiagStatus_CantAssignPciResources;
3622                 goto errout;
3623         }
3624         info->sca_base += info->sca_offset;
3625 
3626         info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3627                                                                 PAGE_SIZE);
3628         if (!info->statctrl_base) {
3629                 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3630                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3631                 info->init_error = DiagStatus_CantAssignPciResources;
3632                 goto errout;
3633         }
3634         info->statctrl_base += info->statctrl_offset;
3635 
3636         if ( !memory_test(info) ) {
3637                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3638                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3639                 info->init_error = DiagStatus_MemoryError;
3640                 goto errout;
3641         }
3642 
3643         return 0;
3644 
3645 errout:
3646         release_resources( info );
3647         return -ENODEV;
3648 }
3649 
3650 static void release_resources(SLMP_INFO *info)
3651 {
3652         if ( debug_level >= DEBUG_LEVEL_INFO )
3653                 printk( "%s(%d):%s release_resources() entry\n",
3654                         __FILE__,__LINE__,info->device_name );
3655 
3656         if ( info->irq_requested ) {
3657                 free_irq(info->irq_level, info);
3658                 info->irq_requested = false;
3659         }
3660 
3661         if ( info->shared_mem_requested ) {
3662                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3663                 info->shared_mem_requested = false;
3664         }
3665         if ( info->lcr_mem_requested ) {
3666                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3667                 info->lcr_mem_requested = false;
3668         }
3669         if ( info->sca_base_requested ) {
3670                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3671                 info->sca_base_requested = false;
3672         }
3673         if ( info->sca_statctrl_requested ) {
3674                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3675                 info->sca_statctrl_requested = false;
3676         }
3677 
3678         if (info->memory_base){
3679                 iounmap(info->memory_base);
3680                 info->memory_base = NULL;
3681         }
3682 
3683         if (info->sca_base) {
3684                 iounmap(info->sca_base - info->sca_offset);
3685                 info->sca_base=NULL;
3686         }
3687 
3688         if (info->statctrl_base) {
3689                 iounmap(info->statctrl_base - info->statctrl_offset);
3690                 info->statctrl_base=NULL;
3691         }
3692 
3693         if (info->lcr_base){
3694                 iounmap(info->lcr_base - info->lcr_offset);
3695                 info->lcr_base = NULL;
3696         }
3697 
3698         if ( debug_level >= DEBUG_LEVEL_INFO )
3699                 printk( "%s(%d):%s release_resources() exit\n",
3700                         __FILE__,__LINE__,info->device_name );
3701 }
3702 
3703 /* Add the specified device instance data structure to the
3704  * global linked list of devices and increment the device count.
3705  */
3706 static void add_device(SLMP_INFO *info)
3707 {
3708         info->next_device = NULL;
3709         info->line = synclinkmp_device_count;
3710         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3711 
3712         if (info->line < MAX_DEVICES) {
3713                 if (maxframe[info->line])
3714                         info->max_frame_size = maxframe[info->line];
3715         }
3716 
3717         synclinkmp_device_count++;
3718 
3719         if ( !synclinkmp_device_list )
3720                 synclinkmp_device_list = info;
3721         else {
3722                 SLMP_INFO *current_dev = synclinkmp_device_list;
3723                 while( current_dev->next_device )
3724                         current_dev = current_dev->next_device;
3725                 current_dev->next_device = info;
3726         }
3727 
3728         if ( info->max_frame_size < 4096 )
3729                 info->max_frame_size = 4096;
3730         else if ( info->max_frame_size > 65535 )
3731                 info->max_frame_size = 65535;
3732 
3733         printk( "SyncLink MultiPort %s: "
3734                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3735                 info->device_name,
3736                 info->phys_sca_base,
3737                 info->phys_memory_base,
3738                 info->phys_statctrl_base,
3739                 info->phys_lcr_base,
3740                 info->irq_level,
3741                 info->max_frame_size );
3742 
3743 #if SYNCLINK_GENERIC_HDLC
3744         hdlcdev_init(info);
3745 #endif
3746 }
3747 
3748 static const struct tty_port_operations port_ops = {
3749         .carrier_raised = carrier_raised,
3750         .dtr_rts = dtr_rts,
3751 };
3752 
3753 /* Allocate and initialize a device instance structure
3754  *
3755  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3756  */
3757 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3758 {
3759         SLMP_INFO *info;
3760 
3761         info = kzalloc(sizeof(SLMP_INFO),
3762                  GFP_KERNEL);
3763 
3764         if (!info) {
3765                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3766                         __FILE__,__LINE__, adapter_num, port_num);
3767         } else {
3768                 tty_port_init(&info->port);
3769                 info->port.ops = &port_ops;
3770                 info->magic = MGSL_MAGIC;
3771                 INIT_WORK(&info->task, bh_handler);
3772                 info->max_frame_size = 4096;
3773                 info->port.close_delay = 5*HZ/10;
3774                 info->port.closing_wait = 30*HZ;
3775                 init_waitqueue_head(&info->status_event_wait_q);
3776                 init_waitqueue_head(&info->event_wait_q);
3777                 spin_lock_init(&info->netlock);
3778                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3779                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3780                 info->adapter_num = adapter_num;
3781                 info->port_num = port_num;
3782 
3783                 /* Copy configuration info to device instance data */
3784                 info->irq_level = pdev->irq;
3785                 info->phys_lcr_base = pci_resource_start(pdev,0);
3786                 info->phys_sca_base = pci_resource_start(pdev,2);
3787                 info->phys_memory_base = pci_resource_start(pdev,3);
3788                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3789 
3790                 /* Because veremap only works on page boundaries we must map
3791                  * a larger area than is actually implemented for the LCR
3792                  * memory range. We map a full page starting at the page boundary.
3793                  */
3794                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3795                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3796 
3797                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3798                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3799 
3800                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3801                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3802 
3803                 info->bus_type = MGSL_BUS_TYPE_PCI;
3804                 info->irq_flags = IRQF_SHARED;
3805 
3806                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3807                 setup_timer(&info->status_timer, status_timeout,
3808                                 (unsigned long)info);
3809 
3810                 /* Store the PCI9050 misc control register value because a flaw
3811                  * in the PCI9050 prevents LCR registers from being read if
3812                  * BIOS assigns an LCR base address with bit 7 set.
3813                  *
3814                  * Only the misc control register is accessed for which only
3815                  * write access is needed, so set an initial value and change
3816                  * bits to the device instance data as we write the value
3817                  * to the actual misc control register.
3818                  */
3819                 info->misc_ctrl_value = 0x087e4546;
3820 
3821                 /* initial port state is unknown - if startup errors
3822                  * occur, init_error will be set to indicate the
3823                  * problem. Once the port is fully initialized,
3824                  * this value will be set to 0 to indicate the
3825                  * port is available.
3826                  */
3827                 info->init_error = -1;
3828         }
3829 
3830         return info;
3831 }
3832 
3833 static void device_init(int adapter_num, struct pci_dev *pdev)
3834 {
3835         SLMP_INFO *port_array[SCA_MAX_PORTS];
3836         int port;
3837 
3838         /* allocate device instances for up to SCA_MAX_PORTS devices */
3839         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3840                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3841                 if( port_array[port] == NULL ) {
3842                         for (--port; port >= 0; --port) {
3843                                 tty_port_destroy(&port_array[port]->port);
3844                                 kfree(port_array[port]);
3845                         }
3846                         return;
3847                 }
3848         }
3849 
3850         /* give copy of port_array to all ports and add to device list  */
3851         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3852                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3853                 add_device( port_array[port] );
3854                 spin_lock_init(&port_array[port]->lock);
3855         }
3856 
3857         /* Allocate and claim adapter resources */
3858         if ( !claim_resources(port_array[0]) ) {
3859 
3860                 alloc_dma_bufs(port_array[0]);
3861 
3862                 /* copy resource information from first port to others */
3863                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3864                         port_array[port]->lock  = port_array[0]->lock;
3865                         port_array[port]->irq_level     = port_array[0]->irq_level;
3866                         port_array[port]->memory_base   = port_array[0]->memory_base;
3867                         port_array[port]->sca_base      = port_array[0]->sca_base;
3868                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3869                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3870                         alloc_dma_bufs(port_array[port]);
3871                 }
3872 
3873                 if ( request_irq(port_array[0]->irq_level,
3874                                         synclinkmp_interrupt,
3875                                         port_array[0]->irq_flags,
3876                                         port_array[0]->device_name,
3877                                         port_array[0]) < 0 ) {
3878                         printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3879                                 __FILE__,__LINE__,
3880                                 port_array[0]->device_name,
3881                                 port_array[0]->irq_level );
3882                 }
3883                 else {
3884                         port_array[0]->irq_requested = true;
3885                         adapter_test(port_array[0]);
3886                 }
3887         }
3888 }
3889 
3890 static const struct tty_operations ops = {
3891         .install = install,
3892         .open = open,
3893         .close = close,
3894         .write = write,
3895         .put_char = put_char,
3896         .flush_chars = flush_chars,
3897         .write_room = write_room,
3898         .chars_in_buffer = chars_in_buffer,
3899         .flush_buffer = flush_buffer,
3900         .ioctl = ioctl,
3901         .throttle = throttle,
3902         .unthrottle = unthrottle,
3903         .send_xchar = send_xchar,
3904         .break_ctl = set_break,
3905         .wait_until_sent = wait_until_sent,
3906         .set_termios = set_termios,
3907         .stop = tx_hold,
3908         .start = tx_release,
3909         .hangup = hangup,
3910         .tiocmget = tiocmget,
3911         .tiocmset = tiocmset,
3912         .get_icount = get_icount,
3913         .proc_fops = &synclinkmp_proc_fops,
3914 };
3915 
3916 
3917 static void synclinkmp_cleanup(void)
3918 {
3919         int rc;
3920         SLMP_INFO *info;
3921         SLMP_INFO *tmp;
3922 
3923         printk("Unloading %s %s\n", driver_name, driver_version);
3924 
3925         if (serial_driver) {
3926                 rc = tty_unregister_driver(serial_driver);
3927                 if (rc)
3928                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3929                                __FILE__,__LINE__,rc);
3930                 put_tty_driver(serial_driver);
3931         }
3932 
3933         /* reset devices */
3934         info = synclinkmp_device_list;
3935         while(info) {
3936                 reset_port(info);
3937                 info = info->next_device;
3938         }
3939 
3940         /* release devices */
3941         info = synclinkmp_device_list;
3942         while(info) {
3943 #if SYNCLINK_GENERIC_HDLC
3944                 hdlcdev_exit(info);
3945 #endif
3946                 free_dma_bufs(info);
3947                 free_tmp_rx_buf(info);
3948                 if ( info->port_num == 0 ) {
3949                         if (info->sca_base)
3950                                 write_reg(info, LPR, 1); /* set low power mode */
3951                         release_resources(info);
3952                 }
3953                 tmp = info;
3954                 info = info->next_device;
3955                 tty_port_destroy(&tmp->port);
3956                 kfree(tmp);
3957         }
3958 
3959         pci_unregister_driver(&synclinkmp_pci_driver);
3960 }
3961 
3962 /* Driver initialization entry point.
3963  */
3964 
3965 static int __init synclinkmp_init(void)
3966 {
3967         int rc;
3968 
3969         if (break_on_load) {
3970                 synclinkmp_get_text_ptr();
3971                 BREAKPOINT();
3972         }
3973 
3974         printk("%s %s\n", driver_name, driver_version);
3975 
3976         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3977                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3978                 return rc;
3979         }
3980 
3981         serial_driver = alloc_tty_driver(128);
3982         if (!serial_driver) {
3983                 rc = -ENOMEM;
3984                 goto error;
3985         }
3986 
3987         /* Initialize the tty_driver structure */
3988 
3989         serial_driver->driver_name = "synclinkmp";
3990         serial_driver->name = "ttySLM";
3991         serial_driver->major = ttymajor;
3992         serial_driver->minor_start = 64;
3993         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3994         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3995         serial_driver->init_termios = tty_std_termios;
3996         serial_driver->init_termios.c_cflag =
3997                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3998         serial_driver->init_termios.c_ispeed = 9600;
3999         serial_driver->init_termios.c_ospeed = 9600;
4000         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4001         tty_set_operations(serial_driver, &ops);
4002         if ((rc = tty_register_driver(serial_driver)) < 0) {
4003                 printk("%s(%d):Couldn't register serial driver\n",
4004                         __FILE__,__LINE__);
4005                 put_tty_driver(serial_driver);
4006                 serial_driver = NULL;
4007                 goto error;
4008         }
4009 
4010         printk("%s %s, tty major#%d\n",
4011                 driver_name, driver_version,
4012                 serial_driver->major);
4013 
4014         return 0;
4015 
4016 error:
4017         synclinkmp_cleanup();
4018         return rc;
4019 }
4020 
4021 static void __exit synclinkmp_exit(void)
4022 {
4023         synclinkmp_cleanup();
4024 }
4025 
4026 module_init(synclinkmp_init);
4027 module_exit(synclinkmp_exit);
4028 
4029 /* Set the port for internal loopback mode.
4030  * The TxCLK and RxCLK signals are generated from the BRG and
4031  * the TxD is looped back to the RxD internally.
4032  */
4033 static void enable_loopback(SLMP_INFO *info, int enable)
4034 {
4035         if (enable) {
4036                 /* MD2 (Mode Register 2)
4037                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4038                  */
4039                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4040 
4041                 /* degate external TxC clock source */
4042                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4043                 write_control_reg(info);
4044 
4045                 /* RXS/TXS (Rx/Tx clock source)
4046                  * 07      Reserved, must be 0
4047                  * 06..04  Clock Source, 100=BRG
4048                  * 03..00  Clock Divisor, 0000=1
4049                  */
4050                 write_reg(info, RXS, 0x40);
4051                 write_reg(info, TXS, 0x40);
4052 
4053         } else {
4054                 /* MD2 (Mode Register 2)
4055                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4056                  */
4057                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4058 
4059                 /* RXS/TXS (Rx/Tx clock source)
4060                  * 07      Reserved, must be 0
4061                  * 06..04  Clock Source, 000=RxC/TxC Pin
4062                  * 03..00  Clock Divisor, 0000=1
4063                  */
4064                 write_reg(info, RXS, 0x00);
4065                 write_reg(info, TXS, 0x00);
4066         }
4067 
4068         /* set LinkSpeed if available, otherwise default to 2Mbps */
4069         if (info->params.clock_speed)
4070                 set_rate(info, info->params.clock_speed);
4071         else
4072                 set_rate(info, 3686400);
4073 }
4074 
4075 /* Set the baud rate register to the desired speed
4076  *
4077  *      data_rate       data rate of clock in bits per second
4078  *                      A data rate of 0 disables the AUX clock.
4079  */
4080 static void set_rate( SLMP_INFO *info, u32 data_rate )
4081 {
4082         u32 TMCValue;
4083         unsigned char BRValue;
4084         u32 Divisor=0;
4085 
4086         /* fBRG = fCLK/(TMC * 2^BR)
4087          */
4088         if (data_rate != 0) {
4089                 Divisor = 14745600/data_rate;
4090                 if (!Divisor)
4091                         Divisor = 1;
4092 
4093                 TMCValue = Divisor;
4094 
4095                 BRValue = 0;
4096                 if (TMCValue != 1 && TMCValue != 2) {
4097                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4098                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4099                          * 50/50 duty cycle.
4100                          */
4101                         BRValue = 1;
4102                         TMCValue >>= 1;
4103                 }
4104 
4105                 /* while TMCValue is too big for TMC register, divide
4106                  * by 2 and increment BR exponent.
4107                  */
4108                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4109                         TMCValue >>= 1;
4110 
4111                 write_reg(info, TXS,
4112                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4113                 write_reg(info, RXS,
4114                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4115                 write_reg(info, TMC, (unsigned char)TMCValue);
4116         }
4117         else {
4118                 write_reg(info, TXS,0);
4119                 write_reg(info, RXS,0);
4120                 write_reg(info, TMC, 0);
4121         }
4122 }
4123 
4124 /* Disable receiver
4125  */
4126 static void rx_stop(SLMP_INFO *info)
4127 {
4128         if (debug_level >= DEBUG_LEVEL_ISR)
4129                 printk("%s(%d):%s rx_stop()\n",
4130                          __FILE__,__LINE__, info->device_name );
4131 
4132         write_reg(info, CMD, RXRESET);
4133 
4134         info->ie0_value &= ~RXRDYE;
4135         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4136 
4137         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4138         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4139         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4140 
4141         info->rx_enabled = false;
4142         info->rx_overflow = false;
4143 }
4144 
4145 /* enable the receiver
4146  */
4147 static void rx_start(SLMP_INFO *info)
4148 {
4149         int i;
4150 
4151         if (debug_level >= DEBUG_LEVEL_ISR)
4152                 printk("%s(%d):%s rx_start()\n",
4153                          __FILE__,__LINE__, info->device_name );
4154 
4155         write_reg(info, CMD, RXRESET);
4156 
4157         if ( info->params.mode == MGSL_MODE_HDLC ) {
4158                 /* HDLC, disabe IRQ on rxdata */
4159                 info->ie0_value &= ~RXRDYE;
4160                 write_reg(info, IE0, info->ie0_value);
4161 
4162                 /* Reset all Rx DMA buffers and program rx dma */
4163                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4164                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4165 
4166                 for (i = 0; i < info->rx_buf_count; i++) {
4167                         info->rx_buf_list[i].status = 0xff;
4168 
4169                         // throttle to 4 shared memory writes at a time to prevent
4170                         // hogging local bus (keep latency time for DMA requests low).
4171                         if (!(i % 4))
4172                                 read_status_reg(info);
4173                 }
4174                 info->current_rx_buf = 0;
4175 
4176                 /* set current/1st descriptor address */
4177                 write_reg16(info, RXDMA + CDA,
4178                         info->rx_buf_list_ex[0].phys_entry);
4179 
4180                 /* set new last rx descriptor address */
4181                 write_reg16(info, RXDMA + EDA,
4182                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4183 
4184                 /* set buffer length (shared by all rx dma data buffers) */
4185                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4186 
4187                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4188                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4189         } else {
4190                 /* async, enable IRQ on rxdata */
4191                 info->ie0_value |= RXRDYE;
4192                 write_reg(info, IE0, info->ie0_value);
4193         }
4194 
4195         write_reg(info, CMD, RXENABLE);
4196 
4197         info->rx_overflow = false;
4198         info->rx_enabled = true;
4199 }
4200 
4201 /* Enable the transmitter and send a transmit frame if
4202  * one is loaded in the DMA buffers.
4203  */
4204 static void tx_start(SLMP_INFO *info)
4205 {
4206         if (debug_level >= DEBUG_LEVEL_ISR)
4207                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4208                          __FILE__,__LINE__, info->device_name,info->tx_count );
4209 
4210         if (!info->tx_enabled ) {
4211                 write_reg(info, CMD, TXRESET);
4212                 write_reg(info, CMD, TXENABLE);
4213                 info->tx_enabled = true;
4214         }
4215 
4216         if ( info->tx_count ) {
4217 
4218                 /* If auto RTS enabled and RTS is inactive, then assert */
4219                 /* RTS and set a flag indicating that the driver should */
4220                 /* negate RTS when the transmission completes. */
4221 
4222                 info->drop_rts_on_tx_done = false;
4223 
4224                 if (info->params.mode != MGSL_MODE_ASYNC) {
4225 
4226                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4227                                 get_signals( info );
4228                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4229                                         info->serial_signals |= SerialSignal_RTS;
4230                                         set_signals( info );
4231                                         info->drop_rts_on_tx_done = true;
4232                                 }
4233                         }
4234 
4235                         write_reg16(info, TRC0,
4236                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4237 
4238                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4239                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4240         
4241                         /* set TX CDA (current descriptor address) */
4242                         write_reg16(info, TXDMA + CDA,
4243                                 info->tx_buf_list_ex[0].phys_entry);
4244         
4245                         /* set TX EDA (last descriptor address) */
4246                         write_reg16(info, TXDMA + EDA,
4247                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4248         
4249                         /* enable underrun IRQ */
4250                         info->ie1_value &= ~IDLE;
4251                         info->ie1_value |= UDRN;
4252                         write_reg(info, IE1, info->ie1_value);
4253                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4254         
4255                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4256                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4257         
4258                         mod_timer(&info->tx_timer, jiffies +
4259                                         msecs_to_jiffies(5000));
4260                 }
4261                 else {
4262                         tx_load_fifo(info);
4263                         /* async, enable IRQ on txdata */
4264                         info->ie0_value |= TXRDYE;
4265                         write_reg(info, IE0, info->ie0_value);
4266                 }
4267 
4268                 info->tx_active = true;
4269         }
4270 }
4271 
4272 /* stop the transmitter and DMA
4273  */
4274 static void tx_stop( SLMP_INFO *info )
4275 {
4276         if (debug_level >= DEBUG_LEVEL_ISR)
4277                 printk("%s(%d):%s tx_stop()\n",
4278                          __FILE__,__LINE__, info->device_name );
4279 
4280         del_timer(&info->tx_timer);
4281 
4282         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4283         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4284 
4285         write_reg(info, CMD, TXRESET);
4286 
4287         info->ie1_value &= ~(UDRN + IDLE);
4288         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4289         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4290 
4291         info->ie0_value &= ~TXRDYE;
4292         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4293 
4294         info->tx_enabled = false;
4295         info->tx_active = false;
4296 }
4297 
4298 /* Fill the transmit FIFO until the FIFO is full or
4299  * there is no more data to load.
4300  */
4301 static void tx_load_fifo(SLMP_INFO *info)
4302 {
4303         u8 TwoBytes[2];
4304 
4305         /* do nothing is now tx data available and no XON/XOFF pending */
4306 
4307         if ( !info->tx_count && !info->x_char )
4308                 return;
4309 
4310         /* load the Transmit FIFO until FIFOs full or all data sent */
4311 
4312         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4313 
4314                 /* there is more space in the transmit FIFO and */
4315                 /* there is more data in transmit buffer */
4316 
4317                 if ( (info->tx_count > 1) && !info->x_char ) {
4318                         /* write 16-bits */
4319                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4320                         if (info->tx_get >= info->max_frame_size)
4321                                 info->tx_get -= info->max_frame_size;
4322                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4323                         if (info->tx_get >= info->max_frame_size)
4324                                 info->tx_get -= info->max_frame_size;
4325 
4326                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4327 
4328                         info->tx_count -= 2;
4329                         info->icount.tx += 2;
4330                 } else {
4331                         /* only 1 byte left to transmit or 1 FIFO slot left */
4332 
4333                         if (info->x_char) {
4334                                 /* transmit pending high priority char */
4335                                 write_reg(info, TRB, info->x_char);
4336                                 info->x_char = 0;
4337                         } else {
4338                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4339                                 if (info->tx_get >= info->max_frame_size)
4340                                         info->tx_get -= info->max_frame_size;
4341                                 info->tx_count--;
4342                         }
4343                         info->icount.tx++;
4344                 }
4345         }
4346 }
4347 
4348 /* Reset a port to a known state
4349  */
4350 static void reset_port(SLMP_INFO *info)
4351 {
4352         if (info->sca_base) {
4353 
4354                 tx_stop(info);
4355                 rx_stop(info);
4356 
4357                 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4358                 set_signals(info);
4359 
4360                 /* disable all port interrupts */
4361                 info->ie0_value = 0;
4362                 info->ie1_value = 0;
4363                 info->ie2_value = 0;
4364                 write_reg(info, IE0, info->ie0_value);
4365                 write_reg(info, IE1, info->ie1_value);
4366                 write_reg(info, IE2, info->ie2_value);
4367 
4368                 write_reg(info, CMD, CHRESET);
4369         }
4370 }
4371 
4372 /* Reset all the ports to a known state.
4373  */
4374 static void reset_adapter(SLMP_INFO *info)
4375 {
4376         int i;
4377 
4378         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4379                 if (info->port_array[i])
4380                         reset_port(info->port_array[i]);
4381         }
4382 }
4383 
4384 /* Program port for asynchronous communications.
4385  */
4386 static void async_mode(SLMP_INFO *info)
4387 {
4388 
4389         unsigned char RegValue;
4390 
4391         tx_stop(info);
4392         rx_stop(info);
4393 
4394         /* MD0, Mode Register 0
4395          *
4396          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4397          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4398          * 03      Reserved, must be 0
4399          * 02      CRCCC, CRC Calculation, 0=disabled
4400          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4401          *
4402          * 0000 0000
4403          */
4404         RegValue = 0x00;
4405         if (info->params.stop_bits != 1)
4406                 RegValue |= BIT1;
4407         write_reg(info, MD0, RegValue);
4408 
4409         /* MD1, Mode Register 1
4410          *
4411          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4412          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4413          * 03..02  RXCHR<1..0>, rx char size
4414          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4415          *
4416          * 0100 0000
4417          */
4418         RegValue = 0x40;
4419         switch (info->params.data_bits) {
4420         case 7: RegValue |= BIT4 + BIT2; break;
4421         case 6: RegValue |= BIT5 + BIT3; break;
4422         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4423         }
4424         if (info->params.parity != ASYNC_PARITY_NONE) {
4425                 RegValue |= BIT1;
4426                 if (info->params.parity == ASYNC_PARITY_ODD)
4427                         RegValue |= BIT0;
4428         }
4429         write_reg(info, MD1, RegValue);
4430 
4431         /* MD2, Mode Register 2
4432          *
4433          * 07..02  Reserved, must be 0
4434          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4435          *
4436          * 0000 0000
4437          */
4438         RegValue = 0x00;
4439         if (info->params.loopback)
4440                 RegValue |= (BIT1 + BIT0);
4441         write_reg(info, MD2, RegValue);
4442 
4443         /* RXS, Receive clock source
4444          *
4445          * 07      Reserved, must be 0
4446          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4447          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4448          */
4449         RegValue=BIT6;
4450         write_reg(info, RXS, RegValue);
4451 
4452         /* TXS, Transmit clock source
4453          *
4454          * 07      Reserved, must be 0
4455          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4456          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4457          */
4458         RegValue=BIT6;
4459         write_reg(info, TXS, RegValue);
4460 
4461         /* Control Register
4462          *
4463          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4464          */
4465         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4466         write_control_reg(info);
4467 
4468         tx_set_idle(info);
4469 
4470         /* RRC Receive Ready Control 0
4471          *
4472          * 07..05  Reserved, must be 0
4473          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4474          */
4475         write_reg(info, RRC, 0x00);
4476 
4477         /* TRC0 Transmit Ready Control 0
4478          *
4479          * 07..05  Reserved, must be 0
4480          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4481          */
4482         write_reg(info, TRC0, 0x10);
4483 
4484         /* TRC1 Transmit Ready Control 1
4485          *
4486          * 07..05  Reserved, must be 0
4487          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4488          */
4489         write_reg(info, TRC1, 0x1e);
4490 
4491         /* CTL, MSCI control register
4492          *
4493          * 07..06  Reserved, set to 0
4494          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4495          * 04      IDLC, idle control, 0=mark 1=idle register
4496          * 03      BRK, break, 0=off 1 =on (async)
4497          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4498          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4499          * 00      RTS, RTS output control, 0=active 1=inactive
4500          *
4501          * 0001 0001
4502          */
4503         RegValue = 0x10;
4504         if (!(info->serial_signals & SerialSignal_RTS))
4505                 RegValue |= 0x01;
4506         write_reg(info, CTL, RegValue);
4507 
4508         /* enable status interrupts */
4509         info->ie0_value |= TXINTE + RXINTE;
4510         write_reg(info, IE0, info->ie0_value);
4511 
4512         /* enable break detect interrupt */
4513         info->ie1_value = BRKD;
4514         write_reg(info, IE1, info->ie1_value);
4515 
4516         /* enable rx overrun interrupt */
4517         info->ie2_value = OVRN;
4518         write_reg(info, IE2, info->ie2_value);
4519 
4520         set_rate( info, info->params.data_rate * 16 );
4521 }
4522 
4523 /* Program the SCA for HDLC communications.
4524  */
4525 static void hdlc_mode(SLMP_INFO *info)
4526 {
4527         unsigned char RegValue;
4528         u32 DpllDivisor;
4529 
4530         // Can't use DPLL because SCA outputs recovered clock on RxC when
4531         // DPLL mode selected. This causes output contention with RxC receiver.
4532         // Use of DPLL would require external hardware to disable RxC receiver
4533         // when DPLL mode selected.
4534         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4535 
4536         /* disable DMA interrupts */
4537         write_reg(info, TXDMA + DIR, 0);
4538         write_reg(info, RXDMA + DIR, 0);
4539 
4540         /* MD0, Mode Register 0
4541          *
4542          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4543          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4544          * 03      Reserved, must be 0
4545          * 02      CRCCC, CRC Calculation, 1=enabled
4546          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4547          * 00      CRC0, CRC initial value, 1 = all 1s
4548          *
4549          * 1000 0001
4550          */
4551         RegValue = 0x81;
4552         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4553                 RegValue |= BIT4;
4554         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4555                 RegValue |= BIT4;
4556         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4557                 RegValue |= BIT2 + BIT1;
4558         write_reg(info, MD0, RegValue);
4559 
4560         /* MD1, Mode Register 1
4561          *
4562          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4563          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4564          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4565          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4566          *
4567          * 0000 0000
4568          */
4569         RegValue = 0x00;
4570         write_reg(info, MD1, RegValue);
4571 
4572         /* MD2, Mode Register 2
4573          *
4574          * 07      NRZFM, 0=NRZ, 1=FM
4575          * 06..05  CODE<1..0> Encoding, 00=NRZ
4576          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4577          * 02      Reserved, must be 0
4578          * 01..00  CNCT<1..0> Channel connection, 0=normal
4579          *
4580          * 0000 0000
4581          */
4582         RegValue = 0x00;
4583         switch(info->params.encoding) {
4584         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4585         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4586         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4587         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4588 #if 0
4589         case HDLC_ENCODING_NRZB:                                        /* not supported */
4590         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4591         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4592 #endif
4593         }
4594         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4595                 DpllDivisor = 16;
4596                 RegValue |= BIT3;
4597         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4598                 DpllDivisor = 8;
4599         } else {
4600                 DpllDivisor = 32;
4601                 RegValue |= BIT4;
4602         }
4603         write_reg(info, MD2, RegValue);
4604 
4605 
4606         /* RXS, Receive clock source
4607          *
4608          * 07      Reserved, must be 0
4609          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4610          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4611          */
4612         RegValue=0;
4613         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4614                 RegValue |= BIT6;
4615         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4616                 RegValue |= BIT6 + BIT5;
4617         write_reg(info, RXS, RegValue);
4618 
4619         /* TXS, Transmit clock source
4620          *
4621          * 07      Reserved, must be 0
4622          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4623          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4624          */
4625         RegValue=0;
4626         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4627                 RegValue |= BIT6;
4628         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4629                 RegValue |= BIT6 + BIT5;
4630         write_reg(info, TXS, RegValue);
4631 
4632         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4633                 set_rate(info, info->params.clock_speed * DpllDivisor);
4634         else
4635                 set_rate(info, info->params.clock_speed);
4636 
4637         /* GPDATA (General Purpose I/O Data Register)
4638          *
4639          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4640          */
4641         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4642                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4643         else
4644                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4645         write_control_reg(info);
4646 
4647         /* RRC Receive Ready Control 0
4648          *
4649          * 07..05  Reserved, must be 0
4650          * 04..00  RRC<4..0> Rx FIFO trigger active
4651          */
4652         write_reg(info, RRC, rx_active_fifo_level);
4653 
4654         /* TRC0 Transmit Ready Control 0
4655          *
4656          * 07..05  Reserved, must be 0
4657          * 04..00  TRC<4..0> Tx FIFO trigger active
4658          */
4659         write_reg(info, TRC0, tx_active_fifo_level);
4660 
4661         /* TRC1 Transmit Ready Control 1
4662          *
4663          * 07..05  Reserved, must be 0
4664          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4665          */
4666         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4667 
4668         /* DMR, DMA Mode Register
4669          *
4670          * 07..05  Reserved, must be 0
4671          * 04      TMOD, Transfer Mode: 1=chained-block
4672          * 03      Reserved, must be 0
4673          * 02      NF, Number of Frames: 1=multi-frame
4674          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4675          * 00      Reserved, must be 0
4676          *
4677          * 0001 0100
4678          */
4679         write_reg(info, TXDMA + DMR, 0x14);
4680         write_reg(info, RXDMA + DMR, 0x14);
4681 
4682         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4683         write_reg(info, RXDMA + CPB,
4684                 (unsigned char)(info->buffer_list_phys >> 16));
4685 
4686         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4687         write_reg(info, TXDMA + CPB,
4688                 (unsigned char)(info->buffer_list_phys >> 16));
4689 
4690         /* enable status interrupts. other code enables/disables
4691          * the individual sources for these two interrupt classes.
4692          */
4693         info->ie0_value |= TXINTE + RXINTE;
4694         write_reg(info, IE0, info->ie0_value);
4695 
4696         /* CTL, MSCI control register
4697          *
4698          * 07..06  Reserved, set to 0
4699          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4700          * 04      IDLC, idle control, 0=mark 1=idle register
4701          * 03      BRK, break, 0=off 1 =on (async)
4702          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4703          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4704          * 00      RTS, RTS output control, 0=active 1=inactive
4705          *
4706          * 0001 0001
4707          */
4708         RegValue = 0x10;
4709         if (!(info->serial_signals & SerialSignal_RTS))
4710                 RegValue |= 0x01;
4711         write_reg(info, CTL, RegValue);
4712 
4713         /* preamble not supported ! */
4714 
4715         tx_set_idle(info);
4716         tx_stop(info);
4717         rx_stop(info);
4718 
4719         set_rate(info, info->params.clock_speed);
4720 
4721         if (info->params.loopback)
4722                 enable_loopback(info,1);
4723 }
4724 
4725 /* Set the transmit HDLC idle mode
4726  */
4727 static void tx_set_idle(SLMP_INFO *info)
4728 {
4729         unsigned char RegValue = 0xff;
4730 
4731         /* Map API idle mode to SCA register bits */
4732         switch(info->idle_mode) {
4733         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4734         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4735         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4736         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4737         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4738         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4739         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4740         }
4741 
4742         write_reg(info, IDL, RegValue);
4743 }
4744 
4745 /* Query the adapter for the state of the V24 status (input) signals.
4746  */
4747 static void get_signals(SLMP_INFO *info)
4748 {
4749         u16 status = read_reg(info, SR3);
4750         u16 gpstatus = read_status_reg(info);
4751         u16 testbit;
4752 
4753         /* clear all serial signals except RTS and DTR */
4754         info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
4755 
4756         /* set serial signal bits to reflect MISR */
4757 
4758         if (!(status & BIT3))
4759                 info->serial_signals |= SerialSignal_CTS;
4760 
4761         if ( !(status & BIT2))
4762                 info->serial_signals |= SerialSignal_DCD;
4763 
4764         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4765         if (!(gpstatus & testbit))
4766                 info->serial_signals |= SerialSignal_RI;
4767 
4768         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4769         if (!(gpstatus & testbit))
4770                 info->serial_signals |= SerialSignal_DSR;
4771 }
4772 
4773 /* Set the state of RTS and DTR based on contents of
4774  * serial_signals member of device context.
4775  */
4776 static void set_signals(SLMP_INFO *info)
4777 {
4778         unsigned char RegValue;
4779         u16 EnableBit;
4780 
4781         RegValue = read_reg(info, CTL);
4782         if (info->serial_signals & SerialSignal_RTS)
4783                 RegValue &= ~BIT0;
4784         else
4785                 RegValue |= BIT0;
4786         write_reg(info, CTL, RegValue);
4787 
4788         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4789         EnableBit = BIT1 << (info->port_num*2);
4790         if (info->serial_signals & SerialSignal_DTR)
4791                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4792         else
4793                 info->port_array[0]->ctrlreg_value |= EnableBit;
4794         write_control_reg(info);
4795 }
4796 
4797 /*******************/
4798 /* DMA Buffer Code */
4799 /*******************/
4800 
4801 /* Set the count for all receive buffers to SCABUFSIZE
4802  * and set the current buffer to the first buffer. This effectively
4803  * makes all buffers free and discards any data in buffers.
4804  */
4805 static void rx_reset_buffers(SLMP_INFO *info)
4806 {
4807         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4808 }
4809 
4810 /* Free the buffers used by a received frame
4811  *
4812  * info   pointer to device instance data
4813  * first  index of 1st receive buffer of frame
4814  * last   index of last receive buffer of frame
4815  */
4816 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4817 {
4818         bool done = false;
4819 
4820         while(!done) {
4821                 /* reset current buffer for reuse */
4822                 info->rx_buf_list[first].status = 0xff;
4823 
4824                 if (first == last) {
4825                         done = true;
4826                         /* set new last rx descriptor address */
4827                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4828                 }
4829 
4830                 first++;
4831                 if (first == info->rx_buf_count)
4832                         first = 0;
4833         }
4834 
4835         /* set current buffer to next buffer after last buffer of frame */
4836         info->current_rx_buf = first;
4837 }
4838 
4839 /* Return a received frame from the receive DMA buffers.
4840  * Only frames received without errors are returned.
4841  *
4842  * Return Value:        true if frame returned, otherwise false
4843  */
4844 static bool rx_get_frame(SLMP_INFO *info)
4845 {
4846         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4847         unsigned short status;
4848         unsigned int framesize = 0;
4849         bool ReturnCode = false;
4850         unsigned long flags;
4851         struct tty_struct *tty = info->port.tty;
4852         unsigned char addr_field = 0xff;
4853         SCADESC *desc;
4854         SCADESC_EX *desc_ex;
4855 
4856 CheckAgain:
4857         /* assume no frame returned, set zero length */
4858         framesize = 0;
4859         addr_field = 0xff;
4860 
4861         /*
4862          * current_rx_buf points to the 1st buffer of the next available
4863          * receive frame. To find the last buffer of the frame look for
4864          * a non-zero status field in the buffer entries. (The status
4865          * field is set by the 16C32 after completing a receive frame.
4866          */
4867         StartIndex = EndIndex = info->current_rx_buf;
4868 
4869         for ( ;; ) {
4870                 desc = &info->rx_buf_list[EndIndex];
4871                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4872 
4873                 if (desc->status == 0xff)
4874                         goto Cleanup;   /* current desc still in use, no frames available */
4875 
4876                 if (framesize == 0 && info->params.addr_filter != 0xff)
4877                         addr_field = desc_ex->virt_addr[0];
4878 
4879                 framesize += desc->length;
4880 
4881                 /* Status != 0 means last buffer of frame */
4882                 if (desc->status)
4883                         break;
4884 
4885                 EndIndex++;
4886                 if (EndIndex == info->rx_buf_count)
4887                         EndIndex = 0;
4888 
4889                 if (EndIndex == info->current_rx_buf) {
4890                         /* all buffers have been 'used' but none mark      */
4891                         /* the end of a frame. Reset buffers and receiver. */
4892                         if ( info->rx_enabled ){
4893                                 spin_lock_irqsave(&info->lock,flags);
4894                                 rx_start(info);
4895                                 spin_unlock_irqrestore(&info->lock,flags);
4896                         }
4897                         goto Cleanup;
4898                 }
4899 
4900         }
4901 
4902         /* check status of receive frame */
4903 
4904         /* frame status is byte stored after frame data
4905          *
4906          * 7 EOM (end of msg), 1 = last buffer of frame
4907          * 6 Short Frame, 1 = short frame
4908          * 5 Abort, 1 = frame aborted
4909          * 4 Residue, 1 = last byte is partial
4910          * 3 Overrun, 1 = overrun occurred during frame reception
4911          * 2 CRC,     1 = CRC error detected
4912          *
4913          */
4914         status = desc->status;
4915 
4916         /* ignore CRC bit if not using CRC (bit is undefined) */
4917         /* Note:CRC is not save to data buffer */
4918         if (info->params.crc_type == HDLC_CRC_NONE)
4919                 status &= ~BIT2;
4920 
4921         if (framesize == 0 ||
4922                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4923                 /* discard 0 byte frames, this seems to occur sometime
4924                  * when remote is idling flags.
4925                  */
4926                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4927                 goto CheckAgain;
4928         }
4929 
4930         if (framesize < 2)
4931                 status |= BIT6;
4932 
4933         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4934                 /* received frame has errors,
4935                  * update counts and mark frame size as 0
4936                  */
4937                 if (status & BIT6)
4938                         info->icount.rxshort++;
4939                 else if (status & BIT5)
4940                         info->icount.rxabort++;
4941                 else if (status & BIT3)
4942                         info->icount.rxover++;
4943                 else
4944                         info->icount.rxcrc++;
4945 
4946                 framesize = 0;
4947 #if SYNCLINK_GENERIC_HDLC
4948                 {
4949                         info->netdev->stats.rx_errors++;
4950                         info->netdev->stats.rx_frame_errors++;
4951                 }
4952 #endif
4953         }
4954 
4955         if ( debug_level >= DEBUG_LEVEL_BH )
4956                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4957                         __FILE__,__LINE__,info->device_name,status,framesize);
4958 
4959         if ( debug_level >= DEBUG_LEVEL_DATA )
4960                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4961                         min_t(unsigned int, framesize, SCABUFSIZE), 0);
4962 
4963         if (framesize) {
4964                 if (framesize > info->max_frame_size)
4965                         info->icount.rxlong++;
4966                 else {
4967                         /* copy dma buffer(s) to contiguous intermediate buffer */
4968                         int copy_count = framesize;
4969                         int index = StartIndex;
4970                         unsigned char *ptmp = info->tmp_rx_buf;
4971                         info->tmp_rx_buf_count = framesize;
4972 
4973                         info->icount.rxok++;
4974 
4975                         while(copy_count) {
4976                                 int partial_count = min(copy_count,SCABUFSIZE);
4977                                 memcpy( ptmp,
4978                                         info->rx_buf_list_ex[index].virt_addr,
4979                                         partial_count );
4980                                 ptmp += partial_count;
4981                                 copy_count -= partial_count;
4982 
4983                                 if ( ++index == info->rx_buf_count )
4984                                         index = 0;
4985                         }
4986 
4987 #if SYNCLINK_GENERIC_HDLC
4988                         if (info->netcount)
4989                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4990                         else
4991 #endif
4992                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
4993                                                   info->flag_buf, framesize);
4994                 }
4995         }
4996         /* Free the buffers used by this frame. */
4997         rx_free_frame_buffers( info, StartIndex, EndIndex );
4998 
4999         ReturnCode = true;
5000 
5001 Cleanup:
5002         if ( info->rx_enabled && info->rx_overflow ) {
5003                 /* Receiver is enabled, but needs to restarted due to
5004                  * rx buffer overflow. If buffers are empty, restart receiver.
5005                  */
5006                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5007                         spin_lock_irqsave(&info->lock,flags);
5008                         rx_start(info);
5009                         spin_unlock_irqrestore(&info->lock,flags);
5010                 }
5011         }
5012 
5013         return ReturnCode;
5014 }
5015 
5016 /* load the transmit DMA buffer with data
5017  */
5018 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5019 {
5020         unsigned short copy_count;
5021         unsigned int i = 0;
5022         SCADESC *desc;
5023         SCADESC_EX *desc_ex;
5024 
5025         if ( debug_level >= DEBUG_LEVEL_DATA )
5026                 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5027 
5028         /* Copy source buffer to one or more DMA buffers, starting with
5029          * the first transmit dma buffer.
5030          */
5031         for(i=0;;)
5032         {
5033                 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5034 
5035                 desc = &info->tx_buf_list[i];
5036                 desc_ex = &info->tx_buf_list_ex[i];
5037 
5038                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5039 
5040                 desc->length = copy_count;
5041                 desc->status = 0;
5042 
5043                 buf += copy_count;
5044                 count -= copy_count;
5045 
5046                 if (!count)
5047                         break;
5048 
5049                 i++;
5050                 if (i >= info->tx_buf_count)
5051                         i = 0;
5052         }
5053 
5054         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5055         info->last_tx_buf = ++i;
5056 }
5057 
5058 static bool register_test(SLMP_INFO *info)
5059 {
5060         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5061         static unsigned int count = ARRAY_SIZE(testval);
5062         unsigned int i;
5063         bool rc = true;
5064         unsigned long flags;
5065 
5066         spin_lock_irqsave(&info->lock,flags);
5067         reset_port(info);
5068 
5069         /* assume failure */
5070         info->init_error = DiagStatus_AddressFailure;
5071 
5072         /* Write bit patterns to various registers but do it out of */
5073         /* sync, then read back and verify values. */
5074 
5075         for (i = 0 ; i < count ; i++) {
5076                 write_reg(info, TMC, testval[i]);
5077                 write_reg(info, IDL, testval[(i+1)%count]);
5078                 write_reg(info, SA0, testval[(i+2)%count]);
5079                 write_reg(info, SA1, testval[(i+3)%count]);
5080 
5081                 if ( (read_reg(info, TMC) != testval[i]) ||
5082                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5083                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5084                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5085                 {
5086                         rc = false;
5087                         break;
5088                 }
5089         }
5090 
5091         reset_port(info);
5092         spin_unlock_irqrestore(&info->lock,flags);
5093 
5094         return rc;
5095 }
5096 
5097 static bool irq_test(SLMP_INFO *info)
5098 {
5099         unsigned long timeout;
5100         unsigned long flags;
5101 
5102         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5103 
5104         spin_lock_irqsave(&info->lock,flags);
5105         reset_port(info);
5106 
5107         /* assume failure */
5108         info->init_error = DiagStatus_IrqFailure;
5109         info->irq_occurred = false;
5110 
5111         /* setup timer0 on SCA0 to interrupt */
5112 
5113         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5114         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5115 
5116         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5117         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5118 
5119 
5120         /* TMCS, Timer Control/Status Register
5121          *
5122          * 07      CMF, Compare match flag (read only) 1=match
5123          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5124          * 05      Reserved, must be 0
5125          * 04      TME, Timer Enable
5126          * 03..00  Reserved, must be 0
5127          *
5128          * 0101 0000
5129          */
5130         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5131 
5132         spin_unlock_irqrestore(&info->lock,flags);
5133 
5134         timeout=100;
5135         while( timeout-- && !info->irq_occurred ) {
5136                 msleep_interruptible(10);
5137         }
5138 
5139         spin_lock_irqsave(&info->lock,flags);
5140         reset_port(info);
5141         spin_unlock_irqrestore(&info->lock,flags);
5142 
5143         return info->irq_occurred;
5144 }
5145 
5146 /* initialize individual SCA device (2 ports)
5147  */
5148 static bool sca_init(SLMP_INFO *info)
5149 {
5150         /* set wait controller to single mem partition (low), no wait states */
5151         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5152         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5153         write_reg(info, WCRL, 0);       /* wait controller low range */
5154         write_reg(info, WCRM, 0);       /* wait controller mid range */
5155         write_reg(info, WCRH, 0);       /* wait controller high range */
5156 
5157         /* DPCR, DMA Priority Control
5158          *
5159          * 07..05  Not used, must be 0
5160          * 04      BRC, bus release condition: 0=all transfers complete
5161          * 03      CCC, channel change condition: 0=every cycle
5162          * 02..00  PR<2..0>, priority 100=round robin
5163          *
5164          * 00000100 = 0x04
5165          */
5166         write_reg(info, DPCR, dma_priority);
5167 
5168         /* DMA Master Enable, BIT7: 1=enable all channels */
5169         write_reg(info, DMER, 0x80);
5170 
5171         /* enable all interrupt classes */
5172         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5173         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5174         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5175 
5176         /* ITCR, interrupt control register
5177          * 07      IPC, interrupt priority, 0=MSCI->DMA
5178          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5179          * 04      VOS, Vector Output, 0=unmodified vector
5180          * 03..00  Reserved, must be 0
5181          */
5182         write_reg(info, ITCR, 0);
5183 
5184         return true;
5185 }
5186 
5187 /* initialize adapter hardware
5188  */
5189 static bool init_adapter(SLMP_INFO *info)
5190 {
5191         int i;
5192 
5193         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5194         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5195         u32 readval;
5196 
5197         info->misc_ctrl_value |= BIT30;
5198         *MiscCtrl = info->misc_ctrl_value;
5199 
5200         /*
5201          * Force at least 170ns delay before clearing
5202          * reset bit. Each read from LCR takes at least
5203          * 30ns so 10 times for 300ns to be safe.
5204          */
5205         for(i=0;i<10;i++)
5206                 readval = *MiscCtrl;
5207 
5208         info->misc_ctrl_value &= ~BIT30;
5209         *MiscCtrl = info->misc_ctrl_value;
5210 
5211         /* init control reg (all DTRs off, all clksel=input) */
5212         info->ctrlreg_value = 0xaa;
5213         write_control_reg(info);
5214 
5215         {
5216                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5217                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5218 
5219                 switch(read_ahead_count)
5220                 {
5221                 case 16:
5222                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5223                         break;
5224                 case 8:
5225                         lcr1_brdr_value |= BIT5 + BIT4;
5226                         break;
5227                 case 4:
5228                         lcr1_brdr_value |= BIT5 + BIT3;
5229                         break;
5230                 case 0:
5231                         lcr1_brdr_value |= BIT5;
5232                         break;
5233                 }
5234 
5235                 *LCR1BRDR = lcr1_brdr_value;
5236                 *MiscCtrl = misc_ctrl_value;
5237         }
5238 
5239         sca_init(info->port_array[0]);
5240         sca_init(info->port_array[2]);
5241 
5242         return true;
5243 }
5244 
5245 /* Loopback an HDLC frame to test the hardware
5246  * interrupt and DMA functions.
5247  */
5248 static bool loopback_test(SLMP_INFO *info)
5249 {
5250 #define TESTFRAMESIZE 20
5251 
5252         unsigned long timeout;
5253         u16 count = TESTFRAMESIZE;
5254         unsigned char buf[TESTFRAMESIZE];
5255         bool rc = false;
5256         unsigned long flags;
5257 
5258         struct tty_struct *oldtty = info->port.tty;
5259         u32 speed = info->params.clock_speed;
5260 
5261         info->params.clock_speed = 3686400;
5262         info->port.tty = NULL;
5263 
5264         /* assume failure */
5265         info->init_error = DiagStatus_DmaFailure;
5266 
5267         /* build and send transmit frame */
5268         for (count = 0; count < TESTFRAMESIZE;++count)
5269                 buf[count] = (unsigned char)count;
5270 
5271         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5272 
5273         /* program hardware for HDLC and enabled receiver */
5274         spin_lock_irqsave(&info->lock,flags);
5275         hdlc_mode(info);
5276         enable_loopback(info,1);
5277         rx_start(info);
5278         info->tx_count = count;
5279         tx_load_dma_buffer(info,buf,count);
5280         tx_start(info);
5281         spin_unlock_irqrestore(&info->lock,flags);
5282 
5283         /* wait for receive complete */
5284         /* Set a timeout for waiting for interrupt. */
5285         for ( timeout = 100; timeout; --timeout ) {
5286                 msleep_interruptible(10);
5287 
5288                 if (rx_get_frame(info)) {
5289                         rc = true;
5290                         break;
5291                 }
5292         }
5293 
5294         /* verify received frame length and contents */
5295         if (rc &&
5296             ( info->tmp_rx_buf_count != count ||
5297               memcmp(buf, info->tmp_rx_buf,count))) {
5298                 rc = false;
5299         }
5300 
5301         spin_lock_irqsave(&info->lock,flags);
5302         reset_adapter(info);
5303         spin_unlock_irqrestore(&info->lock,flags);
5304 
5305         info->params.clock_speed = speed;
5306         info->port.tty = oldtty;
5307 
5308         return rc;
5309 }
5310 
5311 /* Perform diagnostics on hardware
5312  */
5313 static int adapter_test( SLMP_INFO *info )
5314 {
5315         unsigned long flags;
5316         if ( debug_level >= DEBUG_LEVEL_INFO )
5317                 printk( "%s(%d):Testing device %s\n",
5318                         __FILE__,__LINE__,info->device_name );
5319 
5320         spin_lock_irqsave(&info->lock,flags);
5321         init_adapter(info);
5322         spin_unlock_irqrestore(&info->lock,flags);
5323 
5324         info->port_array[0]->port_count = 0;
5325 
5326         if ( register_test(info->port_array[0]) &&
5327                 register_test(info->port_array[1])) {
5328 
5329                 info->port_array[0]->port_count = 2;
5330 
5331                 if ( register_test(info->port_array[2]) &&
5332                         register_test(info->port_array[3]) )
5333                         info->port_array[0]->port_count += 2;
5334         }
5335         else {
5336                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5337                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5338                 return -ENODEV;
5339         }
5340 
5341         if ( !irq_test(info->port_array[0]) ||
5342                 !irq_test(info->port_array[1]) ||
5343                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5344                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5345                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5346                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5347                 return -ENODEV;
5348         }
5349 
5350         if (!loopback_test(info->port_array[0]) ||
5351                 !loopback_test(info->port_array[1]) ||
5352                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5353                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5354                 printk( "%s(%d):DMA test failure for device %s\n",
5355                         __FILE__,__LINE__,info->device_name);
5356                 return -ENODEV;
5357         }
5358 
5359         if ( debug_level >= DEBUG_LEVEL_INFO )
5360                 printk( "%s(%d):device %s passed diagnostics\n",
5361                         __FILE__,__LINE__,info->device_name );
5362 
5363         info->port_array[0]->init_error = 0;
5364         info->port_array[1]->init_error = 0;
5365         if ( info->port_count > 2 ) {
5366                 info->port_array[2]->init_error = 0;
5367                 info->port_array[3]->init_error = 0;
5368         }
5369 
5370         return 0;
5371 }
5372 
5373 /* Test the shared memory on a PCI adapter.
5374  */
5375 static bool memory_test(SLMP_INFO *info)
5376 {
5377         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5378                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5379         unsigned long count = ARRAY_SIZE(testval);
5380         unsigned long i;
5381         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5382         unsigned long * addr = (unsigned long *)info->memory_base;
5383 
5384         /* Test data lines with test pattern at one location. */
5385 
5386         for ( i = 0 ; i < count ; i++ ) {
5387                 *addr = testval[i];
5388                 if ( *addr != testval[i] )
5389                         return false;
5390         }
5391 
5392         /* Test address lines with incrementing pattern over */
5393         /* entire address range. */
5394 
5395         for ( i = 0 ; i < limit ; i++ ) {
5396                 *addr = i * 4;
5397                 addr++;
5398         }
5399 
5400         addr = (unsigned long *)info->memory_base;
5401 
5402         for ( i = 0 ; i < limit ; i++ ) {
5403                 if ( *addr != i * 4 )
5404                         return false;
5405                 addr++;
5406         }
5407 
5408         memset( info->memory_base, 0, SCA_MEM_SIZE );
5409         return true;
5410 }
5411 
5412 /* Load data into PCI adapter shared memory.
5413  *
5414  * The PCI9050 releases control of the local bus
5415  * after completing the current read or write operation.
5416  *
5417  * While the PCI9050 write FIFO not empty, the
5418  * PCI9050 treats all of the writes as a single transaction
5419  * and does not release the bus. This causes DMA latency problems
5420  * at high speeds when copying large data blocks to the shared memory.
5421  *
5422  * This function breaks a write into multiple transations by
5423  * interleaving a read which flushes the write FIFO and 'completes'
5424  * the write transation. This allows any pending DMA request to gain control
5425  * of the local bus in a timely fasion.
5426  */
5427 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5428 {
5429         /* A load interval of 16 allows for 4 32-bit writes at */
5430         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5431 
5432         unsigned short interval = count / sca_pci_load_interval;
5433         unsigned short i;
5434 
5435         for ( i = 0 ; i < interval ; i++ )
5436         {
5437                 memcpy(dest, src, sca_pci_load_interval);
5438                 read_status_reg(info);
5439                 dest += sca_pci_load_interval;
5440                 src += sca_pci_load_interval;
5441         }
5442 
5443         memcpy(dest, src, count % sca_pci_load_interval);
5444 }
5445 
5446 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5447 {
5448         int i;
5449         int linecount;
5450         if (xmit)
5451                 printk("%s tx data:\n",info->device_name);
5452         else
5453                 printk("%s rx data:\n",info->device_name);
5454 
5455         while(count) {
5456                 if (count > 16)
5457                         linecount = 16;
5458                 else
5459                         linecount = count;
5460 
5461                 for(i=0;i<linecount;i++)
5462                         printk("%02X ",(unsigned char)data[i]);
5463                 for(;i<17;i++)
5464                         printk("   ");
5465                 for(i=0;i<linecount;i++) {
5466                         if (data[i]>=040 && data[i]<=0176)
5467                                 printk("%c",data[i]);
5468                         else
5469                                 printk(".");
5470                 }
5471                 printk("\n");
5472 
5473                 data  += linecount;
5474                 count -= linecount;
5475         }
5476 }       /* end of trace_block() */
5477 
5478 /* called when HDLC frame times out
5479  * update stats and do tx completion processing
5480  */
5481 static void tx_timeout(unsigned long context)
5482 {
5483         SLMP_INFO *info = (SLMP_INFO*)context;
5484         unsigned long flags;
5485 
5486         if ( debug_level >= DEBUG_LEVEL_INFO )
5487                 printk( "%s(%d):%s tx_timeout()\n",
5488                         __FILE__,__LINE__,info->device_name);
5489         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5490                 info->icount.txtimeout++;
5491         }
5492         spin_lock_irqsave(&info->lock,flags);
5493         info->tx_active = false;
5494         info->tx_count = info->tx_put = info->tx_get = 0;
5495 
5496         spin_unlock_irqrestore(&info->lock,flags);
5497 
5498 #if SYNCLINK_GENERIC_HDLC
5499         if (info->netcount)
5500                 hdlcdev_tx_done(info);
5501         else
5502 #endif
5503                 bh_transmit(info);
5504 }
5505 
5506 /* called to periodically check the DSR/RI modem signal input status
5507  */
5508 static void status_timeout(unsigned long context)
5509 {
5510         u16 status = 0;
5511         SLMP_INFO *info = (SLMP_INFO*)context;
5512         unsigned long flags;
5513         unsigned char delta;
5514 
5515 
5516         spin_lock_irqsave(&info->lock,flags);
5517         get_signals(info);
5518         spin_unlock_irqrestore(&info->lock,flags);
5519 
5520         /* check for DSR/RI state change */
5521 
5522         delta = info->old_signals ^ info->serial_signals;
5523         info->old_signals = info->serial_signals;
5524 
5525         if (delta & SerialSignal_DSR)
5526                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5527 
5528         if (delta & SerialSignal_RI)
5529                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5530 
5531         if (delta & SerialSignal_DCD)
5532                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5533 
5534         if (delta & SerialSignal_CTS)
5535                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5536 
5537         if (status)
5538                 isr_io_pin(info,status);
5539 
5540         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5541 }
5542 
5543 
5544 /* Register Access Routines -
5545  * All registers are memory mapped
5546  */
5547 #define CALC_REGADDR() \
5548         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5549         if (info->port_num > 1) \
5550                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5551         if ( info->port_num & 1) { \
5552                 if (Addr > 0x7f) \
5553                         RegAddr += 0x40;        /* DMA access */ \
5554                 else if (Addr > 0x1f && Addr < 0x60) \
5555                         RegAddr += 0x20;        /* MSCI access */ \
5556         }
5557 
5558 
5559 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5560 {
5561         CALC_REGADDR();
5562         return *RegAddr;
5563 }
5564 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5565 {
5566         CALC_REGADDR();
5567         *RegAddr = Value;
5568 }
5569 
5570 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5571 {
5572         CALC_REGADDR();
5573         return *((u16 *)RegAddr);
5574 }
5575 
5576 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5577 {
5578         CALC_REGADDR();
5579         *((u16 *)RegAddr) = Value;
5580 }
5581 
5582 static unsigned char read_status_reg(SLMP_INFO * info)
5583 {
5584         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5585         return *RegAddr;
5586 }
5587 
5588 static void write_control_reg(SLMP_INFO * info)
5589 {
5590         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5591         *RegAddr = info->port_array[0]->ctrlreg_value;
5592 }
5593 
5594 
5595 static int synclinkmp_init_one (struct pci_dev *dev,
5596                                           const struct pci_device_id *ent)
5597 {
5598         if (pci_enable_device(dev)) {
5599                 printk("error enabling pci device %p\n", dev);
5600                 return -EIO;
5601         }
5602         device_init( ++synclinkmp_adapter_count, dev );
5603         return 0;
5604 }
5605 
5606 static void synclinkmp_remove_one (struct pci_dev *dev)
5607 {
5608 }
5609 

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