Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/tty/synclink_gt.c

  1 /*
  2  * Device driver for Microgate SyncLink GT serial adapters.
  3  *
  4  * written by Paul Fulghum for Microgate Corporation
  5  * paulkf@microgate.com
  6  *
  7  * Microgate and SyncLink are trademarks of Microgate Corporation
  8  *
  9  * This code is released under the GNU General Public License (GPL)
 10  *
 11  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 13  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 14  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
 15  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 16  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 17  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 18  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 19  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
 21  * OF THE POSSIBILITY OF SUCH DAMAGE.
 22  */
 23 
 24 /*
 25  * DEBUG OUTPUT DEFINITIONS
 26  *
 27  * uncomment lines below to enable specific types of debug output
 28  *
 29  * DBGINFO   information - most verbose output
 30  * DBGERR    serious errors
 31  * DBGBH     bottom half service routine debugging
 32  * DBGISR    interrupt service routine debugging
 33  * DBGDATA   output receive and transmit data
 34  * DBGTBUF   output transmit DMA buffers and registers
 35  * DBGRBUF   output receive DMA buffers and registers
 36  */
 37 
 38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
 39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
 40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
 41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
 42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
 43 /*#define DBGTBUF(info) dump_tbufs(info)*/
 44 /*#define DBGRBUF(info) dump_rbufs(info)*/
 45 
 46 
 47 #include <linux/module.h>
 48 #include <linux/errno.h>
 49 #include <linux/signal.h>
 50 #include <linux/sched.h>
 51 #include <linux/timer.h>
 52 #include <linux/interrupt.h>
 53 #include <linux/pci.h>
 54 #include <linux/tty.h>
 55 #include <linux/tty_flip.h>
 56 #include <linux/serial.h>
 57 #include <linux/major.h>
 58 #include <linux/string.h>
 59 #include <linux/fcntl.h>
 60 #include <linux/ptrace.h>
 61 #include <linux/ioport.h>
 62 #include <linux/mm.h>
 63 #include <linux/seq_file.h>
 64 #include <linux/slab.h>
 65 #include <linux/netdevice.h>
 66 #include <linux/vmalloc.h>
 67 #include <linux/init.h>
 68 #include <linux/delay.h>
 69 #include <linux/ioctl.h>
 70 #include <linux/termios.h>
 71 #include <linux/bitops.h>
 72 #include <linux/workqueue.h>
 73 #include <linux/hdlc.h>
 74 #include <linux/synclink.h>
 75 
 76 #include <asm/io.h>
 77 #include <asm/irq.h>
 78 #include <asm/dma.h>
 79 #include <asm/types.h>
 80 #include <asm/uaccess.h>
 81 
 82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
 83 #define SYNCLINK_GENERIC_HDLC 1
 84 #else
 85 #define SYNCLINK_GENERIC_HDLC 0
 86 #endif
 87 
 88 /*
 89  * module identification
 90  */
 91 static char *driver_name     = "SyncLink GT";
 92 static char *tty_driver_name = "synclink_gt";
 93 static char *tty_dev_prefix  = "ttySLG";
 94 MODULE_LICENSE("GPL");
 95 #define MGSL_MAGIC 0x5401
 96 #define MAX_DEVICES 32
 97 
 98 static struct pci_device_id pci_table[] = {
 99         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103         {0,}, /* terminate list */
104 };
105 MODULE_DEVICE_TABLE(pci, pci_table);
106 
107 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
108 static void remove_one(struct pci_dev *dev);
109 static struct pci_driver pci_driver = {
110         .name           = "synclink_gt",
111         .id_table       = pci_table,
112         .probe          = init_one,
113         .remove         = remove_one,
114 };
115 
116 static bool pci_registered;
117 
118 /*
119  * module configuration and status
120  */
121 static struct slgt_info *slgt_device_list;
122 static int slgt_device_count;
123 
124 static int ttymajor;
125 static int debug_level;
126 static int maxframe[MAX_DEVICES];
127 
128 module_param(ttymajor, int, 0);
129 module_param(debug_level, int, 0);
130 module_param_array(maxframe, int, NULL, 0);
131 
132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
135 
136 /*
137  * tty support and callbacks
138  */
139 static struct tty_driver *serial_driver;
140 
141 static int  open(struct tty_struct *tty, struct file * filp);
142 static void close(struct tty_struct *tty, struct file * filp);
143 static void hangup(struct tty_struct *tty);
144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
145 
146 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
147 static int put_char(struct tty_struct *tty, unsigned char ch);
148 static void send_xchar(struct tty_struct *tty, char ch);
149 static void wait_until_sent(struct tty_struct *tty, int timeout);
150 static int  write_room(struct tty_struct *tty);
151 static void flush_chars(struct tty_struct *tty);
152 static void flush_buffer(struct tty_struct *tty);
153 static void tx_hold(struct tty_struct *tty);
154 static void tx_release(struct tty_struct *tty);
155 
156 static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
157 static int  chars_in_buffer(struct tty_struct *tty);
158 static void throttle(struct tty_struct * tty);
159 static void unthrottle(struct tty_struct * tty);
160 static int set_break(struct tty_struct *tty, int break_state);
161 
162 /*
163  * generic HDLC support and callbacks
164  */
165 #if SYNCLINK_GENERIC_HDLC
166 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
167 static void hdlcdev_tx_done(struct slgt_info *info);
168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
169 static int  hdlcdev_init(struct slgt_info *info);
170 static void hdlcdev_exit(struct slgt_info *info);
171 #endif
172 
173 
174 /*
175  * device specific structures, macros and functions
176  */
177 
178 #define SLGT_MAX_PORTS 4
179 #define SLGT_REG_SIZE  256
180 
181 /*
182  * conditional wait facility
183  */
184 struct cond_wait {
185         struct cond_wait *next;
186         wait_queue_head_t q;
187         wait_queue_t wait;
188         unsigned int data;
189 };
190 static void init_cond_wait(struct cond_wait *w, unsigned int data);
191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
193 static void flush_cond_wait(struct cond_wait **head);
194 
195 /*
196  * DMA buffer descriptor and access macros
197  */
198 struct slgt_desc
199 {
200         __le16 count;
201         __le16 status;
202         __le32 pbuf;  /* physical address of data buffer */
203         __le32 next;  /* physical address of next descriptor */
204 
205         /* driver book keeping */
206         char *buf;          /* virtual  address of data buffer */
207         unsigned int pdesc; /* physical address of this descriptor */
208         dma_addr_t buf_dma_addr;
209         unsigned short buf_count;
210 };
211 
212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
213 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
214 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
215 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
217 #define desc_count(a)      (le16_to_cpu((a).count))
218 #define desc_status(a)     (le16_to_cpu((a).status))
219 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
220 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
221 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
222 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
223 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
224 
225 struct _input_signal_events {
226         int ri_up;
227         int ri_down;
228         int dsr_up;
229         int dsr_down;
230         int dcd_up;
231         int dcd_down;
232         int cts_up;
233         int cts_down;
234 };
235 
236 /*
237  * device instance data structure
238  */
239 struct slgt_info {
240         void *if_ptr;           /* General purpose pointer (used by SPPP) */
241         struct tty_port port;
242 
243         struct slgt_info *next_device;  /* device list link */
244 
245         int magic;
246 
247         char device_name[25];
248         struct pci_dev *pdev;
249 
250         int port_count;  /* count of ports on adapter */
251         int adapter_num; /* adapter instance number */
252         int port_num;    /* port instance number */
253 
254         /* array of pointers to port contexts on this adapter */
255         struct slgt_info *port_array[SLGT_MAX_PORTS];
256 
257         int                     line;           /* tty line instance number */
258 
259         struct mgsl_icount      icount;
260 
261         int                     timeout;
262         int                     x_char;         /* xon/xoff character */
263         unsigned int            read_status_mask;
264         unsigned int            ignore_status_mask;
265 
266         wait_queue_head_t       status_event_wait_q;
267         wait_queue_head_t       event_wait_q;
268         struct timer_list       tx_timer;
269         struct timer_list       rx_timer;
270 
271         unsigned int            gpio_present;
272         struct cond_wait        *gpio_wait_q;
273 
274         spinlock_t lock;        /* spinlock for synchronizing with ISR */
275 
276         struct work_struct task;
277         u32 pending_bh;
278         bool bh_requested;
279         bool bh_running;
280 
281         int isr_overflow;
282         bool irq_requested;     /* true if IRQ requested */
283         bool irq_occurred;      /* for diagnostics use */
284 
285         /* device configuration */
286 
287         unsigned int bus_type;
288         unsigned int irq_level;
289         unsigned long irq_flags;
290 
291         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
292         u32 phys_reg_addr;
293         bool reg_addr_requested;
294 
295         MGSL_PARAMS params;       /* communications parameters */
296         u32 idle_mode;
297         u32 max_frame_size;       /* as set by device config */
298 
299         unsigned int rbuf_fill_level;
300         unsigned int rx_pio;
301         unsigned int if_mode;
302         unsigned int base_clock;
303         unsigned int xsync;
304         unsigned int xctrl;
305 
306         /* device status */
307 
308         bool rx_enabled;
309         bool rx_restart;
310 
311         bool tx_enabled;
312         bool tx_active;
313 
314         unsigned char signals;    /* serial signal states */
315         int init_error;  /* initialization error */
316 
317         unsigned char *tx_buf;
318         int tx_count;
319 
320         char *flag_buf;
321         bool drop_rts_on_tx_done;
322         struct  _input_signal_events    input_signal_events;
323 
324         int dcd_chkcount;       /* check counts to prevent */
325         int cts_chkcount;       /* too many IRQs if a signal */
326         int dsr_chkcount;       /* is floating */
327         int ri_chkcount;
328 
329         char *bufs;             /* virtual address of DMA buffer lists */
330         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
331 
332         unsigned int rbuf_count;
333         struct slgt_desc *rbufs;
334         unsigned int rbuf_current;
335         unsigned int rbuf_index;
336         unsigned int rbuf_fill_index;
337         unsigned short rbuf_fill_count;
338 
339         unsigned int tbuf_count;
340         struct slgt_desc *tbufs;
341         unsigned int tbuf_current;
342         unsigned int tbuf_start;
343 
344         unsigned char *tmp_rbuf;
345         unsigned int tmp_rbuf_count;
346 
347         /* SPPP/Cisco HDLC device parts */
348 
349         int netcount;
350         spinlock_t netlock;
351 #if SYNCLINK_GENERIC_HDLC
352         struct net_device *netdev;
353 #endif
354 
355 };
356 
357 static MGSL_PARAMS default_params = {
358         .mode            = MGSL_MODE_HDLC,
359         .loopback        = 0,
360         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
361         .encoding        = HDLC_ENCODING_NRZI_SPACE,
362         .clock_speed     = 0,
363         .addr_filter     = 0xff,
364         .crc_type        = HDLC_CRC_16_CCITT,
365         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
366         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
367         .data_rate       = 9600,
368         .data_bits       = 8,
369         .stop_bits       = 1,
370         .parity          = ASYNC_PARITY_NONE
371 };
372 
373 
374 #define BH_RECEIVE  1
375 #define BH_TRANSMIT 2
376 #define BH_STATUS   4
377 #define IO_PIN_SHUTDOWN_LIMIT 100
378 
379 #define DMABUFSIZE 256
380 #define DESC_LIST_SIZE 4096
381 
382 #define MASK_PARITY  BIT1
383 #define MASK_FRAMING BIT0
384 #define MASK_BREAK   BIT14
385 #define MASK_OVERRUN BIT4
386 
387 #define GSR   0x00 /* global status */
388 #define JCR   0x04 /* JTAG control */
389 #define IODR  0x08 /* GPIO direction */
390 #define IOER  0x0c /* GPIO interrupt enable */
391 #define IOVR  0x10 /* GPIO value */
392 #define IOSR  0x14 /* GPIO interrupt status */
393 #define TDR   0x80 /* tx data */
394 #define RDR   0x80 /* rx data */
395 #define TCR   0x82 /* tx control */
396 #define TIR   0x84 /* tx idle */
397 #define TPR   0x85 /* tx preamble */
398 #define RCR   0x86 /* rx control */
399 #define VCR   0x88 /* V.24 control */
400 #define CCR   0x89 /* clock control */
401 #define BDR   0x8a /* baud divisor */
402 #define SCR   0x8c /* serial control */
403 #define SSR   0x8e /* serial status */
404 #define RDCSR 0x90 /* rx DMA control/status */
405 #define TDCSR 0x94 /* tx DMA control/status */
406 #define RDDAR 0x98 /* rx DMA descriptor address */
407 #define TDDAR 0x9c /* tx DMA descriptor address */
408 #define XSR   0x40 /* extended sync pattern */
409 #define XCR   0x44 /* extended control */
410 
411 #define RXIDLE      BIT14
412 #define RXBREAK     BIT14
413 #define IRQ_TXDATA  BIT13
414 #define IRQ_TXIDLE  BIT12
415 #define IRQ_TXUNDER BIT11 /* HDLC */
416 #define IRQ_RXDATA  BIT10
417 #define IRQ_RXIDLE  BIT9  /* HDLC */
418 #define IRQ_RXBREAK BIT9  /* async */
419 #define IRQ_RXOVER  BIT8
420 #define IRQ_DSR     BIT7
421 #define IRQ_CTS     BIT6
422 #define IRQ_DCD     BIT5
423 #define IRQ_RI      BIT4
424 #define IRQ_ALL     0x3ff0
425 #define IRQ_MASTER  BIT0
426 
427 #define slgt_irq_on(info, mask) \
428         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
429 #define slgt_irq_off(info, mask) \
430         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
431 
432 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
433 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
435 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
437 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
438 
439 static void  msc_set_vcr(struct slgt_info *info);
440 
441 static int  startup(struct slgt_info *info);
442 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
443 static void shutdown(struct slgt_info *info);
444 static void program_hw(struct slgt_info *info);
445 static void change_params(struct slgt_info *info);
446 
447 static int  register_test(struct slgt_info *info);
448 static int  irq_test(struct slgt_info *info);
449 static int  loopback_test(struct slgt_info *info);
450 static int  adapter_test(struct slgt_info *info);
451 
452 static void reset_adapter(struct slgt_info *info);
453 static void reset_port(struct slgt_info *info);
454 static void async_mode(struct slgt_info *info);
455 static void sync_mode(struct slgt_info *info);
456 
457 static void rx_stop(struct slgt_info *info);
458 static void rx_start(struct slgt_info *info);
459 static void reset_rbufs(struct slgt_info *info);
460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
461 static void rdma_reset(struct slgt_info *info);
462 static bool rx_get_frame(struct slgt_info *info);
463 static bool rx_get_buf(struct slgt_info *info);
464 
465 static void tx_start(struct slgt_info *info);
466 static void tx_stop(struct slgt_info *info);
467 static void tx_set_idle(struct slgt_info *info);
468 static unsigned int free_tbuf_count(struct slgt_info *info);
469 static unsigned int tbuf_bytes(struct slgt_info *info);
470 static void reset_tbufs(struct slgt_info *info);
471 static void tdma_reset(struct slgt_info *info);
472 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
473 
474 static void get_signals(struct slgt_info *info);
475 static void set_signals(struct slgt_info *info);
476 static void enable_loopback(struct slgt_info *info);
477 static void set_rate(struct slgt_info *info, u32 data_rate);
478 
479 static int  bh_action(struct slgt_info *info);
480 static void bh_handler(struct work_struct *work);
481 static void bh_transmit(struct slgt_info *info);
482 static void isr_serial(struct slgt_info *info);
483 static void isr_rdma(struct slgt_info *info);
484 static void isr_txeom(struct slgt_info *info, unsigned short status);
485 static void isr_tdma(struct slgt_info *info);
486 
487 static int  alloc_dma_bufs(struct slgt_info *info);
488 static void free_dma_bufs(struct slgt_info *info);
489 static int  alloc_desc(struct slgt_info *info);
490 static void free_desc(struct slgt_info *info);
491 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
493 
494 static int  alloc_tmp_rbuf(struct slgt_info *info);
495 static void free_tmp_rbuf(struct slgt_info *info);
496 
497 static void tx_timeout(unsigned long context);
498 static void rx_timeout(unsigned long context);
499 
500 /*
501  * ioctl handlers
502  */
503 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
504 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
506 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
507 static int  set_txidle(struct slgt_info *info, int idle_mode);
508 static int  tx_enable(struct slgt_info *info, int enable);
509 static int  tx_abort(struct slgt_info *info);
510 static int  rx_enable(struct slgt_info *info, int enable);
511 static int  modem_input_wait(struct slgt_info *info,int arg);
512 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
513 static int  tiocmget(struct tty_struct *tty);
514 static int  tiocmset(struct tty_struct *tty,
515                                 unsigned int set, unsigned int clear);
516 static int set_break(struct tty_struct *tty, int break_state);
517 static int  get_interface(struct slgt_info *info, int __user *if_mode);
518 static int  set_interface(struct slgt_info *info, int if_mode);
519 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
522 static int  get_xsync(struct slgt_info *info, int __user *if_mode);
523 static int  set_xsync(struct slgt_info *info, int if_mode);
524 static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
525 static int  set_xctrl(struct slgt_info *info, int if_mode);
526 
527 /*
528  * driver functions
529  */
530 static void add_device(struct slgt_info *info);
531 static void device_init(int adapter_num, struct pci_dev *pdev);
532 static int  claim_resources(struct slgt_info *info);
533 static void release_resources(struct slgt_info *info);
534 
535 /*
536  * DEBUG OUTPUT CODE
537  */
538 #ifndef DBGINFO
539 #define DBGINFO(fmt)
540 #endif
541 #ifndef DBGERR
542 #define DBGERR(fmt)
543 #endif
544 #ifndef DBGBH
545 #define DBGBH(fmt)
546 #endif
547 #ifndef DBGISR
548 #define DBGISR(fmt)
549 #endif
550 
551 #ifdef DBGDATA
552 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
553 {
554         int i;
555         int linecount;
556         printk("%s %s data:\n",info->device_name, label);
557         while(count) {
558                 linecount = (count > 16) ? 16 : count;
559                 for(i=0; i < linecount; i++)
560                         printk("%02X ",(unsigned char)data[i]);
561                 for(;i<17;i++)
562                         printk("   ");
563                 for(i=0;i<linecount;i++) {
564                         if (data[i]>=040 && data[i]<=0176)
565                                 printk("%c",data[i]);
566                         else
567                                 printk(".");
568                 }
569                 printk("\n");
570                 data  += linecount;
571                 count -= linecount;
572         }
573 }
574 #else
575 #define DBGDATA(info, buf, size, label)
576 #endif
577 
578 #ifdef DBGTBUF
579 static void dump_tbufs(struct slgt_info *info)
580 {
581         int i;
582         printk("tbuf_current=%d\n", info->tbuf_current);
583         for (i=0 ; i < info->tbuf_count ; i++) {
584                 printk("%d: count=%04X status=%04X\n",
585                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
586         }
587 }
588 #else
589 #define DBGTBUF(info)
590 #endif
591 
592 #ifdef DBGRBUF
593 static void dump_rbufs(struct slgt_info *info)
594 {
595         int i;
596         printk("rbuf_current=%d\n", info->rbuf_current);
597         for (i=0 ; i < info->rbuf_count ; i++) {
598                 printk("%d: count=%04X status=%04X\n",
599                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
600         }
601 }
602 #else
603 #define DBGRBUF(info)
604 #endif
605 
606 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
607 {
608 #ifdef SANITY_CHECK
609         if (!info) {
610                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
611                 return 1;
612         }
613         if (info->magic != MGSL_MAGIC) {
614                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
615                 return 1;
616         }
617 #else
618         if (!info)
619                 return 1;
620 #endif
621         return 0;
622 }
623 
624 /**
625  * line discipline callback wrappers
626  *
627  * The wrappers maintain line discipline references
628  * while calling into the line discipline.
629  *
630  * ldisc_receive_buf  - pass receive data to line discipline
631  */
632 static void ldisc_receive_buf(struct tty_struct *tty,
633                               const __u8 *data, char *flags, int count)
634 {
635         struct tty_ldisc *ld;
636         if (!tty)
637                 return;
638         ld = tty_ldisc_ref(tty);
639         if (ld) {
640                 if (ld->ops->receive_buf)
641                         ld->ops->receive_buf(tty, data, flags, count);
642                 tty_ldisc_deref(ld);
643         }
644 }
645 
646 /* tty callbacks */
647 
648 static int open(struct tty_struct *tty, struct file *filp)
649 {
650         struct slgt_info *info;
651         int retval, line;
652         unsigned long flags;
653 
654         line = tty->index;
655         if (line >= slgt_device_count) {
656                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
657                 return -ENODEV;
658         }
659 
660         info = slgt_device_list;
661         while(info && info->line != line)
662                 info = info->next_device;
663         if (sanity_check(info, tty->name, "open"))
664                 return -ENODEV;
665         if (info->init_error) {
666                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
667                 return -ENODEV;
668         }
669 
670         tty->driver_data = info;
671         info->port.tty = tty;
672 
673         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
674 
675         /* If port is closing, signal caller to try again */
676         if (info->port.flags & ASYNC_CLOSING){
677                 wait_event_interruptible_tty(tty, info->port.close_wait,
678                                              !(info->port.flags & ASYNC_CLOSING));
679                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
680                         -EAGAIN : -ERESTARTSYS);
681                 goto cleanup;
682         }
683 
684         mutex_lock(&info->port.mutex);
685         info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
686 
687         spin_lock_irqsave(&info->netlock, flags);
688         if (info->netcount) {
689                 retval = -EBUSY;
690                 spin_unlock_irqrestore(&info->netlock, flags);
691                 mutex_unlock(&info->port.mutex);
692                 goto cleanup;
693         }
694         info->port.count++;
695         spin_unlock_irqrestore(&info->netlock, flags);
696 
697         if (info->port.count == 1) {
698                 /* 1st open on this device, init hardware */
699                 retval = startup(info);
700                 if (retval < 0) {
701                         mutex_unlock(&info->port.mutex);
702                         goto cleanup;
703                 }
704         }
705         mutex_unlock(&info->port.mutex);
706         retval = block_til_ready(tty, filp, info);
707         if (retval) {
708                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
709                 goto cleanup;
710         }
711 
712         retval = 0;
713 
714 cleanup:
715         if (retval) {
716                 if (tty->count == 1)
717                         info->port.tty = NULL; /* tty layer will release tty struct */
718                 if(info->port.count)
719                         info->port.count--;
720         }
721 
722         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
723         return retval;
724 }
725 
726 static void close(struct tty_struct *tty, struct file *filp)
727 {
728         struct slgt_info *info = tty->driver_data;
729 
730         if (sanity_check(info, tty->name, "close"))
731                 return;
732         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
733 
734         if (tty_port_close_start(&info->port, tty, filp) == 0)
735                 goto cleanup;
736 
737         mutex_lock(&info->port.mutex);
738         if (info->port.flags & ASYNC_INITIALIZED)
739                 wait_until_sent(tty, info->timeout);
740         flush_buffer(tty);
741         tty_ldisc_flush(tty);
742 
743         shutdown(info);
744         mutex_unlock(&info->port.mutex);
745 
746         tty_port_close_end(&info->port, tty);
747         info->port.tty = NULL;
748 cleanup:
749         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
750 }
751 
752 static void hangup(struct tty_struct *tty)
753 {
754         struct slgt_info *info = tty->driver_data;
755         unsigned long flags;
756 
757         if (sanity_check(info, tty->name, "hangup"))
758                 return;
759         DBGINFO(("%s hangup\n", info->device_name));
760 
761         flush_buffer(tty);
762 
763         mutex_lock(&info->port.mutex);
764         shutdown(info);
765 
766         spin_lock_irqsave(&info->port.lock, flags);
767         info->port.count = 0;
768         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
769         info->port.tty = NULL;
770         spin_unlock_irqrestore(&info->port.lock, flags);
771         mutex_unlock(&info->port.mutex);
772 
773         wake_up_interruptible(&info->port.open_wait);
774 }
775 
776 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
777 {
778         struct slgt_info *info = tty->driver_data;
779         unsigned long flags;
780 
781         DBGINFO(("%s set_termios\n", tty->driver->name));
782 
783         change_params(info);
784 
785         /* Handle transition to B0 status */
786         if (old_termios->c_cflag & CBAUD &&
787             !(tty->termios.c_cflag & CBAUD)) {
788                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
789                 spin_lock_irqsave(&info->lock,flags);
790                 set_signals(info);
791                 spin_unlock_irqrestore(&info->lock,flags);
792         }
793 
794         /* Handle transition away from B0 status */
795         if (!(old_termios->c_cflag & CBAUD) &&
796             tty->termios.c_cflag & CBAUD) {
797                 info->signals |= SerialSignal_DTR;
798                 if (!(tty->termios.c_cflag & CRTSCTS) ||
799                     !test_bit(TTY_THROTTLED, &tty->flags)) {
800                         info->signals |= SerialSignal_RTS;
801                 }
802                 spin_lock_irqsave(&info->lock,flags);
803                 set_signals(info);
804                 spin_unlock_irqrestore(&info->lock,flags);
805         }
806 
807         /* Handle turning off CRTSCTS */
808         if (old_termios->c_cflag & CRTSCTS &&
809             !(tty->termios.c_cflag & CRTSCTS)) {
810                 tty->hw_stopped = 0;
811                 tx_release(tty);
812         }
813 }
814 
815 static void update_tx_timer(struct slgt_info *info)
816 {
817         /*
818          * use worst case speed of 1200bps to calculate transmit timeout
819          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
820          */
821         if (info->params.mode == MGSL_MODE_HDLC) {
822                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
823                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
824         }
825 }
826 
827 static int write(struct tty_struct *tty,
828                  const unsigned char *buf, int count)
829 {
830         int ret = 0;
831         struct slgt_info *info = tty->driver_data;
832         unsigned long flags;
833 
834         if (sanity_check(info, tty->name, "write"))
835                 return -EIO;
836 
837         DBGINFO(("%s write count=%d\n", info->device_name, count));
838 
839         if (!info->tx_buf || (count > info->max_frame_size))
840                 return -EIO;
841 
842         if (!count || tty->stopped || tty->hw_stopped)
843                 return 0;
844 
845         spin_lock_irqsave(&info->lock, flags);
846 
847         if (info->tx_count) {
848                 /* send accumulated data from send_char() */
849                 if (!tx_load(info, info->tx_buf, info->tx_count))
850                         goto cleanup;
851                 info->tx_count = 0;
852         }
853 
854         if (tx_load(info, buf, count))
855                 ret = count;
856 
857 cleanup:
858         spin_unlock_irqrestore(&info->lock, flags);
859         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
860         return ret;
861 }
862 
863 static int put_char(struct tty_struct *tty, unsigned char ch)
864 {
865         struct slgt_info *info = tty->driver_data;
866         unsigned long flags;
867         int ret = 0;
868 
869         if (sanity_check(info, tty->name, "put_char"))
870                 return 0;
871         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
872         if (!info->tx_buf)
873                 return 0;
874         spin_lock_irqsave(&info->lock,flags);
875         if (info->tx_count < info->max_frame_size) {
876                 info->tx_buf[info->tx_count++] = ch;
877                 ret = 1;
878         }
879         spin_unlock_irqrestore(&info->lock,flags);
880         return ret;
881 }
882 
883 static void send_xchar(struct tty_struct *tty, char ch)
884 {
885         struct slgt_info *info = tty->driver_data;
886         unsigned long flags;
887 
888         if (sanity_check(info, tty->name, "send_xchar"))
889                 return;
890         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
891         info->x_char = ch;
892         if (ch) {
893                 spin_lock_irqsave(&info->lock,flags);
894                 if (!info->tx_enabled)
895                         tx_start(info);
896                 spin_unlock_irqrestore(&info->lock,flags);
897         }
898 }
899 
900 static void wait_until_sent(struct tty_struct *tty, int timeout)
901 {
902         struct slgt_info *info = tty->driver_data;
903         unsigned long orig_jiffies, char_time;
904 
905         if (!info )
906                 return;
907         if (sanity_check(info, tty->name, "wait_until_sent"))
908                 return;
909         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
910         if (!(info->port.flags & ASYNC_INITIALIZED))
911                 goto exit;
912 
913         orig_jiffies = jiffies;
914 
915         /* Set check interval to 1/5 of estimated time to
916          * send a character, and make it at least 1. The check
917          * interval should also be less than the timeout.
918          * Note: use tight timings here to satisfy the NIST-PCTS.
919          */
920 
921         if (info->params.data_rate) {
922                 char_time = info->timeout/(32 * 5);
923                 if (!char_time)
924                         char_time++;
925         } else
926                 char_time = 1;
927 
928         if (timeout)
929                 char_time = min_t(unsigned long, char_time, timeout);
930 
931         while (info->tx_active) {
932                 msleep_interruptible(jiffies_to_msecs(char_time));
933                 if (signal_pending(current))
934                         break;
935                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
936                         break;
937         }
938 exit:
939         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
940 }
941 
942 static int write_room(struct tty_struct *tty)
943 {
944         struct slgt_info *info = tty->driver_data;
945         int ret;
946 
947         if (sanity_check(info, tty->name, "write_room"))
948                 return 0;
949         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
950         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
951         return ret;
952 }
953 
954 static void flush_chars(struct tty_struct *tty)
955 {
956         struct slgt_info *info = tty->driver_data;
957         unsigned long flags;
958 
959         if (sanity_check(info, tty->name, "flush_chars"))
960                 return;
961         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
962 
963         if (info->tx_count <= 0 || tty->stopped ||
964             tty->hw_stopped || !info->tx_buf)
965                 return;
966 
967         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
968 
969         spin_lock_irqsave(&info->lock,flags);
970         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
971                 info->tx_count = 0;
972         spin_unlock_irqrestore(&info->lock,flags);
973 }
974 
975 static void flush_buffer(struct tty_struct *tty)
976 {
977         struct slgt_info *info = tty->driver_data;
978         unsigned long flags;
979 
980         if (sanity_check(info, tty->name, "flush_buffer"))
981                 return;
982         DBGINFO(("%s flush_buffer\n", info->device_name));
983 
984         spin_lock_irqsave(&info->lock, flags);
985         info->tx_count = 0;
986         spin_unlock_irqrestore(&info->lock, flags);
987 
988         tty_wakeup(tty);
989 }
990 
991 /*
992  * throttle (stop) transmitter
993  */
994 static void tx_hold(struct tty_struct *tty)
995 {
996         struct slgt_info *info = tty->driver_data;
997         unsigned long flags;
998 
999         if (sanity_check(info, tty->name, "tx_hold"))
1000                 return;
1001         DBGINFO(("%s tx_hold\n", info->device_name));
1002         spin_lock_irqsave(&info->lock,flags);
1003         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1004                 tx_stop(info);
1005         spin_unlock_irqrestore(&info->lock,flags);
1006 }
1007 
1008 /*
1009  * release (start) transmitter
1010  */
1011 static void tx_release(struct tty_struct *tty)
1012 {
1013         struct slgt_info *info = tty->driver_data;
1014         unsigned long flags;
1015 
1016         if (sanity_check(info, tty->name, "tx_release"))
1017                 return;
1018         DBGINFO(("%s tx_release\n", info->device_name));
1019         spin_lock_irqsave(&info->lock, flags);
1020         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1021                 info->tx_count = 0;
1022         spin_unlock_irqrestore(&info->lock, flags);
1023 }
1024 
1025 /*
1026  * Service an IOCTL request
1027  *
1028  * Arguments
1029  *
1030  *      tty     pointer to tty instance data
1031  *      cmd     IOCTL command code
1032  *      arg     command argument/context
1033  *
1034  * Return 0 if success, otherwise error code
1035  */
1036 static int ioctl(struct tty_struct *tty,
1037                  unsigned int cmd, unsigned long arg)
1038 {
1039         struct slgt_info *info = tty->driver_data;
1040         void __user *argp = (void __user *)arg;
1041         int ret;
1042 
1043         if (sanity_check(info, tty->name, "ioctl"))
1044                 return -ENODEV;
1045         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1046 
1047         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1048             (cmd != TIOCMIWAIT)) {
1049                 if (tty->flags & (1 << TTY_IO_ERROR))
1050                     return -EIO;
1051         }
1052 
1053         switch (cmd) {
1054         case MGSL_IOCWAITEVENT:
1055                 return wait_mgsl_event(info, argp);
1056         case TIOCMIWAIT:
1057                 return modem_input_wait(info,(int)arg);
1058         case MGSL_IOCSGPIO:
1059                 return set_gpio(info, argp);
1060         case MGSL_IOCGGPIO:
1061                 return get_gpio(info, argp);
1062         case MGSL_IOCWAITGPIO:
1063                 return wait_gpio(info, argp);
1064         case MGSL_IOCGXSYNC:
1065                 return get_xsync(info, argp);
1066         case MGSL_IOCSXSYNC:
1067                 return set_xsync(info, (int)arg);
1068         case MGSL_IOCGXCTRL:
1069                 return get_xctrl(info, argp);
1070         case MGSL_IOCSXCTRL:
1071                 return set_xctrl(info, (int)arg);
1072         }
1073         mutex_lock(&info->port.mutex);
1074         switch (cmd) {
1075         case MGSL_IOCGPARAMS:
1076                 ret = get_params(info, argp);
1077                 break;
1078         case MGSL_IOCSPARAMS:
1079                 ret = set_params(info, argp);
1080                 break;
1081         case MGSL_IOCGTXIDLE:
1082                 ret = get_txidle(info, argp);
1083                 break;
1084         case MGSL_IOCSTXIDLE:
1085                 ret = set_txidle(info, (int)arg);
1086                 break;
1087         case MGSL_IOCTXENABLE:
1088                 ret = tx_enable(info, (int)arg);
1089                 break;
1090         case MGSL_IOCRXENABLE:
1091                 ret = rx_enable(info, (int)arg);
1092                 break;
1093         case MGSL_IOCTXABORT:
1094                 ret = tx_abort(info);
1095                 break;
1096         case MGSL_IOCGSTATS:
1097                 ret = get_stats(info, argp);
1098                 break;
1099         case MGSL_IOCGIF:
1100                 ret = get_interface(info, argp);
1101                 break;
1102         case MGSL_IOCSIF:
1103                 ret = set_interface(info,(int)arg);
1104                 break;
1105         default:
1106                 ret = -ENOIOCTLCMD;
1107         }
1108         mutex_unlock(&info->port.mutex);
1109         return ret;
1110 }
1111 
1112 static int get_icount(struct tty_struct *tty,
1113                                 struct serial_icounter_struct *icount)
1114 
1115 {
1116         struct slgt_info *info = tty->driver_data;
1117         struct mgsl_icount cnow;        /* kernel counter temps */
1118         unsigned long flags;
1119 
1120         spin_lock_irqsave(&info->lock,flags);
1121         cnow = info->icount;
1122         spin_unlock_irqrestore(&info->lock,flags);
1123 
1124         icount->cts = cnow.cts;
1125         icount->dsr = cnow.dsr;
1126         icount->rng = cnow.rng;
1127         icount->dcd = cnow.dcd;
1128         icount->rx = cnow.rx;
1129         icount->tx = cnow.tx;
1130         icount->frame = cnow.frame;
1131         icount->overrun = cnow.overrun;
1132         icount->parity = cnow.parity;
1133         icount->brk = cnow.brk;
1134         icount->buf_overrun = cnow.buf_overrun;
1135 
1136         return 0;
1137 }
1138 
1139 /*
1140  * support for 32 bit ioctl calls on 64 bit systems
1141  */
1142 #ifdef CONFIG_COMPAT
1143 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1144 {
1145         struct MGSL_PARAMS32 tmp_params;
1146 
1147         DBGINFO(("%s get_params32\n", info->device_name));
1148         memset(&tmp_params, 0, sizeof(tmp_params));
1149         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1150         tmp_params.loopback        = info->params.loopback;
1151         tmp_params.flags           = info->params.flags;
1152         tmp_params.encoding        = info->params.encoding;
1153         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1154         tmp_params.addr_filter     = info->params.addr_filter;
1155         tmp_params.crc_type        = info->params.crc_type;
1156         tmp_params.preamble_length = info->params.preamble_length;
1157         tmp_params.preamble        = info->params.preamble;
1158         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1159         tmp_params.data_bits       = info->params.data_bits;
1160         tmp_params.stop_bits       = info->params.stop_bits;
1161         tmp_params.parity          = info->params.parity;
1162         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1163                 return -EFAULT;
1164         return 0;
1165 }
1166 
1167 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1168 {
1169         struct MGSL_PARAMS32 tmp_params;
1170 
1171         DBGINFO(("%s set_params32\n", info->device_name));
1172         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1173                 return -EFAULT;
1174 
1175         spin_lock(&info->lock);
1176         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1177                 info->base_clock = tmp_params.clock_speed;
1178         } else {
1179                 info->params.mode            = tmp_params.mode;
1180                 info->params.loopback        = tmp_params.loopback;
1181                 info->params.flags           = tmp_params.flags;
1182                 info->params.encoding        = tmp_params.encoding;
1183                 info->params.clock_speed     = tmp_params.clock_speed;
1184                 info->params.addr_filter     = tmp_params.addr_filter;
1185                 info->params.crc_type        = tmp_params.crc_type;
1186                 info->params.preamble_length = tmp_params.preamble_length;
1187                 info->params.preamble        = tmp_params.preamble;
1188                 info->params.data_rate       = tmp_params.data_rate;
1189                 info->params.data_bits       = tmp_params.data_bits;
1190                 info->params.stop_bits       = tmp_params.stop_bits;
1191                 info->params.parity          = tmp_params.parity;
1192         }
1193         spin_unlock(&info->lock);
1194 
1195         program_hw(info);
1196 
1197         return 0;
1198 }
1199 
1200 static long slgt_compat_ioctl(struct tty_struct *tty,
1201                          unsigned int cmd, unsigned long arg)
1202 {
1203         struct slgt_info *info = tty->driver_data;
1204         int rc = -ENOIOCTLCMD;
1205 
1206         if (sanity_check(info, tty->name, "compat_ioctl"))
1207                 return -ENODEV;
1208         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1209 
1210         switch (cmd) {
1211 
1212         case MGSL_IOCSPARAMS32:
1213                 rc = set_params32(info, compat_ptr(arg));
1214                 break;
1215 
1216         case MGSL_IOCGPARAMS32:
1217                 rc = get_params32(info, compat_ptr(arg));
1218                 break;
1219 
1220         case MGSL_IOCGPARAMS:
1221         case MGSL_IOCSPARAMS:
1222         case MGSL_IOCGTXIDLE:
1223         case MGSL_IOCGSTATS:
1224         case MGSL_IOCWAITEVENT:
1225         case MGSL_IOCGIF:
1226         case MGSL_IOCSGPIO:
1227         case MGSL_IOCGGPIO:
1228         case MGSL_IOCWAITGPIO:
1229         case MGSL_IOCGXSYNC:
1230         case MGSL_IOCGXCTRL:
1231         case MGSL_IOCSTXIDLE:
1232         case MGSL_IOCTXENABLE:
1233         case MGSL_IOCRXENABLE:
1234         case MGSL_IOCTXABORT:
1235         case TIOCMIWAIT:
1236         case MGSL_IOCSIF:
1237         case MGSL_IOCSXSYNC:
1238         case MGSL_IOCSXCTRL:
1239                 rc = ioctl(tty, cmd, arg);
1240                 break;
1241         }
1242 
1243         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1244         return rc;
1245 }
1246 #else
1247 #define slgt_compat_ioctl NULL
1248 #endif /* ifdef CONFIG_COMPAT */
1249 
1250 /*
1251  * proc fs support
1252  */
1253 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1254 {
1255         char stat_buf[30];
1256         unsigned long flags;
1257 
1258         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1259                       info->device_name, info->phys_reg_addr,
1260                       info->irq_level, info->max_frame_size);
1261 
1262         /* output current serial signal states */
1263         spin_lock_irqsave(&info->lock,flags);
1264         get_signals(info);
1265         spin_unlock_irqrestore(&info->lock,flags);
1266 
1267         stat_buf[0] = 0;
1268         stat_buf[1] = 0;
1269         if (info->signals & SerialSignal_RTS)
1270                 strcat(stat_buf, "|RTS");
1271         if (info->signals & SerialSignal_CTS)
1272                 strcat(stat_buf, "|CTS");
1273         if (info->signals & SerialSignal_DTR)
1274                 strcat(stat_buf, "|DTR");
1275         if (info->signals & SerialSignal_DSR)
1276                 strcat(stat_buf, "|DSR");
1277         if (info->signals & SerialSignal_DCD)
1278                 strcat(stat_buf, "|CD");
1279         if (info->signals & SerialSignal_RI)
1280                 strcat(stat_buf, "|RI");
1281 
1282         if (info->params.mode != MGSL_MODE_ASYNC) {
1283                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1284                                info->icount.txok, info->icount.rxok);
1285                 if (info->icount.txunder)
1286                         seq_printf(m, " txunder:%d", info->icount.txunder);
1287                 if (info->icount.txabort)
1288                         seq_printf(m, " txabort:%d", info->icount.txabort);
1289                 if (info->icount.rxshort)
1290                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1291                 if (info->icount.rxlong)
1292                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1293                 if (info->icount.rxover)
1294                         seq_printf(m, " rxover:%d", info->icount.rxover);
1295                 if (info->icount.rxcrc)
1296                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1297         } else {
1298                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1299                                info->icount.tx, info->icount.rx);
1300                 if (info->icount.frame)
1301                         seq_printf(m, " fe:%d", info->icount.frame);
1302                 if (info->icount.parity)
1303                         seq_printf(m, " pe:%d", info->icount.parity);
1304                 if (info->icount.brk)
1305                         seq_printf(m, " brk:%d", info->icount.brk);
1306                 if (info->icount.overrun)
1307                         seq_printf(m, " oe:%d", info->icount.overrun);
1308         }
1309 
1310         /* Append serial signal status to end */
1311         seq_printf(m, " %s\n", stat_buf+1);
1312 
1313         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1314                        info->tx_active,info->bh_requested,info->bh_running,
1315                        info->pending_bh);
1316 }
1317 
1318 /* Called to print information about devices
1319  */
1320 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1321 {
1322         struct slgt_info *info;
1323 
1324         seq_puts(m, "synclink_gt driver\n");
1325 
1326         info = slgt_device_list;
1327         while( info ) {
1328                 line_info(m, info);
1329                 info = info->next_device;
1330         }
1331         return 0;
1332 }
1333 
1334 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1335 {
1336         return single_open(file, synclink_gt_proc_show, NULL);
1337 }
1338 
1339 static const struct file_operations synclink_gt_proc_fops = {
1340         .owner          = THIS_MODULE,
1341         .open           = synclink_gt_proc_open,
1342         .read           = seq_read,
1343         .llseek         = seq_lseek,
1344         .release        = single_release,
1345 };
1346 
1347 /*
1348  * return count of bytes in transmit buffer
1349  */
1350 static int chars_in_buffer(struct tty_struct *tty)
1351 {
1352         struct slgt_info *info = tty->driver_data;
1353         int count;
1354         if (sanity_check(info, tty->name, "chars_in_buffer"))
1355                 return 0;
1356         count = tbuf_bytes(info);
1357         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1358         return count;
1359 }
1360 
1361 /*
1362  * signal remote device to throttle send data (our receive data)
1363  */
1364 static void throttle(struct tty_struct * tty)
1365 {
1366         struct slgt_info *info = tty->driver_data;
1367         unsigned long flags;
1368 
1369         if (sanity_check(info, tty->name, "throttle"))
1370                 return;
1371         DBGINFO(("%s throttle\n", info->device_name));
1372         if (I_IXOFF(tty))
1373                 send_xchar(tty, STOP_CHAR(tty));
1374         if (tty->termios.c_cflag & CRTSCTS) {
1375                 spin_lock_irqsave(&info->lock,flags);
1376                 info->signals &= ~SerialSignal_RTS;
1377                 set_signals(info);
1378                 spin_unlock_irqrestore(&info->lock,flags);
1379         }
1380 }
1381 
1382 /*
1383  * signal remote device to stop throttling send data (our receive data)
1384  */
1385 static void unthrottle(struct tty_struct * tty)
1386 {
1387         struct slgt_info *info = tty->driver_data;
1388         unsigned long flags;
1389 
1390         if (sanity_check(info, tty->name, "unthrottle"))
1391                 return;
1392         DBGINFO(("%s unthrottle\n", info->device_name));
1393         if (I_IXOFF(tty)) {
1394                 if (info->x_char)
1395                         info->x_char = 0;
1396                 else
1397                         send_xchar(tty, START_CHAR(tty));
1398         }
1399         if (tty->termios.c_cflag & CRTSCTS) {
1400                 spin_lock_irqsave(&info->lock,flags);
1401                 info->signals |= SerialSignal_RTS;
1402                 set_signals(info);
1403                 spin_unlock_irqrestore(&info->lock,flags);
1404         }
1405 }
1406 
1407 /*
1408  * set or clear transmit break condition
1409  * break_state  -1=set break condition, 0=clear
1410  */
1411 static int set_break(struct tty_struct *tty, int break_state)
1412 {
1413         struct slgt_info *info = tty->driver_data;
1414         unsigned short value;
1415         unsigned long flags;
1416 
1417         if (sanity_check(info, tty->name, "set_break"))
1418                 return -EINVAL;
1419         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1420 
1421         spin_lock_irqsave(&info->lock,flags);
1422         value = rd_reg16(info, TCR);
1423         if (break_state == -1)
1424                 value |= BIT6;
1425         else
1426                 value &= ~BIT6;
1427         wr_reg16(info, TCR, value);
1428         spin_unlock_irqrestore(&info->lock,flags);
1429         return 0;
1430 }
1431 
1432 #if SYNCLINK_GENERIC_HDLC
1433 
1434 /**
1435  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1436  * set encoding and frame check sequence (FCS) options
1437  *
1438  * dev       pointer to network device structure
1439  * encoding  serial encoding setting
1440  * parity    FCS setting
1441  *
1442  * returns 0 if success, otherwise error code
1443  */
1444 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1445                           unsigned short parity)
1446 {
1447         struct slgt_info *info = dev_to_port(dev);
1448         unsigned char  new_encoding;
1449         unsigned short new_crctype;
1450 
1451         /* return error if TTY interface open */
1452         if (info->port.count)
1453                 return -EBUSY;
1454 
1455         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1456 
1457         switch (encoding)
1458         {
1459         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1460         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1461         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1462         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1463         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1464         default: return -EINVAL;
1465         }
1466 
1467         switch (parity)
1468         {
1469         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1470         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1471         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1472         default: return -EINVAL;
1473         }
1474 
1475         info->params.encoding = new_encoding;
1476         info->params.crc_type = new_crctype;
1477 
1478         /* if network interface up, reprogram hardware */
1479         if (info->netcount)
1480                 program_hw(info);
1481 
1482         return 0;
1483 }
1484 
1485 /**
1486  * called by generic HDLC layer to send frame
1487  *
1488  * skb  socket buffer containing HDLC frame
1489  * dev  pointer to network device structure
1490  */
1491 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1492                                       struct net_device *dev)
1493 {
1494         struct slgt_info *info = dev_to_port(dev);
1495         unsigned long flags;
1496 
1497         DBGINFO(("%s hdlc_xmit\n", dev->name));
1498 
1499         if (!skb->len)
1500                 return NETDEV_TX_OK;
1501 
1502         /* stop sending until this frame completes */
1503         netif_stop_queue(dev);
1504 
1505         /* update network statistics */
1506         dev->stats.tx_packets++;
1507         dev->stats.tx_bytes += skb->len;
1508 
1509         /* save start time for transmit timeout detection */
1510         dev->trans_start = jiffies;
1511 
1512         spin_lock_irqsave(&info->lock, flags);
1513         tx_load(info, skb->data, skb->len);
1514         spin_unlock_irqrestore(&info->lock, flags);
1515 
1516         /* done with socket buffer, so free it */
1517         dev_kfree_skb(skb);
1518 
1519         return NETDEV_TX_OK;
1520 }
1521 
1522 /**
1523  * called by network layer when interface enabled
1524  * claim resources and initialize hardware
1525  *
1526  * dev  pointer to network device structure
1527  *
1528  * returns 0 if success, otherwise error code
1529  */
1530 static int hdlcdev_open(struct net_device *dev)
1531 {
1532         struct slgt_info *info = dev_to_port(dev);
1533         int rc;
1534         unsigned long flags;
1535 
1536         if (!try_module_get(THIS_MODULE))
1537                 return -EBUSY;
1538 
1539         DBGINFO(("%s hdlcdev_open\n", dev->name));
1540 
1541         /* generic HDLC layer open processing */
1542         if ((rc = hdlc_open(dev)))
1543                 return rc;
1544 
1545         /* arbitrate between network and tty opens */
1546         spin_lock_irqsave(&info->netlock, flags);
1547         if (info->port.count != 0 || info->netcount != 0) {
1548                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1549                 spin_unlock_irqrestore(&info->netlock, flags);
1550                 return -EBUSY;
1551         }
1552         info->netcount=1;
1553         spin_unlock_irqrestore(&info->netlock, flags);
1554 
1555         /* claim resources and init adapter */
1556         if ((rc = startup(info)) != 0) {
1557                 spin_lock_irqsave(&info->netlock, flags);
1558                 info->netcount=0;
1559                 spin_unlock_irqrestore(&info->netlock, flags);
1560                 return rc;
1561         }
1562 
1563         /* assert RTS and DTR, apply hardware settings */
1564         info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1565         program_hw(info);
1566 
1567         /* enable network layer transmit */
1568         dev->trans_start = jiffies;
1569         netif_start_queue(dev);
1570 
1571         /* inform generic HDLC layer of current DCD status */
1572         spin_lock_irqsave(&info->lock, flags);
1573         get_signals(info);
1574         spin_unlock_irqrestore(&info->lock, flags);
1575         if (info->signals & SerialSignal_DCD)
1576                 netif_carrier_on(dev);
1577         else
1578                 netif_carrier_off(dev);
1579         return 0;
1580 }
1581 
1582 /**
1583  * called by network layer when interface is disabled
1584  * shutdown hardware and release resources
1585  *
1586  * dev  pointer to network device structure
1587  *
1588  * returns 0 if success, otherwise error code
1589  */
1590 static int hdlcdev_close(struct net_device *dev)
1591 {
1592         struct slgt_info *info = dev_to_port(dev);
1593         unsigned long flags;
1594 
1595         DBGINFO(("%s hdlcdev_close\n", dev->name));
1596 
1597         netif_stop_queue(dev);
1598 
1599         /* shutdown adapter and release resources */
1600         shutdown(info);
1601 
1602         hdlc_close(dev);
1603 
1604         spin_lock_irqsave(&info->netlock, flags);
1605         info->netcount=0;
1606         spin_unlock_irqrestore(&info->netlock, flags);
1607 
1608         module_put(THIS_MODULE);
1609         return 0;
1610 }
1611 
1612 /**
1613  * called by network layer to process IOCTL call to network device
1614  *
1615  * dev  pointer to network device structure
1616  * ifr  pointer to network interface request structure
1617  * cmd  IOCTL command code
1618  *
1619  * returns 0 if success, otherwise error code
1620  */
1621 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1622 {
1623         const size_t size = sizeof(sync_serial_settings);
1624         sync_serial_settings new_line;
1625         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1626         struct slgt_info *info = dev_to_port(dev);
1627         unsigned int flags;
1628 
1629         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1630 
1631         /* return error if TTY interface open */
1632         if (info->port.count)
1633                 return -EBUSY;
1634 
1635         if (cmd != SIOCWANDEV)
1636                 return hdlc_ioctl(dev, ifr, cmd);
1637 
1638         memset(&new_line, 0, sizeof(new_line));
1639 
1640         switch(ifr->ifr_settings.type) {
1641         case IF_GET_IFACE: /* return current sync_serial_settings */
1642 
1643                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1644                 if (ifr->ifr_settings.size < size) {
1645                         ifr->ifr_settings.size = size; /* data size wanted */
1646                         return -ENOBUFS;
1647                 }
1648 
1649                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1650                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1651                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1652                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1653 
1654                 switch (flags){
1655                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1656                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1657                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1658                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1659                 default: new_line.clock_type = CLOCK_DEFAULT;
1660                 }
1661 
1662                 new_line.clock_rate = info->params.clock_speed;
1663                 new_line.loopback   = info->params.loopback ? 1:0;
1664 
1665                 if (copy_to_user(line, &new_line, size))
1666                         return -EFAULT;
1667                 return 0;
1668 
1669         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1670 
1671                 if(!capable(CAP_NET_ADMIN))
1672                         return -EPERM;
1673                 if (copy_from_user(&new_line, line, size))
1674                         return -EFAULT;
1675 
1676                 switch (new_line.clock_type)
1677                 {
1678                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1679                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1680                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1681                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1682                 case CLOCK_DEFAULT:  flags = info->params.flags &
1683                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1684                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1685                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1686                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1687                 default: return -EINVAL;
1688                 }
1689 
1690                 if (new_line.loopback != 0 && new_line.loopback != 1)
1691                         return -EINVAL;
1692 
1693                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1694                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1695                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1696                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1697                 info->params.flags |= flags;
1698 
1699                 info->params.loopback = new_line.loopback;
1700 
1701                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1702                         info->params.clock_speed = new_line.clock_rate;
1703                 else
1704                         info->params.clock_speed = 0;
1705 
1706                 /* if network interface up, reprogram hardware */
1707                 if (info->netcount)
1708                         program_hw(info);
1709                 return 0;
1710 
1711         default:
1712                 return hdlc_ioctl(dev, ifr, cmd);
1713         }
1714 }
1715 
1716 /**
1717  * called by network layer when transmit timeout is detected
1718  *
1719  * dev  pointer to network device structure
1720  */
1721 static void hdlcdev_tx_timeout(struct net_device *dev)
1722 {
1723         struct slgt_info *info = dev_to_port(dev);
1724         unsigned long flags;
1725 
1726         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1727 
1728         dev->stats.tx_errors++;
1729         dev->stats.tx_aborted_errors++;
1730 
1731         spin_lock_irqsave(&info->lock,flags);
1732         tx_stop(info);
1733         spin_unlock_irqrestore(&info->lock,flags);
1734 
1735         netif_wake_queue(dev);
1736 }
1737 
1738 /**
1739  * called by device driver when transmit completes
1740  * reenable network layer transmit if stopped
1741  *
1742  * info  pointer to device instance information
1743  */
1744 static void hdlcdev_tx_done(struct slgt_info *info)
1745 {
1746         if (netif_queue_stopped(info->netdev))
1747                 netif_wake_queue(info->netdev);
1748 }
1749 
1750 /**
1751  * called by device driver when frame received
1752  * pass frame to network layer
1753  *
1754  * info  pointer to device instance information
1755  * buf   pointer to buffer contianing frame data
1756  * size  count of data bytes in buf
1757  */
1758 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1759 {
1760         struct sk_buff *skb = dev_alloc_skb(size);
1761         struct net_device *dev = info->netdev;
1762 
1763         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1764 
1765         if (skb == NULL) {
1766                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1767                 dev->stats.rx_dropped++;
1768                 return;
1769         }
1770 
1771         memcpy(skb_put(skb, size), buf, size);
1772 
1773         skb->protocol = hdlc_type_trans(skb, dev);
1774 
1775         dev->stats.rx_packets++;
1776         dev->stats.rx_bytes += size;
1777 
1778         netif_rx(skb);
1779 }
1780 
1781 static const struct net_device_ops hdlcdev_ops = {
1782         .ndo_open       = hdlcdev_open,
1783         .ndo_stop       = hdlcdev_close,
1784         .ndo_change_mtu = hdlc_change_mtu,
1785         .ndo_start_xmit = hdlc_start_xmit,
1786         .ndo_do_ioctl   = hdlcdev_ioctl,
1787         .ndo_tx_timeout = hdlcdev_tx_timeout,
1788 };
1789 
1790 /**
1791  * called by device driver when adding device instance
1792  * do generic HDLC initialization
1793  *
1794  * info  pointer to device instance information
1795  *
1796  * returns 0 if success, otherwise error code
1797  */
1798 static int hdlcdev_init(struct slgt_info *info)
1799 {
1800         int rc;
1801         struct net_device *dev;
1802         hdlc_device *hdlc;
1803 
1804         /* allocate and initialize network and HDLC layer objects */
1805 
1806         if (!(dev = alloc_hdlcdev(info))) {
1807                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1808                 return -ENOMEM;
1809         }
1810 
1811         /* for network layer reporting purposes only */
1812         dev->mem_start = info->phys_reg_addr;
1813         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1814         dev->irq       = info->irq_level;
1815 
1816         /* network layer callbacks and settings */
1817         dev->netdev_ops     = &hdlcdev_ops;
1818         dev->watchdog_timeo = 10 * HZ;
1819         dev->tx_queue_len   = 50;
1820 
1821         /* generic HDLC layer callbacks and settings */
1822         hdlc         = dev_to_hdlc(dev);
1823         hdlc->attach = hdlcdev_attach;
1824         hdlc->xmit   = hdlcdev_xmit;
1825 
1826         /* register objects with HDLC layer */
1827         if ((rc = register_hdlc_device(dev))) {
1828                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1829                 free_netdev(dev);
1830                 return rc;
1831         }
1832 
1833         info->netdev = dev;
1834         return 0;
1835 }
1836 
1837 /**
1838  * called by device driver when removing device instance
1839  * do generic HDLC cleanup
1840  *
1841  * info  pointer to device instance information
1842  */
1843 static void hdlcdev_exit(struct slgt_info *info)
1844 {
1845         unregister_hdlc_device(info->netdev);
1846         free_netdev(info->netdev);
1847         info->netdev = NULL;
1848 }
1849 
1850 #endif /* ifdef CONFIG_HDLC */
1851 
1852 /*
1853  * get async data from rx DMA buffers
1854  */
1855 static void rx_async(struct slgt_info *info)
1856 {
1857         struct mgsl_icount *icount = &info->icount;
1858         unsigned int start, end;
1859         unsigned char *p;
1860         unsigned char status;
1861         struct slgt_desc *bufs = info->rbufs;
1862         int i, count;
1863         int chars = 0;
1864         int stat;
1865         unsigned char ch;
1866 
1867         start = end = info->rbuf_current;
1868 
1869         while(desc_complete(bufs[end])) {
1870                 count = desc_count(bufs[end]) - info->rbuf_index;
1871                 p     = bufs[end].buf + info->rbuf_index;
1872 
1873                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1874                 DBGDATA(info, p, count, "rx");
1875 
1876                 for(i=0 ; i < count; i+=2, p+=2) {
1877                         ch = *p;
1878                         icount->rx++;
1879 
1880                         stat = 0;
1881 
1882                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1883                                 if (status & BIT1)
1884                                         icount->parity++;
1885                                 else if (status & BIT0)
1886                                         icount->frame++;
1887                                 /* discard char if tty control flags say so */
1888                                 if (status & info->ignore_status_mask)
1889                                         continue;
1890                                 if (status & BIT1)
1891                                         stat = TTY_PARITY;
1892                                 else if (status & BIT0)
1893                                         stat = TTY_FRAME;
1894                         }
1895                         tty_insert_flip_char(&info->port, ch, stat);
1896                         chars++;
1897                 }
1898 
1899                 if (i < count) {
1900                         /* receive buffer not completed */
1901                         info->rbuf_index += i;
1902                         mod_timer(&info->rx_timer, jiffies + 1);
1903                         break;
1904                 }
1905 
1906                 info->rbuf_index = 0;
1907                 free_rbufs(info, end, end);
1908 
1909                 if (++end == info->rbuf_count)
1910                         end = 0;
1911 
1912                 /* if entire list searched then no frame available */
1913                 if (end == start)
1914                         break;
1915         }
1916 
1917         if (chars)
1918                 tty_flip_buffer_push(&info->port);
1919 }
1920 
1921 /*
1922  * return next bottom half action to perform
1923  */
1924 static int bh_action(struct slgt_info *info)
1925 {
1926         unsigned long flags;
1927         int rc;
1928 
1929         spin_lock_irqsave(&info->lock,flags);
1930 
1931         if (info->pending_bh & BH_RECEIVE) {
1932                 info->pending_bh &= ~BH_RECEIVE;
1933                 rc = BH_RECEIVE;
1934         } else if (info->pending_bh & BH_TRANSMIT) {
1935                 info->pending_bh &= ~BH_TRANSMIT;
1936                 rc = BH_TRANSMIT;
1937         } else if (info->pending_bh & BH_STATUS) {
1938                 info->pending_bh &= ~BH_STATUS;
1939                 rc = BH_STATUS;
1940         } else {
1941                 /* Mark BH routine as complete */
1942                 info->bh_running = false;
1943                 info->bh_requested = false;
1944                 rc = 0;
1945         }
1946 
1947         spin_unlock_irqrestore(&info->lock,flags);
1948 
1949         return rc;
1950 }
1951 
1952 /*
1953  * perform bottom half processing
1954  */
1955 static void bh_handler(struct work_struct *work)
1956 {
1957         struct slgt_info *info = container_of(work, struct slgt_info, task);
1958         int action;
1959 
1960         info->bh_running = true;
1961 
1962         while((action = bh_action(info))) {
1963                 switch (action) {
1964                 case BH_RECEIVE:
1965                         DBGBH(("%s bh receive\n", info->device_name));
1966                         switch(info->params.mode) {
1967                         case MGSL_MODE_ASYNC:
1968                                 rx_async(info);
1969                                 break;
1970                         case MGSL_MODE_HDLC:
1971                                 while(rx_get_frame(info));
1972                                 break;
1973                         case MGSL_MODE_RAW:
1974                         case MGSL_MODE_MONOSYNC:
1975                         case MGSL_MODE_BISYNC:
1976                         case MGSL_MODE_XSYNC:
1977                                 while(rx_get_buf(info));
1978                                 break;
1979                         }
1980                         /* restart receiver if rx DMA buffers exhausted */
1981                         if (info->rx_restart)
1982                                 rx_start(info);
1983                         break;
1984                 case BH_TRANSMIT:
1985                         bh_transmit(info);
1986                         break;
1987                 case BH_STATUS:
1988                         DBGBH(("%s bh status\n", info->device_name));
1989                         info->ri_chkcount = 0;
1990                         info->dsr_chkcount = 0;
1991                         info->dcd_chkcount = 0;
1992                         info->cts_chkcount = 0;
1993                         break;
1994                 default:
1995                         DBGBH(("%s unknown action\n", info->device_name));
1996                         break;
1997                 }
1998         }
1999         DBGBH(("%s bh_handler exit\n", info->device_name));
2000 }
2001 
2002 static void bh_transmit(struct slgt_info *info)
2003 {
2004         struct tty_struct *tty = info->port.tty;
2005 
2006         DBGBH(("%s bh_transmit\n", info->device_name));
2007         if (tty)
2008                 tty_wakeup(tty);
2009 }
2010 
2011 static void dsr_change(struct slgt_info *info, unsigned short status)
2012 {
2013         if (status & BIT3) {
2014                 info->signals |= SerialSignal_DSR;
2015                 info->input_signal_events.dsr_up++;
2016         } else {
2017                 info->signals &= ~SerialSignal_DSR;
2018                 info->input_signal_events.dsr_down++;
2019         }
2020         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2021         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2022                 slgt_irq_off(info, IRQ_DSR);
2023                 return;
2024         }
2025         info->icount.dsr++;
2026         wake_up_interruptible(&info->status_event_wait_q);
2027         wake_up_interruptible(&info->event_wait_q);
2028         info->pending_bh |= BH_STATUS;
2029 }
2030 
2031 static void cts_change(struct slgt_info *info, unsigned short status)
2032 {
2033         if (status & BIT2) {
2034                 info->signals |= SerialSignal_CTS;
2035                 info->input_signal_events.cts_up++;
2036         } else {
2037                 info->signals &= ~SerialSignal_CTS;
2038                 info->input_signal_events.cts_down++;
2039         }
2040         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2041         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2042                 slgt_irq_off(info, IRQ_CTS);
2043                 return;
2044         }
2045         info->icount.cts++;
2046         wake_up_interruptible(&info->status_event_wait_q);
2047         wake_up_interruptible(&info->event_wait_q);
2048         info->pending_bh |= BH_STATUS;
2049 
2050         if (tty_port_cts_enabled(&info->port)) {
2051                 if (info->port.tty) {
2052                         if (info->port.tty->hw_stopped) {
2053                                 if (info->signals & SerialSignal_CTS) {
2054                                         info->port.tty->hw_stopped = 0;
2055                                         info->pending_bh |= BH_TRANSMIT;
2056                                         return;
2057                                 }
2058                         } else {
2059                                 if (!(info->signals & SerialSignal_CTS))
2060                                         info->port.tty->hw_stopped = 1;
2061                         }
2062                 }
2063         }
2064 }
2065 
2066 static void dcd_change(struct slgt_info *info, unsigned short status)
2067 {
2068         if (status & BIT1) {
2069                 info->signals |= SerialSignal_DCD;
2070                 info->input_signal_events.dcd_up++;
2071         } else {
2072                 info->signals &= ~SerialSignal_DCD;
2073                 info->input_signal_events.dcd_down++;
2074         }
2075         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2076         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2077                 slgt_irq_off(info, IRQ_DCD);
2078                 return;
2079         }
2080         info->icount.dcd++;
2081 #if SYNCLINK_GENERIC_HDLC
2082         if (info->netcount) {
2083                 if (info->signals & SerialSignal_DCD)
2084                         netif_carrier_on(info->netdev);
2085                 else
2086                         netif_carrier_off(info->netdev);
2087         }
2088 #endif
2089         wake_up_interruptible(&info->status_event_wait_q);
2090         wake_up_interruptible(&info->event_wait_q);
2091         info->pending_bh |= BH_STATUS;
2092 
2093         if (info->port.flags & ASYNC_CHECK_CD) {
2094                 if (info->signals & SerialSignal_DCD)
2095                         wake_up_interruptible(&info->port.open_wait);
2096                 else {
2097                         if (info->port.tty)
2098                                 tty_hangup(info->port.tty);
2099                 }
2100         }
2101 }
2102 
2103 static void ri_change(struct slgt_info *info, unsigned short status)
2104 {
2105         if (status & BIT0) {
2106                 info->signals |= SerialSignal_RI;
2107                 info->input_signal_events.ri_up++;
2108         } else {
2109                 info->signals &= ~SerialSignal_RI;
2110                 info->input_signal_events.ri_down++;
2111         }
2112         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2113         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2114                 slgt_irq_off(info, IRQ_RI);
2115                 return;
2116         }
2117         info->icount.rng++;
2118         wake_up_interruptible(&info->status_event_wait_q);
2119         wake_up_interruptible(&info->event_wait_q);
2120         info->pending_bh |= BH_STATUS;
2121 }
2122 
2123 static void isr_rxdata(struct slgt_info *info)
2124 {
2125         unsigned int count = info->rbuf_fill_count;
2126         unsigned int i = info->rbuf_fill_index;
2127         unsigned short reg;
2128 
2129         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2130                 reg = rd_reg16(info, RDR);
2131                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2132                 if (desc_complete(info->rbufs[i])) {
2133                         /* all buffers full */
2134                         rx_stop(info);
2135                         info->rx_restart = 1;
2136                         continue;
2137                 }
2138                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2139                 /* async mode saves status byte to buffer for each data byte */
2140                 if (info->params.mode == MGSL_MODE_ASYNC)
2141                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2142                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2143                         /* buffer full or end of frame */
2144                         set_desc_count(info->rbufs[i], count);
2145                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2146                         info->rbuf_fill_count = count = 0;
2147                         if (++i == info->rbuf_count)
2148                                 i = 0;
2149                         info->pending_bh |= BH_RECEIVE;
2150                 }
2151         }
2152 
2153         info->rbuf_fill_index = i;
2154         info->rbuf_fill_count = count;
2155 }
2156 
2157 static void isr_serial(struct slgt_info *info)
2158 {
2159         unsigned short status = rd_reg16(info, SSR);
2160 
2161         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2162 
2163         wr_reg16(info, SSR, status); /* clear pending */
2164 
2165         info->irq_occurred = true;
2166 
2167         if (info->params.mode == MGSL_MODE_ASYNC) {
2168                 if (status & IRQ_TXIDLE) {
2169                         if (info->tx_active)
2170                                 isr_txeom(info, status);
2171                 }
2172                 if (info->rx_pio && (status & IRQ_RXDATA))
2173                         isr_rxdata(info);
2174                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2175                         info->icount.brk++;
2176                         /* process break detection if tty control allows */
2177                         if (info->port.tty) {
2178                                 if (!(status & info->ignore_status_mask)) {
2179                                         if (info->read_status_mask & MASK_BREAK) {
2180                                                 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2181                                                 if (info->port.flags & ASYNC_SAK)
2182                                                         do_SAK(info->port.tty);
2183                                         }
2184                                 }
2185                         }
2186                 }
2187         } else {
2188                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2189                         isr_txeom(info, status);
2190                 if (info->rx_pio && (status & IRQ_RXDATA))
2191                         isr_rxdata(info);
2192                 if (status & IRQ_RXIDLE) {
2193                         if (status & RXIDLE)
2194                                 info->icount.rxidle++;
2195                         else
2196                                 info->icount.exithunt++;
2197                         wake_up_interruptible(&info->event_wait_q);
2198                 }
2199 
2200                 if (status & IRQ_RXOVER)
2201                         rx_start(info);
2202         }
2203 
2204         if (status & IRQ_DSR)
2205                 dsr_change(info, status);
2206         if (status & IRQ_CTS)
2207                 cts_change(info, status);
2208         if (status & IRQ_DCD)
2209                 dcd_change(info, status);
2210         if (status & IRQ_RI)
2211                 ri_change(info, status);
2212 }
2213 
2214 static void isr_rdma(struct slgt_info *info)
2215 {
2216         unsigned int status = rd_reg32(info, RDCSR);
2217 
2218         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2219 
2220         /* RDCSR (rx DMA control/status)
2221          *
2222          * 31..07  reserved
2223          * 06      save status byte to DMA buffer
2224          * 05      error
2225          * 04      eol (end of list)
2226          * 03      eob (end of buffer)
2227          * 02      IRQ enable
2228          * 01      reset
2229          * 00      enable
2230          */
2231         wr_reg32(info, RDCSR, status);  /* clear pending */
2232 
2233         if (status & (BIT5 + BIT4)) {
2234                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2235                 info->rx_restart = true;
2236         }
2237         info->pending_bh |= BH_RECEIVE;
2238 }
2239 
2240 static void isr_tdma(struct slgt_info *info)
2241 {
2242         unsigned int status = rd_reg32(info, TDCSR);
2243 
2244         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2245 
2246         /* TDCSR (tx DMA control/status)
2247          *
2248          * 31..06  reserved
2249          * 05      error
2250          * 04      eol (end of list)
2251          * 03      eob (end of buffer)
2252          * 02      IRQ enable
2253          * 01      reset
2254          * 00      enable
2255          */
2256         wr_reg32(info, TDCSR, status);  /* clear pending */
2257 
2258         if (status & (BIT5 + BIT4 + BIT3)) {
2259                 // another transmit buffer has completed
2260                 // run bottom half to get more send data from user
2261                 info->pending_bh |= BH_TRANSMIT;
2262         }
2263 }
2264 
2265 /*
2266  * return true if there are unsent tx DMA buffers, otherwise false
2267  *
2268  * if there are unsent buffers then info->tbuf_start
2269  * is set to index of first unsent buffer
2270  */
2271 static bool unsent_tbufs(struct slgt_info *info)
2272 {
2273         unsigned int i = info->tbuf_current;
2274         bool rc = false;
2275 
2276         /*
2277          * search backwards from last loaded buffer (precedes tbuf_current)
2278          * for first unsent buffer (desc_count > 0)
2279          */
2280 
2281         do {
2282                 if (i)
2283                         i--;
2284                 else
2285                         i = info->tbuf_count - 1;
2286                 if (!desc_count(info->tbufs[i]))
2287                         break;
2288                 info->tbuf_start = i;
2289                 rc = true;
2290         } while (i != info->tbuf_current);
2291 
2292         return rc;
2293 }
2294 
2295 static void isr_txeom(struct slgt_info *info, unsigned short status)
2296 {
2297         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2298 
2299         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2300         tdma_reset(info);
2301         if (status & IRQ_TXUNDER) {
2302                 unsigned short val = rd_reg16(info, TCR);
2303                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2304                 wr_reg16(info, TCR, val); /* clear reset bit */
2305         }
2306 
2307         if (info->tx_active) {
2308                 if (info->params.mode != MGSL_MODE_ASYNC) {
2309                         if (status & IRQ_TXUNDER)
2310                                 info->icount.txunder++;
2311                         else if (status & IRQ_TXIDLE)
2312                                 info->icount.txok++;
2313                 }
2314 
2315                 if (unsent_tbufs(info)) {
2316                         tx_start(info);
2317                         update_tx_timer(info);
2318                         return;
2319                 }
2320                 info->tx_active = false;
2321 
2322                 del_timer(&info->tx_timer);
2323 
2324                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2325                         info->signals &= ~SerialSignal_RTS;
2326                         info->drop_rts_on_tx_done = false;
2327                         set_signals(info);
2328                 }
2329 
2330 #if SYNCLINK_GENERIC_HDLC
2331                 if (info->netcount)
2332                         hdlcdev_tx_done(info);
2333                 else
2334 #endif
2335                 {
2336                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2337                                 tx_stop(info);
2338                                 return;
2339                         }
2340                         info->pending_bh |= BH_TRANSMIT;
2341                 }
2342         }
2343 }
2344 
2345 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2346 {
2347         struct cond_wait *w, *prev;
2348 
2349         /* wake processes waiting for specific transitions */
2350         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2351                 if (w->data & changed) {
2352                         w->data = state;
2353                         wake_up_interruptible(&w->q);
2354                         if (prev != NULL)
2355                                 prev->next = w->next;
2356                         else
2357                                 info->gpio_wait_q = w->next;
2358                 } else
2359                         prev = w;
2360         }
2361 }
2362 
2363 /* interrupt service routine
2364  *
2365  *      irq     interrupt number
2366  *      dev_id  device ID supplied during interrupt registration
2367  */
2368 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2369 {
2370         struct slgt_info *info = dev_id;
2371         unsigned int gsr;
2372         unsigned int i;
2373 
2374         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2375 
2376         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2377                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2378                 info->irq_occurred = true;
2379                 for(i=0; i < info->port_count ; i++) {
2380                         if (info->port_array[i] == NULL)
2381                                 continue;
2382                         spin_lock(&info->port_array[i]->lock);
2383                         if (gsr & (BIT8 << i))
2384                                 isr_serial(info->port_array[i]);
2385                         if (gsr & (BIT16 << (i*2)))
2386                                 isr_rdma(info->port_array[i]);
2387                         if (gsr & (BIT17 << (i*2)))
2388                                 isr_tdma(info->port_array[i]);
2389                         spin_unlock(&info->port_array[i]->lock);
2390                 }
2391         }
2392 
2393         if (info->gpio_present) {
2394                 unsigned int state;
2395                 unsigned int changed;
2396                 spin_lock(&info->lock);
2397                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2398                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2399                         /* read latched state of GPIO signals */
2400                         state = rd_reg32(info, IOVR);
2401                         /* clear pending GPIO interrupt bits */
2402                         wr_reg32(info, IOSR, changed);
2403                         for (i=0 ; i < info->port_count ; i++) {
2404                                 if (info->port_array[i] != NULL)
2405                                         isr_gpio(info->port_array[i], changed, state);
2406                         }
2407                 }
2408                 spin_unlock(&info->lock);
2409         }
2410 
2411         for(i=0; i < info->port_count ; i++) {
2412                 struct slgt_info *port = info->port_array[i];
2413                 if (port == NULL)
2414                         continue;
2415                 spin_lock(&port->lock);
2416                 if ((port->port.count || port->netcount) &&
2417                     port->pending_bh && !port->bh_running &&
2418                     !port->bh_requested) {
2419                         DBGISR(("%s bh queued\n", port->device_name));
2420                         schedule_work(&port->task);
2421                         port->bh_requested = true;
2422                 }
2423                 spin_unlock(&port->lock);
2424         }
2425 
2426         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2427         return IRQ_HANDLED;
2428 }
2429 
2430 static int startup(struct slgt_info *info)
2431 {
2432         DBGINFO(("%s startup\n", info->device_name));
2433 
2434         if (info->port.flags & ASYNC_INITIALIZED)
2435                 return 0;
2436 
2437         if (!info->tx_buf) {
2438                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2439                 if (!info->tx_buf) {
2440                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2441                         return -ENOMEM;
2442                 }
2443         }
2444 
2445         info->pending_bh = 0;
2446 
2447         memset(&info->icount, 0, sizeof(info->icount));
2448 
2449         /* program hardware for current parameters */
2450         change_params(info);
2451 
2452         if (info->port.tty)
2453                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2454 
2455         info->port.flags |= ASYNC_INITIALIZED;
2456 
2457         return 0;
2458 }
2459 
2460 /*
2461  *  called by close() and hangup() to shutdown hardware
2462  */
2463 static void shutdown(struct slgt_info *info)
2464 {
2465         unsigned long flags;
2466 
2467         if (!(info->port.flags & ASYNC_INITIALIZED))
2468                 return;
2469 
2470         DBGINFO(("%s shutdown\n", info->device_name));
2471 
2472         /* clear status wait queue because status changes */
2473         /* can't happen after shutting down the hardware */
2474         wake_up_interruptible(&info->status_event_wait_q);
2475         wake_up_interruptible(&info->event_wait_q);
2476 
2477         del_timer_sync(&info->tx_timer);
2478         del_timer_sync(&info->rx_timer);
2479 
2480         kfree(info->tx_buf);
2481         info->tx_buf = NULL;
2482 
2483         spin_lock_irqsave(&info->lock,flags);
2484 
2485         tx_stop(info);
2486         rx_stop(info);
2487 
2488         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2489 
2490         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2491                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2492                 set_signals(info);
2493         }
2494 
2495         flush_cond_wait(&info->gpio_wait_q);
2496 
2497         spin_unlock_irqrestore(&info->lock,flags);
2498 
2499         if (info->port.tty)
2500                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2501 
2502         info->port.flags &= ~ASYNC_INITIALIZED;
2503 }
2504 
2505 static void program_hw(struct slgt_info *info)
2506 {
2507         unsigned long flags;
2508 
2509         spin_lock_irqsave(&info->lock,flags);
2510 
2511         rx_stop(info);
2512         tx_stop(info);
2513 
2514         if (info->params.mode != MGSL_MODE_ASYNC ||
2515             info->netcount)
2516                 sync_mode(info);
2517         else
2518                 async_mode(info);
2519 
2520         set_signals(info);
2521 
2522         info->dcd_chkcount = 0;
2523         info->cts_chkcount = 0;
2524         info->ri_chkcount = 0;
2525         info->dsr_chkcount = 0;
2526 
2527         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2528         get_signals(info);
2529 
2530         if (info->netcount ||
2531             (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2532                 rx_start(info);
2533 
2534         spin_unlock_irqrestore(&info->lock,flags);
2535 }
2536 
2537 /*
2538  * reconfigure adapter based on new parameters
2539  */
2540 static void change_params(struct slgt_info *info)
2541 {
2542         unsigned cflag;
2543         int bits_per_char;
2544 
2545         if (!info->port.tty)
2546                 return;
2547         DBGINFO(("%s change_params\n", info->device_name));
2548 
2549         cflag = info->port.tty->termios.c_cflag;
2550 
2551         /* if B0 rate (hangup) specified then negate RTS and DTR */
2552         /* otherwise assert RTS and DTR */
2553         if (cflag & CBAUD)
2554                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2555         else
2556                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2557 
2558         /* byte size and parity */
2559 
2560         switch (cflag & CSIZE) {
2561         case CS5: info->params.data_bits = 5; break;
2562         case CS6: info->params.data_bits = 6; break;
2563         case CS7: info->params.data_bits = 7; break;
2564         case CS8: info->params.data_bits = 8; break;
2565         default:  info->params.data_bits = 7; break;
2566         }
2567 
2568         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2569 
2570         if (cflag & PARENB)
2571                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2572         else
2573                 info->params.parity = ASYNC_PARITY_NONE;
2574 
2575         /* calculate number of jiffies to transmit a full
2576          * FIFO (32 bytes) at specified data rate
2577          */
2578         bits_per_char = info->params.data_bits +
2579                         info->params.stop_bits + 1;
2580 
2581         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2582 
2583         if (info->params.data_rate) {
2584                 info->timeout = (32*HZ*bits_per_char) /
2585                                 info->params.data_rate;
2586         }
2587         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2588 
2589         if (cflag & CRTSCTS)
2590                 info->port.flags |= ASYNC_CTS_FLOW;
2591         else
2592                 info->port.flags &= ~ASYNC_CTS_FLOW;
2593 
2594         if (cflag & CLOCAL)
2595                 info->port.flags &= ~ASYNC_CHECK_CD;
2596         else
2597                 info->port.flags |= ASYNC_CHECK_CD;
2598 
2599         /* process tty input control flags */
2600 
2601         info->read_status_mask = IRQ_RXOVER;
2602         if (I_INPCK(info->port.tty))
2603                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2604         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2605                 info->read_status_mask |= MASK_BREAK;
2606         if (I_IGNPAR(info->port.tty))
2607                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2608         if (I_IGNBRK(info->port.tty)) {
2609                 info->ignore_status_mask |= MASK_BREAK;
2610                 /* If ignoring parity and break indicators, ignore
2611                  * overruns too.  (For real raw support).
2612                  */
2613                 if (I_IGNPAR(info->port.tty))
2614                         info->ignore_status_mask |= MASK_OVERRUN;
2615         }
2616 
2617         program_hw(info);
2618 }
2619 
2620 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2621 {
2622         DBGINFO(("%s get_stats\n",  info->device_name));
2623         if (!user_icount) {
2624                 memset(&info->icount, 0, sizeof(info->icount));
2625         } else {
2626                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2627                         return -EFAULT;
2628         }
2629         return 0;
2630 }
2631 
2632 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2633 {
2634         DBGINFO(("%s get_params\n", info->device_name));
2635         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2636                 return -EFAULT;
2637         return 0;
2638 }
2639 
2640 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2641 {
2642         unsigned long flags;
2643         MGSL_PARAMS tmp_params;
2644 
2645         DBGINFO(("%s set_params\n", info->device_name));
2646         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2647                 return -EFAULT;
2648 
2649         spin_lock_irqsave(&info->lock, flags);
2650         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2651                 info->base_clock = tmp_params.clock_speed;
2652         else
2653                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2654         spin_unlock_irqrestore(&info->lock, flags);
2655 
2656         program_hw(info);
2657 
2658         return 0;
2659 }
2660 
2661 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2662 {
2663         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2664         if (put_user(info->idle_mode, idle_mode))
2665                 return -EFAULT;
2666         return 0;
2667 }
2668 
2669 static int set_txidle(struct slgt_info *info, int idle_mode)
2670 {
2671         unsigned long flags;
2672         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2673         spin_lock_irqsave(&info->lock,flags);
2674         info->idle_mode = idle_mode;
2675         if (info->params.mode != MGSL_MODE_ASYNC)
2676                 tx_set_idle(info);
2677         spin_unlock_irqrestore(&info->lock,flags);
2678         return 0;
2679 }
2680 
2681 static int tx_enable(struct slgt_info *info, int enable)
2682 {
2683         unsigned long flags;
2684         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2685         spin_lock_irqsave(&info->lock,flags);
2686         if (enable) {
2687                 if (!info->tx_enabled)
2688                         tx_start(info);
2689         } else {
2690                 if (info->tx_enabled)
2691                         tx_stop(info);
2692         }
2693         spin_unlock_irqrestore(&info->lock,flags);
2694         return 0;
2695 }
2696 
2697 /*
2698  * abort transmit HDLC frame
2699  */
2700 static int tx_abort(struct slgt_info *info)
2701 {
2702         unsigned long flags;
2703         DBGINFO(("%s tx_abort\n", info->device_name));
2704         spin_lock_irqsave(&info->lock,flags);
2705         tdma_reset(info);
2706         spin_unlock_irqrestore(&info->lock,flags);
2707         return 0;
2708 }
2709 
2710 static int rx_enable(struct slgt_info *info, int enable)
2711 {
2712         unsigned long flags;
2713         unsigned int rbuf_fill_level;
2714         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2715         spin_lock_irqsave(&info->lock,flags);
2716         /*
2717          * enable[31..16] = receive DMA buffer fill level
2718          * 0 = noop (leave fill level unchanged)
2719          * fill level must be multiple of 4 and <= buffer size
2720          */
2721         rbuf_fill_level = ((unsigned int)enable) >> 16;
2722         if (rbuf_fill_level) {
2723                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2724                         spin_unlock_irqrestore(&info->lock, flags);
2725                         return -EINVAL;
2726                 }
2727                 info->rbuf_fill_level = rbuf_fill_level;
2728                 if (rbuf_fill_level < 128)
2729                         info->rx_pio = 1; /* PIO mode */
2730                 else
2731                         info->rx_pio = 0; /* DMA mode */
2732                 rx_stop(info); /* restart receiver to use new fill level */
2733         }
2734 
2735         /*
2736          * enable[1..0] = receiver enable command
2737          * 0 = disable
2738          * 1 = enable
2739          * 2 = enable or force hunt mode if already enabled
2740          */
2741         enable &= 3;
2742         if (enable) {
2743                 if (!info->rx_enabled)
2744                         rx_start(info);
2745                 else if (enable == 2) {
2746                         /* force hunt mode (write 1 to RCR[3]) */
2747                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2748                 }
2749         } else {
2750                 if (info->rx_enabled)
2751                         rx_stop(info);
2752         }
2753         spin_unlock_irqrestore(&info->lock,flags);
2754         return 0;
2755 }
2756 
2757 /*
2758  *  wait for specified event to occur
2759  */
2760 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2761 {
2762         unsigned long flags;
2763         int s;
2764         int rc=0;
2765         struct mgsl_icount cprev, cnow;
2766         int events;
2767         int mask;
2768         struct  _input_signal_events oldsigs, newsigs;
2769         DECLARE_WAITQUEUE(wait, current);
2770 
2771         if (get_user(mask, mask_ptr))
2772                 return -EFAULT;
2773 
2774         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2775 
2776         spin_lock_irqsave(&info->lock,flags);
2777 
2778         /* return immediately if state matches requested events */
2779         get_signals(info);
2780         s = info->signals;
2781 
2782         events = mask &
2783                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2784                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2785                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2786                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2787         if (events) {
2788                 spin_unlock_irqrestore(&info->lock,flags);
2789                 goto exit;
2790         }
2791 
2792         /* save current irq counts */
2793         cprev = info->icount;
2794         oldsigs = info->input_signal_events;
2795 
2796         /* enable hunt and idle irqs if needed */
2797         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2798                 unsigned short val = rd_reg16(info, SCR);
2799                 if (!(val & IRQ_RXIDLE))
2800                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2801         }
2802 
2803         set_current_state(TASK_INTERRUPTIBLE);
2804         add_wait_queue(&info->event_wait_q, &wait);
2805 
2806         spin_unlock_irqrestore(&info->lock,flags);
2807 
2808         for(;;) {
2809                 schedule();
2810                 if (signal_pending(current)) {
2811                         rc = -ERESTARTSYS;
2812                         break;
2813                 }
2814 
2815                 /* get current irq counts */
2816                 spin_lock_irqsave(&info->lock,flags);
2817                 cnow = info->icount;
2818                 newsigs = info->input_signal_events;
2819                 set_current_state(TASK_INTERRUPTIBLE);
2820                 spin_unlock_irqrestore(&info->lock,flags);
2821 
2822                 /* if no change, wait aborted for some reason */
2823                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2824                     newsigs.dsr_down == oldsigs.dsr_down &&
2825                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2826                     newsigs.dcd_down == oldsigs.dcd_down &&
2827                     newsigs.cts_up   == oldsigs.cts_up   &&
2828                     newsigs.cts_down == oldsigs.cts_down &&
2829                     newsigs.ri_up    == oldsigs.ri_up    &&
2830                     newsigs.ri_down  == oldsigs.ri_down  &&
2831                     cnow.exithunt    == cprev.exithunt   &&
2832                     cnow.rxidle      == cprev.rxidle) {
2833                         rc = -EIO;
2834                         break;
2835                 }
2836 
2837                 events = mask &
2838                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2839                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2840                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2841                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2842                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2843                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2844                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2845                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2846                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2847                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2848                 if (events)
2849                         break;
2850 
2851                 cprev = cnow;
2852                 oldsigs = newsigs;
2853         }
2854 
2855         remove_wait_queue(&info->event_wait_q, &wait);
2856         set_current_state(TASK_RUNNING);
2857 
2858 
2859         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2860                 spin_lock_irqsave(&info->lock,flags);
2861                 if (!waitqueue_active(&info->event_wait_q)) {
2862                         /* disable enable exit hunt mode/idle rcvd IRQs */
2863                         wr_reg16(info, SCR,
2864                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2865                 }
2866                 spin_unlock_irqrestore(&info->lock,flags);
2867         }
2868 exit:
2869         if (rc == 0)
2870                 rc = put_user(events, mask_ptr);
2871         return rc;
2872 }
2873 
2874 static int get_interface(struct slgt_info *info, int __user *if_mode)
2875 {
2876         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2877         if (put_user(info->if_mode, if_mode))
2878                 return -EFAULT;
2879         return 0;
2880 }
2881 
2882 static int set_interface(struct slgt_info *info, int if_mode)
2883 {
2884         unsigned long flags;
2885         unsigned short val;
2886 
2887         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2888         spin_lock_irqsave(&info->lock,flags);
2889         info->if_mode = if_mode;
2890 
2891         msc_set_vcr(info);
2892 
2893         /* TCR (tx control) 07  1=RTS driver control */
2894         val = rd_reg16(info, TCR);
2895         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2896                 val |= BIT7;
2897         else
2898                 val &= ~BIT7;
2899         wr_reg16(info, TCR, val);
2900 
2901         spin_unlock_irqrestore(&info->lock,flags);
2902         return 0;
2903 }
2904 
2905 static int get_xsync(struct slgt_info *info, int __user *xsync)
2906 {
2907         DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2908         if (put_user(info->xsync, xsync))
2909                 return -EFAULT;
2910         return 0;
2911 }
2912 
2913 /*
2914  * set extended sync pattern (1 to 4 bytes) for extended sync mode
2915  *
2916  * sync pattern is contained in least significant bytes of value
2917  * most significant byte of sync pattern is oldest (1st sent/detected)
2918  */
2919 static int set_xsync(struct slgt_info *info, int xsync)
2920 {
2921         unsigned long flags;
2922 
2923         DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2924         spin_lock_irqsave(&info->lock, flags);
2925         info->xsync = xsync;
2926         wr_reg32(info, XSR, xsync);
2927         spin_unlock_irqrestore(&info->lock, flags);
2928         return 0;
2929 }
2930 
2931 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2932 {
2933         DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2934         if (put_user(info->xctrl, xctrl))
2935                 return -EFAULT;
2936         return 0;
2937 }
2938 
2939 /*
2940  * set extended control options
2941  *
2942  * xctrl[31:19] reserved, must be zero
2943  * xctrl[18:17] extended sync pattern length in bytes
2944  *              00 = 1 byte  in xsr[7:0]
2945  *              01 = 2 bytes in xsr[15:0]
2946  *              10 = 3 bytes in xsr[23:0]
2947  *              11 = 4 bytes in xsr[31:0]
2948  * xctrl[16]    1 = enable terminal count, 0=disabled
2949  * xctrl[15:0]  receive terminal count for fixed length packets
2950  *              value is count minus one (0 = 1 byte packet)
2951  *              when terminal count is reached, receiver
2952  *              automatically returns to hunt mode and receive
2953  *              FIFO contents are flushed to DMA buffers with
2954  *              end of frame (EOF) status
2955  */
2956 static int set_xctrl(struct slgt_info *info, int xctrl)
2957 {
2958         unsigned long flags;
2959 
2960         DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2961         spin_lock_irqsave(&info->lock, flags);
2962         info->xctrl = xctrl;
2963         wr_reg32(info, XCR, xctrl);
2964         spin_unlock_irqrestore(&info->lock, flags);
2965         return 0;
2966 }
2967 
2968 /*
2969  * set general purpose IO pin state and direction
2970  *
2971  * user_gpio fields:
2972  * state   each bit indicates a pin state
2973  * smask   set bit indicates pin state to set
2974  * dir     each bit indicates a pin direction (0=input, 1=output)
2975  * dmask   set bit indicates pin direction to set
2976  */
2977 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2978 {
2979         unsigned long flags;
2980         struct gpio_desc gpio;
2981         __u32 data;
2982 
2983         if (!info->gpio_present)
2984                 return -EINVAL;
2985         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2986                 return -EFAULT;
2987         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2988                  info->device_name, gpio.state, gpio.smask,
2989                  gpio.dir, gpio.dmask));
2990 
2991         spin_lock_irqsave(&info->port_array[0]->lock, flags);
2992         if (gpio.dmask) {
2993                 data = rd_reg32(info, IODR);
2994                 data |= gpio.dmask & gpio.dir;
2995                 data &= ~(gpio.dmask & ~gpio.dir);
2996                 wr_reg32(info, IODR, data);
2997         }
2998         if (gpio.smask) {
2999                 data = rd_reg32(info, IOVR);
3000                 data |= gpio.smask & gpio.state;
3001                 data &= ~(gpio.smask & ~gpio.state);
3002                 wr_reg32(info, IOVR, data);
3003         }
3004         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3005 
3006         return 0;
3007 }
3008 
3009 /*
3010  * get general purpose IO pin state and direction
3011  */
3012 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3013 {
3014         struct gpio_desc gpio;
3015         if (!info->gpio_present)
3016                 return -EINVAL;
3017         gpio.state = rd_reg32(info, IOVR);
3018         gpio.smask = 0xffffffff;
3019         gpio.dir   = rd_reg32(info, IODR);
3020         gpio.dmask = 0xffffffff;
3021         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3022                 return -EFAULT;
3023         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3024                  info->device_name, gpio.state, gpio.dir));
3025         return 0;
3026 }
3027 
3028 /*
3029  * conditional wait facility
3030  */
3031 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3032 {
3033         init_waitqueue_head(&w->q);
3034         init_waitqueue_entry(&w->wait, current);
3035         w->data = data;
3036 }
3037 
3038 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3039 {
3040         set_current_state(TASK_INTERRUPTIBLE);
3041         add_wait_queue(&w->q, &w->wait);
3042         w->next = *head;
3043         *head = w;
3044 }
3045 
3046 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3047 {
3048         struct cond_wait *w, *prev;
3049         remove_wait_queue(&cw->q, &cw->wait);
3050         set_current_state(TASK_RUNNING);
3051         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3052                 if (w == cw) {
3053                         if (prev != NULL)
3054                                 prev->next = w->next;
3055                         else
3056                                 *head = w->next;
3057                         break;
3058                 }
3059         }
3060 }
3061 
3062 static void flush_cond_wait(struct cond_wait **head)
3063 {
3064         while (*head != NULL) {
3065                 wake_up_interruptible(&(*head)->q);
3066                 *head = (*head)->next;
3067         }
3068 }
3069 
3070 /*
3071  * wait for general purpose I/O pin(s) to enter specified state
3072  *
3073  * user_gpio fields:
3074  * state - bit indicates target pin state
3075  * smask - set bit indicates watched pin
3076  *
3077  * The wait ends when at least one watched pin enters the specified
3078  * state. When 0 (no error) is returned, user_gpio->state is set to the
3079  * state of all GPIO pins when the wait ends.
3080  *
3081  * Note: Each pin may be a dedicated input, dedicated output, or
3082  * configurable input/output. The number and configuration of pins
3083  * varies with the specific adapter model. Only input pins (dedicated
3084  * or configured) can be monitored with this function.
3085  */
3086 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3087 {
3088         unsigned long flags;
3089         int rc = 0;
3090         struct gpio_desc gpio;
3091         struct cond_wait wait;
3092         u32 state;
3093 
3094         if (!info->gpio_present)
3095                 return -EINVAL;
3096         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3097                 return -EFAULT;
3098         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3099                  info->device_name, gpio.state, gpio.smask));
3100         /* ignore output pins identified by set IODR bit */
3101         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3102                 return -EINVAL;
3103         init_cond_wait(&wait, gpio.smask);
3104 
3105         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3106         /* enable interrupts for watched pins */
3107         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3108         /* get current pin states */
3109         state = rd_reg32(info, IOVR);
3110 
3111         if (gpio.smask & ~(state ^ gpio.state)) {
3112                 /* already in target state */
3113                 gpio.state = state;
3114         } else {
3115                 /* wait for target state */
3116                 add_cond_wait(&info->gpio_wait_q, &wait);
3117                 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3118                 schedule();
3119                 if (signal_pending(current))
3120                         rc = -ERESTARTSYS;
3121                 else
3122                         gpio.state = wait.data;
3123                 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3124                 remove_cond_wait(&info->gpio_wait_q, &wait);
3125         }
3126 
3127         /* disable all GPIO interrupts if no waiting processes */
3128         if (info->gpio_wait_q == NULL)
3129                 wr_reg32(info, IOER, 0);
3130         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3131 
3132         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3133                 rc = -EFAULT;
3134         return rc;
3135 }
3136 
3137 static int modem_input_wait(struct slgt_info *info,int arg)
3138 {
3139         unsigned long flags;
3140         int rc;
3141         struct mgsl_icount cprev, cnow;
3142         DECLARE_WAITQUEUE(wait, current);
3143 
3144         /* save current irq counts */
3145         spin_lock_irqsave(&info->lock,flags);
3146         cprev = info->icount;
3147         add_wait_queue(&info->status_event_wait_q, &wait);
3148         set_current_state(TASK_INTERRUPTIBLE);
3149         spin_unlock_irqrestore(&info->lock,flags);
3150 
3151         for(;;) {
3152                 schedule();
3153                 if (signal_pending(current)) {
3154                         rc = -ERESTARTSYS;
3155                         break;
3156                 }
3157 
3158                 /* get new irq counts */
3159                 spin_lock_irqsave(&info->lock,flags);
3160                 cnow = info->icount;
3161                 set_current_state(TASK_INTERRUPTIBLE);
3162                 spin_unlock_irqrestore(&info->lock,flags);
3163 
3164                 /* if no change, wait aborted for some reason */
3165                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3166                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3167                         rc = -EIO;
3168                         break;
3169                 }
3170 
3171                 /* check for change in caller specified modem input */
3172                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3173                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3174                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3175                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3176                         rc = 0;
3177                         break;
3178                 }
3179 
3180                 cprev = cnow;
3181         }
3182         remove_wait_queue(&info->status_event_wait_q, &wait);
3183         set_current_state(TASK_RUNNING);
3184         return rc;
3185 }
3186 
3187 /*
3188  *  return state of serial control and status signals
3189  */
3190 static int tiocmget(struct tty_struct *tty)
3191 {
3192         struct slgt_info *info = tty->driver_data;
3193         unsigned int result;
3194         unsigned long flags;
3195 
3196         spin_lock_irqsave(&info->lock,flags);
3197         get_signals(info);
3198         spin_unlock_irqrestore(&info->lock,flags);
3199 
3200         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3201                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3202                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3203                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3204                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3205                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3206 
3207         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3208         return result;
3209 }
3210 
3211 /*
3212  * set modem control signals (DTR/RTS)
3213  *
3214  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3215  *              TIOCMSET = set/clear signal values
3216  *      value   bit mask for command
3217  */
3218 static int tiocmset(struct tty_struct *tty,
3219                     unsigned int set, unsigned int clear)
3220 {
3221         struct slgt_info *info = tty->driver_data;
3222         unsigned long flags;
3223 
3224         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3225 
3226         if (set & TIOCM_RTS)
3227                 info->signals |= SerialSignal_RTS;
3228         if (set & TIOCM_DTR)
3229                 info->signals |= SerialSignal_DTR;
3230         if (clear & TIOCM_RTS)
3231                 info->signals &= ~SerialSignal_RTS;
3232         if (clear & TIOCM_DTR)
3233                 info->signals &= ~SerialSignal_DTR;
3234 
3235         spin_lock_irqsave(&info->lock,flags);
3236         set_signals(info);
3237         spin_unlock_irqrestore(&info->lock,flags);
3238         return 0;
3239 }
3240 
3241 static int carrier_raised(struct tty_port *port)
3242 {
3243         unsigned long flags;
3244         struct slgt_info *info = container_of(port, struct slgt_info, port);
3245 
3246         spin_lock_irqsave(&info->lock,flags);
3247         get_signals(info);
3248         spin_unlock_irqrestore(&info->lock,flags);
3249         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3250 }
3251 
3252 static void dtr_rts(struct tty_port *port, int on)
3253 {
3254         unsigned long flags;
3255         struct slgt_info *info = container_of(port, struct slgt_info, port);
3256 
3257         spin_lock_irqsave(&info->lock,flags);
3258         if (on)
3259                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3260         else
3261                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3262         set_signals(info);
3263         spin_unlock_irqrestore(&info->lock,flags);
3264 }
3265 
3266 
3267 /*
3268  *  block current process until the device is ready to open
3269  */
3270 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3271                            struct slgt_info *info)
3272 {
3273         DECLARE_WAITQUEUE(wait, current);
3274         int             retval;
3275         bool            do_clocal = false;
3276         unsigned long   flags;
3277         int             cd;
3278         struct tty_port *port = &info->port;
3279 
3280         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3281 
3282         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3283                 /* nonblock mode is set or port is not enabled */
3284                 port->flags |= ASYNC_NORMAL_ACTIVE;
3285                 return 0;
3286         }
3287 
3288         if (tty->termios.c_cflag & CLOCAL)
3289                 do_clocal = true;
3290 
3291         /* Wait for carrier detect and the line to become
3292          * free (i.e., not in use by the callout).  While we are in
3293          * this loop, port->count is dropped by one, so that
3294          * close() knows when to free things.  We restore it upon
3295          * exit, either normal or abnormal.
3296          */
3297 
3298         retval = 0;
3299         add_wait_queue(&port->open_wait, &wait);
3300 
3301         spin_lock_irqsave(&info->lock, flags);
3302         port->count--;
3303         spin_unlock_irqrestore(&info->lock, flags);
3304         port->blocked_open++;
3305 
3306         while (1) {
3307                 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3308                         tty_port_raise_dtr_rts(port);
3309 
3310                 set_current_state(TASK_INTERRUPTIBLE);
3311 
3312                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3313                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3314                                         -EAGAIN : -ERESTARTSYS;
3315                         break;
3316                 }
3317 
3318                 cd = tty_port_carrier_raised(port);
3319 
3320                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3321                         break;
3322 
3323                 if (signal_pending(current)) {
3324                         retval = -ERESTARTSYS;
3325                         break;
3326                 }
3327 
3328                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3329                 tty_unlock(tty);
3330                 schedule();
3331                 tty_lock(tty);
3332         }
3333 
3334         set_current_state(TASK_RUNNING);
3335         remove_wait_queue(&port->open_wait, &wait);
3336 
3337         if (!tty_hung_up_p(filp))
3338                 port->count++;
3339         port->blocked_open--;
3340 
3341         if (!retval)
3342                 port->flags |= ASYNC_NORMAL_ACTIVE;
3343 
3344         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3345         return retval;
3346 }
3347 
3348 /*
3349  * allocate buffers used for calling line discipline receive_buf
3350  * directly in synchronous mode
3351  * note: add 5 bytes to max frame size to allow appending
3352  * 32-bit CRC and status byte when configured to do so
3353  */
3354 static int alloc_tmp_rbuf(struct slgt_info *info)
3355 {
3356         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3357         if (info->tmp_rbuf == NULL)
3358                 return -ENOMEM;
3359         /* unused flag buffer to satisfy receive_buf calling interface */
3360         info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3361         if (!info->flag_buf) {
3362                 kfree(info->tmp_rbuf);
3363                 info->tmp_rbuf = NULL;
3364                 return -ENOMEM;
3365         }
3366         return 0;
3367 }
3368 
3369 static void free_tmp_rbuf(struct slgt_info *info)
3370 {
3371         kfree(info->tmp_rbuf);
3372         info->tmp_rbuf = NULL;
3373         kfree(info->flag_buf);
3374         info->flag_buf = NULL;
3375 }
3376 
3377 /*
3378  * allocate DMA descriptor lists.
3379  */
3380 static int alloc_desc(struct slgt_info *info)
3381 {
3382         unsigned int i;
3383         unsigned int pbufs;
3384 
3385         /* allocate memory to hold descriptor lists */
3386         info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3387                                            &info->bufs_dma_addr);
3388         if (info->bufs == NULL)
3389                 return -ENOMEM;
3390 
3391         info->rbufs = (struct slgt_desc*)info->bufs;
3392         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3393 
3394         pbufs = (unsigned int)info->bufs_dma_addr;
3395 
3396         /*
3397          * Build circular lists of descriptors
3398          */
3399 
3400         for (i=0; i < info->rbuf_count; i++) {
3401                 /* physical address of this descriptor */
3402                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3403 
3404                 /* physical address of next descriptor */
3405                 if (i == info->rbuf_count - 1)
3406                         info->rbufs[i].next = cpu_to_le32(pbufs);
3407                 else
3408                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3409                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3410         }
3411 
3412         for (i=0; i < info->tbuf_count; i++) {
3413                 /* physical address of this descriptor */
3414                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3415 
3416                 /* physical address of next descriptor */
3417                 if (i == info->tbuf_count - 1)
3418                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3419                 else
3420                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3421         }
3422 
3423         return 0;
3424 }
3425 
3426 static void free_desc(struct slgt_info *info)
3427 {
3428         if (info->bufs != NULL) {
3429                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3430                 info->bufs  = NULL;
3431                 info->rbufs = NULL;
3432                 info->tbufs = NULL;
3433         }
3434 }
3435 
3436 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3437 {
3438         int i;
3439         for (i=0; i < count; i++) {
3440                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3441                         return -ENOMEM;
3442                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3443         }
3444         return 0;
3445 }
3446 
3447 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3448 {
3449         int i;
3450         for (i=0; i < count; i++) {
3451                 if (bufs[i].buf == NULL)
3452                         continue;
3453                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3454                 bufs[i].buf = NULL;
3455         }
3456 }
3457 
3458 static int alloc_dma_bufs(struct slgt_info *info)
3459 {
3460         info->rbuf_count = 32;
3461         info->tbuf_count = 32;
3462 
3463         if (alloc_desc(info) < 0 ||
3464             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3465             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3466             alloc_tmp_rbuf(info) < 0) {
3467                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3468                 return -ENOMEM;
3469         }
3470         reset_rbufs(info);
3471         return 0;
3472 }
3473 
3474 static void free_dma_bufs(struct slgt_info *info)
3475 {
3476         if (info->bufs) {
3477                 free_bufs(info, info->rbufs, info->rbuf_count);
3478                 free_bufs(info, info->tbufs, info->tbuf_count);
3479                 free_desc(info);
3480         }
3481         free_tmp_rbuf(info);
3482 }
3483 
3484 static int claim_resources(struct slgt_info *info)
3485 {
3486         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3487                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3488                         info->device_name, info->phys_reg_addr));
3489                 info->init_error = DiagStatus_AddressConflict;
3490                 goto errout;
3491         }
3492         else
3493                 info->reg_addr_requested = true;
3494 
3495         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3496         if (!info->reg_addr) {
3497                 DBGERR(("%s can't map device registers, addr=%08X\n",
3498                         info->device_name, info->phys_reg_addr));
3499                 info->init_error = DiagStatus_CantAssignPciResources;
3500                 goto errout;
3501         }
3502         return 0;
3503 
3504 errout:
3505         release_resources(info);
3506         return -ENODEV;
3507 }
3508 
3509 static void release_resources(struct slgt_info *info)
3510 {
3511         if (info->irq_requested) {
3512                 free_irq(info->irq_level, info);
3513                 info->irq_requested = false;
3514         }
3515 
3516         if (info->reg_addr_requested) {
3517                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3518                 info->reg_addr_requested = false;
3519         }
3520 
3521         if (info->reg_addr) {
3522                 iounmap(info->reg_addr);
3523                 info->reg_addr = NULL;
3524         }
3525 }
3526 
3527 /* Add the specified device instance data structure to the
3528  * global linked list of devices and increment the device count.
3529  */
3530 static void add_device(struct slgt_info *info)
3531 {
3532         char *devstr;
3533 
3534         info->next_device = NULL;
3535         info->line = slgt_device_count;
3536         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3537 
3538         if (info->line < MAX_DEVICES) {
3539                 if (maxframe[info->line])
3540                         info->max_frame_size = maxframe[info->line];
3541         }
3542 
3543         slgt_device_count++;
3544 
3545         if (!slgt_device_list)
3546                 slgt_device_list = info;
3547         else {
3548                 struct slgt_info *current_dev = slgt_device_list;
3549                 while(current_dev->next_device)
3550                         current_dev = current_dev->next_device;
3551                 current_dev->next_device = info;
3552         }
3553 
3554         if (info->max_frame_size < 4096)
3555                 info->max_frame_size = 4096;
3556         else if (info->max_frame_size > 65535)
3557                 info->max_frame_size = 65535;
3558 
3559         switch(info->pdev->device) {
3560         case SYNCLINK_GT_DEVICE_ID:
3561                 devstr = "GT";
3562                 break;
3563         case SYNCLINK_GT2_DEVICE_ID:
3564                 devstr = "GT2";
3565                 break;
3566         case SYNCLINK_GT4_DEVICE_ID:
3567                 devstr = "GT4";
3568                 break;
3569         case SYNCLINK_AC_DEVICE_ID:
3570                 devstr = "AC";
3571                 info->params.mode = MGSL_MODE_ASYNC;
3572                 break;
3573         default:
3574                 devstr = "(unknown model)";
3575         }
3576         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3577                 devstr, info->device_name, info->phys_reg_addr,
3578                 info->irq_level, info->max_frame_size);
3579 
3580 #if SYNCLINK_GENERIC_HDLC
3581         hdlcdev_init(info);
3582 #endif
3583 }
3584 
3585 static const struct tty_port_operations slgt_port_ops = {
3586         .carrier_raised = carrier_raised,
3587         .dtr_rts = dtr_rts,
3588 };
3589 
3590 /*
3591  *  allocate device instance structure, return NULL on failure
3592  */
3593 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3594 {
3595         struct slgt_info *info;
3596 
3597         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3598 
3599         if (!info) {
3600                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3601                         driver_name, adapter_num, port_num));
3602         } else {
3603                 tty_port_init(&info->port);
3604                 info->port.ops = &slgt_port_ops;
3605                 info->magic = MGSL_MAGIC;
3606                 INIT_WORK(&info->task, bh_handler);
3607                 info->max_frame_size = 4096;
3608                 info->base_clock = 14745600;
3609                 info->rbuf_fill_level = DMABUFSIZE;
3610                 info->port.close_delay = 5*HZ/10;
3611                 info->port.closing_wait = 30*HZ;
3612                 init_waitqueue_head(&info->status_event_wait_q);
3613                 init_waitqueue_head(&info->event_wait_q);
3614                 spin_lock_init(&info->netlock);
3615                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3616                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3617                 info->adapter_num = adapter_num;
3618                 info->port_num = port_num;
3619 
3620                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3621                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3622 
3623                 /* Copy configuration info to device instance data */
3624                 info->pdev = pdev;
3625                 info->irq_level = pdev->irq;
3626                 info->phys_reg_addr = pci_resource_start(pdev,0);
3627 
3628                 info->bus_type = MGSL_BUS_TYPE_PCI;
3629                 info->irq_flags = IRQF_SHARED;
3630 
3631                 info->init_error = -1; /* assume error, set to 0 on successful init */
3632         }
3633 
3634         return info;
3635 }
3636 
3637 static void device_init(int adapter_num, struct pci_dev *pdev)
3638 {
3639         struct slgt_info *port_array[SLGT_MAX_PORTS];
3640         int i;
3641         int port_count = 1;
3642 
3643         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3644                 port_count = 2;
3645         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3646                 port_count = 4;
3647 
3648         /* allocate device instances for all ports */
3649         for (i=0; i < port_count; ++i) {
3650                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3651                 if (port_array[i] == NULL) {
3652                         for (--i; i >= 0; --i) {
3653                                 tty_port_destroy(&port_array[i]->port);
3654                                 kfree(port_array[i]);
3655                         }
3656                         return;
3657                 }
3658         }
3659 
3660         /* give copy of port_array to all ports and add to device list  */
3661         for (i=0; i < port_count; ++i) {
3662                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3663                 add_device(port_array[i]);
3664                 port_array[i]->port_count = port_count;
3665                 spin_lock_init(&port_array[i]->lock);
3666         }
3667 
3668         /* Allocate and claim adapter resources */
3669         if (!claim_resources(port_array[0])) {
3670 
3671                 alloc_dma_bufs(port_array[0]);
3672 
3673                 /* copy resource information from first port to others */
3674                 for (i = 1; i < port_count; ++i) {
3675                         port_array[i]->irq_level = port_array[0]->irq_level;
3676                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3677                         alloc_dma_bufs(port_array[i]);
3678                 }
3679 
3680                 if (request_irq(port_array[0]->irq_level,
3681                                         slgt_interrupt,
3682                                         port_array[0]->irq_flags,
3683                                         port_array[0]->device_name,
3684                                         port_array[0]) < 0) {
3685                         DBGERR(("%s request_irq failed IRQ=%d\n",
3686                                 port_array[0]->device_name,
3687                                 port_array[0]->irq_level));
3688                 } else {
3689                         port_array[0]->irq_requested = true;
3690                         adapter_test(port_array[0]);
3691                         for (i=1 ; i < port_count ; i++) {
3692                                 port_array[i]->init_error = port_array[0]->init_error;
3693                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3694                         }
3695                 }
3696         }
3697 
3698         for (i = 0; i < port_count; ++i) {
3699                 struct slgt_info *info = port_array[i];
3700                 tty_port_register_device(&info->port, serial_driver, info->line,
3701                                 &info->pdev->dev);
3702         }
3703 }
3704 
3705 static int init_one(struct pci_dev *dev,
3706                               const struct pci_device_id *ent)
3707 {
3708         if (pci_enable_device(dev)) {
3709                 printk("error enabling pci device %p\n", dev);
3710                 return -EIO;
3711         }
3712         pci_set_master(dev);
3713         device_init(slgt_device_count, dev);
3714         return 0;
3715 }
3716 
3717 static void remove_one(struct pci_dev *dev)
3718 {
3719 }
3720 
3721 static const struct tty_operations ops = {
3722         .open = open,
3723         .close = close,
3724         .write = write,
3725         .put_char = put_char,
3726         .flush_chars = flush_chars,
3727         .write_room = write_room,
3728         .chars_in_buffer = chars_in_buffer,
3729         .flush_buffer = flush_buffer,
3730         .ioctl = ioctl,
3731         .compat_ioctl = slgt_compat_ioctl,
3732         .throttle = throttle,
3733         .unthrottle = unthrottle,
3734         .send_xchar = send_xchar,
3735         .break_ctl = set_break,
3736         .wait_until_sent = wait_until_sent,
3737         .set_termios = set_termios,
3738         .stop = tx_hold,
3739         .start = tx_release,
3740         .hangup = hangup,
3741         .tiocmget = tiocmget,
3742         .tiocmset = tiocmset,
3743         .get_icount = get_icount,
3744         .proc_fops = &synclink_gt_proc_fops,
3745 };
3746 
3747 static void slgt_cleanup(void)
3748 {
3749         int rc;
3750         struct slgt_info *info;
3751         struct slgt_info *tmp;
3752 
3753         printk(KERN_INFO "unload %s\n", driver_name);
3754 
3755         if (serial_driver) {
3756                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3757                         tty_unregister_device(serial_driver, info->line);
3758                 if ((rc = tty_unregister_driver(serial_driver)))
3759                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3760                 put_tty_driver(serial_driver);
3761         }
3762 
3763         /* reset devices */
3764         info = slgt_device_list;
3765         while(info) {
3766                 reset_port(info);
3767                 info = info->next_device;
3768         }
3769 
3770         /* release devices */
3771         info = slgt_device_list;
3772         while(info) {
3773 #if SYNCLINK_GENERIC_HDLC
3774                 hdlcdev_exit(info);
3775 #endif
3776                 free_dma_bufs(info);
3777                 free_tmp_rbuf(info);
3778                 if (info->port_num == 0)
3779                         release_resources(info);
3780                 tmp = info;
3781                 info = info->next_device;
3782                 tty_port_destroy(&tmp->port);
3783                 kfree(tmp);
3784         }
3785 
3786         if (pci_registered)
3787                 pci_unregister_driver(&pci_driver);
3788 }
3789 
3790 /*
3791  *  Driver initialization entry point.
3792  */
3793 static int __init slgt_init(void)
3794 {
3795         int rc;
3796 
3797         printk(KERN_INFO "%s\n", driver_name);
3798 
3799         serial_driver = alloc_tty_driver(MAX_DEVICES);
3800         if (!serial_driver) {
3801                 printk("%s can't allocate tty driver\n", driver_name);
3802                 return -ENOMEM;
3803         }
3804 
3805         /* Initialize the tty_driver structure */
3806 
3807         serial_driver->driver_name = tty_driver_name;
3808         serial_driver->name = tty_dev_prefix;
3809         serial_driver->major = ttymajor;
3810         serial_driver->minor_start = 64;
3811         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3812         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3813         serial_driver->init_termios = tty_std_termios;
3814         serial_driver->init_termios.c_cflag =
3815                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3816         serial_driver->init_termios.c_ispeed = 9600;
3817         serial_driver->init_termios.c_ospeed = 9600;
3818         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3819         tty_set_operations(serial_driver, &ops);
3820         if ((rc = tty_register_driver(serial_driver)) < 0) {
3821                 DBGERR(("%s can't register serial driver\n", driver_name));
3822                 put_tty_driver(serial_driver);
3823                 serial_driver = NULL;
3824                 goto error;
3825         }
3826 
3827         printk(KERN_INFO "%s, tty major#%d\n",
3828                driver_name, serial_driver->major);
3829 
3830         slgt_device_count = 0;
3831         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3832                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3833                 goto error;
3834         }
3835         pci_registered = true;
3836 
3837         if (!slgt_device_list)
3838                 printk("%s no devices found\n",driver_name);
3839 
3840         return 0;
3841 
3842 error:
3843         slgt_cleanup();
3844         return rc;
3845 }
3846 
3847 static void __exit slgt_exit(void)
3848 {
3849         slgt_cleanup();
3850 }
3851 
3852 module_init(slgt_init);
3853 module_exit(slgt_exit);
3854 
3855 /*
3856  * register access routines
3857  */
3858 
3859 #define CALC_REGADDR() \
3860         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3861         if (addr >= 0x80) \
3862                 reg_addr += (info->port_num) * 32; \
3863         else if (addr >= 0x40)  \
3864                 reg_addr += (info->port_num) * 16;
3865 
3866 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3867 {
3868         CALC_REGADDR();
3869         return readb((void __iomem *)reg_addr);
3870 }
3871 
3872 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3873 {
3874         CALC_REGADDR();
3875         writeb(value, (void __iomem *)reg_addr);
3876 }
3877 
3878 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3879 {
3880         CALC_REGADDR();
3881         return readw((void __iomem *)reg_addr);
3882 }
3883 
3884 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3885 {
3886         CALC_REGADDR();
3887         writew(value, (void __iomem *)reg_addr);
3888 }
3889 
3890 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3891 {
3892         CALC_REGADDR();
3893         return readl((void __iomem *)reg_addr);
3894 }
3895 
3896 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3897 {
3898         CALC_REGADDR();
3899         writel(value, (void __iomem *)reg_addr);
3900 }
3901 
3902 static void rdma_reset(struct slgt_info *info)
3903 {
3904         unsigned int i;
3905 
3906         /* set reset bit */
3907         wr_reg32(info, RDCSR, BIT1);
3908 
3909         /* wait for enable bit cleared */
3910         for(i=0 ; i < 1000 ; i++)
3911                 if (!(rd_reg32(info, RDCSR) & BIT0))
3912                         break;
3913 }
3914 
3915 static void tdma_reset(struct slgt_info *info)
3916 {
3917         unsigned int i;
3918 
3919         /* set reset bit */
3920         wr_reg32(info, TDCSR, BIT1);
3921 
3922         /* wait for enable bit cleared */
3923         for(i=0 ; i < 1000 ; i++)
3924                 if (!(rd_reg32(info, TDCSR) & BIT0))
3925                         break;
3926 }
3927 
3928 /*
3929  * enable internal loopback
3930  * TxCLK and RxCLK are generated from BRG
3931  * and TxD is looped back to RxD internally.
3932  */
3933 static void enable_loopback(struct slgt_info *info)
3934 {
3935         /* SCR (serial control) BIT2=loopback enable */
3936         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3937 
3938         if (info->params.mode != MGSL_MODE_ASYNC) {
3939                 /* CCR (clock control)
3940                  * 07..05  tx clock source (010 = BRG)
3941                  * 04..02  rx clock source (010 = BRG)
3942                  * 01      auxclk enable   (0 = disable)
3943                  * 00      BRG enable      (1 = enable)
3944                  *
3945                  * 0100 1001
3946                  */
3947                 wr_reg8(info, CCR, 0x49);
3948 
3949                 /* set speed if available, otherwise use default */
3950                 if (info->params.clock_speed)
3951                         set_rate(info, info->params.clock_speed);
3952                 else
3953                         set_rate(info, 3686400);
3954         }
3955 }
3956 
3957 /*
3958  *  set baud rate generator to specified rate
3959  */
3960 static void set_rate(struct slgt_info *info, u32 rate)
3961 {
3962         unsigned int div;
3963         unsigned int osc = info->base_clock;
3964 
3965         /* div = osc/rate - 1
3966          *
3967          * Round div up if osc/rate is not integer to
3968          * force to next slowest rate.
3969          */
3970 
3971         if (rate) {
3972                 div = osc/rate;
3973                 if (!(osc % rate) && div)
3974                         div--;
3975                 wr_reg16(info, BDR, (unsigned short)div);
3976         }
3977 }
3978 
3979 static void rx_stop(struct slgt_info *info)
3980 {
3981         unsigned short val;
3982 
3983         /* disable and reset receiver */
3984         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3985         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3986         wr_reg16(info, RCR, val);                  /* clear reset bit */
3987 
3988         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3989 
3990         /* clear pending rx interrupts */
3991         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3992 
3993         rdma_reset(info);
3994 
3995         info->rx_enabled = false;
3996         info->rx_restart = false;
3997 }
3998 
3999 static void rx_start(struct slgt_info *info)
4000 {
4001         unsigned short val;
4002 
4003         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
4004 
4005         /* clear pending rx overrun IRQ */
4006         wr_reg16(info, SSR, IRQ_RXOVER);
4007 
4008         /* reset and disable receiver */
4009         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
4010         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
4011         wr_reg16(info, RCR, val);                  /* clear reset bit */
4012 
4013         rdma_reset(info);
4014         reset_rbufs(info);
4015 
4016         if (info->rx_pio) {
4017                 /* rx request when rx FIFO not empty */
4018                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4019                 slgt_irq_on(info, IRQ_RXDATA);
4020                 if (info->params.mode == MGSL_MODE_ASYNC) {
4021                         /* enable saving of rx status */
4022                         wr_reg32(info, RDCSR, BIT6);
4023                 }
4024         } else {
4025                 /* rx request when rx FIFO half full */
4026                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4027                 /* set 1st descriptor address */
4028                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4029 
4030                 if (info->params.mode != MGSL_MODE_ASYNC) {
4031                         /* enable rx DMA and DMA interrupt */
4032                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
4033                 } else {
4034                         /* enable saving of rx status, rx DMA and DMA interrupt */
4035                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4036                 }
4037         }
4038 
4039         slgt_irq_on(info, IRQ_RXOVER);
4040 
4041         /* enable receiver */
4042         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4043 
4044         info->rx_restart = false;
4045         info->rx_enabled = true;
4046 }
4047 
4048 static void tx_start(struct slgt_info *info)
4049 {
4050         if (!info->tx_enabled) {
4051                 wr_reg16(info, TCR,
4052                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4053                 info->tx_enabled = true;
4054         }
4055 
4056         if (desc_count(info->tbufs[info->tbuf_start])) {
4057                 info->drop_rts_on_tx_done = false;
4058 
4059                 if (info->params.mode != MGSL_MODE_ASYNC) {
4060                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4061                                 get_signals(info);
4062                                 if (!(info->signals & SerialSignal_RTS)) {
4063                                         info->signals |= SerialSignal_RTS;
4064                                         set_signals(info);
4065                                         info->drop_rts_on_tx_done = true;
4066                                 }
4067                         }
4068 
4069                         slgt_irq_off(info, IRQ_TXDATA);
4070                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4071                         /* clear tx idle and underrun status bits */
4072                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4073                 } else {
4074                         slgt_irq_off(info, IRQ_TXDATA);
4075                         slgt_irq_on(info, IRQ_TXIDLE);
4076                         /* clear tx idle status bit */
4077                         wr_reg16(info, SSR, IRQ_TXIDLE);
4078                 }
4079                 /* set 1st descriptor address and start DMA */
4080                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4081                 wr_reg32(info, TDCSR, BIT2 + BIT0);
4082                 info->tx_active = true;
4083         }
4084 }
4085 
4086 static void tx_stop(struct slgt_info *info)
4087 {
4088         unsigned short val;
4089 
4090         del_timer(&info->tx_timer);
4091 
4092         tdma_reset(info);
4093 
4094         /* reset and disable transmitter */
4095         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4096         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4097 
4098         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4099 
4100         /* clear tx idle and underrun status bit */
4101         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4102 
4103         reset_tbufs(info);
4104 
4105         info->tx_enabled = false;
4106         info->tx_active = false;
4107 }
4108 
4109 static void reset_port(struct slgt_info *info)
4110 {
4111         if (!info->reg_addr)
4112                 return;
4113 
4114         tx_stop(info);
4115         rx_stop(info);
4116 
4117         info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4118         set_signals(info);
4119 
4120         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4121 }
4122 
4123 static void reset_adapter(struct slgt_info *info)
4124 {
4125         int i;
4126         for (i=0; i < info->port_count; ++i) {
4127                 if (info->port_array[i])
4128                         reset_port(info->port_array[i]);
4129         }
4130 }
4131 
4132 static void async_mode(struct slgt_info *info)
4133 {
4134         unsigned short val;
4135 
4136         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4137         tx_stop(info);
4138         rx_stop(info);
4139 
4140         /* TCR (tx control)
4141          *
4142          * 15..13  mode, 010=async
4143          * 12..10  encoding, 000=NRZ
4144          * 09      parity enable
4145          * 08      1=odd parity, 0=even parity
4146          * 07      1=RTS driver control
4147          * 06      1=break enable
4148          * 05..04  character length
4149          *         00=5 bits
4150          *         01=6 bits
4151          *         10=7 bits
4152          *         11=8 bits
4153          * 03      0=1 stop bit, 1=2 stop bits
4154          * 02      reset
4155          * 01      enable
4156          * 00      auto-CTS enable
4157          */
4158         val = 0x4000;
4159 
4160         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4161                 val |= BIT7;
4162 
4163         if (info->params.parity != ASYNC_PARITY_NONE) {
4164                 val |= BIT9;
4165                 if (info->params.parity == ASYNC_PARITY_ODD)
4166                         val |= BIT8;
4167         }
4168 
4169         switch (info->params.data_bits)
4170         {
4171         case 6: val |= BIT4; break;
4172         case 7: val |= BIT5; break;
4173         case 8: val |= BIT5 + BIT4; break;
4174         }
4175 
4176         if (info->params.stop_bits != 1)
4177                 val |= BIT3;
4178 
4179         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4180                 val |= BIT0;
4181 
4182         wr_reg16(info, TCR, val);
4183 
4184         /* RCR (rx control)
4185          *
4186          * 15..13  mode, 010=async
4187          * 12..10  encoding, 000=NRZ
4188          * 09      parity enable
4189          * 08      1=odd parity, 0=even parity
4190          * 07..06  reserved, must be 0
4191          * 05..04  character length
4192          *         00=5 bits
4193          *         01=6 bits
4194          *         10=7 bits
4195          *         11=8 bits
4196          * 03      reserved, must be zero
4197          * 02      reset
4198          * 01      enable
4199          * 00      auto-DCD enable
4200          */
4201         val = 0x4000;
4202 
4203         if (info->params.parity != ASYNC_PARITY_NONE) {
4204                 val |= BIT9;
4205                 if (info->params.parity == ASYNC_PARITY_ODD)
4206                         val |= BIT8;
4207         }
4208 
4209         switch (info->params.data_bits)
4210         {
4211         case 6: val |= BIT4; break;
4212         case 7: val |= BIT5; break;
4213         case 8: val |= BIT5 + BIT4; break;
4214         }
4215 
4216         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4217                 val |= BIT0;
4218 
4219         wr_reg16(info, RCR, val);
4220 
4221         /* CCR (clock control)
4222          *
4223          * 07..05  011 = tx clock source is BRG/16
4224          * 04..02  010 = rx clock source is BRG
4225          * 01      0 = auxclk disabled
4226          * 00      1 = BRG enabled
4227          *
4228          * 0110 1001
4229          */
4230         wr_reg8(info, CCR, 0x69);
4231 
4232         msc_set_vcr(info);
4233 
4234         /* SCR (serial control)
4235          *
4236          * 15  1=tx req on FIFO half empty
4237          * 14  1=rx req on FIFO half full
4238          * 13  tx data  IRQ enable
4239          * 12  tx idle  IRQ enable
4240          * 11  rx break on IRQ enable
4241          * 10  rx data  IRQ enable
4242          * 09  rx break off IRQ enable
4243          * 08  overrun  IRQ enable
4244          * 07  DSR      IRQ enable
4245          * 06  CTS      IRQ enable
4246          * 05  DCD      IRQ enable
4247          * 04  RI       IRQ enable
4248          * 03  0=16x sampling, 1=8x sampling
4249          * 02  1=txd->rxd internal loopback enable
4250          * 01  reserved, must be zero
4251          * 00  1=master IRQ enable
4252          */
4253         val = BIT15 + BIT14 + BIT0;
4254         /* JCR[8] : 1 = x8 async mode feature available */
4255         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4256             ((info->base_clock < (info->params.data_rate * 16)) ||
4257              (info->base_clock % (info->params.data_rate * 16)))) {
4258                 /* use 8x sampling */
4259                 val |= BIT3;
4260                 set_rate(info, info->params.data_rate * 8);
4261         } else {
4262                 /* use 16x sampling */
4263                 set_rate(info, info->params.data_rate * 16);
4264         }
4265         wr_reg16(info, SCR, val);
4266 
4267         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4268 
4269         if (info->params.loopback)
4270                 enable_loopback(info);
4271 }
4272 
4273 static void sync_mode(struct slgt_info *info)
4274 {
4275         unsigned short val;
4276 
4277         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4278         tx_stop(info);
4279         rx_stop(info);
4280 
4281         /* TCR (tx control)
4282          *
4283          * 15..13  mode
4284          *         000=HDLC/SDLC
4285          *         001=raw bit synchronous
4286          *         010=asynchronous/isochronous
4287          *         011=monosync byte synchronous
4288          *         100=bisync byte synchronous
4289          *         101=xsync byte synchronous
4290          * 12..10  encoding
4291          * 09      CRC enable
4292          * 08      CRC32
4293          * 07      1=RTS driver control
4294          * 06      preamble enable
4295          * 05..04  preamble length
4296          * 03      share open/close flag
4297          * 02      reset
4298          * 01      enable
4299          * 00      auto-CTS enable
4300          */
4301         val = BIT2;
4302 
4303         switch(info->params.mode) {
4304         case MGSL_MODE_XSYNC:
4305                 val |= BIT15 + BIT13;
4306                 break;
4307         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4308         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4309         case MGSL_MODE_RAW:      val |= BIT13; break;
4310         }
4311         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4312                 val |= BIT7;
4313 
4314         switch(info->params.encoding)
4315         {
4316         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4317         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4318         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4319         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4320         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4321         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4322         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4323         }
4324 
4325         switch (info->params.crc_type & HDLC_CRC_MASK)
4326         {
4327         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4328         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4329         }
4330 
4331         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4332                 val |= BIT6;
4333 
4334         switch (info->params.preamble_length)
4335         {
4336         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4337         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4338         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4339         }
4340 
4341         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4342                 val |= BIT0;
4343 
4344         wr_reg16(info, TCR, val);
4345 
4346         /* TPR (transmit preamble) */
4347 
4348         switch (info->params.preamble)
4349         {
4350         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4351         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4352         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4353         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4354         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4355         default:                          val = 0x7e; break;
4356         }
4357         wr_reg8(info, TPR, (unsigned char)val);
4358 
4359         /* RCR (rx control)
4360          *
4361          * 15..13  mode
4362          *         000=HDLC/SDLC
4363          *         001=raw bit synchronous
4364          *         010=asynchronous/isochronous
4365          *         011=monosync byte synchronous
4366          *         100=bisync byte synchronous
4367          *         101=xsync byte synchronous
4368          * 12..10  encoding
4369          * 09      CRC enable
4370          * 08      CRC32
4371          * 07..03  reserved, must be 0
4372          * 02      reset
4373          * 01      enable
4374          * 00      auto-DCD enable
4375          */
4376         val = 0;
4377 
4378         switch(info->params.mode) {
4379         case MGSL_MODE_XSYNC:
4380                 val |= BIT15 + BIT13;
4381                 break;
4382         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4383         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4384         case MGSL_MODE_RAW:      val |= BIT13; break;
4385         }
4386 
4387         switch(info->params.encoding)
4388         {
4389         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4390         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4391         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4392         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4393         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4394         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4395         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4396         }
4397 
4398         switch (info->params.crc_type & HDLC_CRC_MASK)
4399         {
4400         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4401         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4402         }
4403 
4404         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4405                 val |= BIT0;
4406 
4407         wr_reg16(info, RCR, val);
4408 
4409         /* CCR (clock control)
4410          *
4411          * 07..05  tx clock source
4412          * 04..02  rx clock source
4413          * 01      auxclk enable
4414          * 00      BRG enable
4415          */
4416         val = 0;
4417 
4418         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4419         {
4420                 // when RxC source is DPLL, BRG generates 16X DPLL
4421                 // reference clock, so take TxC from BRG/16 to get
4422                 // transmit clock at actual data rate
4423                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4424                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4425                 else
4426                         val |= BIT6;    /* 010, txclk = BRG */
4427         }
4428         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4429                 val |= BIT7;    /* 100, txclk = DPLL Input */
4430         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4431                 val |= BIT5;    /* 001, txclk = RXC Input */
4432 
4433         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4434                 val |= BIT3;    /* 010, rxclk = BRG */
4435         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4436                 val |= BIT4;    /* 100, rxclk = DPLL */
4437         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4438                 val |= BIT2;    /* 001, rxclk = TXC Input */
4439 
4440         if (info->params.clock_speed)
4441                 val |= BIT1 + BIT0;
4442 
4443         wr_reg8(info, CCR, (unsigned char)val);
4444 
4445         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4446         {
4447                 // program DPLL mode
4448                 switch(info->params.encoding)
4449                 {
4450                 case HDLC_ENCODING_BIPHASE_MARK:
4451                 case HDLC_ENCODING_BIPHASE_SPACE:
4452                         val = BIT7; break;
4453                 case HDLC_ENCODING_BIPHASE_LEVEL:
4454                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4455                         val = BIT7 + BIT6; break;
4456                 default: val = BIT6;    // NRZ encodings
4457                 }
4458                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4459 
4460                 // DPLL requires a 16X reference clock from BRG
4461                 set_rate(info, info->params.clock_speed * 16);
4462         }
4463         else
4464                 set_rate(info, info->params.clock_speed);
4465 
4466         tx_set_idle(info);
4467 
4468         msc_set_vcr(info);
4469 
4470         /* SCR (serial control)
4471          *
4472          * 15  1=tx req on FIFO half empty
4473          * 14  1=rx req on FIFO half full
4474          * 13  tx data  IRQ enable
4475          * 12  tx idle  IRQ enable
4476          * 11  underrun IRQ enable
4477          * 10  rx data  IRQ enable
4478          * 09  rx idle  IRQ enable
4479          * 08  overrun  IRQ enable
4480          * 07  DSR      IRQ enable
4481          * 06  CTS      IRQ enable
4482          * 05  DCD      IRQ enable
4483          * 04  RI       IRQ enable
4484          * 03  reserved, must be zero
4485          * 02  1=txd->rxd internal loopback enable
4486          * 01  reserved, must be zero
4487          * 00  1=master IRQ enable
4488          */
4489         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4490 
4491         if (info->params.loopback)
4492                 enable_loopback(info);
4493 }
4494 
4495 /*
4496  *  set transmit idle mode
4497  */
4498 static void tx_set_idle(struct slgt_info *info)
4499 {
4500         unsigned char val;
4501         unsigned short tcr;
4502 
4503         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4504          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4505          */
4506         tcr = rd_reg16(info, TCR);
4507         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4508                 /* disable preamble, set idle size to 16 bits */
4509                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4510                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4511                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4512         } else if (!(tcr & BIT6)) {
4513                 /* preamble is disabled, set idle size to 8 bits */
4514                 tcr &= ~(BIT5 + BIT4);
4515         }
4516         wr_reg16(info, TCR, tcr);
4517 
4518         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4519                 /* LSB of custom tx idle specified in tx idle register */
4520                 val = (unsigned char)(info->idle_mode & 0xff);
4521         } else {
4522                 /* standard 8 bit idle patterns */
4523                 switch(info->idle_mode)
4524                 {
4525                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4526                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4527                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4528                 case HDLC_TXIDLE_ZEROS:
4529                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4530                 default:                         val = 0xff;
4531                 }
4532         }
4533 
4534         wr_reg8(info, TIR, val);
4535 }
4536 
4537 /*
4538  * get state of V24 status (input) signals
4539  */
4540 static void get_signals(struct slgt_info *info)
4541 {
4542         unsigned short status = rd_reg16(info, SSR);
4543 
4544         /* clear all serial signals except RTS and DTR */
4545         info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4546 
4547         if (status & BIT3)
4548                 info->signals |= SerialSignal_DSR;
4549         if (status & BIT2)
4550                 info->signals |= SerialSignal_CTS;
4551         if (status & BIT1)
4552                 info->signals |= SerialSignal_DCD;
4553         if (status & BIT0)
4554                 info->signals |= SerialSignal_RI;
4555 }
4556 
4557 /*
4558  * set V.24 Control Register based on current configuration
4559  */
4560 static void msc_set_vcr(struct slgt_info *info)
4561 {
4562         unsigned char val = 0;
4563 
4564         /* VCR (V.24 control)
4565          *
4566          * 07..04  serial IF select
4567          * 03      DTR
4568          * 02      RTS
4569          * 01      LL
4570          * 00      RL
4571          */
4572 
4573         switch(info->if_mode & MGSL_INTERFACE_MASK)
4574         {
4575         case MGSL_INTERFACE_RS232:
4576                 val |= BIT5; /* 0010 */
4577                 break;
4578         case MGSL_INTERFACE_V35:
4579                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4580                 break;
4581         case MGSL_INTERFACE_RS422:
4582                 val |= BIT6; /* 0100 */
4583                 break;
4584         }
4585 
4586         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4587                 val |= BIT4;
4588         if (info->signals & SerialSignal_DTR)
4589                 val |= BIT3;
4590         if (info->signals & SerialSignal_RTS)
4591                 val |= BIT2;
4592         if (info->if_mode & MGSL_INTERFACE_LL)
4593                 val |= BIT1;
4594         if (info->if_mode & MGSL_INTERFACE_RL)
4595                 val |= BIT0;
4596         wr_reg8(info, VCR, val);
4597 }
4598 
4599 /*
4600  * set state of V24 control (output) signals
4601  */
4602 static void set_signals(struct slgt_info *info)
4603 {
4604         unsigned char val = rd_reg8(info, VCR);
4605         if (info->signals & SerialSignal_DTR)
4606                 val |= BIT3;
4607         else
4608                 val &= ~BIT3;
4609         if (info->signals & SerialSignal_RTS)
4610                 val |= BIT2;
4611         else
4612                 val &= ~BIT2;
4613         wr_reg8(info, VCR, val);
4614 }
4615 
4616 /*
4617  * free range of receive DMA buffers (i to last)
4618  */
4619 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4620 {
4621         int done = 0;
4622 
4623         while(!done) {
4624                 /* reset current buffer for reuse */
4625                 info->rbufs[i].status = 0;
4626                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4627                 if (i == last)
4628                         done = 1;
4629                 if (++i == info->rbuf_count)
4630                         i = 0;
4631         }
4632         info->rbuf_current = i;
4633 }
4634 
4635 /*
4636  * mark all receive DMA buffers as free
4637  */
4638 static void reset_rbufs(struct slgt_info *info)
4639 {
4640         free_rbufs(info, 0, info->rbuf_count - 1);
4641         info->rbuf_fill_index = 0;
4642         info->rbuf_fill_count = 0;
4643 }
4644 
4645 /*
4646  * pass receive HDLC frame to upper layer
4647  *
4648  * return true if frame available, otherwise false
4649  */
4650 static bool rx_get_frame(struct slgt_info *info)
4651 {
4652         unsigned int start, end;
4653         unsigned short status;
4654         unsigned int framesize = 0;
4655         unsigned long flags;
4656         struct tty_struct *tty = info->port.tty;
4657         unsigned char addr_field = 0xff;
4658         unsigned int crc_size = 0;
4659 
4660         switch (info->params.crc_type & HDLC_CRC_MASK) {
4661         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4662         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4663         }
4664 
4665 check_again:
4666 
4667         framesize = 0;
4668         addr_field = 0xff;
4669         start = end = info->rbuf_current;
4670 
4671         for (;;) {
4672                 if (!desc_complete(info->rbufs[end]))
4673                         goto cleanup;
4674 
4675                 if (framesize == 0 && info->params.addr_filter != 0xff)
4676                         addr_field = info->rbufs[end].buf[0];
4677 
4678                 framesize += desc_count(info->rbufs[end]);
4679 
4680                 if (desc_eof(info->rbufs[end]))
4681                         break;
4682 
4683                 if (++end == info->rbuf_count)
4684                         end = 0;
4685 
4686                 if (end == info->rbuf_current) {
4687                         if (info->rx_enabled){
4688                                 spin_lock_irqsave(&info->lock,flags);
4689                                 rx_start(info);
4690                                 spin_unlock_irqrestore(&info->lock,flags);
4691                         }
4692                         goto cleanup;
4693                 }
4694         }
4695 
4696         /* status
4697          *
4698          * 15      buffer complete
4699          * 14..06  reserved
4700          * 05..04  residue
4701          * 02      eof (end of frame)
4702          * 01      CRC error
4703          * 00      abort
4704          */
4705         status = desc_status(info->rbufs[end]);
4706 
4707         /* ignore CRC bit if not using CRC (bit is undefined) */
4708         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4709                 status &= ~BIT1;
4710 
4711         if (framesize == 0 ||
4712                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4713                 free_rbufs(info, start, end);
4714                 goto check_again;
4715         }
4716 
4717         if (framesize < (2 + crc_size) || status & BIT0) {
4718                 info->icount.rxshort++;
4719                 framesize = 0;
4720         } else if (status & BIT1) {
4721                 info->icount.rxcrc++;
4722                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4723                         framesize = 0;
4724         }
4725 
4726 #if SYNCLINK_GENERIC_HDLC
4727         if (framesize == 0) {
4728                 info->netdev->stats.rx_errors++;
4729                 info->netdev->stats.rx_frame_errors++;
4730         }
4731 #endif
4732 
4733         DBGBH(("%s rx frame status=%04X size=%d\n",
4734                 info->device_name, status, framesize));
4735         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4736 
4737         if (framesize) {
4738                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4739                         framesize -= crc_size;
4740                         crc_size = 0;
4741                 }
4742 
4743                 if (framesize > info->max_frame_size + crc_size)
4744                         info->icount.rxlong++;
4745                 else {
4746                         /* copy dma buffer(s) to contiguous temp buffer */
4747                         int copy_count = framesize;
4748                         int i = start;
4749                         unsigned char *p = info->tmp_rbuf;
4750                         info->tmp_rbuf_count = framesize;
4751 
4752                         info->icount.rxok++;
4753 
4754                         while(copy_count) {
4755                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4756                                 memcpy(p, info->rbufs[i].buf, partial_count);
4757                                 p += partial_count;
4758                                 copy_count -= partial_count;
4759                                 if (++i == info->rbuf_count)
4760                                         i = 0;
4761                         }
4762 
4763                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4764                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4765                                 framesize++;
4766                         }
4767 
4768 #if SYNCLINK_GENERIC_HDLC
4769                         if (info->netcount)
4770                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4771                         else
4772 #endif
4773                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4774                 }
4775         }
4776         free_rbufs(info, start, end);
4777         return true;
4778 
4779 cleanup:
4780         return false;
4781 }
4782 
4783 /*
4784  * pass receive buffer (RAW synchronous mode) to tty layer
4785  * return true if buffer available, otherwise false
4786  */
4787 static bool rx_get_buf(struct slgt_info *info)
4788 {
4789         unsigned int i = info->rbuf_current;
4790         unsigned int count;
4791 
4792         if (!desc_complete(info->rbufs[i]))
4793                 return false;
4794         count = desc_count(info->rbufs[i]);
4795         switch(info->params.mode) {
4796         case MGSL_MODE_MONOSYNC:
4797         case MGSL_MODE_BISYNC:
4798         case MGSL_MODE_XSYNC:
4799                 /* ignore residue in byte synchronous modes */
4800                 if (desc_residue(info->rbufs[i]))
4801                         count--;
4802                 break;
4803         }
4804         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4805         DBGINFO(("rx_get_buf size=%d\n", count));
4806         if (count)
4807                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4808                                   info->flag_buf, count);
4809         free_rbufs(info, i, i);
4810         return true;
4811 }
4812 
4813 static void reset_tbufs(struct slgt_info *info)
4814 {
4815         unsigned int i;
4816         info->tbuf_current = 0;
4817         for (i=0 ; i < info->tbuf_count ; i++) {
4818                 info->tbufs[i].status = 0;
4819                 info->tbufs[i].count  = 0;
4820         }
4821 }
4822 
4823 /*
4824  * return number of free transmit DMA buffers
4825  */
4826 static unsigned int free_tbuf_count(struct slgt_info *info)
4827 {
4828         unsigned int count = 0;
4829         unsigned int i = info->tbuf_current;
4830 
4831         do
4832         {
4833                 if (desc_count(info->tbufs[i]))
4834                         break; /* buffer in use */
4835                 ++count;
4836                 if (++i == info->tbuf_count)
4837                         i=0;
4838         } while (i != info->tbuf_current);
4839 
4840         /* if tx DMA active, last zero count buffer is in use */
4841         if (count && (rd_reg32(info, TDCSR) & BIT0))
4842                 --count;
4843 
4844         return count;
4845 }
4846 
4847 /*
4848  * return number of bytes in unsent transmit DMA buffers
4849  * and the serial controller tx FIFO
4850  */
4851 static unsigned int tbuf_bytes(struct slgt_info *info)
4852 {
4853         unsigned int total_count = 0;
4854         unsigned int i = info->tbuf_current;
4855         unsigned int reg_value;
4856         unsigned int count;
4857         unsigned int active_buf_count = 0;
4858 
4859         /*
4860          * Add descriptor counts for all tx DMA buffers.
4861          * If count is zero (cleared by DMA controller after read),
4862          * the buffer is complete or is actively being read from.
4863          *
4864          * Record buf_count of last buffer with zero count starting
4865          * from current ring position. buf_count is mirror
4866          * copy of count and is not cleared by serial controller.
4867          * If DMA controller is active, that buffer is actively
4868          * being read so add to total.
4869          */
4870         do {
4871                 count = desc_count(info->tbufs[i]);
4872                 if (count)
4873                         total_count += count;
4874                 else if (!total_count)
4875                         active_buf_count = info->tbufs[i].buf_count;
4876                 if (++i == info->tbuf_count)
4877                         i = 0;
4878         } while (i != info->tbuf_current);
4879 
4880         /* read tx DMA status register */
4881         reg_value = rd_reg32(info, TDCSR);
4882 
4883         /* if tx DMA active, last zero count buffer is in use */
4884         if (reg_value & BIT0)
4885                 total_count += active_buf_count;
4886 
4887         /* add tx FIFO count = reg_value[15..8] */
4888         total_count += (reg_value >> 8) & 0xff;
4889 
4890         /* if transmitter active add one byte for shift register */
4891         if (info->tx_active)
4892                 total_count++;
4893 
4894         return total_count;
4895 }
4896 
4897 /*
4898  * load data into transmit DMA buffer ring and start transmitter if needed
4899  * return true if data accepted, otherwise false (buffers full)
4900  */
4901 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4902 {
4903         unsigned short count;
4904         unsigned int i;
4905         struct slgt_desc *d;
4906 
4907         /* check required buffer space */
4908         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4909                 return false;
4910 
4911         DBGDATA(info, buf, size, "tx");
4912 
4913         /*
4914          * copy data to one or more DMA buffers in circular ring
4915          * tbuf_start   = first buffer for this data
4916          * tbuf_current = next free buffer
4917          *
4918          * Copy all data before making data visible to DMA controller by
4919          * setting descriptor count of the first buffer.
4920          * This prevents an active DMA controller from reading the first DMA
4921          * buffers of a frame and stopping before the final buffers are filled.
4922          */
4923 
4924         info->tbuf_start = i = info->tbuf_current;
4925 
4926         while (size) {
4927                 d = &info->tbufs[i];
4928 
4929                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4930                 memcpy(d->buf, buf, count);
4931 
4932                 size -= count;
4933                 buf  += count;
4934 
4935                 /*
4936                  * set EOF bit for last buffer of HDLC frame or
4937                  * for every buffer in raw mode
4938                  */
4939                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4940                     info->params.mode == MGSL_MODE_RAW)
4941                         set_desc_eof(*d, 1);
4942                 else
4943                         set_desc_eof(*d, 0);
4944 
4945                 /* set descriptor count for all but first buffer */
4946                 if (i != info->tbuf_start)
4947                         set_desc_count(*d, count);
4948                 d->buf_count = count;
4949 
4950                 if (++i == info->tbuf_count)
4951                         i = 0;
4952         }
4953 
4954         info->tbuf_current = i;
4955 
4956         /* set first buffer count to make new data visible to DMA controller */
4957         d = &info->tbufs[info->tbuf_start];
4958         set_desc_count(*d, d->buf_count);
4959 
4960         /* start transmitter if needed and update transmit timeout */
4961         if (!info->tx_active)
4962                 tx_start(info);
4963         update_tx_timer(info);
4964 
4965         return true;
4966 }
4967 
4968 static int register_test(struct slgt_info *info)
4969 {
4970         static unsigned short patterns[] =
4971                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4972         static unsigned int count = ARRAY_SIZE(patterns);
4973         unsigned int i;
4974         int rc = 0;
4975 
4976         for (i=0 ; i < count ; i++) {
4977                 wr_reg16(info, TIR, patterns[i]);
4978                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4979                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4980                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4981                         rc = -ENODEV;
4982                         break;
4983                 }
4984         }
4985         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4986         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4987         return rc;
4988 }
4989 
4990 static int irq_test(struct slgt_info *info)
4991 {
4992         unsigned long timeout;
4993         unsigned long flags;
4994         struct tty_struct *oldtty = info->port.tty;
4995         u32 speed = info->params.data_rate;
4996 
4997         info->params.data_rate = 921600;
4998         info->port.tty = NULL;
4999 
5000         spin_lock_irqsave(&info->lock, flags);
5001         async_mode(info);
5002         slgt_irq_on(info, IRQ_TXIDLE);
5003 
5004         /* enable transmitter */
5005         wr_reg16(info, TCR,
5006                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
5007 
5008         /* write one byte and wait for tx idle */
5009         wr_reg16(info, TDR, 0);
5010 
5011         /* assume failure */
5012         info->init_error = DiagStatus_IrqFailure;
5013         info->irq_occurred = false;
5014 
5015         spin_unlock_irqrestore(&info->lock, flags);
5016 
5017         timeout=100;
5018         while(timeout-- && !info->irq_occurred)
5019                 msleep_interruptible(10);
5020 
5021         spin_lock_irqsave(&info->lock,flags);
5022         reset_port(info);
5023         spin_unlock_irqrestore(&info->lock,flags);
5024 
5025         info->params.data_rate = speed;
5026         info->port.tty = oldtty;
5027 
5028         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5029         return info->irq_occurred ? 0 : -ENODEV;
5030 }
5031 
5032 static int loopback_test_rx(struct slgt_info *info)
5033 {
5034         unsigned char *src, *dest;
5035         int count;
5036 
5037         if (desc_complete(info->rbufs[0])) {
5038                 count = desc_count(info->rbufs[0]);
5039                 src   = info->rbufs[0].buf;
5040                 dest  = info->tmp_rbuf;
5041 
5042                 for( ; count ; count-=2, src+=2) {
5043                         /* src=data byte (src+1)=status byte */
5044                         if (!(*(src+1) & (BIT9 + BIT8))) {
5045                                 *dest = *src;
5046                                 dest++;
5047                                 info->tmp_rbuf_count++;
5048                         }
5049                 }
5050                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5051                 return 1;
5052         }
5053         return 0;
5054 }
5055 
5056 static int loopback_test(struct slgt_info *info)
5057 {
5058 #define TESTFRAMESIZE 20
5059 
5060         unsigned long timeout;
5061         u16 count = TESTFRAMESIZE;
5062         unsigned char buf[TESTFRAMESIZE];
5063         int rc = -ENODEV;
5064         unsigned long flags;
5065 
5066         struct tty_struct *oldtty = info->port.tty;
5067         MGSL_PARAMS params;
5068 
5069         memcpy(&params, &info->params, sizeof(params));
5070 
5071         info->params.mode = MGSL_MODE_ASYNC;
5072         info->params.data_rate = 921600;
5073         info->params.loopback = 1;
5074         info->port.tty = NULL;
5075 
5076         /* build and send transmit frame */
5077         for (count = 0; count < TESTFRAMESIZE; ++count)
5078                 buf[count] = (unsigned char)count;
5079 
5080         info->tmp_rbuf_count = 0;
5081         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5082 
5083         /* program hardware for HDLC and enabled receiver */
5084         spin_lock_irqsave(&info->lock,flags);
5085         async_mode(info);
5086         rx_start(info);
5087         tx_load(info, buf, count);
5088         spin_unlock_irqrestore(&info->lock, flags);
5089 
5090         /* wait for receive complete */
5091         for (timeout = 100; timeout; --timeout) {
5092                 msleep_interruptible(10);
5093                 if (loopback_test_rx(info)) {
5094                         rc = 0;
5095                         break;
5096                 }
5097         }
5098 
5099         /* verify received frame length and contents */
5100         if (!rc && (info->tmp_rbuf_count != count ||
5101                   memcmp(buf, info->tmp_rbuf, count))) {
5102                 rc = -ENODEV;
5103         }
5104 
5105         spin_lock_irqsave(&info->lock,flags);
5106         reset_adapter(info);
5107         spin_unlock_irqrestore(&info->lock,flags);
5108 
5109         memcpy(&info->params, &params, sizeof(info->params));
5110         info->port.tty = oldtty;
5111 
5112         info->init_error = rc ? DiagStatus_DmaFailure : 0;
5113         return rc;
5114 }
5115 
5116 static int adapter_test(struct slgt_info *info)
5117 {
5118         DBGINFO(("testing %s\n", info->device_name));
5119         if (register_test(info) < 0) {
5120                 printk("register test failure %s addr=%08X\n",
5121                         info->device_name, info->phys_reg_addr);
5122         } else if (irq_test(info) < 0) {
5123                 printk("IRQ test failure %s IRQ=%d\n",
5124                         info->device_name, info->irq_level);
5125         } else if (loopback_test(info) < 0) {
5126                 printk("loopback test failure %s\n", info->device_name);
5127         }
5128         return info->init_error;
5129 }
5130 
5131 /*
5132  * transmit timeout handler
5133  */
5134 static void tx_timeout(unsigned long context)
5135 {
5136         struct slgt_info *info = (struct slgt_info*)context;
5137         unsigned long flags;
5138 
5139         DBGINFO(("%s tx_timeout\n", info->device_name));
5140         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5141                 info->icount.txtimeout++;
5142         }
5143         spin_lock_irqsave(&info->lock,flags);
5144         tx_stop(info);
5145         spin_unlock_irqrestore(&info->lock,flags);
5146 
5147 #if SYNCLINK_GENERIC_HDLC
5148         if (info->netcount)
5149                 hdlcdev_tx_done(info);
5150         else
5151 #endif
5152                 bh_transmit(info);
5153 }
5154 
5155 /*
5156  * receive buffer polling timer
5157  */
5158 static void rx_timeout(unsigned long context)
5159 {
5160         struct slgt_info *info = (struct slgt_info*)context;
5161         unsigned long flags;
5162 
5163         DBGINFO(("%s rx_timeout\n", info->device_name));
5164         spin_lock_irqsave(&info->lock, flags);
5165         info->pending_bh |= BH_RECEIVE;
5166         spin_unlock_irqrestore(&info->lock, flags);
5167         bh_handler(&info->task);
5168 }
5169 
5170 

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