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Linux/drivers/tty/synclink_gt.c

  1 /*
  2  * Device driver for Microgate SyncLink GT serial adapters.
  3  *
  4  * written by Paul Fulghum for Microgate Corporation
  5  * paulkf@microgate.com
  6  *
  7  * Microgate and SyncLink are trademarks of Microgate Corporation
  8  *
  9  * This code is released under the GNU General Public License (GPL)
 10  *
 11  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 13  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 14  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
 15  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 16  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 17  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 18  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 19  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
 21  * OF THE POSSIBILITY OF SUCH DAMAGE.
 22  */
 23 
 24 /*
 25  * DEBUG OUTPUT DEFINITIONS
 26  *
 27  * uncomment lines below to enable specific types of debug output
 28  *
 29  * DBGINFO   information - most verbose output
 30  * DBGERR    serious errors
 31  * DBGBH     bottom half service routine debugging
 32  * DBGISR    interrupt service routine debugging
 33  * DBGDATA   output receive and transmit data
 34  * DBGTBUF   output transmit DMA buffers and registers
 35  * DBGRBUF   output receive DMA buffers and registers
 36  */
 37 
 38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
 39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
 40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
 41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
 42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
 43 /*#define DBGTBUF(info) dump_tbufs(info)*/
 44 /*#define DBGRBUF(info) dump_rbufs(info)*/
 45 
 46 
 47 #include <linux/module.h>
 48 #include <linux/errno.h>
 49 #include <linux/signal.h>
 50 #include <linux/sched.h>
 51 #include <linux/timer.h>
 52 #include <linux/interrupt.h>
 53 #include <linux/pci.h>
 54 #include <linux/tty.h>
 55 #include <linux/tty_flip.h>
 56 #include <linux/serial.h>
 57 #include <linux/major.h>
 58 #include <linux/string.h>
 59 #include <linux/fcntl.h>
 60 #include <linux/ptrace.h>
 61 #include <linux/ioport.h>
 62 #include <linux/mm.h>
 63 #include <linux/seq_file.h>
 64 #include <linux/slab.h>
 65 #include <linux/netdevice.h>
 66 #include <linux/vmalloc.h>
 67 #include <linux/init.h>
 68 #include <linux/delay.h>
 69 #include <linux/ioctl.h>
 70 #include <linux/termios.h>
 71 #include <linux/bitops.h>
 72 #include <linux/workqueue.h>
 73 #include <linux/hdlc.h>
 74 #include <linux/synclink.h>
 75 
 76 #include <asm/io.h>
 77 #include <asm/irq.h>
 78 #include <asm/dma.h>
 79 #include <asm/types.h>
 80 #include <asm/uaccess.h>
 81 
 82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
 83 #define SYNCLINK_GENERIC_HDLC 1
 84 #else
 85 #define SYNCLINK_GENERIC_HDLC 0
 86 #endif
 87 
 88 /*
 89  * module identification
 90  */
 91 static char *driver_name     = "SyncLink GT";
 92 static char *slgt_driver_name = "synclink_gt";
 93 static char *tty_dev_prefix  = "ttySLG";
 94 MODULE_LICENSE("GPL");
 95 #define MGSL_MAGIC 0x5401
 96 #define MAX_DEVICES 32
 97 
 98 static struct pci_device_id pci_table[] = {
 99         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103         {0,}, /* terminate list */
104 };
105 MODULE_DEVICE_TABLE(pci, pci_table);
106 
107 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
108 static void remove_one(struct pci_dev *dev);
109 static struct pci_driver pci_driver = {
110         .name           = "synclink_gt",
111         .id_table       = pci_table,
112         .probe          = init_one,
113         .remove         = remove_one,
114 };
115 
116 static bool pci_registered;
117 
118 /*
119  * module configuration and status
120  */
121 static struct slgt_info *slgt_device_list;
122 static int slgt_device_count;
123 
124 static int ttymajor;
125 static int debug_level;
126 static int maxframe[MAX_DEVICES];
127 
128 module_param(ttymajor, int, 0);
129 module_param(debug_level, int, 0);
130 module_param_array(maxframe, int, NULL, 0);
131 
132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
135 
136 /*
137  * tty support and callbacks
138  */
139 static struct tty_driver *serial_driver;
140 
141 static int  open(struct tty_struct *tty, struct file * filp);
142 static void close(struct tty_struct *tty, struct file * filp);
143 static void hangup(struct tty_struct *tty);
144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
145 
146 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
147 static int put_char(struct tty_struct *tty, unsigned char ch);
148 static void send_xchar(struct tty_struct *tty, char ch);
149 static void wait_until_sent(struct tty_struct *tty, int timeout);
150 static int  write_room(struct tty_struct *tty);
151 static void flush_chars(struct tty_struct *tty);
152 static void flush_buffer(struct tty_struct *tty);
153 static void tx_hold(struct tty_struct *tty);
154 static void tx_release(struct tty_struct *tty);
155 
156 static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
157 static int  chars_in_buffer(struct tty_struct *tty);
158 static void throttle(struct tty_struct * tty);
159 static void unthrottle(struct tty_struct * tty);
160 static int set_break(struct tty_struct *tty, int break_state);
161 
162 /*
163  * generic HDLC support and callbacks
164  */
165 #if SYNCLINK_GENERIC_HDLC
166 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
167 static void hdlcdev_tx_done(struct slgt_info *info);
168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
169 static int  hdlcdev_init(struct slgt_info *info);
170 static void hdlcdev_exit(struct slgt_info *info);
171 #endif
172 
173 
174 /*
175  * device specific structures, macros and functions
176  */
177 
178 #define SLGT_MAX_PORTS 4
179 #define SLGT_REG_SIZE  256
180 
181 /*
182  * conditional wait facility
183  */
184 struct cond_wait {
185         struct cond_wait *next;
186         wait_queue_head_t q;
187         wait_queue_t wait;
188         unsigned int data;
189 };
190 static void init_cond_wait(struct cond_wait *w, unsigned int data);
191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
193 static void flush_cond_wait(struct cond_wait **head);
194 
195 /*
196  * DMA buffer descriptor and access macros
197  */
198 struct slgt_desc
199 {
200         __le16 count;
201         __le16 status;
202         __le32 pbuf;  /* physical address of data buffer */
203         __le32 next;  /* physical address of next descriptor */
204 
205         /* driver book keeping */
206         char *buf;          /* virtual  address of data buffer */
207         unsigned int pdesc; /* physical address of this descriptor */
208         dma_addr_t buf_dma_addr;
209         unsigned short buf_count;
210 };
211 
212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
213 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
214 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
215 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
217 #define desc_count(a)      (le16_to_cpu((a).count))
218 #define desc_status(a)     (le16_to_cpu((a).status))
219 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
220 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
221 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
222 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
223 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
224 
225 struct _input_signal_events {
226         int ri_up;
227         int ri_down;
228         int dsr_up;
229         int dsr_down;
230         int dcd_up;
231         int dcd_down;
232         int cts_up;
233         int cts_down;
234 };
235 
236 /*
237  * device instance data structure
238  */
239 struct slgt_info {
240         void *if_ptr;           /* General purpose pointer (used by SPPP) */
241         struct tty_port port;
242 
243         struct slgt_info *next_device;  /* device list link */
244 
245         int magic;
246 
247         char device_name[25];
248         struct pci_dev *pdev;
249 
250         int port_count;  /* count of ports on adapter */
251         int adapter_num; /* adapter instance number */
252         int port_num;    /* port instance number */
253 
254         /* array of pointers to port contexts on this adapter */
255         struct slgt_info *port_array[SLGT_MAX_PORTS];
256 
257         int                     line;           /* tty line instance number */
258 
259         struct mgsl_icount      icount;
260 
261         int                     timeout;
262         int                     x_char;         /* xon/xoff character */
263         unsigned int            read_status_mask;
264         unsigned int            ignore_status_mask;
265 
266         wait_queue_head_t       status_event_wait_q;
267         wait_queue_head_t       event_wait_q;
268         struct timer_list       tx_timer;
269         struct timer_list       rx_timer;
270 
271         unsigned int            gpio_present;
272         struct cond_wait        *gpio_wait_q;
273 
274         spinlock_t lock;        /* spinlock for synchronizing with ISR */
275 
276         struct work_struct task;
277         u32 pending_bh;
278         bool bh_requested;
279         bool bh_running;
280 
281         int isr_overflow;
282         bool irq_requested;     /* true if IRQ requested */
283         bool irq_occurred;      /* for diagnostics use */
284 
285         /* device configuration */
286 
287         unsigned int bus_type;
288         unsigned int irq_level;
289         unsigned long irq_flags;
290 
291         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
292         u32 phys_reg_addr;
293         bool reg_addr_requested;
294 
295         MGSL_PARAMS params;       /* communications parameters */
296         u32 idle_mode;
297         u32 max_frame_size;       /* as set by device config */
298 
299         unsigned int rbuf_fill_level;
300         unsigned int rx_pio;
301         unsigned int if_mode;
302         unsigned int base_clock;
303         unsigned int xsync;
304         unsigned int xctrl;
305 
306         /* device status */
307 
308         bool rx_enabled;
309         bool rx_restart;
310 
311         bool tx_enabled;
312         bool tx_active;
313 
314         unsigned char signals;    /* serial signal states */
315         int init_error;  /* initialization error */
316 
317         unsigned char *tx_buf;
318         int tx_count;
319 
320         char *flag_buf;
321         bool drop_rts_on_tx_done;
322         struct  _input_signal_events    input_signal_events;
323 
324         int dcd_chkcount;       /* check counts to prevent */
325         int cts_chkcount;       /* too many IRQs if a signal */
326         int dsr_chkcount;       /* is floating */
327         int ri_chkcount;
328 
329         char *bufs;             /* virtual address of DMA buffer lists */
330         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
331 
332         unsigned int rbuf_count;
333         struct slgt_desc *rbufs;
334         unsigned int rbuf_current;
335         unsigned int rbuf_index;
336         unsigned int rbuf_fill_index;
337         unsigned short rbuf_fill_count;
338 
339         unsigned int tbuf_count;
340         struct slgt_desc *tbufs;
341         unsigned int tbuf_current;
342         unsigned int tbuf_start;
343 
344         unsigned char *tmp_rbuf;
345         unsigned int tmp_rbuf_count;
346 
347         /* SPPP/Cisco HDLC device parts */
348 
349         int netcount;
350         spinlock_t netlock;
351 #if SYNCLINK_GENERIC_HDLC
352         struct net_device *netdev;
353 #endif
354 
355 };
356 
357 static MGSL_PARAMS default_params = {
358         .mode            = MGSL_MODE_HDLC,
359         .loopback        = 0,
360         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
361         .encoding        = HDLC_ENCODING_NRZI_SPACE,
362         .clock_speed     = 0,
363         .addr_filter     = 0xff,
364         .crc_type        = HDLC_CRC_16_CCITT,
365         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
366         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
367         .data_rate       = 9600,
368         .data_bits       = 8,
369         .stop_bits       = 1,
370         .parity          = ASYNC_PARITY_NONE
371 };
372 
373 
374 #define BH_RECEIVE  1
375 #define BH_TRANSMIT 2
376 #define BH_STATUS   4
377 #define IO_PIN_SHUTDOWN_LIMIT 100
378 
379 #define DMABUFSIZE 256
380 #define DESC_LIST_SIZE 4096
381 
382 #define MASK_PARITY  BIT1
383 #define MASK_FRAMING BIT0
384 #define MASK_BREAK   BIT14
385 #define MASK_OVERRUN BIT4
386 
387 #define GSR   0x00 /* global status */
388 #define JCR   0x04 /* JTAG control */
389 #define IODR  0x08 /* GPIO direction */
390 #define IOER  0x0c /* GPIO interrupt enable */
391 #define IOVR  0x10 /* GPIO value */
392 #define IOSR  0x14 /* GPIO interrupt status */
393 #define TDR   0x80 /* tx data */
394 #define RDR   0x80 /* rx data */
395 #define TCR   0x82 /* tx control */
396 #define TIR   0x84 /* tx idle */
397 #define TPR   0x85 /* tx preamble */
398 #define RCR   0x86 /* rx control */
399 #define VCR   0x88 /* V.24 control */
400 #define CCR   0x89 /* clock control */
401 #define BDR   0x8a /* baud divisor */
402 #define SCR   0x8c /* serial control */
403 #define SSR   0x8e /* serial status */
404 #define RDCSR 0x90 /* rx DMA control/status */
405 #define TDCSR 0x94 /* tx DMA control/status */
406 #define RDDAR 0x98 /* rx DMA descriptor address */
407 #define TDDAR 0x9c /* tx DMA descriptor address */
408 #define XSR   0x40 /* extended sync pattern */
409 #define XCR   0x44 /* extended control */
410 
411 #define RXIDLE      BIT14
412 #define RXBREAK     BIT14
413 #define IRQ_TXDATA  BIT13
414 #define IRQ_TXIDLE  BIT12
415 #define IRQ_TXUNDER BIT11 /* HDLC */
416 #define IRQ_RXDATA  BIT10
417 #define IRQ_RXIDLE  BIT9  /* HDLC */
418 #define IRQ_RXBREAK BIT9  /* async */
419 #define IRQ_RXOVER  BIT8
420 #define IRQ_DSR     BIT7
421 #define IRQ_CTS     BIT6
422 #define IRQ_DCD     BIT5
423 #define IRQ_RI      BIT4
424 #define IRQ_ALL     0x3ff0
425 #define IRQ_MASTER  BIT0
426 
427 #define slgt_irq_on(info, mask) \
428         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
429 #define slgt_irq_off(info, mask) \
430         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
431 
432 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
433 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
435 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
437 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
438 
439 static void  msc_set_vcr(struct slgt_info *info);
440 
441 static int  startup(struct slgt_info *info);
442 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
443 static void shutdown(struct slgt_info *info);
444 static void program_hw(struct slgt_info *info);
445 static void change_params(struct slgt_info *info);
446 
447 static int  register_test(struct slgt_info *info);
448 static int  irq_test(struct slgt_info *info);
449 static int  loopback_test(struct slgt_info *info);
450 static int  adapter_test(struct slgt_info *info);
451 
452 static void reset_adapter(struct slgt_info *info);
453 static void reset_port(struct slgt_info *info);
454 static void async_mode(struct slgt_info *info);
455 static void sync_mode(struct slgt_info *info);
456 
457 static void rx_stop(struct slgt_info *info);
458 static void rx_start(struct slgt_info *info);
459 static void reset_rbufs(struct slgt_info *info);
460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
461 static void rdma_reset(struct slgt_info *info);
462 static bool rx_get_frame(struct slgt_info *info);
463 static bool rx_get_buf(struct slgt_info *info);
464 
465 static void tx_start(struct slgt_info *info);
466 static void tx_stop(struct slgt_info *info);
467 static void tx_set_idle(struct slgt_info *info);
468 static unsigned int free_tbuf_count(struct slgt_info *info);
469 static unsigned int tbuf_bytes(struct slgt_info *info);
470 static void reset_tbufs(struct slgt_info *info);
471 static void tdma_reset(struct slgt_info *info);
472 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
473 
474 static void get_signals(struct slgt_info *info);
475 static void set_signals(struct slgt_info *info);
476 static void enable_loopback(struct slgt_info *info);
477 static void set_rate(struct slgt_info *info, u32 data_rate);
478 
479 static int  bh_action(struct slgt_info *info);
480 static void bh_handler(struct work_struct *work);
481 static void bh_transmit(struct slgt_info *info);
482 static void isr_serial(struct slgt_info *info);
483 static void isr_rdma(struct slgt_info *info);
484 static void isr_txeom(struct slgt_info *info, unsigned short status);
485 static void isr_tdma(struct slgt_info *info);
486 
487 static int  alloc_dma_bufs(struct slgt_info *info);
488 static void free_dma_bufs(struct slgt_info *info);
489 static int  alloc_desc(struct slgt_info *info);
490 static void free_desc(struct slgt_info *info);
491 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
493 
494 static int  alloc_tmp_rbuf(struct slgt_info *info);
495 static void free_tmp_rbuf(struct slgt_info *info);
496 
497 static void tx_timeout(unsigned long context);
498 static void rx_timeout(unsigned long context);
499 
500 /*
501  * ioctl handlers
502  */
503 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
504 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
506 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
507 static int  set_txidle(struct slgt_info *info, int idle_mode);
508 static int  tx_enable(struct slgt_info *info, int enable);
509 static int  tx_abort(struct slgt_info *info);
510 static int  rx_enable(struct slgt_info *info, int enable);
511 static int  modem_input_wait(struct slgt_info *info,int arg);
512 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
513 static int  tiocmget(struct tty_struct *tty);
514 static int  tiocmset(struct tty_struct *tty,
515                                 unsigned int set, unsigned int clear);
516 static int set_break(struct tty_struct *tty, int break_state);
517 static int  get_interface(struct slgt_info *info, int __user *if_mode);
518 static int  set_interface(struct slgt_info *info, int if_mode);
519 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
522 static int  get_xsync(struct slgt_info *info, int __user *if_mode);
523 static int  set_xsync(struct slgt_info *info, int if_mode);
524 static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
525 static int  set_xctrl(struct slgt_info *info, int if_mode);
526 
527 /*
528  * driver functions
529  */
530 static void add_device(struct slgt_info *info);
531 static void device_init(int adapter_num, struct pci_dev *pdev);
532 static int  claim_resources(struct slgt_info *info);
533 static void release_resources(struct slgt_info *info);
534 
535 /*
536  * DEBUG OUTPUT CODE
537  */
538 #ifndef DBGINFO
539 #define DBGINFO(fmt)
540 #endif
541 #ifndef DBGERR
542 #define DBGERR(fmt)
543 #endif
544 #ifndef DBGBH
545 #define DBGBH(fmt)
546 #endif
547 #ifndef DBGISR
548 #define DBGISR(fmt)
549 #endif
550 
551 #ifdef DBGDATA
552 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
553 {
554         int i;
555         int linecount;
556         printk("%s %s data:\n",info->device_name, label);
557         while(count) {
558                 linecount = (count > 16) ? 16 : count;
559                 for(i=0; i < linecount; i++)
560                         printk("%02X ",(unsigned char)data[i]);
561                 for(;i<17;i++)
562                         printk("   ");
563                 for(i=0;i<linecount;i++) {
564                         if (data[i]>=040 && data[i]<=0176)
565                                 printk("%c",data[i]);
566                         else
567                                 printk(".");
568                 }
569                 printk("\n");
570                 data  += linecount;
571                 count -= linecount;
572         }
573 }
574 #else
575 #define DBGDATA(info, buf, size, label)
576 #endif
577 
578 #ifdef DBGTBUF
579 static void dump_tbufs(struct slgt_info *info)
580 {
581         int i;
582         printk("tbuf_current=%d\n", info->tbuf_current);
583         for (i=0 ; i < info->tbuf_count ; i++) {
584                 printk("%d: count=%04X status=%04X\n",
585                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
586         }
587 }
588 #else
589 #define DBGTBUF(info)
590 #endif
591 
592 #ifdef DBGRBUF
593 static void dump_rbufs(struct slgt_info *info)
594 {
595         int i;
596         printk("rbuf_current=%d\n", info->rbuf_current);
597         for (i=0 ; i < info->rbuf_count ; i++) {
598                 printk("%d: count=%04X status=%04X\n",
599                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
600         }
601 }
602 #else
603 #define DBGRBUF(info)
604 #endif
605 
606 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
607 {
608 #ifdef SANITY_CHECK
609         if (!info) {
610                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
611                 return 1;
612         }
613         if (info->magic != MGSL_MAGIC) {
614                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
615                 return 1;
616         }
617 #else
618         if (!info)
619                 return 1;
620 #endif
621         return 0;
622 }
623 
624 /**
625  * line discipline callback wrappers
626  *
627  * The wrappers maintain line discipline references
628  * while calling into the line discipline.
629  *
630  * ldisc_receive_buf  - pass receive data to line discipline
631  */
632 static void ldisc_receive_buf(struct tty_struct *tty,
633                               const __u8 *data, char *flags, int count)
634 {
635         struct tty_ldisc *ld;
636         if (!tty)
637                 return;
638         ld = tty_ldisc_ref(tty);
639         if (ld) {
640                 if (ld->ops->receive_buf)
641                         ld->ops->receive_buf(tty, data, flags, count);
642                 tty_ldisc_deref(ld);
643         }
644 }
645 
646 /* tty callbacks */
647 
648 static int open(struct tty_struct *tty, struct file *filp)
649 {
650         struct slgt_info *info;
651         int retval, line;
652         unsigned long flags;
653 
654         line = tty->index;
655         if (line >= slgt_device_count) {
656                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
657                 return -ENODEV;
658         }
659 
660         info = slgt_device_list;
661         while(info && info->line != line)
662                 info = info->next_device;
663         if (sanity_check(info, tty->name, "open"))
664                 return -ENODEV;
665         if (info->init_error) {
666                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
667                 return -ENODEV;
668         }
669 
670         tty->driver_data = info;
671         info->port.tty = tty;
672 
673         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
674 
675         mutex_lock(&info->port.mutex);
676         info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
677 
678         spin_lock_irqsave(&info->netlock, flags);
679         if (info->netcount) {
680                 retval = -EBUSY;
681                 spin_unlock_irqrestore(&info->netlock, flags);
682                 mutex_unlock(&info->port.mutex);
683                 goto cleanup;
684         }
685         info->port.count++;
686         spin_unlock_irqrestore(&info->netlock, flags);
687 
688         if (info->port.count == 1) {
689                 /* 1st open on this device, init hardware */
690                 retval = startup(info);
691                 if (retval < 0) {
692                         mutex_unlock(&info->port.mutex);
693                         goto cleanup;
694                 }
695         }
696         mutex_unlock(&info->port.mutex);
697         retval = block_til_ready(tty, filp, info);
698         if (retval) {
699                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
700                 goto cleanup;
701         }
702 
703         retval = 0;
704 
705 cleanup:
706         if (retval) {
707                 if (tty->count == 1)
708                         info->port.tty = NULL; /* tty layer will release tty struct */
709                 if(info->port.count)
710                         info->port.count--;
711         }
712 
713         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
714         return retval;
715 }
716 
717 static void close(struct tty_struct *tty, struct file *filp)
718 {
719         struct slgt_info *info = tty->driver_data;
720 
721         if (sanity_check(info, tty->name, "close"))
722                 return;
723         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
724 
725         if (tty_port_close_start(&info->port, tty, filp) == 0)
726                 goto cleanup;
727 
728         mutex_lock(&info->port.mutex);
729         if (tty_port_initialized(&info->port))
730                 wait_until_sent(tty, info->timeout);
731         flush_buffer(tty);
732         tty_ldisc_flush(tty);
733 
734         shutdown(info);
735         mutex_unlock(&info->port.mutex);
736 
737         tty_port_close_end(&info->port, tty);
738         info->port.tty = NULL;
739 cleanup:
740         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
741 }
742 
743 static void hangup(struct tty_struct *tty)
744 {
745         struct slgt_info *info = tty->driver_data;
746         unsigned long flags;
747 
748         if (sanity_check(info, tty->name, "hangup"))
749                 return;
750         DBGINFO(("%s hangup\n", info->device_name));
751 
752         flush_buffer(tty);
753 
754         mutex_lock(&info->port.mutex);
755         shutdown(info);
756 
757         spin_lock_irqsave(&info->port.lock, flags);
758         info->port.count = 0;
759         info->port.tty = NULL;
760         spin_unlock_irqrestore(&info->port.lock, flags);
761         tty_port_set_active(&info->port, 0);
762         mutex_unlock(&info->port.mutex);
763 
764         wake_up_interruptible(&info->port.open_wait);
765 }
766 
767 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
768 {
769         struct slgt_info *info = tty->driver_data;
770         unsigned long flags;
771 
772         DBGINFO(("%s set_termios\n", tty->driver->name));
773 
774         change_params(info);
775 
776         /* Handle transition to B0 status */
777         if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
778                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
779                 spin_lock_irqsave(&info->lock,flags);
780                 set_signals(info);
781                 spin_unlock_irqrestore(&info->lock,flags);
782         }
783 
784         /* Handle transition away from B0 status */
785         if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
786                 info->signals |= SerialSignal_DTR;
787                 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
788                         info->signals |= SerialSignal_RTS;
789                 spin_lock_irqsave(&info->lock,flags);
790                 set_signals(info);
791                 spin_unlock_irqrestore(&info->lock,flags);
792         }
793 
794         /* Handle turning off CRTSCTS */
795         if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
796                 tty->hw_stopped = 0;
797                 tx_release(tty);
798         }
799 }
800 
801 static void update_tx_timer(struct slgt_info *info)
802 {
803         /*
804          * use worst case speed of 1200bps to calculate transmit timeout
805          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
806          */
807         if (info->params.mode == MGSL_MODE_HDLC) {
808                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
809                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
810         }
811 }
812 
813 static int write(struct tty_struct *tty,
814                  const unsigned char *buf, int count)
815 {
816         int ret = 0;
817         struct slgt_info *info = tty->driver_data;
818         unsigned long flags;
819 
820         if (sanity_check(info, tty->name, "write"))
821                 return -EIO;
822 
823         DBGINFO(("%s write count=%d\n", info->device_name, count));
824 
825         if (!info->tx_buf || (count > info->max_frame_size))
826                 return -EIO;
827 
828         if (!count || tty->stopped || tty->hw_stopped)
829                 return 0;
830 
831         spin_lock_irqsave(&info->lock, flags);
832 
833         if (info->tx_count) {
834                 /* send accumulated data from send_char() */
835                 if (!tx_load(info, info->tx_buf, info->tx_count))
836                         goto cleanup;
837                 info->tx_count = 0;
838         }
839 
840         if (tx_load(info, buf, count))
841                 ret = count;
842 
843 cleanup:
844         spin_unlock_irqrestore(&info->lock, flags);
845         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
846         return ret;
847 }
848 
849 static int put_char(struct tty_struct *tty, unsigned char ch)
850 {
851         struct slgt_info *info = tty->driver_data;
852         unsigned long flags;
853         int ret = 0;
854 
855         if (sanity_check(info, tty->name, "put_char"))
856                 return 0;
857         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
858         if (!info->tx_buf)
859                 return 0;
860         spin_lock_irqsave(&info->lock,flags);
861         if (info->tx_count < info->max_frame_size) {
862                 info->tx_buf[info->tx_count++] = ch;
863                 ret = 1;
864         }
865         spin_unlock_irqrestore(&info->lock,flags);
866         return ret;
867 }
868 
869 static void send_xchar(struct tty_struct *tty, char ch)
870 {
871         struct slgt_info *info = tty->driver_data;
872         unsigned long flags;
873 
874         if (sanity_check(info, tty->name, "send_xchar"))
875                 return;
876         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
877         info->x_char = ch;
878         if (ch) {
879                 spin_lock_irqsave(&info->lock,flags);
880                 if (!info->tx_enabled)
881                         tx_start(info);
882                 spin_unlock_irqrestore(&info->lock,flags);
883         }
884 }
885 
886 static void wait_until_sent(struct tty_struct *tty, int timeout)
887 {
888         struct slgt_info *info = tty->driver_data;
889         unsigned long orig_jiffies, char_time;
890 
891         if (!info )
892                 return;
893         if (sanity_check(info, tty->name, "wait_until_sent"))
894                 return;
895         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
896         if (!tty_port_initialized(&info->port))
897                 goto exit;
898 
899         orig_jiffies = jiffies;
900 
901         /* Set check interval to 1/5 of estimated time to
902          * send a character, and make it at least 1. The check
903          * interval should also be less than the timeout.
904          * Note: use tight timings here to satisfy the NIST-PCTS.
905          */
906 
907         if (info->params.data_rate) {
908                 char_time = info->timeout/(32 * 5);
909                 if (!char_time)
910                         char_time++;
911         } else
912                 char_time = 1;
913 
914         if (timeout)
915                 char_time = min_t(unsigned long, char_time, timeout);
916 
917         while (info->tx_active) {
918                 msleep_interruptible(jiffies_to_msecs(char_time));
919                 if (signal_pending(current))
920                         break;
921                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
922                         break;
923         }
924 exit:
925         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
926 }
927 
928 static int write_room(struct tty_struct *tty)
929 {
930         struct slgt_info *info = tty->driver_data;
931         int ret;
932 
933         if (sanity_check(info, tty->name, "write_room"))
934                 return 0;
935         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
936         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
937         return ret;
938 }
939 
940 static void flush_chars(struct tty_struct *tty)
941 {
942         struct slgt_info *info = tty->driver_data;
943         unsigned long flags;
944 
945         if (sanity_check(info, tty->name, "flush_chars"))
946                 return;
947         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
948 
949         if (info->tx_count <= 0 || tty->stopped ||
950             tty->hw_stopped || !info->tx_buf)
951                 return;
952 
953         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
954 
955         spin_lock_irqsave(&info->lock,flags);
956         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
957                 info->tx_count = 0;
958         spin_unlock_irqrestore(&info->lock,flags);
959 }
960 
961 static void flush_buffer(struct tty_struct *tty)
962 {
963         struct slgt_info *info = tty->driver_data;
964         unsigned long flags;
965 
966         if (sanity_check(info, tty->name, "flush_buffer"))
967                 return;
968         DBGINFO(("%s flush_buffer\n", info->device_name));
969 
970         spin_lock_irqsave(&info->lock, flags);
971         info->tx_count = 0;
972         spin_unlock_irqrestore(&info->lock, flags);
973 
974         tty_wakeup(tty);
975 }
976 
977 /*
978  * throttle (stop) transmitter
979  */
980 static void tx_hold(struct tty_struct *tty)
981 {
982         struct slgt_info *info = tty->driver_data;
983         unsigned long flags;
984 
985         if (sanity_check(info, tty->name, "tx_hold"))
986                 return;
987         DBGINFO(("%s tx_hold\n", info->device_name));
988         spin_lock_irqsave(&info->lock,flags);
989         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
990                 tx_stop(info);
991         spin_unlock_irqrestore(&info->lock,flags);
992 }
993 
994 /*
995  * release (start) transmitter
996  */
997 static void tx_release(struct tty_struct *tty)
998 {
999         struct slgt_info *info = tty->driver_data;
1000         unsigned long flags;
1001 
1002         if (sanity_check(info, tty->name, "tx_release"))
1003                 return;
1004         DBGINFO(("%s tx_release\n", info->device_name));
1005         spin_lock_irqsave(&info->lock, flags);
1006         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1007                 info->tx_count = 0;
1008         spin_unlock_irqrestore(&info->lock, flags);
1009 }
1010 
1011 /*
1012  * Service an IOCTL request
1013  *
1014  * Arguments
1015  *
1016  *      tty     pointer to tty instance data
1017  *      cmd     IOCTL command code
1018  *      arg     command argument/context
1019  *
1020  * Return 0 if success, otherwise error code
1021  */
1022 static int ioctl(struct tty_struct *tty,
1023                  unsigned int cmd, unsigned long arg)
1024 {
1025         struct slgt_info *info = tty->driver_data;
1026         void __user *argp = (void __user *)arg;
1027         int ret;
1028 
1029         if (sanity_check(info, tty->name, "ioctl"))
1030                 return -ENODEV;
1031         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1032 
1033         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1034             (cmd != TIOCMIWAIT)) {
1035                 if (tty_io_error(tty))
1036                     return -EIO;
1037         }
1038 
1039         switch (cmd) {
1040         case MGSL_IOCWAITEVENT:
1041                 return wait_mgsl_event(info, argp);
1042         case TIOCMIWAIT:
1043                 return modem_input_wait(info,(int)arg);
1044         case MGSL_IOCSGPIO:
1045                 return set_gpio(info, argp);
1046         case MGSL_IOCGGPIO:
1047                 return get_gpio(info, argp);
1048         case MGSL_IOCWAITGPIO:
1049                 return wait_gpio(info, argp);
1050         case MGSL_IOCGXSYNC:
1051                 return get_xsync(info, argp);
1052         case MGSL_IOCSXSYNC:
1053                 return set_xsync(info, (int)arg);
1054         case MGSL_IOCGXCTRL:
1055                 return get_xctrl(info, argp);
1056         case MGSL_IOCSXCTRL:
1057                 return set_xctrl(info, (int)arg);
1058         }
1059         mutex_lock(&info->port.mutex);
1060         switch (cmd) {
1061         case MGSL_IOCGPARAMS:
1062                 ret = get_params(info, argp);
1063                 break;
1064         case MGSL_IOCSPARAMS:
1065                 ret = set_params(info, argp);
1066                 break;
1067         case MGSL_IOCGTXIDLE:
1068                 ret = get_txidle(info, argp);
1069                 break;
1070         case MGSL_IOCSTXIDLE:
1071                 ret = set_txidle(info, (int)arg);
1072                 break;
1073         case MGSL_IOCTXENABLE:
1074                 ret = tx_enable(info, (int)arg);
1075                 break;
1076         case MGSL_IOCRXENABLE:
1077                 ret = rx_enable(info, (int)arg);
1078                 break;
1079         case MGSL_IOCTXABORT:
1080                 ret = tx_abort(info);
1081                 break;
1082         case MGSL_IOCGSTATS:
1083                 ret = get_stats(info, argp);
1084                 break;
1085         case MGSL_IOCGIF:
1086                 ret = get_interface(info, argp);
1087                 break;
1088         case MGSL_IOCSIF:
1089                 ret = set_interface(info,(int)arg);
1090                 break;
1091         default:
1092                 ret = -ENOIOCTLCMD;
1093         }
1094         mutex_unlock(&info->port.mutex);
1095         return ret;
1096 }
1097 
1098 static int get_icount(struct tty_struct *tty,
1099                                 struct serial_icounter_struct *icount)
1100 
1101 {
1102         struct slgt_info *info = tty->driver_data;
1103         struct mgsl_icount cnow;        /* kernel counter temps */
1104         unsigned long flags;
1105 
1106         spin_lock_irqsave(&info->lock,flags);
1107         cnow = info->icount;
1108         spin_unlock_irqrestore(&info->lock,flags);
1109 
1110         icount->cts = cnow.cts;
1111         icount->dsr = cnow.dsr;
1112         icount->rng = cnow.rng;
1113         icount->dcd = cnow.dcd;
1114         icount->rx = cnow.rx;
1115         icount->tx = cnow.tx;
1116         icount->frame = cnow.frame;
1117         icount->overrun = cnow.overrun;
1118         icount->parity = cnow.parity;
1119         icount->brk = cnow.brk;
1120         icount->buf_overrun = cnow.buf_overrun;
1121 
1122         return 0;
1123 }
1124 
1125 /*
1126  * support for 32 bit ioctl calls on 64 bit systems
1127  */
1128 #ifdef CONFIG_COMPAT
1129 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1130 {
1131         struct MGSL_PARAMS32 tmp_params;
1132 
1133         DBGINFO(("%s get_params32\n", info->device_name));
1134         memset(&tmp_params, 0, sizeof(tmp_params));
1135         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1136         tmp_params.loopback        = info->params.loopback;
1137         tmp_params.flags           = info->params.flags;
1138         tmp_params.encoding        = info->params.encoding;
1139         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1140         tmp_params.addr_filter     = info->params.addr_filter;
1141         tmp_params.crc_type        = info->params.crc_type;
1142         tmp_params.preamble_length = info->params.preamble_length;
1143         tmp_params.preamble        = info->params.preamble;
1144         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1145         tmp_params.data_bits       = info->params.data_bits;
1146         tmp_params.stop_bits       = info->params.stop_bits;
1147         tmp_params.parity          = info->params.parity;
1148         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1149                 return -EFAULT;
1150         return 0;
1151 }
1152 
1153 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1154 {
1155         struct MGSL_PARAMS32 tmp_params;
1156 
1157         DBGINFO(("%s set_params32\n", info->device_name));
1158         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1159                 return -EFAULT;
1160 
1161         spin_lock(&info->lock);
1162         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1163                 info->base_clock = tmp_params.clock_speed;
1164         } else {
1165                 info->params.mode            = tmp_params.mode;
1166                 info->params.loopback        = tmp_params.loopback;
1167                 info->params.flags           = tmp_params.flags;
1168                 info->params.encoding        = tmp_params.encoding;
1169                 info->params.clock_speed     = tmp_params.clock_speed;
1170                 info->params.addr_filter     = tmp_params.addr_filter;
1171                 info->params.crc_type        = tmp_params.crc_type;
1172                 info->params.preamble_length = tmp_params.preamble_length;
1173                 info->params.preamble        = tmp_params.preamble;
1174                 info->params.data_rate       = tmp_params.data_rate;
1175                 info->params.data_bits       = tmp_params.data_bits;
1176                 info->params.stop_bits       = tmp_params.stop_bits;
1177                 info->params.parity          = tmp_params.parity;
1178         }
1179         spin_unlock(&info->lock);
1180 
1181         program_hw(info);
1182 
1183         return 0;
1184 }
1185 
1186 static long slgt_compat_ioctl(struct tty_struct *tty,
1187                          unsigned int cmd, unsigned long arg)
1188 {
1189         struct slgt_info *info = tty->driver_data;
1190         int rc = -ENOIOCTLCMD;
1191 
1192         if (sanity_check(info, tty->name, "compat_ioctl"))
1193                 return -ENODEV;
1194         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1195 
1196         switch (cmd) {
1197 
1198         case MGSL_IOCSPARAMS32:
1199                 rc = set_params32(info, compat_ptr(arg));
1200                 break;
1201 
1202         case MGSL_IOCGPARAMS32:
1203                 rc = get_params32(info, compat_ptr(arg));
1204                 break;
1205 
1206         case MGSL_IOCGPARAMS:
1207         case MGSL_IOCSPARAMS:
1208         case MGSL_IOCGTXIDLE:
1209         case MGSL_IOCGSTATS:
1210         case MGSL_IOCWAITEVENT:
1211         case MGSL_IOCGIF:
1212         case MGSL_IOCSGPIO:
1213         case MGSL_IOCGGPIO:
1214         case MGSL_IOCWAITGPIO:
1215         case MGSL_IOCGXSYNC:
1216         case MGSL_IOCGXCTRL:
1217         case MGSL_IOCSTXIDLE:
1218         case MGSL_IOCTXENABLE:
1219         case MGSL_IOCRXENABLE:
1220         case MGSL_IOCTXABORT:
1221         case TIOCMIWAIT:
1222         case MGSL_IOCSIF:
1223         case MGSL_IOCSXSYNC:
1224         case MGSL_IOCSXCTRL:
1225                 rc = ioctl(tty, cmd, arg);
1226                 break;
1227         }
1228 
1229         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1230         return rc;
1231 }
1232 #else
1233 #define slgt_compat_ioctl NULL
1234 #endif /* ifdef CONFIG_COMPAT */
1235 
1236 /*
1237  * proc fs support
1238  */
1239 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1240 {
1241         char stat_buf[30];
1242         unsigned long flags;
1243 
1244         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1245                       info->device_name, info->phys_reg_addr,
1246                       info->irq_level, info->max_frame_size);
1247 
1248         /* output current serial signal states */
1249         spin_lock_irqsave(&info->lock,flags);
1250         get_signals(info);
1251         spin_unlock_irqrestore(&info->lock,flags);
1252 
1253         stat_buf[0] = 0;
1254         stat_buf[1] = 0;
1255         if (info->signals & SerialSignal_RTS)
1256                 strcat(stat_buf, "|RTS");
1257         if (info->signals & SerialSignal_CTS)
1258                 strcat(stat_buf, "|CTS");
1259         if (info->signals & SerialSignal_DTR)
1260                 strcat(stat_buf, "|DTR");
1261         if (info->signals & SerialSignal_DSR)
1262                 strcat(stat_buf, "|DSR");
1263         if (info->signals & SerialSignal_DCD)
1264                 strcat(stat_buf, "|CD");
1265         if (info->signals & SerialSignal_RI)
1266                 strcat(stat_buf, "|RI");
1267 
1268         if (info->params.mode != MGSL_MODE_ASYNC) {
1269                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1270                                info->icount.txok, info->icount.rxok);
1271                 if (info->icount.txunder)
1272                         seq_printf(m, " txunder:%d", info->icount.txunder);
1273                 if (info->icount.txabort)
1274                         seq_printf(m, " txabort:%d", info->icount.txabort);
1275                 if (info->icount.rxshort)
1276                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1277                 if (info->icount.rxlong)
1278                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1279                 if (info->icount.rxover)
1280                         seq_printf(m, " rxover:%d", info->icount.rxover);
1281                 if (info->icount.rxcrc)
1282                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1283         } else {
1284                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1285                                info->icount.tx, info->icount.rx);
1286                 if (info->icount.frame)
1287                         seq_printf(m, " fe:%d", info->icount.frame);
1288                 if (info->icount.parity)
1289                         seq_printf(m, " pe:%d", info->icount.parity);
1290                 if (info->icount.brk)
1291                         seq_printf(m, " brk:%d", info->icount.brk);
1292                 if (info->icount.overrun)
1293                         seq_printf(m, " oe:%d", info->icount.overrun);
1294         }
1295 
1296         /* Append serial signal status to end */
1297         seq_printf(m, " %s\n", stat_buf+1);
1298 
1299         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1300                        info->tx_active,info->bh_requested,info->bh_running,
1301                        info->pending_bh);
1302 }
1303 
1304 /* Called to print information about devices
1305  */
1306 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1307 {
1308         struct slgt_info *info;
1309 
1310         seq_puts(m, "synclink_gt driver\n");
1311 
1312         info = slgt_device_list;
1313         while( info ) {
1314                 line_info(m, info);
1315                 info = info->next_device;
1316         }
1317         return 0;
1318 }
1319 
1320 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1321 {
1322         return single_open(file, synclink_gt_proc_show, NULL);
1323 }
1324 
1325 static const struct file_operations synclink_gt_proc_fops = {
1326         .owner          = THIS_MODULE,
1327         .open           = synclink_gt_proc_open,
1328         .read           = seq_read,
1329         .llseek         = seq_lseek,
1330         .release        = single_release,
1331 };
1332 
1333 /*
1334  * return count of bytes in transmit buffer
1335  */
1336 static int chars_in_buffer(struct tty_struct *tty)
1337 {
1338         struct slgt_info *info = tty->driver_data;
1339         int count;
1340         if (sanity_check(info, tty->name, "chars_in_buffer"))
1341                 return 0;
1342         count = tbuf_bytes(info);
1343         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1344         return count;
1345 }
1346 
1347 /*
1348  * signal remote device to throttle send data (our receive data)
1349  */
1350 static void throttle(struct tty_struct * tty)
1351 {
1352         struct slgt_info *info = tty->driver_data;
1353         unsigned long flags;
1354 
1355         if (sanity_check(info, tty->name, "throttle"))
1356                 return;
1357         DBGINFO(("%s throttle\n", info->device_name));
1358         if (I_IXOFF(tty))
1359                 send_xchar(tty, STOP_CHAR(tty));
1360         if (C_CRTSCTS(tty)) {
1361                 spin_lock_irqsave(&info->lock,flags);
1362                 info->signals &= ~SerialSignal_RTS;
1363                 set_signals(info);
1364                 spin_unlock_irqrestore(&info->lock,flags);
1365         }
1366 }
1367 
1368 /*
1369  * signal remote device to stop throttling send data (our receive data)
1370  */
1371 static void unthrottle(struct tty_struct * tty)
1372 {
1373         struct slgt_info *info = tty->driver_data;
1374         unsigned long flags;
1375 
1376         if (sanity_check(info, tty->name, "unthrottle"))
1377                 return;
1378         DBGINFO(("%s unthrottle\n", info->device_name));
1379         if (I_IXOFF(tty)) {
1380                 if (info->x_char)
1381                         info->x_char = 0;
1382                 else
1383                         send_xchar(tty, START_CHAR(tty));
1384         }
1385         if (C_CRTSCTS(tty)) {
1386                 spin_lock_irqsave(&info->lock,flags);
1387                 info->signals |= SerialSignal_RTS;
1388                 set_signals(info);
1389                 spin_unlock_irqrestore(&info->lock,flags);
1390         }
1391 }
1392 
1393 /*
1394  * set or clear transmit break condition
1395  * break_state  -1=set break condition, 0=clear
1396  */
1397 static int set_break(struct tty_struct *tty, int break_state)
1398 {
1399         struct slgt_info *info = tty->driver_data;
1400         unsigned short value;
1401         unsigned long flags;
1402 
1403         if (sanity_check(info, tty->name, "set_break"))
1404                 return -EINVAL;
1405         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1406 
1407         spin_lock_irqsave(&info->lock,flags);
1408         value = rd_reg16(info, TCR);
1409         if (break_state == -1)
1410                 value |= BIT6;
1411         else
1412                 value &= ~BIT6;
1413         wr_reg16(info, TCR, value);
1414         spin_unlock_irqrestore(&info->lock,flags);
1415         return 0;
1416 }
1417 
1418 #if SYNCLINK_GENERIC_HDLC
1419 
1420 /**
1421  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1422  * set encoding and frame check sequence (FCS) options
1423  *
1424  * dev       pointer to network device structure
1425  * encoding  serial encoding setting
1426  * parity    FCS setting
1427  *
1428  * returns 0 if success, otherwise error code
1429  */
1430 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1431                           unsigned short parity)
1432 {
1433         struct slgt_info *info = dev_to_port(dev);
1434         unsigned char  new_encoding;
1435         unsigned short new_crctype;
1436 
1437         /* return error if TTY interface open */
1438         if (info->port.count)
1439                 return -EBUSY;
1440 
1441         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1442 
1443         switch (encoding)
1444         {
1445         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1446         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1447         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1448         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1449         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1450         default: return -EINVAL;
1451         }
1452 
1453         switch (parity)
1454         {
1455         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1456         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1457         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1458         default: return -EINVAL;
1459         }
1460 
1461         info->params.encoding = new_encoding;
1462         info->params.crc_type = new_crctype;
1463 
1464         /* if network interface up, reprogram hardware */
1465         if (info->netcount)
1466                 program_hw(info);
1467 
1468         return 0;
1469 }
1470 
1471 /**
1472  * called by generic HDLC layer to send frame
1473  *
1474  * skb  socket buffer containing HDLC frame
1475  * dev  pointer to network device structure
1476  */
1477 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1478                                       struct net_device *dev)
1479 {
1480         struct slgt_info *info = dev_to_port(dev);
1481         unsigned long flags;
1482 
1483         DBGINFO(("%s hdlc_xmit\n", dev->name));
1484 
1485         if (!skb->len)
1486                 return NETDEV_TX_OK;
1487 
1488         /* stop sending until this frame completes */
1489         netif_stop_queue(dev);
1490 
1491         /* update network statistics */
1492         dev->stats.tx_packets++;
1493         dev->stats.tx_bytes += skb->len;
1494 
1495         /* save start time for transmit timeout detection */
1496         netif_trans_update(dev);
1497 
1498         spin_lock_irqsave(&info->lock, flags);
1499         tx_load(info, skb->data, skb->len);
1500         spin_unlock_irqrestore(&info->lock, flags);
1501 
1502         /* done with socket buffer, so free it */
1503         dev_kfree_skb(skb);
1504 
1505         return NETDEV_TX_OK;
1506 }
1507 
1508 /**
1509  * called by network layer when interface enabled
1510  * claim resources and initialize hardware
1511  *
1512  * dev  pointer to network device structure
1513  *
1514  * returns 0 if success, otherwise error code
1515  */
1516 static int hdlcdev_open(struct net_device *dev)
1517 {
1518         struct slgt_info *info = dev_to_port(dev);
1519         int rc;
1520         unsigned long flags;
1521 
1522         if (!try_module_get(THIS_MODULE))
1523                 return -EBUSY;
1524 
1525         DBGINFO(("%s hdlcdev_open\n", dev->name));
1526 
1527         /* generic HDLC layer open processing */
1528         rc = hdlc_open(dev);
1529         if (rc)
1530                 return rc;
1531 
1532         /* arbitrate between network and tty opens */
1533         spin_lock_irqsave(&info->netlock, flags);
1534         if (info->port.count != 0 || info->netcount != 0) {
1535                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1536                 spin_unlock_irqrestore(&info->netlock, flags);
1537                 return -EBUSY;
1538         }
1539         info->netcount=1;
1540         spin_unlock_irqrestore(&info->netlock, flags);
1541 
1542         /* claim resources and init adapter */
1543         if ((rc = startup(info)) != 0) {
1544                 spin_lock_irqsave(&info->netlock, flags);
1545                 info->netcount=0;
1546                 spin_unlock_irqrestore(&info->netlock, flags);
1547                 return rc;
1548         }
1549 
1550         /* assert RTS and DTR, apply hardware settings */
1551         info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1552         program_hw(info);
1553 
1554         /* enable network layer transmit */
1555         netif_trans_update(dev);
1556         netif_start_queue(dev);
1557 
1558         /* inform generic HDLC layer of current DCD status */
1559         spin_lock_irqsave(&info->lock, flags);
1560         get_signals(info);
1561         spin_unlock_irqrestore(&info->lock, flags);
1562         if (info->signals & SerialSignal_DCD)
1563                 netif_carrier_on(dev);
1564         else
1565                 netif_carrier_off(dev);
1566         return 0;
1567 }
1568 
1569 /**
1570  * called by network layer when interface is disabled
1571  * shutdown hardware and release resources
1572  *
1573  * dev  pointer to network device structure
1574  *
1575  * returns 0 if success, otherwise error code
1576  */
1577 static int hdlcdev_close(struct net_device *dev)
1578 {
1579         struct slgt_info *info = dev_to_port(dev);
1580         unsigned long flags;
1581 
1582         DBGINFO(("%s hdlcdev_close\n", dev->name));
1583 
1584         netif_stop_queue(dev);
1585 
1586         /* shutdown adapter and release resources */
1587         shutdown(info);
1588 
1589         hdlc_close(dev);
1590 
1591         spin_lock_irqsave(&info->netlock, flags);
1592         info->netcount=0;
1593         spin_unlock_irqrestore(&info->netlock, flags);
1594 
1595         module_put(THIS_MODULE);
1596         return 0;
1597 }
1598 
1599 /**
1600  * called by network layer to process IOCTL call to network device
1601  *
1602  * dev  pointer to network device structure
1603  * ifr  pointer to network interface request structure
1604  * cmd  IOCTL command code
1605  *
1606  * returns 0 if success, otherwise error code
1607  */
1608 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1609 {
1610         const size_t size = sizeof(sync_serial_settings);
1611         sync_serial_settings new_line;
1612         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1613         struct slgt_info *info = dev_to_port(dev);
1614         unsigned int flags;
1615 
1616         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1617 
1618         /* return error if TTY interface open */
1619         if (info->port.count)
1620                 return -EBUSY;
1621 
1622         if (cmd != SIOCWANDEV)
1623                 return hdlc_ioctl(dev, ifr, cmd);
1624 
1625         memset(&new_line, 0, sizeof(new_line));
1626 
1627         switch(ifr->ifr_settings.type) {
1628         case IF_GET_IFACE: /* return current sync_serial_settings */
1629 
1630                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1631                 if (ifr->ifr_settings.size < size) {
1632                         ifr->ifr_settings.size = size; /* data size wanted */
1633                         return -ENOBUFS;
1634                 }
1635 
1636                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1637                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1638                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1639                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1640 
1641                 switch (flags){
1642                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1643                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1644                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1645                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1646                 default: new_line.clock_type = CLOCK_DEFAULT;
1647                 }
1648 
1649                 new_line.clock_rate = info->params.clock_speed;
1650                 new_line.loopback   = info->params.loopback ? 1:0;
1651 
1652                 if (copy_to_user(line, &new_line, size))
1653                         return -EFAULT;
1654                 return 0;
1655 
1656         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1657 
1658                 if(!capable(CAP_NET_ADMIN))
1659                         return -EPERM;
1660                 if (copy_from_user(&new_line, line, size))
1661                         return -EFAULT;
1662 
1663                 switch (new_line.clock_type)
1664                 {
1665                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1666                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1667                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1668                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1669                 case CLOCK_DEFAULT:  flags = info->params.flags &
1670                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1671                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1672                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1673                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1674                 default: return -EINVAL;
1675                 }
1676 
1677                 if (new_line.loopback != 0 && new_line.loopback != 1)
1678                         return -EINVAL;
1679 
1680                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1681                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1682                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1683                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1684                 info->params.flags |= flags;
1685 
1686                 info->params.loopback = new_line.loopback;
1687 
1688                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1689                         info->params.clock_speed = new_line.clock_rate;
1690                 else
1691                         info->params.clock_speed = 0;
1692 
1693                 /* if network interface up, reprogram hardware */
1694                 if (info->netcount)
1695                         program_hw(info);
1696                 return 0;
1697 
1698         default:
1699                 return hdlc_ioctl(dev, ifr, cmd);
1700         }
1701 }
1702 
1703 /**
1704  * called by network layer when transmit timeout is detected
1705  *
1706  * dev  pointer to network device structure
1707  */
1708 static void hdlcdev_tx_timeout(struct net_device *dev)
1709 {
1710         struct slgt_info *info = dev_to_port(dev);
1711         unsigned long flags;
1712 
1713         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1714 
1715         dev->stats.tx_errors++;
1716         dev->stats.tx_aborted_errors++;
1717 
1718         spin_lock_irqsave(&info->lock,flags);
1719         tx_stop(info);
1720         spin_unlock_irqrestore(&info->lock,flags);
1721 
1722         netif_wake_queue(dev);
1723 }
1724 
1725 /**
1726  * called by device driver when transmit completes
1727  * reenable network layer transmit if stopped
1728  *
1729  * info  pointer to device instance information
1730  */
1731 static void hdlcdev_tx_done(struct slgt_info *info)
1732 {
1733         if (netif_queue_stopped(info->netdev))
1734                 netif_wake_queue(info->netdev);
1735 }
1736 
1737 /**
1738  * called by device driver when frame received
1739  * pass frame to network layer
1740  *
1741  * info  pointer to device instance information
1742  * buf   pointer to buffer contianing frame data
1743  * size  count of data bytes in buf
1744  */
1745 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1746 {
1747         struct sk_buff *skb = dev_alloc_skb(size);
1748         struct net_device *dev = info->netdev;
1749 
1750         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1751 
1752         if (skb == NULL) {
1753                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1754                 dev->stats.rx_dropped++;
1755                 return;
1756         }
1757 
1758         memcpy(skb_put(skb, size), buf, size);
1759 
1760         skb->protocol = hdlc_type_trans(skb, dev);
1761 
1762         dev->stats.rx_packets++;
1763         dev->stats.rx_bytes += size;
1764 
1765         netif_rx(skb);
1766 }
1767 
1768 static const struct net_device_ops hdlcdev_ops = {
1769         .ndo_open       = hdlcdev_open,
1770         .ndo_stop       = hdlcdev_close,
1771         .ndo_change_mtu = hdlc_change_mtu,
1772         .ndo_start_xmit = hdlc_start_xmit,
1773         .ndo_do_ioctl   = hdlcdev_ioctl,
1774         .ndo_tx_timeout = hdlcdev_tx_timeout,
1775 };
1776 
1777 /**
1778  * called by device driver when adding device instance
1779  * do generic HDLC initialization
1780  *
1781  * info  pointer to device instance information
1782  *
1783  * returns 0 if success, otherwise error code
1784  */
1785 static int hdlcdev_init(struct slgt_info *info)
1786 {
1787         int rc;
1788         struct net_device *dev;
1789         hdlc_device *hdlc;
1790 
1791         /* allocate and initialize network and HDLC layer objects */
1792 
1793         dev = alloc_hdlcdev(info);
1794         if (!dev) {
1795                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1796                 return -ENOMEM;
1797         }
1798 
1799         /* for network layer reporting purposes only */
1800         dev->mem_start = info->phys_reg_addr;
1801         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1802         dev->irq       = info->irq_level;
1803 
1804         /* network layer callbacks and settings */
1805         dev->netdev_ops     = &hdlcdev_ops;
1806         dev->watchdog_timeo = 10 * HZ;
1807         dev->tx_queue_len   = 50;
1808 
1809         /* generic HDLC layer callbacks and settings */
1810         hdlc         = dev_to_hdlc(dev);
1811         hdlc->attach = hdlcdev_attach;
1812         hdlc->xmit   = hdlcdev_xmit;
1813 
1814         /* register objects with HDLC layer */
1815         rc = register_hdlc_device(dev);
1816         if (rc) {
1817                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1818                 free_netdev(dev);
1819                 return rc;
1820         }
1821 
1822         info->netdev = dev;
1823         return 0;
1824 }
1825 
1826 /**
1827  * called by device driver when removing device instance
1828  * do generic HDLC cleanup
1829  *
1830  * info  pointer to device instance information
1831  */
1832 static void hdlcdev_exit(struct slgt_info *info)
1833 {
1834         unregister_hdlc_device(info->netdev);
1835         free_netdev(info->netdev);
1836         info->netdev = NULL;
1837 }
1838 
1839 #endif /* ifdef CONFIG_HDLC */
1840 
1841 /*
1842  * get async data from rx DMA buffers
1843  */
1844 static void rx_async(struct slgt_info *info)
1845 {
1846         struct mgsl_icount *icount = &info->icount;
1847         unsigned int start, end;
1848         unsigned char *p;
1849         unsigned char status;
1850         struct slgt_desc *bufs = info->rbufs;
1851         int i, count;
1852         int chars = 0;
1853         int stat;
1854         unsigned char ch;
1855 
1856         start = end = info->rbuf_current;
1857 
1858         while(desc_complete(bufs[end])) {
1859                 count = desc_count(bufs[end]) - info->rbuf_index;
1860                 p     = bufs[end].buf + info->rbuf_index;
1861 
1862                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1863                 DBGDATA(info, p, count, "rx");
1864 
1865                 for(i=0 ; i < count; i+=2, p+=2) {
1866                         ch = *p;
1867                         icount->rx++;
1868 
1869                         stat = 0;
1870 
1871                         status = *(p + 1) & (BIT1 + BIT0);
1872                         if (status) {
1873                                 if (status & BIT1)
1874                                         icount->parity++;
1875                                 else if (status & BIT0)
1876                                         icount->frame++;
1877                                 /* discard char if tty control flags say so */
1878                                 if (status & info->ignore_status_mask)
1879                                         continue;
1880                                 if (status & BIT1)
1881                                         stat = TTY_PARITY;
1882                                 else if (status & BIT0)
1883                                         stat = TTY_FRAME;
1884                         }
1885                         tty_insert_flip_char(&info->port, ch, stat);
1886                         chars++;
1887                 }
1888 
1889                 if (i < count) {
1890                         /* receive buffer not completed */
1891                         info->rbuf_index += i;
1892                         mod_timer(&info->rx_timer, jiffies + 1);
1893                         break;
1894                 }
1895 
1896                 info->rbuf_index = 0;
1897                 free_rbufs(info, end, end);
1898 
1899                 if (++end == info->rbuf_count)
1900                         end = 0;
1901 
1902                 /* if entire list searched then no frame available */
1903                 if (end == start)
1904                         break;
1905         }
1906 
1907         if (chars)
1908                 tty_flip_buffer_push(&info->port);
1909 }
1910 
1911 /*
1912  * return next bottom half action to perform
1913  */
1914 static int bh_action(struct slgt_info *info)
1915 {
1916         unsigned long flags;
1917         int rc;
1918 
1919         spin_lock_irqsave(&info->lock,flags);
1920 
1921         if (info->pending_bh & BH_RECEIVE) {
1922                 info->pending_bh &= ~BH_RECEIVE;
1923                 rc = BH_RECEIVE;
1924         } else if (info->pending_bh & BH_TRANSMIT) {
1925                 info->pending_bh &= ~BH_TRANSMIT;
1926                 rc = BH_TRANSMIT;
1927         } else if (info->pending_bh & BH_STATUS) {
1928                 info->pending_bh &= ~BH_STATUS;
1929                 rc = BH_STATUS;
1930         } else {
1931                 /* Mark BH routine as complete */
1932                 info->bh_running = false;
1933                 info->bh_requested = false;
1934                 rc = 0;
1935         }
1936 
1937         spin_unlock_irqrestore(&info->lock,flags);
1938 
1939         return rc;
1940 }
1941 
1942 /*
1943  * perform bottom half processing
1944  */
1945 static void bh_handler(struct work_struct *work)
1946 {
1947         struct slgt_info *info = container_of(work, struct slgt_info, task);
1948         int action;
1949 
1950         info->bh_running = true;
1951 
1952         while((action = bh_action(info))) {
1953                 switch (action) {
1954                 case BH_RECEIVE:
1955                         DBGBH(("%s bh receive\n", info->device_name));
1956                         switch(info->params.mode) {
1957                         case MGSL_MODE_ASYNC:
1958                                 rx_async(info);
1959                                 break;
1960                         case MGSL_MODE_HDLC:
1961                                 while(rx_get_frame(info));
1962                                 break;
1963                         case MGSL_MODE_RAW:
1964                         case MGSL_MODE_MONOSYNC:
1965                         case MGSL_MODE_BISYNC:
1966                         case MGSL_MODE_XSYNC:
1967                                 while(rx_get_buf(info));
1968                                 break;
1969                         }
1970                         /* restart receiver if rx DMA buffers exhausted */
1971                         if (info->rx_restart)
1972                                 rx_start(info);
1973                         break;
1974                 case BH_TRANSMIT:
1975                         bh_transmit(info);
1976                         break;
1977                 case BH_STATUS:
1978                         DBGBH(("%s bh status\n", info->device_name));
1979                         info->ri_chkcount = 0;
1980                         info->dsr_chkcount = 0;
1981                         info->dcd_chkcount = 0;
1982                         info->cts_chkcount = 0;
1983                         break;
1984                 default:
1985                         DBGBH(("%s unknown action\n", info->device_name));
1986                         break;
1987                 }
1988         }
1989         DBGBH(("%s bh_handler exit\n", info->device_name));
1990 }
1991 
1992 static void bh_transmit(struct slgt_info *info)
1993 {
1994         struct tty_struct *tty = info->port.tty;
1995 
1996         DBGBH(("%s bh_transmit\n", info->device_name));
1997         if (tty)
1998                 tty_wakeup(tty);
1999 }
2000 
2001 static void dsr_change(struct slgt_info *info, unsigned short status)
2002 {
2003         if (status & BIT3) {
2004                 info->signals |= SerialSignal_DSR;
2005                 info->input_signal_events.dsr_up++;
2006         } else {
2007                 info->signals &= ~SerialSignal_DSR;
2008                 info->input_signal_events.dsr_down++;
2009         }
2010         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2011         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2012                 slgt_irq_off(info, IRQ_DSR);
2013                 return;
2014         }
2015         info->icount.dsr++;
2016         wake_up_interruptible(&info->status_event_wait_q);
2017         wake_up_interruptible(&info->event_wait_q);
2018         info->pending_bh |= BH_STATUS;
2019 }
2020 
2021 static void cts_change(struct slgt_info *info, unsigned short status)
2022 {
2023         if (status & BIT2) {
2024                 info->signals |= SerialSignal_CTS;
2025                 info->input_signal_events.cts_up++;
2026         } else {
2027                 info->signals &= ~SerialSignal_CTS;
2028                 info->input_signal_events.cts_down++;
2029         }
2030         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2031         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2032                 slgt_irq_off(info, IRQ_CTS);
2033                 return;
2034         }
2035         info->icount.cts++;
2036         wake_up_interruptible(&info->status_event_wait_q);
2037         wake_up_interruptible(&info->event_wait_q);
2038         info->pending_bh |= BH_STATUS;
2039 
2040         if (tty_port_cts_enabled(&info->port)) {
2041                 if (info->port.tty) {
2042                         if (info->port.tty->hw_stopped) {
2043                                 if (info->signals & SerialSignal_CTS) {
2044                                         info->port.tty->hw_stopped = 0;
2045                                         info->pending_bh |= BH_TRANSMIT;
2046                                         return;
2047                                 }
2048                         } else {
2049                                 if (!(info->signals & SerialSignal_CTS))
2050                                         info->port.tty->hw_stopped = 1;
2051                         }
2052                 }
2053         }
2054 }
2055 
2056 static void dcd_change(struct slgt_info *info, unsigned short status)
2057 {
2058         if (status & BIT1) {
2059                 info->signals |= SerialSignal_DCD;
2060                 info->input_signal_events.dcd_up++;
2061         } else {
2062                 info->signals &= ~SerialSignal_DCD;
2063                 info->input_signal_events.dcd_down++;
2064         }
2065         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2066         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2067                 slgt_irq_off(info, IRQ_DCD);
2068                 return;
2069         }
2070         info->icount.dcd++;
2071 #if SYNCLINK_GENERIC_HDLC
2072         if (info->netcount) {
2073                 if (info->signals & SerialSignal_DCD)
2074                         netif_carrier_on(info->netdev);
2075                 else
2076                         netif_carrier_off(info->netdev);
2077         }
2078 #endif
2079         wake_up_interruptible(&info->status_event_wait_q);
2080         wake_up_interruptible(&info->event_wait_q);
2081         info->pending_bh |= BH_STATUS;
2082 
2083         if (tty_port_check_carrier(&info->port)) {
2084                 if (info->signals & SerialSignal_DCD)
2085                         wake_up_interruptible(&info->port.open_wait);
2086                 else {
2087                         if (info->port.tty)
2088                                 tty_hangup(info->port.tty);
2089                 }
2090         }
2091 }
2092 
2093 static void ri_change(struct slgt_info *info, unsigned short status)
2094 {
2095         if (status & BIT0) {
2096                 info->signals |= SerialSignal_RI;
2097                 info->input_signal_events.ri_up++;
2098         } else {
2099                 info->signals &= ~SerialSignal_RI;
2100                 info->input_signal_events.ri_down++;
2101         }
2102         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2103         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2104                 slgt_irq_off(info, IRQ_RI);
2105                 return;
2106         }
2107         info->icount.rng++;
2108         wake_up_interruptible(&info->status_event_wait_q);
2109         wake_up_interruptible(&info->event_wait_q);
2110         info->pending_bh |= BH_STATUS;
2111 }
2112 
2113 static void isr_rxdata(struct slgt_info *info)
2114 {
2115         unsigned int count = info->rbuf_fill_count;
2116         unsigned int i = info->rbuf_fill_index;
2117         unsigned short reg;
2118 
2119         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2120                 reg = rd_reg16(info, RDR);
2121                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2122                 if (desc_complete(info->rbufs[i])) {
2123                         /* all buffers full */
2124                         rx_stop(info);
2125                         info->rx_restart = 1;
2126                         continue;
2127                 }
2128                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2129                 /* async mode saves status byte to buffer for each data byte */
2130                 if (info->params.mode == MGSL_MODE_ASYNC)
2131                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2132                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2133                         /* buffer full or end of frame */
2134                         set_desc_count(info->rbufs[i], count);
2135                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2136                         info->rbuf_fill_count = count = 0;
2137                         if (++i == info->rbuf_count)
2138                                 i = 0;
2139                         info->pending_bh |= BH_RECEIVE;
2140                 }
2141         }
2142 
2143         info->rbuf_fill_index = i;
2144         info->rbuf_fill_count = count;
2145 }
2146 
2147 static void isr_serial(struct slgt_info *info)
2148 {
2149         unsigned short status = rd_reg16(info, SSR);
2150 
2151         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2152 
2153         wr_reg16(info, SSR, status); /* clear pending */
2154 
2155         info->irq_occurred = true;
2156 
2157         if (info->params.mode == MGSL_MODE_ASYNC) {
2158                 if (status & IRQ_TXIDLE) {
2159                         if (info->tx_active)
2160                                 isr_txeom(info, status);
2161                 }
2162                 if (info->rx_pio && (status & IRQ_RXDATA))
2163                         isr_rxdata(info);
2164                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2165                         info->icount.brk++;
2166                         /* process break detection if tty control allows */
2167                         if (info->port.tty) {
2168                                 if (!(status & info->ignore_status_mask)) {
2169                                         if (info->read_status_mask & MASK_BREAK) {
2170                                                 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2171                                                 if (info->port.flags & ASYNC_SAK)
2172                                                         do_SAK(info->port.tty);
2173                                         }
2174                                 }
2175                         }
2176                 }
2177         } else {
2178                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2179                         isr_txeom(info, status);
2180                 if (info->rx_pio && (status & IRQ_RXDATA))
2181                         isr_rxdata(info);
2182                 if (status & IRQ_RXIDLE) {
2183                         if (status & RXIDLE)
2184                                 info->icount.rxidle++;
2185                         else
2186                                 info->icount.exithunt++;
2187                         wake_up_interruptible(&info->event_wait_q);
2188                 }
2189 
2190                 if (status & IRQ_RXOVER)
2191                         rx_start(info);
2192         }
2193 
2194         if (status & IRQ_DSR)
2195                 dsr_change(info, status);
2196         if (status & IRQ_CTS)
2197                 cts_change(info, status);
2198         if (status & IRQ_DCD)
2199                 dcd_change(info, status);
2200         if (status & IRQ_RI)
2201                 ri_change(info, status);
2202 }
2203 
2204 static void isr_rdma(struct slgt_info *info)
2205 {
2206         unsigned int status = rd_reg32(info, RDCSR);
2207 
2208         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2209 
2210         /* RDCSR (rx DMA control/status)
2211          *
2212          * 31..07  reserved
2213          * 06      save status byte to DMA buffer
2214          * 05      error
2215          * 04      eol (end of list)
2216          * 03      eob (end of buffer)
2217          * 02      IRQ enable
2218          * 01      reset
2219          * 00      enable
2220          */
2221         wr_reg32(info, RDCSR, status);  /* clear pending */
2222 
2223         if (status & (BIT5 + BIT4)) {
2224                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2225                 info->rx_restart = true;
2226         }
2227         info->pending_bh |= BH_RECEIVE;
2228 }
2229 
2230 static void isr_tdma(struct slgt_info *info)
2231 {
2232         unsigned int status = rd_reg32(info, TDCSR);
2233 
2234         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2235 
2236         /* TDCSR (tx DMA control/status)
2237          *
2238          * 31..06  reserved
2239          * 05      error
2240          * 04      eol (end of list)
2241          * 03      eob (end of buffer)
2242          * 02      IRQ enable
2243          * 01      reset
2244          * 00      enable
2245          */
2246         wr_reg32(info, TDCSR, status);  /* clear pending */
2247 
2248         if (status & (BIT5 + BIT4 + BIT3)) {
2249                 // another transmit buffer has completed
2250                 // run bottom half to get more send data from user
2251                 info->pending_bh |= BH_TRANSMIT;
2252         }
2253 }
2254 
2255 /*
2256  * return true if there are unsent tx DMA buffers, otherwise false
2257  *
2258  * if there are unsent buffers then info->tbuf_start
2259  * is set to index of first unsent buffer
2260  */
2261 static bool unsent_tbufs(struct slgt_info *info)
2262 {
2263         unsigned int i = info->tbuf_current;
2264         bool rc = false;
2265 
2266         /*
2267          * search backwards from last loaded buffer (precedes tbuf_current)
2268          * for first unsent buffer (desc_count > 0)
2269          */
2270 
2271         do {
2272                 if (i)
2273                         i--;
2274                 else
2275                         i = info->tbuf_count - 1;
2276                 if (!desc_count(info->tbufs[i]))
2277                         break;
2278                 info->tbuf_start = i;
2279                 rc = true;
2280         } while (i != info->tbuf_current);
2281 
2282         return rc;
2283 }
2284 
2285 static void isr_txeom(struct slgt_info *info, unsigned short status)
2286 {
2287         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2288 
2289         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2290         tdma_reset(info);
2291         if (status & IRQ_TXUNDER) {
2292                 unsigned short val = rd_reg16(info, TCR);
2293                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2294                 wr_reg16(info, TCR, val); /* clear reset bit */
2295         }
2296 
2297         if (info->tx_active) {
2298                 if (info->params.mode != MGSL_MODE_ASYNC) {
2299                         if (status & IRQ_TXUNDER)
2300                                 info->icount.txunder++;
2301                         else if (status & IRQ_TXIDLE)
2302                                 info->icount.txok++;
2303                 }
2304 
2305                 if (unsent_tbufs(info)) {
2306                         tx_start(info);
2307                         update_tx_timer(info);
2308                         return;
2309                 }
2310                 info->tx_active = false;
2311 
2312                 del_timer(&info->tx_timer);
2313 
2314                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2315                         info->signals &= ~SerialSignal_RTS;
2316                         info->drop_rts_on_tx_done = false;
2317                         set_signals(info);
2318                 }
2319 
2320 #if SYNCLINK_GENERIC_HDLC
2321                 if (info->netcount)
2322                         hdlcdev_tx_done(info);
2323                 else
2324 #endif
2325                 {
2326                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2327                                 tx_stop(info);
2328                                 return;
2329                         }
2330                         info->pending_bh |= BH_TRANSMIT;
2331                 }
2332         }
2333 }
2334 
2335 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2336 {
2337         struct cond_wait *w, *prev;
2338 
2339         /* wake processes waiting for specific transitions */
2340         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2341                 if (w->data & changed) {
2342                         w->data = state;
2343                         wake_up_interruptible(&w->q);
2344                         if (prev != NULL)
2345                                 prev->next = w->next;
2346                         else
2347                                 info->gpio_wait_q = w->next;
2348                 } else
2349                         prev = w;
2350         }
2351 }
2352 
2353 /* interrupt service routine
2354  *
2355  *      irq     interrupt number
2356  *      dev_id  device ID supplied during interrupt registration
2357  */
2358 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2359 {
2360         struct slgt_info *info = dev_id;
2361         unsigned int gsr;
2362         unsigned int i;
2363 
2364         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2365 
2366         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2367                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2368                 info->irq_occurred = true;
2369                 for(i=0; i < info->port_count ; i++) {
2370                         if (info->port_array[i] == NULL)
2371                                 continue;
2372                         spin_lock(&info->port_array[i]->lock);
2373                         if (gsr & (BIT8 << i))
2374                                 isr_serial(info->port_array[i]);
2375                         if (gsr & (BIT16 << (i*2)))
2376                                 isr_rdma(info->port_array[i]);
2377                         if (gsr & (BIT17 << (i*2)))
2378                                 isr_tdma(info->port_array[i]);
2379                         spin_unlock(&info->port_array[i]->lock);
2380                 }
2381         }
2382 
2383         if (info->gpio_present) {
2384                 unsigned int state;
2385                 unsigned int changed;
2386                 spin_lock(&info->lock);
2387                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2388                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2389                         /* read latched state of GPIO signals */
2390                         state = rd_reg32(info, IOVR);
2391                         /* clear pending GPIO interrupt bits */
2392                         wr_reg32(info, IOSR, changed);
2393                         for (i=0 ; i < info->port_count ; i++) {
2394                                 if (info->port_array[i] != NULL)
2395                                         isr_gpio(info->port_array[i], changed, state);
2396                         }
2397                 }
2398                 spin_unlock(&info->lock);
2399         }
2400 
2401         for(i=0; i < info->port_count ; i++) {
2402                 struct slgt_info *port = info->port_array[i];
2403                 if (port == NULL)
2404                         continue;
2405                 spin_lock(&port->lock);
2406                 if ((port->port.count || port->netcount) &&
2407                     port->pending_bh && !port->bh_running &&
2408                     !port->bh_requested) {
2409                         DBGISR(("%s bh queued\n", port->device_name));
2410                         schedule_work(&port->task);
2411                         port->bh_requested = true;
2412                 }
2413                 spin_unlock(&port->lock);
2414         }
2415 
2416         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2417         return IRQ_HANDLED;
2418 }
2419 
2420 static int startup(struct slgt_info *info)
2421 {
2422         DBGINFO(("%s startup\n", info->device_name));
2423 
2424         if (tty_port_initialized(&info->port))
2425                 return 0;
2426 
2427         if (!info->tx_buf) {
2428                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2429                 if (!info->tx_buf) {
2430                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2431                         return -ENOMEM;
2432                 }
2433         }
2434 
2435         info->pending_bh = 0;
2436 
2437         memset(&info->icount, 0, sizeof(info->icount));
2438 
2439         /* program hardware for current parameters */
2440         change_params(info);
2441 
2442         if (info->port.tty)
2443                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2444 
2445         tty_port_set_initialized(&info->port, 1);
2446 
2447         return 0;
2448 }
2449 
2450 /*
2451  *  called by close() and hangup() to shutdown hardware
2452  */
2453 static void shutdown(struct slgt_info *info)
2454 {
2455         unsigned long flags;
2456 
2457         if (!tty_port_initialized(&info->port))
2458                 return;
2459 
2460         DBGINFO(("%s shutdown\n", info->device_name));
2461 
2462         /* clear status wait queue because status changes */
2463         /* can't happen after shutting down the hardware */
2464         wake_up_interruptible(&info->status_event_wait_q);
2465         wake_up_interruptible(&info->event_wait_q);
2466 
2467         del_timer_sync(&info->tx_timer);
2468         del_timer_sync(&info->rx_timer);
2469 
2470         kfree(info->tx_buf);
2471         info->tx_buf = NULL;
2472 
2473         spin_lock_irqsave(&info->lock,flags);
2474 
2475         tx_stop(info);
2476         rx_stop(info);
2477 
2478         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2479 
2480         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2481                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2482                 set_signals(info);
2483         }
2484 
2485         flush_cond_wait(&info->gpio_wait_q);
2486 
2487         spin_unlock_irqrestore(&info->lock,flags);
2488 
2489         if (info->port.tty)
2490                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2491 
2492         tty_port_set_initialized(&info->port, 0);
2493 }
2494 
2495 static void program_hw(struct slgt_info *info)
2496 {
2497         unsigned long flags;
2498 
2499         spin_lock_irqsave(&info->lock,flags);
2500 
2501         rx_stop(info);
2502         tx_stop(info);
2503 
2504         if (info->params.mode != MGSL_MODE_ASYNC ||
2505             info->netcount)
2506                 sync_mode(info);
2507         else
2508                 async_mode(info);
2509 
2510         set_signals(info);
2511 
2512         info->dcd_chkcount = 0;
2513         info->cts_chkcount = 0;
2514         info->ri_chkcount = 0;
2515         info->dsr_chkcount = 0;
2516 
2517         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2518         get_signals(info);
2519 
2520         if (info->netcount ||
2521             (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2522                 rx_start(info);
2523 
2524         spin_unlock_irqrestore(&info->lock,flags);
2525 }
2526 
2527 /*
2528  * reconfigure adapter based on new parameters
2529  */
2530 static void change_params(struct slgt_info *info)
2531 {
2532         unsigned cflag;
2533         int bits_per_char;
2534 
2535         if (!info->port.tty)
2536                 return;
2537         DBGINFO(("%s change_params\n", info->device_name));
2538 
2539         cflag = info->port.tty->termios.c_cflag;
2540 
2541         /* if B0 rate (hangup) specified then negate RTS and DTR */
2542         /* otherwise assert RTS and DTR */
2543         if (cflag & CBAUD)
2544                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2545         else
2546                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2547 
2548         /* byte size and parity */
2549 
2550         switch (cflag & CSIZE) {
2551         case CS5: info->params.data_bits = 5; break;
2552         case CS6: info->params.data_bits = 6; break;
2553         case CS7: info->params.data_bits = 7; break;
2554         case CS8: info->params.data_bits = 8; break;
2555         default:  info->params.data_bits = 7; break;
2556         }
2557 
2558         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2559 
2560         if (cflag & PARENB)
2561                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2562         else
2563                 info->params.parity = ASYNC_PARITY_NONE;
2564 
2565         /* calculate number of jiffies to transmit a full
2566          * FIFO (32 bytes) at specified data rate
2567          */
2568         bits_per_char = info->params.data_bits +
2569                         info->params.stop_bits + 1;
2570 
2571         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2572 
2573         if (info->params.data_rate) {
2574                 info->timeout = (32*HZ*bits_per_char) /
2575                                 info->params.data_rate;
2576         }
2577         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2578 
2579         tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2580         tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2581 
2582         /* process tty input control flags */
2583 
2584         info->read_status_mask = IRQ_RXOVER;
2585         if (I_INPCK(info->port.tty))
2586                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2587         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2588                 info->read_status_mask |= MASK_BREAK;
2589         if (I_IGNPAR(info->port.tty))
2590                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2591         if (I_IGNBRK(info->port.tty)) {
2592                 info->ignore_status_mask |= MASK_BREAK;
2593                 /* If ignoring parity and break indicators, ignore
2594                  * overruns too.  (For real raw support).
2595                  */
2596                 if (I_IGNPAR(info->port.tty))
2597                         info->ignore_status_mask |= MASK_OVERRUN;
2598         }
2599 
2600         program_hw(info);
2601 }
2602 
2603 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2604 {
2605         DBGINFO(("%s get_stats\n",  info->device_name));
2606         if (!user_icount) {
2607                 memset(&info->icount, 0, sizeof(info->icount));
2608         } else {
2609                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2610                         return -EFAULT;
2611         }
2612         return 0;
2613 }
2614 
2615 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2616 {
2617         DBGINFO(("%s get_params\n", info->device_name));
2618         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2619                 return -EFAULT;
2620         return 0;
2621 }
2622 
2623 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2624 {
2625         unsigned long flags;
2626         MGSL_PARAMS tmp_params;
2627 
2628         DBGINFO(("%s set_params\n", info->device_name));
2629         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2630                 return -EFAULT;
2631 
2632         spin_lock_irqsave(&info->lock, flags);
2633         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2634                 info->base_clock = tmp_params.clock_speed;
2635         else
2636                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2637         spin_unlock_irqrestore(&info->lock, flags);
2638 
2639         program_hw(info);
2640 
2641         return 0;
2642 }
2643 
2644 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2645 {
2646         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2647         if (put_user(info->idle_mode, idle_mode))
2648                 return -EFAULT;
2649         return 0;
2650 }
2651 
2652 static int set_txidle(struct slgt_info *info, int idle_mode)
2653 {
2654         unsigned long flags;
2655         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2656         spin_lock_irqsave(&info->lock,flags);
2657         info->idle_mode = idle_mode;
2658         if (info->params.mode != MGSL_MODE_ASYNC)
2659                 tx_set_idle(info);
2660         spin_unlock_irqrestore(&info->lock,flags);
2661         return 0;
2662 }
2663 
2664 static int tx_enable(struct slgt_info *info, int enable)
2665 {
2666         unsigned long flags;
2667         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2668         spin_lock_irqsave(&info->lock,flags);
2669         if (enable) {
2670                 if (!info->tx_enabled)
2671                         tx_start(info);
2672         } else {
2673                 if (info->tx_enabled)
2674                         tx_stop(info);
2675         }
2676         spin_unlock_irqrestore(&info->lock,flags);
2677         return 0;
2678 }
2679 
2680 /*
2681  * abort transmit HDLC frame
2682  */
2683 static int tx_abort(struct slgt_info *info)
2684 {
2685         unsigned long flags;
2686         DBGINFO(("%s tx_abort\n", info->device_name));
2687         spin_lock_irqsave(&info->lock,flags);
2688         tdma_reset(info);
2689         spin_unlock_irqrestore(&info->lock,flags);
2690         return 0;
2691 }
2692 
2693 static int rx_enable(struct slgt_info *info, int enable)
2694 {
2695         unsigned long flags;
2696         unsigned int rbuf_fill_level;
2697         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2698         spin_lock_irqsave(&info->lock,flags);
2699         /*
2700          * enable[31..16] = receive DMA buffer fill level
2701          * 0 = noop (leave fill level unchanged)
2702          * fill level must be multiple of 4 and <= buffer size
2703          */
2704         rbuf_fill_level = ((unsigned int)enable) >> 16;
2705         if (rbuf_fill_level) {
2706                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2707                         spin_unlock_irqrestore(&info->lock, flags);
2708                         return -EINVAL;
2709                 }
2710                 info->rbuf_fill_level = rbuf_fill_level;
2711                 if (rbuf_fill_level < 128)
2712                         info->rx_pio = 1; /* PIO mode */
2713                 else
2714                         info->rx_pio = 0; /* DMA mode */
2715                 rx_stop(info); /* restart receiver to use new fill level */
2716         }
2717 
2718         /*
2719          * enable[1..0] = receiver enable command
2720          * 0 = disable
2721          * 1 = enable
2722          * 2 = enable or force hunt mode if already enabled
2723          */
2724         enable &= 3;
2725         if (enable) {
2726                 if (!info->rx_enabled)
2727                         rx_start(info);
2728                 else if (enable == 2) {
2729                         /* force hunt mode (write 1 to RCR[3]) */
2730                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2731                 }
2732         } else {
2733                 if (info->rx_enabled)
2734                         rx_stop(info);
2735         }
2736         spin_unlock_irqrestore(&info->lock,flags);
2737         return 0;
2738 }
2739 
2740 /*
2741  *  wait for specified event to occur
2742  */
2743 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2744 {
2745         unsigned long flags;
2746         int s;
2747         int rc=0;
2748         struct mgsl_icount cprev, cnow;
2749         int events;
2750         int mask;
2751         struct  _input_signal_events oldsigs, newsigs;
2752         DECLARE_WAITQUEUE(wait, current);
2753 
2754         if (get_user(mask, mask_ptr))
2755                 return -EFAULT;
2756 
2757         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2758 
2759         spin_lock_irqsave(&info->lock,flags);
2760 
2761         /* return immediately if state matches requested events */
2762         get_signals(info);
2763         s = info->signals;
2764 
2765         events = mask &
2766                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2767                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2768                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2769                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2770         if (events) {
2771                 spin_unlock_irqrestore(&info->lock,flags);
2772                 goto exit;
2773         }
2774 
2775         /* save current irq counts */
2776         cprev = info->icount;
2777         oldsigs = info->input_signal_events;
2778 
2779         /* enable hunt and idle irqs if needed */
2780         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2781                 unsigned short val = rd_reg16(info, SCR);
2782                 if (!(val & IRQ_RXIDLE))
2783                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2784         }
2785 
2786         set_current_state(TASK_INTERRUPTIBLE);
2787         add_wait_queue(&info->event_wait_q, &wait);
2788 
2789         spin_unlock_irqrestore(&info->lock,flags);
2790 
2791         for(;;) {
2792                 schedule();
2793                 if (signal_pending(current)) {
2794                         rc = -ERESTARTSYS;
2795                         break;
2796                 }
2797 
2798                 /* get current irq counts */
2799                 spin_lock_irqsave(&info->lock,flags);
2800                 cnow = info->icount;
2801                 newsigs = info->input_signal_events;
2802                 set_current_state(TASK_INTERRUPTIBLE);
2803                 spin_unlock_irqrestore(&info->lock,flags);
2804 
2805                 /* if no change, wait aborted for some reason */
2806                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2807                     newsigs.dsr_down == oldsigs.dsr_down &&
2808                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2809                     newsigs.dcd_down == oldsigs.dcd_down &&
2810                     newsigs.cts_up   == oldsigs.cts_up   &&
2811                     newsigs.cts_down == oldsigs.cts_down &&
2812                     newsigs.ri_up    == oldsigs.ri_up    &&
2813                     newsigs.ri_down  == oldsigs.ri_down  &&
2814                     cnow.exithunt    == cprev.exithunt   &&
2815                     cnow.rxidle      == cprev.rxidle) {
2816                         rc = -EIO;
2817                         break;
2818                 }
2819 
2820                 events = mask &
2821                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2822                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2823                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2824                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2825                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2826                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2827                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2828                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2829                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2830                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2831                 if (events)
2832                         break;
2833 
2834                 cprev = cnow;
2835                 oldsigs = newsigs;
2836         }
2837 
2838         remove_wait_queue(&info->event_wait_q, &wait);
2839         set_current_state(TASK_RUNNING);
2840 
2841 
2842         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2843                 spin_lock_irqsave(&info->lock,flags);
2844                 if (!waitqueue_active(&info->event_wait_q)) {
2845                         /* disable enable exit hunt mode/idle rcvd IRQs */
2846                         wr_reg16(info, SCR,
2847                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2848                 }
2849                 spin_unlock_irqrestore(&info->lock,flags);
2850         }
2851 exit:
2852         if (rc == 0)
2853                 rc = put_user(events, mask_ptr);
2854         return rc;
2855 }
2856 
2857 static int get_interface(struct slgt_info *info, int __user *if_mode)
2858 {
2859         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2860         if (put_user(info->if_mode, if_mode))
2861                 return -EFAULT;
2862         return 0;
2863 }
2864 
2865 static int set_interface(struct slgt_info *info, int if_mode)
2866 {
2867         unsigned long flags;
2868         unsigned short val;
2869 
2870         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2871         spin_lock_irqsave(&info->lock,flags);
2872         info->if_mode = if_mode;
2873 
2874         msc_set_vcr(info);
2875 
2876         /* TCR (tx control) 07  1=RTS driver control */
2877         val = rd_reg16(info, TCR);
2878         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2879                 val |= BIT7;
2880         else
2881                 val &= ~BIT7;
2882         wr_reg16(info, TCR, val);
2883 
2884         spin_unlock_irqrestore(&info->lock,flags);
2885         return 0;
2886 }
2887 
2888 static int get_xsync(struct slgt_info *info, int __user *xsync)
2889 {
2890         DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2891         if (put_user(info->xsync, xsync))
2892                 return -EFAULT;
2893         return 0;
2894 }
2895 
2896 /*
2897  * set extended sync pattern (1 to 4 bytes) for extended sync mode
2898  *
2899  * sync pattern is contained in least significant bytes of value
2900  * most significant byte of sync pattern is oldest (1st sent/detected)
2901  */
2902 static int set_xsync(struct slgt_info *info, int xsync)
2903 {
2904         unsigned long flags;
2905 
2906         DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2907         spin_lock_irqsave(&info->lock, flags);
2908         info->xsync = xsync;
2909         wr_reg32(info, XSR, xsync);
2910         spin_unlock_irqrestore(&info->lock, flags);
2911         return 0;
2912 }
2913 
2914 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2915 {
2916         DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2917         if (put_user(info->xctrl, xctrl))
2918                 return -EFAULT;
2919         return 0;
2920 }
2921 
2922 /*
2923  * set extended control options
2924  *
2925  * xctrl[31:19] reserved, must be zero
2926  * xctrl[18:17] extended sync pattern length in bytes
2927  *              00 = 1 byte  in xsr[7:0]
2928  *              01 = 2 bytes in xsr[15:0]
2929  *              10 = 3 bytes in xsr[23:0]
2930  *              11 = 4 bytes in xsr[31:0]
2931  * xctrl[16]    1 = enable terminal count, 0=disabled
2932  * xctrl[15:0]  receive terminal count for fixed length packets
2933  *              value is count minus one (0 = 1 byte packet)
2934  *              when terminal count is reached, receiver
2935  *              automatically returns to hunt mode and receive
2936  *              FIFO contents are flushed to DMA buffers with
2937  *              end of frame (EOF) status
2938  */
2939 static int set_xctrl(struct slgt_info *info, int xctrl)
2940 {
2941         unsigned long flags;
2942 
2943         DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2944         spin_lock_irqsave(&info->lock, flags);
2945         info->xctrl = xctrl;
2946         wr_reg32(info, XCR, xctrl);
2947         spin_unlock_irqrestore(&info->lock, flags);
2948         return 0;
2949 }
2950 
2951 /*
2952  * set general purpose IO pin state and direction
2953  *
2954  * user_gpio fields:
2955  * state   each bit indicates a pin state
2956  * smask   set bit indicates pin state to set
2957  * dir     each bit indicates a pin direction (0=input, 1=output)
2958  * dmask   set bit indicates pin direction to set
2959  */
2960 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2961 {
2962         unsigned long flags;
2963         struct gpio_desc gpio;
2964         __u32 data;
2965 
2966         if (!info->gpio_present)
2967                 return -EINVAL;
2968         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2969                 return -EFAULT;
2970         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2971                  info->device_name, gpio.state, gpio.smask,
2972                  gpio.dir, gpio.dmask));
2973 
2974         spin_lock_irqsave(&info->port_array[0]->lock, flags);
2975         if (gpio.dmask) {
2976                 data = rd_reg32(info, IODR);
2977                 data |= gpio.dmask & gpio.dir;
2978                 data &= ~(gpio.dmask & ~gpio.dir);
2979                 wr_reg32(info, IODR, data);
2980         }
2981         if (gpio.smask) {
2982                 data = rd_reg32(info, IOVR);
2983                 data |= gpio.smask & gpio.state;
2984                 data &= ~(gpio.smask & ~gpio.state);
2985                 wr_reg32(info, IOVR, data);
2986         }
2987         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2988 
2989         return 0;
2990 }
2991 
2992 /*
2993  * get general purpose IO pin state and direction
2994  */
2995 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2996 {
2997         struct gpio_desc gpio;
2998         if (!info->gpio_present)
2999                 return -EINVAL;
3000         gpio.state = rd_reg32(info, IOVR);
3001         gpio.smask = 0xffffffff;
3002         gpio.dir   = rd_reg32(info, IODR);
3003         gpio.dmask = 0xffffffff;
3004         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3005                 return -EFAULT;
3006         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3007                  info->device_name, gpio.state, gpio.dir));
3008         return 0;
3009 }
3010 
3011 /*
3012  * conditional wait facility
3013  */
3014 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3015 {
3016         init_waitqueue_head(&w->q);
3017         init_waitqueue_entry(&w->wait, current);
3018         w->data = data;
3019 }
3020 
3021 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3022 {
3023         set_current_state(TASK_INTERRUPTIBLE);
3024         add_wait_queue(&w->q, &w->wait);
3025         w->next = *head;
3026         *head = w;
3027 }
3028 
3029 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3030 {
3031         struct cond_wait *w, *prev;
3032         remove_wait_queue(&cw->q, &cw->wait);
3033         set_current_state(TASK_RUNNING);
3034         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3035                 if (w == cw) {
3036                         if (prev != NULL)
3037                                 prev->next = w->next;
3038                         else
3039                                 *head = w->next;
3040                         break;
3041                 }
3042         }
3043 }
3044 
3045 static void flush_cond_wait(struct cond_wait **head)
3046 {
3047         while (*head != NULL) {
3048                 wake_up_interruptible(&(*head)->q);
3049                 *head = (*head)->next;
3050         }
3051 }
3052 
3053 /*
3054  * wait for general purpose I/O pin(s) to enter specified state
3055  *
3056  * user_gpio fields:
3057  * state - bit indicates target pin state
3058  * smask - set bit indicates watched pin
3059  *
3060  * The wait ends when at least one watched pin enters the specified
3061  * state. When 0 (no error) is returned, user_gpio->state is set to the
3062  * state of all GPIO pins when the wait ends.
3063  *
3064  * Note: Each pin may be a dedicated input, dedicated output, or
3065  * configurable input/output. The number and configuration of pins
3066  * varies with the specific adapter model. Only input pins (dedicated
3067  * or configured) can be monitored with this function.
3068  */
3069 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3070 {
3071         unsigned long flags;
3072         int rc = 0;
3073         struct gpio_desc gpio;
3074         struct cond_wait wait;
3075         u32 state;
3076 
3077         if (!info->gpio_present)
3078                 return -EINVAL;
3079         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3080                 return -EFAULT;
3081         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3082                  info->device_name, gpio.state, gpio.smask));
3083         /* ignore output pins identified by set IODR bit */
3084         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3085                 return -EINVAL;
3086         init_cond_wait(&wait, gpio.smask);
3087 
3088         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3089         /* enable interrupts for watched pins */
3090         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3091         /* get current pin states */
3092         state = rd_reg32(info, IOVR);
3093 
3094         if (gpio.smask & ~(state ^ gpio.state)) {
3095                 /* already in target state */
3096                 gpio.state = state;
3097         } else {
3098                 /* wait for target state */
3099                 add_cond_wait(&info->gpio_wait_q, &wait);
3100                 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3101                 schedule();
3102                 if (signal_pending(current))
3103                         rc = -ERESTARTSYS;
3104                 else
3105                         gpio.state = wait.data;
3106                 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3107                 remove_cond_wait(&info->gpio_wait_q, &wait);
3108         }
3109 
3110         /* disable all GPIO interrupts if no waiting processes */
3111         if (info->gpio_wait_q == NULL)
3112                 wr_reg32(info, IOER, 0);
3113         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3114 
3115         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3116                 rc = -EFAULT;
3117         return rc;
3118 }
3119 
3120 static int modem_input_wait(struct slgt_info *info,int arg)
3121 {
3122         unsigned long flags;
3123         int rc;
3124         struct mgsl_icount cprev, cnow;
3125         DECLARE_WAITQUEUE(wait, current);
3126 
3127         /* save current irq counts */
3128         spin_lock_irqsave(&info->lock,flags);
3129         cprev = info->icount;
3130         add_wait_queue(&info->status_event_wait_q, &wait);
3131         set_current_state(TASK_INTERRUPTIBLE);
3132         spin_unlock_irqrestore(&info->lock,flags);
3133 
3134         for(;;) {
3135                 schedule();
3136                 if (signal_pending(current)) {
3137                         rc = -ERESTARTSYS;
3138                         break;
3139                 }
3140 
3141                 /* get new irq counts */
3142                 spin_lock_irqsave(&info->lock,flags);
3143                 cnow = info->icount;
3144                 set_current_state(TASK_INTERRUPTIBLE);
3145                 spin_unlock_irqrestore(&info->lock,flags);
3146 
3147                 /* if no change, wait aborted for some reason */
3148                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3149                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3150                         rc = -EIO;
3151                         break;
3152                 }
3153 
3154                 /* check for change in caller specified modem input */
3155                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3156                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3157                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3158                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3159                         rc = 0;
3160                         break;
3161                 }
3162 
3163                 cprev = cnow;
3164         }
3165         remove_wait_queue(&info->status_event_wait_q, &wait);
3166         set_current_state(TASK_RUNNING);
3167         return rc;
3168 }
3169 
3170 /*
3171  *  return state of serial control and status signals
3172  */
3173 static int tiocmget(struct tty_struct *tty)
3174 {
3175         struct slgt_info *info = tty->driver_data;
3176         unsigned int result;
3177         unsigned long flags;
3178 
3179         spin_lock_irqsave(&info->lock,flags);
3180         get_signals(info);
3181         spin_unlock_irqrestore(&info->lock,flags);
3182 
3183         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3184                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3185                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3186                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3187                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3188                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3189 
3190         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3191         return result;
3192 }
3193 
3194 /*
3195  * set modem control signals (DTR/RTS)
3196  *
3197  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3198  *              TIOCMSET = set/clear signal values
3199  *      value   bit mask for command
3200  */
3201 static int tiocmset(struct tty_struct *tty,
3202                     unsigned int set, unsigned int clear)
3203 {
3204         struct slgt_info *info = tty->driver_data;
3205         unsigned long flags;
3206 
3207         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3208 
3209         if (set & TIOCM_RTS)
3210                 info->signals |= SerialSignal_RTS;
3211         if (set & TIOCM_DTR)
3212                 info->signals |= SerialSignal_DTR;
3213         if (clear & TIOCM_RTS)
3214                 info->signals &= ~SerialSignal_RTS;
3215         if (clear & TIOCM_DTR)
3216                 info->signals &= ~SerialSignal_DTR;
3217 
3218         spin_lock_irqsave(&info->lock,flags);
3219         set_signals(info);
3220         spin_unlock_irqrestore(&info->lock,flags);
3221         return 0;
3222 }
3223 
3224 static int carrier_raised(struct tty_port *port)
3225 {
3226         unsigned long flags;
3227         struct slgt_info *info = container_of(port, struct slgt_info, port);
3228 
3229         spin_lock_irqsave(&info->lock,flags);
3230         get_signals(info);
3231         spin_unlock_irqrestore(&info->lock,flags);
3232         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3233 }
3234 
3235 static void dtr_rts(struct tty_port *port, int on)
3236 {
3237         unsigned long flags;
3238         struct slgt_info *info = container_of(port, struct slgt_info, port);
3239 
3240         spin_lock_irqsave(&info->lock,flags);
3241         if (on)
3242                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3243         else
3244                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3245         set_signals(info);
3246         spin_unlock_irqrestore(&info->lock,flags);
3247 }
3248 
3249 
3250 /*
3251  *  block current process until the device is ready to open
3252  */
3253 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3254                            struct slgt_info *info)
3255 {
3256         DECLARE_WAITQUEUE(wait, current);
3257         int             retval;
3258         bool            do_clocal = false;
3259         unsigned long   flags;
3260         int             cd;
3261         struct tty_port *port = &info->port;
3262 
3263         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3264 
3265         if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3266                 /* nonblock mode is set or port is not enabled */
3267                 tty_port_set_active(port, 1);
3268                 return 0;
3269         }
3270 
3271         if (C_CLOCAL(tty))
3272                 do_clocal = true;
3273 
3274         /* Wait for carrier detect and the line to become
3275          * free (i.e., not in use by the callout).  While we are in
3276          * this loop, port->count is dropped by one, so that
3277          * close() knows when to free things.  We restore it upon
3278          * exit, either normal or abnormal.
3279          */
3280 
3281         retval = 0;
3282         add_wait_queue(&port->open_wait, &wait);
3283 
3284         spin_lock_irqsave(&info->lock, flags);
3285         port->count--;
3286         spin_unlock_irqrestore(&info->lock, flags);
3287         port->blocked_open++;
3288 
3289         while (1) {
3290                 if (C_BAUD(tty) && tty_port_initialized(port))
3291                         tty_port_raise_dtr_rts(port);
3292 
3293                 set_current_state(TASK_INTERRUPTIBLE);
3294 
3295                 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3296                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3297                                         -EAGAIN : -ERESTARTSYS;
3298                         break;
3299                 }
3300 
3301                 cd = tty_port_carrier_raised(port);
3302                 if (do_clocal || cd)
3303                         break;
3304 
3305                 if (signal_pending(current)) {
3306                         retval = -ERESTARTSYS;
3307                         break;
3308                 }
3309 
3310                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3311                 tty_unlock(tty);
3312                 schedule();
3313                 tty_lock(tty);
3314         }
3315 
3316         set_current_state(TASK_RUNNING);
3317         remove_wait_queue(&port->open_wait, &wait);
3318 
3319         if (!tty_hung_up_p(filp))
3320                 port->count++;
3321         port->blocked_open--;
3322 
3323         if (!retval)
3324                 tty_port_set_active(port, 1);
3325 
3326         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3327         return retval;
3328 }
3329 
3330 /*
3331  * allocate buffers used for calling line discipline receive_buf
3332  * directly in synchronous mode
3333  * note: add 5 bytes to max frame size to allow appending
3334  * 32-bit CRC and status byte when configured to do so
3335  */
3336 static int alloc_tmp_rbuf(struct slgt_info *info)
3337 {
3338         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3339         if (info->tmp_rbuf == NULL)
3340                 return -ENOMEM;
3341         /* unused flag buffer to satisfy receive_buf calling interface */
3342         info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3343         if (!info->flag_buf) {
3344                 kfree(info->tmp_rbuf);
3345                 info->tmp_rbuf = NULL;
3346                 return -ENOMEM;
3347         }
3348         return 0;
3349 }
3350 
3351 static void free_tmp_rbuf(struct slgt_info *info)
3352 {
3353         kfree(info->tmp_rbuf);
3354         info->tmp_rbuf = NULL;
3355         kfree(info->flag_buf);
3356         info->flag_buf = NULL;
3357 }
3358 
3359 /*
3360  * allocate DMA descriptor lists.
3361  */
3362 static int alloc_desc(struct slgt_info *info)
3363 {
3364         unsigned int i;
3365         unsigned int pbufs;
3366 
3367         /* allocate memory to hold descriptor lists */
3368         info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3369                                            &info->bufs_dma_addr);
3370         if (info->bufs == NULL)
3371                 return -ENOMEM;
3372 
3373         info->rbufs = (struct slgt_desc*)info->bufs;
3374         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3375 
3376         pbufs = (unsigned int)info->bufs_dma_addr;
3377 
3378         /*
3379          * Build circular lists of descriptors
3380          */
3381 
3382         for (i=0; i < info->rbuf_count; i++) {
3383                 /* physical address of this descriptor */
3384                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3385 
3386                 /* physical address of next descriptor */
3387                 if (i == info->rbuf_count - 1)
3388                         info->rbufs[i].next = cpu_to_le32(pbufs);
3389                 else
3390                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3391                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3392         }
3393 
3394         for (i=0; i < info->tbuf_count; i++) {
3395                 /* physical address of this descriptor */
3396                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3397 
3398                 /* physical address of next descriptor */
3399                 if (i == info->tbuf_count - 1)
3400                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3401                 else
3402                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3403         }
3404 
3405         return 0;
3406 }
3407 
3408 static void free_desc(struct slgt_info *info)
3409 {
3410         if (info->bufs != NULL) {
3411                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3412                 info->bufs  = NULL;
3413                 info->rbufs = NULL;
3414                 info->tbufs = NULL;
3415         }
3416 }
3417 
3418 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3419 {
3420         int i;
3421         for (i=0; i < count; i++) {
3422                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3423                         return -ENOMEM;
3424                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3425         }
3426         return 0;
3427 }
3428 
3429 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3430 {
3431         int i;
3432         for (i=0; i < count; i++) {
3433                 if (bufs[i].buf == NULL)
3434                         continue;
3435                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3436                 bufs[i].buf = NULL;
3437         }
3438 }
3439 
3440 static int alloc_dma_bufs(struct slgt_info *info)
3441 {
3442         info->rbuf_count = 32;
3443         info->tbuf_count = 32;
3444 
3445         if (alloc_desc(info) < 0 ||
3446             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3447             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3448             alloc_tmp_rbuf(info) < 0) {
3449                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3450                 return -ENOMEM;
3451         }
3452         reset_rbufs(info);
3453         return 0;
3454 }
3455 
3456 static void free_dma_bufs(struct slgt_info *info)
3457 {
3458         if (info->bufs) {
3459                 free_bufs(info, info->rbufs, info->rbuf_count);
3460                 free_bufs(info, info->tbufs, info->tbuf_count);
3461                 free_desc(info);
3462         }
3463         free_tmp_rbuf(info);
3464 }
3465 
3466 static int claim_resources(struct slgt_info *info)
3467 {
3468         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3469                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3470                         info->device_name, info->phys_reg_addr));
3471                 info->init_error = DiagStatus_AddressConflict;
3472                 goto errout;
3473         }
3474         else
3475                 info->reg_addr_requested = true;
3476 
3477         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3478         if (!info->reg_addr) {
3479                 DBGERR(("%s can't map device registers, addr=%08X\n",
3480                         info->device_name, info->phys_reg_addr));
3481                 info->init_error = DiagStatus_CantAssignPciResources;
3482                 goto errout;
3483         }
3484         return 0;
3485 
3486 errout:
3487         release_resources(info);
3488         return -ENODEV;
3489 }
3490 
3491 static void release_resources(struct slgt_info *info)
3492 {
3493         if (info->irq_requested) {
3494                 free_irq(info->irq_level, info);
3495                 info->irq_requested = false;
3496         }
3497 
3498         if (info->reg_addr_requested) {
3499                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3500                 info->reg_addr_requested = false;
3501         }
3502 
3503         if (info->reg_addr) {
3504                 iounmap(info->reg_addr);
3505                 info->reg_addr = NULL;
3506         }
3507 }
3508 
3509 /* Add the specified device instance data structure to the
3510  * global linked list of devices and increment the device count.
3511  */
3512 static void add_device(struct slgt_info *info)
3513 {
3514         char *devstr;
3515 
3516         info->next_device = NULL;
3517         info->line = slgt_device_count;
3518         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3519 
3520         if (info->line < MAX_DEVICES) {
3521                 if (maxframe[info->line])
3522                         info->max_frame_size = maxframe[info->line];
3523         }
3524 
3525         slgt_device_count++;
3526 
3527         if (!slgt_device_list)
3528                 slgt_device_list = info;
3529         else {
3530                 struct slgt_info *current_dev = slgt_device_list;
3531                 while(current_dev->next_device)
3532                         current_dev = current_dev->next_device;
3533                 current_dev->next_device = info;
3534         }
3535 
3536         if (info->max_frame_size < 4096)
3537                 info->max_frame_size = 4096;
3538         else if (info->max_frame_size > 65535)
3539                 info->max_frame_size = 65535;
3540 
3541         switch(info->pdev->device) {
3542         case SYNCLINK_GT_DEVICE_ID:
3543                 devstr = "GT";
3544                 break;
3545         case SYNCLINK_GT2_DEVICE_ID:
3546                 devstr = "GT2";
3547                 break;
3548         case SYNCLINK_GT4_DEVICE_ID:
3549                 devstr = "GT4";
3550                 break;
3551         case SYNCLINK_AC_DEVICE_ID:
3552                 devstr = "AC";
3553                 info->params.mode = MGSL_MODE_ASYNC;
3554                 break;
3555         default:
3556                 devstr = "(unknown model)";
3557         }
3558         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3559                 devstr, info->device_name, info->phys_reg_addr,
3560                 info->irq_level, info->max_frame_size);
3561 
3562 #if SYNCLINK_GENERIC_HDLC
3563         hdlcdev_init(info);
3564 #endif
3565 }
3566 
3567 static const struct tty_port_operations slgt_port_ops = {
3568         .carrier_raised = carrier_raised,
3569         .dtr_rts = dtr_rts,
3570 };
3571 
3572 /*
3573  *  allocate device instance structure, return NULL on failure
3574  */
3575 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3576 {
3577         struct slgt_info *info;
3578 
3579         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3580 
3581         if (!info) {
3582                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3583                         driver_name, adapter_num, port_num));
3584         } else {
3585                 tty_port_init(&info->port);
3586                 info->port.ops = &slgt_port_ops;
3587                 info->magic = MGSL_MAGIC;
3588                 INIT_WORK(&info->task, bh_handler);
3589                 info->max_frame_size = 4096;
3590                 info->base_clock = 14745600;
3591                 info->rbuf_fill_level = DMABUFSIZE;
3592                 info->port.close_delay = 5*HZ/10;
3593                 info->port.closing_wait = 30*HZ;
3594                 init_waitqueue_head(&info->status_event_wait_q);
3595                 init_waitqueue_head(&info->event_wait_q);
3596                 spin_lock_init(&info->netlock);
3597                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3598                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3599                 info->adapter_num = adapter_num;
3600                 info->port_num = port_num;
3601 
3602                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3603                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3604 
3605                 /* Copy configuration info to device instance data */
3606                 info->pdev = pdev;
3607                 info->irq_level = pdev->irq;
3608                 info->phys_reg_addr = pci_resource_start(pdev,0);
3609 
3610                 info->bus_type = MGSL_BUS_TYPE_PCI;
3611                 info->irq_flags = IRQF_SHARED;
3612 
3613                 info->init_error = -1; /* assume error, set to 0 on successful init */
3614         }
3615 
3616         return info;
3617 }
3618 
3619 static void device_init(int adapter_num, struct pci_dev *pdev)
3620 {
3621         struct slgt_info *port_array[SLGT_MAX_PORTS];
3622         int i;
3623         int port_count = 1;
3624 
3625         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3626                 port_count = 2;
3627         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3628                 port_count = 4;
3629 
3630         /* allocate device instances for all ports */
3631         for (i=0; i < port_count; ++i) {
3632                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3633                 if (port_array[i] == NULL) {
3634                         for (--i; i >= 0; --i) {
3635                                 tty_port_destroy(&port_array[i]->port);
3636                                 kfree(port_array[i]);
3637                         }
3638                         return;
3639                 }
3640         }
3641 
3642         /* give copy of port_array to all ports and add to device list  */
3643         for (i=0; i < port_count; ++i) {
3644                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3645                 add_device(port_array[i]);
3646                 port_array[i]->port_count = port_count;
3647                 spin_lock_init(&port_array[i]->lock);
3648         }
3649 
3650         /* Allocate and claim adapter resources */
3651         if (!claim_resources(port_array[0])) {
3652 
3653                 alloc_dma_bufs(port_array[0]);
3654 
3655                 /* copy resource information from first port to others */
3656                 for (i = 1; i < port_count; ++i) {
3657                         port_array[i]->irq_level = port_array[0]->irq_level;
3658                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3659                         alloc_dma_bufs(port_array[i]);
3660                 }
3661 
3662                 if (request_irq(port_array[0]->irq_level,
3663                                         slgt_interrupt,
3664                                         port_array[0]->irq_flags,
3665                                         port_array[0]->device_name,
3666                                         port_array[0]) < 0) {
3667                         DBGERR(("%s request_irq failed IRQ=%d\n",
3668                                 port_array[0]->device_name,
3669                                 port_array[0]->irq_level));
3670                 } else {
3671                         port_array[0]->irq_requested = true;
3672                         adapter_test(port_array[0]);
3673                         for (i=1 ; i < port_count ; i++) {
3674                                 port_array[i]->init_error = port_array[0]->init_error;
3675                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3676                         }
3677                 }
3678         }
3679 
3680         for (i = 0; i < port_count; ++i) {
3681                 struct slgt_info *info = port_array[i];
3682                 tty_port_register_device(&info->port, serial_driver, info->line,
3683                                 &info->pdev->dev);
3684         }
3685 }
3686 
3687 static int init_one(struct pci_dev *dev,
3688                               const struct pci_device_id *ent)
3689 {
3690         if (pci_enable_device(dev)) {
3691                 printk("error enabling pci device %p\n", dev);
3692                 return -EIO;
3693         }
3694         pci_set_master(dev);
3695         device_init(slgt_device_count, dev);
3696         return 0;
3697 }
3698 
3699 static void remove_one(struct pci_dev *dev)
3700 {
3701 }
3702 
3703 static const struct tty_operations ops = {
3704         .open = open,
3705         .close = close,
3706         .write = write,
3707         .put_char = put_char,
3708         .flush_chars = flush_chars,
3709         .write_room = write_room,
3710         .chars_in_buffer = chars_in_buffer,
3711         .flush_buffer = flush_buffer,
3712         .ioctl = ioctl,
3713         .compat_ioctl = slgt_compat_ioctl,
3714         .throttle = throttle,
3715         .unthrottle = unthrottle,
3716         .send_xchar = send_xchar,
3717         .break_ctl = set_break,
3718         .wait_until_sent = wait_until_sent,
3719         .set_termios = set_termios,
3720         .stop = tx_hold,
3721         .start = tx_release,
3722         .hangup = hangup,
3723         .tiocmget = tiocmget,
3724         .tiocmset = tiocmset,
3725         .get_icount = get_icount,
3726         .proc_fops = &synclink_gt_proc_fops,
3727 };
3728 
3729 static void slgt_cleanup(void)
3730 {
3731         int rc;
3732         struct slgt_info *info;
3733         struct slgt_info *tmp;
3734 
3735         printk(KERN_INFO "unload %s\n", driver_name);
3736 
3737         if (serial_driver) {
3738                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3739                         tty_unregister_device(serial_driver, info->line);
3740                 rc = tty_unregister_driver(serial_driver);
3741                 if (rc)
3742                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3743                 put_tty_driver(serial_driver);
3744         }
3745 
3746         /* reset devices */
3747         info = slgt_device_list;
3748         while(info) {
3749                 reset_port(info);
3750                 info = info->next_device;
3751         }
3752 
3753         /* release devices */
3754         info = slgt_device_list;
3755         while(info) {
3756 #if SYNCLINK_GENERIC_HDLC
3757                 hdlcdev_exit(info);
3758 #endif
3759                 free_dma_bufs(info);
3760                 free_tmp_rbuf(info);
3761                 if (info->port_num == 0)
3762                         release_resources(info);
3763                 tmp = info;
3764                 info = info->next_device;
3765                 tty_port_destroy(&tmp->port);
3766                 kfree(tmp);
3767         }
3768 
3769         if (pci_registered)
3770                 pci_unregister_driver(&pci_driver);
3771 }
3772 
3773 /*
3774  *  Driver initialization entry point.
3775  */
3776 static int __init slgt_init(void)
3777 {
3778         int rc;
3779 
3780         printk(KERN_INFO "%s\n", driver_name);
3781 
3782         serial_driver = alloc_tty_driver(MAX_DEVICES);
3783         if (!serial_driver) {
3784                 printk("%s can't allocate tty driver\n", driver_name);
3785                 return -ENOMEM;
3786         }
3787 
3788         /* Initialize the tty_driver structure */
3789 
3790         serial_driver->driver_name = slgt_driver_name;
3791         serial_driver->name = tty_dev_prefix;
3792         serial_driver->major = ttymajor;
3793         serial_driver->minor_start = 64;
3794         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3795         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3796         serial_driver->init_termios = tty_std_termios;
3797         serial_driver->init_termios.c_cflag =
3798                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3799         serial_driver->init_termios.c_ispeed = 9600;
3800         serial_driver->init_termios.c_ospeed = 9600;
3801         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3802         tty_set_operations(serial_driver, &ops);
3803         if ((rc = tty_register_driver(serial_driver)) < 0) {
3804                 DBGERR(("%s can't register serial driver\n", driver_name));
3805                 put_tty_driver(serial_driver);
3806                 serial_driver = NULL;
3807                 goto error;
3808         }
3809 
3810         printk(KERN_INFO "%s, tty major#%d\n",
3811                driver_name, serial_driver->major);
3812 
3813         slgt_device_count = 0;
3814         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3815                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3816                 goto error;
3817         }
3818         pci_registered = true;
3819 
3820         if (!slgt_device_list)
3821                 printk("%s no devices found\n",driver_name);
3822 
3823         return 0;
3824 
3825 error:
3826         slgt_cleanup();
3827         return rc;
3828 }
3829 
3830 static void __exit slgt_exit(void)
3831 {
3832         slgt_cleanup();
3833 }
3834 
3835 module_init(slgt_init);
3836 module_exit(slgt_exit);
3837 
3838 /*
3839  * register access routines
3840  */
3841 
3842 #define CALC_REGADDR() \
3843         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3844         if (addr >= 0x80) \
3845                 reg_addr += (info->port_num) * 32; \
3846         else if (addr >= 0x40)  \
3847                 reg_addr += (info->port_num) * 16;
3848 
3849 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3850 {
3851         CALC_REGADDR();
3852         return readb((void __iomem *)reg_addr);
3853 }
3854 
3855 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3856 {
3857         CALC_REGADDR();
3858         writeb(value, (void __iomem *)reg_addr);
3859 }
3860 
3861 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3862 {
3863         CALC_REGADDR();
3864         return readw((void __iomem *)reg_addr);
3865 }
3866 
3867 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3868 {
3869         CALC_REGADDR();
3870         writew(value, (void __iomem *)reg_addr);
3871 }
3872 
3873 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3874 {
3875         CALC_REGADDR();
3876         return readl((void __iomem *)reg_addr);
3877 }
3878 
3879 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3880 {
3881         CALC_REGADDR();
3882         writel(value, (void __iomem *)reg_addr);
3883 }
3884 
3885 static void rdma_reset(struct slgt_info *info)
3886 {
3887         unsigned int i;
3888 
3889         /* set reset bit */
3890         wr_reg32(info, RDCSR, BIT1);
3891 
3892         /* wait for enable bit cleared */
3893         for(i=0 ; i < 1000 ; i++)
3894                 if (!(rd_reg32(info, RDCSR) & BIT0))
3895                         break;
3896 }
3897 
3898 static void tdma_reset(struct slgt_info *info)
3899 {
3900         unsigned int i;
3901 
3902         /* set reset bit */
3903         wr_reg32(info, TDCSR, BIT1);
3904 
3905         /* wait for enable bit cleared */
3906         for(i=0 ; i < 1000 ; i++)
3907                 if (!(rd_reg32(info, TDCSR) & BIT0))
3908                         break;
3909 }
3910 
3911 /*
3912  * enable internal loopback
3913  * TxCLK and RxCLK are generated from BRG
3914  * and TxD is looped back to RxD internally.
3915  */
3916 static void enable_loopback(struct slgt_info *info)
3917 {
3918         /* SCR (serial control) BIT2=loopback enable */
3919         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3920 
3921         if (info->params.mode != MGSL_MODE_ASYNC) {
3922                 /* CCR (clock control)
3923                  * 07..05  tx clock source (010 = BRG)
3924                  * 04..02  rx clock source (010 = BRG)
3925                  * 01      auxclk enable   (0 = disable)
3926                  * 00      BRG enable      (1 = enable)
3927                  *
3928                  * 0100 1001
3929                  */
3930                 wr_reg8(info, CCR, 0x49);
3931 
3932                 /* set speed if available, otherwise use default */
3933                 if (info->params.clock_speed)
3934                         set_rate(info, info->params.clock_speed);
3935                 else
3936                         set_rate(info, 3686400);
3937         }
3938 }
3939 
3940 /*
3941  *  set baud rate generator to specified rate
3942  */
3943 static void set_rate(struct slgt_info *info, u32 rate)
3944 {
3945         unsigned int div;
3946         unsigned int osc = info->base_clock;
3947 
3948         /* div = osc/rate - 1
3949          *
3950          * Round div up if osc/rate is not integer to
3951          * force to next slowest rate.
3952          */
3953 
3954         if (rate) {
3955                 div = osc/rate;
3956                 if (!(osc % rate) && div)
3957                         div--;
3958                 wr_reg16(info, BDR, (unsigned short)div);
3959         }
3960 }
3961 
3962 static void rx_stop(struct slgt_info *info)
3963 {
3964         unsigned short val;
3965 
3966         /* disable and reset receiver */
3967         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3968         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3969         wr_reg16(info, RCR, val);                  /* clear reset bit */
3970 
3971         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3972 
3973         /* clear pending rx interrupts */
3974         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3975 
3976         rdma_reset(info);
3977 
3978         info->rx_enabled = false;
3979         info->rx_restart = false;
3980 }
3981 
3982 static void rx_start(struct slgt_info *info)
3983 {
3984         unsigned short val;
3985 
3986         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3987 
3988         /* clear pending rx overrun IRQ */
3989         wr_reg16(info, SSR, IRQ_RXOVER);
3990 
3991         /* reset and disable receiver */
3992         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3993         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3994         wr_reg16(info, RCR, val);                  /* clear reset bit */
3995 
3996         rdma_reset(info);
3997         reset_rbufs(info);
3998 
3999         if (info->rx_pio) {
4000                 /* rx request when rx FIFO not empty */
4001                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4002                 slgt_irq_on(info, IRQ_RXDATA);
4003                 if (info->params.mode == MGSL_MODE_ASYNC) {
4004                         /* enable saving of rx status */
4005                         wr_reg32(info, RDCSR, BIT6);
4006                 }
4007         } else {
4008                 /* rx request when rx FIFO half full */
4009                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4010                 /* set 1st descriptor address */
4011                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4012 
4013                 if (info->params.mode != MGSL_MODE_ASYNC) {
4014                         /* enable rx DMA and DMA interrupt */
4015                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
4016                 } else {
4017                         /* enable saving of rx status, rx DMA and DMA interrupt */
4018                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4019                 }
4020         }
4021 
4022         slgt_irq_on(info, IRQ_RXOVER);
4023 
4024         /* enable receiver */
4025         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4026 
4027         info->rx_restart = false;
4028         info->rx_enabled = true;
4029 }
4030 
4031 static void tx_start(struct slgt_info *info)
4032 {
4033         if (!info->tx_enabled) {
4034                 wr_reg16(info, TCR,
4035                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4036                 info->tx_enabled = true;
4037         }
4038 
4039         if (desc_count(info->tbufs[info->tbuf_start])) {
4040                 info->drop_rts_on_tx_done = false;
4041 
4042                 if (info->params.mode != MGSL_MODE_ASYNC) {
4043                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4044                                 get_signals(info);
4045                                 if (!(info->signals & SerialSignal_RTS)) {
4046                                         info->signals |= SerialSignal_RTS;
4047                                         set_signals(info);
4048                                         info->drop_rts_on_tx_done = true;
4049                                 }
4050                         }
4051 
4052                         slgt_irq_off(info, IRQ_TXDATA);
4053                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4054                         /* clear tx idle and underrun status bits */
4055                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4056                 } else {
4057                         slgt_irq_off(info, IRQ_TXDATA);
4058                         slgt_irq_on(info, IRQ_TXIDLE);
4059                         /* clear tx idle status bit */
4060                         wr_reg16(info, SSR, IRQ_TXIDLE);
4061                 }
4062                 /* set 1st descriptor address and start DMA */
4063                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4064                 wr_reg32(info, TDCSR, BIT2 + BIT0);
4065                 info->tx_active = true;
4066         }
4067 }
4068 
4069 static void tx_stop(struct slgt_info *info)
4070 {
4071         unsigned short val;
4072 
4073         del_timer(&info->tx_timer);
4074 
4075         tdma_reset(info);
4076 
4077         /* reset and disable transmitter */
4078         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4079         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4080 
4081         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4082 
4083         /* clear tx idle and underrun status bit */
4084         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4085 
4086         reset_tbufs(info);
4087 
4088         info->tx_enabled = false;
4089         info->tx_active = false;
4090 }
4091 
4092 static void reset_port(struct slgt_info *info)
4093 {
4094         if (!info->reg_addr)
4095                 return;
4096 
4097         tx_stop(info);
4098         rx_stop(info);
4099 
4100         info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4101         set_signals(info);
4102 
4103         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4104 }
4105 
4106 static void reset_adapter(struct slgt_info *info)
4107 {
4108         int i;
4109         for (i=0; i < info->port_count; ++i) {
4110                 if (info->port_array[i])
4111                         reset_port(info->port_array[i]);
4112         }
4113 }
4114 
4115 static void async_mode(struct slgt_info *info)
4116 {
4117         unsigned short val;
4118 
4119         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4120         tx_stop(info);
4121         rx_stop(info);
4122 
4123         /* TCR (tx control)
4124          *
4125          * 15..13  mode, 010=async
4126          * 12..10  encoding, 000=NRZ
4127          * 09      parity enable
4128          * 08      1=odd parity, 0=even parity
4129          * 07      1=RTS driver control
4130          * 06      1=break enable
4131          * 05..04  character length
4132          *         00=5 bits
4133          *         01=6 bits
4134          *         10=7 bits
4135          *         11=8 bits
4136          * 03      0=1 stop bit, 1=2 stop bits
4137          * 02      reset
4138          * 01      enable
4139          * 00      auto-CTS enable
4140          */
4141         val = 0x4000;
4142 
4143         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4144                 val |= BIT7;
4145 
4146         if (info->params.parity != ASYNC_PARITY_NONE) {
4147                 val |= BIT9;
4148                 if (info->params.parity == ASYNC_PARITY_ODD)
4149                         val |= BIT8;
4150         }
4151 
4152         switch (info->params.data_bits)
4153         {
4154         case 6: val |= BIT4; break;
4155         case 7: val |= BIT5; break;
4156         case 8: val |= BIT5 + BIT4; break;
4157         }
4158 
4159         if (info->params.stop_bits != 1)
4160                 val |= BIT3;
4161 
4162         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4163                 val |= BIT0;
4164 
4165         wr_reg16(info, TCR, val);
4166 
4167         /* RCR (rx control)
4168          *
4169          * 15..13  mode, 010=async
4170          * 12..10  encoding, 000=NRZ
4171          * 09      parity enable
4172          * 08      1=odd parity, 0=even parity
4173          * 07..06  reserved, must be 0
4174          * 05..04  character length
4175          *         00=5 bits
4176          *         01=6 bits
4177          *         10=7 bits
4178          *         11=8 bits
4179          * 03      reserved, must be zero
4180          * 02      reset
4181          * 01      enable
4182          * 00      auto-DCD enable
4183          */
4184         val = 0x4000;
4185 
4186         if (info->params.parity != ASYNC_PARITY_NONE) {
4187                 val |= BIT9;
4188                 if (info->params.parity == ASYNC_PARITY_ODD)
4189                         val |= BIT8;
4190         }
4191 
4192         switch (info->params.data_bits)
4193         {
4194         case 6: val |= BIT4; break;
4195         case 7: val |= BIT5; break;
4196         case 8: val |= BIT5 + BIT4; break;
4197         }
4198 
4199         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4200                 val |= BIT0;
4201 
4202         wr_reg16(info, RCR, val);
4203 
4204         /* CCR (clock control)
4205          *
4206          * 07..05  011 = tx clock source is BRG/16
4207          * 04..02  010 = rx clock source is BRG
4208          * 01      0 = auxclk disabled
4209          * 00      1 = BRG enabled
4210          *
4211          * 0110 1001
4212          */
4213         wr_reg8(info, CCR, 0x69);
4214 
4215         msc_set_vcr(info);
4216 
4217         /* SCR (serial control)
4218          *
4219          * 15  1=tx req on FIFO half empty
4220          * 14  1=rx req on FIFO half full
4221          * 13  tx data  IRQ enable
4222          * 12  tx idle  IRQ enable
4223          * 11  rx break on IRQ enable
4224          * 10  rx data  IRQ enable
4225          * 09  rx break off IRQ enable
4226          * 08  overrun  IRQ enable
4227          * 07  DSR      IRQ enable
4228          * 06  CTS      IRQ enable
4229          * 05  DCD      IRQ enable
4230          * 04  RI       IRQ enable
4231          * 03  0=16x sampling, 1=8x sampling
4232          * 02  1=txd->rxd internal loopback enable
4233          * 01  reserved, must be zero
4234          * 00  1=master IRQ enable
4235          */
4236         val = BIT15 + BIT14 + BIT0;
4237         /* JCR[8] : 1 = x8 async mode feature available */
4238         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4239             ((info->base_clock < (info->params.data_rate * 16)) ||
4240              (info->base_clock % (info->params.data_rate * 16)))) {
4241                 /* use 8x sampling */
4242                 val |= BIT3;
4243                 set_rate(info, info->params.data_rate * 8);
4244         } else {
4245                 /* use 16x sampling */
4246                 set_rate(info, info->params.data_rate * 16);
4247         }
4248         wr_reg16(info, SCR, val);
4249 
4250         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4251 
4252         if (info->params.loopback)
4253                 enable_loopback(info);
4254 }
4255 
4256 static void sync_mode(struct slgt_info *info)
4257 {
4258         unsigned short val;
4259 
4260         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4261         tx_stop(info);
4262         rx_stop(info);
4263 
4264         /* TCR (tx control)
4265          *
4266          * 15..13  mode
4267          *         000=HDLC/SDLC
4268          *         001=raw bit synchronous
4269          *         010=asynchronous/isochronous
4270          *         011=monosync byte synchronous
4271          *         100=bisync byte synchronous
4272          *         101=xsync byte synchronous
4273          * 12..10  encoding
4274          * 09      CRC enable
4275          * 08      CRC32
4276          * 07      1=RTS driver control
4277          * 06      preamble enable
4278          * 05..04  preamble length
4279          * 03      share open/close flag
4280          * 02      reset
4281          * 01      enable
4282          * 00      auto-CTS enable
4283          */
4284         val = BIT2;
4285 
4286         switch(info->params.mode) {
4287         case MGSL_MODE_XSYNC:
4288                 val |= BIT15 + BIT13;
4289                 break;
4290         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4291         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4292         case MGSL_MODE_RAW:      val |= BIT13; break;
4293         }
4294         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4295                 val |= BIT7;
4296 
4297         switch(info->params.encoding)
4298         {
4299         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4300         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4301         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4302         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4303         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4304         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4305         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4306         }
4307 
4308         switch (info->params.crc_type & HDLC_CRC_MASK)
4309         {
4310         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4311         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4312         }
4313 
4314         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4315                 val |= BIT6;
4316 
4317         switch (info->params.preamble_length)
4318         {
4319         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4320         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4321         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4322         }
4323 
4324         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4325                 val |= BIT0;
4326 
4327         wr_reg16(info, TCR, val);
4328 
4329         /* TPR (transmit preamble) */
4330 
4331         switch (info->params.preamble)
4332         {
4333         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4334         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4335         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4336         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4337         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4338         default:                          val = 0x7e; break;
4339         }
4340         wr_reg8(info, TPR, (unsigned char)val);
4341 
4342         /* RCR (rx control)
4343          *
4344          * 15..13  mode
4345          *         000=HDLC/SDLC
4346          *         001=raw bit synchronous
4347          *         010=asynchronous/isochronous
4348          *         011=monosync byte synchronous
4349          *         100=bisync byte synchronous
4350          *         101=xsync byte synchronous
4351          * 12..10  encoding
4352          * 09      CRC enable
4353          * 08      CRC32
4354          * 07..03  reserved, must be 0
4355          * 02      reset
4356          * 01      enable
4357          * 00      auto-DCD enable
4358          */
4359         val = 0;
4360 
4361         switch(info->params.mode) {
4362         case MGSL_MODE_XSYNC:
4363                 val |= BIT15 + BIT13;
4364                 break;
4365         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4366         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4367         case MGSL_MODE_RAW:      val |= BIT13; break;
4368         }
4369 
4370         switch(info->params.encoding)
4371         {
4372         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4373         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4374         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4375         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4376         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4377         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4378         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4379         }
4380 
4381         switch (info->params.crc_type & HDLC_CRC_MASK)
4382         {
4383         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4384         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4385         }
4386 
4387         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4388                 val |= BIT0;
4389 
4390         wr_reg16(info, RCR, val);
4391 
4392         /* CCR (clock control)
4393          *
4394          * 07..05  tx clock source
4395          * 04..02  rx clock source
4396          * 01      auxclk enable
4397          * 00      BRG enable
4398          */
4399         val = 0;
4400 
4401         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4402         {
4403                 // when RxC source is DPLL, BRG generates 16X DPLL
4404                 // reference clock, so take TxC from BRG/16 to get
4405                 // transmit clock at actual data rate
4406                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4407                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4408                 else
4409                         val |= BIT6;    /* 010, txclk = BRG */
4410         }
4411         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4412                 val |= BIT7;    /* 100, txclk = DPLL Input */
4413         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4414                 val |= BIT5;    /* 001, txclk = RXC Input */
4415 
4416         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4417                 val |= BIT3;    /* 010, rxclk = BRG */
4418         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4419                 val |= BIT4;    /* 100, rxclk = DPLL */
4420         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4421                 val |= BIT2;    /* 001, rxclk = TXC Input */
4422 
4423         if (info->params.clock_speed)
4424                 val |= BIT1 + BIT0;
4425 
4426         wr_reg8(info, CCR, (unsigned char)val);
4427 
4428         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4429         {
4430                 // program DPLL mode
4431                 switch(info->params.encoding)
4432                 {
4433                 case HDLC_ENCODING_BIPHASE_MARK:
4434                 case HDLC_ENCODING_BIPHASE_SPACE:
4435                         val = BIT7; break;
4436                 case HDLC_ENCODING_BIPHASE_LEVEL:
4437                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4438                         val = BIT7 + BIT6; break;
4439                 default: val = BIT6;    // NRZ encodings
4440                 }
4441                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4442 
4443                 // DPLL requires a 16X reference clock from BRG
4444                 set_rate(info, info->params.clock_speed * 16);
4445         }
4446         else
4447                 set_rate(info, info->params.clock_speed);
4448 
4449         tx_set_idle(info);
4450 
4451         msc_set_vcr(info);
4452 
4453         /* SCR (serial control)
4454          *
4455          * 15  1=tx req on FIFO half empty
4456          * 14  1=rx req on FIFO half full
4457          * 13  tx data  IRQ enable
4458          * 12  tx idle  IRQ enable
4459          * 11  underrun IRQ enable
4460          * 10  rx data  IRQ enable
4461          * 09  rx idle  IRQ enable
4462          * 08  overrun  IRQ enable
4463          * 07  DSR      IRQ enable
4464          * 06  CTS      IRQ enable
4465          * 05  DCD      IRQ enable
4466          * 04  RI       IRQ enable
4467          * 03  reserved, must be zero
4468          * 02  1=txd->rxd internal loopback enable
4469          * 01  reserved, must be zero
4470          * 00  1=master IRQ enable
4471          */
4472         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4473 
4474         if (info->params.loopback)
4475                 enable_loopback(info);
4476 }
4477 
4478 /*
4479  *  set transmit idle mode
4480  */
4481 static void tx_set_idle(struct slgt_info *info)
4482 {
4483         unsigned char val;
4484         unsigned short tcr;
4485 
4486         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4487          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4488          */
4489         tcr = rd_reg16(info, TCR);
4490         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4491                 /* disable preamble, set idle size to 16 bits */
4492                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4493                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4494                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4495         } else if (!(tcr & BIT6)) {
4496                 /* preamble is disabled, set idle size to 8 bits */
4497                 tcr &= ~(BIT5 + BIT4);
4498         }
4499         wr_reg16(info, TCR, tcr);
4500 
4501         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4502                 /* LSB of custom tx idle specified in tx idle register */
4503                 val = (unsigned char)(info->idle_mode & 0xff);
4504         } else {
4505                 /* standard 8 bit idle patterns */
4506                 switch(info->idle_mode)
4507                 {
4508                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4509                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4510                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4511                 case HDLC_TXIDLE_ZEROS:
4512                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4513                 default:                         val = 0xff;
4514                 }
4515         }
4516 
4517         wr_reg8(info, TIR, val);
4518 }
4519 
4520 /*
4521  * get state of V24 status (input) signals
4522  */
4523 static void get_signals(struct slgt_info *info)
4524 {
4525         unsigned short status = rd_reg16(info, SSR);
4526 
4527         /* clear all serial signals except RTS and DTR */
4528         info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4529 
4530         if (status & BIT3)
4531                 info->signals |= SerialSignal_DSR;
4532         if (status & BIT2)
4533                 info->signals |= SerialSignal_CTS;
4534         if (status & BIT1)
4535                 info->signals |= SerialSignal_DCD;
4536         if (status & BIT0)
4537                 info->signals |= SerialSignal_RI;
4538 }
4539 
4540 /*
4541  * set V.24 Control Register based on current configuration
4542  */
4543 static void msc_set_vcr(struct slgt_info *info)
4544 {
4545         unsigned char val = 0;
4546 
4547         /* VCR (V.24 control)
4548          *
4549          * 07..04  serial IF select
4550          * 03      DTR
4551          * 02      RTS
4552          * 01      LL
4553          * 00      RL
4554          */
4555 
4556         switch(info->if_mode & MGSL_INTERFACE_MASK)
4557         {
4558         case MGSL_INTERFACE_RS232:
4559                 val |= BIT5; /* 0010 */
4560                 break;
4561         case MGSL_INTERFACE_V35:
4562                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4563                 break;
4564         case MGSL_INTERFACE_RS422:
4565                 val |= BIT6; /* 0100 */
4566                 break;
4567         }
4568 
4569         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4570                 val |= BIT4;
4571         if (info->signals & SerialSignal_DTR)
4572                 val |= BIT3;
4573         if (info->signals & SerialSignal_RTS)
4574                 val |= BIT2;
4575         if (info->if_mode & MGSL_INTERFACE_LL)
4576                 val |= BIT1;
4577         if (info->if_mode & MGSL_INTERFACE_RL)
4578                 val |= BIT0;
4579         wr_reg8(info, VCR, val);
4580 }
4581 
4582 /*
4583  * set state of V24 control (output) signals
4584  */
4585 static void set_signals(struct slgt_info *info)
4586 {
4587         unsigned char val = rd_reg8(info, VCR);
4588         if (info->signals & SerialSignal_DTR)
4589                 val |= BIT3;
4590         else
4591                 val &= ~BIT3;
4592         if (info->signals & SerialSignal_RTS)
4593                 val |= BIT2;
4594         else
4595                 val &= ~BIT2;
4596         wr_reg8(info, VCR, val);
4597 }
4598 
4599 /*
4600  * free range of receive DMA buffers (i to last)
4601  */
4602 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4603 {
4604         int done = 0;
4605 
4606         while(!done) {
4607                 /* reset current buffer for reuse */
4608                 info->rbufs[i].status = 0;
4609                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4610                 if (i == last)
4611                         done = 1;
4612                 if (++i == info->rbuf_count)
4613                         i = 0;
4614         }
4615         info->rbuf_current = i;
4616 }
4617 
4618 /*
4619  * mark all receive DMA buffers as free
4620  */
4621 static void reset_rbufs(struct slgt_info *info)
4622 {
4623         free_rbufs(info, 0, info->rbuf_count - 1);
4624         info->rbuf_fill_index = 0;
4625         info->rbuf_fill_count = 0;
4626 }
4627 
4628 /*
4629  * pass receive HDLC frame to upper layer
4630  *
4631  * return true if frame available, otherwise false
4632  */
4633 static bool rx_get_frame(struct slgt_info *info)
4634 {
4635         unsigned int start, end;
4636         unsigned short status;
4637         unsigned int framesize = 0;
4638         unsigned long flags;
4639         struct tty_struct *tty = info->port.tty;
4640         unsigned char addr_field = 0xff;
4641         unsigned int crc_size = 0;
4642 
4643         switch (info->params.crc_type & HDLC_CRC_MASK) {
4644         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4645         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4646         }
4647 
4648 check_again:
4649 
4650         framesize = 0;
4651         addr_field = 0xff;
4652         start = end = info->rbuf_current;
4653 
4654         for (;;) {
4655                 if (!desc_complete(info->rbufs[end]))
4656                         goto cleanup;
4657 
4658                 if (framesize == 0 && info->params.addr_filter != 0xff)
4659                         addr_field = info->rbufs[end].buf[0];
4660 
4661                 framesize += desc_count(info->rbufs[end]);
4662 
4663                 if (desc_eof(info->rbufs[end]))
4664                         break;
4665 
4666                 if (++end == info->rbuf_count)
4667                         end = 0;
4668 
4669                 if (end == info->rbuf_current) {
4670                         if (info->rx_enabled){
4671                                 spin_lock_irqsave(&info->lock,flags);
4672                                 rx_start(info);
4673                                 spin_unlock_irqrestore(&info->lock,flags);
4674                         }
4675                         goto cleanup;
4676                 }
4677         }
4678 
4679         /* status
4680          *
4681          * 15      buffer complete
4682          * 14..06  reserved
4683          * 05..04  residue
4684          * 02      eof (end of frame)
4685          * 01      CRC error
4686          * 00      abort
4687          */
4688         status = desc_status(info->rbufs[end]);
4689 
4690         /* ignore CRC bit if not using CRC (bit is undefined) */
4691         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4692                 status &= ~BIT1;
4693 
4694         if (framesize == 0 ||
4695                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4696                 free_rbufs(info, start, end);
4697                 goto check_again;
4698         }
4699 
4700         if (framesize < (2 + crc_size) || status & BIT0) {
4701                 info->icount.rxshort++;
4702                 framesize = 0;
4703         } else if (status & BIT1) {
4704                 info->icount.rxcrc++;
4705                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4706                         framesize = 0;
4707         }
4708 
4709 #if SYNCLINK_GENERIC_HDLC
4710         if (framesize == 0) {
4711                 info->netdev->stats.rx_errors++;
4712                 info->netdev->stats.rx_frame_errors++;
4713         }
4714 #endif
4715 
4716         DBGBH(("%s rx frame status=%04X size=%d\n",
4717                 info->device_name, status, framesize));
4718         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4719 
4720         if (framesize) {
4721                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4722                         framesize -= crc_size;
4723                         crc_size = 0;
4724                 }
4725 
4726                 if (framesize > info->max_frame_size + crc_size)
4727                         info->icount.rxlong++;
4728                 else {
4729                         /* copy dma buffer(s) to contiguous temp buffer */
4730                         int copy_count = framesize;
4731                         int i = start;
4732                         unsigned char *p = info->tmp_rbuf;
4733                         info->tmp_rbuf_count = framesize;
4734 
4735                         info->icount.rxok++;
4736 
4737                         while(copy_count) {
4738                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4739                                 memcpy(p, info->rbufs[i].buf, partial_count);
4740                                 p += partial_count;
4741                                 copy_count -= partial_count;
4742                                 if (++i == info->rbuf_count)
4743                                         i = 0;
4744                         }
4745 
4746                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4747                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4748                                 framesize++;
4749                         }
4750 
4751 #if SYNCLINK_GENERIC_HDLC
4752                         if (info->netcount)
4753                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4754                         else
4755 #endif
4756                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4757                 }
4758         }
4759         free_rbufs(info, start, end);
4760         return true;
4761 
4762 cleanup:
4763         return false;
4764 }
4765 
4766 /*
4767  * pass receive buffer (RAW synchronous mode) to tty layer
4768  * return true if buffer available, otherwise false
4769  */
4770 static bool rx_get_buf(struct slgt_info *info)
4771 {
4772         unsigned int i = info->rbuf_current;
4773         unsigned int count;
4774 
4775         if (!desc_complete(info->rbufs[i]))
4776                 return false;
4777         count = desc_count(info->rbufs[i]);
4778         switch(info->params.mode) {
4779         case MGSL_MODE_MONOSYNC:
4780         case MGSL_MODE_BISYNC:
4781         case MGSL_MODE_XSYNC:
4782                 /* ignore residue in byte synchronous modes */
4783                 if (desc_residue(info->rbufs[i]))
4784                         count--;
4785                 break;
4786         }
4787         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4788         DBGINFO(("rx_get_buf size=%d\n", count));
4789         if (count)
4790                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4791                                   info->flag_buf, count);
4792         free_rbufs(info, i, i);
4793         return true;
4794 }
4795 
4796 static void reset_tbufs(struct slgt_info *info)
4797 {
4798         unsigned int i;
4799         info->tbuf_current = 0;
4800         for (i=0 ; i < info->tbuf_count ; i++) {
4801                 info->tbufs[i].status = 0;
4802                 info->tbufs[i].count  = 0;
4803         }
4804 }
4805 
4806 /*
4807  * return number of free transmit DMA buffers
4808  */
4809 static unsigned int free_tbuf_count(struct slgt_info *info)
4810 {
4811         unsigned int count = 0;
4812         unsigned int i = info->tbuf_current;
4813 
4814         do
4815         {
4816                 if (desc_count(info->tbufs[i]))
4817                         break; /* buffer in use */
4818                 ++count;
4819                 if (++i == info->tbuf_count)
4820                         i=0;
4821         } while (i != info->tbuf_current);
4822 
4823         /* if tx DMA active, last zero count buffer is in use */
4824         if (count && (rd_reg32(info, TDCSR) & BIT0))
4825                 --count;
4826 
4827         return count;
4828 }
4829 
4830 /*
4831  * return number of bytes in unsent transmit DMA buffers
4832  * and the serial controller tx FIFO
4833  */
4834 static unsigned int tbuf_bytes(struct slgt_info *info)
4835 {
4836         unsigned int total_count = 0;
4837         unsigned int i = info->tbuf_current;
4838         unsigned int reg_value;
4839         unsigned int count;
4840         unsigned int active_buf_count = 0;
4841 
4842         /*
4843          * Add descriptor counts for all tx DMA buffers.
4844          * If count is zero (cleared by DMA controller after read),
4845          * the buffer is complete or is actively being read from.
4846          *
4847          * Record buf_count of last buffer with zero count starting
4848          * from current ring position. buf_count is mirror
4849          * copy of count and is not cleared by serial controller.
4850          * If DMA controller is active, that buffer is actively
4851          * being read so add to total.
4852          */
4853         do {
4854                 count = desc_count(info->tbufs[i]);
4855                 if (count)
4856                         total_count += count;
4857                 else if (!total_count)
4858                         active_buf_count = info->tbufs[i].buf_count;
4859                 if (++i == info->tbuf_count)
4860                         i = 0;
4861         } while (i != info->tbuf_current);
4862 
4863         /* read tx DMA status register */
4864         reg_value = rd_reg32(info, TDCSR);
4865 
4866         /* if tx DMA active, last zero count buffer is in use */
4867         if (reg_value & BIT0)
4868                 total_count += active_buf_count;
4869 
4870         /* add tx FIFO count = reg_value[15..8] */
4871         total_count += (reg_value >> 8) & 0xff;
4872 
4873         /* if transmitter active add one byte for shift register */
4874         if (info->tx_active)
4875                 total_count++;
4876 
4877         return total_count;
4878 }
4879 
4880 /*
4881  * load data into transmit DMA buffer ring and start transmitter if needed
4882  * return true if data accepted, otherwise false (buffers full)
4883  */
4884 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4885 {
4886         unsigned short count;
4887         unsigned int i;
4888         struct slgt_desc *d;
4889 
4890         /* check required buffer space */
4891         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4892                 return false;
4893 
4894         DBGDATA(info, buf, size, "tx");
4895 
4896         /*
4897          * copy data to one or more DMA buffers in circular ring
4898          * tbuf_start   = first buffer for this data
4899          * tbuf_current = next free buffer
4900          *
4901          * Copy all data before making data visible to DMA controller by
4902          * setting descriptor count of the first buffer.
4903          * This prevents an active DMA controller from reading the first DMA
4904          * buffers of a frame and stopping before the final buffers are filled.
4905          */
4906 
4907         info->tbuf_start = i = info->tbuf_current;
4908 
4909         while (size) {
4910                 d = &info->tbufs[i];
4911 
4912                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4913                 memcpy(d->buf, buf, count);
4914 
4915                 size -= count;
4916                 buf  += count;
4917 
4918                 /*
4919                  * set EOF bit for last buffer of HDLC frame or
4920                  * for every buffer in raw mode
4921                  */
4922                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4923                     info->params.mode == MGSL_MODE_RAW)
4924                         set_desc_eof(*d, 1);
4925                 else
4926                         set_desc_eof(*d, 0);
4927 
4928                 /* set descriptor count for all but first buffer */
4929                 if (i != info->tbuf_start)
4930                         set_desc_count(*d, count);
4931                 d->buf_count = count;
4932 
4933                 if (++i == info->tbuf_count)
4934                         i = 0;
4935         }
4936 
4937         info->tbuf_current = i;
4938 
4939         /* set first buffer count to make new data visible to DMA controller */
4940         d = &info->tbufs[info->tbuf_start];
4941         set_desc_count(*d, d->buf_count);
4942 
4943         /* start transmitter if needed and update transmit timeout */
4944         if (!info->tx_active)
4945                 tx_start(info);
4946         update_tx_timer(info);
4947 
4948         return true;
4949 }
4950 
4951 static int register_test(struct slgt_info *info)
4952 {
4953         static unsigned short patterns[] =
4954                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4955         static unsigned int count = ARRAY_SIZE(patterns);
4956         unsigned int i;
4957         int rc = 0;
4958 
4959         for (i=0 ; i < count ; i++) {
4960                 wr_reg16(info, TIR, patterns[i]);
4961                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4962                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4963                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4964                         rc = -ENODEV;
4965                         break;
4966                 }
4967         }
4968         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4969         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4970         return rc;
4971 }
4972 
4973 static int irq_test(struct slgt_info *info)
4974 {
4975         unsigned long timeout;
4976         unsigned long flags;
4977         struct tty_struct *oldtty = info->port.tty;
4978         u32 speed = info->params.data_rate;
4979 
4980         info->params.data_rate = 921600;
4981         info->port.tty = NULL;
4982 
4983         spin_lock_irqsave(&info->lock, flags);
4984         async_mode(info);
4985         slgt_irq_on(info, IRQ_TXIDLE);
4986 
4987         /* enable transmitter */
4988         wr_reg16(info, TCR,
4989                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4990 
4991         /* write one byte and wait for tx idle */
4992         wr_reg16(info, TDR, 0);
4993 
4994         /* assume failure */
4995         info->init_error = DiagStatus_IrqFailure;
4996         info->irq_occurred = false;
4997 
4998         spin_unlock_irqrestore(&info->lock, flags);
4999 
5000         timeout=100;
5001         while(timeout-- && !info->irq_occurred)
5002                 msleep_interruptible(10);
5003 
5004         spin_lock_irqsave(&info->lock,flags);
5005         reset_port(info);
5006         spin_unlock_irqrestore(&info->lock,flags);
5007 
5008         info->params.data_rate = speed;
5009         info->port.tty = oldtty;
5010 
5011         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5012         return info->irq_occurred ? 0 : -ENODEV;
5013 }
5014 
5015 static int loopback_test_rx(struct slgt_info *info)
5016 {
5017         unsigned char *src, *dest;
5018         int count;
5019 
5020         if (desc_complete(info->rbufs[0])) {
5021                 count = desc_count(info->rbufs[0]);
5022                 src   = info->rbufs[0].buf;
5023                 dest  = info->tmp_rbuf;
5024 
5025                 for( ; count ; count-=2, src+=2) {
5026                         /* src=data byte (src+1)=status byte */
5027                         if (!(*(src+1) & (BIT9 + BIT8))) {
5028                                 *dest = *src;
5029                                 dest++;
5030                                 info->tmp_rbuf_count++;
5031                         }
5032                 }
5033                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5034                 return 1;
5035         }
5036         return 0;
5037 }
5038 
5039 static int loopback_test(struct slgt_info *info)
5040 {
5041 #define TESTFRAMESIZE 20
5042 
5043         unsigned long timeout;
5044         u16 count = TESTFRAMESIZE;
5045         unsigned char buf[TESTFRAMESIZE];
5046         int rc = -ENODEV;
5047         unsigned long flags;
5048 
5049         struct tty_struct *oldtty = info->port.tty;
5050         MGSL_PARAMS params;
5051 
5052         memcpy(&params, &info->params, sizeof(params));
5053 
5054         info->params.mode = MGSL_MODE_ASYNC;
5055         info->params.data_rate = 921600;
5056         info->params.loopback = 1;
5057         info->port.tty = NULL;
5058 
5059         /* build and send transmit frame */
5060         for (count = 0; count < TESTFRAMESIZE; ++count)
5061                 buf[count] = (unsigned char)count;
5062 
5063         info->tmp_rbuf_count = 0;
5064         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5065 
5066         /* program hardware for HDLC and enabled receiver */
5067         spin_lock_irqsave(&info->lock,flags);
5068         async_mode(info);
5069         rx_start(info);
5070         tx_load(info, buf, count);
5071         spin_unlock_irqrestore(&info->lock, flags);
5072 
5073         /* wait for receive complete */
5074         for (timeout = 100; timeout; --timeout) {
5075                 msleep_interruptible(10);
5076                 if (loopback_test_rx(info)) {
5077                         rc = 0;
5078                         break;
5079                 }
5080         }
5081 
5082         /* verify received frame length and contents */
5083         if (!rc && (info->tmp_rbuf_count != count ||
5084                   memcmp(buf, info->tmp_rbuf, count))) {
5085                 rc = -ENODEV;
5086         }
5087 
5088         spin_lock_irqsave(&info->lock,flags);
5089         reset_adapter(info);
5090         spin_unlock_irqrestore(&info->lock,flags);
5091 
5092         memcpy(&info->params, &params, sizeof(info->params));
5093         info->port.tty = oldtty;
5094 
5095         info->init_error = rc ? DiagStatus_DmaFailure : 0;
5096         return rc;
5097 }
5098 
5099 static int adapter_test(struct slgt_info *info)
5100 {
5101         DBGINFO(("testing %s\n", info->device_name));
5102         if (register_test(info) < 0) {
5103                 printk("register test failure %s addr=%08X\n",
5104                         info->device_name, info->phys_reg_addr);
5105         } else if (irq_test(info) < 0) {
5106                 printk("IRQ test failure %s IRQ=%d\n",
5107                         info->device_name, info->irq_level);
5108         } else if (loopback_test(info) < 0) {
5109                 printk("loopback test failure %s\n", info->device_name);
5110         }
5111         return info->init_error;
5112 }
5113 
5114 /*
5115  * transmit timeout handler
5116  */
5117 static void tx_timeout(unsigned long context)
5118 {
5119         struct slgt_info *info = (struct slgt_info*)context;
5120         unsigned long flags;
5121 
5122         DBGINFO(("%s tx_timeout\n", info->device_name));
5123         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5124                 info->icount.txtimeout++;
5125         }
5126         spin_lock_irqsave(&info->lock,flags);
5127         tx_stop(info);
5128         spin_unlock_irqrestore(&info->lock,flags);
5129 
5130 #if SYNCLINK_GENERIC_HDLC
5131         if (info->netcount)
5132                 hdlcdev_tx_done(info);
5133         else
5134 #endif
5135                 bh_transmit(info);
5136 }
5137 
5138 /*
5139  * receive buffer polling timer
5140  */
5141 static void rx_timeout(unsigned long context)
5142 {
5143         struct slgt_info *info = (struct slgt_info*)context;
5144         unsigned long flags;
5145 
5146         DBGINFO(("%s rx_timeout\n", info->device_name));
5147         spin_lock_irqsave(&info->lock, flags);
5148         info->pending_bh |= BH_RECEIVE;
5149         spin_unlock_irqrestore(&info->lock, flags);
5150         bh_handler(&info->task);
5151 }
5152 
5153 

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